IntelR 80960 RN I/O Processor Datasheet

Intel ® 80960RN I/O Processor 

Data Sheet 

Product Features 

■ Complies with PCI Local Bus Specification, Revision 2.2 

■ Universal (5 V and 3.3 V) PCI Signalling Environment (C-stepping only) 

■ 

■ 

■ 

■ 

High Performance Intel ® 80960JT Core 

—Sustained One Instruction/Clock Execution 

—16 Kbyte, Two-Way Set-Associative 

Instruction Cache 

—4 Kbyte, Direct-Mapped Data Cache 

—Sixteen 32-Bit Global Registers 

—Sixteen 32-Bit Local Registers 

—1 Kbyte, Internal Data RAM 

—Local Register Cache 

(Eight Available Stack Frames) 

—Two 32-Bit On-Chip Timer Units 

PCI-to-PCI Bridge Unit 

—Eight Delayed Read/Write Buffers 

HoldinguptoeightTransactions 

—Primary and Secondary 64-bit PCI 

Interfaces 

—TwoPostingBuffersHoldingupto12 

Transactions 

—Delayed and Posted Transaction Support 

—Forwards Memory, I/O, Configuration 

Commands from PCI Bus to PCI Bus 

I 2 O Messaging Unit 

—Four Message Registers 

— Two Doorbell Registers 

—Four Circular Queues 

—1004 Index Registers 

Memory Controller 

—128 Mbytes of 64-Bit SDRAM or 

64 Mbytes of 32-Bit SDRAM 

—ECC Single-Bit error correction, 

Double-Bit error detection 

—Two Independent Banks for SRAM / 

ROM/Flash(8Mbyte/Bank;8-Bit) 

■ 

■ 

■ 

■ 

■ 

■ 

■ 

■ 

Two Address Translation Units 

— Connects Internal Bus to 64-bit PCI Buses 

—Inbound/Outbound Address Translation 

Support 

—Direct Outbound Addressing Support 

DMA Controller 

—Three Independent Channels 

—PCI Memory Controller Interface 

—64-Bit Internal + PCI Bus Addressing 

—Independent Interface to 64-bit Primary 

and Secondary PCI Buses 

—264 Mbyte/sec Burst Transfers to PCI and 

SDRAM Memory 

—Direct Addressing to/from PCI Buses 

—Unaligned Transfers Supported in 

Hardware 

— Two Channels Dedicated to Primary PCI Bus 

—One Channel Dedicated to Secondary PCI Bus 

I 2 C Bus Interface Unit 

—Serial Bus 

—Master/Slave Capabilities 

—System Management Functions 

Secondary PCI Arbitration Unit 

—Supports Six Secondary PCI Devices 

—Multi-priority Arbitration Algorithm 

Private PCI Device Support 

Perimeter Land Grid Array Package 

—540-pin 

Application Accelerator 

—Built-in hardware XOR engine 

Performance Monitoring 

—Ninety-eight events monitored on-chip 

Order Number: 273157-010 

June, 2002


Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual 

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability 

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to 

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not 

intended for use in medical, life saving, or life sustaining applications. 

Intel may make changes to specifications and product descriptions at any time, without notice. 

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for 

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. 

The Intel ® 80960RN I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published 

specifications. Current characterized errata are available on request. 

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 

1-800-548-4725 or by visiting Intel's website at http://www.intel.com. 

Copyright © Intel Corporation, 2002 

Intel, Intel Solutions960 and Intel i960 are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. 

*Other names and brands may be claimed as the property of others. 

Data Sheet


Contents 

1.0 About this Document................................................................................................7 

1.1 Intel ® Solutions960 ® Program ...............................................................................7 

1.2 Terminology...........................................................................................................7 

1.3 Additional Information Sources .............................................................................7 

2.0 Functional Overview .................................................................................................8 

2.1 Key Functional Units .............................................................................................9 

2.1.1 PCI-to-PCI Bridge Unit .............................................................................9 

2.1.2 Private PCI Device Support......................................................................9 

2.1.3 DMA Controller.........................................................................................9 

2.1.4 Address Translation Unit ..........................................................................9 

2.1.5 Messaging Unit.........................................................................................9 

2.1.6 Memory Controller Unit ..........................................................................10 

2.1.7 I2C Bus Interface Unit ............................................................................10 

2.1.8 Secondary PCI Arbitration Unit ..............................................................10 

2.1.9 Application Accelerator Unit ...................................................................10 

2.1.10 Performance Monitor Unit ......................................................................10 

2.1.11 Bus Interface Unit...................................................................................10 

2.2 Intel ® i960 ® Core Features (Intel ® 80960JT).......................................................11 

2.2.1 Burst Bus................................................................................................12 

2.2.2 Timer Unit...............................................................................................12 

2.2.3 Priority Interrupt Controller .....................................................................12 

2.2.4 Faults and Debugging ............................................................................12 

2.2.5 On-Chip Cache and Data RAM ..............................................................12 

2.2.6 Local Register Cache .............................................................................13 

2.2.7 Test Features .........................................................................................13 

2.2.8 Memory-Mapped Control Registers .......................................................13 

2.2.9 Instructions, Data Types and Memory Addressing Modes.....................13 

3.0 Package Information...............................................................................................15 

3.1 Package Introduction...........................................................................................15 

3.1.1 Functional Signal Definitions ..................................................................15 

3.1.1.1 Signal Pin Descriptions .............................................................16 

3.1.2 540-Lead H-PBGA Package ..................................................................26 

3.2 Package Thermal Specifications .........................................................................38 

3.2.1 Thermal Specifications ...........................................................................38 

3.2.1.1 Ambient Temperature................................................................38 

3.2.1.2 Case Temperature ....................................................................38 

3.2.1.3 Thermal Resistance ..................................................................39 

3.2.2 Thermal Analysis....................................................................................39 

3.3 Heat Sink Information..........................................................................................40 

3.4 Vendor Information..............................................................................................40 

3.4.1 Socket-Header Vendor...........................................................................40 

3.4.2 Burn-in Socket Vendor ...........................................................................40 

3.4.3 Shipping Tray Vendor.............................................................................41 

3.4.4 Logic Analyzer Interposer Vendor ..........................................................41 

3.4.5 JTAG Emulator Vendor ..........................................................................41 

3.5 ............................................................................................................................41 

Data Sheet 3


4.0 Electrical Specifications........................................................................................42 

4.1 Absolute Maximum Ratings ................................................................................42 

4.2 V CC5REF Pin Requirements (V DIFF ).....................................................................43 

4.3 V CCPLL Pin Requirements ...................................................................................43 

4.4 Targeted DC Specifications ................................................................................44 

4.5 Targeted AC Specifications.................................................................................46 

4.5.1 Clock Signal Timings..............................................................................46 

4.5.2 PCI Interface Signal Timings..................................................................47 

4.5.3 Intel ® 80960JN Core Interface Timings.................................................. 48 

4.5.4 SDRAM/Flash Interface Signal Timings .................................................48 

4.5.5 Boundary Scan Test Signal Timings ...................................................... 49 

4.5.6 I2C Interface Signal Timings .................................................................. 50 

4.6 AC Timing Waveforms ........................................................................................51 

4.7 AC Test Conditions ............................................................................................. 53 

5.0 Device Identification on Reset............................................................................54 

4 Data Sheet


Figures 

Tables 

1 Intel ® 80960RN Functional Block Diagram ..................................................... 8 

2 Intel ® 80960JT Core Block Diagram ............................................................. 11 

3 540L H-PBGA Package Diagram (Top and Side View) ................................ 26 

4 540L H-PBGA Package Diagram (Bottom View) .......................................... 27 

5 Thermocouple Attachment - A) No Heatsink / B) With Heatsink ................... 38 

6 V CC5REF Current-Limiting Resistor................................................................ 43 

7 V CCPLL Lowpass Filter .................................................................................. 43 

8 P_CLK, TCK, DCLKIN, DCLKOUT Waveform............................................. 51 

9 T OV Output Delay Waveform......................................................................... 51 

10 T OF Output Float Waveform .......................................................................... 52 

11 T IS and T IH Input Setup and Hold Waveform ................................................ 52 

12 I 2 C Interface Signal Timings.......................................................................... 52 

13 AC Test Load (all signals except SDRAM and Flash signals)....................... 53 

1 Related Documentation................................................................................... 7 

2 Instruction Set .............................................................................................. 14 

3 Pin Description Nomenclature....................................................................... 16 

4 Memory Controller Signals ............................................................................ 17 

5 Primary PCI Bus Signals ............................................................................... 20 

6 Secondary PCI Arbiter Signals...................................................................... 21 

7 Secondary PCI Bus Signals .......................................................................... 22 

8 Intel ® 80960Jx Core Signals and Configuration Straps................................. 24 

9 I 2 C, JTAG, Core Signals ............................................................................... 25 

10 540-Lead H-PBGA Package — Signal Name Order ..................................... 28 

11 540-Lead H-PBGA Pinout — Ballpad Number Order.................................... 33 

12 540-Lead H-PBGA Package Thermal Characteristics .................................. 39 

13 Heat Sink Vendors and Contacts .................................................................. 40 

14 Socket-Header Vendor.................................................................................. 40 

15 Burn-in Socket Vendor .................................................................................. 40 

16 Shipping Tray Vendor.................................................................................... 41 

17 Logic Analyzer Interposer Vendor ................................................................. 41 

18 JTAG Emulator Vendor ................................................................................. 41 

19 Operating Conditions..................................................................................... 42 

20 V DIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)......... 43 

21 DC Characteristics ........................................................................................ 44 

22 I CC Characteristics ........................................................................................ 45 

23 Input Clock Timings....................................................................................... 46 

24 SDRAM Output Clock Timings ...................................................................... 46 

25 PCI Signal Timings....................................................................................... 47 

26 Intel ® 80960JN Core Signal Timings............................................................. 48 

27 SDRAM / Flash Signal Timings..................................................................... 48 

28 Boundary Scan Test Signal Timings ............................................................. 49 

29 I2C Interface Signal Timings ......................................................................... 50 

30 Device ID Registers...................................................................................... 54 

Data Sheet 5


This Page Intentionally Left Blank 

6 Data Sheet


1.0 About this Document 

This is the data sheet for the Intel ® 80960RN processor. This data sheet contains a functional 

overview, mechanical data (package signal locations and simulated thermal characteristics), 

targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional 

descriptions other than parametric performance is published in the i960 ® RM/RN I/O Processor 

Developer’s Manual. 

1.1 Intel ® Solutions960 ® Program 

The Intel ® Solutions960 ® program features a wide variety of development tools which support the 

i960 ® processor family. Many of these tools are developed by partner companies; some are 

developed by Intel, such as profile-driven optimizing compilers. For more information on these 

products, contact your local Intel representative. 

1.2 Terminology 

In this document, the following terms are used: 

• Primary and Secondary PCI buses are the 80960RN processor’s external PCI buses which 

conform to PCI SIG specifications. 

• Intel ® 80960 core refers to the Intel ® 80960JT processor which is integrated into the 80960RN 

processor. 

1.3 Additional Information Sources 

Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. 

Intel Corporation 

Literature Sales 

P.O. Box 5937 

Denver, CO 80217-9808 

1-800-548-4725 

Table 1. 

Related Documentation 

Document Title 

Order / Contact 

i960 ® RM/RN I/O Processor Developer’s Manual Intel Order # 273158 

i960 ® Jx Microprocessor User’s Guide Intel Order # 272483 

i960 ® RM/RN/RS I/O Processor Specification Update Intel Order # 273164 

PCI Local Bus Specification, Revision 2.2 PCI Special Interest Group 1-800-433-5177 

PCI-to-PCI Bridge Architecture Specification, Revision 1.1 PCI Special Interest Group 1-800-433-5177 

I 2 C Peripherals for Microcontrollers 

Philips Semiconductor 

Data Sheet 7


2.0 Functional Overview 

As indicated in Figure 1, the 80960RN processor combines many features with the 80960JT to create 

an intelligent I/O processor. Subsections following the figure briefly describe the main features; for 

detailed functional descriptions, refer to the i960 ® RM/RN I/O Processor Developer’s Manual. 

The PCI bus is an industry standard, high performance, low latency system bus that operates up to 

264 Mbyte/s. The 80960RN processor, a multi-function PCI device, is fully compliant with the 

PCI Local Bus Specification, Revision 2.2. Function 0 is the PCI-to-PCI bridge unit; Function 1 is 

the address translation unit. 

The PCI-to-PCI bridge unit is the path between two independent 64-bit PCI buses and provides the 

ability to overcome PCI electrical load limits. The addition of the Intel ® i960 ® core processor 

brings intelligence to the bridge. 

The 80960RN processor, object code compatible with the i960 core processor, is capable of 

sustained execution at the rate of one instruction per clock. 

The internal bus, a 64-bit PCI-like bus, is a high-speed interface to local memory and I/O. Physical 

and logical memory attributes are programmed via memory-mapped control registers (MMRs); an 

extension not found on the Intel ® i960Kx,SxorCxprocessors. 

Figure 1. 

Intel ® 80960RN Functional Block Diagram 

Local Memory 

(SDRAM, Flash) 

I 2 C Serial Bus 

80960RN Processor 

80960 Core 

Memory 

Controller 

Bus 

Interface 

I 2 CBus 

Interface 

Application 

Accelerator 

Internal 

Arbitration 

64-bit Internal Bus 

Messaging 

Unit 

Two DMA 

Channels 

Address 

Translation 

One DMA 

Channel 

Address 

Translation 

64-bit/32-bit Primary PCI Bus 

PCI to PCI 

Bridge 

64-bit/32-bit Secondary PCI Bus 

Performance 

Monitoring 

Unit 

Secondary 

PCI Arbitration 

Unit 

8 Data Sheet


2.1 Key Functional Units 

2.1.1 PCI-to-PCI Bridge Unit 

The PCI-to-PCI bridge unit (referred to as “bridge”) connects two independent PCI buses. Each 

PCI bus may be 32 or 64 bits wide. The bridge is fully compliant with the PCI-to-PCI Bridge 

Architecture Specification, Revision 1.1 published by the PCI Special Interest Group. The bridge 

forwards bus transactions on one PCI bus to the other PCI bus. Dedicated data queues support high 

performance bandwidth on the PCI buses. The 80960RN supports PCI 64-bit Dual Address Cycle 

(DAC) addressing. 

The bridge has dedicated PCI configuration space accessible through the primary PCI bus. 

2.1.2 Private PCI Device Support 

The 80960RN processor explicitly supports private PCI devices on the secondary PCI bus. The 

bridge and Address Translation Unit work together to hide private PCI devices from PCI 

configuration cycles and allow these hidden devices to use a private PCI address space. The 

Address Translation Unit issues PCI configuration cycles to configure hidden devices. 

2.1.3 DMA Controller 

The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents 

and local memory. Three separate DMA channels accommodate data transfers: two for primary 

PCI bus, one for the secondary PCI bus. The DMA Controller supports chaining and unaligned 

data transfers. The DMA Controller is programmable only through the i960 core processor. 

2.1.4 Address Translation Unit 

The Address Translation Unit (ATU) allows PCI transactions direct access to local memory. The 

80960RN processor has direct access to both PCI buses. The ATU supports transactions between 

PCI address space and 80960RN processor address space. 

Address translation is controlled through programmable registers accessible from both the primary 

PCI interface and the 80960 core. Dual access to registers allows flexibility in mapping the two 

address spaces. 

2.1.5 Messaging Unit 

The Messaging Unit (MU) provides data transfer between the PCI system and the 80960RN 

processor. The Messaging Unit uses interrupts to notify the PCI system or the 80960RN processor 

when new data arrives. The MU has four messaging mechanisms: Message Registers, Doorbell 

Registers, Circular Queues, and Index Registers. Each mechanism allows a host processor or 

external PCI device and the 80960RN processor to communicate through message passing and 

interrupt generation. 

Data Sheet 9


2.1.6 Memory Controller Unit 

The Memory Controller Unit (MCU) allows direct control of a local SDRAM and Flash subsystem. 

The MCU features programmable chip selects, a wait state generator and Error Correction and 

Detection. With the ATU configuration registers, local memory can be configured as PCI 

addressable memory or private processor memory. 

2.1.7 I 2 C Bus Interface Unit 

The I 2 C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and 

slave device residing on the I 2 C bus. The I 2 C bus is a serial bus developed by Philips 

Semiconductor comprising a two pin interface. The bus allows the 80960RN processor to interface 

to other I 2 C peripherals and microcontrollers for system management functions. It requires a 

minimum of hardware for an economical system to relay status and reliability information on the 

I/O subsystem to an external device. For more information, see I 2 C Peripherals for 

Microcontrollers (Philips Semiconductor). 

2.1.8 Secondary PCI Arbitration Unit 

The Secondary PCI Arbitration Unit provides PCI arbitration for the secondary PCI bus. The 

arbitration includes a fairness algorithm with programmable priorities and six external PCI Request 

and Grant signal pairs. 

2.1.9 Application Accelerator Unit 

The Application Accelerator Unit (AAU) provides hardware acceleration of XOR functions 

commonly used in RAID algorithms. Additionally, the AAU provides block moves within local 

memory. The Application Accelerator interfaces the internal bus and operates on data within local 

memory. The AAU is programmable through the i960 core processor and supports chaining and 

unaligned data transfers. 

2.1.10 Performance Monitor Unit 

The Performance Monitor Unit (PMU) allows software to monitor the performance of the different 

buses: Primary PCI, Secondary PCI, and Internal. Multiple performance characteristics are 

captured with 14 mode registers and a global time stamp register. 

2.1.11 Bus Interface Unit 

The Bus Interface Unit (BIU) provides an interface between the 100 MHz 80960JT core and the 

66 MHz internal bus. To optimize performance, the BIU implements prefetching and write merging. 

10 Data Sheet


2.2 Intel ® i960 ® Core Features (Intel ® 80960JT) 

The processing power of the 80960RN processor comes from the 100 MHz 80960JT processor 

core. The 80960JT is a scalar implementation of the 80960 Core Architecture. Figure 2 shows a 

block diagram of the 80960JT Core processor. 

Factors that contribute to the 80960JT core’s performance include: 

• 100 MHz Single-clock execution of most instructions 

• Independent Multiply/Divide Unit 

• Efficient instruction pipeline minimizes pipeline break latency 

• Register and resource scoreboarding allow overlapped instruction execution 

• 128-bit register bus speeds local register caching 

• 16 Kbyte two-way set-associative, integrated instruction cache 

• 4 Kbyte direct-mapped, integrated data cache 

• 1 Kbyte integrated data RAM delivers zero wait state program data 

Figure 2. 

The 80960 core operates out of its own 32-bit address space, which is independent of the PCI 

address space. Local memory can be: 

• Made visible to the PCI address space 

• Kept private to the 80960JT core 

• Allocated as a combination of the two 

Intel ® 80960JT Core Block Diagram 

P_CLK 

TAP 

5 

PLL, Clocks, 

Power Mgmt 

Boundary Scan 

Controller 

8-Set 

Local Register 

Cache 

128 

Global / Local 

Register File 

SRC1 SRC2 DST 

Multiply 

Divide 

Unit 

SRC1 

SRC2 

DST 

Instruction Cache 

16 Kbyte Two-Way Set 

Associative 

Instruction Sequencer 

Constants 

Execution 

and 

Address 

Generation 

Unit 

Effective 

Address 

SRC1 

SRC2 

DST 

Control 

3 Independent 32-Bit SRC1, SRC2, and DST Buses 

Memory 

Interface 

Unit 

32-bit Addr 

32-bit Data 

SRC1 

DST 

32-bit buses 

address / data 

Physical Region 

Configuration 

Bus 

Control Unit 

Bus Request 

Queues 

Two 32-Bit 

Timers 

Control 

Address/ 

Data Bus 

Interrupt 

Programmable 

Port 

Interrupt Controller 9 

Memory-Mapped 

Register Interface 

1Kbyte 

Data RAM 

4Kbyte 

Direct Mapped 

Data Cache 

32 

Data Sheet 11


2.2.1 Burst Bus 

2.2.2 Timer Unit 

A 32-bit high-performance bus controller interfaces the 80960RN processor to the Bus Interface 

Unit. The Bus Control Unit fetches instructions and transfers data on the internal bus at the rate of 

up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed. 

Data caching is programmed through a group of logical memory templates and a defaults register. 

The Bus Control Unit’s features include: 

• Multiplexed external bus minimizes pin count 

• External ready control for address-to-data, data-to-data and data-to-next-address wait state types 

• Little endian byte ordering 

• Unaligned bus accesses performed transparently 

• Three-deep load/store queue decouples the bus from the 80960 core 

Upon reset, the 80960JT conducts an internal self test. Before executing its first instruction, it 

performs an external bus confidence test by performing a checksum on the first words of the 

Initialization Boot Record. 

The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several 

clock rates and generating interrupts. Each is programmed through the Timer Unit registers. These 

memory-mapped registers are addressable on 32-bit boundaries. Timers have a single-shot mode 

and auto-reload capabilities for continuous operation. Each timer has an independent interrupt 

request to the 80960JT’s interrupt controller. The TU can generate a fault when unauthorized writes 

from user mode are detected. 

2.2.3 Priority Interrupt Controller 

Low interrupt latency is critical to many embedded applications. As part of its highly flexible 

interrupt mechanism, the 80960JT exploits several techniques to minimize latency: 

• Interrupt vectors and interrupt handler routines can be reserved on-chip 

• Register frames for high-priority interrupt handlers can be cached on-chip 

• The interrupt stack can be placed in cacheable memory space 

2.2.4 Faults and Debugging 

The 80960JT employs a comprehensive fault model. The processor responds to faults by making 

implicit calls to a fault handling routine. Specific information collected for each fault allows the 

fault handler to diagnose exceptions and recover appropriately. 

The processor also has built-in debug capabilities. With software, the 80960JT may be configured 

to detect as many as seven different trace event types. Alternatively, mark and fmark instructions 

can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are 

also available to trap on execution and data addresses. 

2.2.5 On-Chip Cache and Data RAM 

Memory subsystems often impose substantial wait state penalties. The 80960JT integrates 

considerable storage resources on-chip to decouple CPU execution from the external bus. The 

80960JT includes a 16 Kbyte instruction cache, a 4 Kbyte data cache and 1 Kbyte data RAM. 

12 Data Sheet


2.2.6 Local Register Cache 

The 80960JT rapidly allocates and deallocates local register sets during context switches. The processor 

needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. 

2.2.7 Test Features 

The 80960RN processor incorporates numerous features that enhance the user’s ability to test both 

the processor and the system to which it is attached. These features include ONCE (On-Circuit 

Emulation) mode and Boundary Scan (JTAG). 

The 80960JT provides testability features compatible with IEEE Standard Test Access Port and 

Boundary Scan Architecture (IEEE Std. 1149.1). 

One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE 

mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism. 

ONCE mode is useful for board-level testing. This feature allows a mounted 80960RN processor to 

electrically “remove” itself from a circuit board allowing system-level testing where a remote 

tester can exercise the processor system. 

The test logic does not interfere with component or system behavior and ensures that components 

function correctly and the connections between various components are correct. 

The JTAG Boundary Scan feature is an alternative to conventional “bed-of-nails” testing. 

Boundary Scan can examine connections that might otherwise be inaccessible to a test system. 

2.2.8 Memory-Mapped Control Registers 

The 80960JT is compliant with 80960 family architecture. Each memory-mapped, 32-bit register is 

accessed via memory-format instructions. The processor ensures that these accesses do not 

generate external bus cycles. 

2.2.9 Instructions, Data Types and Memory Addressing Modes 

As with all 80960 family processors, the instruction set supports several different data types and formats: 

• Bit 

• Bit fields 

• Integer (8-, 16-, 32-, 64-bit) 

• Ordinal (8-, 16-, 32-, 64-bit unsigned integers) 

• Triple word (96 bits) 

• Quad word (128 bits) 

The 80960JT provides a full set of addressing modes for C and assembly: 

• Two Absolute modes 

• Five Register Indirect modes 

• Index with displacement mode 

• IP with displacement mode 

Data Sheet 13


Table 2 shows the available 80960JT instructions. 

Table 2. 

Instruction Set 

Data Movement Arithmetic Logical Bit, Bit Field and Byte 

Add 

Subtract 

Load 

Store 

Move 

Conditional Select 

Load Address 

Multiply 

Divide 

Remainder 

Modulo 

Shift 

Extended Shift 

Extended Multiply 

Extended Divide 

Add with Carry 

Subtract with Carry 

Conditional Add 

Conditional Subtract 

Rotate 

And 

Not And 

And Not 

Or 

Exclusive Or 

Not Or 

Or Not 

Nor 

Exclusive Nor 

Not 

Nand 

Set Bit 

Clear Bit 

Not Bit 

Alter Bit 

Scan For Bit 

Span Over Bit 

Extract 

Modify 

Scan Byte for Equal 

Byte Swap 

Comparison Branch Call/Return Fault 

Compare 

Conditional Compare 

Compare and Increment 

Compare and 

Decrement 

Test Condition Code 

Check Bit 

Unconditional Branch 

Conditional Branch 

Compare and Branch 

Call 

Call Extended 

Call System 

Return 

Branch and Link 

Conditional Fault 

Synchronize Faults 

Debug 

Processor 

Management 

Atomic 

Flush Local Registers 

Modify Trace Controls 

Mark 

Force Mark 

Modify Arithmetic 

Controls 

Modify Process Controls 

Halt 

System Control 

Cache Control 

Interrupt Control 

Atomic Add 

Atomic Modify 

14 Data Sheet


3.0 Package Information 

3.1 Package Introduction 

The 80960RN processor is offered in a Perimeter Land Grid Array (PBGA) package. This is a 

perimeter array package with five rows of ball connections in the outer area of the package. See 

Figure 4 “540L H-PBGA Package Diagram (Bottom View)” on page 27. 

3.1.1 Functional Signal Definitions 

This section defines the pins and signals in the following tables: 

• Table 3 “Pin Description Nomenclature” on page 16 

• Table 4 “Memory Controller Signals” on page 17 

• Table 5 “Primary PCI Bus Signals” on page 20 

• Table 6 “Secondary PCI Arbiter Signals” on page 21 

• Table 8 “Intel ® 80960Jx Core Signals and Configuration Straps” on page 24 

• Table 9 “I 2 C, JTAG, Core Signals” on page 25 

Data Sheet 15


3.1.1.1 Signal Pin Descriptions 

Table 3. 

Pin Description Nomenclature 

Symbol 

Description 

I 

O 

I/O 

Input pin only 

Output pin only 

Pin can be either an input or output 

OD Open Drain pin 

- Pin must be connected as described 

N/C 

5V 

Sync(...) 

Async 

Prst(...) 

Srst(...) 

Irst(...) 

P32(...) 

S32(...) 

NO CONNECT. Do not make electrical connections to these balls. 

Input pin is 5 volt tolerant 

Synchronous. Inputs meet setup and hold times relative to an input clock. 

Sync(P) Synchronous to P_CLK 

Sync(D) Synchronous to DCLKIN 

Sync(T) Synchronous to TCK 

Asynchronous. Inputs may be asynchronous relative to P_CLK, DCLKIN, orTCK. All 

asynchronous signals are level-sensitive. 

While the P_RST# pin is asserted, the pin: 

Prst(1) Is driven to Vcc 

Prst(0) Is driven to Vss 

Prst(X) Is driven to unknown state 

Prst(H)IspulleduptoVcc 

Prst(L)IspulleddowntoVss 

Prst(Z) Floats 

Prst(Q) Is a valid output 

Since P_RST# is asynchronous, these are asynchronous events. 

While the S_RST# pin is asserted, the pin: 

Srst(1) Is driven to Vcc 

Srst(0) Is driven to Vss 

Srst(X) Is driven to unknown state 

Srst(H)IspulleduptoVcc 

Srst(L)IspulleddowntoVss 

Srst(Z) Floats 

Srst(Q) Is a valid output 

Note that S_RST# is asserted when P_RST# is asserted or BCR[6] is set with software. 

While the I_RST# pin is asserted, the pin: 

Irst(1) Is driven to Vcc 

Irst(0) Is driven to Vss 

Irst(X) Is driven to unknown state 

Irst(H)IspulleduptoVcc 

Irst(L)IspulleddowntoVss 

Irst(Z) Floats 

Irst(Q) Is a valid output 

Note that I_RST# is asserted when P_RST# is asserted or EBCR[5] is set with software. 

While the Primary PCI Bus is configured as a 32-bit PCI bus by the Primary central resource: 

P32(H) is pulled up internally to Vcc 

P32(L) is pulled down internally to Vss 

While the Secondary PCI Bus is configured as a 32-bit PCI bus with 32BITPCI_EN#: 

S32(H) is pulled up internally to Vcc 

S32(L) is pulled down internally to Vss 

16 Data Sheet


Table 4. Memory Controller Signals (Sheet 1 of 3) 

Name Count Type Description 

DCLKOUT 

1 O 

Irst(Q) 

SDRAM OUTPUT CLOCK dedicated for SDRAM memory 

subsystem. 

DCLKIN 

1 I SDRAM INPUT CLOCK dedicated for SDRAM memory 

subsystem. Used to skew DCLKOUT appropriately to 

accommodate flight time and clock buffer delays. 

SA[11:0] 

SBA[1:0] 

SRAS# 

SCAS# 

SDQM[7:0] 

SWE# 

SCE[1:0]# 

SCKE[1:0] 

DQ[63:0] 

SCB[7:0] 

ROE# 

RWE# 

RCE[1:0]# 

RALE 

12 O 

Irst(Q) 

2 O 

Irst(Q) 

1 O 

Irst(1) 

1 O 

Irst(1) 

8 O 

Irst(1) 

1 O 

Irst(1) 

2 O 

Irst(1) 

2 O 

Irst(Q) 

64 I/O 

Irst(1) 

Sync(D) 

8 I/O 

Irst(1) 

Sync(D) 

1 O 

Irst(1) 

1 O 

Irst(1) 

2 O 

Irst(1) 

1 O 

Irst(0) 

SDRAM MULTIPLEXED ADDRESS BUS carries the multiplexed 

row and column addresses to the SDRAM memory banks. For 

SA[10], see note 1. 

SDRAM INTERNAL BANK SELECT indicates which of the SDRAM 

internal banks are read or written during the current transaction. 

SDRAM ROW ADDRESS STROBE indicates the presence of a valid 

row address on the Multiplexed Address Bus SA[11:0]. See note 1. 

SDRAM COLUMN ADDRESS STROBE indicates the presence of 

a valid column address on the Multiplexed Address Bus SA[11:0]. 

Seenote1. 

SDRAM DATA MASK controls which of the eight bytes on the data 

bus should be written or read. When SDQM[7:0] asserted, the 

SDRAM devices do not accept/drive valid data from/to the byte 

lanes. When SDQM[7:0] deasserted, the SDRAM devices 

accept/drivevaliddatafrom/tothebytelanes. 

By convention, SDQM[1] masks two x8 SDRAM devices. 

Functionally, all SDQM[7:0] signals are equivalent. 

SDRAM WRITE ENABLE indicates that the current memory 

transaction is a write operation. See note 1. 

SDRAM CHIP ENABLE enables the SDRAM devices for a 

memory access (1 per bank supported). See note 1. 

SCKE[1:0] are the clock enables for the SDRAM memory. 

Deasserting will place the SDRAM in self-refresh mode. See note 1. 

DATA BUS carries 64-bit data to and from memory. During a data 

(T d ) cycle, read or write data is present on one or more contiguous 

bytes, comprising DQ[63:56], DQ[55:48], DQ[47:40], DQ[39:32], 

DQ[31:24], DQ[23:16], DQ[15:8] and DQ[7:0]. During write 

operations, unused pins are driven to determinate values. 

ERROR CORRECTION CODE carries the 8-bit ECC code to and 

from memory during data cycles. 

ROM OUTPUT ENABLE specifies, during a T a cycle, whether the 

operation is a write (1) or read (0) to the ROM interface. It remains 

valid during T d cycles. When ROE# is asserted, the data is 

transferred from the memory on RAD[16:9]. 

ROM WRITE ENABLE indicates the direction data is to be 

transferred to/from ROM and controls the WE input on the ROM 

device. When RWE# is asserted, the data is transferred to the 

memory on DQ[7:0]. 

FLASH CHIP ENABLE enables Flash devices for a memory access. 

ROM ADDRESS LATCH ENABLE indicates the cycle in which the 

address on RAD[16:3] should be externally latched for the Flash 

subsystem. 

Data Sheet 17




RAD[16:9] 

RAD[8] 

RAD[7] 

RAD[6]/ 

RST_MODE# 

(Config. Pin) 

RAD[5] 

RAD[4]/ 

STEST 

(Config. Pin) 

RAD[3]/ 

RETRY 

(Config. Pin) 

8 I/O 

5V 

Irst(X) 

Sync(D) 

1 O 

Prst(H) 

1 O 

Prst(H) 

1 I/O 

5V 

Prst(H) 

1 O 

Prst(H) 

1 I/O 

5V 

Prst(H) 

1 I/O 

5V 

Prst(H) 

FLASH ADDRESS/DATA BUS: Duringanaddress(T a ) cycle, bits 

16:9 contain a physical word address. During a data cycle (Td), bits 

16:9 carry data bits 16:9 of the Flash data byte. 

FLASH ADDRESS BUS: During an address (T a ) cycle, bit 8 contain 

a physical word address. RAD[8]. multiplexes physical address bits 

[22] with [8]. Refer to the MCU chapter of the i960 ® RM/RN I/O 

Processor Developer’s Manual for details. 



[21] with [7]. Refer to the MCU chapter of the i960 ® RM/RN I/O 

Processor Developer’s Manual for details. 



[20] with [6]. Within four clocks after the deassertion of P_RST#, 

this pin is an output only. Refer to the MCU chapter of the i960 ® 

RM/RN I/O Processor Developer’s Manual for details. 

RESET MODE is sampled at Primary PCI bus reset to determine if 

the 80960RN processor is to be held in reset. If asserted, the 

80960RN processor will be held in reset until the 80960 Processor 

Reset bit is cleared in the Extended Bridge Control Register. 











SELF TEST enables or disables the processor’s internal self-test 

feature at initialization. STEST is examined at the end of P_RST#. 

When STEST is asserted, the processor performs its internal 

self-test and the external bus confidence test. When STEST is 

deasserted, the processor performs only the external bus 

confidence test. 

0 = Self Test Disabled 

1 = Self Test Enabled 






RETRY is sampled at Primary PCI bus reset to determine if the 

Primary PCI interface will be disabled. If high, the Primary PCI 

interface will disable PCI configuration cycles by signaling a Retry 

until the Configuration Cycle Retry bit is cleared in the Extended 

Bridge Control Register. If low, the Primary PCI interface allow 

configuration cycles to occur. 

18 Data Sheet




RAD[2]/ 

32BITMEM_EN# 

(Config. Pin) 

RAD[1]/ 

32BITPCI_EN# 

(Config. Pin) 

RAD[0] 

1 I/O 

5V 

Prst(H) 

1 I/O 

5V 

Prst(H) 

1 O 

Prst(H) 

FLASH ADDRESS BUS: During an address (T a ) cycle, bit 2 

contains a physical word address. Within four clocks after the 

deassertion of P_RST#, this pin is an output only. Refer to the MCU 

chapter of the i960 ® RM/RN I/O Processor Developer’s Manual for 

details. 

32-BIT Memory Enable The 32BITMEM_EN# signal is sampled at 

Primary PCI Reset to notify the memory controller if 32-bit wide 

SDRAM memories are connected to the memory controller. 

If 32BITMEM_EN# is high, the memory controller supports the 

64-bit SDRAM protocol for accesses to SDRAM memories. 

If 32BITMEM_EN# is low, the memory controller supports the 

32-bit SDRAM protocol for accesses to SDRAM memories. 


contains a physical word address. Within four clocks after the 

deassertion of P_RST#, this pin is an output only. Refer to the MCU 

chapter of the i960 ® RM/RN I/O Processor Developer’s Manual for 

details. 

32-BIT Secondary PCI Enable The 32BITPCI_EN# signal is 

sampled at Primary PCI Reset to notify the secondary PCI arbiter 

NOT to generate the 64-bit protocol of the rising edge of the 

secondary reset for the secondary PCI bus. 

If 32BITPCI_EN# is high, the secondary PCI arbiter asserts 

S_REQ64# during S_RST#, indicating the secondary PCI bus is a 

64-bit bus. 

If 32BITPCI_EN# is low, the secondary PCI arbiter does not assert 

S_REQ64# during S_RST#, indicating the secondary PCI bus is 

NOT a 64-bit bus. 


contains a physical word address. Refer to the MCU chapter of the 

i960 ® RM/RN I/O Processor Developer’s Manual for details. 

NOTE: 

1. These pins remain functional for 20 DCLKIN periods after I_RST# is asserted for a warm boot. The 

designated Irst() state applies after 20 DCLKIN periods after I_RST# is asserted. For more details, refer to 

the MCU Chapter of the i960 ® RM/RN I/O Processor Developer’s Manual. 

Data Sheet 19


Table 5. Primary PCI Bus Signals (Sheet 1 of 2) 


P_AD[31:0] 32 

P_AD[63:32] 32 

P_PAR 1 

P_PAR64 1 

P_C/BE[3:0]# 4 

P_C/BE[7:4]# 4 

P_REQ# 1 

P_REQ64# 1 

P_GNT# 1 

P_ACK64# 1 

P_FRAME# 1 

P_IRDY# 1 

P_TRDY# 1 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

P32(H) 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

P32(H) 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

P32(H) 

O 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

P32(Z) 

I 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

P32(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

PRIMARY PCI ADDRESS/DATA is the multiplexed PCI address 

and bottom 32 bits of the data bus. 

PRIMARY PCI DATA is the upper 32 bits of the primary PCI data 

bus driven during the data phase. 

PRIMARY PCI BUS PARITY is even parity across P_AD[31:0] and 

P_C/BE[3:0]#. 

PRIMARY PCI BUS UPPER DWORD PARITY is even parity 

across P_AD[63:32] and P_C/BE[7:4]#. 

PRIMARY PCI BUS COMMAND and BYTE ENABLES are 

multiplexed on the same PCI pins. During the address phase, they 

define the bus command. During the data phase, they are used as 

byte enables for P_AD[31:0]. 

PRIMARY PCI BUS BYTE ENABLES are as byte enables for 

P_AD[63:32] during the data phase. 

PRIMARY PCI BUS REQUEST indicates to the primary PCI bus 

arbiter that the 80960RN processor desires use of the PCI bus. 

PRIMARY PCI BUS REQUEST 64-BIT TRANSFER indicates the 

attempt of a 64-bit transaction on the primary PCI bus. If the target 

is 64-bit capable, the target acknowledges the attempt with the 

assertion of P_ACK64#. 

PRIMARY PCI BUS GRANT indicates that access to the primary 

PCI bus has been granted. 

PRIMARY PCI BUS ACKNOWLEDGE 64-BIT TRANSFER 

indicates that the device has positively decoded its address as the 

target of the current access and the target is willing to transfer data 

using the full 64-bit data bus. 

PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the 

beginning and duration of an access. 

PRIMARY PCI BUS INITIATOR READY indicates the initiating 

agent’s ability to complete the current data phase of the 

transaction. During a write, it indicates that valid data is present on 

the Address/Data bus. During a read, it indicates the processor is 

ready to accept the data. 

PRIMARY PCI BUS TARGET READY indicates the target agent’s 

ability to complete the current data phase of the transaction. During a 

read, it indicates that valid data is present on the Address/Data bus. 

During a write, it indicates the target is ready to accept the data. 

20 Data Sheet


Table 5. Primary PCI Bus Signals (Sheet 2 of 2) 


P_STOP# 1 

P_DEVSEL# 1 

P_SERR# 1 

P_CLK 1 

P_RST# 1 

P_PERR# 1 

P_LOCK# 1 

P_IDSEL 1 

P_INT[A:D]# 4 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

Sync(P) 

Prst(Z) 

I/O 

5V 

OD 

Sync(P) 

Prst(Z) 

I 

5V 

I 

5V 

Async 

I/O 

5V 

Sync(P) 

Prst(Z) 

I 

5V 

Sync(P) 

I 

5V 

Sync(P) 

O 

OD 

Prst(Z) 

PRIMARY PCI BUS STOP indicates a request to stop the current 

transaction on the primary PCI bus. 

PRIMARY PCI BUS DEVICE SELECT is driven by a target agent 

that has successfully decoded the address. As an input, it indicates 

whether or not an agent has been selected. 

PRIMARY PCI BUS SYSTEM ERROR is driven for address parity 

errors on the primary PCI bus. 

PRIMARY PCI BUS INPUT CLOCK provides the timing for all 

primary PCI transactions and is the clock source for all internal 

80960RN units. 

PRIMARY RESET brings PCI-specific registers, sequencers, and 

signals to a consistent state. When P_RST# is asserted: 

PCI output signals are driven to a known consistent state. 

PCI bus interface output signals are three-stated. 

open drain signals such as P_SERR# are floated. 

P_RST# may be asynchronous to P_CLK when asserted or 

deasserted. Although asynchronous, deassertion must be 

guaranteed to be a clean, bounce-free edge. 

PRIMARY PCI BUS PARITY ERROR is asserted when a data 

parity error occurs during a primary PCI bus transaction. 

PRIMARY PCI BUS LOCK indicates the need to perform an atomic 

operation on the primary PCI bus. 

PRIMARY PCI BUS INITIALIZATION DEVICE SELECT is used to 

select the 80960RN during a Configuration Read or Write 

command on the primary PCI bus. 

PRIMARY PCI BUS INTERRUPT requests an interrupt. The 

assertion and deassertion of P_INT[A:D]# is asynchronous to 

P_CLK. A device asserts its P_INT[A:D]# line when requesting 

attention from its device driver. Once the P_INT[A:D]# signal is 

asserted, it remains asserted until the device driver clears the 

pending request. P_INT[A:D]# Interrupts are level sensitive. 

Table6. 

SecondaryPCIArbiterSignals 


S_REQ[5:0]# 

S_GNT[5:0]# 

6 I 

5V 

Sync(P) 

6 O 

Srst(Z) 

SECONDARY PCI BUS REQUESTS are the request signals from 

devices 0 through 5 on the secondary PCI bus. 

SECONDARY PCI BUS GRANT are grant signals sent to devices 

5-0 on the secondary PCI bus 

Data Sheet 21


Table 7. Secondary PCI Bus Signals (Sheet 1 of 2) 


S_AD[31:0] 32 

S_AD[63:32] 32 

S_PAR 1 

S_PAR64 1 

S_C/BE[3:0]# 4 

S_C/BE[7:4]# 4 

S_REQ64# 1 

S_ACK64# 1 

S_FRAME# 1 

S_IRDY# 1 

S_TRDY# 1 

S_STOP# 1 

I/O 

5V 

Sync(P) 

Srst(0) 

I/O 

5V 

Sync(P) 

Srst(Z) 

S32(H) 

I/O 

Sync(P) 

Srst(0) 

I/O 

5V 

Sync(P) 

Srst(Z) 

S32(H) 

I/O 

5V 

Sync(P) 

Srst(0) 

I/O 

5V 

Sync(P) 

Srst(Z) 

S32(H) 

I/O 

5V 

Sync(P) 

Srst(Q) 

S32(Z) 

I/O 

5V 

Sync(P) 

Srst(Z) 

S32(Z) 

I/O 

5V 

Sync(P) 

Srst(Z) 

I/O 

5V 

Sync(P) 

Srst(Z) 

I/O 

5V 

Sync(P) 

Srst(Z) 

I/O 

5V 

Sync(P) 

Srst(Z) 

SECONDARY PCI ADDRESS/DATA is the multiplexed secondary 

PCI address and lower 32 bits of the data bus. 

SECONDARY PCI DATA is the upper 32 bits of the secondary PCI 

data bus. 

SECONDARY PCI BUS PARITY is even parity across S_AD[31:0] 

and S_C/BE[3:0]#. 

SECONDARY PCI BUS UPPER DWORD PARITY is even parity 

across S_AD[63:32] and S_C/BE[7:4]#. 

SECONDARY PCI BUS COMMAND and BYTE ENABLES are 

multiplexed on the same PCI pins. During the address phase, they 

define the bus command. During the data phase, they are used as 

the byte enables for S_AD[31:0]. 

SECONDARY PCI BYTE ENABLES are used as byte enables for 

S_AD[63:32] during secondary PCI data phases. 

SECONDARY PCI BUS REQUEST 64-BIT TRANSFER indicates 

the attempt of a 64-bit transaction on the secondary PCI bus. If the 

target is 64-bit capable, the target acknowledges the attempt with 

the assertion of S_ACK64#. 

SECONDARY PCI BUS ACKNOWLEDGE 64-BIT TRANSFER 

indicates that the device has positively decoded its address as the 

target of the current access, indicates the target is willing to transfer 

data using 64 bits. 

SECONDARY PCI BUS CYCLE FRAME is asserted to indicate the 

beginning and duration of an access. 

SECONDARY PCI BUS INITIATOR READY indicates the initiating 


transaction. During a write, it indicates that valid data is present on 

the secondary Address/Data bus. During a read, it indicates the 

processor is ready to accept the data. 

SECONDARY PCI BUS TARGET READY indicates the target 


transaction. During a read, it indicates that valid data is present on 

the secondary Address/Data bus. During a write, it indicates the 

target is ready to accept the data. 

SECONDARY PCI BUS STOP indicates a request to stop the 

current transaction on the secondary PCI bus. 

22 Data Sheet


Table 7. Secondary PCI Bus Signals (Sheet 2 of 2) 


S_DEVSEL# 1 

S_SERR# 1 

S_RST# 1 

S_PERR# 1 

S_LOCK# 1 

I/O 

5V 

Sync(P) 

Srst(Z) 

I/O 

5V 

OD 

Sync(P) 

Srst(Z) 

O 

Async 

I/O 

5V 

Sync(P) 

Srst(Z) 

I/O 

5V 

Sync(P) 

Srst(Z) 

SECONDARY PCI BUS DEVICE SELECT is driven by a target 

agent that has successfully decoded the address. As an input, it 

indicates whether or not an agent has been selected. 

SECONDARY PCI BUS SYSTEM ERROR is driven for address 

parity errors on the secondary PCI bus. 

SECONDARY PCI BUS RESET is an output based on P_RST#. It 

brings PCI-specific registers, sequencers, and signals to a 

consistent state. When P_RST# is asserted or BCR[6] is set, it 

causes S_RST# to assert and: 

• PCI output signals are driven to a known consistent state. 

• PCI bus interface output signals are three-stated. 

• open drain signals such as S_SERR# are floated 

S_RST# may be asynchronous to S_CLKIN when asserted or 

deasserted. Although asynchronous, deassertion must be 

guaranteed to be a clean, bounce-free edge. 

SECONDARY PCI BUS PARITY ERROR is asserted when a data 

parity error during a secondary PCI bus transaction. 

SECONDARY PCI BUS LOCK indicates the need to perform an 

atomic operation on the secondary PCI bus. 

Data Sheet 23


Table 8. 

Intel ® 80960Jx Core Signals and Configuration Straps 


SECONDARY PCI BUS INTERRUPT REQUESTS. S_INT[D:A]# 

assertion and deassertion is asynchronous to P_CLK. Asdevice 

asserts S_INT[D:A]# when requesting attention from it device 

driver. When S_INT[D:A]# is asserted, it remains asserted until the 

device driver clears the pending request. S_INT[D:A]# interrupts 

are level low sensitive. 

XINT[3:0]#/ 

S_INT[D:A]# 

4 

I 

5V 

Async 

EXTERNAL INTERRUPT. External devices use this signal to 

request an interrupt service. These signals operate in dedicated 

mode, where each signal is assigned a dedicated interrupt level. 

The S_INT[D:A]#/XINT[3:0]# signals can be directed as follows: 

Sec. PCIPrimary PCIi960 core processor 

S_INTA#⇒P_INTA# or XINT0# 

S_INTB#⇒P_INTB# or XINT1# 

S_INTC#⇒P_INTC# or XINT2# 

S_INTD#⇒P_INTD# or XINT3# 

XINT[5:4]# 2 

NMI# 1 

I 

5V 

Async 

I 

5V 

Async 

EXTERNAL INTERRUPT pins are used to request 80960RN 

interrupt service. 

NON-MASKABLE INTERRUPT causes an i960 core processor 

non-maskable interrupt event to occur. NMI# is the highest priority 

interrupt source. 

V CC5REF 1 - 

V CCPLL 3 - 

INPUT REFERENCE VOLTAGE is strapped to 5 V. This reference 

voltage allows the 80960RN input pins to be 5 V tolerant. 

PLL POWER is a separate V CC supply pin for the phase lock loop 

clock generator. It is intended for external connection to the V CC 

board plane. In noisy environments, add a simple bypass filter 

circuit to reduce noise-induced clock jitter and its effects on timing 

relationships. 

FAIL# 1 

O 

Irst(0) 

FAIL indicates a failure of the processor’s built-in self-test 

performed during initialization. FAIL# is asserted immediately upon 

reset and toggles during self-test to indicate the status of individual 

tests: 

When self-test passes, the processor deasserts FAIL# and 

commences operation from user code. 

When self-test fails, the processor asserts FAIL# and then stops 

executing. Self-test failing does not cause the bridge to stop 

execution. 

0 = Self Test Failed 

1 = Self Test Passed 

24 Data Sheet


Table 9. 

I 2 C, JTAG, Core Signals 


TCK 1 

I 

5V 

TEST CLOCK is an input which provides the clocking function for 

the IEEE 1149.1 Boundary Scan Testing (JTAG). State information 

and data are clocked into the component on the rising edge and 

data is clocked out of the component on the falling edge. 

TDI 1 

I 

5V 

Sync(T) 

TDO 1 O 

TEST DATA INPUT is the serial input pin for the JTAG feature. TDI 

is sampled on the rising edge of TCK, during the SHIFT-IR and 

SHIFT-DR states of the Test Access Port. This signal has a weak 

internal pull-up to ensure proper operation when this signal is 

unconnected. 

TEST DATA OUTPUT is the serial output pin for the JTAG feature. 

TDO is driven on the falling edge of TCK during the SHIFT-IR and 

SHIFT-DR states of the Test Access Port. At other times, TDO floats. 

TRST# 1 

TMS 1 

SDA 1 

SCL 1 

LCDINIT# 1 

I_RST# 1 

ONCE# 

(Config. Pin) 

1 

I 

5V 

Async 

I 

5V 

Sync(T) 

I/O 

5V 

OD 

Irst(Z) 

I/O 

5V 

OD 

Irst(Z) 

I 

Sync(I) 

O 

Async 

I 

5V 

TEST RESET asynchronously resets the Test Access Port (TAP) 

controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). 

This signal has a weak internal pull-up to ensure proper operation 

when this signal is unconnected. 

TEST MODE SELECT is sampled at the rising edge of TCK to 

select the operation of the test logic for IEEE 1149.1 Boundary 

Scan testing. This signal has a weak internal pull-up to ensure 

proper operation when this signal is unconnected. 

I 2 CDATAis used for data transfer and arbitration on the I 2 Cbus. 

I 2 CCLOCKprovides synchronous operation of the I 2 Cbus. 

LCD INITIALIZATION is a static signal used to initialize the internal 

logic for the LCD960 debugger. This signal has an internal pull-up 

for normal operation. 

INTERNAL BUS RESET indicates when the internal bus has been 

reset with P_RST# or a software reset. 

ONCE MODE: The processor samples this pin during reset. If it is 

asserted LOW at the end of reset, the processor enters ONCE 

Mode. In ONCE Mode, the processor stops all clocks and floats all 

output pins except the TDO and RAD[8:0] pins. The pin has a weak 

internal pull-up which is active during reset to ensure normal 

operation if the pin is left unconnected. 

Data Sheet 25


3.1.2 540-Lead H-PBGA Package 

Figure 3. 

540L H-PBGA Package Diagram (Top and Side View) 

Pin#1Corner 

42.500 ± 0.200 

GC80960RN100 

SSSSSS 

MALAY 

FFFFFFFF-[{SN}] 

M 

INTEL © ‘98 

27.700 

27.700 

42.500 ± 0.200 

0.55 ± 0.15 

Slug 

1.56 REF 

Seating Plane 

1.025 ± 0.075 

3.845 ± 0.255 

Ball spacing is 1.270 

Ball width is 0.750 ± 0.150 

2.150 ± 0.150 

NOTES: 

1. All dimensions and tolerances conform to ANSI Y14.5M 1982. 

2. Dimensions are measured at the maximum solder ball diameter parallel to primary datum. 

3. Primary datum and seating plane are defined by the spherical crowns of the solder balls. 

4. All dimensions are in millimeters. 

5. S spec numbers are only printed on the C-X steppings. 

26 Data Sheet


Figure 4. 

540L H-PBGA Package Diagram (Bottom View) 

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 

AM 

AL 

AK 

AJ 

AH 

AG 

AF 

AE 

AD 

AC 

AB 

AA 

Y 

W 

V 

U 

T 

R 

P 

N 

M 

L 

K 

J 

H 

G 

F 

E 

D 

C 

B 

A 

AM 

AL 

AK 

AJ 

AH 

AG 

AF 

AE 

AD 

AC 

AB 

AA 

Y 

W 

V 

U 

T 

R 

P 

N 

M 

L 

K 

J 

H 

G 

F 

E 

D 

C 

B 

A 

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 

Data Sheet 27


Table 10. 540-Lead H-PBGA Package — Signal Name Order (Sheet 1 of 5) 

Signal Ball # Signal Ball # Signal Ball # 

DCLKIN E21 DQ35 C24 N/C AG1 

DCLKOUT A22 DQ36 E24 N/C AL16 

DQ00 D22 DQ37 B25 P_ACK64# V5 

DQ01 A23 DQ38 E25 P_AD00 U1 

DQ02 C23 DQ39 C26 P_AD01 U2 

DQ03 A24 DQ40 A27 P_AD02 U3 

DQ04 D24 DQ41 C27 P_AD03 T1 

DQ05 A25 DQ42 A28 P_AD04 T3 

DQ06 C25 DQ43 G32 P_AD05 T4 

DQ07 A26 DQ44 H31 P_AD06 T5 

DQ08 E26 DQ45 H28 P_AD07 R1 

DQ09 B27 DQ46 J30 P_AD08 R3 

DQ10 E27 DQ47 J28 P_AD09 R5 

DQ11 C28 DQ48 W28 P_AD10 P1 

DQ12 H32 DQ49 Y31 P_AD11 P3 

DQ13 H30 DQ50 Y28 P_AD12 P4 

DQ14 J32 DQ51 AA30 P_AD13 P5 

DQ15 J29 DQ52 AA28 P_AD14 N1 

DQ16 W29 DQ53 AB31 P_AD15 N2 

DQ17 Y32 DQ54 AB28 P_AD16 K3 

DQ18 Y30 DQ55 AC30 P_AD17 K4 

DQ19 AA32 DQ56 AC28 P_AD18 K5 

DQ20 AA29 DQ57 AD31 P_AD19 J1 

DQ21 AB32 DQ58 AD28 P_AD20 J2 

DQ22 AB30 DQ59 AE30 P_AD21 J3 

DQ23 AC32 DQ60 AE28 P_AD22 J5 

DQ24 AC29 DQ61 AF31 P_AD23 H1 

DQ25 AD32 DQ62 AF28 P_AD24 H5 

DQ26 AD30 DQ63 AH32 P_AD25 G1 

DQ27 AE32 FAIL# E12 P_AD26 G2 

DQ28 AE29 LCDINIT# A21 P_AD27 G3 

DQ29 AF32 I_RST# A11 P_AD28 E5 

DQ30 AF30 ONCE# C21 P_AD29 A6 

DQ31 AG32 NMI# A9 P_AD30 C6 

DQ32 E22 N/C A16 P_AD31 D6 

DQ33 B23 N/C G5 P_AD32 AG2 

DQ34 E23 N/C V28 P_AD33 AG3 

28 Data Sheet




P_AD34 AF1 P_C/BE6# V3 RALE B19 

P_AD35 AF3 P_C/BE7# V4 RCE0# C19 

P_AD36 AF4 P_FRAME# L5 RCE1# E19 

P_AD37 AF5 P_DEVSEL# L1 P_IDSEL H3 

P_AD38 AE1 P_GNT# A7 ROE# D20 

P_AD39 AE2 P_INTA# E8 RWE# A20 

P_AD40 AE3 P_INTB# D8 SA00 N30 

P_AD41 AE5 P_INTC# E7 SA01 N29 

P_AD42 AD1 P_INTD# C7 SA02 N28 

P_AD43 AD3 P_IRDY# L3 SA03 P32 

P_AD44 AD4 P_LOCK# M4 SA04 P31 

P_AD45 AD5 P_PAR N3 SA05 P30 

P_AD46 AC1 P_PAR64 W3 SA06 P28 

P_AD47 AC2 P_PERR# M3 SA07 R32 

P_AD48 AC3 P_SERR# M1 SA08 R30 

P_AD49 AC5 P_STOP# M5 SA09 R29 

P_AD50 AB1 P_REQ# E6 SA10 R28 

P_AD51 AB3 P_REQ64# U5 SA11 T32 

P_AD52 AB4 P_RST# B7 SBA0 T31 

P_AD53 AB5 P_TRDY# L2 SBA1 T30 

P_AD54 AA1 RAD00 A13 SCAS# L30 

P_AD55 AA2 RAD01 B13 SCB0 K32 

P_AD56 AA3 RAD02 C13 SCB1 K30 

P_AD57 AA5 RAD03 E13 SCB2 V31 

P_AD58 Y1 RAD04 A14 SCB3 W32 

P_AD59 Y3 RAD05 C14 SCB4 K31 

P_AD60 Y4 RAD06 D14 SCB5 K28 

P_AD61 Y5 RAD07 E14 SCB6 V30 

P_AD62 W1 RAD08 A15 SCB7 W30 

P_AD63 W2 RAD09 C15 SCE0# M30 

P_CLK C20 RAD10 E15 SCE1# M28 

P_C/BE0# R2 RAD11 E17 SCKE0 T28 

P_C/BE1# N5 RAD12 A18 SCKE1 U32 

P_C/BE2# K1 RAD13 C18 SCL A8 

P_C/BE3# H4 RAD14 D18 SDA C8 

P_C/BE4# W5 RAD15 E18 SDQM0 L29 

P_C/BE5# V1 RAD16 A19 SDQM1 M32 

Data Sheet 29




SDQM2 U30 S_AD28 AJ25 S_C/BE1# AJ19 

SDQM3 U28 S_AD29 AK25 S_C/BE2# AM21 

SDQM4 L28 S_AD30 AM25 S_C/BE3# AH24 

SDQM5 M31 S_AD31 AH26 S_C/BE4# AL12 

SDQM6 U29 S_AD32 AH1 S_C/BE5# AM12 

SDQM7 V32 S_AD33 AH3 S_C/BE6# AH13 

SRAS# N32 S_AD34 AH4 S_C/BE7# AJ13 

SWE# L32 S_AD35 AJ2 S_DEVSEL# AM20 

S_ACK64# AM13 S_AD36 AJ5 S_FRAME# AK21 

S_AD00 AH14 S_AD37 AK5 S_GNT0# AM26 

S_AD01 AK14 S_AD38 AM5 S_GNT1# AJ27 

S_AD02 AL14 S_AD39 AH6 S_GNT2# AM27 

S_AD03 AM14 S_AD40 AK6 S_GNT3# AK28 

S_AD04 AH15 S_AD41 AL6 S_GNT4# AM28 

S_AD05 AJ15 S_AD42 AM6 S_GNT5# AK29 

S_AD06 AK15 S_AD43 AH7 S_IRDY# AJ21 

S_AD07 AM15 S_AD44 AJ7 S_LOCK# AK20 

S_AD08 AJ17 S_AD45 AK7 S_PAR AK19 

S_AD09 AK17 S_AD46 AM7 S_PAR64 AK12 

S_AD10 AM17 S_AD47 AH8 S_PERR# AH20 

S_AD11 AH18 S_AD48 AK8 S_REQ0# AL26 

S_AD12 AK18 S_AD49 AL8 S_REQ1# AH27 

S_AD13 AL18 S_AD50 AM8 S_REQ2# AK27 

S_AD14 AM18 S_AD51 AH9 S_REQ3# AH28 

S_AD15 AH19 S_AD52 AJ9 S_REQ4# AL28 

S_AD16 AH22 S_AD53 AK9 S_REQ5# AJ29 

S_AD17 AK22 S_AD54 AM9 S_REQ64# AK13 

S_AD18 AL22 S_AD55 AH10 S_RST# AK26 

S_AD19 AM22 S_AD56 AK10 S_SERR# AM19 

S_AD20 AH23 S_AD57 AL10 S_STOP# AL20 

S_AD21 AJ23 S_AD58 AM10 S_TRDY# AH21 

S_AD22 AK23 S_AD59 AH11 TCK C12 

S_AD23 AM23 S_AD60 AJ11 TDI A12 

S_AD24 AK24 S_AD61 AK11 TDO E11 

S_AD25 AL24 S_AD62 AM11 TMS B11 

S_AD26 AM24 S_AD63 AH12 TRST# C11 

S_AD27 AH25 S_C/BE0# AH17 V CC A17 

30 Data Sheet




V CC A29 V CC F2 V CC AL3 

V CC B2 V CC F3 V CC AL4 

V CC B3 V CC F4 V CC AL5 

V CC B4 V CC G30 V CC AL7 

V CC B5 V CC G31 V CC AL9 

V CC B6 V CC H2 V CC AL11 

V CC B8 V CC J31 V CC AL13 

V CC B10 V CC K2 V CC AL15 

V CC B12 V CC L31 V CC AL17 

V CC B14 V CC M2 V CC AL19 

V CC B16 V CC N31 V CC AL21 

V CC B17 V CC P2 V CC AL23 

V CC B18 V CC R31 V CC AL25 

V CC B20 V CC T2 V CC AL27 

V CC B22 V CC U31 V CC AL29 

V CC B24 V CC V2 V CC AL30 

V CC B26 V CC W31 V CC AL31 

V CC B28 V CC Y2 V CC AM4 

V CC B29 V CC AA31 V CC AM16 

V CC B30 V CC AB2 V CC5REF E20 

V CC B31 V CC AC31 V CCPLL1 C22 

V CC C2 V CC AD2 V CCPLL2 B15 

V CC C3 V CC AE31 V CCPLL3 D26 

V CC C5 V CC AF2 V SS A1 

V CC C16 V CC AG30 V SS A2 

V CC C29 V CC AG31 V SS A3 

V CC C30 V CC AH2 V SS A4 

V CC C31 V CC AH30 V SS A5 

V CC D2 V CC AH31 V SS A30 

V CC D12 V CC AJ1 V SS A31 

V CC D30 V CC AJ30 V SS A32 

V CC D31 V CC AJ31 V SS B1 

V CC D32 V CC AK2 V SS B21 

V CC E2 V CC AK3 V SS B32 

V CC E3 V CC AK30 V SS C1 

V CC E10 V CC AK31 V SS C4 

V CC E31 V CC AL2 V SS C17 

Data Sheet 31




V SS C32 V SS F32 V SS AJ6 

V SS D1 V SS G4 V SS AJ8 



V SS D5 V SS H29 V SS AJ14 

V SS D7 V SS J4 V SS AJ16 

V SS D9 V SS K29 V SS AJ18 

V SS D11 V SS L4 V SS AJ20 

V SS D13 V SS M29 V SS AJ22 

V SS D15 V SS N4 V SS AJ24 

V SS D16 V SS P29 V SS AJ26 

V SS D17 V SS R4 V SS AJ28 

V SS D19 V SS T29 V SS AJ32 

V SS D21 V SS U4 V SS AK1 

V SS D23 V SS V29 V SS AK4 

V SS D25 V SS W4 V SS AK16 

V SS D27 V SS Y29 V SS AK32 

V SS D28 V SS AA4 V SS AL1 

V SS D29 V SS AB29 V SS AL32 

V SS E1 V SS AC4 V SS AM1 

V SS E4 V SS AD29 V SS AM2 

V SS E16 V SS AE4 V SS AM3 

V SS E28 V SS AF29 V SS AM29 

V SS E29 V SS AG4 V SS AM30 



V SS F1 V SS AG29 XINT0# B9 

V SS F5 V SS AH5 XINT1# C9 

V SS F28 V SS AH16 XINT2# E9 

V SS F29 V SS AH29 XINT3# A10 

V SS F30 V SS AJ3 XINT4# C10 

V SS F31 V SS AJ4 XINT5# D10 

32 Data Sheet


Table 11. 540-Lead H-PBGA Pinout — Ballpad Number Order (Sheet 1 of 5) 

Ball # Signal Ball # Signal Ball # Signal 

A1 V SS B6 V CC C11 TRST# 

A2 V SS B7 P_RST# C12 TCK 

A3 V SS B8 V CC C13 RAD02 

A4 V SS B9 XINT0# C14 RAD05 

A5 V SS B10 V CC C15 RAD09 

A6 P_AD29 B11 TMS C16 V CC 

A7 P_GNT# B12 V CC C17 V SS 

A8 SCL B13 RAD01 C18 RAD13 

A9 NMI# B14 V CC C19 RCE0# 

A10 XINT3# B15 V CCPLL2 C20 P_CLK 

A11 I_RST# B16 V CC C21 ONCE# 

A12 TDI B17 V CC C22 V CCPLL1 

A13 RAD00 B18 V CC C23 DQ02 

A14 RAD04 B19 RALE C24 DQ35 

A15 RAD08 B20 V CC C25 DQ06 

A16 N/C B21 V SS C26 DQ39 

A17 V CC B22 V CC C27 DQ41 

A18 RAD12 B23 DQ33 C28 DQ11 

A19 RAD16 B24 V CC C29 V CC 

A20 RWE# B25 DQ37 C30 V CC 

A21 LCDINIT# B26 V CC C31 V CC 

A22 DCLKOUT B27 DQ09 C32 V SS 

A23 DQ01 B28 V CC D1 V SS 

A24 DQ03 B29 V CC D2 V CC 



A27 DQ40 B32 V SS D5 V SS 

A28 DQ42 C1 V SS D6 P_AD31 

A29 V CC C2 V CC D7 V SS 

A30 V SS C3 V CC D8 P_INTB# 

A31 V SS C4 V SS D9 V SS 

A32 V SS C5 V CC D10 XINT5# 

B1 V SS C6 P_AD30 D11 V SS 

B2 V CC C7 P_INTD# D12 V CC 

B3 V CC C8 SDA D13 V SS 

B4 V CC C9 XINT1# D14 RAD06 

B5 V CC C10 XINT4# D15 V SS 

Data Sheet 33




D16 V SS E21 DCLKIN H28 DQ45 

D17 V SS E22 DQ32 H29 V SS 

D18 RAD14 E23 DQ34 H30 DQ13 

D19 V SS E24 DQ36 H31 DQ44 

D20 ROE# E25 DQ38 H32 DQ12 

D21 V SS E26 DQ08 J1 P_AD19 

D22 DQ00 E27 DQ10 J2 P_AD20 

D23 V SS E28 V SS J3 P_AD21 

D24 DQ04 E29 V SS J4 V SS 

D25 V SS E30 V SS J5 P_AD22 

D26 V CCPLL3 E31 V CC J28 DQ47 

D27 V SS E32 V SS J29 DQ15 

D28 V SS F1 V SS J30 DQ46 

D29 V SS F2 V CC J31 V CC 

D30 V CC F3 V CC J32 DQ14 

D31 V CC F4 V CC K1 P_C/BE2# 

D32 V CC F5 V SS K2 V CC 

E1 V SS F28 V SS K3 P_AD16 

E2 V CC F29 V SS K4 P_AD17 

E3 V CC F30 V SS K5 P_AD18 

E4 V SS F31 V SS K28 SCB5 

E5 P_AD28 F32 V SS K29 V SS 

E6 P_REQ# G1 P_AD25 K30 SCB1 

E7 P_INTC# G2 P_AD26 K31 SCB4 

E8 P_INTA# G3 P_AD27 K32 SCB0 

E9 XINT2# G4 V SS L1 P_DEVSEL# 

E10 V CC G5 N/C L2 P_TRDY# 

E11 TDO G28 V SS L3 P_IRDY# 

E12 FAIL# G29 V SS L4 V SS 

E13 RAD03 G30 V CC L5 P_FRAME# 

E14 RAD07 G31 V CC L28 SDQM4 

E15 RAD10 G32 DQ43 L29 SDQM0 

E16 V SS H1 P_AD23 L30 SCAS# 

E17 RAD11 H2 V CC L31 V CC 

E18 RAD15 H3 P_IDSEL L32 SWE# 

E19 RCE1# H4 P_C/BE3# M1 P_SERR# 

E20 V CC5REF H5 P_AD24 M2 V CC 

34 Data Sheet




M3 P_PERR# R32 SA07 W29 DQ16 

M4 P_LOCK# T1 P_AD03 W30 SCB7 

M5 P_STOP# T2 V CC W31 V CC 

M28 SCE1# T3 P_AD04 W32 SCB3 

M29 V SS T4 P_AD05 Y1 P_AD58 

M30 SCE0# T5 P_AD06 Y2 V CC 

M31 SDQM5 T28 SCKE0 Y3 P_AD59 

M32 SDQM1 T29 V SS Y4 P_AD60 

N1 P_AD14 T30 SBA1 Y5 P_AD61 

N2 P_AD15 T31 SBA0 Y28 DQ50 

N3 P_PAR T32 SA11 Y29 V SS 

N4 V SS U1 P_AD00 Y30 DQ18 

N5 P_C/BE1# U2 P_AD01 Y31 DQ49 

N28 SA02 U3 P_AD02 Y32 DQ17 

N29 SA01 U4 V SS AA1 P_AD54 

N30 SA00 U5 P_REQ64# AA2 P_AD55 

N31 V CC U28 SDQM3 AA3 P_AD56 

N32 SRAS# U29 SDQM6 AA4 V SS 

P1 P_AD10 U30 SDQM2 AA5 P_AD57 

P2 V CC U31 V CC AA28 DQ52 

P3 P_AD11 U32 SCKE1 AA29 DQ20 

P4 P_AD12 V1 P_C/BE5# AA30 DQ51 

P5 P_AD13 V2 V CC AA31 V CC 

P28 SA06 V3 P_C/BE6# AA32 DQ19 

P29 V SS V4 P_C/BE7# AB1 P_AD50 

P30 SA05 V5 P_ACK64# AB2 V CC 

P31 SA04 V28 N/C AB3 P_AD51 

P32 SA03 V29 V SS AB4 P_AD52 

R1 P_AD07 V30 SCB6 AB5 P_AD53 

R2 P_C/BE0# V31 SCB2 AB28 DQ54 

R3 P_AD08 V32 SDQM7 AB29 V SS 

R4 V SS W1 P_AD62 AB30 DQ22 

R5 P_AD09 W2 P_AD63 AB31 DQ53 

R28 SA10 W3 P_PAR64 AB32 DQ21 

R29 SA09 W4 V SS AC1 P_AD46 

R30 SA08 W5 P_C/BE4# AC2 P_AD47 

R31 V CC W28 DQ48 AC3 P_AD48 

Data Sheet 35




AC4 V SS AG1 N/C AH28 S_REQ3# 

AC5 P_AD49 AG2 P_AD32 AH29 V SS 

AC28 DQ56 AG3 P_AD33 AH30 V CC 

AC29 DQ24 AG4 V SS AH31 V CC 

AC30 DQ55 AG5 V SS AH32 DQ63 

AC31 V CC AG28 V SS AJ1 V CC 

AC32 DQ23 AG29 V SS AJ2 S_AD35 

AD1 P_AD42 AG30 V CC AJ3 V SS 

AD2 V CC AG31 V CC AJ4 V SS 

AD3 P_AD43 AG32 DQ31 AJ5 S_AD36 

AD4 P_AD44 AH1 S_AD32 AJ6 V SS 

AD5 P_AD45 AH2 V CC AJ7 S_AD44 

AD28 DQ58 AH3 S_AD33 AJ8 V SS 

AD29 V SS AH4 S_AD34 AJ9 S_AD52 

AD30 DQ26 AH5 V SS AJ10 V SS 

AD31 DQ57 AH6 S_AD39 AJ11 S_AD60 

AD32 DQ25 AH7 S_AD43 AJ12 V SS 

AE1 P_AD38 AH8 S_AD47 AJ13 S_C/BE7# 

AE2 P_AD39 AH9 S_AD51 AJ14 V SS 

AE3 P_AD40 AH10 S_AD55 AJ15 S_AD05 

AE4 V SS AH11 S_AD59 AJ16 V SS 

AE5 P_AD41 AH12 S_AD63 AJ17 S_AD08 

AE28 DQ60 AH13 S_C/BE6# AJ18 V SS 

AE29 DQ28 AH14 S_AD00 AJ19 S_C/BE1# 

AE30 DQ59 AH15 S_AD04 AJ20 V SS 

AE31 V CC AH16 V SS AJ21 S_IRDY# 

AE32 DQ27 AH17 S_C/BE0# AJ22 V SS 

AF1 P_AD34 AH18 S_AD11 AJ23 S_AD21 

AF2 V CC AH19 S_AD15 AJ24 V SS 

AF3 P_AD35 AH20 S_PERR# AJ25 S_AD28 

AF4 P_AD36 AH21 S_TRDY# AJ26 V SS 

AF5 P_AD37 AH22 S_AD16 AJ27 S_GNT1# 

AF28 DQ62 AH23 S_AD20 AJ28 V SS 

AF29 V SS AH24 S_C/BE3# AJ29 S_REQ5# 

AF30 DQ30 AH25 S_AD27 AJ30 V CC 

AF31 DQ61 AH26 S_AD31 AJ31 V CC 

AF32 DQ29 AH27 S_REQ1# AJ32 V SS 

36 Data Sheet




AK1 V SS AL1 V SS AM1 V SS 

AK2 V CC AL2 V CC AM2 V SS 


AK4 V SS AL4 V CC AM4 V CC 

AK5 S_AD37 AL5 V CC AM5 S_AD38 

AK6 S_AD40 AL6 S_AD41 AM6 S_AD42 






AK12 S_PAR64 AL12 S_C/BE4# AM12 S_C/BE5# 

AK13 S_REQ64# AL13 V CC AM13 S_ACK64# 



AK16 V SS AL16 N/C AM16 V CC 



AK19 S_PAR AL19 V CC AM19 S_SERR# 

AK20 S_LOCK# AL20 S_STOP# AM20 S_DEVSEL# 

AK21 S_FRAME# AL21 V CC AM21 S_C/BE2# 





AK26 S_RST# AL26 S_REQ0# AM26 S_GNT0# 

AK27 S_REQ2# AL27 V CC AM27 S_GNT2# 

AK28 S_GNT3# AL28 S_REQ4# AM28 S_GNT4# 

AK29 S_GNT5# AL29 V CC AM29 V SS 



AK32 V SS AL32 V SS AM32 V SS 

Data Sheet 37


3.2 Package Thermal Specifications 

The device is specified for operation when T C (case temperature) is within the range of 0°C to 

85°C, depending on operating conditions. Refer to the “Thermal Data for the 540-lead PBGA 

package” application note for more information regarding maximum case temperatures on the 

540-lead PBGA package. Case temperature may be measured in any environment to determine 

whether the processor is within specified operating range. Measure the case temperature at the 

center of the top surface, opposite the ballpad. 

3.2.1 Thermal Specifications 

This section defines the terms used for thermal analysis. 

3.2.1.1 Ambient Temperature 

Ambient temperature, T A , is the temperature of the ambient air surrounding the package. In a 

system environment, ambient temperature is the temperature of the air upstream from the package. 

3.2.1.2 Case Temperature 

To ensure functionality and reliability, the device is specified for proper operation when the case 

temperature, T C , is within the specified range as indicated in Table 12 “540-Lead H-PBGA 

Package Thermal Characteristics” on page 39. 

When measuring case temperature, attention to detail is required to ensure accuracy. If a 

thermocouple is used, calibrate it before taking measurements. Errors may result when the 

measured surface temperature is affected by the surrounding ambient air temperature. Such errors 

may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by 

radiation, or conduction through thermocouple leads. 

To minimize measurement errors: 

• Use a 35 gauge K-type thermocouple or equivalent. 

• Attach the thermocouple bead or junction to the package top surface at a location 

corresponding to the center of the die (Figure 5A). The center of the die gives a more accurate 

measurement and less variation as the boundary condition changes. 

• Attach the thermocouple bead at a 0° angle with respect to the package as shown in Figure 5A, 

when no heatsink is attached. 

• When a passive heat sink is attached, a groove is made on the bottom surface of the heatsink 

and the thermocouple is attached at a 0° angle, as shown in Figure 5B. 

Figure 5. 

Thermocouple Attachment - A) No Heatsink / B) With Heatsink 

80960RN 

Bottom of 

Processor 

Thermocouple 

Heatsink 

Groove for 

thermocouple 

A) No Heatsink B) With Heatsink 

38 Data Sheet


3.2.1.3 Thermal Resistance 

The thermal resistance value for the case-to-ambient, θ CA , is used as a measure of the cooling 

solution’s thermal performance. 

3.2.2 Thermal Analysis 

Table 12 lists the case-to-ambient thermal resistances of the 80960RN for different air flow rates 

with and without a heat sink. 

To calculate T A , the maximum ambient temperature to conform to a particular case temperature: 

T A =T C -P(θ CA ) 

Compute P by multiplying I CC and V CC .Valuesforθ JC and θ CA are given in Table 12. 

Junction temperature (T J ) is commonly used in reliability calculations. T J can be calculated from 

θ JC (thermal resistance from junction to case) using the following equation: 

T J =T C +P(θ JC ) 

Similarly, when T A is known, the corresponding case temperature (T C ) can be calculated as 

follows: 

T C =T A +P(θ CA ) 

The θ JA (Junction to Ambient) for this package is currently estimated at 13.10° C/Watt with no 

airflow and no heatsink. The θ JA (Junction to Ambient) for this package is currently estimated at 

8.30° C/Watt with no airflow and a passive heatsink: 

θ JA = θ JC + θ CA 

Table 12. 

540-Lead H-PBGA Package Thermal Characteristics 

Thermal Resistance — °C/Watt 

Airflow — ft./min (m/sec) 

Parameter 

0 

(0) 

50 

(0.25) 

100 

(0.50) 

200 

(1.01) 

300 

(1.52) 

400 

(2.03) 

600 

(3.04) 

800 

(4.06) 

θ JC (Junction-to-Case) 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 

θ CA (Case-to-Ambient) 

Without Heatsink 

12.66 11.61 10.66 9.26 8.26 7.61 6.57 5.78 


With Passive 0.25 in. 9.0 8.2 7.5 6.1 5.1 4.7 3.8 3.2 

Heatsink 2,3 


With Passive 0.35 in. 7.86 6.96 6.06 4.56 3.66 3.16 2.56 2.16 

Heatsink 2 

θ JA 

θ JC 

θ CA 

Data Sheet 39


3.3 Heat Sink Information 

Under normal circumstances, a heat sink is not required for the 80960RN. 

Table 13 provides a list of suggested sources for heat sinks. This is neither an endorsement nor a 

warranty of the performance of any of the listed products and/or companies. 

Table 13. 

Heat Sink Vendors and Contacts 

Company 

Factory 

Representative 

Phone # Fax # 

Heatsink Part # 

Passive 

AAVID Thermalloy, Inc 

80 Commercial Street 

Concord, NH 03301 USA 

info@aavid.com 

http://www.aavidthermalloy.com/atp/atp.html 

Attention: Sales (603) 224-9988 (603) 223-1790 21933B withoou thermal 

grease (uses pins) 

21935B withoou thermal 

grease (uses pins) 

3.4 Vendor Information 

Table 14 through Table 18 provide vendor details for socket-headers, burn-in sockets, shipping 

trays, logic analyzer interposers and JTAG emulators for the Intel ® 80960RN. This is neither an 

endorsement nor a warranty of the performance of any of the listed products and/or companies. 

3.4.1 Socket-Header Vendor 

Table 14. 

Socket-Header Vendor 

Company 

Adapter Technologies, Inc. 

214-218 South 4th St. 

Perkasie, PA 18944 

Factory 

Representative 

Phone/Fax # 

John Miller 215-258-5750/ 

215-258-5760 

Part # 

BGA 540 Pin Header BGA 540 Pin Socket Carrier 

BGAH-540-0-01-3201-0277-1 BGA-540-0-02-3201-0275P-130 

3.4.2 Burn-in Socket Vendor 

Table 15. 

Burn-in Socket Vendor 

Company Factory Representative Phone # Burn-in Socket Part # 

Texas Instruments 

111 Forbes Blvd. 

Mansfield, MA 02048 

W. Ray Johnson 508-236-5375 ULGA540-005 

40 Data Sheet


3.4.3 Shipping Tray Vendor 

Table 16. 

Shipping Tray Vendor 

Company Factory Representative Phone # Shipping Tray Part # 

3M Ron Goth 602-465-5381 7-0000-21001-184-167 

3.4.4 Logic Analyzer Interposer Vendor 

Table 17. 

Logic Analyzer Interposer Vendor 

Company Factory Representative Phone/Fax # Part # 

Packard-Hughes Interconnect 

17150 Von Karman Ave 

Irvine, CA 92614-0968 

Karen May 949-660-5773 

949-660-5825 

1126898 

3.4.5 JTAG Emulator Vendor 

3.5 

Table 18. 

JTAG Emulator Vendor 

Company 

Factory Representative 

Phone/ 

Fax # 

Part # 

Spectrum Digital, Inc. 

Jeff Bond 

281-494-4500/ 

281-494-5310 

701500 

Data Sheet 41


4.0 Electrical Specifications 

4.1 Absolute Maximum Ratings 

Parameter 

Storage Temperature 

Case Temperature Under Bias 

Supply Voltage wrt. V SS 

Supply Voltage wrt. V SS on V CC5 

VoltageonAnyBallwrt.V SS 

Maximum Rating 

–55°C to+125°C 

0°C to+85°C 

–0.5 V to + 4.6 V 

–0.5 V to + 6.5 V 

–0.5 V to V CC +0.5V 

NOTICE: This data sheet contains information on 

products in the design phase of development. Do 

not finalize a design with this information. Revised 

information will be published when the product 

becomes available. The specifications are subject 

to change without notice. Contact your local Intel 

representative before finalizing a design. 

†WARNING: Stressing the device beyond the 

“Absolute Maximum Ratings” may cause 

permanent damage. These are stress ratings only. 

Operation beyond the “Operating Conditions” is 

not recommended and extended exposure beyond 

the “Operating Conditions” may affect device 

reliability. 

Table 19. 

Operating Conditions 

Symbol Parameter Min Max Units Notes 

V CC Supply Voltage 3.0 3.6 V 

V CC5 Input Protection Bias V CC V CC +2.5 V 

F P_CLK Input Clock Frequency 16 33.33 MHz 

T C 

Case Temperature Under Bias 

GC (540L PBGA) 0 85 °C 

42 Data Sheet


4.2 V CC5REF Pin Requirements (V DIFF ) 

In mixed voltage systems that drive 80960RN processor inputs in excess of 3.3 V, the V CC5REF pin 

must be connected to the system’s 5 V supply. To limit current flow into the V CC5REF pin, there is 

a limit to the voltage differential between the V CC5REF pin and the other V CC pins. The voltage 

differential between the V CC5REF pin and its 3.3 V V CC pins should never exceed 2.25 V. This 

limit applies to power-up, power-down, and steady-state operation. Table 20 outlines this 

requirement. 

If the voltage difference requirements cannot be met due to system design limitations, an alternate 

solution may be employed. As shown in Figure 6, a minimum of 100 Ω series resistor may be used 

to limit the current into the V CC5REF pin. This resistor ensures that current drawn by the V CC5REF 

pin does not exceed the maximum rating for this pin. 

Figure 6. 

V CC5REF Current-Limiting Resistor 

+5 V (±0.25 V) VCC5REF Pin 

100 Ω 

(±5%, 0.5 W) 

This resistor is not necessary in systems that can guarantee the V DIFF specification. 

In 3.3 V-only systems (only applies to 80960RN C-x steppings) and systems that drive pins from 

3.3 V logic, connect the V CC5REF pindirectlytothe3.3VV CC plane. 

Table 20. V DIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) 


V DIFF V CC5 -V CC Difference 2.25 V (1) 

NOTE: 

1. V CC5REF input should not exceed V CC by more than 2.25 V during power-up and power-down, or during 

steady-state operation. 

4.3 V CCPLL Pin Requirements 

To reduce clock skew on the i960 Jx processor, the V CCPLL pin for the Phase Lock Loop (PLL) 

circuit is isolated on the pinout. The lowpass filter, as shown in Figure 7, reduces noise induced 

clock jitter and its effects on timing relationships in system designs. The trace lengths between the 

4.7 µF capacitor, the 0.01 µF capacitor, and V CCPLL must be as short as possible. 

Figure 7. 

V CCPLL Lowpass Filter 

10Ω, 5%, 1/8W 

V CC 

(Board Plane) 

+ 

4.7µF 

0.01µF 

V CCPLL 

(On i960 ® Jx processors) 

Data Sheet 43


4.4 Targeted DC Specifications 

Table 21. 

DC Characteristics 


V IL5 Input Low Voltage 5 Volt PCI -0.5 0.8 V (1,4) 

V IH5 Input High Voltage 5 Volt PCI 2 V CC +0.5 V (1,4) 

V IL3.3 Input Low Voltage 3.3 Volt PCI -0.5 0.3V CC V (1,4,5) 

V IH3.3 Input High Voltage 3.3 Volt PCI 0.5V CC V CC + 0.5 V (1,4,5) 

V OL1 Output Low Voltage Processor signals 0.4 V I OL =6mA(3) 

V OH1 

Output High Voltage Processor signals 

2.4 

V CC -0.5 

V 

I OH =-2mA(3) 

I OH =-200µA (3, 6) 

V OL2 

Output Low Voltage 5 V PCI / Flash 

signals 

0.4 V I OL =6mA(1) 

V OH2 

Output High Voltage 5 V PCI / Flash 

signals 

2.4 V I OH =-2mA(1) 

V OL3 Output Low Voltage SDRAM signals -2.0 0.4 V I OL =3mA(4) 

V OH3 Output High Voltage SDRAM signals 2.4 V CC +2.0 V I OH =-2mA(4) 

V OL4 Output Low Voltage 3.3 V PCI signals 0.1V CC V I OL =1500µA (1,5) 

V OH4 Output Low Voltage 3.3 V PCI signals 0.9V CC V I OH =-500µA (1,5) 

C IN Input Capacitance - PBGA 10 pF F S_CLK =T F Min (1, 2) 

C OUT I/O or Output Capacitance - PBGA 10 pF F S_CLK =T F Min (1, 2) 

C CLK S_CLK Capacitance - PBGA 5 10 pF F S_CLK =T F Min (1, 2) 

C IDSEL IDSEL Ball Capacitance 8 pF (1,2) 

L PIN Ball Inductance 25 nH (1,2) 

NOTES: 

1. As required by the PCI Local Bus Specification, Revision 2.2. 

2. Not tested. 

3. Processor signals include RALE, RCE[1:0]#, ROE#, RWE#, XINT[5:4]#, NMI#, FAIL#, TDI, TDO, TMS, 

TRST#, SDA, andSCL. 

4. SDRAM signals include SA[11:0], SBA[1:0], SCAS#, SCE[1:0]#, SCKE[1:0], SDQM[7:0], SRAS#, 

SWE#, DCLKIN, DCLKOUT, DQ[63:0], andSCB[7:0]. 

5. 3.3 V PCI signalling only supported on C-x steppings on the 80960RN processor 

6. Guaranteed by characterization 

44 Data Sheet


Table 22. 

I CC Characteristics 

Symbol Parameter Typ Max Units Notes 

I LI1 

I LI2 

Input Leakage Current for each signal except 

TMS, TRST#, TDI, ONCE#, RAD[8:0] and 

LCDINIT#. 

Input Leakage Current for TMS, TRST#, TDI, 

ONCE#, RAD[8:0] and LCDINIT#. 

±5 µA 0 ≤ V IN ≤ V CC 

-140 -250 µA V IN =0.45V(1) 

I LO Output Leakage Current ± 5 µA 0.4 ≤ V OUT ≤ V CC 

I CC Active 

(Power 

Supply) 

I CC Active 

(Thermal) 

Power Supply Current 1.65 A (1,2) 

Thermal Current 1.2 A (1,3) 

I CC Active 

(Power 

Modes) 

Reset Mode 

ONCE Mode 

0.95 

0.02 

A 

(4) 

(4) 

NOTES: 

1. Measured with device operating and outputs loaded to the test condition in Figure 13. 

2. I CC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using 

one of the worst case instruction mixes with V CC = 3.6 V and ambient temperature = 55°C. 

3. I CC Active (Thermal) value is provided for your system’s thermal management. Typical I CC is measured 

with V CC = 3.3 V and ambient temperature = 55°C. 

4. I CC Test (Power modes) refers to the I CC values that are tested when the device is in Reset mode or ONCE 

mode with V CC = 3.6 V and ambient temperature = 55°C. 

Data Sheet 45


4.5 Targeted AC Specifications 

4.5.1 Clock Signal Timings 

Table 23. 

Input Clock Timings 


T F P_CLK Frequency 16 33.33 MHz 

T C P_CLK Period 30 62.5 ns (1) 

T CS P_CLK Period Stability ±250 ps Adjacent Clocks (2) 

TCH P_CLK High Time 12 ns Measured at 1.5 V (2) 

T CL P_CLK Low Time 12 ns Measured at 1.5 V (2) 

T CR P_CLK Rise Time 1 4 V/ns 0.4 V to 2.4 V (2) 

T CF P_CLK Fall Time 1 4 V/ns 2.4 V to 0.4 V (2) 

T DICS DCLKIN Period Stability ±250 ps Adjacent Clocks (2) 

T DICH DCLKIN High Time 5 ns Measured at 1.5 V (2) 

T DICL DCLKIN Low Time 5 ns Measured at 1.5 V (2) 

NOTES: 

1. See Figure 8 “P_CLK, TCK, DCLKIN, DCLKOUT Waveform” on page 51. 


Table 24. 

SDRAM Output Clock Timings 


T DOF DCLKOUT Frequency 2T F MHz 

T DOC DCLKOUT Period T C /2 ns (1) 

T DOCS DCLKOUT Period Stability ±250 ps Adjacent Clocks 

TDOCH DCLKOUT High Time 5 ns Measured at 1.5 V 

T DOCL DCLKOUT Low Time 5 ns Measured at 1.5 V 

NOTE: 

1. See Figure 8 “P_CLK, TCK, DCLKIN, DCLKOUT Waveform” on page 51. 

46 Data Sheet


4.5.2 PCI Interface Signal Timings 

Table 25. 

PCI Signal Timings 


T OV1 

Output Valid Delay from P_CLK - PCI Signals Except 2 11 ns 

P_REQ#, P_INT[A:D]#, andS_GNT[5:0]# 

(1,2) 

T OV2 Output Valid Delay from P_CLK - P_INT[A:D]# 0 25 ns (1,2,6) 

T OV3 Output Valid Delay from P_CLK - S_REQ64# 0 ns (1,2,8) 

T OV4 

Output Valid Delay from P_CLK - P_REQ# and 

2 12 ns 

S_GNT[5:0]# 

(1,2) 

T OF Output Float Delay from P_CLK 28 ns (1,4,5,6) 

T IS1 

Input Setup to P_CLK - PCI Signals Except P_GNT# and 7 ns 

S_REQ[5:0]# 

(1,3) 

T IS2 Input Setup to P_CLK - P_GNT# 10 ns (1,3) 

T IS3 Input Setup to P_CLK - S_REQ[5:0]# 12 ns (1,3) 

T IH1 Input Hold from P_CLK - PCI Signals 0 ns (1,3) 

T IS4 Input Setup to P_CLK - S_INT[A:D]# 25 ns (1,3,7,9) 

T IH2 Input Hold to P_CLK - S_INT[A:D]# 2 ns (1,3,7,9) 

T IS5 Input Setup to P_CLK - P_RST# 6 ns (1,3,7) 

T IH3 Input Hold to P_CLK - P_RST# 2 ns (1,3,7) 

T IS6 Input Setup to P_RST# - P_REQ64# 10T c ns (1,3) 

T IH4 Input Hold to P_RST# - P_REQ64# 0 50 ns (1,3) 

NOTES: 

1. The PCI Local Bus Specification, Revision 2.2 requires that all of the PCI signal AC timings use 0 pF for 

minimum timings and 50 pF for maximum timings. 

2. See Figure 9 “T OV Output Delay Waveform” on page 51. 

3. See Figure 11 “T IS and T IH Input Setup and Hold Waveform” on page 52. 

4. A float condition occurs when the output current becomes less than I LO . Float delay is not tested. See 

Figure 10 “T OF Output Float Waveform” on page 52. 

5. See Figure 10 “T OF Output Float Waveform” on page 52. 

6. Outputs precharged to V CC5 . 

7. P_RST#, S_INT[A:D]# may be synchronous or asynchronous. Meeting setup and hold time guarantees 

recognition at a particular clock edge. 

8. S_REQ64# is asserted asynchronously with respect to P_RST#. S_REQ64# is deasserted one P_CLK 

after the deassertion of S_RST#. 

9. S_INT[A:D]# must be asserted for a minimum of two P_CLK periods to guarantee recognition. 

Data Sheet 47


4.5.3 Intel ® 80960JN Core Interface Timings 

Table 26. 

Intel ® 80960JN Core Signal Timings 


T OV5 Output Valid Delay from P_CLK - FAIL# 2 TBD ns (1,5) 

T IS7 Input Setup to P_CLK - NMI#, XINT[5:4]# 25 ns (2,3) 

T IH5 Input Hold from P_CLK - NMI#, XINT[5:4]# 2 ns (2,3) 

NOTES: 



3. Setup and hold times must be met for proper processor operation. NMI# and XINT[5:4]# may be 

synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock 

edge. For asynchronous operation, NMI# and XINT[5:4]# must be asserted for a minimum of two P_CLK 

periods to guarantee recognition. 

4. Core signals include: XINT[5:4]#, NMI#, FAIL# . 

5. The processor asserts FAIL# during built-in self-test. If self-test passes, FAIL# is deasserted. The 

processor asserts FAIL# during the bus confidence test. If the test passes, FAIL# is deasserted and user 

program execution begins. 

4.5.4 SDRAM/Flash Interface Signal Timings 

Table 27. 

SDRAM / Flash Signal Timings 

Sym Parameter Min Max Units Notes 

T OV6 

Output Valid Delay from DCLKIN - SA[11:0], SBA[1:0], SCAS#, 1.62 6.60 ns 

SRAS#, and SWE#. 

(1,5) 

T OV7 Output Valid Delay from DCLKIN - DQ[63:0], andSCB[7:0]. 2.03 7.14 ns (1,5) 

T OV8 Output Valid Delay from DCLKIN - SDQM[7:0] 2.57 6.85 ns (1,5) 

T OV9 Output Valid Delay from DCLKIN - SCKE[1:0] 1.74 5.50 ns (1,5) 

T OV10 Output Valid Delay from DCLKIN - SCE[1:0]# 1.65 5.25 ns (1,5) 

T IS8 Input Setup to DCLKIN - DQ[63:0], andSCB[7:0] 3.00 ns (2) 

T IH6 Input Hold from DCLKIN - DQ[63:0], and SCB[7:0] 1.5 ns (2) 

T OV11 

Output Valid Delay from DCLKIN - RAD[16:0], RALE, RCE[1:0]#, 1.4 11.0 ns 

ROE#, andRWE#. 

(1,5) 

T IS9 Input Setup to DCLKIN -RAD[16:0] 5 ns (2) 

T IH7 Input Hold from DCLKIN - RAD[16:0] 1.4 ns (2) 

NOTES: 



3. SDRAM signals include SA[11:0], SBA[1:0], SCAS#, SCE[1:0]#, SCKE[1:0], SDQM[7:0], SRAS#, 

SWE#, DQ[63:0], andSCB[7:0]. Timings are for 3.3 V signalling environment. 

4. Flash signals include RAD[16:0], RALE, RCE[1:0]#, ROE#, andRWE#. Timings are for 5V signalling 

environment. 

5.Theseoutputvalidtimesarespecifiedwitha0pFloading. 

48 Data Sheet


4.5.5 Boundary Scan Test Signal Timings 

Table 28. 

Boundary Scan Test Signal Timings 


T BSF TCK Frequency 0 0.5T F MHz 

T BSCH TCK High Time 15 ns Measured at 1.5 V (1) 

T BSCL TCK Low Time 15 ns Measured at 1.5 V (1) 

T BSCR TCK Rise Time 5 ns 0.8 V to 2.0 V (1) 

T BSCF TCK Fall Time 5 ns 2.0 V to 0.8 V (1) 

T BSIS1 Input Setup to TCK — TDI, TMS 4 ns (4) 

T BSIH1 

Input Hold from TCK — TDI, 

TMS 

6 ns (4) 

T BSIS2 Input Setup to TCK — TRST# 25 ns (4) 

T BSIH2 Input Hold from TCK — TRST# 3 ns (4) 

T BSOV1 TDO Valid Delay 3 30 ns Relative to falling edge of TCK (2,3) 

T OF1 TDO Float Delay 3 30 ns Relative to falling edge of TCK (2,5) 

T OV12 

All Outputs (Non-Test) Valid 

Delay 

3 30 ns Relative to falling edge of TCK (2,3) 

T OF2 

T IS10 

T IH8 

All Outputs (Non-Test) Float 

Delay 

Input Setup to TCK — All Inputs 

(Non-Test) 

Input Hold from TCK — All Inputs 

(Non-Test) 

3 30 ns Relative to falling edge of TCK (2,5) 

4 ns (4) 

6 ns (4) 

NOTES: 


2. Outputs precharged to V CC5 . 

3. See Figure9“T OV Output Delay Waveform” on page 51. 


5. A float condition occurs when the output current becomes less than I LO . Float delay is not tested. See 

Figure 10 “T OF Output Float Waveform” on page 52. 

Data Sheet 49


4.5.6 I 2 C Interface Signal Timings 

Table 29. 

I 2 C Interface Signal Timings 

Symbol 

Parameter 

Std. Mode 

Fast Mode 

Min Max Min Max 

Units 

Notes 

F SCL SCL Clock Frequency 0 100 0 400 KHz 

T BUF 

BusFreeTimeBetweenSTOPandSTART 

Condition 

4.7 1.3 µs (1) 

T HDSTA Hold Time (repeated) START Condition 4 0.6 µs (1,3) 

T LOW SCL Clock Low Time 4.7 1.3 µs (1,2) 

T HIGH SCL Clock High Time 4 0.6 µs (1,2) 

T SUSTA SetupTimeforaRepeatedSTARTCondition 4.7 0.6 µs (1) 

T HDDAT Data Hold Time 0 0 0.9 µs (1) 

T SUDAT Data Setup Time 250 100 ns (1) 

T SR SCL and SDA Rise Time 1000 20+0.1C b 300 ns (1,4) 

T SF SCL and SDA Fall Time 300 20+0.1C b 300 ns (1,4) 

T SUSTO Setup Time for STOP Condition 4 0.6 µs (1) 

NOTES: 

1. See Figure 12 “I 2 C Interface Signal Timings” on page 52. 


3. After this period, the first clock pulse is generated. 

4. C b = the total capacitance of one bus line, in pF. 

50 Data Sheet


4.6 AC Timing Waveforms 

Figure 8. 

P_CLK, TCK, DCLKIN, DCLKOUT Waveform 

T CR 

T CF 

2.0V 

1.5V 

0.8V 

T CH 

T CL 

T C 

Figure 9. 

T OV Output Delay Waveform 

P_CLK / DCLKIN 1.5V 

1.5V 

T OVX Max 

T OVX Min 

1.5V Valid 

1.5V 

Data Sheet 51


Figure 10. 

T OF Output Float Waveform 

P_CLK / DCLKIN 

1.5V 

1.5V 

T OF 

Figure 11. 

T IS and T IH Input Setup and Hold Waveform 

P_CLK / DCLKIN 

1.5V 

1.5V 

1.5V 

T IHX 

T ISX 

1.5V 

Valid 

Figure 12. 

I 2 C Interface Signal Timings 

SDA 

T BUF 

T LOW 

T SR 

T SF 

T HDSTA 

T SUSTO 

T HDSTA T SP 

Stop 

T HDDAT 

T HIGH 

T SUDAT T SUSTA 

Repeated 

Stop 

Start 

Start 

SCL 

52 Data Sheet


4.7 AC Test Conditions 

The AC specifications in Section 4.5, “Targeted AC Specifications” on page 46 are tested with a 

50 pF load indicated in Figure 13. 

Figure 13. 

AC Test Load (all signals except SDRAM and Flash signals) 

Output Ball 

C L 

C L =50pF 

The PCI maximum AC specifications are tested with the 50 pF load indicated in Figure 13. The 

PCI minimum AC specifications are tested with a 0 pF load. All of the SDRAM and Flash timings 

are specified for a 0 pF load. 

Data Sheet 53


5.0 Device Identification on Reset 

During the manufacturing process, values characterizing the i960 RM/RN I/O processor type and 

stepping are programmed into memory-mapped registers. The i960 RM/RN I/O processor contains 

two, read-only device ID MMRs. One holds the Processor Device ID (PDIDR MMR Location - 

0000 1710H) and the other holds the i960 Core Processor Device ID (DEVICEID MMR Location - 

FF00 8710H). During initialization, the DEVICEID is placed in g0. 

The device identification values are compliant with the IEEE 1149.1 specification and Intel 

standards. Table 30 describes the fields of the two Device IDs. 

Table 30. 

Note: 

The value programmed into these registers varies with stepping. Refer to the Specification Update 

for the correct value. 

Device ID Registers 

IB 

ro 

31 

ro 

ro 

28 24 20 16 12 8 4 0 

ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 

PCI 

na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na 

IB: 

PCI: 

0000 1710H 

FF00 8710H 

NA 

Legend:NA = Not AccessibleRO = Read Only 

RV = ReservedPR = PreservedRW = Read/Write 

RS = Read/SetRC = Read Clear 

IB = Internal Bus AddressPCI = PCI Configuration Address Offset 

Bit Default Description 

31:28 X Version - Indicates stepping changes. 

27 X 

V CC - Indicates device voltage type. 

0=5.0V 

1=3.3V 

26:21 X Product Type - Indicates the generation or “family member”. 

20:17 X Generation Type - Indicates the generation of the device. 

16:12 X Model Type - Indicates member within a series and specific model information. 

11:01 X 

Manufacturer ID - Indicates manufacturer ID assigned by IEEE. 

0000 0001 001 = Intel Corporation 

0 1 Constant 

54 Data Sheet

IntelR 80960 RN I/O Processor Datasheet

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?