![INSTRUCTION SET SUMMARY 8051
-1-
CHAPTER 3
INSTRUCTION SET SUMMARY
Structure of Assembly Language
[label:] Mnemonic [operands] [;comment]
LOOP: MOV A,#01H ; Write 1 to Acc
MOV R7,A ;(R7) ο (A)
[PC] op code [operands] [ ]
8000H 74H 01H
8002H FFH
Figure 3.1 Structure of Assembly Language
Symbol Interpretation
ο Is replaced by β¦.
( ) The contents of β¦
(( )) The data pointed at by β¦.
rrr One of 8 register; 000 = R0, 001 = R1, 010=R2,..etc
dddddddd Data bits
aaaaaaaa Address bits (byte address)
bbbbbbbb Address of a bit (bit address)
i Indirect addressing using R0 or R1
eeeeeeee 8-bit relative address (or offset)
Assembler](https://image.slidesharecdn.com/instructionsetsummary-140513060723-phpapp02/85/instruction-set-summary-1-320.jpg)
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Instruction set summary
- 1. INSTRUCTION SET SUMMARY 8051 -1- CHAPTER 3 INSTRUCTION SET SUMMARY Structure of Assembly Language [label:] Mnemonic [operands] [;comment] LOOP: MOV A,#01H ; Write 1 to Acc MOV R7,A ;(R7) ο (A) [PC] op code [operands] [ ] 8000H 74H 01H 8002H FFH Figure 3.1 Structure of Assembly Language Symbol Interpretation ο Is replaced by β¦. ( ) The contents of β¦ (( )) The data pointed at by β¦. rrr One of 8 register; 000 = R0, 001 = R1, 010=R2,..etc dddddddd Data bits aaaaaaaa Address bits (byte address) bbbbbbbb Address of a bit (bit address) i Indirect addressing using R0 or R1 eeeeeeee 8-bit relative address (or offset) Assembler
- 2. INSTRUCTION SET SUMMARY 8051 -2- ADDRESSING MODES Eight types addressing modes β’ Register β’ Direct β’ Indirect β’ Immediate β’ Relative β’ Absolute β’ Long β’ Indexed Register Addressing The 8051 assembly language indicates register addressing with the symbol Rn where n is from 0 to 7. Opcode n Register Addressing Examples:- MOVRn,A ORL A,Rn Bytes: 1 Bytes: 1 Cycle: 1 Cycle: 1 Encoding: 11111rrr Encoding: 01001rrr Operation: (Rn) ο (A) Operation: (A) ο (A) OR (Rn) Example: MOV R3,A Example: ORL A,R5 Encoding: 11111011 or FBH Encoding: 01001101 or 4DH
- 3. INSTRUCTION SET SUMMARY 8051 -3- For instruction using register addressing, either the source or destination operand contains a register. Example MOVA,R7 Bytes : 1 Cycles : 1 Encoding : 11101rrr Operation : (A) ο (Rn) EFH. This instruction moves the 8-bit content of register 7 to the accumulator. There are 4 βbanksβ of working register β, address 00 ο 1FH, but only one is active at a time. For Example:- MOV PSW,#00011000B PSW BIT 7 BIT 0 Carry Aux. C Flag0 R.Bank 1 R. Bank 0 Overflow Reserved Even. P CY AC F0 RS1 RS0 0V - P RS1 RS0 0 0 bank 0; addresses 00H - 07H 0 1 bank 1: addresses 08H - 0FH 1 0 bank 2: addresses 10H - 17H 1 1 bank 3: addresses 18H β 1FH Activates register bank 3 by setting the register bank select bits (RS1 and RS0) in PSW bit positions 4 and 3. Some instructions are specific to a certain register so address bits are not needed. The opcode itself indicates the register. For Example:- INC DPTR ;(DPTR) ο (DPTR) + 1
- 4. INSTRUCTION SET SUMMARY 8051 -4- Is a 1-byte instruction that adds 1 to the 16-bit data pointer. Example3-2 What is the opcode for the following instruction? What does it do? MUL AB Opcode = A4H Operation : (B) ο HIGHBYTE OF (A) x (B) (A) ο LOWBYTE OF (A) x (B) Direct Addressing Direct addressing can access any on-chip variable or hardware register. An additional byte is appended to the opcode specifying the location to be used. Only internal RAM and SFRs can be directly accessed. OPCODE Direct address Example:- MOV P1,A ; (direct) ο (A). Opcode = 11110101 Direct Address = aaaaaaaa Transfer the content of Acc to Port 1. Using Appendix C as a reference the complete encoding of this instruction is 11110101 β 1st byte (opcode) 10010000 β 2nd byte (address of P1)
- 5. INSTRUCTION SET SUMMARY 8051 -5- Examples:- MOV direct,A DEC direct Bytes: 2 Bytes: 2 Cycle: 1 Cycle: 1 Encoding: 11110101 aaaaaaaa Encoding: 00010101 aaaaaaaa Operation: (direct) ο (A) Operation: (direct) ο (direct) - 1 Example: MOV 20H,A Example: DEC B ; B is at 0F0H Encoding: F5H 20H Encoding: 15H F0H Moving data MOV R5,A ; (R5) ο (A) MOV A,R0 ; (A) ο (R0) Logical operations ANL A,R5 ; (A) ο (A) AND (R5) XRL R5,A ; (R5) ο (R5) exOR (A) Arithmetic Operation ADD A,R3 ; (A) ο (A) + (R3) ADDC A,R3 ; (A) ο (A) + (R3) + C
- 6. INSTRUCTION SET SUMMARY 8051 -6- Indirect Addressing The instruction specifies a register which contains the address of the operand. Opcode i Examples:- MOVX @Ri,A ADD A,@Ri Bytes: 1 Bytes: 1 Cycle: 2 Cycle: 1 Encoding: 1111001i Encoding: 0010011i Operation: ((Rn)) ο (A) Operation: (A) ο (A) OR ((Ri)) Example: MOVX @R0,A Example: ADD A,@R1 Encoding: F2H Encoding: 27H Example:- MOV A,@R0 The Source is the memory location pointed by R0, the contents of which are copied into the Accumulator which is the destination register. MOV @R1,A The Accumulator is the source and its contents are copied into the destination which is the memory location pointed by R1. Example:- (a) What is the opcode for the following instruction? (b) What does this instruction do? MOV A,@R0
- 7. INSTRUCTION SET SUMMARY 8051 -7- Solution (a) E6H (b) The instruction moves a byte of data from internal RAM to the Accumulator. The data are moved from the location whose address is in R0. Examples:- MOVX A,@DPTR MOVX @DPTR,A Bytes: 1 Bytes: 1 Cycle: 2 Cycle: 2 Encoding: 1110000 Encoding: 11110000 Operation: (A) ο ((DPTR)) Operation: ((DPTR)) ο (A) Example:- Moving data MOV @R1,A ((R1)) ο (A) MOV A,@R1 (A) ο ((R0)) Logical Operation ORL A,@R0 (A) ο (A) OR ((R0)) XRL @R1,A ((R1)) ο ((R1)) exOR (A) Arithmetic Operation ADD A,@R0 (A) ο (A) + ((R0)) ADDC A,@R1 (A) ο (A) + ((R1)) + C Immediate Addressing The destination register is loaded with a constant value immediately. Opcode Immediate data
- 8. INSTRUCTION SET SUMMARY 8051 -8- Examples:- ANL A,#data MOV DPTR,#DATA16 Bytes: 2 Bytes: 3 Cycle: 1 Cycle: 2 Encoding: 01010100 dddddddd Encoding: 10010000 dddddddd dddddddd Operation: (A) ο (A) AND #data Operation: (DPTR) ο #data16 Example: ANL A,#0F0H Example: MOV DPTR,#2800H Encoding: 54H F0H Encoding: 90H 28H 00H Example:- MOV A,#12 Loads the value of 12 into the Accumulator. Moving data MOV A,#F1H ; (A) ο F1H MOV R3,#C1H ; (R3) ο 1CH Arithmetic Operation ADD A,#10H ; (A)ο (A) + 10H ADDC A,#10H ; (A)ο (A) + 10H + C Logical operation ORL A,#33H ; (A)ο (A) OR 33H ANL A,88H ; (15H) ο (15H) AND 88H
- 9. INSTRUCTION SET SUMMARY 8051 -9- Relative Addressing Relative Addressing is used only with certain jump instruction. A relative address or offset is an 8-bit signed value, which is added to the program counter to form the address of the next instruction executed. Range -128 to +127 locations. Opcode Relative Offset Example :- SJMP THERE THERE: MOV A,R1 ADD A,@R0 : : SJMP THERE 010A 0109 0108 0107 Relative offset from Address 0102H is β5β 0101 05 SJMP 0100 80 0107H 00FF Code Memory SJMP is in memory location 0100H and Offset is in the memory location 0101H. Destination = PC + offset = 0102 + 5
- 10. INSTRUCTION SET SUMMARY 8051 -10- = 0107H Example:- The instruction SJMP 9030H is in the memory location 9000H and 9001H. What are the machine language bytes for this instruction? 80H, 2EH Destination = 9030H = PC + offset Therefore, offset = destination β PC = 9030H β 9002H = 2EH Example:- JZ rel JB bit,rel Bytes: 2 Bytes: 3 Cycle: 2 Cycle: 2 Encoding: 01100000 eeeeeeee Encoding: 00100000 bbbbbbbb eeeeeeee Operation: Operation: (PC) ο (PC) + 2 (PC) ο (PC) + 3 IF (A) = 0 IF (bit) = 1 Then (PC) ο (PC) + byte_2 Then (PC) ο (PC) + byte_3 Example:- LABEL: MOV A,P1 ANL A,#1 JZ LABEL MOV P0,P1 β¦β¦
- 11. INSTRUCTION SET SUMMARY 8051 -11- Absolute Addressing This type of addressing mode is used only with ACALL and AJMP instruction. These 2-byte instructions allow branching within the current 2K page of code memory by providing the 11 least-significant bits of the destination address in the opcode (A10-A8) and byte 2 of the instruction (A7-A0). A10 β A8 Opcode A7 A6 A5 A4 A3 A2 A1 A0 2 K page 31 : : : 2 K page 2 2 K page 1 2 K page 0 FFFFH F800H Within any 2 K page only the lower 11 bits change OFFFH 0800H 07FFH 0000
- 12. INSTRUCTION SET SUMMARY 8051 -12- Offers the advantage of short (2-byte) instructions, but has the disadvantages of limiting the range for the destination and providing position-dependent code. If the label THERE represents an instruction at address 0F46H, and the instruction AJMP THERE is in memory locations 0900H and 0901H, the assembler will encode the instruction as 111 00001 - 1st byte (A10 β A8 + opcode) 01000110 - 2nd byte (A7 β A0) 0F46H = 0000 1111 0100 1110B Example:- An ACALL instruction is in memory locations 1024H and 1025H. The subroutine to which the call is directed begins in memory location 17A6H. What are the machine language bytes for the ACALL instruction? Encoding for ACALL: aaa10001 aaaaaaaa A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0 17A6H = 0 0 0 1 0 1 1 1 1 0 1 0 0 1 1 0 Therefore, 11110001 10100110 = F1H, A6H
- 13. INSTRUCTION SET SUMMARY 8051 -13- Long Addressing Long addressing is used only with the LCALL and LJMP instructions. These 3-byte instruction include a full 16-bit destination address as bytes 2 and 3 of the instruction. The 1st byte β Opcode 2nd and 3rd - Destination Address. Opcode A15βA8 High byte add. A7βA0 Low byte add. The advantage is that the full 64K code space may be used, but the disadvantage is that the instructions are 3 byte long and are position- dependent. Example:- LJMP addr16 LCALL addr16 Bytes: 3 Bytes: 3 Cycle: 2 Cycle: 2 Encoding: Encoding: 00000010 aaaaaaaa aaaaaaaa 00010010 aaaaaaaa aaaaaaaa Operation: Operation: (PC) ο addr16 (PC) ο (PC) + 3, (SP) ο (SP) + 1, ((SP)) ο (PCL), (SP) ο (SP) + 1, ((SP)) ο (PCH), (PC) ο addr16 Example:- What are the machine language bytes for the following instruction? LJMP 8AF2H Opcode High Byte Add. Low Byte Add. Encoding :- 00000010 aaaaaaaa aaaaaaaa Hence, the machine language bytes are 02H, 8AH,F2H
- 14. INSTRUCTION SET SUMMARY 8051 -14- Indexed Addressing Indexed Addressing uses a base register(either the PC or the data pointer) and an offset(Accumulator) in forming the effective address for a JMP or MOVC instruction. Opcode Jump tables or look-up tables are easily created using indexed addressing. Examples:- MOVC A,@A+<base-reg> and JMP @A+DPTR Example: What is the opcode for the following instruction? MOVC A,@A+DPTR Solution: 93 H Example:- REL_PC: INC A ;(A) <- (A) + 1 MOVC A,@A+PC RET DB 66H DB 77H DB 88H DB 99H If The subroutine is called with the accumulator equal to 01H, it returns with 77H in the accumulator. See Appendix C page 273 for further information.
- 15. INSTRUCTION SET SUMMARY 8051 -15- Example:- Write a program to display 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 continuously through Port1. Insert some delay between each displayed digit. Display Common-Anode Display Common-Anode 0 C0H A 88H 1 F9H b 83H 2 A4H C C6H 3 B0H d A1H 4 99H E 86H 5 92H F 8EH 6 82H 7 F8H 8 80H 9 98H
- 16. INSTRUCTION SET SUMMARY 8051 -16- ORG 0H ULANG: MOV P1,#0C0H LCALL DELAY MOV P1,#0F9H LCALL DELAY MOV P1,#0A4H LCALL DELAY - - - SJMP ULANG DELAY: MOV R5,#20H AGAIN: MOV R6,#255 LOOP1: MOV R7,#0F0H LOOP: DJNZ R7,LOOP DJNZ R6,LOOP1 DJNZ R5,AGAIN RET END OR
- 17. INSTRUCTION SET SUMMARY 8051 -17- ORG 0000H ULANG: CLR A MOV R0,A MOV DPTR,#NOMBO TAMBAH: MOV A,R0 MOVC A,@A+DPTR MOV P1,A LCALL DELAY INC R0 CJNE R0,#11,TAMBAH SJMP ULANG DELAY: MOV R5,#10 LOOP2: MOV R6,#255 LOOP1: MOV R7,#255 LOOP: DJNZ R7,LOOP DJNZ R6,LOOP1 DJNZ R5,LOOP2 RET NOMBO: DB 0C0H,0F9H,0A4H,0B0H,99H,92H,82H,0F8H,80H,98H END