M O S Fi e l d - Effect

Tra n s i sto rs ( M O S F ETs)

Introduction 235 4:8. . The MOSFET lnternal

4.1 Device Structl.lte and Physic�1 . Capacitances and High- .
Operation 236 .. Frequency Model 320
4.2 Gurrent':':'Voltage · 4.9 FrequencyResponse of .
Characteristics ·248 . . the GS Amplifier $26 . .
4.3 MOSFET CircuitsatDG 262 4.10 The CMOSDigital Logic .
Inverter }36
4.4 The M OSFETas an Ampli. fier 4, ti The Depletion�Type. .
- - - - - - -

and as a Switch !l'70 MOSFET 346

4.5 Bia�ing in.MOSArn�lifier · 4.12 The SPICE M6sFEliVlodei
Circuits · �80 • •• lind Simulation Example . 35 1
. .. .

4.6 Small-Signal Operati. pn and

. .
. .
.
.
.

. Summary. 359
. . . .
.

Models 287
. .
.

4.7 Single�Stage MOS Problems · · 360 .

.. Amplifiers 299
.
.

I NT R O D U CT I O N
Having studied the junction diode, which is the most basic two-terminal semiconductor
device, we now tum our attention to three-terminal semiconductor devices. Three-terminal
devices are far more useful than two-terminal ones because they can be used in a multitude
of applications, ranging from signal amplification to digital logic and memory. The basic
principle involved is the use of the voltage between two terminals to control the current
flowing in the third terminal. In this way a three-terminal device can be used to realize a
controlled source, which as we have learned in Chapter 1 is the basis for amplifier design.
Also, in the extreme, the control signal can be used to cause the current in the third terrriinal
to change from zero to a large value, thus allowing the device to act as a switch. As we also

235
236 C H A PT E R 4 M O S F I E L D - E F F ECT TRA N S I STO RS ( M O S F ETs)

learned in Chapter 1, the switch is the basis for the realization of the logic inverter, the basic
element of digital circuits.
There are two major types of three-terminal semiconductor device: the metal-oxicte_
semiconductor field-effect transistor (MOSFET), which is studied in this chapter, and the
bipolar junction transistor (BJT), which we shall study in Chapter 5. Although each of the two
transistor types offers unique features and areas of application, the MOSFET has become by
far the most widely used electronic device, especially in the design of integrated circuits (ICs),
which are circuits fabricated on a single silicon chip.
Compared to BJTs, MOSFETs can be made quite small (i.e., requiring a small area on
the silicon IC chip), and their manufacturing process is relatively simple (see Appendix A).
Also, their operation requires comparatively little power. Furthermore, circuit designers have
found ingenious ways to implement digital and analog functions utilizing l\10SFETs almost
exclusively (i.e., with very few or no resistors). All of these properties have made it possible
to pack large numbers of MOSFETs (>200 million !) on a single IC chip to implement very
sophisticated, very-Iarge-scale-integrated (VLSI) circuits such as those for memory and micro­
processors. Analog circuits such as amplifiers and filters are also implemented in MOS
technology, albeit in smaller less-dense chips. Also, both analog and digital functions are
increasingly being implemented on the same IC chip, in what is known as mixed-signal design.
The objective of this chapter is to develop in the reader a high degree of familiarity with
the MOSFET: its physical structure and operation, terminal characteristics, circuit models,
and basic circuit applications, both, as an amplifier and a digital logic inverter. Although dis­
crete MOS transistors exist, and the material studied in this chapter will enable the reader to
design discrete MOS circuits, our study of the MOSFET is strongly influenced by the fact
that most of its applications are in integrated-circuit design. The design of IC analog and
digital MOS circuits occupies a large proportion of the remainder of this book.

4 . 1 D EV I C E STR U CT U RE A N D PHYSICA L O P E RATI O N

The enhancement-type MOSFET is the most widely used field-effect transistor. In this sec­
tion, we shall study its structure and physical operation. This will lead to the current-voltage
characteristics of the device, studied in the next section.

4.1 .1 Device Structure

Figure 4. 1 , shows the physical structure of the n-channel enhancemenHype MOSFET. The
meaning of the names "enhancement" and "n-channel" will become apparent shortly. The
transistor is fabricated on a p-type substrate, which is a single-crystal silicon wafer that pro­
vides physical support for the device (and for the entire circuit in the case of an integrated
+
circuit). Two heavily doped n-type regions, indicated in the figure as the n source ! and the
+
n drain regions, are created in the substrate. A thin layer of silicon dioxide (Si02) of thick­
ness tox (typically 2-50 nm), 2 which is an excellent electrical insulator, is grown on the sur­
face of the substrate, covering the area between the source and drain regions. Metal is
deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts
are also made to the source region, the drain region, and the substrate, also known as the

1 +
The notation n indicates heavily doped n-type silicon. Conversely, n-is used to denote lightly doped
2 An-type silicon. Similar notation applies forp-type silicon.
nanometer (nm) is 10-9 m or 0.001 pm. A micrometer (,pm), or 1micron, is 10-10 6 m. Sometimes the
oxide thickness is expressed in angstroms. An angstrom (A) is 10- nm, or 10- m.
 4 . 1 D EV I C E STRUCTU R E A N D P H YSICAL O P E RATI O N 237

Source
region

Drain region
(a)
Source (S) Gate (G) Drain (D)

Body
(B)
(b)
FIGURE 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross­
section. Typically L 0.1 to 3 11m, W 0.2 to 100 11m, and the thickness of the oxide layer (tox) is in the
= =
range of 2 to 50 nm.
body.3 Thus four terminals are brought out: the gate terminal (0), the source terminal (S),
the drain terminal (D), and the substrate or body terminal (B).
At this point it should be clear that the name of the device (metal-oxide-sell).iconductor PET)
is derived from its physical structure. The name, however, has become a general one and is

3
In Fig. 4.1, the contact to the body is shown on the bottom of the device. This will prove he1pfu1 1ater
in explaining a phenomenon known as the "body effect." It is important to note, however, that in actual
Ies, contact to the body is made at a location on the top of the device.
238 C H A P T E R 4 M O S F I E L D- E F F ECT TRA N S I STORS ( M O S F ETs)

used also for FETs that do not use metal for the gate electrode. In fact, most modern MOSFETs
are fabricated using a process known as silicon-gate technology, in which a certain type of
silicon, called polysilicon, is used to form the gate electrode (see Appendix A). Our description
of MOSFET operation and characteristics applies irrespective of the type of gate electrode.
Another name for the MOSFET is the insulated-gate FET or IGFET. This name also
arises from the physical structure of the device, emphasizing the fact that the gate electrode
is electrically insulated trom the device body (by the oxide layer). It is this insulation that
5
causes the current in the gate terminal to be extremely small (of the order of 1 0- 1 A).
Observe that the substrate forms pn junctions with the source and drain regions. In nor­
mal operation these pn junctions are kept reverse-biased at all times. Since the drain will be
at a positive voltage relative to the source, the two pn junctions can be effectively cut off by
simply connecting the substrate terminal to the source terminal. We shall assume this to
be the case in the following description of MOSFET operation. Thus, here, the substrate will
be considered as having no effect on device operation, and the MOSFET will be treated as a
three-terminal device, with the terminals being the gate (G), the source (S), and the drain (D).
It will be shown that a voltage applied to the gate controls current flow between source and
drain. This current will flow in the longitudinal direction from drain to source in the region
labeled "channel region." Note that this region has a length L and a width W, two important
parameters of the MOSFET. Typically, L is in the range of 0 . 1 f.1lll to 3 Jim, and W is in the
range of 0.2 Jim to 100 Jim. Finally, note that the MOSFET is a symmetrical device; thus its
source and drain can be interchanged with no change in device characteristics.

4.1 .2 Operation with No Gate Voltage

With no bias voltage applied to the gate, two back-to-back diodes exist in series between
drain and source. One diode is formed by the pn junction between the n+ drain region and
the p-type substrate, and the other diode is formed by the pn junction between the p-type
substrate and the n+ source region. These back-to-back diodes prevent current conduction
from drain to source when a voltage VDS is applied. In fact, the path between drain and
source has a very high resistance (of the order of 10 12 Q).

4.1 .3 Creating a Channel for Current Flow

Consider next the situation depicted in Fig. 4.2. Here we have grounded the source and the
drain and applied a positive voltage to the gate. Since the source is grounded, the gate voltage
appears in effect between gate and source and thus is denoted VGS' The positive voltage on the
gate causes, in the first instance, the free holes (which are positively charged) to be repelled
from the region of the substrate under the gate (the channel region). These holes are pushed
downward into the substrate, leaving behind a carrier-depletion region. The depletion region is
populated by the bound negative charge associated with the acceptor atoms. These charges are
"uncovered" because the neutralizing holes have been pushed downward into the substrate.
As well, the positive gate voltage attracts electrons from the n+ source and drain regions
(where they are in abundance) into the channel region. When a sufficient number of elec­
trons accumulate near the surface of the substrate under the gate, an n region is in effect cre­
ated, connecting the source and drain regions, as indicated in Fig. 4.2. Now if a voltage is
applied between drain and source, current flows through this induced n region, carried by
the mobile electrons. The induced n region thus forms a channel for current flow from drain
to source and is aptly called so. Correspondingly, the MOSFET of Fig. 4.2 is called an
n-channel MOSFET or, alternatively, an NMOS transistor. Note that an n-channel
MOSFET is formed in a p-type substrate: The channel is created by inverting the substrate
surface from p type to n type. Hence the induced channel is also called an inversion layer.
 4 . 1 DEVICE STR U CT U R E A N D P HYS I CAL O P E RATI O N 239

+ Gate electrode

Depletion region
B

FIGURE 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An
n channel is induced at the top of the substrate beneath the gate.

The value of VGS at which a sufficient number of mobile electrons accumulate in the
channel region to form a conducting channel is called the threshold voltage and is denoted
Vr4 Obviously, Vt for an n-channel FET is positive. The value of Vt is controlled during
device fabrication and typically lies in the range of 0.5 V to 1.0 V.
The gate and the channel region of the MOSFET form a parallel-plate capacitor, with the
oxide layer acting as the capacitor dielectric. The positive gate voltage causes positive
charge to accumulate on the top plate of the capacitor (the gate electrode). The correspond­
ing negative charge on the bottom plate is formed by the electrons in the induced channel.
An electric field thus develops in the vertical direction. It is this field that controls the
amount of charge in the channel, and thus it determines the channel conductivity and, in
turn, the current that will flow through the channel when a voltage VDS is applied.

4.1 .4 Applying a Small VDS

Having induced a channel, we now apply a positive voltage VDS between drain and source, as
shown in Fig. 4.3. We first consider the case where VDS is small (i.e., 50 mV or so). The voltage
VDS causes a current iD to flow through the induced n channel. Current is carried by free elec­
trons traveling from source to drain (hence the names source and drain). By convention, the
direction of current flow is opposite to that of the flow of negative charge. Thus the current
in the channel, iD, will be from drain to source, as indicated in Fig. 4.3 . The magnitude of iD
depends on the density of electrons in the channel, which in turn depends on the magnitude
of VGS' Specifically, for VGS Vt the channel is just induced and the current conducted is still
=

negligibly small. As VGS exceeds VI' more electrons are attracted into the channel. We may
visualize the increase in charge carriers in the channel as an increase in th,e channel depth.
The result is a channel of increased conductance or, equivalently, reduced resistance. In fact,
the conductance of the channel is proportional to the excess gate voltage (vGS Vt), also -

4 Some texts use VT to denote the threshold voltage. We use V, to avoid confusion with the thermal
voltage VT.
240 CHAPTER 4 M O S F I E L D - E F F ECT TRA N S I STORS ( M O S F ETs)

+
.I.
vGS

G t iG = 0
+
.I.
t D
-= VDS (small)

t is = ID
iD
S

FIGURE 4.3 An NMOS transistor with vGs > V, and with a small VDS applied. The device acts as a resis­
tance whose value is determined by VGS' Specifically, the channel conductance is proportional to VGS V" and -

thus iD is proportional to (vGS - V,) vvs- Note that the depletion region is not shown (for simplicity).

known as the effective voltage or the overdrive voltage. It follows that the current iD will
be proportional to vGS V, and, of course, to the voltage VDS that causes iD to flow.
-

Figure 4.4 shows a sketch of iD versus VDS for various values of VGS' We observe that the
MOSFET is operating as a linear resistance whose value is controlled by VGS' The resistance
is infinite for VGS :::;; V" and its value decreases as VGS exceeds V,,·

0.4 VGS = V, + 2V

0.3 VGS = V, + l .5 V

0.2 VGS = V, + 1V

0.1 VGS = V, + 0.5 V

VGS :S V,

o 50 100 150 200

FIGURE 4.4 The ID-vDs characteristics of the MOSFET in Fig. 4.3 when the voltage applied between
drain and source, VDS, is kept small. The device operates as a linear resistor whose value is controlled by VGS'
 4 . 1 DEVICE STR U CTU R E A N D P H YS I CAL O P E RATI O N 241

The description above indicates that for the MOSFET to conduct, a channel has to be
increasing VGS above the threshold voltage VI enhances the channel, hence
induced. Then,
ncement-mode operation and enhancement-type MOSFET. Finally,
the names enha
we note that the current that leaves the source terminal (is) is equal to the current that enters
the drain terminal (iD), and the gate current iG = O.

�t �� J«! M()�Jt,f6r' lsYt �: ()

' ';
'
4.i From the d�sCriPrl{) � QVe6ithe �rati of the s�!i11'v �110te tqDiS proP rUonat
to (VGS"'- V,)VDS: Find the col;ls tant of proportionality for the partiCular devIce whose characteristics are
depicted in Fig: 4.4. Also, give the range of drain-to�spurce. . resistances
. .
corresponding to an, overdrive
' '
voltage, vas - V" of 0.5 V to :2 V..
Ans. l mA/V2; 2 kQ to 0.5 ill

4.1 .5 Operation as VDS Is Increased

We next consider the situation as VDS is increased. For this purpose let VGS be held constant
at a value greater than VI' Refer to Fig. 4.5, and note that VDS appears as a voltage drop
across the length of the channel. That is, as we travel along the channel from source to
drain, the voltage (measured relative to the source) increases from 0 to VDS' Thus the volt­
age between the gate and points along the channel decreases from VGS at the source end to
VGS - VDS at the drain end. Since the channel depth depends on this voltage, we find that the
channel is no longer of uniform depth; rather, the channel will take the tapered form shown
in Fig. 4.5, being deepest at the source end and shallowest at the drain end. As VDS is
increased, the channel becomes more tapered and its resistance increases correspondingly.
Thus the iD-VDS curve does not continue as a straight line but bends as shown in Fig. 4.6.
Eventually, when VDS is increased to the value that reduces the voltage between gate and

VGS .I. VDS

+
+

G t iG = 0
iD t
t is = iD
D -
S

FIGURE 4.5 Operation of the enhancement NMOS transistor as VDS is increased. The induced channel
acquires a tapered shape, and its resistance increases as VDS is increased. Here, VGS is kept constant at a
value > VI"
242 C H A P T E R 4 M O S F I E L D- E F F ECT TRA N S I STORS ( M O S F ETs)

� Triode �: ...
<<----- Saturation ---....,��

VDS < VOS - V, VDS

V, 2:: VOS -

� Current saturates because the

��----�--���--------
Curve bends because
the channel resistance channel is pinched off at the
increases with VDS drain end, and VDS no longer
affects the channel.
Almost a straight line
with slope proportional
-
to (vos V,)

o = VOS - Vt
VDSsat VDS

FIGURE 4.6 The drain current iD versus the drain-to-source voltage VDS for an enhancement-type NMOS
transistor operated with vGs > VI"
channel at the drain end to Vt-that is, VGD == Vt or VGS - VDS = Vt or VDS = VGS - VI-the chan­
nel depth at the drain end decreases to almost zero, and the channel is said to be pinched
off. Increasing VDS beyond this value has little effect (theoretically, no effect) on the channel
shape, and the current through the channel remains constant at the value reached for VDS =
VGS - Vt' The drain current thus saturates at this value, and the MOSFET is said to have
entered the saturation region of operation. The voltage VDS at which saturation occurs is
denoted VDSsat'

(4. 1)

Obviously, for every value of VGS 2 V" there is a corresponding value of VDSsat. The device oper­
ates in the saturation region if vDS 2 VDSsat. The region of the iD-vDS characteristic obtained
for VDS < VDSsat is called the triode region, a carryover from the days of vacuum-tube devices
whose operation a FET resembles.
To help further in visualizing the effect of VDS, we show in Fig. 4.7 sketches of the chan­
nel as VDS is increased while VGS is kept constant. Theoretically, any increasein VDS above

Source Drain

t VDS = 0
FIGURE 4.7 Increasing VDS causes the channel to acquire a tapered shape. Eventually, as VDS reaches
VGS - -
V" the channel is pinched off at the drain end. Increasing VDS above VGS V, has little effect (theoretically,
no effect) on the channel's shape.
 4 . 1 DEVICE STR U CTU R E A N D P HY S I C A L O P E RAT I O N 243

(whiCh is equal t� VGS - Vt) h.as no effect on the chan2el s?ape �nd simply appears
�:
V sat
tion regIOn surroundmg the channel and the n dram regIOn.
a oss the deple

4.1 .6 Derivation of the iD-VDS Relations h i p

The description of physical operation presented above can b e used to derive an expression
for the iv-vvs relationship depicted in Fig. 4.6. Toward that end, assume that a voltage VGS is
and source with vGs > Vt to induce a channel. Also, assume that a volt­
applied between gate
age VV S is app lied between drain and source. First, we shall consider operation in the triode
regio n, for which the channel must be continuous and thus VGV must be greater than Vt or,
equi vale ntly, VV S < VGS - Vt· In this case the channel will have the tapered shape shown in
Fig. 4.8.
The reader will recall that in the MOSFET, the gate and the channel region form a parallel-
plate capacitor for which the oxide layer serves as a dielectric. If the capacitance per unit
gate area is denoted Cox and the thickness of the oxide layer is tax' then

(4.2)

where 80x is the permittivity of the silicon oxide,

3.9 X 8.854 X 10- == 3 .45 X 10-

12 11
80x == 3.980 == Flm

The oxide thickness tax is determined by the process technology used to fabricate the
3 2 2
MOSFET. As an example, for tax == 1 0 nm, Cox 3.45 X 1 0- F/m , or 3.45 fF/.um as it is
==

usually expressed.
Now refer to Fig. 4.8 and consider the infinitesimal strip of the gate at distance x from
the source. The capacitance of this strip is CoxW dx. To find the charge stored on this infini­
tesimal strip of the gate capacitance, we multiply the capacitance by the effective voltage

Oxide
Capacitor of value
Cox W dx

I I I
011
I
I E
= _ dv(x)
dx
I I I I
I...-l-v- (x)
----;..j i-..l.
� ... dv(x)
I I
0 VDS
.. Voltage
I I I I I
I I I I I ..
0 L x
FIGURE 4.8 Derivation of the iD-VDS characteristic of the NMOS transistor.
244 C H A PT E R 4 M O S F I E LD-E F F E CT TRA N S I STO R S ( M O S F ETs)

between the gate and the channel at point x, where the effective voltage is the voltage that is
responsible for inducing the channel at point x and is thus [VOS - VeX) Vt] where vex) is the
-

voltage in the channel at point x. It follows that the electron charge dq in the infinitesimal
portion of the channel at point x is

(4.3)

where the leading negative sign accounts for the fact that dq is a negative charge.
The voltage VDS produces an electric field along the channel in the negative x direction.
At point x this field can be expressed as

_ dv(x)
E(x) =
dx
The electric field E(x) causes the electron charge dq to drift toward the drain with a velocity
dxldt,

(4.4)

where f.1n is the mobility of electrons in the channel (called surface mobility). It is a physical
parameter whose value depends on the fabrication process technology. The resulting drift
current i can be obtained as follows:

1. = dq
-
dt
=
dq dx
dx dt
Substituting for the charge-per-unit-length dq Idx from Eq. (4.3), and for the electron drift
velocity dxl dt from Eq. (4.4), results in

- Jin Cox W [ vos - ve x) Vt] �

. =
d��
I -

Although evaluated at a particular point in the channel, the current i must be constant at all
points along the channel. Thus i must be equal to the source-to-drain current. Since we are
interested in the drain-to-source current iD, we can find it as

which can be rearranged in the form

Jin Cox W [ vos - Vt - vex)] dv(x)

iD dx =

Integrating both sides of this equation from x = 0 to x = L and, correspondingly, for v(O) = 0
to veL) = VDS,

gives

(4.5)
 4 . 1 DEVI CE STR U CTU R E A N D P HYS I CAL O P E RATI O N 245

This is the expression for the iD-VDS characteristic in the triode region. The value of the cur­

�
ent at the edge of the triode region or, equivalently, at the beginning of the saturation region
an be obtained by substituting VDS = Ves - Vt, resulting in

(4.6)

This is the expression for the iD-VDS characteristic in the saturation region; it simply gives
the saturation value of iD corresponding to the given Ves. (Recall that in saturation iD remains
constant for a given Ves as VDS is varied.)
In the expressions in Eqs. (4.5) and (4.6), J1n Cox is a constant determined by the process
technology used to fabricate the n-channel MOSFET. It is known as the process transcon­
ductance parameter, for as we shall see shortly, it determines the value of the MOSFET
transconductance, is denoted k� , and has the dimensions of AJV2:

(4.7)

Of course, the iD-VDS expressions in Eqs. (4.5) and (4.6) can be written in terms of k� as
follows:

(Triode region) (4.5a)

(Saturation region) (4.6a)

In this book we will use the forms with (J1nCox) and with k� interchangeably.
From Eqs. (4.5) and (4.6) we see that the drain current is proportional to the ratio of the
channel width W to the channel length L, known as the aspect ratio of the MOSFET. The
values of W and L can be selected by the circuit designer to obtain the desired i- v character­
istics. For a given fabrication process, however, there is a minimum channel length, L in. In
m
fact, the minimum channel length that is possible with a given fabrication process is used to
characterize the process and is being continually reduced as technology advances. For
instance, at the time of this writing (2003) the state-of-the-art in MOS technology is a O.1 3-J1m
process, meaning that for this process the minimum channel length possible is 0.13 J1m.
There also is a minimum value for the channel width W. For instance, for the O. 13-J1m pro­
cess just mentioned, Wmin is 0. 1 6 J1m. Finally, we should note that the oxide thickness tax
scales down with Lmin- Thus, for a 1 .5-J1m technology, tox is 25 nm, but the modern O. 1 3-J1m
technology mentioned above has tax = 2 nm.

Consider a process technology for which Lrnin = 0.4 11m, tox = 8 urn, Jin =
2
450 cm N· s, and Vr = 0.7 V.
(a) Find Cox and k� .
(b) For a MOSFET with W /L = 8 Jim/ 0.8 Jim, calculate the values of Ves and VDSrnin needed
to operate the transistor in the saturation region with a dc current ID = 1 00 JiA.
(c) For the device in (b), find the value of Ves required to cause the device to operate as a 1 000-0
resistor for very small VDS.
246 C H A P T E R 4 M O S F I E L D - E F F ECT TRA N S I STORS (MOS F ETs)

Solution 1
(a) Cox = - =
Cox 3.45 X 10-9 = 4.32 10- F/m2
1 -
x
3
tax 8 X 10-
= 4.32 fFI,um2 2
k� ,un Cox = 450 (cm2/V·s) 4.32 (fFI,um )
= X

= 450 X 10 6(,um2/V·s) X 4.32 X 1O- 5 (FI,um2 )

8 1
194 X 10- (FIY·s)
194 ,uA/y2
(b) For operation in the saturation region,
I.D = 2:1 WL ( VGS - Vt)2
k'
n

Thus,
100 = 1 X 194 X 0.8
-

2
8 VGS - 0.7)2
-(
which results in
VGS - 0.7 0.32 Y=

or
VGS = 1.02 Y
and
VDSmin = VGS - Vt = 0.32 Y
(c) For the MOSFET in the triode region with VDS very small,
iD = k� WL ( vGSl - Vt ) vDS
from which the drain-to-source resistance TDS cal be found as

Thus
1000 = 194 X 10 -6 X 1lO e - 0.7)
vGS
which yields
VGS -0.7 = 0.52 Y
VGS 1.22
= Y
 4 . 1 D EV I C E STRUCTU R E A N D P H YSICAL O P ERAT I O N 247

FOraO.8�pni iJro6��ste�ljrib��iYf9r�h1kl1,tox . .
'i
drive vQItage V v == V(]S � Vt/reqi#r�di() ()penlt�
h
ii
4.2

O.2 mA. Wha:tis the.ininimumvalue of VDs .needed?

:'2 " . . . • . . ' 2 " . . . . . ' . . '
... . . .. . . . .
Ans. 2.3 fF/pm ; 127 pAN . ; 0.40 Y; 0.40 Y
4.3 U e the expression for operation in the triode region to show that an n�channel MOSFET operated in
s
aturation with an overdrive voltage Vo v == Vos "'" VI and having a small VD.S acro s it behav�s approxi-
s s
mately e
as a linear r sist ance rDS'

rD S = l /[ � l
k� Vo v

Calculate the value of rDS obtained for a device having k� = 100 pA/y2 and W/L = 10 when operated
with an overdrive voltage of 0.5 Y.
Ans. 2 kD

4.1 .7 The p- Channei MOSFET

Ap-channel enhancement-type MOSFET (PMOS transistor), fabricated on an n-type substrate
with p+ regions for the drain and source, has holes as charge carriers. The device operates
in the same manner as the n-channel device except that VGS and VDS are negative and the
threshold voltage Vt is negative. Also, the current iD enters the source terminal and leaves
through the drain terminal.
PMOS technology originally dominated MOS manufacturing. However, because NMOS
devices can be made smaller and thus operate faster, and because NMOS historically required
lower supply voltages than PMOS, NMOS technology has virtually replaced PMOS. Never­
theless, it is important to be familiar with the PMOS transistor for two reasons: PMOS devices
are still available for discrete-circuit design, and more importantly, both PMOS and NMOS
transistors are utilized in complementary MOS or CMOS circuits, which is currently the
dominant MOS technology.
4.1 .8 Com plementary MOS or CMOS
As the name implies, complementary MOS technology employs MOS transistors of both
polarities. Although CMOS circuits are somewhat more difficult to fabricate than NMOS,
the availability of complementary devices makes possible many powerful circuit-design possi­
bilities. Indeed, at the present time CMOS is the most widely used of all the IC technologies.
This statement applies to both analog and digital circuits. CMOS technology has virtually
replaced designs based on NMOS transistors alone. Furthermore, at the time of this writing
(2003), CMOS technology has taken over many applications that just a few years ago were
possible only with bipolar devices. Throughout this book, we will study many CMOS circuit
techniques.
Figure 4.9 shows a cross-section of a CMOS chip illustrating how the PMQS and NMOS
transistors are fabricated. Observe that while the NMOS transistor is implemented directly in
the p-type substrate, the PMOS transistor is fabricated in a specially created n region, known
as an well. The two devices are isolated from each other by a thick region of oxide that func­
n
tions as an insulator. Not shown on the diagram are the connections made to the p-type body
and to the n well. The latter connection serves as the body terminal for the PMOS transistor.
248 C H A P T E R 4 M O S F I E LD- E F F ECT TRA N S I STO RS (MOS F ETs)

NMOS PMOS

S G D D G S

FIGURE 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a
separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is
used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to
the n well; the latter functions as the body terminal for the p-channel device.

4.1 .9 O perating the MOS Tra nsistOlr in the Subth reshOlld Reg iOln
The above description of the n-channel MOSFET operation implies that for Vcs < Vt, no cur­
rent flows and the device is cut off. This is not entirely true, for it has been found that for
values of Vcs smaller than but close to Vt, a small drain current flows. In this subthreshold
region of operation the drain current is exponentially related to Vcs, much like the ie-VEE
relationship of a BJT, as will be shown in the next chapter.
Although in most applications the MOS transistor is operated with Vcs > Vt, there are
special, but a growing number of, applications that make use of subthreshold operation. In
this book, we will not consider subthreshold operation any further and refer the reader to the
references listed in Appendix F.

4.2 C U R R E N T -VO LTAG E C H A RA CT E R i ST I CS

Building on the physical foundation established in the previous section for the operation of
the enhancement MOS transistor, we present in this section its complete current-voltage
characteristics. These characteristics can be measured at dc or at low frequencies and thus
are called static characteristics. The dynamic effects that limit the operation of the MOSFET
at high frequencies and high switching speeds will be discussed in Section 4.8.

4.2.1 Circuit SymbOlI

Figure 4. 1O(a) shows the circuit symbol for the n-channel enhancement-type MOSFET.
Observe that the spacing between the two vertical lines that represent the gate and the chan­
nel indicates the fact that the gate electrode is insulated from the body of the device. The
polarity of the p-type substrate (body) and the n channel is indicated by the arrowhead on
the line representing the body (B). This arrowhead also indicates the polarity of the transistor,
namely, that it is an n-channel device.
in
Although the MOSFET is a symmetrical device, it is often useful circuit design to desig­
nate one terminal as the source and the other as the drain (without having to write S and D
beside the terminals). This objective is achieved in the modified circuit symbol shown in
Fig. 4.1 O(b). Here an arrowhead is placed on the source terminal, thus distinguishing it from
 ""II',
' ,t"

4.2 C U R R E NT-VOLTAG E C H A RACT E R I STICS 249

D D D

0--/ B G 0---1 1------0 B I

!
G I0Il----0

s s s
(a) (b) (c)
FIGURE 4.1 0 (a) Circuit symbol for tbe n-channel enhancement-type MOSFET. (b) Modified circuit
symbol with an arrowhead on tbe source terminal to distinguish it from the drain and to indicate device
polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to tbe body
or when the effect of the body on device operation is unimportant.

the drain terminal. The arrowhead points in the normal direction of current flow and thus
indicates the polarity of the device (i.e., n channel). Observe that in the modified symbol,
there is no need to show the arrowhead on the body line. Although the circuit symbol of
Fig. 4. 1O(b) clearly distinguishes the source from the drain, in practice it is the polarity of
the voltage impressed across the device that determines source and drain; the drain is always
positive relative to the source in an n-channel FET
In applications where the source is connected to the body of the device, a further simpli­
fication of the circuit symbol is possible, as indicated in Fig. 4. 1 0( c). This symbol is also
used in applications when the effect of the body on circuit operation is not important, as will
be seen later.

4.2.2 The iD-VDS Cha racteristics

Figure 4. 1 l (a) shows an n-channel enhancement-type MOSFET with voltages VGS and VDS
applied and with the normal directions of current flow indicated. This conceptual circuit can
be used to measure the iD-vDs characteristics, which are a family of curves, each measured
at a constant VGS' From the study of physical operation in the previous section, we expect
i
each of the iD-vDs curves to have the shape shown in F g. 4.6. This indeed is the case, as is
evident from Fig. 4. 1 l (b), which shows a typical set of iD-VDS characteristics. A thorough
understanding of the MOSFET terminal characteristics is essential for the reader who
intends to design MOS circuits.
The characteristic curves in Fig. 4. 1 l (b) indicate that there are three distinct regions of
operation: the cutoff region, the triode region, and the saturation region. The saturation
region is used if the FET is to operate as an amplifier. For operation as a switch, the cutoff
and triode regions are utilized. The device is cut off when VGS < Vt. To operate the MOSFET
in the triode region we must first induce a channel,

VGS � Vt (Induced channel) (4.8)

and then keep VDS small enough so that the channel remains continuous. This is achieved by
ensuring that the gate-to-drain voltage is

VGD > Vt (Continuous channel) (4.9)

This condition can be stated explicitly in terms of VDS by writing VGD = VGS + VSD = VGS - VDS;
thus,
250 C H A P T E R 4 M O S F I ELD-E F F ECT TRA N S I STO RS ( M O S F ETs)

iD (rnA)

2.0

1 .5

1.0

0.5
+

Ves :S V, (cutoff)
(a) (b)
directions of current flow indicated. (b) The iD-VDS characteristics for a device with k� ( WIL) = 1 .0 ruAN2 .
FIGURE 4.1 1 (a) An n-channel enhancement-type MOSFET with VGS and VDS applied and with the no=al

which can be rearranged to yield

VDS < Vcs - V, (Continuous channel) (4. 1 0)
Either Eq. (4.9) or Eq. (4. 1 0) can be used to ascertain triode-region operation. In words, the
n-channel enhancement-type MOSFET operates in the triode region when Vcs is greater than
V, and the drain voltage is lower than the gate voltage by at least Vt volts.
In the triode region, the iD-vDs characteristics can be described by the relationship of

�[ ( ves - Vt) VDS - � v;sJ

Eq. (4.5), which we repeat here,

iD == k� (4. 1 1 )

where k� f..ln Cox is the process transconductance parameter; its value is determined by
the fabrication technology. If VDS is sufficiently small so that we can neglect the v;s term in
==

Eq. (4. 1 1), we obtain for the iD-vDS characteristics near the origin the relationship

�
iD = k� ( ves - Vt) vDS (4. 12)

This linear relationship represents the operation of the MOS transistor as a linear resistance
rDS whose value is controlled by VCS' Specifically, for VCS set to a value Vcs, rDs is given by

(4. 1 3)

We discussed this region of operation in the previous section (refer to Fig. 4.4). It is also
useful to express rDS in terms of the gate-to-source overdrive voltage,

Vo v == Vcs - Vt (4. 14)

 4.2 C U RR E NT-VOLTAG E C H A RACTE R I STICS 251

as

(4. 1 5)

Finally, we urge the reader to show that the approximation involved in writing Eq. (4. 12)
is based on the assumption that vDS <%: 2Va v '
To operate the MOSFET in the saturation region, a channel must be induced,

VGS � Vt (Induced channel) (4. 1 6)

and pinched off at the drain end by raising VDS to a value that results in the gate-to-drain
voltage falling below Vt,

VGD :s; Vt (Pinched-off channel) (4. 17)

This condition can be expressed explicitly in terms of VDS as

VDS � VGS - Vt (Pinched-off channel) (4. 1 8)

In words, the n-channel enhancement-type MOSFET operates in the saturation region when
VGS is greater than Vt and the drain voltage does not fall below the gate voltage by more
than Vt volts.
The boundary between the triode region and the saturation region is characterized by

VDS = VGS - Vt (Boundary) (4. 1 9)

Substituting this value of VDS into Eq. (4. 1 1) gives the saturation value of the current iD as

(4.20)

Thus in saturation the MOSFET provides a drain current whose value is independent of the
drain voltage VDS and is determined by the gate voltage VGS according to the square-law rela­
tionship in Eq. (4.20), a sketch of which is shown in Fig. 4.12. Since the drain current
is independent of the drain voltage, the saturated MOSFET behaves as an ideal current
source whose value is controlled by VGS according to the nonlinear relationship in Eq. (4.20).
Figure 4 . 1 3 shows a circuit representation of this view of MOSFET operation in the satura­
tion region. Note that this is a large-signal equivalent-circuit model.
Referring back to the iD-vDS characteristics in Fig. 4. 1 1 (b), we note that the boundary
between the triode and the saturation regions is shown as a broken-line curve. Since this
curve is characterized by VDS VGS - Vt, its equation can be found by substituting for VGS - Vt
=

by VDS in either the triode-region equation (Eq. 4. 1 1) or the saturation-region equation

(Eq. 4.20). The result is

(4.21)

It should be noted that the characteristics depicted in Figs. 4.4, 4. 1 1 , and 4 . 1 2 are for a
MOSFET with k�(W/L) = 1 .0 mAN2 and Vt = 1 V.
Finally, the chart in Fig. 4.14 shows the relative levels of the terminal voltages of the
enhancement-type NMOS transistor for operation, both in the triode region and the saturation
region.
252 C H A P T E R 4 M O S F I E L D-E F F ECT TRA N S I STORS ( M O S F ETs)

iD (rnA)

2.0

1.5
VDS � vos - V,

1.0

0.5

0.5
.t-
o 1 1.5 2 2.5 3 VOS (V)

V,

kn W/L = 1 .0 mAN )
FIGURE 4.1 2 The iD-vGS characteristic for' an enhancement-type NMOS transistor in saturation ( V, = 1 V.
' 2 .
iD
�
G D
+
VDS

VGS � V,
vDS 2: VGS - V,

FIGURE 4.1 3 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation
region.

Voltage II

I
II

Overdrive

t
voltage Saturation

�
t
V,
D ()
Triode FIGURE 4.14 The relative levels of the

t ------
--'-- -'---
V,
{} terminal voltages of the enhancement NMOS
S transistor for operation in the triode region and
in the saturation region.
 4.2 C U R R E NT-VO LTAG E C H A RACTER I STICS 253

� '
on
4.4 An enhancementctype.NMOS tJ:ariSist r with Vt = 0:7Vhas its source te inal grounded anda 1.5-V de "
applied to the gate. In what region does the deviCe operate :for (a) Vp = +0.5 V? (b) VD = 0 .9. V ?
.. .
(c) VD;: 3 V?
Ans. (a) Triode; (b)Satunition; (c) Saturation
4.5 If the NMOS device in ExercIse 4.4 has flnC:x 100 flAJV2, W = 10 flm, and L 1 tim, find the value
= =
. of
drain current that results in each of the three cases (a),'(b), and tc) specified in Exercise 4.4:
Ans. (a) 275 flA; (b) 3 20 J-LA; (c) 320 flA
4.6 An enhancement-type NMOS transistor with Vt 0.7 V conducts a current iD 100 f1A when vGS =,vDS
. ls o , calcula
= =

=1.2 V. Find the value of iD for vGs == 1.5 V and VDS ;= 3 V. A ' te the value of the drain�to-
source.resistance rDS for small vDS and VGS = 3:2 V ; ·'
Ans. 256 flA; 500 Q

4 .2.3 Finite Output Resistance in Saturation

'
Equation (4.12) and the corresponding large-signal equivalent circuit in Fig. 4.13 indicate
that in saturation, iD is independent of VDS. Thus a change !1VDS in the drain-to-source volt­
age causes a zero change in iD, which implies that the incremental resistance looking into
the drain of a saturated MOSFET is infinite. This, however, is an idealization based on the
premise that once the channel is pinched off at the drain end, further increases in VDS have no
effect on the channel' s shape. But, in practice, increasing VDS beyond VDSsat does affect the chan­
nel somewhat. Specifically, as VDS is increased, the channel pinch-off point is moved slightly
away from the drain, toward the source. This is illustrated in Fig. 4.15, from which we note
that the voltage across the channel remains constant at VGS - Vt = VDSsat, and the additional
voltage applied to the drain appears as a voltage drop across the narrow depletion region
between the end of the channel and the drain region. This voltagc accelerates the electrons
that reach the drain end of the channel and sweeps them across the depletion region into the
drain. Note, however, that (with depletion-layer widening) the channel length is in effect
reduced, from L to L - !1L, a phenomenon known as channel-length modulation. Now,
since iD is inversely proportional to the channel length (Eq. 4.20), iD increases with VDS'

Drain
1
1

i1""':(0----- L - 6L ----:"'",i,1 6L�I<E-

1
VDSsat = VGS - V, + - VDS - VDSsat

1 1 1
1 1
I«'----- L -------'>1
FIGURE til.1 5 Increasing VVS beyond VVSsat causes the channel pinch-off point to move slightly away from
the drain, thus reducing the effective channel length (by M).
254 CHAPTER 4 M O S F I ELD-E F F E CT TRA N S I STORS (MOS F ETs)

To account for the dependence of iD on VDS in saturation, we replace L in Eq. (4.20) with
L - M to obtain

l D = 2: kn L - f1L VGS - t
. 1 ' W
( V )2
- ! kn' W
-
1
2 L l - (f1L/L) GS
(v t
_ V )2
2 L
n ( �
== ! k ' W I +
f1L ( V
L
)
GS t _
v )2
where we have assumed that (f1L/ L) � 1. Now, if we assume that M is proportional to VDS,
f1L = AtVDS

( 1 + AtL VDS) ( VGS - vi

where At is a process-technology parameter with the dimensions of J.1mN, we obtain for iD,

iD = ! k� W
2 L
Usually, X/L is denoted A,
A = At
-
L
l
It follows that A is a process-technology parameter with the dimensions of y- and that, for
a given process, A is inversely proportional to the length selected for the channel. In terms
of A, the expression for iD becomes

iD = ! k� W ( vGS - Vt)\1 + AVDS) (4.22)

2 L
A typical set of iD-VDS characteristics showing the effect of channel-length modulation is
displayed in Fig. 4.16. The observed linear dependence of iD on VDS in the saturation region
is represented in Eq. (4.22) by the factor ( 1 + AVDS)' From Fig. 4. 1 6 we observe that when
the straight-line iD-VDS characteristics are extrapolated they intercept the vDs-axis at the
point VDS = -VA, where VA is a positive voltage. Equation (4.22), however, indicates that iD = 0

VGS - Vt = 2.0 V
Triode ��� ,.

VGS - Vt = 1 .5 V

VGS - V, = 1 .0 V

FIGURE 4.1 6 Effect of VDS on iD in the saturation region. The MOSFET parameter VA depends on the
process technology and, for a given process, is proportional to the channel length L.
 4.2 C U R R E NT-VOLTAG E C H A RACT E R I ST I C S 255

=0

'-----a D
+ + FiGURE 4.1 7 Large-signal equiva­
lent circuit model of the n-channel
VGS MOSFET in saturation, incorporating
the output resistance rD . The output
resistance models the linear depen­
dence of iD on VDS and is given by
Eq. (4.22).

at VDS == - 1 / /t. It follows that

I
VA 1
==

and thus VA is a process-technology parameter with the dimensions of V. For a given pro­
cess, VA is proportional to the channel length L that the designer selects for a MOSFET. Just
as in the case of /t, we can isolate the dependence of VA on L by expressing it as

VA == V� L
where V� is entirely process-technology dependent with the dimensions of V/pm. Typically,
V� falls in the range of 5 V/flm to 50 V/flm. The voltage VA is usually referred to as the Early
voltage, after 1M. Early, who discovered a similar phenomenon for the BJT (Chapter 5).
Equation (4.22) indicates that when channel-length modulation is taken into account,
the saturation values of iD depend on VDS' Thus, for a given VCS, a change AVDs yields a
corresponding change AiD in the drain current iD. It follows that the output resistance of
the current source representing iD in saturation is no longer infinite. Defining the output
. 5
reSIstance r as a

(4.23)
and using Eq. (4.22) results in
[/t k'� W ( Vcs - vi
L
-1J (4.24)

which can be written as

(4.25)
or, equivalently,

r
VA
o ==
-
(4.26)
ID
t
where ID is the drain current without channel-length modulation taken into account; tha is,

ID == �k� � ( Vcs - Vt)2

Thus the output resistance is inversely proportional to the drain current. Finally, we show in
Fig. 4.17 the large-signal equivalent circuit model incorporating rD.

5 In this book we use ro to denote the output resistance in saturation, and rDS to denote the drain-to­
source resistance in the triode region, for small VDS'
256 CHAPTER 4 M a S F I E L D-E F F ECT TRA N S I STO RS ( M O S F ETs)

An�OS tr�nsistot iSfabricrted in.a o.4�pniproi1ss.4aving flnCox=o.io6Jiwi·���·. vl �.·�bvl��of·

channel length. If L = O.8 ,um and W;; 16 ,um, findVA
device is operated with an overdrive voWlgeVov 0.5 V and
and A.Find thevcUue ofip that results when the
== VDS
= 1 V. Also, find the value ofr.o atthis
operating point.IfVDS is increased by 2 V, what is the corresponding
. change
. in ID?
Ans. 40 V; 0.025 V�l; 0.51 mA;80 kQ; O.025 mA

4.2.4 Characteristics of the p-Ch annel M O S F ET

The circuit symbol for the p-channel enhancement-type MOSFET is shown in Fig. 4. 1 8(a).
Figure 4.1 8(b) shows a modified circuit symbol in which an arrowhead pointing in the nor­
mal direction of current flow is included on the source terminal. For the case where the
source is connected to the substrate, the simplified symbol of Fig. 4 . 1 8(c) is usually used.
The voltage and current polarities for normal operation are indicated in Fig. 4.l 8(d). Recall
that for the p-channel device the threshold voltage VI is negative. To induce a channel we
apply a gate voltage that is more negative than VI'

vcs ::::: , vl (Induced channel) (4.27)

s s s

G 0-----1 t------0 B

D D D
(a) (b) (c)

+ is = iD
� VDS
VGS
+

iG = 0 + iD +

(d)

FIGURE 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol
with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is con­
nected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated.
Note that VGS and VDS are negative and iD flows out of the drain terminal.
 4.2 C U R R E NT-VOLTA G E C H A RACT E R I STI C S 257

or, equivalently,

and apply a drain voltage that is more negative than the source voltage (i.e., VDS is negative
or, equivalently, VSD is positive). The current iD flows out of the drain terminal, as indicated
in the figure. To operate in the triode region VDS must satisfy

VDS � VGS Vt
-
(Continuous channel) (4.28)

that is, the drain voltage must be higher than the gate voltage by at least I Vtl . The current iD
is given by the same equation as for NMOS, Eq. (4. 1 1), except for replacing k� with k;,

(4.29)

where VGS, Vt, and VDS are negative and the transconductance parameter k; is given by
(4.30)
where J1p is the mobility of holes in the induced p channel. Typically, J1p = 0.25 to 0.5J1n and
is process-technology dependent.
To operate in saturation, VDS must satisfy the relationship

VDS S VGS V t
-
(Pinched-off channel) (4.3 1)

that is, the drain voltage must be lower than (gate voltage + [ Vt l ) . The current iD is given by
the same equation used for NMOS, Eq. (4.22), again with k� replaced with k;,

(4.32)

where vGS' Vt, A, and VDS are all negative. We should note, however, that in evaluating ro
using Eqs. (4.24) through (4.26), the magnitudes of A and VA should be used.
To recap, to turn a PMOS transistor on, the gate voltage has to be made lower than that
of the source by at least I Vtl . To operate in the triode region, the drain voltage has to exceed
that of the gate by at least I Vtl ; otherwise, the PMOS operates in saturation.
Finally, the chart in Fig. 4.19 provides a pictorial representation of these operating
conditions.

S t
Voltage

I V, I 11-

1 �
Threshold Triode
t
¢ I Vtl
r:
.------JJ�_
-' D

Saturation FIGURE 4.1 9 The relative levels of the termi­

Overdrive
voltage II nal voltages of the enhancement-type PMOS
II transistor for operation in the triode region and
II in the saturation region.
258 CHAPTER 4 M O S F I ELD-E F F E CT TRA N S I STO RS (MOS F ETs)

. . . . ' . ' ... .T��:PMos,i�an�1�to� �h()�in,.Flg. E4.�ha�yt·f= -i V, K; �WllAIYZ" ¥d'�/L '""'10'(<l)Fina

Ii .• .. : ..
• .
.
;
• • · tI:l:�il;)itg�pfl!o'fo:rWhich .tl;Ie transist9r Cont;tti�ts: (b}In ierws of: V&; :{ind 'the range. ofYB'forwruch the' ··
:r. "ci " , . .•.•.• tf<U1�ist6i:1 9per�t�s .ih tbe· tijode. regi6n,' (6) In terins 'Qf �;;,'fjnd.tlle r$ie .pfVnt9f whiCh .tlJeitran�i$tor•.
.
..
. .

. . .... .. ' ,·ilii '." i ,oper<lctes iu. satqration:� (d)'NegleCtihg,chatine14erigtli 1)iodW.,atiOu{i.e:; ·IlS�JlmillgX ""'0);:fltuJ tlie yal'aes
... . ..
.. . .
.

'.ib�:IVovl �diV(i illId the corresp()ndingxa�ge{)! VpJo.opeJ;ate the transistorjn th� sahlrati�nmode With
''In �\15.jlA .(e)Jf X,;= ::,"0:04 V�l, fihd tht:lvalu� ofr" corresponding tq tM over<ltive voltage determineq
.

iin {d). (f}iFQr.A � -0.02 .)11

·

.andfor tlfe ya1ue9fV()v�etermined in (d}, fll1diIDiat.VD=+3 V arid atVn ==

' OV; hence; calcllillte the val ue
.. . . o! tIie'.
apparent outputresisfancein' satllfation. Compare to the.yalue
. . .
.
. .'

f6uridin (e);

VD FJGURE E4.B
Ans. (a) Vo ::::; ' +4 Y; (b) VD � VG + l; (c) VD :; VG + l ; (d). 0.5 V, 3.5 V, ::::; 4.5 V; (e) 0.67 M.!.1�
(f) 7 8 p.A, 82.5 f.1A, 0.67 M.!.1 (same).

4.2.5 The Role of the Substrate-The Body Effect

In many applications the source tenninal is connected to the substrate (or body) terminal B,
which results in the pn junction between the substrate and the induced channel (see Fig. 4.5)
having a constant zero (cutoff) bias. In such a case the substrate does not play any role in
circuit operation and its existence can be ignored altogether.
In integrated circuits, however, the substrate is usually common to many MOS transistors.
In order to maintain the cutoff condition for all the substrate-to-channel junctions, the sub­
strate is usually connected to the most negative power supply in an NMOS circuit (the most
positive in a PMOS circuit). The resulting reverse-bias voltage between source and body
(VSB in an n-channel device) will have an effect on device operation. To appreciate this fact,
consider an NMOS transistor and let its substrate be made negative relative to the source.
The reverse bias voltage will widen the depletion region (refer to Fig. 4.2) . This in turn
reduces the channel depth. To return the channel to its former state, VGS has to be increased.
The effect of VSB on the channel can be most conveniently represented as a change in the
threshold voltage Vt. Specifically, it has been shown that increasing the reverse substrate
bias voltage VSB results in an increase in Vt according to the relationship

(4.33)
where Vto is the threshold voltage for VSB "" 0; </} is a physical parameter with (2</>/) typically
0.6 V; r is a fabrication-process parameter given by

r
J2qNAcs
-'---=--;.:.-.::
""
(4.34)
Cox
 I" !
I

!!
II

4.2 C U R R E NT-VOLTA G E C H A RACTER I ST I C S 259

- 19
where q is the electron charge ( 1 .6 x 10 C), NA is the doping concentration of the p-type sub­
is the permittivity of silicon ( 1 1 .780 1 1 .7 x 8.854 10- 14
= 1 .04 X 10-12 FJcm),
The parameter y has the dimension of JV and is typically 0.4 y lf2. Finally, note that
, and C x
strate s =

Eq. (4. 33) applies equally well for p-channel devices with VSB replaced by the reverse bias
of the substrate, VBS (or, alternatively, replace VSB by I VsBI) and note that y is negative. In
evaluating Y, NA must be replaced with ND, the doping concentration of the n well in
which the PMOS is formed. For p-channel devices, 2cfJf is typically 0.75 V, and y is typically
-0.5 lf2.
y
Equation (4.33) indicates that an incremental change in VSB gives rise to an incremental
change in VI' which in tum results in an incremental change in iD even though VCS might
have been kept constant. It follows that the body voltage controls iD; thus the body acts as
another gate for the MOSFET, a phenomenon known as the body effect. Here we note that
the parameter yis known as the body-effect parameter. The body effect can cause consid­
erable degradation in circuit performance, as will be shown in Chapter 6.

hNMOStransistorhaiVtO � b.8 .·SCP;;= (}.7t�a:dr�6.4 V1l2. Firid ·�.

Ans: L23 V

4.2.6 Tem pe rature Effects

Both Vt and k' are temperature sensitive. The magnitude of VI decreases by about 2 mY for
every 1 °C rise in temperature. This decrease in I Vtl gives rise to a corresponding increase in
drain current as temperature is increased. However, because k' decreases with temperature
and its effect is a dominant one, the overall observed effect of a temperature increase is a
decrease in drain current. This very interesting result is put to use in applying the MOSFET
in power circuits (Chapter 14).

4.2.7 B reakdown and I n put Protection

As the voltage on the drain is increased, a value is reached at which the pn junction between
the drain region and substrate suffers avalanche breakdown (see Section 3.7.4). This break­
down usually occurs at voltages of 20 Y to 150 Y and results in a somewhat rapid increase
in current (known as a weak avalanche). ,
Another breakdown effect that occurs at lower voltages (about 20 Y) in modem devices
is called punch-through. It occurs in devices with relatively short channels when the drain
voltage is increased to the point that the depletion region surrounding the drain region
extends through the channel to the source. The drain current then increases rapidly. Normally,
punch-through does not result in permanent damage to the device.
Yet another kind of breakdown occurs when the gate-to-source voltage exceeds about
30 Y. This is the breakdown of the gate oxide and results in permanent damage to the
device. Although 30 Y may seem high, it must be remembered that the MOSFET has a very
high input resistance, and a very small input capacitance, and thus small amounts of static
charge accumulating on the gate capacitor can cause its breakdown voltage to be exceeded.
260 C H A P T E R 4 M O S F I E LD-E F F ECT TRA N S I STO RS ( M O S F ETs)

To prevent the accumulation of static charge on the gate capacitor of a MOSFET, gate­
protection devices are usually included at the input terminals of MOS integrated circuits.
The protection mechanism invariably makes use of clamping diodes.

4.2.8 Summary
For easy reference we present in Table 4.1 a summary of the current-voltage relationships
for enhancement-type MOSFETs.

NMOS Transistor

Symbol:
D D

G cr------i l-----o B G cr------i

s VSB = 0
Overdrive voltage:
Vov = VGS - V,
VGS= Vt + Vov
Operation in the triode region:
iii Conditions:
(1) vGs ;::: V, <=> vov ;::: 0
(2) VGD ;::: Vt <=> VDS ::; vGS - V, <=> VDS ::; Vov
i- v Characteristics:
iD = ,unCox Z [evGS - Vt)VDS - � v;sJ
iii

Operation in the saturation region:

iii Conditions:
(1) VGS ;::: V, <=> vov ;::: 0
(2) VGD ::; V, VDS � vGS V, VDS ;::: Vov
<=> - <=>

iii i- v Characteristics:
iD = 2! ,unCox.!!:L ( vGS - Vi( 1 + AVDS)
 4.2 C U R R E NT-VO LTAG E C H A RACT E R I ST I C S 261

III Large-signal equivalent circuit model:

where
1 W 2
ID = 2J.1n Cox L ( VGS - V,)
Threshold voltage:

V, = VtO + yU'-"
2 --:- V-SBI---' - JEF;)
¢f-+---;-I=
Process parameters :

Cox = cox/tox (F/m2 )

k� = J.1n Cox (A/V2 )
V� = ( VA /L) (Vim)
A = ( l I VA ) (V-I )
y = J2 qNA c/ Cox (V I I2)
Constants:
co= 8.854 x 10-12 Flm
cox= 3.9co = 3.45 x 1O-1 1 Flm
cs= 1 1 .7£0 1 .04 x 1 0-10 Flm
=

q = 1 . 602 X 1 0- 19 C

PMOS Transistor
Symbol:
s s

G o-j l-----o B G o--N

D D
VSB = 0
Overdrive voltage:
Vo v = VGS - V,
VSG = i V ,l + I Vovl

(Continued)
262 CHAPTER 4 MOS F I E L D- E F F ECT TRA N S ISTORS (MOS F ETs)

i-v Characteristics:
Same relationships as for NMOS transistors except:
11 Replace,um k� , andNA with ,up' k; , andND, respectively.
/I V" VtO, VA' ?c' and yare negative.
/I Conditions for operation in the triode region:
(1) VCS ;<:; V, ¢=>vov ;<:; 0 ¢=>
vsc ;:: / V,I

(2) VDC ;:: I V,I ¢=>VDS ;:: vcs V,- ¢=> VSD ;<:; I vovl

11 Conditions for operation in the saturation region:

(1) VCS ;<:; VI ¢=> vov ;<:; 0 ¢=>vSG ;:: /VII

(2) vDC ;<:; I VII ¢=> vDS ;<:; vcs V, - ¢=> VSD ;:: I vov l

/I Large-signal equivalent circuit model:

S
+ +

'iHY���-i::f+---'---o
�
D
iD

where

4.3 M OS FET C I R C U I TS AT D C
Having studied the current-voltage characteristics of MOSFETs, we now consider circuits in
which only dc voltages and currents are of concern. Specifically, we shall present a series of
design and analysis examples of MOSFET circuits at dc. The objective is to instill in the
reader a familiarity with the device and the ability to perform MOSFET circuit analysis both
rapidly and effectively.
In the following examples, to keep matters simple and thus focus attention on the
essence of MOSFET circuit operation, we will generally neglect channel-length modulation;
that is, we will assume A = O. We will find it convenient to work in terms of the overdrive
voltage; Vov = Ves Vt· Recall that for NMOS, Vt and Vov are positive while, for PMOS, Vt
and Vav are negative. For PMOS the reader may prefer tb write Vse = I Vesl
-

I Vtl I Vavl .
= +
 4.3 M OS FET C I RC U ITS AT DC 263

Design the circuit of Fig. 4.20 s o that the transistor operates at ID 0.4 rnA and VD +0.5 V . The
NMOS transistor has V, 0.7 V, fLnCox = 1 00 fLAJV2 , L 1 fLm, and W 32 fLm. Neglect the
= =

= = =

channel-length modulation effect (i.e., assume that /L 0). =

VDD = + 2.5 V

Vss = - 2.5 V FIG U RE 4.20 Circuit for Example 4.2.

Solution
Since VD 0.5 V is greater than Vo , this means the NMOS transistor is operating in the saturation
=

region, and we use the saturation-region expression of iD to determine the required value of Vos,
1 W 2
ID =
"2fLnCox L ( V os - VI)
Substituting Vos - V, = Vav' !D = 0.4 rnA = 400 ,uA, 11,Pox = 100 fLAN2, and W/ L = 321 1 gives

1 32 2
400 = - x 100 x � Va v
2 1.

which results in

Va v = 0.5 V
Thus,

Vos =
V, + Va v = 0.7 + 0.5 = l .2 V
Referring to Fig. 4.20, we note that the gate is at ground potential. Thus the source must be at - l .2 V,
and the required value of Rs can be determined from

- Vs - Vss
Rs -
ID
= - l .2 - (-2.5)
= 3.25 kQ
0.4
To .establish a dc voltage of +0.5 V at the drain, we must select RD as follows:

- VDD - VD
RD -
ID
2.5 - 0.5
= 5 kQ
0.4
264 C H A P T E R 4 M O S F I E L D - E F F ECT TRA N S I STORS ( M O S F ETs)

D4.10 Fig . 4.20 for the following case� VDD == -Vss == 2.5 V, � = 1 V, j..l,,cox = 60 pAl
V2 , WIL :::; · 1 20 f.1m/] pm, ID = 0.3 rllA, and Vzj
Redesign ilie circllit of
+ 0.4 V.
ill ; RD ;=: 7 ill
==

Ans. Rs = 3.3

Design the circuit in Fig. 4.21 to obtain a current ID of SO j..tA Find the value required for R , and
find the dc voltage YD' Let the NMOS transistor have Vt == 0.6 V, f.1n Cox 200 f.1AIV2 ,==

L == O.S f.1m, and W == 4 f.1m. Neglect the channel-length modulation effect (i.e., assume It == 0 ).

VDD = +3V

FIGURE 4.21 Circuit for Example 4.3.

Solution
Because VDC == 0, VD == Vc and the FET is operating in the saturation region. Thus,
"2f.1n Cox L ( Vcs - Vt )
1 W 2
ID ==

"2 f.1n Cox L VOv

1 W 2
==

from which we obtain Vov as

Vov ==
f.1n Cox ( WIL )

2 X SO
200 X (4/0.S)
== 0.4 V

Thus,

Vcs == Vt + Vov == 0.6 + 0.4 == 1 V

and the drain voltage will be
VD == Vc == +1 V
The required value for R can be found as follows:

R
VDD - VD
ID
==

3-1
== == 25 kQ
O.OSO
 4.3 M OS F ET C I RCU ITS AT DC 265

FIG U R E E4.1 2

Ans. 80 /LA; + 1 .4 V

Design the circuit in Fig. 4.22 to establish a drain voltage of 0.1

V . What is the effective resistance
between drain and source at this operating point? Let Vt = 1
V and k�( W/L ) = 1
mA/V2 .

VDD = +5 V

VD = +0.1 V
FIGURE 4.22 Circuit for Example 4.4.

Solut ion
Since the drain voltage is lower than the gate voltage by 4.9V and V t = 1 V , the MOSFET is
operating in the triode region. Thus the current ID is given by

ID = k� .zT( VGS - Vt) VDs - � V�sJ

ID = 1 X [(5 - 1) X O. l - � X O.OlJ
= 0. 3 95rnA
266 C H A P T E R 4 M OS F I E LD-E F F E CT TRA N S I STORS ( M O S F ETs)

The required value for RD can be found as follows:

In a practical discrete-circuit design problem one selects the closest standard value available
for, say, 5% resistors-in this case, 1 2 see Appendix
kQ; Since the transistor is operating in
G.
the triode region with a small VDS, the effective drain-to-source resistance can be determined as
follows:

. ·;;13··��i!'�icircuit.������1�<t:.��:���:��f;v ls ctOUltll�(l�

Ans. Q.imA;o.05V . .

Analyze the circuit shown in Fig. 4.23(a) to determine the voltages at all nodes and the currents
through all branches. Let Vt 1 V and k� (W/L ) mA/V2 . Ncglect the channel-length
modulation effect (i.e., assume /L = 0).
= = 1

VDD = + lO V + 10 V

RGI = lO MO l O MO 6 kO

+ 5 V $-------1
RG2 = lO MO Rs = 6 kO l O MO 6 kO

(a) (b)

FIGURE 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.
 4.3 M O S F ET C I R C U ITS AT DC 267

sol uti on
i s zero, the voltage at the gate is simply determined by the voltage divider
Since the gate current
rs,
formed by the two l O-MQ resisto

VG = VDDRG2RG2RGl = 10 x 10 10+
+
---

10
= +S V

With this positive voltage at the gate, the NMOS transistor will be turned on. We do not know,
however, whether the transistor will be operating in the saturation region or in the triode region.
We shall assume saturation-region operation, solve the problem, and then check the validity of
our assumption. Obviously, if our assumption turns out not to be valid, we will have to solve the

Refer to Fig. 4.23(b). Since the voltage at the gate is S V and the voltage at the source is
problem again for triode-region operation.

ID (rnA) x 6 (kQ) = 61D ' we have

Thus ID is given by

ID = �k� �(VGS- vi
= 2 X l x (S - 6ID - l )
1 2
which results in the following quadratic equation in ID:

This equation yields two values for ID: 0.89 rnA and O.S rnA. The first value results in a source
voltage of 6 x 0.89 =S.34, which is greater than the gate voltage and does not make physical
sense as it would imply that the NMOS transistor is cut off. Thus,

ID = O.S mA
VS = O.S x 6 = +3 V
VGS = S-3 = 2V
VD = 1 0 - 6 X O.S \= +7 V
Since VD VG - Vt,
> the transistor is operating in saturation, as initially assumed.

Ans. 12 kQ
D4;15 4.23 for the following requirements: VDD = +S V, ID == .032 rnA, Vs =
Rede sign the circuit of Fig.
1.6 V, VD =:
3.4 V, with a l-JiA current through the voltage divider RGl, . RG2• Assume the same
MOSFET as in Example 4.S.
Ans. RGl = 1.6 MQ; RG2 = 3.4 MQ, Rs = RD ;:: S kQ
268 C H A P T E R 4 M O S F I E L D - E F F ECT TRA N S I STO RS ( M O S F ETs)

k;( WIL)
Design the circuit of Fig. 4.24 so that the transistor operates in saturation with ID = 0.5 rnA and
VD = +3 V. Let the enhancement-type PMOS transistor have Vt = -1 V and
1 mAN2 . Assume A = O. What is the largest value that RD can have while maintaining saturation_
==

region operation?

VDD = +5 V

VD = +3 V

FIGURE 4.24 Circuit for Example 4.6.

Solution
Since the MOSFET is to be in saturation, we can write

ID = � k;�( VGS- vi
_- 2lep WL v2ov
Substituting ID = 0.5 rnA and k;WIL 2
= 1 rnA/V and recalling that for a PMOS transistor Vov
is negative, we obtain

Vo v = -1 V

GS
and
V = Vt + Vov = - 1 - 1 = -2 V
Since the source is at +5 V, the gate voltage must be set to +3 V. This can be achieved by
the appropriate selection of the values of RGJ and RG2. A possible selection is RGl = 2 MQ and
RG2 = 3 MQ.
The value of RD can be found from

Vtl
- = 6 kQ
0.5

Saturation-mode operation will be maintained up to the point that VD exceeds VG by I ; that is, until

VDm"" = 3+1 = 4V

This value of drain voltage is obtained with RD given by

RD = -
4 = 8 kQ
0.5
 4.3 M O S F ET C I RCU ITS AT DC 269

Th eNMOS PMOS
and 2transistors in theV circuit of Fig. 4.25(a) are matched with k�(WJLn) =
k '( Wp p )
/L = 1 /V and Vtn
rnA - ip = 1 V. Assuming
= 0 for both devices, find the
JL =
p . . as well as the voltage for -- 0 V, +2.5 V, and -2. 5 V.
VI
entsIDN and IDP, Va,
drain curr
+2.S V +2.5 V

Qp Qp
t iDP t IDP
VI
' PDN
Va OV Va
t IDN
lO kil l O kil

- -
- 2.S V - 2.S V
(a) (b)
+2.S V

+2.5 V �
r--- --Q -+- Va L---_...._
... -c va

-2.S V
(c) (d)
FIGURE 4.25 Circuits for Example 4.7.

Solution
Figure 4.25(b) shows the circuit for theI case = 0 V. We note that since Q and Qp are perfectly
matched and are operating at equal VGsl (2.5 V), the circuit
VI N
IV is symmetrical, which dictates that
va = 0 V. Thus both QN and Qp are operating with D GI 0 and, hence, in saturation. The
=

drain currents can now be found from 2

ID P = IDN � X I X (2.5 - 1)
=

= 1.125 rnA

Next, we consider the circuit with +2. 5 V. Transistor Qp will have a VGS of zero and
VI =
thus will be cut off, reducing the circuit to that shown in Fig. 4.25(c). We note that will be Va
270 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

negative, and thus VGD will be greater than V" causing QN to operate in the triode region. For
simplicity we shall assume that VDS is small and thus use

IDN == k� ( Wn /Ln )(VGS - Vt) VDS

1 [2.5 - (-2.5) 1 ] [ va - (-2.5) ]
-

From the circuit diagram shown i n Fig. 4.25(c), w e can also write
0 - va
IDN (rnA) -_
10 (kQ)
These two equations can be solved simultaneously to yield
IDN = 0.244 rnA Va = -2.44 V
Note that VDS -2.44 - (-2.5) = 0.06 V, which is small as assumed.
=
Finally, the situation for the case VI -2.5 V [Fig. 4.25(d)] will be the exact complement
=

of the case vI + 2.5 V: Transistor QN will be off. Thus IDN 0, Qp will be operating in the
= =
triode region with IDP = 2.44 rnA and Va +2.44 V. =

-2.5 V
FIGURE E4. 1 6

4.4 T H E M OS F ET AS A N A M P L I F I E R A N D AS A SWITCH
6
In this section we begin our study o f the use o f MOSFETs in the design of amplifier circuits.
The basis for this important MOSFET application is that when operated in the saturation region,
the MOSFET acts as a voltage-controlled current source: Changes in the gate-to-source voltage

6 An introduction to amplifiers from an external-terminals point �f view was presented in Chapter 1

(Sections 1 .4 and 1 :5), and it would be helpful for readers who are not familiar with basic amplifier
concepts to review some of this material before proceeding with the study of MOS amplifiers.
 4 . 4 T H E M O S F ET AS AN A M P LI F I E R A N D AS A SWITCH 271

;�
v give rise to changes in the drain current iD• Thus the saturated MOSFET can be used to
lement a transconductance amplifier (see Section 1.5). However, since we are interested in
line amplification-that is, in amplifiers whose output signal (in this case, the drain current iD)
ar
is linearly related to their input signal (in this case, the gate-to-source voltage ves)-we will
have to find a way around the highly nonlinear (square-law) relationship of iD to Ves.
The technique we will utilize to obtain linear amplification from a fundamentally non­
lin ar device is that of dc biasing the MOSFET to operate at a certain appropriate Ves and a
e
corresponding ID and then superimposing the voltage signal to be amplified, Vgs' on the de
bias voltage Yes· By keeping the signal Vgs "small," the resulting change in drain current, id,
can be made proportional to Vgs ' This technique was introduced in a general way in Section 1 .4
and was applied in the case of the diode in Section 3.3.8. However, before considering the
small-signal operation of the MOSFET amplifier, we will look at the "big picture": We will
study the total or large-signal operation of a MOSFET amplifier. We will do this by deriving
the voltage transfer characteristic of a commonly used MOSFET amplifier circuit. From the
voltage transfer characteristic we will be able to clearly see the region over which the tran­
sistor can be biased to operate as a small-signal amplifier as well as those regions where it
can be operated as a switch (i.e., being either fully "on" or fully "off"). MOS switches find
application in both analog and digital circuits.

4.4 .1 large-Signal Operation-The Tr�nsfer Characteristic

Figure 4.26(a) shows the basic structure (skeleton) of the most commonly used MOSFET
amplifier, the common-source (CS) circuit. The name common-source or grounded-source

Triode � Saturation
I

VGS > �B

VGS = �B

.���� __
____
------------
----------- V� < �B

Q
�';-"4-....-----""';:�---------
. VGS = �Q
Load-line
slope - lIRD
=

i__-'---,�--------i----";:;"'�---- VGS =
.•.

A
o Voc VOB =
"lE - V,

(a) (b)

FIGURE 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine
(a).
the transfer characteristic of the amplifier in
272 CH APTE R 4 M O S F I ELD- E F F ECT TRA N S I STORS ( M O S F ETs)

Q l� Ql in � Q l in
cutoff I saturation I triode region
VDD ....-
. .......... I
X

:
AI I
I Slope at Q = voltage gain
I
I
I I
I I
I I
- - i - -
----'I:----,'---\---�- Time
I
I I
I

:
I
I
I
I I I I
I I I I
_ _ l _ --+ --I- --+
I I I I
I I I I I
I I I I I c
�c ��JC����
��-�-�-�- �-�- �-�-
� -�-
��=i ____ �
__

I "1B = VOB + Vr
I
,

Time

(c)

FIGURE 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.

circuit arises because when the circuit is viewed as a two-port network, the grounded source
terminal is common to both the input port, between gate and source, and the output port,
between drain and source. Note that although the basic control action of the MOSFET is that
changes in Vcs (here, changes in VI as Vcs VI) give rise to changes in iD, we are using a resistor
==

RD to obtain an output voltage Va,

(4.35)

In this way the transconductance amplifier is converted into a voltage amplifier. Finally,
note that of course a dc power supply is needed to tum the MOSFET on and to supply the
necessary power for its operation.
We wish to analyze the circuit of Fig. 4.26(a) to determine its output voltage Va for vari­
ous values of its input voltage Vb that is, to determine the voltage transfer characteristic of
 4.4 T H E M O S F ET AS AN A M P LI F I E R A N D A S A SWITCH 273

. For this purpose, we will a�su�e VI to b e in th� range of 0 to VDD. �o

the CS amplifier . . . .
greater insight into the operatIOn of the CIrCUlt, we WIll denve Its transfer charactenstlc
obtain
in tWO ways: graphically and analytically.

4.4.2 G ra p hica l Derivation of the Transfer Characteristic

'
The operation of the common-source circuit is governed by the MOSFET s iD-VDS charac­
teristics and by the relationship between iD and VDS imposed by connecting the drain to the
power supply VDD via resistor RD, namely

(4.36)

or, equivalently,

(4.37)

Figure 4.26(b) shows a sketch of the MOSFET' s iWVDS characteristic curve� superimposed
on which is a straight line representing the iD-VDS relationship of Eq. (4.37). Ooserve that the
straight line intersects the vDs-axis at VDD [ since from Eq. (4.36) VDS VDD at iD == 0] and has
==

a slope of - 1 /RD . Since RD is usually thought of as the load resistor of the amplifier
(i.e., the resistor across which the amplifier provides its output voltage), the straight line in
Fig. 4.26(b) is known as the load line.
The graphical construction of Fig. 4.26(b) can now be used to determine Va (equal to
VDS) for each given value of VI (Ves VI). Specifically, for any given value of Vb we locate
==

the corresponding iD-VDS curve and find Va from the point of intersection of this curve with
the load line.
Qualitatively, the circuit works as follows: Since Ves == Vb we see that for VI < V I ' the
transistor will be cut off, iD will be zero, and Va VDS == VDD. Operation will be at the point
==

labeled A. As VI exceeds Vt, the transistor turns on, iD increases, and Va decreases. Since Va
will initially be high, the transistor will be operating in the saturation region. This corre­
sponds to points along the segment of the load line from A to B . We have identified a partic­
ular point in this region of operation and labeled it Q. It is obtained for Ves VIQ and has the
==

==
coordinates VaQ VDSQ and IDQ .
Saturation-region operation continues until Va decreases to the point that it is below VI
by Vt volts. At this point, VDS == Ves - Vt, and the MOSFET enters its triode region of opera­
tion. This is indicated in Fig. 4.26(b) by point B, which is at the intersection of the load line
and the broken-line curVe that defines the boundary between the saturation and the triode
regions. Point B is defined by

For VI > VIE, the transistor is driven deeper into the triode region. Note that because the
characteristic curves in the triode region are bunched together, the output voltage decreases
slowly towards zero. Here we have identified a particular operating point C obtained for
==
VI VDD. The corresponding output voltage Vac will usually be very small. This point-by­
point determination of the transfer characteristic results in the transfer curve shown in
Fig. 4.26(c). Observe that we have delineated its three distinct segments, each corresponding
. to one of the three regions of operation of MOSFET Qj. We have also labeled the critical
points of the transfer curve in correspondence with the points in Fig. 4.26(b).
--

CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STO R S ( M O S F ETs)

4.4.3 Operation as a Switch

When the MOSFET is used as a switch, it is operated at the extreme points of the transfer
curve. Specifically, the device is turned off by keeping VI < Vt resulting in operation some­
where on the segment XA with Vo = VDD• The switch is turned on by applying a voltage
close to VDD, resulting in operation close to point C with Vo very small (at C, Vo = Vod . At
this juncture we observe that the transfer curve of Fig. 4.26(c) is of the form presented in
Section 1.7 for the digital logic inverter. Indeed, the common-source MOS circuit can be
used as a logic inverter with the "low" voltage level close to 0 V and the "high" level close
to VDD• More elaborate MOS logic inverters are studied in Section 4. 10.

4.4.4 Operation as a linear Amplifie r

T o operate the MOSFET a s an amplifier w e make use of the saturation-mode segment of the
transfer curve. The device is biased at a point located somewhere close to the middle of the
curve; point Q is a good example of an appropriate bias point. The dc bias point is also
called the quiescent point, which is the reason for labeling it Q. The voltage signal to be
amplified Vi is then superimposed on the dc voltage VIQ as shown in Fig. 4.26(c). By keeping
Vi sufficiently small to restrict operation to an almost linear segment of the transfer curve,
the resulting output voltage signal Vo will be proportional to Vi' That is, the amplifier will be
very nearly linear, and Vo will have the same waveform as Vi except that it will be larger by a
factor equal to the voltage gain of the amplifier at Q, Av, where

(4.38)

Thus the voltage gain is equal to the slope of the transfer curve at the bias point Q. Observe
that the slope is negative, and thus the basic CS amplifier is inverting. This should be also
evident from the waveforms of Vi and Vo shown in Fig. 4.26(c). It should be obvious that if
the amplitude of the input signal Vi is increased, the output signal will become distorted
since operation will no longer be restricted to an almost linear segment of the transfer
curve.
We shall return to the small-signal operation of the MOSFET in Section 4.6. For the
time being, however, we wish to make an important observation about selecting an appro­
priate location for the bias point Q. Since the output signal will be superimposed on the dc
voltage at the drain VOQ or VDSQ, it is important that VDSQ be of such value to allow for the
required output signal swing. That is, VDSQ should be lower than VDD by a sufficient amount
and higher than VOB by a sufficient amount to allow for the required positive and negative
output signal swing, respectively. If VDSQ is too close to VDD, the positive peaks of the out­
put signals might "bump" into VDD and would be clipped off, because the MOSFET would
tum off for part of the cycle. We speak of this situation as the circuit not having sufficient
"headroom." Similarly, if VDSQ is too close to the boundary of the triode region, the MOSFET
would enter the triode region for the part of the cycle near the negative peaks, resulting
in a distorted output signal. We speak of this situation as the circuit not having sufficient
"legroom." Finally, it is important to note that although we made our comments on the
selection of bias-point location in the context of a given transfer curve, the circuit designer
also has to decide on a value for RD, which of course determines the transfer curve. It
is therefore more appropriate when considering the location of the bias point Q to do
so with reference to the iD- VDS plane. This point is further illustrated by the sketch in
Fig. 4.27.
 4.4 T H E M O S F ET AS AN A M P LI F I ER A N D AS A SWITCH 275

-------��
VGS = .•.

FIGURE 4.27 Two load lines and corresponding bias points. Bias point QI does not leave sufficient room
for positive signal swing at the drain (too close to VDzj). Bias point Q2 is too close to the boundary of the tri­
ode region and might not allow for sufficient negative signal swing.

"
4.4.5 Analytical Expressions for the Transfer Characteristic
The i-v relationships that describe the MOSFET operation in the three regions-cutoff,
saturation, and triode-can be easily used to derive analytical expressions for the three seg­
ments of the transfer characteristic in Fig. 4.26(a).

The Cutoff-Region Segment, XA Here, VI :;; V I ' and Va = VDD ·

The Saturation-Region Segment, AQB Here, VI :2: Vt, and Va :2: VI - Vt• Neglecting
channel-length modulation and substituting for iD from

into

gives

(4.39)

We can use this relationship to derive an expression for the incremental voltage gain A v at a
bias point Q at which VI = VIQ as follows:
276 CHAPTER 4 M O S F I E L D- E F F ECT TRA N S I STO RS ( M O S F ETs)

Thus,

(4.40)

Observe that the voltage gain is proportional to the values of RD, the transconductance
parameter k� = fin Cox, the transistor aspect ratio W/L, and the overdrive voltage at the bias
point Vav = VIQ - Vt. _

Another simple and very useful expression for the voltage gain can be obtained by sub­
stituting VI = VIQ and Va = VaQ in Eq. (4.39), utilizing Eq. (4.40), and substituting VIQ - Vt ==

Vav. The result is

(4.4 1)

where VRD is the de voltage across the drain resistor RD; that is, VRD VDD -
= VaQ .
The end point of the saturation-region segment is characterized by

(4.42)

Thus its coordinates can be determined by substituting Va = VaB and VI = VIB in Eq. (4.39)
and solving the resulting equation simultaneously with Eq. (4.42).

The Triode-Region Segment, Be Here, VI � Vn and Va :S; VI - Vt• Substituting for iD by

the triode-region expression

into

gives

The portion of this segment for which Va is small is given approximately by

which reduces to

(4.43)

We can use the expression for rDS, the drain-to-source resistance near the origin of the iD-VDS
plane (Eq. 4.13),
 4.4 T H E M O S F ET AS A N A M P L I F I E R A N D AS A SWITCH 277

(4.4 3) to obtain
together with Eq.
rDS
Vo = VDD (4.44)
rDs + R D
---

which makes intuitive sense: For small Vo, the MOSFET operates as a resistance rDS (whose
value is determined by VI), which forms with RD a voltage divider across VDD• Usually,
and Eq. (4.44) reduces to
'DS � RD ,

(4.45)

'\

To make the above analysis more concrete we consider a numerical example. Specifically, con­
2
sider the CS circuit of Fig. 4.26(a) for the case k� ( W/L ) = 1 rnA/V , V, 1 V, RD = 1 8 kO, and
=

VDD = l O V.

Solution
First, we determine the coordinates of important points on the transfer curve.

(a) Point X:

Va = lOV

(b) Point A:

Va = lOV

(c) Point B: Substituting

VI = VIB = VOB + V,
= VOB + 1
and Vo = VOB in Eq. (4.39) results in
2
9 V OB + V OB - 10 = 0

which has two roots, only one of which makes physical sense, namely,

VOB = I V
Correspondingly,

VJB = 1 + 1 = 2 V

(d) Point C: From Eq. (4.43) we find

10
Voc = = 0.06 1 V
1 + 18 x 1 x ( l0 - 1)

which is very small, justifying our use of the approximate expression in Eq. (4.43).
Next, we bias the amplifier to operate at an appropriate point on the saturation-region seg­
ment. Since this segment extends from Vo = 1 V to 10 V, we choose to operate at VOQ = 4 V. This
point allows for reasonable signal swing in both directions and provides a higher voltage gain
,
than available at the middle of the range (i.e., at VOQ = 5.5 V). To operate at an output dc voltage
278 CHAPTER 4 M O S F I E L D-E F F ECT TRA N S I STO RS (MOS F ETs)

of 4 V, the dc drain current must be

ID =
VDD - VaQ = 10 - 4 =
0.333 rnA
R D 18

W e can find the required overdrive voltage Vav from

Va v = ) x�
2 .333
= 0.8 1 6 V

Thus, we must operate the MOSFET at a dc gate-to-source voltage

VGSQ = Vt + Vav = 1 .8 1 6 V
The voltage-gain of the amplifier at this bias point can be found from Eq. (4.40) as

Av = -18 x 1 x ( 1 .8 1 6 - 1 )
= - 14.7 VIV

To gain insight into the operation of the amplifier we apply an input signal Vi of, say, 1 50 mV
peak-to-peak amplitude, of, say, triangular waveform. Figure 4.28(a) shows such a signal super­
imposed on the dc bias voltage VGSQ 1 .8 1 6 V. As shown, VGS varies linearly between 1 .741 V
=

and 1 . 891 V around the bias value of 1 .8 1 6 V. Correspondingly, iD will be

At vGS = 1 .741 V, iD = � x 1 x ( 1 .741 - 1 l = 0.275 rnA

At vGS = 1 .8 1 6 V, iD = � x 1 x ( 1 . 8 1 6 - d = 0.333 rnA
At vGS = 1 .891 V, iD = � x 1 x ( 1 .891 _ 1 ) 2 = 0.397 rnA

Note that the negative increment in iD is (0.333 - 0.275) = 0.058 rnA while the positive increment
is (0.397 - 0.333) 0.064 rnA, which are slightly different, indicating that the segment of the
=

iD- vGS curve (or, equivalently, of the va- vI curve) is not perfectly linear, as should be expected.
The output voltage will vary around the bias value VaQ = 4 V and will have the following extremities:

At vGS = 1 .74 1 V, iD = 0.275 rnA and va = 10 - 0.275 x 18 = 5.05 V

,

At vGS = 1 .891 V, iD = 0.397 rnA, and va = 10 - 0.397 x 1 8 = 2 .85 V

Thus, while the positive increment is 1 .05 V, the negative excursion is slightly larger at 1 . 1 5 V,
again a result of the nonlinear transfer characteristic. The nonlinear distortion of Va can be
reduced by reducing the amplitude of the input signal.
Further insight into the operation of this amplifier can be gained by considering its graphical
analysis shown in Fig. 4.28(b). Observe that as VGS varies, because of Vi' the instantaneous
operating point moves along the load line, being at the intersection of the load line and the iD-VDS
curve corresponding to the instantaneous value of VGS'
We note that by biasing the transistor at a quiescent point in the middle of the saturation
region, we ensure that the instantaneous operating point always remains in the saturation region,
and thus nonlinear distortion is minimized. Finally, we note that in this example we carried out
our calculations to three decimal digits, simply to illustrate the concepts involved. In practice,
this degree of precision is not justified for approximate manual analysis.
 Vcs == VI t
1.8 91 V ----

1
1--------- - -
150 mV
V"Q == 1.81 6 V - - - - -

1 .74 1 V - - - -- _ _ _ _ _ _ 1 _

1 Time
(a)

iD (rnA)

0.6

Vcs == 1 .89 1 V

Vcs == 1.816 V
Vcs = 1 .741 V ,.. Time

Vcs = 1 .5 V

/
/
o 2 3 4 5 6 7 8 9
I
10 Va (V)
I
I
I
I
I
I

i
I

I
t
Time
1 0( > 1 0( ... 1
1.15 V 1 .05 V

(b)
FIG UR E 4.2 8 Example 4.8 .

279
280 C H A P T E R 4 M O S F I E L D-E F F ECT TRA N S I STORS ( M O S F ETs)

4.4.6 A Final Remark on Biasing

In the above example, the MOSFET was assumed to b e biased at a constant VGS of 1.816 V.
Although it is possible to generate a constant bias voltage using an appropriate voltage­
divider network across the power supply VDD or across another reference voltage that may
be available in the system, fixing the value of VGS is not a good biasing technique. In the next
section we will explain why this is so and present superior biasing schemes.
"" � �",'" � ''''' "'� �': <-

.
>- ' " � � >< ,,- _c � �--"' n: � .

/': �:
EXER€ISES "
"
. _
. .. , . �

. · · \fig,.;4.2�(¢)(eaJ. G�'Ve �:�i:l YiXlu�s of·VjQ; ;YJkI VO'Q;. and .Vas.. (b) Use·.tIie! YiUrIe$ in (a) t() .�eter;rllinil- die • . ·
• llirgesj aUowableyalueofthe negativepeak·of th� ()utputsIgnal and the llla.ghitude ofthe 'c()rr€l>ponding .
..
'" . . p()sitive peak of tbeinptit signaLDisregaid distortion causedby thesquare�law MQSFETcIiaracteristic.
(c) Re�at (b) for the positive�output peak and the correspondiug negative-input peak. (d) From the
results of(b) and (c), what isthe maxirimll amplitude of a sine wave that can be applied at the input and
the corresponding output amplitude... WIiat value ofgain do tbese ampIitudes imply? Whyis it different
:fr()m the 14.7 \TN found ·in Example 4.81
.

Ans. (a) 1 .816 V,2 V, 4 V, J V; (b) 3 V, 0. 1 84 V;(c) 6V, O,816V; (d) 0.184 V, 3 V, 16.3 V/V,
'

because of the nonlinear transfer characteristk

4018 Derive the voltage-gain expression inEq. (4.41). Us\,? the expression to verify the gain value found in
Example 4.8.

4.5 B I AS I N G I N M O S A M P L I FI ER C I RCU I TS
As mentioned in the previous section, an essential step in the design of a MOSFET amplifier
circuit is the establishment of an appropriate dc operating point for the transistor. This is the
step known as biasing or bias design. An appropriate dc operating point or bias point is char­
acterized by a stable and predictable dc drain current ID and by a dc drain-to-source voltage
VDS that ensures operation in the saturation region for all expected input-signal levels.

4.5. 1 Biasing by Fixing VGS

The most straightforward approach to biasing a MOSFET is to fix its gate-to-source voltage
VGS to the value required to provide the desired ID• This voltage value can be derived from
the power supply voltage VDD through the use of an appropriate voltage divider. Alternatively,
it can be derived from another suitable reference voltage that might be available in the system.
Independent of how the voltage VGS may be generated, this is not a good approach to biasing
a MOSFET. To understand the reason for this statement, recall that

ID = 2,'l'
1
n Cox VVL ( VGS - Vt)2
and note that the values of the threshold voltage 11;, the oxide-capacitance and (to a lesser Cox ,
extent) the transistor aspect ratio VV/ L vary widely among devices of supposedly the same size
and type. This is certainly the case for discrete devices, in which large spreads in the values of
these parameters occur among devices of the same manufacturer' s part number. The spread is
also large in integrated circuits, especially among devices fabricated on different wafers and
certainly between different batches of wafers. Furthermore, both Vt and fln depend on tempera­
ture, with the result that if we fix the value of VGS, the drain current ID becomes very much
temperature dependent.
 A.S B I A S I N G I N M O S A M P L I F I E R C I R C U ITS 281

Device 2

FIGURE 4.29 The use of fixed bias (constant VGs) can result in a large variability in the value of [D'
Devices 1 and 2 represent extremes among units of the same type.

To emphasize the point that biasing by fixing Ves is not a good technique, we show in
Fig. 4.29 two iD-Ves characteristic curves representing extreme values in a batch of MOSFETs
of the same type. Observe that for the fixed value of Ves, the resultant spread in the values of
the drain current can be substantial.

4.5.2 Biasing by Fixing VG and Connecting a Resistance in the Source

An excellent biasing technique for discrete MOSFET circuits consists of fixing the dc volt­
age at the gate, Ve, and connecting a resistance in the source lead, as shown in Fig. 4.30(a).
For this circuit we can write
(4.46)

Now, if Ve is much greater than Ves, ID will be mostly determined by the values of Ve and
Rs· However, even if Ve is not much larger than Ves, resistor Rs provides negative feedback,
which acts to stabilize the value of the bias current ID' To see how this comes about consider
the case when ID increases for whatever reason. Equation (4.46) indicates that since Ve is
constant, Ves will have to decrease. This in turn results in a decrease in ID, a change that is
opposite to that initially assumed. Thus the action of Rs works to keep ID as constant as pos­
sible. This negative feedback action of Rs gives it the name degeneration resistance, a
name that we will appreciate much better at a later point in this text.
Figure 4.30(b) provides a graphical illustration of the effectiveness of this biasing scheme.
Here we show the iD�Ves characteristics for two devices that represent the extremes of a batch of
MOSFETs. Superimposed on the device characteristics is a straight line that represents the con­
straint imposed by the bias circuit-namely, Eq. (4.46). The intersection of this straight line
with the iD-Ves characteristic curve provides the coordinates (ID and Yes) of the bias point.
Observe that compared to the case of fixed Yes, here the variability obtained in ID is much
smaller. Also, note that the variability decreases as Ve and Rs are made larger (providing a
bias line that is less steep).
282 CHAPTER 4 M O S F I E L D - E F F ECT TRA N S I STO R S (MOS F ETs)

iD

Device 2 .
DeVlce 1
0 I
+ +
1m
VG
Rs ID l

0 VGS2 VGS1
- -

(a) (b)

VDD
VDD
RD

f\:
RG I
0

0
VG
� Rsig tID
Rc ,_
+
Rs
-
RG2 Vsig

- - - - - - Vss

(c) (d) (e)

F I G U R E 4.30 Biasing using a fixed voltage at the gate. Va. and a resistance in the source lead, Rs: (a) basic
arrangement; (b) reduced variability in ID; (e) practical implementation using a single supply; (d) coupling of a
signal source to the gate using a capacitor eel; (e) practical implementation using two supplies.

Two possible practical discrete implementations of this bias scheme are shown in
Fig. 4.30(c) and (e). The circuit in Fig. 4.30(c) utilizes one power-supply VDD
and derives
VG through a voltage divider (RCb RG2) .
Since = 0, Ic RGl RC2
and can be selected to be very
large (in the MQ range), allowing the MOSFET to present a large input resistance to a signal
source that may be connected to the gate through a coupling capacitor, as shown in
Fig. 4.30(d). Here capacitor Ccl blocks dc and thus allows us to couple the signal Vsig to
the amplifier input without disturbing the MOSFET dc bias point. The value of Cel should
be selected sufficiently large so that it approximates a short circuit at all signal frequencies
of interest. We shall study capacitively coupled MOSFET amplifiers, which are suitable
only in discrete circuit design, in Section 4.7. Finally, note that in the circuit of Fig. 4.30(c),
resistor RD
is selected to be as large as possible to obtain high gain but small enough to
allow for the desired signal swing at the drain while keeping the MOSFET in saturation at
all times.
When two power supplies are available, as is often the case, the somewhat simpler bias
arrangement of Fig. 4.30(e) can be utilized. This circuit is an implementation of Eq. (4.46), with
VC replaced by Vss.
Resistor Rc
establishes a dc ground at the gate and presents a high input
resistance to a signal source that may be connected to the gate through a coupling capacitor.
 4.5 B I AS I N G I N M O S A M P L I F I E R C I R C U ITS 283

the circuit of Fig. 4.30(c) to establish a dc drain current ID = 0.5 rnA The
It is required to design 2 .

MOSFE T is spec ified to have V, 1 V and k�WIL 1 rnA1V . For simplicity, neglect the
= =

channe l-len gth modulation effect (i.e., assume A 0). Use a power-supply VDD 1 5 V. Calculate
= =
the percenta ge change in the value of ID obtained when the MOSFET is replaced with another
unit h aving the same k�W I L but Vt 1 .5 V .
=

soluti on
As a rule of thumb for designing this classical biasing circuit, we choose RD and Rs to provide
one-third of the power-supply voltage VDD as a drop across each of RD, the transistor (i.e., VDS)
and Rs. For VDD = 1 5 V, this choice makes VD + 10 V and Vs = +5 V . Now, since ID is required
=

to be 0.5 rnA, we can find the values of RD and Rs as follows:

= 15 - 10 =
VD D - VD
RD = 10 kQ
ID 0.5

Rs = RVss 5
0.5
l O kQ

The required value of VGS can be determined by first calculating the overdrive voltage Vov from
= �k� ( WIL) V�v
ID

0.5 = � x 1 x V�v

which yields Vov = 1 V, and thus,

VGS =
VI + Vo v = 1 + 1 = 2V
Now, since Vs = +5 V, VG must be
VG= VS + VGS = 5 + 2 = 7 V
To establish this voltage at the gate we may select R Gl = S MQ and RGZ = 7 MQ. The final circuit
is shown in Fig. 4.3 1 . Observe that the dc voltage at the drain (+ 10 V) allows for a positive signal
swing of +5 V (i.e., up to VDD) and a negative signal swing of -4 V [i.e., down to (VG - V,)] .

VDD = + 1 5 V

I
O.5 � tI
-

S MD

VD = + l O V

VG = + 7 V 0--+----1

Vs = +5 V

7 MD Rs = lO kD

FIGURE 4.31 Circuit for Example 4.9.

284 C H A P T E R 4 M O S F I E LD-E F F ECT TRA N S I STO RS (MOS F ETs)

If the NMOS transistor is replaced with another having

found as follows:
V, :== l . 5 Y, the new value of In can be
(4.47)

VG VGS + InRs
:==

VGS + lOIn
7 :== (4.48)

Solving Eqs, (4.47) and (4.48) together yields

In :== 0.455 rnA

Thus the change in In is

!oJ n :== 0.455 - 0,5 :== -0.045 rnA

0 045
which is - , x 100 = -9 % change,
0,5

'i'L ��i�j;��it�t���� � ���t:�����; : ·

! �h:�c'ill1�o�:1�i;�6��!ft � i:h�:&W��<��:!�t;�X'j:c�
1 mA/V ,auci Z: , 'Wha,t1;sth:e perceI},tage change
anotherh�fvingYt�
:::': (J ;
L5 V? '
obt<tmedwhen th,e tramnstofls replaced :WItn:C ,....
. . . .. .
'
lUIiJ
' . ' . .
.
.

il.ns, V(fs = 2 Yi -":75% > , .., . . .. .

••
. .
. ,..
1}4�20 Design th;circuit Oflig.4.30(e)tq opetate �t ade drain cutrentof O:5 mA and Vn
. . . . "

=:; +2 V. Le� V, ;;'.1' Y,

.. . . .. . .. . .

k�WIL == l.mAIV , /1,= 0, V1JD =;; VSS == 5 V. USe standard 5%reslstor values (see Appendix G), and
.
givethe resulting values oUD, VD,and Vs.
"
. '. .

Ans. Rn :== Rs = 6.2kn;lo =

.
OA9mA,Vs",-L96 V, and Vn = +1.96 Y. RG can be selected in the range of
I MQ to lO MQ.

4.5.3 Biasing Using a Drain-to-Gate Feedback Resistor

A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor
connected between the drain and the gate is shown in Fig. 4,32, Here the large feedback
resistance RG I
(usually in the MQ range) forces the dc voltage at the gate to be equal to that at
the drain (becauseG 0), Thus we can write
=:;

VGs :== Vns :== Vnn-Rnln

which can be rewritten in the form

(4.49)

which is identical in form to Eq. (4.46), which describes the operation of the bias scheme
discussed above [that in Fig. 4,30(a)]. Thus, here too, if for some reason changes, say In
increases, then Eq, (4.49) indicates that must decrease, The decrease in in turnVGS VGS
causes a decrease in In,
a change that is opposite in direction to the one originally assumed.
Thus the negative feedback or degeneration provided by
constant as possible,
works to keep the value of as RG In
 4.5 B I AS I N G I N M O S A M P L I F I E R C I R C U ITS 285

FIGURE 4.32 Biasing the MOSFET using a large drain-to-gate feedback resis­
tance, RG.

The circuit of Fig. 4.32 can be utilized as a CS amplifier by applying the input voltage
signal to the gate via a coupling capacitor so as not to disturb the de bias conditions already
established. The amplified output signal at the drain can be coupled to another part of the cir­
cuit, again via a capacitor. We shall consider such a CS amplifier circuit in Section 4.6. There
we will learn that this circuit has the drawback of a rather limited output voltage signal swing.

D4.� 1 Itis requited (� desigJi tbe2;ir6llit in Fig."4.32'tb'Op�tale ata�d6dr;Utl6urtent�fQ,5 1riA. Aisu1Il� Vl)k= ..
+5 N, k� WIL = l rriAIV , "'t= i V, andA,= 1). Use astandan:l5% resistance valuefor Ro., and giydhy
.
actual v alues obtained forID andVD•
Ans. RD =: 6.2kQ;JD == 0.49 rnA; VD == 1.96 V

4.5.4 Biasing USing a Constant-Current Source

The most effective scheme for biasing a MOSFET amplifier is that using a constant-current
source. Figure 4.33(a) shows such an arrangement applied to a discrete MOSFET. Here RG
(usually in the MQ range) establishes a dc ground at the gate and presents a large resistance
to an input signal source that can be capacitively coupled to the gate. Resistor establishes
an appropriate dc voltage at the drain to allow for the required output signal swing while
RD
ensuring that the transistor always remains in the saturation region.
I
A circuit for implementing the constant-current source is shown in Fig. 4.33(b). The
heart of the circuit is transistor Ql> whose drain is shorted to its gate and thus is operating in
the saturation region, such that

(4.50)

where we have neglected channel-length modulation (i.e., assumed A 0). The drain current
=
of QJ is supplied by VDD R.
through resistor Since the gate currents are zero,

ID1 = I REF = ....:: +--=---"-'"

....VDD� Vss - VGS
R (4.51)
286 C H A P T E R 4 M O S F I E L D- E F F ECT TRA N S I STO RS (MOS F ETs)

To source of
RD R transistor Q
lREF t
in Fig. 4.33 (a)

r
0
�

ID lt

Rc QJ

- Vss - Vss

(a) (b)

F I G U R E 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the
constant-current source I using a current mirror.

R
where the current through is considered to be the reference current of the current source
and is denoted IREP' Given the parameter values of Q I and a desired value for IREF, Eqs. (4.50)
and (4.51 ) can be used to determine the value of R.
Now consider transistor Q2: It has the
same VGS
as Q I ; thus if we assume that it is operating in saturation, its drain current, which is
the desired current I of the current source, will be

(4.52)

where we have neglected channel-length modulation. Equations (4.51) and (4.52) enable us
to relate the current I to the reference current IREF,

( WILh
I - IREF (4.53)
( W IL) I

Thus I is related to IREF by the ratio of the aspect ratios of QI and Q2' This circuit, known as
a current mirror, is very popular in the design of IC MOS amplifiers and will be studied in
great detail in Chapter 6.
 4.6 S M A LL-S I G N A L O P E RATI O N A N D M O D E LS 287

4. 5.5 A Final Remark

The bias circuits studied in this section are intended for discrete-circuit applications. The only
exception is the curr
�nt mirror circuit of Fig. 4.33(b) w��h, as �entione� ab�ve, is extensively
used in IC design. BIaS arrangements for IC MOS amplIfIers wIll be studIed ill Chapter 6.

4.6 S M All-S I G NA L O PE RAT I O N A N D M O D E LS

In our study of the large-signal operation of the common-source MOSFET amplifier in
Section 4.4 we learned that linear amplification can be obtained by biasing the MOSFET
to operate in the saturation region and by keeping the input signal small. Having studied
methods for biasing the MOS transistor in the previous section, we now turn our attention to
exploring small-signal operation in some detail. For this purpose we utilize the conceptual
common-source amplifier circuit shown in Fig. 4.34. Here the MOS transistor is biased by
applying a de voltage VGS'
a clearly impractical arrangement but one that is simple and use­
ful for our purposes. The input signal to be amplified, vgs' is shown superimposed on the de
bias voltage VGS'The output voltage is taken at the drain.

4.6.1 The DC Bias Point

The de bias current ID can be found by setting the signal Vgs to zero; thus,

ID = � k�� (VGS - Vt )2 (4.54)

where we have neglected channel-length modulation (i.e., we have assumed A = 0). The de
voltage at the drain, VDS
or simply VD
(since S is grounded), will be

VD = VDD - RDID (4.55)

To ensure saturation-region operation, we must have

VD > VGS - Vt
Furthermore, since the total voltage at the drain will have a signal component superimposed
on VD, VD
swing.
has to be sufficiently greater than (VGS - Vt) to allow for the required signal

FIGURE 4.34 Conceptual circuit utilized to study the operation of

the MOSFET as a small-signal amplifier.
288 C H A P T E R 4 M O S F I E L D-E F F ECT TRA N S I STORS ( M O S F ETs)

4.6.2 The Signal Current in the Drain Terminal

Next, consider the situation with the input signal Vgs applied. The total instantaneous gate-to­
source voltage will be

VGS = VGS + Vgs (4.5 6)

resulting in a total instantaneous drain current iv,

iD = � k� � (VGS + Vgs - Vt)2

= 2! k ' WL (VGS - Vt)2 + k ' WL (VGs- Vt)vgs + 2! kn' WL v2gs
n n (4.57)

The first term on the right-hand side of Eq. (4.57) can be recognized as the dc bias current JD
(Eq. 4.54). The second term represents a current component that is directly proportional to
the input signal Vgs.
The third term is a current component that is proportional to the square
of the input signal. This last component is undesirable because it represents nonlinear dis­
tortion. To reduce the nonlinear distortion introduced by the MOSFET, the input signal
should be kept small so that

resulting in

(4.58)

or, equivalently,

(4.59)
where Vov is the overdrive voltage at which the transistor is operating.
If this small-signal condition is satisfied, we may neglect the last term in Eq. (4.57) and
express iD as

(4.60)
where

id = k� � (VGS - Vt) vgs

The parameter that relates id and Vgs is the MOSFET transconductance gm'

gm =
id
= k ' W ( VGS - Vt)
n (4.61)
-
Vgs L
or in terms of the overdrive voltage Vov,
(4.62)

Figure 4.35 presents a graphical interpretation of the small-signal operation of the enhancement
MOSFET amplifier. Note that gm is equal to the slope of the iD-vGS
characteristic at the bias
point,

(4.63)
 4.6 SMALL-S I G N A L O P E RATI O N A N D M O D E LS 289

An almost

FIGURE 4.35 Small-signal operation of the enhancement MOSFET amplifier.

This is the formal definition of gm , which can be shown to yield the expressions given in
Eqs. (4.6 1) and (4.62).

4.6.3 The Voltage Gain

Returning t o the circuit o f Fig. 4.34, w e can express the total instantaneous drain voltage VD
as follows:

VD VDD - RDiD
=

Under the small-signal condition, we have

VD DD-RD (ID + id)
= V
which can be rewritten as
VD = VD-RDid
Thus the signal component of the drain voltage is

(4.64)

which indicates that the voltage gain is given by

(4.65)

Vd
The minus sign in Eq. (4.65) indicates that the output signal is 1 800 out of phase with
respect to the input signal Vgs' This is illustrated in Fig. 4.36, which shows VGS VD'
and
input signal is assumed to have a triangular waveform with an amplitude much smaller than
The

2(VGS - Vt), the small-signal condition in Eq. (4.58), to ensure linear operation. For opera­
tion in the saturation region at all times, the minimum value of VD should not fall below the
corresponding value of VG by more than Vt. Also, the maximum value of VD should be
290 C H A P T E R 4 M OS F I E L D-E F F ECT TRA N S I STORS ( M O S F ETs)

VGS

¥ « 2 (Vc;s - v,)

o
FIGURE 4.36 Total instantaneous voltages VGS and VD for the circuit in Fig. 4.34.

smaller than V DD;

otherwise the FET will enter the cutoff region and the peaks of the output
signal waveform will be clipped off.
Finally, we note that by substituting for gm from Eq. (4.61) the voltage gain expression
in Eq. (4.65) becomes identical to that derived in Section 4.4-namely, Eq. (4.40) .

4.6.4 Separating the DC Analysis and the Signal Analysis

From the preceding analysis, we see that under the small-signal approximation, signal quan­
tities are superimposed on dc quantities. For instance, the total drain current iD equals the dc
ID id,
current plus the signal current the total drain voltage VD = VD + Vd, and so on. It follows
that the analysis and design can be greatly simplified by separating dc or bias calculations
from small-signal calculations. That is, once a stable dc operating point has been established
and all dc quantities calculated, we may then perform signal analysis ignoring dc quantities.

4.6.5 Small-Signal Equ iv� lent- Circuit M od els

From a signal point of view the FET behaves a s a voltage-controlled current source. It
accepts a signal Vgs between gate and source and provides a current gm Vgs at the drain terminal.
The input resistance of this controlled source is very high-ideally, infinite. The output
resistance-that is, the resistance looking into the drain-also is high, and we have assumed
 4.6 SMALL- S I G N A L O P E RATI O N AND M O D E LS 291

�-.,------o D
G 0-----0
+

s s
(a) (b)

gnal models for the MOSFET: (a) neglecting the dependence of iD on VDS in satu­
F IGU RE 4.37 Small-si
ration (the channel-length modulation effect); and (b) including the effect of channel-length modulation,
modeled by output resistance r = I VAI /1D '
0

it to be infinite thus far. Putting all of this together, we arrive at the circuit in Fig. 4.37(a),
which represents the small-signal operation of the MOSFET and is thus a small-signal
model or a small-signal equivalent circuit.
In the analysis of a MOSFET amplifier circuit, the transistor can be replaced by the
equivalent circuit model shown in Fig. 4.37(a). The rest of the circuit remains unchanged
except that ideal constant dc voltage sources are replaced by short circuits. This is a result
of the fact that the voltage across an ideal constant dc voltage source does not change, and
thus there will always be a zero voltage signal across a constant dc voltage source. A dual
statement applies for constant dc current sources; namely, the signal current of an ideal con­
stant dc current source will always be zero, and thus an ideal constant dc current source can
be replaced by an open-circuit in the small-signal equivalent circuit of the amplifier. The
circuit resulting can then be used to perform any required signal analysis, such as calculating
voltage gain.
The most serious shortcoming of the small-signal model of Fig. 4.37(a) is that it
assumes the drain current in saturation is independent of the drain voltage. From our study

VDS
of the MOSFET characteristics in saturation, we know that the drain current does in fact
depend on in a linear manner. Such dependence was modeled by a finite resistance r0
between drain and source, whose value was given by Eq. (4.26) in Section 4.2.3, which
we repeat here as

ID
I I
VA
ra = (4.66)

where VA = 1/ /L is a MOSFET parameter that either is specified or can be measured. It

ID
should be recalled that for a given process technology, VA is proportional to the MOSFET
channel length. The current is the value of the dc drain current without the channel-length
.
modulation taken into account; that is,

(4.67)

Typically, ro is in the range of 10 kn to 1000 kn. It follows that the accuracy of the small­
signal model can be improved by including ro in parallel with the controlled source, as
shown in Fig. 4.37(b).
It is important to note that the small-signal model parameters gm and ro depend on the dc
bias point of the MOSFET.
292 CHAPTER 4 M O S F I E L D - E F F E CT TRA N S I STO RS ( M O S F ETs)

Returning to the amplifier of Fig. 4.34, we find that replacing the MOSFET with the
small-signal model of Fig. 4.37(b) results in the voltage-gain expression

(4. 68)

Thus the finite output resistance ro results in a reduction in the magnitude of the voltage gain.
Although the analysis above is performed on an NMOS transistor, the results, and the
equivalent circuit models of Fig. 4.37, apply equally well to PMOS devices, except for using
IVcsI ,I Vt l , ovl , and I VA I and replacing with
IV k� k; .
4.6.6 The Transconductance 9m
We shall now take a closer look at the MOSFET transconductance given by Eq. (4.61), which
we repeat here as

(4.69)

This relationship indicates that gm is proportional to the process transconductance parameter

k� =f.1nCox and to the WIL ratio of the MOS transistor; hence to obtain relatively large trans­
conductance the device must be short and wide. We also observe that for a given device the
transconductance is proportional to the overdrive voltage, Vov Ves
Vt , the amount by
= -

which the bias voltage Ves

exceeds the threshold voltage Vr
Note, however, that increas­
ing gm by biasing the device at a larger Ves
has the disadvantage of reducing the allowable
voltage signal swing at the drain.
Another useful expression for gm can be obtained by substituting for (Ves
- Vt) in Eq. (4.69)
by J2IDf(k� (WfL» [from Eq. (4.53)] :

gm = J2k� JwfL ,ff; (4.70)

This expression shows that

1 . For a given MOSFET, gm is proportional to the square root of the dc bias current.
2. At a given bias current, gm is proportional to JwfL.
In contrast, the transconductance of the bipolar junction transistor (BIT) studied in Chapter 5
is proportional to the bias current and is independent of the physical size and geometry of
the device.
To gain some insight into the values of gm obtained in MOSFETs consider an integrated­
ID
circuit device operating at = 0.5 rnA and having = k� 120
f.1A/V2 . Equation (4.70) shows
that for WIL = 1 , gm = 0.35 rnA/V, whereas a device for which Wit = 1 00 has gm =
3.5 mAN. In contrast, a BIT operating at a collector current of 0.5 rnA 'has gm = mAIV. 20
Yet another useful expression for gm of the MOSFET can be obtained by substituting for
k�(WIL) in Eq. (4.69) by 2ID/eVes -
Vt)2:

gm
2ID 2ID (4.71)
=

Ves - Vt Vov
=

In summary, there are three different relationships for determining gm-Eqs. (4.69),
(4.70), and (4.71 )-and there are three design parameters-(WIL), Vov, and any two of ID,
which can be chosen independently. That is, the designer may choose to operate the MOSFET
with a certain overdrive voltage Vov and at a particular current ID ;
the required WIL ratio can
then be found and the resulting gm determined.
 4.6 S M A LL-S I G N A L O P E RATI O N A N D M O D E LS 293

co�on-source :vrOSFET amplifier utilizing the drai�-to-gate

Figure 4.38 (a) shows a discrete . .
ng arrangement. The lllput sIgnal Vi IS coupled to the gate VIa a large capacItor, and
feedback biasi
coupled to the load resistance RL via another large capacitor. We
the output signal at the drain is
yze this amplifier circuit to determine its small-signal voltage gain, its input resis­
The transistor has Vt = 1 .5 V,
wish to anal
tance, and the largest allowable input signal. k� (W;L) =0.25 mA/V2,
and VA = 50 V. Assume the coupling capacitors to be sufficiently large so as to act as short circuits
at the signal frequ encies of intere st.

+ 15 V

!i
:I 1
I

= 10 Mil Ii
[i
RG

rl
II:i!
iii
Ii,

Ii!
l-------1

rI I1.i'il
I',
II

I
i
I!
(a) I,
III

1,',:
11,
D
+ il
I

II
,:1

Ii

Ii
"

II
il

S Ii
iII
1
1'1i'l
II
(b)

Iii',
I I!
FIGURE 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.

Solution

[i ,
II'
I!

Ii I:
We first evaluate the dc operating point as follows:
2
ID = 21 x 0.25 ( VGS - 1 .5) (4.72)
i
where, for simplicity, we have neglected the channel-length modulation effect. Since the dc gate
current is zero, there will be no dc voltage drop across RG; thus VGS VD, which, when substituted
'I
i!,l
I
in Eq. (4.72), yields
=

(4.73)

I,1i
it

it:
"I
2 94 C H A P T E R 4 M O S F I E LD - E F F ECT TRA N S I STORS (MOS F ETs)

Also,
VD = 15 - RDID = 15 - lOID (4. 74)
Solving Eqs. (4.73) and (4.74) together gives
ID = 1 .06 mA and VD = 4.4 V

(Note that the other solution to the quadratic equation is not physically meaningful.)
The value of gm is given by

gm = k��(VGS - Vt)
= 0.25 (4.4 - 1 .5) = 0.725 mAN
The output resistance ro is given by
V 50
ro = -A = - = 47 kQ
ID 1 .06
Figure 4.38(b) shows the small-signal equivalent circuit of the amplifier, where we observe that the
coupling capacitors have been replaced with short circuits and the dc supply has been replaced with
a short circuit to ground. Since RG is very large (10 MQ), the current through it can be neglected
compared to that of the controlled source gm vgs' enabling us to write for the output voltage

Vo = g - Vg CRDIIRLllr )
m s o

Since Vgs = Vi' the voltage gain is

= - 0.725( 10/1101147) = -3.3 V/V

To evaluate the input resistance Rill' we note that the input current ii is given by
ii = ( vi - vo )/RG

Thus,
R In
- == RG
Vi
=
10
= 2 . 33 MQ
= -
ii 4.3 4.3
- -

The largest allowable input signal Vi is determined by the need to keep the MOSFET in satu­
ration at all times; that is,
VDS ;::: VGS - Vt
Enforcing this condition, with equality, at the point vGS is maximum and VDS is correspondingly
minimum, we write
VDSrnin =
VGSmax - Vt

4.4 - 3.%i = 4.4 + Vi - 1 .5

 4.6 SMALL-S I G N A L O P E RATI O N A N D M O D ELS 295

which results in
Vi = 0 34 V
.

negative direction, this input signal amplitude results in VCSmin = 4.4 0.34
Note that in the
- =
4.0 6 V , which is larger than V" and thus the transistor remains conducting. Thus, as we have sur­
mis ed, the limitation on input signal amplitude is posed by the upper-end considerations, and the
maximum allowable input signal peak is 0.34 V.

4.6. 7 The T Equivalent-Circuit Model

Through a simple circuit transformation it is possible to develop an alternative equivalent­
circuit model for the MOSFET. The development of such a model, known as the T model, is
illustrated in Fig. 4.39. Figure 4.39(a) shows the equivalent circuit studied above without roo
In Fig. 4.39(b) we have added a second gm Vgs current source in heries with the original con­
trolled source. This addition obviously does not change the terminal currents and is thus
allowed. The newly created circuit node, labeled X, is joined to the gate terminal G in
Fig. 4.39(c). Observe that the gate current does not change-that is, it remains equal to
zero-and thus this connection does not alter the terminal characteristics. We now note that

G --o
i7!iE"'i-
iHic D G D

S S
(a) (b)

G D

s
s
(d) (c)
FIGURE 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, To has
been omitted but can be added between D and S in the T model of (d).
p
C HAPTER 4 MOS F I E LD- E F F ECT TRA N S I STORS ( M O S F ETs)

G G

(a) (b)
FIGURE 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance rD. (b) An
alternative representation of the T model.

we have a controlled current source gmVgs connected across its control voltage Vgs. We can
replace this controlled source by a resistance as long as this resistance draws an equal cur­
rent as the source. (See the source-absorption theorem in Appendix C.) Thus the value of the
resistance is vg/gm vgs = I /gm . This replacement is shown in Fig. 4.39(d), which depicts
the alternative model. Observe that ig is still zero, id i
g m vgs' and s = vg/( l l gm) = gm vgs'
=

all the same as in the original model in Fig. 4.39(a).

The model of Fig. 4.39(d) shows that the resistance between gate and source looking
into the source is I Igm. This observation and the T model prove useful in many applica­
tions. Note that the resistance between gate and source, looking into the gate, is infinite.
In developing the T model we did not include roo If desired, this can be done by incorpo­
rating in the circuit of Fig. 4.39(d) a resistance ro between drain and source, as shown in
Fig. 4.40(a). An alternative representation of the T model in which the voltage-controlled
current source is replaced with a current-controlled current source is shown in Fig. 4.40(b).
Finally, we should note that in order to distinguish the model of Fig. 4.37(b) from the equiv­
alent T model, the former is sometimes referred to as the hybrid-n model, a carryover from
the bipolar transistor literature. The origin of this name will be explained in the next chapter.

4.6.8 Modeling the Body Effect �

As mentioned in Section 4.2, the body effect occurs in a MOSFET when the source is not
tied to the substrate (which is always connected to the most-negative power supply in the
integrated circuit for n-channel devices and to the most-positive for p-channel devices).
Thus the substrate (body) will be at signal ground, but since the source is not, a signal volt­
age Vbs develops between the body (B) and the source (S). In Section 4.2, it was mentioned
that the substrate acts as a "second gate" or a backgate for the MOSFET. Thus the signal Vbs
gives rise to a drain-current component, which we shall write as gmbvbs' where gmb is the body
transconductance, defined as

diD I
gmb == a (4.75)
VBS vcs � constant
I vDS � constant

iD
Recalling that depends on
(4.61) can be used to obtain
VBS through the dependence of Vt VBS'
on Eqs. (4.20), (4.33), and

(4.76)
 4.6 S M A L L- S I G N A L O P E RATI O N A N D M O D ELS 297

D
G .0:-:.---0 B

G 0----1 1----0 B

S s

(a) (b)

FIG URE 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected
to the body.

where
r (4.77)

Typically the value of X lies in the range 0 . 1 to 0.3.

Figure 4.41 shows the MOSFET model augmented to include the controlled source
gmb vbs that models the body effect. This is the model to be used whenever the source is not
connected to the substrate.
Finally, although the analysis above was performed on a NMOS transistor, the results
and the equivalent circuit of Fig. 4.41 apply equally well to PMOS transistors, except for using
I VGsl, 1 Vr!, l Vovl, I VA I, IVSBI, Irl, and I A I and replacing k� with k;.

4 .6.9 Summary
We conclude this section by presenting in Table 4.2 a summary of the formulas for calculating
the values of the small-signal MOSFET parameters. Observe that for gm we have three different
formulas, each providing the circuit designer with insight regarding design choices. We shall
make frequent comments on these in later sections and chapters.

Small-Signal Parameters
NMOS transistors:
Transconductance:

J
II
I
= J.lnCoxT,W Vov = 2D
W
gm = 2J.lnCox ID
T, Vo v
II Output resistance:
ro = VAlID = l I AJD
!Ill Body transconductance:

= Xgm = r gm
gmb
2 J2 ¢f + VSB
PMOS transistors:
Same formulas as for NMOS except using lVovL I VA I , IAt IrI, I V
sEI, and Ix l and replacing J.ln with J.lp•
(Continued)
298 C H A P T E R 4 M O S F I E L D - E F F ECT TRA N S I STO R S (MOS F ETs)

TABLE 4.2 (Continued)

Small-Signal Equivalent Circuit Models when /Vssi 0 (i.e., No Body Effect)

=

S s s
Hybrid-n model T models
(i
Small-Signal Circuit Model when J Vssl "* 0 .e., Including the Body Effect)

s
Hybrid-nmodel

�� � 'L � � d������W:d1m���1�!��t� :
'"
. 4� �� � �� i ili �
' n
ves "" o:�· 1)Jini�\
sin. qji vCllts; find va asstiroing thatthe small-signal �pprdxinlatio.n hol<ls. What are the u

cmtinr and maximuin values ofvn? (e) Use Eq.. (4.5,1) to detennine th£ vaijous cpmponents:of ffy 'Using ·
the identitY (sin2 (f)t = cos. 2(Ot), WOW that thereis a slight shift inl.6 (bynowmuch?l and thatthere is a
second-harmonic component (i:e., a component willi frequency 2(0). Express the amplitude ofllie seCond�
harmonic component as a percentage ofthe arri])litude ofthe fundamentaL(This . valueisknown as the
second-harmonic distortion.)
AilS. (a) 200 j1A, 3 V; (b) O.4 mA!V� (c) -4 V!V; (d) va == "':0.8 sinon volts, 2.2 V, 3.8 V; (e) in ==
(204 + 80 sinOJt --' 4 cos 2 OJt) f1A, 5%
 4.7 S I N G LE-STA G E M O S A M P L I F I E R S 299

4.24 An NMO S transistor has JLnCox = 60 JLAlV2, WIL � 40, V, = 1 V, and VA = 15 V. Find gm and ro when
(a) the bias voltage VGS = 1.5 V, and when (b) the bias currentID == 0.5 rnA.
Ans. (a) L 2 mA1V, 50 k£!; (b) 1.55 mAlV, 30 k£!
4.25 A MOSFET is to operate at ID = 0.1 rnA and is to have gm = 1 rnAIV. If k� = 50 JLAJV2, find the
reqnired WIL ratio and the overdrive voltage.
Ans. 100, 0.2 V
4.26 For a fabrication process for which J1p = 0.4JL", find the ratio of the width of a PMOS transi stor to the
width of an NMOS transistor so that the two devices have equal gm for the same bias conditions. The
.
two devic es have equal channel lengths.
'. .. .. . '

V ll�" and VsB = 4 V, find X= gm&/gm'

��

•.
.. , ,
.
4.27 For an NMOS transistof with 2</>, = 0. V� r==O.5
6

Ans. OJ.2 .. . ' .. . • . . " . .. . .• .' . . . . .

. .. .
" i ." , " . c ' . .. . " i .
.
. .
.and g� ,when. \. tjly ,
.

'
and W{L,:;; .16 ,ttrn!O:S #nt.Firi�tiD'
' .
" , ' " ' ... . . . •

", ' · ·" f'· · " · · f ··i� ·'(· . · · i 1 ·· ' · ' '"
. ..

transistor ha� v/� �rV,. k; =; 6f) )1A!V?;

" b'" "d . v, . .
4.28 .A..PMOS .
i d th. e vi1iUe, O ro l i/i;. at. .L. . :;= ,i. ,f.tID.iJ "Fi, .7" ii ., ' i i.. " , .i ," ,
' ' ' ' .<

Ans. 216�;\():i'2 pii\fv;,;97.� W::; "

. " 1 ' 6 iH ' "
devlcecls Jase at 'GS "F -L 'v; A1so, flll
. O O'4"V-1 ' "
' ' " "

';" i;4S:ifJI\li���.J$�I.�\t;((;
4.7 S I N G L E-STAG E M OS A M P L I F I ERS
Having studied MOS amplifier biasing (Section 4.5) and the small-signal operation and
models of the MOSFET amplifier (Section 4.6), we are now ready to consider the vmious
configurations utilized in the design of MOS amplifiers. In this section we shall do this for the
case of discrete MOS amplifiers, leaving the study of integrated-circuit (IC) MOS amplifiers to
Chapter 6. Beside being useful in their own right, discrete MOS amplifiers are somewhat
easier to understand than their IC counterparts for two main reasons: The separation between
dc and signal quantities is more obvious in discrete circuits, and discrete circuits utilize resis­
tors as amplifier loads. In contrast, as we shall see in Chapter 6, IC MOS amplifiers employ
constant-current sources as amplifier loads, with these being implemented using additional
MOSFETs and resulting in more complicated circuits. Thus the circuits studied in this section
should provide us with both an introduction to the subject of MOS amplifier configurations
and a solid base on which to build during our study of IC MOS amplifiers in Chapter 6,
Since in discrete circuits the MOSFET source is usually tied to the substrate, the body
effect will be absent. Therefore in this section we shall not take the body effect into account.
Also, in some circuits we will neglect ro in order to keep the analysis simple and focus our
attention at this early stage on the salient features of the amplifier configurations studied.

4.7. 1 The Basic Structure

. Figure 4.42 shows the basic circuit we shall utilize to implement the various configurations
of discrete-circuit MOS amplifiers. Among the various schemes for biasing discrete MOS
300 C H A P T E R 4 M O S F I E L D-E F F ECT TRA N S I STO RS ( M O S F ETs)

FIGURE 4.42 Basic structure of the circuit used

to realize single-stage discrete-circuit MOS amplifier
- Vss configurations.

amplifiers (Section 4.5) we have selected, for both its effectiveness and its simplicity, the
one employing constant-current biasing. Figure 4.42 indicates the dc current and the dc volt­
ages resulting at various nodes.

'EX:ERcrISE � , ." ,'

. ,

, " , - : '
. " ' ,, " . '

�
- J' � , � , �

ov

-2.5 V

- lO V

(a) FIGU RE E4.30

 4.7 S I N G LE-STA G E M O S A M P L I F I E R S 301

8m = l mA/V
= 150.kO

4.1.2 Characterizing Amplifiers

As we begin our study of MOS amplifier circuits, it is important to know how to characterize
the performance of amplifiers as circuit building blocks. An introduction to this subject was
presented in Section 1.5. However, the material of Section 1 .5 was limited to unilateral
amplifiers. A number of the amplifier circuits we shall study in this book, though none in
this chapter, are not unilateral; that is, they have internal feedback that may cause their input
resistance to depend on the load resistance. Similarly, internal feedback may cause the out­
put resistance to depend on the value of the resistance of the signal source feeding the ampli­
fief. To accommodate nonunilateral amplifiers, we present, in Table 4.3, a general set of
parameters and equivalent circuits that we will employ in characterizing and comparing
transistor amplifiers. A number of remarks are in order:

1 . The amplifier is shown fed with a signal source having an open-circuit voltage Vsig
and an internal resistanceRsig' These can be the parameters of an actual signal source
or the TMvenin equivalent of the output circuit of another amplifier stage preceding
the one under study in a cascade amplifier. Similarly, RL can be an actual load resis­
tance or the input resistance of a succeeding amplifier stage in a cascade amplifier.
2. Parameters and
Ri, Rm Avm Ai$> Gm pertain to the amplifier proper; that is, they do not
depend on the values of and
Rsig Rv By contrast, and
Rill' Rout, Av, Ai' Gvo' Gv may
depend on one or both of and
Rsig Rv I Also, observe the relationships of related pairs
of these parameters; for instance, = and
Ri Rill RL�=' Ro Rout R . �O '
= i "g
3. As mentioned above, for nonunilateral amplifiers, Rill may depend on Rv and Rout
may depend on Rsig. Although none of the amplifiers studied in this chapter are of this
type, we shall encounter nonunilateral MOSFET amplifiers in Chapter 6 and beyond.
No such dependencies exist for unilateral amplifiers, for which Rill = Ri and Rout = Ro·
4. The loading of the amplifier on the signal source is determined by the input resis­
tance Rill' The value of Rill determines the current ii that the amplifier draws from the
signal source. It also determines the proportion of the signal Vsig that appears at the
input of the amplifier proper (i.e., v;).
302 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs) �
TABLE 4.3 (haracteri$tic Parameters of�!llplifie�s 'i

Circuit

+ +

Definitions
II Input resistance with no load: II Output resistance:
Ri
== 5
ii RL== 1
II Input resistance:
==
R- 10
5
Ii
• +
II Open-circuit voltage gain:
A vo ==
�I v·I
RL==
Vsig = 0
II Voltage gain:
==
II Open-circuit overall voltage gain:
!!..£. I
Av �
Vi
==
Gvo
II Short-circuit current gain: Vsig RL==

A iS '"
�I
Ii
RL=O
Overall voltage gain:
Gv ==
II Current gain:
A. I == �I i
•

II Short-circuit transconductance:

II
Gm == �
Vi I RL=O
Output resistance of amplifier proper:
I
-�
R0 =
l.x I vi=O

+
Vi =0
 4.7 S I N G LE-STA G E M O S A M P L I F I E R S 303

Equivalent Circuits
11 A:

11 B:

11 C:

Relationships

Gv = Rin A o �
Rin + Rsig RL + Ra
v

Gva = _R ' _ A va
_I_
Ri + Rsig

5. When evaluating the gain Av from the open-circuit value A va, Ro is the output resis­
tance to use. This is because Av is based on feeding the amplifier with an ideal voltage
signal Vi' This should be evident from Equivalent Circuit A in Table 4.3. On the other
hand, if we are evaluating the overall voltage gain Gv from its open-circuit value GVO '
the output resistance to use is Rout. This is because Gv is based on feeding the ampli­
fier with vsigo which has an internal resistance Rsig ' This should be evident from
Equivalent Circuit C in Table 4.3.
6. We urge the reader to carefully examine and reflect on the definitions and the six
relationships presented in Table 4.3 . Example 4. 1 1 should help in this regard.
 I
304 CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STORS ( M O S F ETs)

A transistor amplifier is fed with a signal source having an open-circuit voltage Vsig of 10 mV and
an internal resistance Rsig of 100 ill . The voltage Vi at the amplifier input and the output voltage
Va are measured both without and with a load resistance RL = 10 kQ connected to the amplifier
output. The measured results are as follows:
v; (mV) vo (mV}

Without RL 9 90
With RL connected 8 70

Find all the amplifier parameters.

Solution
First, we use the data obtained for RL = 00 to determine
A vo = 90 = 10 V/V
9
and
G vo
90 = 9 V/V
=

10
Now, since

which gives
900 kQ
Ri =

Next, we use the data obtained when RL = 10 kQ is connected to the amplifier output to determine
70 8.75 V/V
A = v =

8
and
Gv = 70 7 V/V
10
=

The values ofA v and A vo can be used to determine Ro as follows:

Av = Av --
OR
RL
L + Ro
8.75 = 0_
10 _1_
l O + Ro
which gives
Ro = 1 .43 kQ
Similarly, we use the values of Gv and Gv o to determine Rout from
RL
Gv = G vo ---"-­
RL + Rout
7 = 9 _1-,0_
10 + Rout
 4.7 S I N G LE-STAG E M O S A M P L I F I E RS 305

resulting in
Rout = 2.86 kQ
The value of Rin can be determined from
Vi Rin
Vsig Rin + Rsig
Thus ,

which yields
Rin = 400 kQ
The short-circuit transconductance Gm can be found. as follows:

v = ...!Q.. = 7
A o
Gm =
Ro 1 .43
rnAlV
and the current gain Ai can be determined as follows:
volRL Vo Rin
A· =
I
--

V/Rin Vi RL
Rin
= 8.75 x
400 = 350 AlA
= Av
RL 10
Finally, we determine the short-circuit current gain Ais as follows. From Equivalent Circuit A in
Table 4.3, the short-circuit output current is

However, to determine Vi we need to know the value of Rin obtained with RL = O. Toward that
end, note that from Equivalent Circuit C, the output short-circuit current can be found as

Now, equating the two expressions for iosc and substituting for Gvo by

I
R
G vo = A vo
Ri + Rsig
and for Vi from

results in

= 8l . 8 kQ
We now can use

to obtain

10 x 8 l .8/ l .43 = 572 AlA

306 CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

4.31 (a) If in the amplifier of Example 4.11 , Rsig is doubled, find the values for Rin, Gv, and Rout. (b) Repeat
for RL doubled (but Rsig unchanged;i.e., 100 ill). (c) Repeat for both Rsig and RL doubled.
Ans. (a) 400 ill , 5.83 V /V, 4.03 ill ; (b) 538 kQ, 7.87 V/V, 2.86 kQ; (c) 538 kQ, 6.8 V/V, 4.03 kQ

4.1.3 The Common-Source (CS) Amplifier

The common-source (CS) or grounded-source configuration is the most widely used of all
MOSFET amplifier circuits. A common-source amplifier realized using the circuit of
Fig. 4.42 is shown in Fig. 4.43(a). Observe that to establish a signal ground, or an ac ground
as it is sometimes called, at the source, we have connected a large capacitor, Cs, between the
source and ground. This capacitor, usually in the f.1F range, is required to provide a very small
impedance (ideally, zero impedance; i.e., in effect, a short circuit) at all signal frequencies of
interest. In this way, the signal current passes through Cs to ground and thus bypasses the out­
I
put resistance of current source (and any other circuit component that might be connected to
the MOSFET source); hence, Cs is called a bypass capacitor. Obviously, the lower the sig­
nal frequency, the less effective the bypass capacitor becomes. This issue will be studied in
Section 4.9. For our purposes here we shall assume that Cs is acting as a perfect short circuit
and thus is establishing a zero signal'voltage at the MOSFET source.
In order not to disturb the dc bias current and voltages, the signal to be amplified, shown
as voltage source Vsig with an internal resistance Rsig, is connected to the gate through a large
capacitor CCl' Capacitor CCl, known as a coupling capacitor, is required to act as a perfect
short circuit at all signal frequencies of interest while blocking dc. Here again, we note that
as the signal frequency is lowered, the impedance of CCl (i.e., IIj(j)CCl) will increase and
its effectiveness as a coupling capacitor will be correspondingly reduced. This problem too
will be considered in Section 4.9 when the dependence of the amplifier operation on fre­
quency is studied. For our purposes here we shall assume CCl is acting as a perfect short
circuit as far as the signal is concerned. B efore leaving eCl' we should point out that in sit­
uations where the signal source can provide an appropriate dc path to ground, the gate can
be connected directly to the signal source and both RG and CCl can be dispensed with.
The voltage signal resulting at the drain is coupled to the load resistance RL via another
coupling capacitor CC2' We shall assume that CC2 acts as a perfect short circuit at all signal
frequencies of interest and thus that the output voltage Va = Vd' Note that RL can be either an
actual load resistor, to which the amplifier is required to provide its output voltage signal, or
it can be the input resistance of another amplifier stage in cases where more than one stage
of amplification is needed. (We will study multistage amplifiers in Chapter 7.)
To determine the terminal characteristics of the CS amplifier-that is, its input resis­
tance, voltage gain, and output resistance-we replace the MOSFET with its small-signal
model. The resulting circuit is shown in Fig. 4.43(b). At the outset we observe that this
amplifier is unilateral. Therefore R ill does not depend on Rv and thus Rill .:,= Ri• Also, Rout
will not depend on Rsig, and thus Rout = RD . Analysis of this circuit is straightforward and
proceeds in a step-by-step manner, from the signal source to the amplifier load. At the input

ig = 0

(4.78)

(4.79)
 4.7 S I N G L E-STA G E M O S A M P L I F I E R S 307

...__---1

1---0-_---0
va

- Vss
(a)

(b)

o
-----?o-

(c)
FIGURE 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the
amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with
the MOSFET model implicitly utilized.
308 CHAPTER 4 MaS F I E LD-E F F ECT TRA N S I STORS ( M O S F ETs)

Usually R G is selected very large (e.g., in the MQ range) with the result that in many appli­
cations R G � Rsig and

Now

and

Thus the voltage gain A v is

Av = -gm(ro " RD " RL) (4.80)
and the open-circuit voltage gain A va is
A va = -gm(ro " RD) (4.81)
The overall voltage gain from the signal-source to the load will be

Rin
Gv = Av
R in + R sig

Rc :� gm(ro "
Sig
RD " RL) (4.82)

Finally, to determine the amplifier output resistance R out we set Vsig to 0; that is, we replace
the signal generator Vsig with a short circuit and look back into the output terminal, as indi­
cated in Fig. 4.43 . The result can be found by inspection as
(4.83)
As we have seen, including the output resistance ro
in the analysis of the CS amplifier is
ro
straightforward: Since appears between drain and source, it in effect appears in parallel
r
with RD ' Since it is usually the case that a � RD , the effect of ro will be a slight decrease in
the voltage gain and a decrease in Rout-the latter being a beneficial effect!
Although small-signal equivalent circuit models provide a systematic process for the
analysis of any amplifier circuit, the effort involved in drawing the equivalent circuit is
sometimes not justified. That is, in simple situations and after a lot of practice, one can perform
the small-signal analysis directly on the original circuit. In such a situation, the small-signal
MOSFET model is employed implicitly rather than explicitly. In order to get the reader
started in this direction, we show in Fig. 4.43(c) the small-signal analysis of the CS amplifier
performed on a somewhat simplified version of the circuit. We urge the reader to examine
this analysis and to correlate it with the analysis using the equivalent circuit of Fig. 4.43(b).

. 4;32 '20rt�ider a Cs.ainpliflerbased on theCiicllit lUIalyzedi� ExerCii� 4.�O. Specifical1Y,ref;tt�the resuIK

.
.. .,. of that exetcise shown in Fig; E4.30: Find R�;A;;o; and>Rout; bothwlthoutand with taken into aCcolmt
ra

Thencalciilate the overall voltage gain·Gv, withr" taken into account, for the cas�Rsjg = lOO kQ. and
. RL = 15 kQ. Ifvsig is a 0.4-V peak-to�peak sinusoid, what output signal Vo results?
Ans. Withoutl'o : Rin= 4.7 MQ, Avo = -15 VIV, and Rout = 15 kQ; with r,,:RJn = 4.7 MO, Avo = -I3.6 VN,
and Rout = 13.6 kO; Gv = -7 VIV; Va is a 2:8-V peak-to-peak sinusoid up ri pos d
s e m e 011
a dc drain
voltage of +2.5 V.
 4.7 S I N G L E-STA G E M O S A M P L I F I E R S 309

We conclude our study of the C S amplifier by noting that it has a very high input
resistance, a moderately high voltage gain, and a relatively high output resistance.

4. 7.4 The Common-Source Amplifier with a Source Resistance

It is often beneficial to insert a resistance Rs in the source lead of the common-source ampli­
fier, as shown in Fig. 4.44(a). The corresponding small-signal equivalent circuit is shown in

Vd __ --1 I----c)---.�-{) Va

l
---

o
�

Vi

- Vss

vj(L + Rs)
(a)
id = i =
--«---
D 0-------+--0--<_---0 Va

(b)
FIGURE 4.44 (a) Common-source amplifier with a resistance Rs in the source lead. (b) Small-signal
equivalent circuit with ro neglected.
310 C HAPTER 4 M O S F I ELD-E F F ECT TRA N S I STO RS ( M O S F ETs)

Fig. 4.44(b) where we note that the transistor has been replaced by its T equivalent-circuit
model. The T model is used in preference to the n model because it makes the analysis in
this case somewhat simpler. In general, whenever a resistance is connected in the source
lead, as for instance in the source-follower circuit we shall consider shortly, the T model is
preferred: The source resistance then simply appears in series with the resistance 1 /gm,
which represents the resistance between source and gate, looking into the source.
It should be noted that we have not included ro in the equivalent-circuit model. Including
ro would complicate the analysis considerably; ro would connect the output node of the

amplifier to the input side and thus would make the amplifier nonunilateral. Fortunately, it
turns out that the effect of ro on the operation of this discrete-circuit amplifier is not important.
This can be verified using SPICE simulation (Section 4. 12). This is not the case, however, for
the integrated-circuit version of the circuit where ro plays a major role and must be taken
into account in the analysis and design of the circuit, which we shall do in Chapter 6.
From Fig. 4.44(b) we see that as in the case of the CS amplifier,

(4.84)
and thus,

c R
Vi = Vsig----"- (4.85)
R c + Rsig
Unlike the CS circuit, however, here Vgs is only a fraction of Vi. It can be determined from
the voltage divider composed of I I gm and Rs that appears across the amplifier input as
follows:
1

V.� (4.86)
'-.l
gm
+ Rs

Thus we can use the value of Rs to control the magnitude of the signal Vgs and thus ensure
that Vgs does not become too large and cause unacceptably high nonlinear distortion. (Recall
the constraint on Vgs given by Eq. 4.59). This is the first benefit of including resistor Rs.
Other benefits will be encountered in later sections and chapters. For instance, we will show
by SPICE simulation in Section 4. 12 that Rs causes the useful bandwidth of the amplifier to
be extended. The mechanism by which Rs causes such improvements in amplifier perfor­
mance is that of negative feedback. Unfortunately, the price paid for these improvements is
a reduction in voltage gain, as we shall now show.
The current id is equal to the current i flowing in the source lead; thus,

id = i = (4.87)
-.l + Rs
gm

Thus including Rs reduces id by the factor (1 + gmRS) ' which is hardly surprising since this
is the factor relating Vgs to Vi and the MOSFET produces id = gmVgs. Equation (4.87) indicates
also that the effect of Rs can be thought of as reducing the effective gm by the factor (1 + g�s)·
The output voltage can now be found from

Vo = -iARD II RL )
gm(RD II RL)
=-=-'--"'----'::..:. v ·
1 + gmRs I
 4.7 S I N G L E-STA G E M O S A M P L I F I E R S 31 1

Thus the voltage gain is

A v
= _
gm(RD II
R L)
1 + gmRS
(4. 88)

and setting RL = 00 gives

(4.89)

The overall voltage gain G is v

Gv = _
RG gm(RD II RL ) (4.90)
RG + Rsig 1 + grnRs
Comparing Eqs. (4. 88), (4.89), and (4.90) with their counterparts without
(1 + gmRS) '
Rs
indicates that
including Rs results in a gain reduction by the factor In Chapter 8 we shall study
negative feedback in some detail. There we will learn that this factor is called the amount of
feedback and that it determines both the magnitude of performance improvements and, as a
trade-off, the reduction in gain. At this point, we should recall that in Section 4.5 we saw
that a resistance Rs in the source lead increases dc bias stability; that is, Rs
reduces the vari­
ability inID. The action of Rs ID
that reduces the variability of is exactly the same action we
are observing here: Rs
in the circuit of Fig. 4.44 is reducing id, which is, after:"all, just a vari­
ation in ID• Because of its action in reducing the gain, Rs
is called source degeneration
resistance.
Another useful interpretation of the gain expression in Eq. (4.88) is that the gain from
gate to drain is simply the ratio of the total resistance in the drain, (RD
II R L), to the total
resistance in the source, [( 1 / gm) + Rsl
Finally, we wish to direct the reader ' s attention to the small-signal analysis that is
performed and indicated directly on the circuit in Fig. 4.44(a). Again, with some practice,
the reader should be able to dispense, in simple situations, with the extra work involved
in drawing a complete equivalent circuit model and use the MOSFET model implicitly.
This also has the added advantage of providing greater insight regarding circuit opera­
tion and, furthermore, reduces the probability of making manipulation errors in circuit
analysis.

I,'>i<>

, . ' , . i'.(;3"In:ix��ci�;:.'g1�e�;��li�d:�n1���iL��:�:�'·d;�lYpe;��t�.�e·J.;·��i�[,;i��i���(i1�iij�i()U��Jfsi��hf��iiii,c!;;;'!i/
, theGS amplifier of2�8Vpeak�to�peak.Assuhte tbatfor'somefeasonwenow have aJ1iri.p!ltsign�l thte� .'
'times as large as before (i.e:; 1.2 V p�p) andthat we wish to modify the Circuit' to keep
. the output $ignal
level unchanged. What value should. we .use fqr. Rs?
Ans. 2.15 kQ

4.7.5 The Common-Gate (CG) Amplifier

By establishing a signal ground on the MOSFET gate terminal, a circuit configuration
aptly named common-gate (CG) or grounded-gate amplifier is obtained. The input sig­
nal is applied to the source, and the output is taken at the drain, with the gate forming a
3 1 :2 C H A P T E R 4 M O S F I E L D- E F F ECT TRA N S I STORS ( M O S F ETs)

common terminal between the input and output ports. Figure 4.45(a) shows a CG amplifier
obtained from the circuit of Fig. 4.42. Observe that since both the dc and ac voltages at the
gate are to be zero, we have connected the gate directly to ground, thus eliminating resistor Rc
altogether. Coupling capacitors Ccl and Ce2 perform similar functions to those the CS circuit.
in
The small-signal equivalent circuit model of the CG amplifier is shown in Fig. 4.45(b).
Since resistor Rsig appears directly in series with the MOSFET source lead we have selected
the T model for the transistor. Either model, of course, can be used and yields identical

F I G U R E 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equiva­
lent circuit of the amplifier in (a).
 4.7 S I N G L E-STA G E MOS A M P L I F I E R S 313

- Vss

(c)

FIGURE 4.45 (Continued) (c) The common-gate amplifier fed with a current-signal input.

results; however, the T model is more convenient in this case. Observe also that we have not
included To ' Including To here would complicate the analysis considerably, for it would
appear between the output and input of the amplifier. We will consider the effect of To when
we study the IC form of the CG amplifier in Chapter 6.
From inspection of the equivalent-circuit model in Fig. 4.45(b) we see that the input
resistance is
1
Rin = - (4. 9 1)
gm
This should have been expected since we are looking into the source terminal of the MOSFET
and the gate is grounded? Furthermore, since the circuit is unilateral, Rin is independent of
Rv and Rin = Ri• Since gm is of the order of 1 mA/V , the input resistance of the CG ampli­
fier can be relatively low (of the order of 1 kQ) and certainly much lower than in the case of
the CS amplifier. It follows that significant loss of signal strength can occur in coupling the
signal to the input of the CG amplifier, since

(4.92)

Thus,
1

(4.93)

7 As we will see in Chapter 6, when ro is taken into account, Rin depends on RD and RL and can be quite
different from 1 1 gm '
314 C H A P T E R 4 M O S F I E L D - E F F ECT TRA N S I STO RS ( M O S F ETs)

from which we see that to keep the loss in signal strength small, the source resistance Rsig
should be small,

The current i; is given by

and the drain current id is

Thus the output voltage can be found as

resulting in the voltage gain

(4.94)

from which the open-circuit voltage gain can be found as

A vo = grnRD (4.95)

The overall voltage gain can be obtained as follows:

1
Rin A gm A Av
(4.96a)
v 1 +R v
Gv =
= =

Rin + Rsig - 1 + gmR sig

sig
gm
resulting in

(4.96b)

Finally, the output resistance is found by inspection to be

(4.97)

Comparing these expressions with those for the common-source amplifier we make the
following observations:

1. Unlike the CS amplifier, which is inverting, the CO amplifier is noninverting. This,

however, is seldom a significant consideration.
2. While the CS amplifier has a very high input resistance, the input resistance of the CO
amplifier is low.
3. While the A v values of both CS and CO amplifiers are nearly identical, the overall
voltage gain of the CO amplifier is smaller by the factor 1 + grnRsig (Eq. 4.96b), which
is due to the low input resistance of the CO circuit.

The observations above do not show any particular advantage for the CO circuit; to
explore this circuit further we take a closer look at its operation. Figure 4.45(c) shows the
CO amplifier fed with a signal current-source isig having an internal resistance Rsig. This can,
of course, be the Norton equivalent of the signal source used in Fig. 4.45(a). Now, using
 4.7 S I N G LE-STAGE M O S A M P L I F I E RS 315

Rin = 1 /gm and the current-divider rule we can find the fraction of isig that flows into the
MOSFET source, ii'

(4.98)

Normally, Rsig � 1 / g m , and

(4.98a)

Thus we see that the circuit presents a relatively low input resistance 1 I g m to the input signal­
current source, resulting in very little signal-current attenuation at the input. The MOSFET
then reproduces this current in the drain terminal at a much higher output resistance. The cir­
cuit thus acts in effect as a unity-gain current amplifier or a current follower. This view
of the operation of the common-gate amplifier has resulted in its most popular application,
in a configuration known as the cascode circuit, which we shall study in Chapter 6.
Another area of application of the CG amplifier makes use of its superior high-frequency
performance, as compared to that of the CS stage (Section 4.9). We shall study wideband
amplifier circuits in Chapter 6. Here we should note that the low input-resistance of the CG
amplifier can be an advantage in some very-high-frequency applications where the input
signal connection can be thought of as a transmission line and the 1 Ig m input resistance of
the CG amplifier can be made to function as the termination resistance of the transmission
line (see Problem 4.86).

· i;�4't6�side�\��G.aJp;iJi;�es�g1�dnsb1� th�icircuii6f·Fi�,�.J2,i�irichisJh�YzeJiA;E�eict§�:4.:S�:�i�}. :. .. •.•.

anruysis results displayed In Fig: E4.:?O. Note that gm ::;:.l mAtv ai1d Ri5 = 15 k(i FindRiu, R�ui, ·
Ai"", Av, aI).dQ:" fo.l' RL = 15 1.<0 llndBsig = SO h. Wha t Will the overall voltage &� =o
the
. . gaillbeco
. .
mefor ..
1 kO? 10 kQ? 100 kO?
. .
.

Ans. 1 kQ, 15 kO, +15 VIV, +7.5 VIV, +6.85 VIV; +3.7SV/V; 0.68 VIV ; 0.07 VIV

4.7.6 The Common-Drain or Source-Follower Amplifier

The last single-stage MOSFET amplifier configuration we shall study is that obtained by
establishing a signal ground at the drain and using it as a terminal common to the input port,
between gate and drain, and the output port, between source and drain. By analogy to the CS
and CG amplifier configurations, this circuit is called common-drain or grounded-drain
amplifier. However, it is known more popularly as the source follower, for a reason that
will become apparent shortly.
Figure 4.46(a) shows a common-drain amplifier based on the circuit of Fig. 4.42. Since
the drain is to function as a signal ground, there is no need for resistor RD, and it has therefore
been eliminated. The input signal is coupled via capacitor Co to the MOSFET gate, and the
output signal at the MOSFET source is coupled via capacitor Ce2 to a load resistor Rv
Since RL is in effect connected in series with the source terminal of the transistor (current
source I acts as an open circuit as far as signals are concerned), it is more convenient to use
the MOSFET' s T model. The resulting small-signal equivalent circuit of the common-drain
 VDD

Rsig

F
ee2

l
Va
Vsig

I RL
-
Rin

Rout
- Vss

(a)

e------o Vo

(b)

ov

(c) (d)
FIGURE 4.46 (a) common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit
A
model. (c) Small-signal analysis performed directly on the circuit. (d) Circuit for determining the output
resistance Rout of the source follower.
 4.7 S I N G LE-STA G E M O S A M P L I F I E RS 317

amplifier is shown in Fig. 4.46(b). Analysis of this circuit is straightforward and proceeds as
follows: The input resistance Rin is given by

(4.99)

Thus,

(4. 100)

Usually Rc is selected to be much larger than Rsig with the result that

To proceed with the analysis, it is important to note that ro appears in effect in parallel with
Rv with the result that between the gate and ground we have a resistance (1 I g m ) in series
with (RL II ro ) . The signal Vi appears across this total resistance. Thus we may use the voltage­
divider rule to determine Vo as

Vo = (4. 1 0 1)

from which the voltage gain A v is obtained as

R L II ro
A v = ---==---=-- (4. 1 02)
(RL II ro) + 1..­
gm
and the open-circuit voltage gain A vo as

(4. 103)
1
ro + -
gm
Normally ro � 1 lgm, causing the open-circuit voltage gain from gate to source, A vo in
Eq. (4. 1 03), to become nearly unity. Thus the voltage at the source follows that at the
gate, giving the circuit its popular name of source follower. Also, in many discrete-circuit
applications, ro � RL , which enables Eq. (4. 102) to be approximated by

Av � � (4. 102a)
- I
RL + ­
g m

The overall voltage gain Gv can be found by combining Eqs. (4. 100) and (4. 102), with the
result that

(4. 1 04)

which approaches unity for R c � Rsig , ro � I I gmo and ro � RL ·

To emphasize the fact that it is usually faster to perform the small-signal analysis
directly on the circuit diagram with the MOSFET small-signal model utilized only implic­
itly, we show such as analysis in Fig. 4.46(c). Once again, observe that to separate the intrinsic
action of the MOSFET from the Early effect, we have extracted the output resistance ro and
shown it separately.
318 CHAPTER 4 M O S F I E LD- E F F ECT TRA N S I STO RS ( M O S F ETs)

The circuit for determining the output resistance Rout is shown in Fig. 4.46(d). Because
the gate voltage is now zero, looking back into the source we see between the source and
ground a resistance I Igm in parallel with To; thus,

1
R out = - II T 0 (4. 1 05)
gm
Normally, To P 1 I gm , reducing Rout to

Rout = g-1m
_
(4. 106)

which indicates that Rout will be moderately low.

We observe that although the source-follower circuit has a large amount of internal feed­
back (as we will find out in Chapter 8), its Rin is independent of RL (and thus R; Rin) and its =
Rout is independent of Rsig (and thus Ro = RouJ. The reason for this, however, is the zero gate
current.
In conclusion, the source follower features a very high input resistance, a relatively low
output resistance, and a voltage gain that is less than but close to unity. It finds application
in situations in which we need to connect a voltage-signal source that is providing a signal
of reasonable magnitude but has a very high internal resistance to a much smaller load
resistance-that is, as a unity-gain voltage buffer amplifier. The need for such amplifiers
was discussed in Section 1 .5 . The source follower is also used as the output stage in a multi­
stage amplifier, where its function is to equip the overall amplifier with a low output resis­
tance, thus enabling it to supply relatively large load currents without loss of gain (i.e., with
little reduction of output signal level.) The design of output stages is studied in Chapter 14.

, ,
.. . .
'

H*HR€ISH , . .,- . . '

. ,
" ' " '

��jJ;i'{�'8!�������1f{t'��'�t��!�Jfi�!;�:�1
(a)Rjn =4.7 i1vid; 'Avo�'
"
,. ':" 'acccnirtt. ' (b). Fin<l ilie 9verall;smalr:: signal;vciltage , gain G� With roJaken' mto account. , ," " "
," , , \ . ', , ;; , :; '\
'
7
I V/V (\\'ithout 1:0),' 6:993' V/V. (�ithiTo); A,!�' b.938 (�ith9ut TO); 0.932 V
, "

(with To); Rout 1 kO (without r,,) , O,993 ill (with T,;) ; (b) 0 : 6 8 V/V '"
" Ans
.

4.7.7 Summary and Comparisons

For easy reference we present in Table 4.4 a summary of the characteristics of the various
configurations of discrete single-stage MOSFET amplifiers. In addition to the remar�s
already made throughout this section on the relative merits of the various configurations, th�
results displayed in Table 4.4 enable us to make the following concluding points:

1. The CS configuration is the best suited for obtaining the bulk of the gain required in
an amplifier. Depending on the magnitude of the gain required, either a single CS
stage or a cascade of two or three CS stages can be used.
2. Including a resistor Rs in the source lead of the CS stage provides a number of
improvements in its performance, as will be seen in later chapters, at the expense of
reduced gain.
common-Source

I-----o----e--{")

c�
va

l
- Vss
Common-Source with Source Resistance VDD

1--0--+_--0 Neglecting ro:

Va
Rin = RG
A =
RD II RL = gm(RD II RL)
_

-.l l + gmRs
v
gm + Rs
Rout = RD

Vgs
= _�_
Vi l + gmRs
- Vss
Common Gate

Ce2 Neglecting ro:

Va 1
Rin = gm

l
-

RL
-

Rout

- Vss (Continued)

319
320 C H A P T E R 4 M O S F I E LD-E F F ECT TRA N S I STO R S (MOS F ETs)

c' '
: \' � <
TABLE 4.4 . (Conti�Ued) .
Common-Drain or Source Follower

Rin = RG
ro II RL
Av = ---"-
-""--.,--
(ro II RL) + g
�
m

3. The low input resistance of the CG amplifier makes it useful only in specific applica­
tions. These include voltage amplifiers that do not require a high input resistance and
that take advantage of the excellent high-frequency performance of the CG configu­
ration (see Chapter 6) and as a unity-gain current amplifier or current follower. This
latter application gives rise to the most popular application of the common-gate con­
figuration, the cascode amplifier (see Chapter 6).
4. The source follower fmds application as a voltage buffer for connecting a high-resistance
source to a low-resistance load and as the output stage in a multistage amplifier.

4 . 8 T H E M OS F ET I NT E R N A L CAPACI TA N C E S
. A N D H I G H - F R EQU E N CY M O D E L
From our study of the physical operation of the MOSFET in Section 4. 1 , we know that the
device has internal capacitances. In fact, we used one of these, the gate-to-channel capaci­
tance, in our derivation of the MOSFET i-v
characteristics. We did, however, implicitly
assume that the steady-state charges on these capacitances are acquired instantaneously. In
other words, we did not account for the finite time required to charge and discharge the var­
ious internal capacitances. As a result, the device models we derived, such as the small-signal
model, do not include any capacitances. The use of these models would predict constant
amplifier gains independent of frequency. We know, however, that this is (unfortunately)
not the case; in fact, the gain of every MOSFET amplifier falls off at some high frequency.
Similarly, the MOSFET digital logic inverter exhibits a finite nonzero propagation delay.
To be able to predict these results, the MOSFET model must be augmented by including
internal capacitances. This is the subject of this section.
To visualize the physical origin of the various internal capacitances, the reader is
referred to Fig. 4. 1 . There are basically two types of internal capacitances in the MOSFET :

1 . The gate capacitive effect: The gate electrode (polysilicon) forms a parallel-plate
capacitor with the channel, with the oxide layer serving as the capacitor dielectric.
We discussed the gate (or oxide) capacitance in Section 4. 1 and denoted its value per
unit area as CoX"
 . " ,\
4 . 8 T H E M OS F ET I NT E R N A L CAPACITA N C E S A N D H I G H- F R E Q U E N CY M O D E L 321

2 . The source-body and drain-body depletion-layer capacitances: These are the capaci­
tances of the reverse-biased pn junctions formed by the n+ source region (also called
the source diffusion) and the p-type substrate and by the n+ drain region (the drain
diffusion) and the substrate. Evaluation of these capacitances will utilize the material
studied in Chapter 3.
These two capacitive effects can be modeled by including capacitances in the MOSFET
m odel between its four terminals, G, D, S, and B . There will be five capacitances in total:
Cg g Cgb, Csb, and Cdb, where the subscripts indicate the location of the capacitances in
s, C d,
the model. In the following, we show how the values of the five model capacitances can
be determined. We will do so by considering each of the two capacitive effects separately.

4.8.1 The Gate Capacitive Effect

The gate capacitive effect can be modeled by the three capacitances Cgs, Cgd, and Cgb• The
values of these capacitances can be determined as follows:
1. When the MOSFET is operating in the triode region at small VDS, the channel will be
of uniform depth. The gate-channel capacitance will be WL Cox and can be modeled
by dividing it equally between the source and drain ends; thus,

Cgs = Cgd = � WL Cox (triode region) (4. 107)

This is obviously an approximation (as all modeling is) but works well for triode­
region operation even when VDS is not small.
2. When the MOSFET operates in saturation, the channel has a tapered shape and is
pinched off at or near the drain end. It can be shown that the gate-to-channel capaci­
tance in this case is approximately � WL Cox and can be modeled by assigning this
entire amount to Cgs, and a zero amount to Cgd (because the channel is pinched off at

}
the drain) ; thus,

Cg s � WL Cox
=
( saturation region)
(4. 1 08)
Cgd = 0 (4. 109 )

3. When the MOSFET is cut off, the channel disappears, and thus Cgs = Cgd = O. How­
ever, we can (after some rather complex reasoning) model the gate capacitive effect

O}
by assigning a capacitance WL Cox to the gate-body model capacitance; thus,

Cg s Cgd = (4. 1 10)

(cutoff)
=

Cg b = WL Cox (4. 1 1 1)
4. There is an additional small capacitive component that should be added to Cgs and
Cgd in all the preceding formulas. This is the capacitance that results from the fact
that the source and drain diffusions extend slightly under the gate oxide (refer to
Fig. 4.1). If the overlap length is denoted Lov, we see that the overlap capacitance
component is

(4. 1 12)
Typically, Lov = 0.05 to 0. 1L.
 MOS F I ELD- E F F ECT TRAN S I STORS ( M O S F ETs)
(HAPTER 4

4.8.2 The Junction Capacitances

The depletion-layer capacitances of the two reverse-biased pn junctions formed between each
and the drain diffusions and the body can be determined using the formula
of the source
dev eloped in Section 3.7.3 (Eq. 3.56). Thus, for the source diffusion, we have the source­
body cap acitance, Csb'
CsbO

J
(4. 1 13 )
1 + VSB
Vo
where CsbO is the value of Csb at zero body-source bias, VSB
is the magnitude of the reverse­
bias v oltage, and is Vo
the junction built-in voltage (0.6 V to 0.8 V). Similarly, for the drain
diffusi on, we have the drain-body capacitance Cdb,
CdbO

J
Cdb - (4. 1 14)
1 + VDB
Vo
where CdbO is the capacitance value at zero reverse-bias voltage and VDB
is the magnitude of
this rev erse-bias voltage. Note that we have assumed that for both junctions, the grading
' ent m = :2I •
ICl
co e ff·
It should be noted also that each of these junction capacitances includes a component
ari g from the bottom side of the diffusion and a component arising from the side walls of
sin
the diffusion. In this regard, observe that each diffusion has three side walls that are in con­
tact with the substrate and thus contribute to the junction capacitance (the fourth wall is in
contact with the channel). In more advanced MOSFET modeling, the two components of
each of the junction capacitances are calculated separately.
The formulas for the junction capacitances in Eqs. (4. 1 1 3) and (4. 1 14) assume small­
sig operation. These formulas, however, can be modified to obtain approximate average
nal
values for the capacitances when the transistor is operating under large-signal conditions
such as in logic circuits. Finally, typical values for the various capacitances -exhibited by an
n-channel MOSFET in a relatively modem (0.5 11m) CMOS process are given in the following
exercise.

· l;b:�b.05 jLm; .CsbO = .C�bO · ·

, -

· ·4.34fror .. • . . . .. . .. capacitances when the.transfs-

10ff, Vo .
CgS' .Cgd,
. Csb' .and Cdb, (N..ot�: You may consult TaQle 4. 1 for
. . .
ff/,aJ�l.72 fF; 24.7 fF; 1.72 fF; 6.1 fF; 4.1 fF
. .. .
tOfis f . the nhV . . . .
Sl.l'llLC;Vl.'<>WllC".
lueS 0 . .. .
va . 5
..
·Ans. 3.4

4.8.3 The High-Frequency MOS FET Model

figure 4.47(a) shows the small-signal model of the MOSFET, including the four capaci­
tances Cgs' Cgd, Csb' and Cdb• This model can be used to predict the high-frequency response
of MOSFET amplifiers. It is, however, quite complex for manual analysis, and its use is
 4.8 T H E M OS F ET I NT E R N A L CAPACITA N C E S A N D H I G H - F R E Q U E N C Y M O D E L 323

s B
(a)

s
(b)

s
(c)
FiGURE 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit
for the case in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b)
with Cdb neglected (to simplify analysis).

limited to computer simulation using, for example, SPICE. Fortunately, for the case when the
source is connected to the body, the model simplifies considerably, as shown in Fig. 4.47(b).
In this model, Cgd, although small, plays a significant role in determining the high-frequency
response of amplifiers (Section 4.9) and thus must be kept in the model. Capacitance Cdb, on
the other hand, can usually be neglected, resulting in significant simplification of manual
analysis. The resulting circuit is shown in Fig. 4.47(c).
324 C H A P T E R 4 M OS F I ELD- E F F ECT TRA N S I STORS (MOS F ETs)

FIGURE 4.48 Determining the short-circuit current gain 1/Ii'

4.8.4 The MOS FET U nity-Gain Frequency (fr)

A figure of merit for the high-frequency operation of the MOSFET as an amplifier is the
unity-gain frequency, iT. This is defined as the frequency at which the short-circuit current­
gain of the common-source configuration becomes unity. Figure 4.48 shows the MOSFET
hybrid-n model with the source as the common terminal between the input and output ports.
To determine the short-circuit current gain, the input is fed with a current-source signal Ii
8
and the output terminals are short-circuited. It is easy to see that the current in the short
circuit is given by

10 = gmVgs - S CgdVgs
Recalling that Cgd is small, at the frequencies of interest, the second term in this equation
can be neglected,

(4.1 15)
From Fig. 4.48, we can express Vgs in terms of the input current Ii as
Vgs = 1;1 s ( Cgs + Cgd) (4.1 16)
Equations (4.1 15) and (4.1 16) can be combined to obtain the short-circuit current gain,

(4. 1 17)

For physical frequencies s = jro, it can be seen that the magnitude of the current gain
becomes unity at the frequency

roT = gm l(Cgs + Cgd)

Thus the unity-gain frequency fT = OJTI2n is

(4. 1 18)

Since fT is proportional to gm and inversely proportional to the FET internal capacitances, the
higher the value offT, the more effective the FET becomes as an amplifier. Substituting for
gm using Eq. (4.70), we can express fT in terms of the bias current ID (see Problem 4.92).
8 Note that since we are now dealing with quantities (currents, in this case) that are functions of frequency,
or, equivalently, the Laplace variable s, we are using capital letters with lowercase subscripts for our
symbols. This conforms to the symbol notation introduced in Chapter 1 .
 4.8 TH E M O S F ET I N T ER N A L CAPACITA N C E S A N D H I G H - F R EQ U E NCY M O D E L 325

Alternatively, we can substitute for gm from Eq. (4.69) to express/T in terms of the overdrive
voltage Vov (see Problem 4.93). Both expressions.. yield
.
additional insight into the high-
frequency operation of the MOSFET.
Typically,fT ranges from about 100 MHz for the older technologies (e.g., a 5-flm CMOS
p ess) to many GHz for newer high-speed technologies (e.g., a O.1 3-flm CMOS process).
roc

4.37 CalculatefT fo�:t�e. �-Chann��:NlOSFET 'ihJ�e c���citaJl. .y. es·Ee:�'. . :;�u#�iin ·e�e:ti��·'4�3gt'���J��!���;3;.· ): ·'·
ation at flA and that k; 16.0
100 "" /lA/V . . ..
,
. .
i •• •
"
.
•

,
•
•
•
•

" '

Alis. 3.7 GHz

4.8.5 Summary
We conclude this section by presenting a summary in Table 4.5.

Model

s B

Model Parameters

J
gm = flnCox w V ov =
W
2fln Cox - 1D = -
2 ID
L L Vov
326 C H A P T E R 4 M OS F I ELD- E F F ECT TRAN S I STORS ( M O S F ETs)

4.9 FREQU E N CY RES PO N S E O F THE CS A M P L I F I E R 9

In this section we study the dependence of the gain of the MOSFET common-source ampli­
fier of Fig. 4.49(a) on the frequency of the input signal. Before we begin, however, a note on
terminology is in order: Since we will be dealing with voltages and currents that are func­
tions of frequency or, more generally, the complex-frequency variable s, we will use Upper­
case letters with lowercase subscripts to represent them (e.g., Vgs' Vd, Vo).

4.9.1 The Three Frequency Bands

When the circuit of Fig. 4.49(a) was studied in Section 4.7.3, it was assumed that the cou­
pling capacitors Ccl and CC2 and the bypass capacitor Cs were acting as perfect short circuits at
all signal frequencies of interest. We also neglected the internal capacitances of the MOSFET;
that is, Cgs and Cgd of the MOSFET high-frequency model shown in Fig. 4.47(c) were
assumed to be sufficiently small to act as open circuits at all signal frequencies of interest.
As a result of ignoring all capacitive effects, the gain expressions derived Section 4.7.3
in
were independent of frequency. In reality, however, this situation applies over only a lim­
ited, though normally wide, band of frequencies. This is illustrated in Fig. 4.49(b), which
shows a sketch of the magnitude of the overall voltage gain, I G vi, of the CS amplifier versus
frequency. We observe that the gain i� almost constant over a wide frequency band, called
the midband. The value of the midband gain AM corresponds to the overall voltage gain Gv
that we derived in Section 4.7.2, namely,

(4. 1 19)

Figure 4.49(b) shows that the gain falls off at signal frequencies below and above the
midband. The gain falloff in the low-frequency band is due to the fact that even though
CCb CC2, and Cs are large capacitors (in the flF range), as the signal frequency is reduced,
their impedances increase, and they no longer behave as short circuits. On the other hand,
the gain falls off in the high-frequency band as a result of Cgs and Cgd, which though very
small (in the pF or fraction of pF range for discrete devices and much lower for IC devices),
their impedances at high frequencies decrease and thus can no longer be considered as open
circuits. It is our objective in this section to study the mechanisms by which these two sets
of capacitances affect the amplifier gain in the low-frequency and the high-frequency bands.
In this way, we will be able to determine the frequenciesfH andfu which define the extent of
the midband, as shown in Fig. 4.49(b).
The midband is obviously the useful frequency band of the amplifier. Usually, 1£ and fH
are the frequencies at which the gain drops by 3 dB below its value at midband. The amplifier
bandwidth or 3-dB bandwidth is defined as the difference between the lower (1£) and the
upper or higher (fH) 3-dB frequencies, /

(4. 120)

and since, usually, fL <is fH'

(4. 121)

9 We strongly urge the reader to review Section 1 .6 before proceeding with the study of this section.
 4.9 F R E Q U E NCY R E S P O N S E O F T H E CS A M P L I F I E R 327

- Vss

(a)

I Yo I (dB)
v" g ---.:;.
,...,.. ' oE-
o(------ Midband ------.,.. 1' oE-
o(- High-frequency band

:
,..,.

:
Low-frequency 1
band •All capacitances can be neglected
Gain falls off
Gain falls off I
•
•
I due to the effect
due to the effect I 3 dB I of and Cgs Cgd
o Cl, S,
fC C - ""1" - - - - - -
T
andCcz
20 log IAMI (dB)

iL
1 fH
..

f (Hz)
(b)
FIGURE 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response
of the amplifier in (a) delineating the three frequency bands of interest.

A figure-of-merit for the amplifier is its gain-bandwidth product, which is defined as

(4. 122)

It will be shown at a later stage that in amplifier design it is usually possible to trade-off gain
for bandwidth. One way to accomplish this, for instance, is by adding a source degeneration
resistance Rs, as we have done in Section 4.7.4.
328 CHAPTER 4 M O S F I E L D- E F F ECT TRA N S I STORS ( M O S F ETs)

4.9.2 The H igh-Frequency Response

To determine the gain, or the transfer function, of the amplifier of Fig. 4.49(a) at high fre­
quencies, and particularly the upper 3-dB frequency fR, we replace the MOSFET with its
high-frequency model of Fig. 4.47(c). At these frequencies, CCl ' Cel> and Cs will be behav­
ing as perfect short circuits. The result is the high-frequency amplifier equivalent circuit
shown in Fig. 4.50(a).
The equivalent circuit of Fig. 4.50(a) can be simplified by utilizing the TMvenin theo­
rem at the input side and by combining the three parallel resistances at the output side. The
resulting simplified circuit is shown in Fig. 4.50(b). This circuit can be further simplified if
we can find a way to deal with the bridging capacitor Cgd that connects the output node to
the input side. Toward that end, consider first the output node. It can be seen that the load
current is (grn (gm
Vgs - Igd), where Vgs) is the output current of the transistor and Igd is the cur­
rent supplied through the very small capacitance Cgd. At frequencies in the vicinity of fR,
which defines the edge of the midband, it is reasonable to assume that Igd is still much
smaller than (gm
Vg,), with the result that Vo can be given approximately by
(4. 123)

-
(a)
X

R;ig = RSig//RG G ---,lJo-

Cgd
--;...
Igd .
Igd
�--- -�----'--O Vo

V�
+
(RG �GRSi.g) Vsig +
X'

I
C" gmVgs

- -
(b)

FIGURE 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit;
(b) the circuit of (a) simplified at the input and the output;
 4.9 F R E Q U E NCY R E S P O N S E O F TH E CS A M P L I F I E R 329

+
X'

Ceq = Cgd (1 + gm�f)

y
Cin
(c)

1 ;° 1 (dB)
Slg

- - - - -...,...----��

-20 dB/decade

f(Hz)
(log scale)
(d)
FIGURE 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent
capacitance Ceq; (d) the frequency response plot, which is that of a low-pass single-time-constant circuit.

where

R{ = ra II RD 1/ RL
Since Va = VdS' Eq. (4. 123) indicates that the gain from gate to drain is -gmR{, the same
value as in the midband. The current Igd can now be found as

Igd = sCgd( Vgs - Va)

= sCgAVgs - (-gmR{ Vgs)]
= sCgd( l + gmRU Vgs
330 CHAPT ER 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

Now, the left-hand side of the circuit in Fig. 4.50(b), at XX', knows of the existence of C
�
only through the current Igd. Therefore, we can replace Cgd by an equivalent capacitance Ceq
between the gate and ground as long as Ceq draws a current equal to Igd. That is,

sCeqVgs = sCgd( 1 + gmR�) Vgs

which results in

(4.124)

Using Ceq enables us to simplify the equivalent circuit at the input side to that shown in
Fig. 4.50(c). We recognize the circuit of Fig. 4.50(c) as a single-time-constant (STC) circuit
of the low-pass type (Section 1 .6 and Appendix D) . Reference to Table 1 .2 enables us to
express the output voltage Vgs of the STC circuit in the form

(4. 125)

where mo is the corner frequency or the break frequency of the STC circuit,

mo = l/CinR:ig (4. 126)

with

(4. 1 27)

and

(4. 128)

Combining Eqs. (4.123) and (4. 125) results in the following expression for the high-frequency
gain of the CS amplifier,

(4. 129)

which can be expressed in the form

(4. 1 30)

where the midband gain AM is given by Eq. (4. 1 1 9) and mH is the upper 3-dB frequency,

1
mH = mo = (4. 1 3 1)
CinR :ig

and

f mH 1 (4. 1 32)
H =
2 rc 2rcCinR:ig
 4.9 F R E Q U E N CY R E S P O N S E O F T H E CS A M P L I F I E R 331

We thus see that the high-frequency response will be that of a low-pass STC network with a
3 -dB frequency fH determined by the time constant CinR;;g . Figure 4.50(d) shows a sketch of
the magnitude of the high-frequency gain.
Before leaving this section we wish to make a number of observations:

1. The upper 3-dB frequency is determined by the interaction of R:ig = R sig II RG and
Cin Cgs + Cgd( 1 + gmR� ) . Since the bias resistance RG i s usually very large, it can
=

be neglected, resulting in R:ig == Rsig , the resistance of the signal source. It follows
that a large value of Rsig will cause fH to be lowered.
2. The total input capacitance Cin is usually dominated by Ceq' which in turn is made
large by the multiplication effect that Cgd undergoes. Thus, although Cgd is usually
a very small capacitance, its effect on the amplifier frequency response can be very
significant as a result of its multiplication by the factor ( 1 + gmR{), which is approxi­
mately equal to the midband gain of the amplifier.
3. The multiplication effect that Cgd undergoes comes about because it is connected
between two nodes whose voltages are related by a large negative gain (-gmR{).
This effect is known as the Miller effect, and ( 1 + gmR{) is known as the Miller
multiplier. It is the Miller effect that causes the CS amplifier to have a large total
input capacitance Cin and hence a low fH'
4. To extend the high-frequency response of a MOSFET amplifier, we have to find con­
figurations in which the Miller effect is absent or at least reduced. We shall return to
this subject at great length in Chapter 6.
5. The above analysis, resulting in an STC or a single-pole response, is a simplified one.
Specifically, it is based on neglecting Igd relative to gmVgs' an assumption that applies
well at frequencies not too much higher than fH' A more exact analysis of the circuit
in Fig. 4.50(a) will be carried out in Chapter 6. The results above, however, are more
than sufficient for our current needs.

Find the midband gain AM and the upper 3-dB frequency fH of a CS amplifier fed with a signal
source having an internal resistance Rsig 100 kQ. The amplifier has R G 4.7 MQ , Rv = RL =
= =

15 kQ, gm = 1 mAIV, ra = 150 kQ , Cgs = 1 pF , and Cgd = 0.4 pF .

Solution

where

R{ = ra II Rv II RL = 150 11 15 11 1 5 = 7.14 kQ.

gmR{ = 1 x 7.14 = 7.14 VIV

Thus,
4 .7
AM = - x 7. 14 = -7 VIV
4 .7 + 0. 1
332 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

The equivalent capacitance, Ceq' is found as

Ceq = (1 + gmR{ ) Cg d

= ( l + 7. 14 ) x 0.4 = 3.26 pF

The total input capacitance Cin can be now obtained as

Cin = Cgs + Ceq = 1 + 3 .26 = 4.26 pF

The upper 3-dB frequency 1H is found from

1H = 1
27fCin (Rsig II RG )
1
12
2 7f X 4. 10- (0.1 1 4.7 ) 106
26 x x
= 382 kHz

Ans� -7.12 3.7

:
4.39 Ifit is possibleto replace fue MOSFET used in the amplifief in Example4.12withanbther having the
same Cgs but a smaller .Cgd' what is IDe maximum value that its Cgd can be in order to obtain anfH of at
least 1 MHz?
.

Ans. 0.08 pF

4.9.3 The low-Frequency Response

To determine the low-frequency gain or transfer function of the common-source amplifier,
we show in Fig. 4 .5 1(a)
the circuit with the dc sources eliminated (current source I open­
circuited and voltage source VDD short-circuited). We shall perform the small-signal analysis
directly on this circuit. However, we will ignore roo This is done in order to keep the analysis
simple and thus focus attention on significant issues. The effect of ro on the low-frequency
operation of this amplifier is minor, as can be verified by a SPICE simulation (Section 4.12).
The analysis begins at the signal generator by finding the fraction of Vsig that appears at
the transistor gate,

which can be written in the alternate form

RG S
(4.133)
Vg = Vsig R--"" -
G + R sig
-------

S
1
+
ee l (R G + Rsig )
Thus we see that the expression for the signal transmission from signal generator to ampli­
fier input has acquired a frequency-dependent factor. From our study of frequency response
 4.9 F R E Q U E N CY R E S P O N S E O F TH E CS A M P L I F I E R 333

Ro
Ce2
Va
lo t
t Id

t Id

�J
+

�
RG -
Vg

gm
C
-

FiGURE 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity,
ra is neglected.

in Section 1.6 (see also Appendix D), we recognize this factor as the transfer function of an
STC network of the high-pass type with a break or comer frequency (00 = 1 / C Cl (RG + Rsig ).
Thus the effect of the coupling capacitor CCI is to introduce a high-pass STC response with
a break frequency that we shall denote (OP ! ,

(4.134)

Continuing with the analysis, we next determine the drain current Id by dividing Vg by the
total impedance in the source circuit which is [( 1 /gm ) + ( 1 /sCs)] to obtain

which can be written in the alternate form

Id = gm Vg S -- (4.135)
s + gm
Cs
We observe that Cs introduces a frequency-dependent factor, which is also of the STC high­
pass type. Thus the amplifier acquires another break frequency,

gm
(OP2 = -
Cs
(4. 136)
To complete the analysis, we find Vo by first using the current-divider rule to determine
the fraction of Id that flows through Rv

RD ---=--
Io = -Id --

RD + --1 RL
S CC2 +
334 C H APTER 4 M O S F I ELD- E F F ECT TRA N S I STORS ( M OS F ETs)

and then multiplying 10 by RL to obtain

(4. 1 3 7)

from which we see that Ce2 introduces a third STC high-pass factor, giving the amplifier a
third break frequency at

(4. 138)

The overall low-frequency transfer function of the amplifier can be found by combining
Eqs. (4. 133), (4. 1 35), and (4. 1 37) and replacing the break frequencies by their symbols from
Eqs. (4. 134), (4. 1 36), and (4. 1 38),

(4. 1 39)

The low-frequency magnitude response can be obtained from Eq. (4. 1 39) by replacing s by
JOJ and finding I VoI Vsig! . In many cases, however, one of the three break frequencies can be
much higher than the other two, say by a factor greater than 4. In such a case, it is this highest­
frequency break point that will determine the lower 3-dB frequency,iL, and we do not have
to do any additional hand analysis. For instance, because the expression for OJPl includes gm
(Eq. 4. 1 36), OJP l is usually higher than OJp! and OJp3 . If OJPl is sufficiently separated from OJp]
and OJp3, then

/L == /Pl

which means that in such a case, the bypass capacitor determines the low end of the mid­
band. Figure 4.52 shows a sketch of the low-frequency gain of a CS amplifier in which the
three break frequencies are sufficiently separated so that their effects appear distinct.
Observe that at each break frequency, the slope of the asymptotes to the gain function
increases by 20 dB/decade. Readers familiar with poles and zeros will recognize/Ph /Pl, and
/P3 as the frequencies of the three real low-frequency poles of the amplifier. We will use
poles and zeros and related s-plane concepts later on in Chapter 6 and beyond.
Before leaving this section, it is essential that the reader be able to quickl�'find the fime­
constant and hence the break frequency associated with each of the three capacitors. The
procedure is simple:

1 . Reduce Vsig to zero.

2. Consider each capacitor separately; that is, assume that the other two capacitors are
acting as perfect short circuits .
3. For each capacitor, find the total resistance seen between its terminals. This is the
resistance that determines the time constant associated with this capacitor.

The reader is encouraged to apply this procedure to Ceh Cs, and Ce2 and thus see that
Eqs. (4. 1 34), (4. 136), and (4. 1 38) can be written by inspection.

Selecting Values for the Coupling and Bypass Capacitors We now address the design
issue of selecting appropriate values for Ceh Cs, and Ce2. The design objective is to place
the lower 3-dB frequency /L at a specified value while minimizing the capacitor values.
 4.9 F R E Q U E N CY R E S P O N S E O F T H E C S A M P L I F I E R 335

Vo d )
( B
Vsig
I
-,,=--�,,",,"---- - - - -

O �------�--�L---�--�
iP! iP3 iP2 i (Hz)
(log scale)

FIGURE 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break
frequencies are sufficiently separated for their effects to appear distinct.

Since as mentioned above Cs results in the highest of the three break frequencies, the total
capacitance is minimized by selecting Cs so that its break frequency IP2 = It- We then decide
on the location of the other two break frequencies, say 5 to 10 times lower than the frequency
of the dominant one, IP2' However, the values selected for Ip! and Ip should not be too low,
3
for that would require larger values for Ccl and CC2 than may be necessary. The design
procedure will be illustrated by an example.

We wish to select appropriate values for the coupling capacitors CC! and CC2 and the bypass
capacitor Cs for the CS amplifier whose high-frequency response was analyzed in Example 4.12.
The amplifier has Rc = 4.7
MO, RD = RL = 15
kO, Rsig = 100
kO, and gm = 1 rnAIV.
It is required
to have iL at100 Hz and that the nearest break frequency be at least a decade lower.

Solution
We select Cs so that

Thus,

1 10-3 1.6
X
I1F
2n 100
x
336 CH APTER 4 M O S F I E L D- E F FECT TRA N S I STO RS ( M O S F ETs)

Forfp] = fp3 = 1 0 Hz, we obtain

10 =
6
+ 4.7) X 1 0
------

2n:CC l ( 0 . 1
which yields

CC l = 3.3 nF
and

10 =
+ 1 5 ) x 1 03
-------

2n:Cc2 ( l5
which results in

CC2 = 0.53 f.1F

� �� - '" "" ''''' � � ,, ��� j} �¥ S-J\¥ -j';'�7�i:(-i' ",,�, ""' r-: ':? "'¢"::<'!'$2�� '1;'_ ��- �M = ¢ "' b �""","" � �< ,,��,'e-c
,, ,,, !

;
�
� ? ,

E�ER�ISE " "

" " : ;& : " ,:" :

� ::: l�I\:Q.
',,' ' '",' , ' ' ' " ', " "

,) 'i 4.40AC
S atnplifi�rhas eCl =: �.ljlF>RG ::: 10MQ, R&ig= 100 Q,gm 2 rnAN,RD =RL
Find AM, fp!> fn, fp3, andtv
Ans. -9.9 VN; 0.016 Hz; 318.3 Hz; 8 Hz; 318.3 Hz ,

4.9.4 A Final Remark

The frequency response of the other amplifier configurations will be studied in Chapter 6.

4.1 0 T H E CMOS D I G I TA L LO G I C I NV E RTE R

Complementary MOS or CMOS logic circuits have been available as standard packages for
use in conventional digital system design since the early 1970s. Such packages contain logic
gates and other digital system building blocks with the number of gates per package ranging
from a few (small-scale integrated or SSI circuits) to few tens (medium-scall\ integrated or
MSI circuits).
In the late 1970s, as the era of large- and very-Iarge-scale integration (LSI and VLSI;
hundreds to hundreds of thousands of gates per chip) began, circuits using only n-channel
MOS transistors, known as NMOS, became the fabrication technology of choice. Indeed, early
VLSI circuits, such as the early microprocessors, employed NMOS technology. Although
at that time the design flexibility and other advantages that CMOS offers were known,
the CMOS technology available then was too complex to produce such high-density VLSI
chips economically. However, as advances in processing technology were made, this state of
affairs changed radically. In fact, CMOS technology has now completely replaced NMOS at
all levels of integration, in both analog and digital applications.
For any IC technology used in digital circuit design, the basic circuit element is the logic
lO
inverter. Once the operation and characteristics of the inverter circuit are thoroughly

10 A study of the digital logic inverter as a circuitbuilding block was presented in Section 1.7 . A review
of this material before proceeding with the current section should prove helpful.
 4 . 1 0 TH E C M O S D I G ITAL LOG I C I NVERTER 337

FIGURE 4.53 The CMOS inverter.

understood, the results can be extended to the design of logic gates and other more complex
circuits. In this section we provide such a study for the CMOS inverter. Our study of the
CMOS inverter and logic circuits will continue in Chapter 10.
The basic CMOS inverter is shown in Fig. 4.53. It utilizes two matched enhancement­
type MOSFETs: one, QN, with an n channel and the other, Qp, with a p channel. The body of
each device is connected to its source and thus no body effect arises. As will be seen shortly,
the CMOS circuit realizes the conceptual inverter implementation studied in Chapter 1
(Fig. l .32), where a pair of switches are operated in a complementary fashion by the input
voltage VI.

4.1 0.1 Circuit Operation

We first consider the two extreme cases: when VI is at logic-O level, which is approximately
o V; and when vI is at 10gic-1 level, which is approximately VDD volts. In both cases, for ease
of exposition we shall consider the n-channel device QN to be the driving transistor and the
p-channel device Qp to be the load. However, since the circuit is completely symmetric, this
assumption is obviously arbitrary, and the reverse would lead to identical results.
Figure 4.54 illustrates the case when VI = VDD, showing the iD-VDS characteristic curve
for QN with VGSN = VDD. (Note that iD = i and VDSN = va) . Superimposed on the QN character­
istic curve is the load curve, which is the iD- vSD curve of Qp for the case VSGP = 0 V. Since
VSGP < I Vtl, the load curve will be a horizontal straight line at almost zero current level. The
operating point will be at the intersection of the two curves, where we note that the output
voltage is nearly zero (typically less than 10 mY) and the current through the two devices is
also nearly zero. This means that the power dissipation in the circuit is very small (typically a
fraction of a rnicrowatt). Note, however, that although QN is operating at nearly zero current
and zero drain-source voltage (i.e., near the origin of the iD-VDS plane), the operating point is
on a steep segment of the iD-VDS characteristic curve. Thus QN provides a low-resistance path
between the output terminal and ground, with the resistance obtained using Eq. (4. 1 3) as

(4. 140)

Figure 4.54(c) shows the equivalent circuit of the inverter when the input is high. This cir­
cuit confirms that va == VaL = 0 V and that the power dissipation in the inverter is zero.
 "

338 C H A P T E R 4 M O S F I E L D- E F F ECT TRA N S I STO R S ( M O S F ETs)

Load curve '---0 vo == 0

(VSGP = 0)

o VOL = 0
(a) (b) (c)

FIG U RE 4.54 Operation of the CMOS inverter when VI is high: (a) circuit with VI VDD (logic-l level, or
=

VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit.

+ Load curve
(vSGP = VDD)

Operating point

)
VOH = VDD
I 1
VGSN = VOL = 0

- o
(a) (b) (c)

FIGURE 4.55 Operation of the CMOS inverter when VI is low: (a) circuit with VI = 0 V (logic-O level, or
VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit.

The other extreme case, when VI = 0 V, is illustrated in Fig. 4.55. In this case QN is oper­
ating at VGSN = 0; hence its iD-vDS characteristic is almost a horizontal straight line at zero
current level. The load curve is the iD-vSD characteristic of the p-channel device with VSGP =
VDD• As shown, at the operating point the output voltage is almost equal to" VDD (typically
less than 10 mV below VDD) , and the current in the two devices is still nearly zero. Thus the
power dissipation in the circuit is very small in both extreme states.
Figure 4.55(c) shows the equivalent circuit of the inverter when the iuput is low. Here
we see that Qp provides a low-resistance path between the output terminal and" the dc supply
VDD, with the resistance given by

(4. 141)

The equivalent circuit confirms that in this case Vo == VO H = VDD and that the power dissipation
in the inverter is zero.
 4 . 1 0 TH E C M O S D I G ITAL LOG I C I NV E RTER 339

It should be noted, however, that in spite of the fact that the quiescent current is zero, the
load-driving capability of the CMOS inverter is high. For instance, with the input high, as in
the circuit of Fig. 4.54, transistor QN can sink a relatively large load current. This current can
quickly discharge the load capacitance, as will be seen shortly. Because of its action in sinking
load current and thus pulling the output voltage down toward ground, transistor QN is known
as the "pull-down" device. Similarly, with the input low, as in the circuit of Fig. 4.55, tran­
sistor Qp can source a relatively large load currcnt. This current can quickly charge up a
load capacitance, thus pulling the output voltage up toward VDD. Hence, Qp is known as
the "pull-up" device. The reader will recall that we used this terminology in connection
with the conceptual inverter circuit of Fig. 1. 32.
From the above, we conclude that the basic CMOS logic inverter behaves as an ideal
inverter. In summary:

1 . The output voltage levels are 0 and VDD, and thus the signal swing is the maximum
possible. This, coupled with the fact that the inverter can be designed to provide a
symmetrical voltage-transfer characteristic, results in wide noise margins.
2. The static power dissipation in the inverter is zero (neglecting the dissipation due to
leakage currents) in both of its states. (Recall that the static power dissipation is so
named so as to distinguish it from the dynamic power dissipation arising from the
repeated switching of the inverter, as will be discussed shortly.)
3. A low-resistance path exists between the output terminal and ground (in the low­
output state) or VDD (in the high-output state). These low-resistance paths ensure that
the output voltage is 0 or VDD independent of the exact values of the (W/L) ratios or
other device parameters. Furthermore, the low output resistance makes the inverter
less sensitive to the effects of noise and other disturbances.
4. The active pull-up and pull-down devices provide the inverter with high output­
driving capability in both directions. As will be seen, this speeds up the operation
considerably.
5. The input resistance of the inverter is infinite (because IG = 0). Thus the inverter can
drive an arbitrarily large number of similar inverters with no loss in signal level. Of
course, each additional inverter increases the load capacitance on the driving inverter
and slows down the operation. Shortly, we will consider the inverter switching
times.

4.1 0.2 The Voltage Transfer Characteristic

The complete voltage-transfer characteristic (VTC) of the CMOS inverter can be obtained
by repeating the graphical procedure, used above in the two extreme cases, for all inter­
mediate values of VI' In the following, we shall calculate the critical points of the resulting
voltage transfer curve. For this we need the i-v relationships of QN and Qp. For QN,

(4. 142)

and

(4.143)
340 CHAPTER 4 M O S F I E LD-E F F ECT TRA N S I STORS ( M O S F ETs)

For Qp,

iDP k; (�)J(VDD - VI - l VtPj )(VDD -VO) -� (VDD - VO )2J

=

for Va VI + I Vtp l ?: (4.144)

iDP 2� k; (W)
and

=
L p( VDD - VI - l Vtpl )2 (4. 145)

The CMOS inverter is usually designed to have Y'rn I Vtpl VI '

and = = k,;(WIL)n =

k; (WIL)p- It should be noted that since flp

is 0.3 to 0.5 times the value of to make flm
k' (WIL) of the two devices equal, the width of the p-channel device is made two to
three times that of the n-channel device. More specifically, the two devices are designed
to have equal lengths, with widths related by
Wp = fln
Wn flp
This will result in k�(WIL) n k;(WIL)p' and the inverter will have a symmetric transfer
=

characteristic and equal current-driving capability in both directions (pull-up and pull-down).
With QN and Qp matched, the CMOS inverter has the voltage transfer characteristic
shown in Fig. 4.56. As indicated, the transfer characteristic has five distinct segments corre­
sponding to different combinations of modes of operation of QN and Qp. The vertical

QN in saturation
Qp in triode region
1

VOH = VDD
I
QN off 1A 1
�

�:
1-----1--__
Slope = - 1

(V�D V) :
1
1
1
+
- - - I- - - -J -
B
1 I
1 I
1 1
1
� inQNsaturation
and Qp

1 QNQp inin triode

1

(V�D V) :C
1 1

Slope =
1 saturation
_ 1
_ - _ - - - - - - region
I
I I
I
1 1 1
1 I I 1
1 1 I 1
Qp off 1l
1 1 1 ID 1

V - VDD
th - 2

FIGURE 4.56 The voltage transfer characteristic of the CMOS inverter.

 4 . 1 0 TH E C M O S D I G ITAL L O G I C I NVERTER 341

segment B C is obtained when both QN and Qp are operating in the saturation region.
Because we are neglecting the finite output resistance in saturation, the inverter gain in this
region is infinite. From symmetry, this vertical segment occurs at VI VDD I2 and is
=

bounded by vo (B ) = VDD I2 + Vt and vo (C ) =VDDI2 - Vt .

The reader will recall from Section 1.7 that in addition to VOL and VOH, two other points
on the transfer curve determine the noise margins of the inverter. These are the maximum
permitted logic-O or "low" level at the input, VIV and the minimum permitted logic- l or
"high" level at the input, V/H. These are formally defined as the two points on the transfer
curve at which the incremental gain is unity (i.e., the slope is 1 VN). �

To determine VIH, we note that QN is in the triode region, and thus its current is given by
Eq. (4.142), while Qp is in saturation and its current is given by Eq. (4. 145). Equating iDN
and iDP, and assuming matched devices, gives

(4.146)
Differentiating both sides relative to VI results in

in which we substitute VI = V/H and d Vol d VI = - 1 to obtain

(4. 147)

Substituting VI = V/H and for Vo from Eq. (4.147) in Eq. (4.146) gives
(4. 148)
VIL can be determined in a manner similar to that used to find V/H. Alternatively, we can
use the symmetry relationship
VDD VDD -
VlH - -- - V/L
2
=

2
together with V/H from Eq. (4.148) to obtain

V/L = �(3 VDD + 2Vt) (4.149)

The noise margins can now be determined as follows:

NMH = V OH - VlH
= VDD - �(5VDD - 2Vt)
= �(3VDD + 2Vt) (4.150)
NML = V/L - VOL
= � (3 VDD + 2Vt) - 0
= �(3VDD + 2Vt) (4. 151)
As expected, the symmetry o f the voltage transfer characteristic results in equal noise mar­
gins. Of course, if QN and Qp are not matched, the voltage transfer characteristic will no
longer be symmetric, and the noise margins will not be equal (see Problem 4.107).
342 CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STORS (MOS F ETs)

4.43 An inverter fabricatedin a l .2-J1m CMOS technology uses the :ininimum possible channel lengths (I.e.,
Ln Lp == 1.2 J1m). IT Wn 1.8 J1m, find the value of Wp that would result in QN and Qp being matched.
2
.For: .this technology, k� ::::: 80 J1AIV , 27J1AIV2, Vtn 0.8 V, and VDD ::::: 5 Y Also, calculate
k; :::::
== ==

the value of the output resistance of the inverter when Vo = VOL;

==

Ans. 5.4 J1m; 2 kQ

4.44 Show: that the threshold voltage V'h of a CMOS inverter (see Fig. 4.56) is given by

..
.. th =
r('{D -
·
� lVtPr> + Vtn
..
.
V
l+r .
.

4.1 0.3 Dynamic Operation

As explained in Section 1 .7, the speed of operation of a digital system (e.g., a computer) is
determined by the propagation delay of the logic gates used to construct the system. Since
the inverter is the basic logic gate of any digital IC technology, the propagation delay of the
inverter is a fundamental parameter in characterizing the technology. In the following, we
analyze the switching operation of the CMOS inverter to determine its propagation delay.
Figure 4.S7(a) shows the inverter with a capacitor C between the output \lode and ground.
Here C represents the sum of the appropriate internal capacitances of the MOSFETs QN and
Qp, the capacitance of the interconnect wire between the inverter output node and the input(s)
of the other logic gates the inverter is driving, and the total input capacit"lllce of these load
(or fan-out) gates. We assume that the inverter is driven by the ideal pulse (zero rise
and fall times) shown in Fig. 4.S7(b). Since the circuit is symmetric (assuming matched
MOSFETs), the rise and fall times of the output waveform should be equal. It is sufficient,
therefore, to consider either the turn-on or the turn-off process. In the following, we consider

O.
the first.
Figure 4.S7(c) shows the trajectory of the operating point obtained when the input pulse
goes from VOL = 0 to VOH = VDD at time t ::::: Just prior to the leading edge of the input pulse
(that is, at t = 0-) the output voltage equals VDD and capacitor C is charged to this voltage.
At t = 0, VI rises to VDD, causing Qp to turn off immediately. From then on, the circuit is
equivalent to that shown in Fig. 4.S7(d) with the initial value of va = VDD• Thus the operating
point at t ::::: 0+ is point E, at which it can be seen that QN will be in the saturation region and
conducting a large current. As C discharges, the current of QN remains constant until va :::::
VDD - Vt (point F). Denoting this portion of the discharge interval tPHL! (where the subscript
 4.1 0 T H E C M O S D I G I TAL LOG I C I NVE RTE R 343

r
VD V,

t iDP 0 I
0
I
I
I �
t
I I
I
VI Va

e
va
I I
t PHL � � �� t PLH
I

I
VDD II
VDD II
2
- 0
(a) (b)

Operating
point at
t = 0+

I
I I
IE
Capacii or

I through QN l'
I discharge I
.-------_�

I I
I
Op � rating
II va

I I
Operating point

I
I t = O�
after switching
I p omt at
is completed
I AI
�____�--�--------�
D L- ________

(c) Cd)

fiGURE 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and out­
put waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN;
(d) equivalent circuit during the capacitor discharge.

HL indicates the high-to-low output transition), we can write

C[VDD - (VDD - Vt )]
� k� (�) ( VDD - vi
tpHL I

n
(4. 1 52)

l k ' (WL ) ( VDD Vt)2

2
n
n
_

Beyond point F, transistor QN operates in the triode region, and thus its current is given by
Eq. (4. 142). This portion of the discharge interval can be described by
344 CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STORS (MOS F ETs)

Substituting for iDN from Eq. (4.142) and rearranging the differential equation, we obtain

(4.153)

To find the component of the delay time tpHL during which Vo decreases from (VDD - V,) to
the 50% point, Vo = VDDI2, we integrate both sides of Eq. (4.153). Denoting this compo­
nent of delay time tpHLl> we find that

(4.154)

Using the fact that

I (3 VDDVDD- 4 Vt)
enables us to evaluate the integral in Eq. (4. 154) and thus obtain

tpHL2 =
C n (4.155)
kn, ( WIL M VDD - Vt )
The two components of tpHL in Eqs. (4.152) and (4.155) can be added to obtain

(4.156)

For the usual case of Vt = 0.2 VDD ' this equation reduces to

- 1.6C (4.157)
tPHL
k'(W
n IL) n VDD
Similar analysis of the turn-off process yields an expression for tpLH identical to that in
Eq. (4. 157) except for k�( WIL)n replaced with k;C WIL)r The propagation delay tp is the
average of tpHL and tPLH' From Eq. (4.157), we note that to obtain lower 'propagation delays
and hence faster operation, C should be minimized, a higher process transconductance param­
eter k' should be utilized, the transistor WI L ratio should be increased, and the power-supply
voltage VDD should be increased. There are, of course, design trade-offs and physical limits
involved in making choices for these parameter values. This subject, however, is too advanced
for our present needs .

t:���1�S!��:']����
. . , �W�2�·
. .
•��5' AilS; 0:8 ns; h. 8ns; 0.8ns '. .. . .

6 V\T ; S
: i
4.46 For the CMOS inverter fExercise4A2,. hich is intended orS l and MSI circlritapplications, find ip.
. .
if the load capacitance is 15 pF.
Ans. 6 ns
 4 . 1 0 T H E C M O S D I G ITAL LOG I C I NVERT E R 345

FIGURE 4.58 The current i n the CMOS

inverter versus the input voltage.

4.1 0.4 Current Flow and Power Dissipation

As the CMOS inverter is switched, current flows through the series connection of QN and
Qp. Figure 4.58 shows the inverter current as a function of VI' We note that the current peaks
at the switching threshold, Vth VI = Va V DDI 2 . This current gives rise to dynamic power
= =

dissipation in the CMOS inverter. However, a more significant component of dynamic power
dissipation results from the current that flows in QN and Qp when the inverter is loaded by a
capacitor C.
An expression for this latter component can be derived as follows: Consider once more
the circuit in Fig. 4.57(a). At t 0-, Va = VDD and the energy stored on the capacitor is
=

� C V1D' At t = 0, VI goes high to VDD, Qp turns off, and QN turns on. Transistor QN then dis­
charges the capacitor, and at the end of the discharge interval, the capacitor voltage is
reduced to zero. Thus during the discharge interval, energy of � CV�JD is removed from C
and dissipated in QN' Next consider the other half of the cycle when VI goes low to zero.
Transistor QN turns off, and Qp conducts and charges the capacitor. Let the instantaneous
current supplied by Qp to C be denoted i. This current is, of course, coming from the power
supply VDD. Thus the energy drawn from the supply during the charging period will be
S VDDi dt VDDS i dt = VDDQ, where Q is the charge supplied to the capacitor; that is, Q =
=

CVDD. Thus the energy drawn from the supply during the charging interval is CV�D' At the
end of the charging interval, the capacitor voltage will be VDD, and thus the energy stored in
it will be �CV1D' It follows that during the charging interval, half of the energy drawn from
the supply, � CV1D' is dissipated in Qp.
From the above, we see that in every cycle, �CV1D of energy is dissipated QN and
in
� CV�D dissipated Qp, for a total energy dissipation in the inverter of CV1D' Now if the
in
in
inverter is switched at the rate ofj cycles per second, the dynamic power dissipation it will be

2
PD = jCVDD (4. 158)

Observe that the frequency of operation is related to the propagation delay: The lower the
propagation delay, the higher the frequency at which the circuit can be operated and, accord­
ing to Eq. (4. 1 58), the higher the power dissipation in the circuit. A figure of merit or a quality
measure of the particular circuit technology is the delay-power product (DP),

(4. 1 59)
346 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STORS ( M OS F ETs)

The delay-power product tends to be a constant for a particular digital circuit technology
and can be used to compare different technologies. Obviously the lower the value of DP the
more effective is the technology. The delay-power product has the units of joules, and is in
effect a measure of the energy dissipated per cycle of operation. Thus for CMOS where
most of the power dissipation is dynamic, we can take DP as simply CV�>D'

4.4t'��r
�ns; L&mA
· 4A8'Let the iI1verter specified in ExerCise4.42 be loaded by a.i�-pl<capa:¢:itanc¢. Fl.Attcthedyfi amic tibWei�
. dissipation thatresults wheh the inverter is swi,tchedat a frequency of 2 MHz. What is':tlle avera'ge ...
current drawn from the 'power
-- supply?
-
. . . .. . . .. . . ..
-,' : �- . - , , , ' ,
-

Ans. 3 mW; 0.3 rnA

4.49 Consider� CMOS VLSI chip having 100,OOOgates Iabricatedin a 1.2-,uin CMOS teclinology. Letthe
load capacitaIlce per gate be 30 IE If the chip is operated from a 5- V supply and Is sWitcheda:t atateuf
. 100MHz, find (a) the power dissiPation per gate and (b) the total power dissipated in tile chipassiIming
.
that only 30% of the gates are switched at any one time. .
Ails. 75 pW; 2:25 W

4 . 1 0.5 Summary
In this section, we have provided an introduction to CMOS digital circuits. For convenient
reference, Table 4.6 provides a summary of the important characteristics of the inverter.
We shall return to this subject in Chapter 1 0, where a variety of CMOS logic circuits are
studied.

4.1 1 TH E DEPLETI O N -TYP E M OS FET

In this section we briefly discuss another type of MOSFET, the depletion-type MOSFET. Its
structure is similar to that of the enhancement-type MOSFET with one important difference:
The depletion MOSFET has a physically implanted channel. Thus an n-channel depletion­

O.
type MOSFET has an n-type silicon region connecting the n+ source and the n+ drain
regions at the top of the p-type substrate. Thus if a voltage VDS is applied between drain and
source, a current iD flows for VGS = In other words, there is no need to induce a channel,
unlike the case of the enhancement MOSFET.
The channel depth and hence its conductivity can be controlled by iJGS in exactly the
same manner as in the enhancement-type device. Applying a positive VGS enhances the chan­
nel by attracting more electrons into it. Here, however, we also can apply a negative VGS,
which causes electrons to be repelled from the channel, and thus the channel becomes shal­
lower and its conductivity decreases. The negative VGS is said to deplete the channel of its
charge carriers, and this mode of operation (negative vGs) is called depletion mode. As the
magnitude of VGS is increased in the negative direction, a value is reached at which the chan­
nel is completely depleted of charge carriers and iD is reduced to zero even though VDS
 4.1 1 T H E D E P LETIO N -TY P E M OS F ET 347

TABLE.4.6 ·· summ�rYOf rxrportaritchara<:t�tisticS oftheCfylOSLogk inverter.

l

Gate Output Resistance

/ [ k:(Z)n ( VDD - V,n ) ]

Bl When Va is low (current sinking) (Fig. 4.54) :

rDSN = 1

/ [k; (Z)p ( VDD - I V,pl )]

II When va is high (current sourcing) (Fig. 4.55 ) :

rDSP = l

Gate Threshold Voltage

Point on VTC at which Va = VI:

where

k; ( WIL)p
r =

k� ( WIL)n

Switching Current and Power Dissipation (Fig. 4.58)

(Z)n ,up(Z)p :
Noise Margins (Fig. 4.56)

For matched devices, that is, ,un =

Vth = VDD/2

VIL = �(3 VDD + 2 V, )

VIH = �( 5 VDD - 2 Vt)

NMH = NML = �(3 VDD + 2 V,)

Propagation Delay (Fig. 4.57)

For V, == O.2 VDD :

1 .6 C ·
tPLH -
=:
kp' ( W IL) p VDD
CHAPTER 4 MOS F I ELD- E F F ECT TRA N S I STORS ( M O S F ETs)

D D

G � ____----0 B G 0--1

FIGURE 4.59 (a) Circuit symbol for the n- channel

S S depletion-type MOSFET. (b) Simplified circuit
symbol applicable for the case the substrate (B) is
(a) (b) connected to the source (S).

may be still applied. This negative value of VGS is the threshold voltage of the n-channel
depletion-type MOSFET.
The description above suggests (correctly) that a depletion-type MOSFET can be oper­
ated in the enhancement mode by applying a positive VGS and in the depletion mode by
applying a negative VGS. The iD-vDS characteristics are similar to those for the enhancement
device except that Vt of the n-channel depletion device is negative.
Figure 4.59(a) shows the circuit symbol for the n-channel depletion-type MOSFET. This
symbol differs from that of the enhancement-type device in only one respect: There is a
shaded area next to the vertical line representing the channel, signifying that a physical
channel exists. When the body (B) is connected to the source (S), the simplified symbol
shown in Fig. 4.59(b) can be used.
The iD-vDs characteristics of a depletion-type n-channel MOSFET for which Vt = - 4 V
2
and k�(W IL) = 2 mA/V are sketched in Fig. 4.60(b). (These numbers are typical of dis­
crete devices.) Although these characteristics do not show the dependence of iD on VDS in
saturation, such dependence exists and is identical to the case of the . enhancement-type
device. Observe that because the threshold voltage Vt is negative, th� depletion NMOS
will operate in the triode region as long as the drain voltage does not exceed the gate
voltage by more than [ Vtl. For it to operate in saturation, the drain voltage must be
greater than the gate voltage by at least [ Vtl volts. The chart in Fig. 4.61 shows the rela­
tive levels of the terminal voltages of the depletion NMOS transistor for the two regions
of operation.
Figure 4.60(c) shows the iD-vGS characteristics in saturation, indicating both the deple­
tion and enhancement modes of operation.
The current-voltage characteristics of the depletion-type MOSFET are described by the
equations identical to those for the enhancement device except that, for an n-channel deple­
tion device, Vt is negative.
A special parameter for the depletion MOSFET is the value of drain current obtained in
saturation with VGS = O. This is denoted IDss and is indicated in Fig. 4.60(b) and (c). It can be
shown that

(4. 1 60)

Depletion-type MOSFETs can be fabricated on the same Ie chip as enhancement-type

devices, resulting in circuits with improved characteristics, as will be shown in a later
chapter.
 4. 1 1 T H E D E P L ET I O N -TYP E M O S F ET 349

� Depletion ---:*'E-- Enhancement �

mode mode

VDS :2: VGS - V,

iG = 0
-7>
G o>-----I
+

VGS
I
-4 3 -2 - 1 0
- 2 VGS (V)
V,
(a) (c)

36
32
28
24
20
lDSS 16
12
8
4
0
VGS :5 -4 V (V,)
(b)

FIG URE 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which
V, = -4 V and k�( W/L) 2 mA/V2; (a) transistor with current and voltage polarities indicated; (b) the iD-VDS
=

characteristics; (c) the iD-vGS characteristic in saturation.

 -,
.;� �
<---,

.
.
.• ..
.

>� ;;:
-:�
-�J
350 CHAPTER 4 M O S F I E LD-E F F ECT TRA N S I STORS ( M O S F ETs)

Voltage
II
II
Saturation

G ----
f
--'-
I Vt l D
D

II
Triode

Threshold
S
f I V, I
FIGURE 4.61 The relative levels of terminal
voltages of a depletion-type NMOS transistor
for operation in the triode and the saturation
regions. The case shown is for operation in the
enhancement mode (vGS is positive).

p-channel p-channel n-channel n-channel

enhancement depletion depletion enhancement

of both polarities (operating in saturation). Note that the characteristic curves inter�ect the VGS axis at V,.
FIGURE 4.62 Sketches of the iD-vGS characteristics for MOSFETs of enhancement and depletion types,

Also note that for generality somewhat ditferent values of [ V,I are shown for n-channel and p-channel
devices.

In the above, we have discussed only n-channel depletion devices. Depletion PMOS
transistors are available in discrete form and operate in a manner similar to their n-channel
counterparts except that the polarities of all voltages (including V,) are reversed. Also, in a
p-channel device, iD flows from source to drain, entering the source terminal and leaving
by way of the drain terminal. As a summary, we show in Fig. 4.62 sketches of the iD-vGS
characteristics of enhancement and depletion MOSFETs of both polarities (operating in
saturation).
 4. 1 2 T H E S P I C E M OS F ET M O D E L A N D S I M U LATI O N EXAM P L E 351

4.51 The depletion-type MOSFET in Fig. E4.51 has k�(WIL) 4 mAIV2 and V, = -2 V. What is the value
=

of IDss? Neglecting the effect of VDS on iD in the saturation region, find the voltage that will appear at the
source terminal.

+5 V

2 mA

FI(iURE E4.51

Ans. S mA; +1 v
4.52 Find i as a function of·vfor the circuit in Fig. E4.52: Neglectthe effect of vDS on iD in the �aturation
.. region.

4 . 1 2 T H E S P I C E M OS F ET M O D E L
A N D S I M U LATI O N EXA M P L E
We conclude this chapter with a discussion of the models that SPICE uses to simulate the
MOSFET. We will also illustrate the use of SPICE in the simulation of the CS amplifier
circuit.

4.1 2.1 MOS FET Models

To simulate the operation of a MOSFET circuit, a simulator requires a mathematical model
to represent the characteristics of the MOSFET. The model we have derived in this chapter to
represent the MOSFET is a simplified or first-order model. This model, called the square­
law model because of the quadratic i-v relationship in saturation, works well for transistors
with relatively long channels. However, for devices with short channels, especially submicron
transistors, many physical effects that we have neglected come into play, with the result that
the derived first-order model no longer accurately represents the actual operation of the
MOSFET.
p

352 CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STORS (MOS F ETs)

The simple square-law model is useful for understanding the basic operation of the
MOSFET as a circuit element and is indeed used to obtain approximate pencil-and-paper
circuit designs. However, more elaborate models, which account for short-channel effects,
are required to be able to predict the performance of integrated circuits with a certain degree
of precision prior to fabrication. Such models have indeed been developed and continue to
be refined to more accurately represent the higher-order effects in short-channel transistors
through a mix of physical relationships and empirical data. Examples include the Berkeley
short-channel IGFET model (BSIM) and the EKV model, popular in Europe. Currently, semi­
conductor manufacturers rely on such sophisticated models to accurately represent the fabri­
cation process. These manufacturers select a MOSFET model and then extract the values for
the corresponding model parameters using both their knowledge of the details of the fabri­
cation process and extensive measurements on a variety of fabricated MOSFETs. A great
deal of effort is expended on extracting the model parameter values. Such effort pays off in
fabricated circuits exhibiting performance very close to that predicted by simulation, thus
reducing the need for costly redesign.
Although it is beyond the scope of this book to delve into the subject of MOSFET model­
ing and short-channel effects, it is important that the reader be aware of the limitations of the
square-law model and of the availability of more accurate but, unfortunately, more complex
MOSFET models. In fact, the power of computer simulation is more apparent when one has
to use these complex device models in the analysis and design of integrated circuits.
SPICE-based simulators, like PSpice, provide the user with a choice of MOSFET models.
The corresponding SPICE model parameters (whose values are provided by the semiconductor
manufacturer) include a parameter, called LEVEL, which selects the MOSFET model to be
used by the simulator. Although the value of this parameter is not always indicative of the
accuracy, nor of the complexity of the corresponding MOSFET model, LEVEL = 1 corre­
sponds to the simplest first-order model (called the Shichman-Hodges model) which is
based on the square-law MOSFET equations presented in this chapter. For simplicity, we
will use this model to illustrate the description of the MOSFET model parameters in SPICE
and to simulate the example circuit in PSpice. However, the reader is again reminded of the
need to use a more sophisticated model than the level- 1 model to accurately predict the circuit
performance, especially for submicron transistors.

4.1 2.2 MOSFFT M od el Parameters

Table 4.7 provides a listing of some of the MOSFET model parameters used in the Level-1
model of SPICE. The reader should already be familiar with these parameters, except for a
few, which are described next.

MOSFET Diode Parameters For the two reverse-biased diodes formed between each of
the source and drain diffusion regions and the body (see Fig. 4.1) the saturation-current density
is modeled in SPICE by the parameter JS. Furthermore, based on the parameters specified in
Table 4.7, SPICE will calculate the depletion-layer (junction) capacitances discussed in

( (
Section 4.8.2 as

VDB) MJ )
CJ CJSW
cdb AD + PD (4. 161)
VDB MJSW
=

1+ 1+
PB .. PB

Csb = ( ��) MJ
1+
CJ
AS + ( �;) MJSW
1+
CJSW
PS (4. 162)
 4.1 2 T H E S P I C E M OS F ET M O D E L A N D S I M U LATI O N EXAM P L E 353

SPICE Book
Para meter Symbol Description Units

Basic Model Parameters

LEVEL MOSFET model selector
TOX Gate-oxide thickness m
COX Gate-oxide capacitance, per unit area F/m2
Carrier mobility 2
UO !1 cm /V, s
KP k' Process transconductance parameter A/V2
LAMBDA IL Channel-length modulation coefficient V- I

Threshold Voltage Parameters

VTO Zero-bias threshold voltage
GAMMA Body-effect parameter
NSUB Substrate doping
PHI Surface inversion potential

MOSFET Diode Parameters

JS Body-junction saturation-current density
CJ Zero-bias body-junction capacitance, per unit area
over the drain/source region
MJ Grading coefficient, for area component
CJSW Zero-bias body-junction capacitance, per unit length along F/m
the sidewall (periphery) of the drain/source region
MJSW Grading coefficient, for sidewall component
PB Body-junction built-in potential V

MOSFET Dimension Parameters

LD Lateral diffusion into the channel m
from the sourceldrain diffusion regions
WD Sideways diffusion into the channel m
from the body along the width

MOS Gate-Capacitance Parameters

CGBO Gate-body overlap capacitance, per unit channel length F/m
CGDO Gate-drain overlap capacitance, per unit channel width F/m
CGSO Gate-source overlap capacitance, per unit channel width F/m

where AD and AS are the areas while PD and PS are the perimeters of, respectively, the
drain and source regions of the MOSFET. The first capacitance term in Eqs. (4. 1 6 1 ) and
(4. 1 62) represents the depletion-layer (junction) capacitance over the bottom plate of the
drain and source regions. The second capacitance term accounts for the depletion-layer
capacitance along the sidewall (periphery) of these regions. Both terms are expressed using
the formula developed in Section 3 .7.3 (Eq. 3 .56). The values of AD, AS, PD, and PS must
'
be specified by the user based on the dimensions of the device being used.

MOSFET Dimension and Gate-Capacitance Parameters In a fabricated MOSFET,

the effective channel length Leff is shorter than the nominal (or drawn) channel length L
(as specified by the designer) because the source and drain diffusion regions extend slightly
354 C H A P T E R 4 M O S F I E LD- E F F ECT TRA N S I STORS ( M OS F ETs)

under the gate oxide during fabrication. Furthermore, the effective channel width Weff of the
MOSFET is shorter than the nominal or drawn channel width W because of the sideways diffu­
sion into the channel from the body along the width. Based on the parameters specified in
Table 4.7,
Leff = L - 2LD (4. 163)

�ff = W - 2WD (4. 164)

In a manner analogous to using Lov to denote LD, we will use the symbol Wov to denote WD.
Consequently, as indicated in Section 4.8 . 1 , the gate-source capacitance Cgs and the gate­
drain capacitance Cgd must be increased by an overlap component of, respectively,

CgS, ov = W CGSO (4. 165)

and

Cgd, ov = W CGDO (4. 166)

Similarly, the gate-body capacitance Cgb must be increased by an overlap component of

Cgb, ov = L CGBO (4. 167)

The reader may have observed that there is a built-in redundancy in specifying the
MOSFET model parameters in SPICE. For example, the user may specify the value of KP
for a MOSFET or, alternatively, specify TOX an4 UO and let SPICE compute KP as UO
TOX. Similarly, GAMMA can be directly specified, or the physical parameters that enable
SPICE to determine it can be specified (e.g., NSUB). In any case, the user-specified values
will always take precedence over (i.e., override) those values calculated by SPICE. As
another example, note that the user has the option of either directly specifying the overlap
capacitances CGBO, CGDO, and CGSO or letting SPICE compute them as CGDO = CGSO =

LD COX and CGBO = WD COX.

Table 4.8 provides typical values for the Level-l MOSFET model parameters of a modem
O.5-.um CMOS technology and, for comparison, those of an old (even obsolete) 5-.um CMOS
technology. The corresponding values for the minimum channel length Lmin, minimum channel
width Wmin, and the maximum supply voltage (VDD + I Vss l ) max are as follows:

Techn()logy (VDD + JVsslJ max

5-f.1rn CMOS 5 f.1rn 12.5 f.1rn lO V
O.5-f.1rn CMOS O.5 f.1rn 1 .25 f.1rn 3.3 V

Because of the thinner gate oxide in modem CMOS technologies, the maximum supply volt­
age must be reduced to ensure that the MOSFET terminal voltages do not cause a breakdown
of the oxide dielectric under the gate. The shrinking supply voltage is one of the most challenging
design aspects of analog integrated circuits in advanced CMOS technologies. From Table 4.8,
the reader may have observed some other trends in CMOS processes. For example, as Lmin is
reduced, the channel-length modulation effect becomes more pronounced and, hence, the value
of A increases. This results in MOSFETs having smaller output resistance ro and, therefore,
smaller "intrinsic gains" (Chapter 6). Another example is the decrease in surface mobility .u in
modem CMOS technologies and the corresponding increase in the ratio of .uJ.up, from 2 to
 4.12 T H E S P I C E M OS F ET M O D E L A N D S I M U LATI O N EXAM P L E 355

S-l1m CMOS Process O.S-l1m CMOS Process

NMOS PMOS NMOS PMOS
LEVEL
TOX 85e-9 85e-9 9.5e-9 9.5e-9
VO 750 250 460 1 15
LAMBDA 0.01 0.03 0. 1 0.2
GAMMA 1 .4 0.65 0.5 0045
VTO -1 0.7 -0.8
PHI 0.7 0.65 0.8 0.75
LD 0.7e-6 0.6e-6 0.08e-6 0.0ge-6
JS 1e-6 1e-6 lOe-9 5e-9
CJ 0.4e-3 0. 18e-3 0.57e-3 0.93e-3
MJ 0.5 0.5 0.5 0.5
CJSW 0.8e-9 0.6e-9 0.12e-9 0. 17e-9
MJSW 0.5 0.5 0.4 0.35
PB 0.7 0.7 0.9 0.9
CGBO 0.2e-9 0.2e-9 0.38e-9 0.38e-9
CGDO OAe-9 0.4e-9 0.4e-9 0.35e-9
CGSO 0.4e-9 0.4e-9 OAe-9 0.35e-9
1 In PSpice, we have created MOSFET parts corresponding to the above models. Readers can find these parts in the
SEDRA.olb library, which is available on the CD accompanying this book as well as on-line at www.sedrasmith.org.
The NMOS and PMOS parts for the O.5-pm CMOS technology are labelled NMOSOP5_BODY and PMOSOP5_BODY,
respectively. The NMOS and PMOS parts for the 5-,um CMOS technology are labelled NMOS5PO_BODY and
PMOS5PO_BODY, respectively. Furthermore, parts NMOSOP5 and PMOSOP5 are created to correspond to, respectively,
part NMOSOP5_BODY with its body connected to net 0 and part PMOSOP5_BODY with its body connected to net VDD.

close to 5. The impact of this and other trends on the design of integrated circuits in advanced
CMOS technologies are discussed in Chapter 6 (see in particular Section 6.2).
When simulating a MOSFET circuit, the user needs to specify both the values of the
model parameters and the dimensions of each MOSFET in the circuit being simulated. At
least, the channel length L and width W must be specified. The areas AD and AS and the
perimeters PD and PS need to be specified for SPICE to model the body-junction capaci­
tances (otherwise, zero capacitances would be assumed). The exact values of these geometry
parameters depend on the actual layout of the device (Appendix A). However, to estimate
these dimensions, we will assume that a metal contact is to be made to each of the source
and drain regions of the MOSFET. For this purpose, typically, these diffusion regions must
be extended past the end of the channel (i.e., in the L-direction in Fig. 4 . 1 ) by at least
2.75 Lmin. Thus, the minimum area and perimeter of a drain/source diffusion region with a
contact are, respectively,
AD = AS = 2.75LminW (4. 1 68)
and
PD = PS = 2 X 2.75Lmin +W (4. 1 69)
Unless otherwise specified, we will use Eqs. (4. 168) and (4. 1 69) to estimate the dimensions
of the drain/source regions in our examples.
Finally, we note that SPICE computes the values for the parameters of the MOSFET
small-signal model based on the de operating point (bias point). These are then used by
SPICE to perform the small-signal analysis (ac analysis).
356 CHAPTER 4 M O S F I E LD-E F F ECT TRA N S I STORS ( M OS F ETs)

THE CS AMPLIFIER
In this example, we will use PSpice to compute the frequency response of the C S amplifier whose
Capture schematic is shown in Fig. 4.63 Y Observe that the MOSFET has its source and body
connected in order to cancel the body effect. We will assume a 0.5-.um CMOS technology for the
MOSFET and use the SPICE level-1 model parameters listed in Table 4.8. We will also assume a
signal-source resistance Rsig 10 kQ, a load resistance RL = 50 kQ, and bypass and coupling
=

capacitors of 10 .uP. The targeted specifications for this CS amplifier are a midband gain AM =
10 VN and a maximum power consumption P = 1 .5 mW. As should always be the case with
computer simulation, we will begin with an approximate pencil-and-paper design. We will then
use PSpice to fine-tune our design, and to investigate the performance of the final design. In this
way, maximum advantage and insight can be obtained from simulation.
With a 3.3-V power supply, the drain current of the MOSFET must be limited to [D =

P/VDD = 1 .5 mW /3.3 V = 0.45 rnA to meet the power consumption specification. Choosing
Vov= 0.3 V (a typical value in low-voltage designs) and VDS = VDD / 3 (to achieve a large signal
swing at the output), the MOSFET can now be sized as

0.45 X 10-3 == 53 (4. 170)

.
� ( l70.1 x 10-6 )(0.3) 2 [ 1 + 0. 1 ( 1 . 1 )]

where k� = .unC ox = 170. 1 .uAN2 (from Table 4.8). Here, Leff rather than L is used to more accu­
rately compute [D. The effect of using Weff rather than W is much less important because typically
W � Wov. Thus, choosing L 0.6 .um results in Leff L - 2Lov= 0.44 .um and W = 23.3 .urn. Note
= =

that we chose L slightly larger than Lmin• This is a common practice in the design of analog ICs to
minimize the effects of fabrication nonidealities on the actual value of L. As we will study in later
chapters, this is particularly important when the circuit performance depends on the matching
between the dimensions of two or more MOSFETs (e.g., in the current-mirror circuits we will study
in Chapter 6).
Next, RD is calculated based on t�e desired voltage gain:

(4. 171)

where gm = 3.0 mAN and ro = 22.2 kQ. Hence, the output bias voltage is Vo = VDD - [DRD ==

1 .39 V. An Rs = ( Vo - VDD/3)/[D = 630 Q is needed to bias the MOSFET at a VDS VDD/3 . =

Finally, resistors RGI = 2 MQ and RG2 = 1 .3 MQ are chosen to set the gate bias voltage at
VG = [DRs + VOV + Vtn 1.29 V. Using large values for these gate resistors ensures that both
'"

their power consumption and the loading effect on the input signal source are negligible. Note
that we neglected the body effect in the expression for VG to simplify our hand calculations.
We will now use PSpice to verify our design and investigate the performance of the CS
amplifier. We begin by performing a bias-point simulation to verify that the MOSFET is properly

1 1 The
reader is reminded that the Capture schematics and the corresponding PSpice simulation files
of all SPICE examples in this book can be· found on the text's CD as well as on its website
(www.sedrasmith.org). In these schematics (as· shown in Fig. 4.63), we used variable parameters to
enter the values of the various circuit components, including the dimensions of the MOSFET. This
will allow the reader to investigate the effect of changing component values by simply changing the
corresponding parameter values.
 4. 1 2 T H E S P I C E M O S F ET M O D E L A N D S I M U LATI O N EXAM P L E 357

�
VDD VDD

PARAMETERS:
eel = lOu { RGl } { RD }
ceo = lOu { CCO }
OUT
es = lOu
RD = 4.2K {CCl}

=
VDD IN { Rsig}

1l
RGl = 2E6 { RL }
W = {W}
RG2 = 1 .3E6
L {L}
RL = 50K

r
-= 0
RS = 630 I Vac
Rsig = 10K DC � { VDD)
OVdc
W = 22u {CS)
L = 0.6u
VDD = 3.3 -= 0
o -= 0

F!GURE 4.63 Capture schematic of the CS amplifier in Example 4. 14.

biased in the saturation region and that the dc voltages and currents are within the desired specifi­
cations. Based on this simulation, we have decreased the value of W to 22 pm to limit ID to about
0.45 mAo Next, to measure the midband gain AM and the 3-dB frequencies fL andfH' we apply a I -V
ac voltage at the input, perform an ac-analysis simulation, and plot the output voltage magnitude
(in dB) versus frequency as shown in Fig. 4.64. This corresponds to the magnitude response of
12
the CS amplifier because we chose a I -V input signal. Accordingly, the midband gain is AM =

9.55 V/V and the 3-dB bandwidth is BW =fH fL = 1 22. 1 MHz. Figure 4.64 further shows that
-

the gain begins to fall off at about 300 Hz but flattens out again at about 10 Hz. This flattening in
the gain at low frequencies is due to a real transmission zero13 introduced in the transfer function
of the amplifier by Rs together with Cs. This zero occurs at a frequency fz = 1 /(2nRsCs ) =

25.3 Hz, which is typically between the break frequencies fpz and fp3 derived in Section 4.9.3
(Fig. 4.52). So, let u s now verify this phenomenon by resimulating the CS amplifier with a
es 0 (i.e., removing Cs) in order to move fz to infinity and remove its effect. The correspond­
ing frequency response is plotted also in Fig. 4.64. As expected, with Cs = 0, we do not
=

observe any flattening in the low-frequency response of the amplifier, which now looks simi­
lar to that in Fig. 4.52. However, because the CS amplifier now includes a source resistor Rs,
AM has dropped by a factor of 2.6. This factor is approximately equal to ( 1 + gn!?s) , as
expected from our study of the CS amplifier with a source-degeneration resistance in Sec­
tion 4.7.4. Note that the bandwidth B W has increased by approximately the same factor as the
drop in gain AM. As we will learn in Chapter 8 when we study negative feedback, the source­
degeneration resistor Rs provides negative feedback, which allows us to trade off gain for
wider bandwidth.

12 The reader should not be alarmed about the use of a such a large signal amplitude. Recall (Sec­
tion 2.9. 1) that in a small-signal (ac) simulation, SPICE first finds the small-signal equivalent circuit
at the bias point and then analyzes this linear circuit. Such ac analysis can, of course, be done with
any ac signal amplitude. However, a I-V ac input is convenient to use as the resulting ac output corre­
sponds to the voltage gain of the circuit.
1 3 Readers who have not yet studied poles and zeros can either refer to Appendix E or skip these few
sentences.
358 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STORS ( M O S F ETs)

15

10

100m 1.0 10 100 1 .0K 10K lOOK 1.0M 10M 100M LOG
a 0 dB (V(OUT))
Frequency (Hz)

FIGURE 4.64 Frequency response of the CS amplifier in Example 4.14 with Cs = 10 f.1F and Cs = 0 (i.e.,
Cs removed).

To conclude this example, we will demonstrate the improved bias stability achieved when a
source resistor Rs is used (see the discussion in Section 4.5.2). Specifically, we will change (in the
MOSFET level- l model for part NMOSOP5) the value of the zero-bias threshold yoltage parame­
ter VTO by ±l5% and perform a bias-point simulation in PSpice. Table 4.9 shows the correspond­
ing variations in ID and Vo for the case in which Rs 630 Q. For the case without source
=

degeneration, we use an Rs = 0 in th.e schematic of Fig. 4.63. Furthermore, to obtain the same ID
and Vo in both cases (for the nominal threshold voltage Vto 0.7 V), we use an R�2 0.88 MQ to
= =

reduce VG to around Vov + Vtn 1 V. The corresponding variations in the bias point are shown
=

in Table 4.9. Accordingly, we see that the source degeneration resistor makes the bias point of the
CS amplifier less sensitive to changes in the threshold voltage. In fact, the reader can show for the
values displayed in Table 4.9 that the variation in bias current (/':,.1/1) is reduced by approxi­
mately the same factor, ( l + grfis). However, unless a large bypass capacitor Cs is used, this
reduced sensitivity comes at the expense of a reduction in the midband gain (as we observed in
this example when we simulated the frequency response of the CS amplifier with a Cs 0). =

Rs= 630 0 Rs = O
Vtno ID (mA) Vo (V) ID (mA) Vo (V)
0.60 0.56 0.962 0.71 0.33
0.7 0.46 1 .39 0.45 1 .40
0.81 0.36 1.81 0.21 2.40
 S U M MA RY 359

S U M M A RY

Ij The enhancement-type MOSFET is currently the most high frequencies; and the common-drain or source-follower
widely used semiconductor device. It is the basis of configuration, which is employed as a voltage buffer or as
CMOS technology, which is the most popular IC fabri­ the output stage of a multistage amplifier. Refer to the
cation technology at this time. CMOS provides both n­ summary at the end of Section 4.7, and in particular to
channel (NMOS) andp-channel (PMOS) transistors, which Table 4.4, which provides a summary and a comparison of
increases design flexibility. The minimum MOSFET the attributes of the various single-stage MOSFET ampli­
channel length achievable with a given CMOS process is fier configurations.
used to characterize the process. This figure has been con­
tinually reduced and is currently about f.1m.
0.1 Ii For the MOSFET high-frequency model and the formulas
for determining the model parameters, refer to Table 4.5.
Ij The current-voltage characteristics of the MOSFET are
presented in Section 4.2 and are summarized in Table 4. 1 . Ii The internal capacitances of the MOSFET cause the gain
of MOS amplifiers to fall off at high frequencies. Also, the
• Techniques for analyzing MOSFET circuits at dc are coupling and bypass capacitors that are used in discrete
illustrated in Section 4.3 via a number of examples. MOS amplifiers cause the gain to fall off at low frequen­
cies. The frequency band over which both sets of capaci­
Ij The large-signal operation of the basic common-source tors can be neglected, and hence over which the gain is
(CS) resistively loaded MOSFET is studied in Section 4.4. constant, is known as the midband. The amplifier frequency
The voltage transfer characteristic is derived, both graphi­ response is characterized by the midband gain AM and the
cally and analytically, and is used to show the three lower and upper 3-dB frequenciesfL andfH, respectively,
regions of operation: cutoff and triode, which are useful and the bandwidth is (fH 1£).
for the application of the MOSFET as a switch and as a -

digital logic inverter; and saturation, which is the region III Analysis of the frequency response of the common source
for amplifier operation. To obtain linear amplification, the amplifier (Section 4.9) shows that its high-frequency re­
transistor is biased to operate somewhere near the middle sponse is determined by the interaction of the total input
of the saturation region, and the signal is superimposed on capacitanceCin and the effective resistance of the signal
the dc bias VGS and kept small. The small-signal gain is source,
R;ig; 1I2 nCinR ;ig .
fH = The input capacitance
equal to the slope of the transfer characteristic at the bias Cin Cgs (1 gmR{) Cgd ,
= + + which can be dominated by the
point (see Fig. 4.26). second term. Thus, while
Cgd is small, its effect can be
very significant because it is multiplied by a factor ap­
Ii A key step in the design of transistor amplifiers is to bias proximately equal to the midband gain. This is the Miller
the transistor to operate at an appropriate point in the sat­ effect.
uration region. A good bias design ensures that the param­
eters of the bias point, [D' Vov, and VDS, are predictable and III The CMOS digital logic inverter provides a near-ideal
stable, and do not vary by a large amount when the tran­ implementation of the logic inversion function. Its charac­
sistor is replaced by another of the same type. A variety teristics are studied in Section 4.10 and summarized in
of biasing methods suitable for discrete-circuit design are Table 4.6.
presented in Section 4.5.
III The depletion-type MOSFET has an implanted channel
Ii The small-signal operation of the MOSFET as well as cir­ and thus can be operated in either the depletion or en­
cuit models that represent it are covered in Section 4.6. hancement modes. It is characterized by the same equa­
A summary of the relationships for determining the tions used for the enhancement device except for having a
values of MOSFET model parameters is provided in negative V, (positive V, fof depletion PMOS transistors).
Table 4.2.
III Although there is no substitute for pencil-and-paper cir­
Ii Grounding one of the three terminals of the MOSFET re­ cuit design employing simplified device models, computer
sults in a two-port network with the grounded terminal simulation using SPICE with more elaborate, and hence
serving as a common terminal between the input and out­ more precise, IIfodels is essential for checking and fine­
put ports. Accordingly, there are three basic MOSFET tuning the design before fabrication.
amplifier configurations: the CS configuration, which is
the most widely used; the common-gate (CG) configuration, III Our study of MOSFET amplifiers continues in Chapter 6
which has special applications and is particularly useful at and that of digital CMOS circuits in Chapter 10.
360 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STO RS (MOSFETs)

PROBLEMS
S E C T I O N 4 . 1 : D E V I C E S T R U CT U R E A N D in the following cases:
P H YS I C A L O P E R A T I O N
(a) VCS = 5 V and VDS = 1 V
4.1 MOS technology is used to fabricate a capacitor, utiliz­ (b) VCS = 2 V and VDS = 1.2 V
ing the gate metallization and the substrate as the capacitor (c) VCS = 5 V and VDS = 0.2 V
electrodes. Find the area required per 1-pF capacitance for (d) VCS = VDS = 5 V
oxide thickness ranging from 5 nm to 40 nm. For a square
plate capacitor of 10 pF, what maximum dimensions are
S ECTION 4.2: CURRE NT-VOLTAGE CHARACT E R I STICS
needed?
4 . 8 Consider an NMOS transistor that is identical to, except
4.2 A particular MOSFET using the same gate structure and for having half the width of, the transistor whose iD-VDS charac­
channel length as the transistor whose iD-vDS characteristics teristics are shown in Fig. 4.1 1 (b). How should the vertical axis
are shown in Fig. 4.4 has a channel width that is 10 times be relabeled so that the characteristics correspond to the nar­
greater. How should the vertical axis be relabelled to repre­ rower device? If the narrower device is operated in saturation
sent this change? Find the new constant of proportionality with an overdrive voltage of 1.5 V, what value of iD results?
relating iD and (vcs - V,)VDS' What is the range of drain-to­
source resistance, rDS, corresponding to an overdrive voltage 4 . 9 Explain why the graphs in Fig. 4.1 1(b) do not change as V,
(vcr V,) ranging from 0.5 V to 2 V? is changed. Can you devise a more general (i.e., V, independent)
representation of the characteristics presented in Fig. 4.12?
4 . 3 With the knowledge that I1p O .4l1n' what must be
""
the relative width of n-channel and p-channel devices if 4 . 1 0,For the transistor whose iD-vcs characteristics are
they are to have equal drain currents when operated in the depicted in Fig. 4.12, sketch iD versus the overdrive voltage Vov ==
saturation mode with overdrive voltages of the same VCS - V, for VDS 2': Vov. What is the advantage of this graph over
magnitude? that in Fig. 4.12? Sketch, on the same diagram, the graph for a

4 . 4 An n-channel device has k� = 50 I1A/V , V, = 0.8 V,

2 device that is identical except for having half the width.
and WIL = 20. The device is to operate as a switch for small 4 . 1 1 An NMOS transistor having V, = 1 V is operated in the
VDS' utilizing a control voltage VCS in the range 0 V to 5 V. triode region with VDS small. With Vcs = 1 .5 V, it is found to
have a resistance rDS of 1 kQ. What value of Vcs is required to
obtain rDS = 200 Q? Find the corresponding res�stance values
Find the switch closure resistance, rDS, and closure voltage,
VDS' obtained when vcs = 5 V and iD = 1 rnA Recalling that
.

I1p O .4l1m what must WIL be for a p-channel device that

"" obtained with a device having twice the value of W.
provides the same performance as the n-channel device in 4.1 2 A particular enhancement MOSFET for which V, =
this application? 1 V and k�'(WIL) = 0.1 mAIV2 is to be operated in the satura­
4 . 5 An n-channel MOS device in a technology for which tion region. If iD is to be 0.2 find the required vcs and the
rnA ,

oxide thickness 2is 20 urn, minimum gate length is 1 11m, minimum required VDS' Repeat for iD = 0.8 rnA.
k� = 100 I1A/V , and V, = 0.8 V operates in the triode
4.1 3 A particular n-channel enhancement MOSFET is mea­
region, with small VDS and with the gate-source voltage in the sured to have a drain current of 4 at Vcs = VDS = 5 V and of
rnA
range 0 V to +5 V. What device width is needed to ensure that 1 rnA at Vcs = VDS = 3 V. What are the values of k� (WIL) and V,
the minimum available resistance is 1 ill?
for this device?

15 nm, I1n = 550 cm2/V . s, and V, = 0.7 V.

4.6 Consider a CMOS process for which Lmin 0.8 11m, tax =
=

D 4 . 1 4 For a particular IC-fabrication process, the trans­

conductance parameter k� = 50 I1A/V2, and V, = 1 V. In an
(a) Find Cox and k� . application in which Vcs = VDS = Vsupply ='5 V, a drain current
(b) For an NMOS transistor with WIL = 16 I1m/0.8 11m, calcu­ of 0.8 rnAis required of a device of minimum length of 2 J1ill.
late the values of Vov, Vcs, and VDSmin needed to operate the What value of channel width must the design use?
transistor in the saturation region with a dc current ID = 100 11A.
region with VDS = 0.1 V, is found to conduct 60 J1A for Vcs =
4 . 1 5 An NMOS transistor, operating in the linear-resistance
(c) For the device in (b), find the value of Vov and Vcs
2 V and 160 I1A for VCS = 4 V. What is the apparent value of
required to cause the device to operate as a 1000-Q resistor
threshold voltage V,? If k� = 50 I1A!V2 , what is the device
for very small VDS'
4 . 7 Consider an n-channel MOSFET with tax = 20 nm, I1n = WIL ratio? What current would you expect to flow with Vcs =
650 cm2/V . s, V, = 0.8 V, and WIL = 10. Find the drain current 3 V and VDS = 0. 15 V? If the device is operated at VCS = 3 V, at
 PROBLEMS , 361

what value of VDS will the drain end of the MOSFET channel
about i of that needed. What dimensional change can be
100 JiA is found to have an output resistance of 0.5 MQ,
just reach pinch off, and what is the corresponding drain
current? made to solve the problem? What is the new device length?
The new device width? The new W/L ratio? What is VA for the
4 . 1 6 For an NMOS transistor, for which V, = 0.8 V, operat­
standard device in this IC? The new device?
ing with VCS in the range of 1.5 V to 4 V, what is the largest
value of VDS for which the channel remains continuous? 0 4 . 2 2 For a particular n-channel MOS technology, in
4 . 1 1 An NMOS transistor, fabricated with W = 100 pm and which the minimum channel length is 1 pm, the associated
L =5 pm in a technology for which k� = 50 pANz and V, = value of A is 0.02 y-l . If a particular device for which L is
1 V, is to be operated at very low values of VDS as a linear resis­ 3 pm operates at VDS = 1 V with a drain current of 80 fiA, what
tor. For VCS varying from 1 . 1 V to 1 1 V, what range of resistor does the drain current become if VDS is raised to 5 V? What
values can be obtained? What is the available range if percentage change does this represent? What can be clone to
reduce the percentage by a factor of 2?
(a) the device width is halved?
(b) the device length is halved? 4.. 2 3 An NMOS transistor is fabricated in a 0.8-Jim process
(c) both the width and length are halved? having k� = 130 JiANz and V� = 20 V/Jim of channel
length. If L = 1 .6 Jim and W = 16 Jim, find VA and A. Find
4. 1 8 When the drain and gate of a MOSFET are connected the value of ID that results when the device is operated with
together, a two-terminal device known as a "diode-connected an overdrive voltage of 0.5 V and VDS = 2 V. Also, find
transistor" results. Figure P4. 1 8 shows such devices obtained the value of ro at this operating point. If VDS is increased by
from MOS transistors of both polarities. Show that 1 V, what is the corresponding change in ID?
(a) the i-v relationship is given by 4 . 2 4 Complete the missing entries in the following table,
which describes characteristics of suitably biased NMOS
transistors:

(b) the incremental resistance r for a device biased to operate

MOS 2 3 4
at v = I V,I + Vov is given by
.Ii, (V-I ) 0.01
VA (V) 50 200
ID (mA) 5 0.1
ro (kO) 30 100 1000
+
4 . 2 5 An NMOS transistor with A = 0.01 V-I is operating at
a dc current D = 1 mAo If the channel length is doubled, find
I
v v the new values of A, VA' ID, and ro for each of the following
two cases:
(a) Vcs and VDS are fixed.
(b) ID and VDS are fixed.
(a) (b)
4 . 2 6 An enhancement PMOS transistor has k;( WIL) =
2
FIGURE P4.1 8 80 JiAIV , V, = -1.5 V, and A = -0.02 y-l . The gate is con­
nected to gronnd and the source to +5 V. Find the drain current
4 . 1 9 For a particular MOSFET operating in the satura­ for VD = +4 V, + 1.5 V, 0 V, and -5 V.
tion region at a constant VCS' iD is found to be 2 mA for VDS =
4 V and 2.2 mA for VDS = 8 V. What values of rO' VA' and A 4 . 2 7 A p-channel transistor for which I Vtl 1 V and I VAI =
=

correspond? 50 V operates in saturation with I vcsI = 3 V, I vDsl = 4 V, and

iD = 3 mAo Find corresponding signed values for VCS, Vsc, VDS'
4 . 2 0 A particular MOSFET has VA = 50 V. For operation at VSD, V"� VA' A, and k; (W/L).
0.1 mA and 1 mA, what are the expected output resistances?
In each case, for a change in VDS of 1 V, what percentage 4 . 2 8 In a technology for which the gate-oxide thickness is
change in drain current would you expect? 20 nm, fmd the value ofNA for which r = 0.5 V 112. If the doping
level is maintained but the gate oxide thickness is increased to
III 4 . 2 1 In a particular IC design in which the standard channel 100 nm, what does r become? If r is to be kept constant at
length is 2 pm, an NMOS device with WIL of 5 operating at 0.5 V I12, to what value must the doping level be changed?
362 C H A P T E R 4 M O S F I ELD-E F F ECT TRAN S I STORS ( M O S F ETs)

4.29 In a particular application, an n-channel MOSFET + lO V +1 V +1 V

L
operates with VSB in the range 0 V to 4 V. If V,o is nominally
1.0 V, find the range of V, that results if y = 0.5 V 1I2 and 2¢! =
0 .6 V. If the gate oxide thickness is increased by a factor of 4,
what does the threshold voltage become?
4.30 A p-channel transistor operates in saturation with its
source voltage 3 V lower than its substrate. For y 0.5 V I12,
=

2¢! = 0.75 V, and V,o = -0.7 V, find V,.

* 4 . 3 1 (a) Using the expression for iD in saturation and
neglecting the channel-length modulation effect (i.e., let A = 0),
derive an expression for the per unit change in iD per °C -9 V
[(aiDliD)/ aT] in terms of the per unit change in k� per °C
[( ak� Ik� )IaT] the temperature coefficient of V, in V1°C (a) (b)
(aV,I aT), and VGS and V"
(b) If V, decreases by 2 mV for every °C rise in temperature,
find the temperature coefficient of k� that results in iD
decreasing by O.2%/OC when the NMOS transistor with V, = 1 V + lO V +5 V
is operated at VGs = 5 V.
*4.32 Various NMOS and PMOS transistors are measured
in operation, as shown in the table at the bottom of the page.
For each transistor, find the value of f.1CoxWIL and V, that
apply and complete the table, with V in volts, I in f.1A, and
f.1CoxWIL in f.1A/V2'.
*4 . 3 3 All the transistors in the circuits shown in Fig. P4.33
have the same values of l V,I , k', WIL, and A. Moreover, A is
negligibly small. All operate in saturation at ID = I and
I V Gsl = I VDsl = 3 V. Find the voltages VI' Vz, V3, and V4• If -5 V
I V,I = I V and I = 2 rnA how large a resistor can be
,
(c) (d)
inserted in series with each drain connection while maintain­
ing saturation? What is the largest resistor that can be placed FIGURE P4.33
in series with each gate? If the current source I requires at
least 2 V between its terminals to operate properly, what is
the largest resistor that can be placed in series with each S E C T I O N 4 . 3 : M O S F E T C I R C U I T S AT D C
MOSFET source while ensuring saturated-mode operation of D 4 . 3 4 Design the circuit of Fig. 4.20 to establish a drain
each transistor at ID = I? In the latter limiting situation, what current of 1 rnA and a drain voltage of 0 V. The MOSFET has
do VI' Vz, V3, and V4 become? V, = I V, f.1nCox = 60 f.1A/V2, L = 3 f.1m, and W = 100 f.1m.

Vs VG VD ID
;

Case Transistor Type Mode f.1Co"WIL Vt

a 0 2 5 100
0 3 5 400
b 2 5 3 -4.5 50
2 5 2 -0.5 450
c 3 5 3 4 200
3 5 2 0 800
d 4 -2 0 0 72
4 -4 0 -3 270
1>4.3 5 Consider the circuit of Fig. E4.12. Let QI and Qz have Find the required values of gate width for each of Qjo
2
V, == 0.6 V, J.1nCox 200 J.1A1V , LI Lz 0.8 J.1m, WI == 8 J.1m,
== == == Qz, and Q3 to obtain the voltage and current values
and ,1, == O. indicated.

(a) Find the value of R required to establish a current of

+S V
0.2 mA in QI ·
(b) Find Wz and a new value for Rz so that Qz operates in the
saturation region with a current of O.S mA and a drain voltage
of 1 V.

I> 4 . 3 6 The PMOS transistor in the circuit of Fig. P4.36 has ,-----+--0 + 3.S V
2
V, == -0.7 V, J.1pCox 60 J.1A1V , L 0.8 J.1m, and ,1, == O. Find
== ==

the values required for W and R in order to establish a drain

.----+--0 + 1 .S V
current of l IS J.1A and a voltage VD of 3.S V.

VDD = S V

FIGURE P4.38
4 . 3 9 Consider the circuit of Fig. 4.23(a). In Example 4.S it
2
was found that when V, = 1 V and k�(W/L) = 1 mAIV , the
drain current is O.S rnA and the drain voltage is +7 V. If the tran­
sistor is replaced with another having V, == 2 V and k�(W/L) =

2 mAlV2, find the new values of ID and VD. Comment on how

FIGURE P4.36 tolerant (or intolerant) the circuit is to changes in device
parameters .
D 4 . : n The NMOS transistors in the circuit of Fig. P4.37
2 D 4 .41) Using an enhancement-type PMOS transistor with V,
have V, 1 V, J.lnCox == 1 20 J.1A1V , ,1, == 0, and LI Lz 1 J.1m.
=

2
- 1 .S V, k; (W/L) == 1 mAIV , and A 0, design a circuit that
== == =

Find the required values of gate width for each of QI and Qz,
=

resembles that in Fig. 4.23(a). Using a 10-V supply design for

and the value of R, to obtain the voltage and current values
indicated.
a gate voltage of +6 V, a drain current of O.S rnA
, and a drain
voltage of +S V. Find the values of Rs and RD.

4 . 4 1 The MOSFET in Fig. P4.41 has V, == 1 V, k� = 100 f.1AJ

+S V 2
V , and A == O. Find the required values of W/L and of R so
that when VI== VDD == +S V, rDs = SO n, and Vo == SO mV.

,---��--o + 3.S V

R
r-�+----o + 1.S V

FIGURE P4.37
0 4 . 3 8 The NMOS transistors in the circuit of Fig. P4.38 have
V, 1 V, J.lnCox = 120 J.1A1V2 , ,1, = 0, and LI = Lz = Lz 1 J.1ffi.
== = FIGURE P4.41
364 CHAPTER 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

4 .42 In the circuits shown in Fig. P4.42, transistors are +5 V +5 V

characterized by I V,I = 2 V, k'WIL = 1 mA/V2, and .Ie = O.

(a) Find the labelled voltages VI through V7•

(b) In each of the circuits, replace the current source with a
resistor. Select the resistor value to yield a current as close to
that of the current source as possible, while using resistors
specified in the 1 % table provided in Appendix G. Find the
new values of VI to V7·
100 pA
+ lO V

(a) (b)

+ lO V +5 V

�--o V3

2 rnA 1 rnA

- lO V (c) (d)
(a) (b)
+5 V
+ lO V
+ lO V

2 mA
r---+---o Vti

(f)

+5 V

- 10 V
r VB

(c) l OO k!!

F i G U R E P4042
-5 V
4 . 4 3 For each of the circuits in Fig. P4.43, find the labeled
node voltages. For all transistors, k�(WIL) = 0.4 mAIV2 , V, = (g) (h)
1 V, and .le = O. F I G U R E P4.43
 PROBLEMS 365

4.44 For each of the circuits shown in Fig. P4.44, find the +3 V +3 V
labeled node voltages. The NMOS transistors have VI = 1 V
and k� W/L = 2 rnAN2. Assume A = 0.

�h
+ lO V

+ lO V
V4

L
+5 V 1 kO
V2
V3

VI -

V4

r
(a) (b)

V2 Vs
+3 V

1 kO
1 kO

16
-5 V
Vs
(a) (b)
FIGURE P4.44
2
* 4 . 4 5 For the PMOS transistor in the circuit shown in
Fig. P4.45, k; = 8 JiAIV , W/L = 25, and / VIPI = 1 V. For
1 = 100 JiA, find the voltages VSD and VSG for R = 0, 10 kn,
30 kn, and 1 00 kn. For what value of R is VSD = VSG? VSD = (c)
VSG12? VSD = VSG/lO?
FIGURE P4.46
+ lO V
* 4 . 4 7 For the devices in the circuits of Fig. P4.47, / VII =
1 V, A = 0, Y= 0, JinCox = 50 J1A!V2, L = 1 Jim, and W = 10 Jim.
Find V2 and 12, How do these values change if Q3 and Q4 are
made to have W = 100 Jim?

+5 V

FIGURE P4.45
4 .4 6 For the circuits in Fig. P4.46, JinCox = 2.5 JipCox =
2
20 JiAIV , / VII = 1 V, A = 0, Y = 0, L = 10 Jim, and W =
30 Jim, unless otherwise specified. Find the labeled currents
and voltages. FIGURE P4.47
 366 C H A P T E R 4 M O S F I E L D - E F F ECT TRA N S I STO RS ( M O S F ETs)

4 . 48 In the circuit of Fig. P4.48, transistors Qj and Q2 have giving the values of ID (rnA), Vav (V), Ves V1Q (V),Av (v1V),
=

V, = 1 V, and the process transconductance parameter k� = the magnitude of the largest allowable positive-output signal v+
100 1lAIV2 • Assuming A = 0, find Vj, Vb and V3 for each of (V), and the magnitude of the largest allowable negative-ou:­
the following cases: put signal v� (V) for values of VDS = VaQ in therange of 1 V to

VDS = 1 V, 2 V, 3 V, . . . , 10 V). Note that v; is determined by

10 V, in increments of 1 V (i.e., there should be table rows for
(a) ( WIL)j = ( WILh 20
=

(b) ( WIL)j = 1.S(WIL)2 = 20 the MOSFET entering cutoff and v� by the MOSFET enter­
+S V ing the triode region.
4 .5 1 Various measurements are made on an NMOS ampli­
fier for which the drain resistor RD is 20 ill . First, dc mea­
surements show the voltage across the drain resistor, VRD, to
be 2 V and the gate-to-source bias voltage to be 1 .2 V. Then,
ac measurements with small signals show the voltage gain to
be -10 VIV. What is the value of V, for this transistor? If the
process transconductance parameter k� is SO IlAIV2 , what is
the MOSFET's W/L?
* D 4 . 5 :2 Refer to the expression for the incremental voltage
gain in Eq. (4.41). Various design considerations place a lower
limit on the value of the overdrive voltage Vav. For our purposes
here, let this lower limit be 0.2 V. Also, assume that VDD = S V.
200 /LA
(a) Without allowing any room for output voltage swing,
what is the maximum voltage gain achievable?
(b) If we are required to allow for an output voltage swing of
±O.S V, what dc bias voltage should be established at the drain
FIGURE P4.48 to obtain maximum gain? What gain value is achievable?
What input signal results in a ±O.S-V output swing?
(c) For the situation in (b), find WIL of the transistor to estab­
S E C T I O N 4 . 4 : T H E M O S F E T AS AN A M P L I F I E R
lish a dc drain current of 100 J.LA. For the given process tech-
A N D AS A SWITCH nology, kn = 100 J1AIV .
I 2 /

4 . 4 9 Consider the CS amplifier of Fig. 4.26(a) for the case (d) Find the required value of RD.
VDD S V, RD 24 kO,
= = k� (W/L) = 1 mAIV2, and V, 1 V.=

4 . 5 3 The expression for the incremental voltage gain Av

(a) Find the coordinates of the two end points of the saturation­ given in Eq. (4.41) can be written in as
region segment of the amplifier transfer characteristic, that is,
points A and B on the sketch of Fig. 4.26(c).
(b) If the amplifier is biased to operate with an overdrive
voltage Vav of O.S V, find the coordinates of the bias point QI
on the transfer characteristic. Also, find the value of ID and of where VDS is the bias voltage at the drain (called VaQ in the
the incremental gain Av at the bias point. text). This expression indicates that for given values of VDD
(c) For the situation in (b), and disregarding the distortion and Vav, the gain magnitude can be increased by biasing the
caused by the MOSFET's square-law characteristic, what is transistor at a lower VDS• This, however, reduces the allowable
the largest amplitude of a sine-wave voltage signal that can be output signal swing in the negative direction. Assuming linear
applied at the input while the transistor remains in saturation? operation around the bias point, show that the largest possible
What is the amplitude of the output voltage signal that negative output signal peak Vo that is achievable while the
results? What gain value does the combination of these ampli­ transistor remains saturated is
tudes imply? By what percentage is this gain value different
from the incremental gain value calculated above? Why is
there a difference?
* 4 . 5 0 We wish to investigate the operation of the CS For VDD S V and Vav O.S V, provide a table of values for
= =

amplifier circuit studied in Example 4.8 for various bias con­ Av' -Da , and the corresponding Vi for VDS 1 V, 1 .S V, 2 V,
ditions, that is, for bias at various points along the saturation­
region segment of the transfer characteristic. Prepare a table
and 2.S V. If k�WIL = 1
for which VDS = 1 V.
mAlV2, =

find ID and RD for the design

 PROBLEMS 367

4 . 54 Figure P4.54 shows a CS amplifier in which the load * I) 4 . 5 i' In an electronic instrument using the biasing
resistor RD has been replaced with another NMOS transistor Qz scheme shown in Fig. 4.30(c), a manufacturing error reduces
connected as a two-terminal device. Note that because VDG of Rs to zero. Let VDD = 12 V, RGl = 5.6 MO, and RG2 = 2.2 MO.
Qz is zero, it will be operating in saturation at all times, even What is the value of VG created? If supplier specifications
when VI 0 and iDZ = iDl = O. Note also that the two transistors
= allow k�(WIL) to vary from 220 to 380 J1A1V2 and V, to vary
conduct equal drain currents. Using iDl = iD2, show that for the from 1.3 to 2.4 V, what are the extreme values of ID that may
range of VI over which Ql is operating in saturation, that is, for result? What value of Rs should have been installed to limit
the maximum value of ID to 0.15 rnA? Choose an appropriate
standard 5% resistor value (refer to Appendix G). What extreme
the output voltage will be given by values of current now result?
4 . 5 8 An enhancement NMOS transistor is connected in the
- v (W/L) I _ (W/L) I
va DD - V, + V VI bias circuit of Fig. 4.30(c), with VG = 4 V and Rs = 1 ko. The
- (W/Lh ' (W/Lh transistor has V, = 2 V and k�(WIL) = 2 mAJV2. What bias
where we have assumed V'l = Vt2 = V,, Thus the circuit func­ current results? If a transistor for which k�(WIL) is 50%
tions as a linear amplifier, even for large input signals. For higher is used, what is the resulting percentage increase in ID?
(W/L) l = (50 J1m/0.5 J1m) and (W/Lh = (5 J1m/0.5 4 . S 9 The bias circuit of Fig. 4.30(c) is used in a design with
J1m), find the voltage gain. VG = 5 V and Rs = 1 ill.For an enhancement MOSFET with
VDD k�(WIL) = 2 mAJV2, the source voltage was measured and
found to be 2 V. What must V, be for this device? If a device
for which V, is 0.5 V less is used, what does Vs become? What
bias current results?
0 4 . 6 0 Design the circuit of Fig. 4.30(e) for an enhance­
ment MOSFET having V, = 2 V and k�(W/L) = 2 mAIV2. Let
VDD = Vss = 10 V. Design for a de bias current of 1 rnA and for
the largest possible voltage gain (and thus the largest possible
RD) consistent with allowing a 2-V peak-to-peak voltage swing
at the drain. Assume that the signal voltage on the source ter­
minal of the FET is zero.
0 4 . 6 1 Design the circuit in Fig. P4.61 so that the transistor
operates in saturation with VD biased 1 V from the edge of the
triode region, with ID = 1 rnA and VD = 3 V, for each of the
following two devices (use a lO-J1A current in the voltage
FiGURE P4.54 divider);
(a) [ V,[ = 1 V and k; WIL = 0.5 mAJV2
SECTION 4 . 5 : B IA S I N G I N MOS A M P L I F I E R (b) [ V,[ = 2 V and k; WIL = 1 .25 mAJV2
CI RCU ITS For each case, specify the values ofVG, VD, Vs, Rj, Rz, Rs, and RD'
i) 4 . S S Consider the classical biasing scheme shown in
+ lO V
Fig. 4.30(c), using a 15-V supply. For the MOSFET, V, = 1 .2 V,
A,= 0, k� = 80 f.1AIV2, W = 240 J1m, and L = 6 J1m. Arrange that
the drain current is 2 rnA, with about one-third of the supply
voltage across each of Rs and RD' Use 22 MO for the larger of
RGl and RGz. What are the values of RGb RGz, Rs, and RD that you
have chosen? Specify them to two significant digits. For your
design, how far is the drain voltage from the edge of saturation?
VG o-----<�---I
0 4 . S 6 Using the circuit topology displayed in Fig. 4.30(e),
arrange to bias the NMOS transistor at ID = 2 rnA with VD
midway between cutoff and the beginning of triode operation.
The available supplies are ±15 V. For the NMOS transistor,
V, = 0.8 V, A, = 0, k� = 50 J1A1V2, W 200 J1m, and L = 4 J1m.
=

Use a gate-bias resistor of 1 0 MO. Specify Rs and RD to two

significant digits. FIGURE P4.61
368 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

* * 0 4 . 62 A very useful way to characterize the stability of

the bias current ID is to evaluate the sensitivity of ID relative
to a particular transistor parameter whose variability might be
large. The sensitivity of ID relative to the MOSFET parameter
K = � k' ( W/L) is defined as
ID OID/ID OlD K
S = OK/K - oK ID
_ _

and its value, when multiplied by the variability (or tolerance)

of K, provides the corresponding expected variability of ID•
The purpose of this problem is to investigate the use of
the sensitivity function in the design of the bias circuit of
Fig. 4.30(e).
(a) Show that for constant,
V,

si' = 1/ (1 + 2 ,ji{i;R
FIGURE P4.66
s)
S E C T I O N 4 . 6 : S M A L L - S I G N A l O P.E RA T I O N
(b) For a MOSFET having K = 100 IlA/V2 with a variability AND MODElS
.{;�'

of ±l 0% and 1 V, find the value of Rs that would result

V, =
in ID = 100 f.1A with a variability of ±1 %. Also, find and Vas
*4 . 6 7 This problem investigates the nonlinear distortion intro­
duced by a MOSFET amplifier. Let the signal be a sine wave Vgs
the required value of Vss.
(c) If the available supply = 5 V, find the value of Rs for
Vss
Using the trigonometric identity sin2 e � - � cos2e, show
with amplitude and substitute
Vgs' sin OJt in Eq. (4.57).
Vgs = Vgs

ID = 100 f.1A. Evaluate the sensitivity function, and give the =

expected variability, of ID in this case. that the ratio of the signal at frequency 20J to that
at frequency OJ, expressed as a percentage (known as the
4 . 6 3 For the circuit in Fig. 4.33(a) with I = 1 rnA Ro = 0, second-harmonic distortion) is
RD = 5 ill, and VDD = 10 V, consider the behavior in each of
,

the following two cases. In each case, find the voltages Vs, Second-harmonic distortion = 4! X 100 Vg s
V av
VD, and VDS that result. If in a particular application is 10 mV, find the minimum
Vgs
(a) V, = 1 V and k�WIL 0.5 mA/V2 2
= overdrive voltage at which the transistor should be operated
(b) = 2 V and k� WIL 1.25 mA/V
V, = so that the second-harmonic distortion is kept to less than 1 %.
4 .6 4 In the circuit of Fig. 4.32, letRG= 10 MQ, RD = 10 kQ, 4 . 6 8 Consider an NMOS transistor having k� WIL 2 rnAN • =
2
and VDD = 10 V. For each of the following two transistors, find Let the transistor be biased at 1 V. For operation in
Vav =
the voltages VD and Va. saturation, what dc bias current ID results? If a +0.1-V signal
(a) = 1 V and k�WIL 0.5 mA/V2 2
V,
is superimposed on find the corresponding increment in
Vas'

(b) 2 V and k�WIL 1.25 mA/V

V, =
=
collector current by evaluating the total collector current iD _
=
and subtracting the dc bias current ID. Repeat for a -O.l-V
D 4 . 6 5 Using the feedback bias arrangement shown in signal. Use these results to estimate gm of the FET at this bias
Fig. 4.32 with a 9-V supply and an NMOS point. Compare with the value of gm obtained using Eq. (4.62).
V, = 1 V and k�(WIL) = 0.4 mA/V2, find RDdevice for which
to establish a 4 . 6 9 Consider the FET amplifier of Fig. 4.34 for the case
drain current of 0.2 rnA. If resistor values are limited to those V, = 2 V, k�(WIL) = 1 mA/V2, = 4 V, VDD = 10 V, and
Vas
on the 5% resistor scale (see Appendix G), what value would RD = 3.6 kQ.
you choose? What values of current and VD result?
1)4.66 Figure P4.66 shows a variation of the feedback-bias
(a) Find the dc quantities ID and YD'
circuit of Fig. 4.32. Using a 6�V supply with2 an NMOS transis­ (b) Calculate the value of gm at the bias point.
torfor which = 1.2 V, k�WIL 3.2 mA/V and.li, 0, provide
V, =
(c) Calculate the value of the voltage gain.
(d) If the MOSFET has .Ii, = om y-1 , find ro at the bias point
a design which biases the transistor at ID = 2 rnA with VDS
=

large enough to allow saturation operation for a 2-V negative and calculate the voltage gain.
signal swing at the drain. Use 22 MQ as the largest resistor in * D 4 . " 0 An NMOS amplifier is to be designed to provide a
the feedback-bias network. What values of RD, RGl, and R02 0.50-V peak output signal across a 50-ill load that can be
have you chosen? Specify all resistors to two significant digits. used as a drain resistor. If a gain of at least 5 VIV is needed,
 P RO B LEM S 369

what gm is required? Using a de supply of 3 V, what values of 4 . 1 4 For the NMOS amplifier in Fig. P4.74, replace the
ID and Vov would you choose? What
.
WIL ratio is required if transistor with its T equivalent circuit of Fig. 4.39(d). Derive
2
Pn Cox == 100 pAN ? If V, == 0.8 V, fmd VGs. expressions for the voltage gains V,/ V; and vdl Vi.

*D4.11 In this problem we investigate an optimum design

of the CS amplifier circuit of Fig. 4.34. First, use the voltage
gain expression Av == -gmRD together with Eq. (4.7 1 ) for gm
to show that

A v == _2IDRD == 2(VDD - VD)

Vov Vov
which is the expression we obtained in Section 4.4 (Eq. 4.41).
Next, let the maximum positive input signal be Vi. To keep the Vs
second-harmonic distortion to an acceptable level, we bias
the MOSFET to operate at an overdrive voltage Vov � Vi. Let
Vov == mvi· Now, to maximize the voltage gain I Avl , we
design for the lowest possible VD. Show that the minimum VD
that is consistent with allowing a negative signal voltage swing
at the drain of IAvlv; while maintaining saturation-mode oper­
ation is given by F I G U RE P4.74

o4 . 1 S In the circuit of Fig. P4.75, the NMOS transistor has

I V,I == 0.9 V and VA == 50 V and operates with VD == 2 V. What
is the voltage gain V/Vi? What do VD and the gain become
Now, find Vov, VD, Av, and Vo for the case VDD == 3 V, v; == for I increased to 1 mA?
20 mV, and m == 10. If it is desired to operate this transistor at + VDD
ID 100 pA, find the values of RD and WIL, assuming that for
==

2
this process technology k� 100 pA/V .
==

4 . 1 2 In the table below, for enhancement MOS transistors 1 = 500pA

operating under a variety of conditions, complete as many
entries as possible. Although some data is not available, it is
always possible to calculate gm using one of Eqs. (4.69),
(4.70) or (4.7 1). In the table, current is in rnA, voltage in V, and
2
dimensions in pm. Assume Pn 500 cm2/Vs, f../p == 250 cm /Vs,
==

2
and Cox == 0.4 fF/pm .
Vi
4 . 1 3 An NMOS technology has PnCox 50 pAN and V, ==
==
2
0.7 V. For a transistor with L == 1 pm, find the value of W that
results in gm == 1 mAN at ID == 0.5 rnA. Also, fmd the required VGs. F i G U R E 1=»4.75

Case Type ID IVGsl IVrI Vov W L WIL k'(WIL) 9m

a N 1 3 2
b N 1 0.7 0.5 50
c N 10 2
d N 0.5 0.5
e N 0. 1 10 2
f N 1.8 0.8 40 4
g P 2 25
h P 3 500
P 10 4000 2
j P 10 4
k P 1 30 3
I P 0. 1 5 8
 370 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STORS ( M O S F ETs)

4.76 For a O.S-.um CMOS fabrication process: Vtn = O.S V, Sketch this parabolic curve together with the tangent at a
2
Vtp = -0.9 V, .unCox = 90 .uAN , .upCox = 30 .uAlV , Cox
2 = point whose coordinates are (Vov, ID). The slope of this tan­
2
1.9 fFl.um , ¢f = 0.34 V, Y = 0.5 V l/2 , VA (n-channe1 devices)
= = the vov-axis at Vovl2 and thus that gm = 2ldVov .
gent is gm at this bias point. Show that this tangent intersects
SL (.urn), and I VAI (p-channel devices) l 2L (.urn). Find
the small-signal model parameters (gm, ro, and gmb) for
both an NMOS and a PMOS transistor having WIL 20 .urn! = S E C T I O N 4 . 7 : S I N G L E - S TA G E M O S A M P L I F I E RS
2 .urn and operating at !D 100 .uA with I VsBI = 1 V. Also,
=
4.79 Calculate the overall voltage gain Gv of a common­
find the overdrive voltage at which each device must be
operating.
source amplifier for which gm 2 mAJV, ro 50 kQ, RD
= = =

10 kQ, and RG = 10 MQ. The amplifier is fed from a signal

4.77
sburce with a Thevenin resistance of 0.5 MQ, and the ampli­
Figure P4.77 shows a discrete-circuit CS amplifier
fier output is coupled to a load resistance of 20 ill .
employing the classical biasing scheme studied in Section 4.5.
The input signal Vsig is coupled to the gate through a very 1> 4 . 8 0 This problem investigates a redesign of the common­
large capacitor (shown as infinite). The transistor source is source amplifier of Exercise 4.32 whose bias design was done
connected to ground at signal frequencies via a very large in Exercise 4.30 and shown in Fig. E4.30. Please refer to
capacitor (shown as infinite). The output voltage signal that these two exercises.
develops at the drain is coupled to a load resistance via a very
large capacitor (shown as infinite). (a) The open-circuit voltage gain of the CS amplifier can be

= ==
written as
(a) If the transistor has Vt = 1 V, and k� W/L 2 mAJV2, ver­
ify that the bias circuit establishes VGS 2 V, ID 1 rnA, and
VD +7.5 V. That is, assume these values, and verify that they
=

are consistent with the values of the circuit components and

Verify that this expression yields the results in Exercise 4.32
the device parameters.
(b) Find gm and ro if VA 100 V.
=-
(i.e., Ava 1 5 VN).
(b) Avo can be doubled by reducing Vov by a factor of 2, (i.e.,
=

(c) Draw a complete small-signal equivalent circuit for the

from 1 V to 0.5 V) while VD is kept unchanged. What corre­
amplifier assuming all capacitors behave as short circuits at
sponding values for ID, RD, gm, and ro apply?
signal frequencies.
(c) Find Avo and Rout with rol taken into account.
(d) Find Rin, Vg/ Vsig , vol vgs ' and Vol Vsig .
(d) For the same value of signal-generator resistance Rsig =
4 . '1 8
The fundamental relationship that describes MOSFET 100 kQ, the same value of gate-bias resistance RG = 4.S MQ,
operation is the parabolic relationship between Vov and iD, and the same value of load resistance RL 15 = evaluate the
ill,
new value of overall voltage gain G with ro taken into account.
v

(e) Compare your results to those obtained in Exercises 4.30

and 4.32, and comment.

+15 V

l O Mfl 7.5 kfl

00

Rsig = 100 kfl

1="
00

10 kfl
00

Vsig
3k �' OJ- =

- -
Rin

FIGURE P4.77
 PROBLEMS 371

4 . 8 1 A common-gate amplifier using an n-channel enhance­ coaxial cable. Transistor QI operates as a CS amplifier and Q2
=
ment MOS transistor for which gm 5 mAIV has a 5-ill as a CG amplifier. For proper operation, transistor Q2 is
drain resistance CRD) and a 2-kQ load resistance CRL). The required to present a 50-Q resistance to the cable. This situa­
amplIfier is driven by a voltage source having a 200-Q resis­ tion is known as "proper termination" of the cable and
tance. What is the input resistance of the amplifier? What is ensures that there will be no signal reflection coming back on
the overall voltage gain Gv? If the circuit allows a bias-current the cable. When the cable is properly terminated, its input
increase by a factor of 4 while maintaining linear operation, resistance is 50 Q. What must gm2 be? If QI is biased at the
what do the input resistance and voltage gain become? same point as Qb what is the amplitude of the current pulses
in the drain of QI? What is the amplitude of the voltage
4 . 8 2 A CS amplifier using an NMOS transistor biased in pulses at the drain of QI ? What value of RD is required to pro­
the manner of Fig. 4.43 for which g = 2 mA!V is found to
m
vide I-V pulses at the drain of Q2?
have an overall voltage gain Gv of -16 VN. What value
should a resistance Rs inserted in the source lead have to * D4 . 8 7The MOSFET in the circuit of Fig. P4.87 has VI =
reduce the voltage gain by a factor of 4 ? 1 V, k� WIL = 0.8 mAIV2, and VA = 40 V.
4.83 The overall voltage gain of the amplifier of Fig. 4.44(a) (a) Find the values of Rs, RD, and RG so that lD = 0.1 rnA, the
was measured with a resistance Rs of 1 ill in place and found largest possible value for RD is used while a maximum signal
to be -10 VN. When Rs is shorted, but the circuit operation swing at the drain of ±1 V is possible, and the input resistance
remained linear the gain doubled. What must gm be? What value at the gate is 10 MQ.
Cb) Find the values of g and ro at the bias point.

Y
of Rs is needed to obtain an overall voltage gain of -8 VN? m

(c) If terminal Z is grounded, terminal X is connected to a

4.84 Careful measurements performed on the source fol­ signal source having a resistance of 1 MQ, and terminal is
lower of Fig. 4.46(a) show that the open-circuit voltage gain connected to a load resistance of 40 ill , find the voltage gain
ied, it is found that the gain is halved for RL = 500 Q. If the Y
is 0.98 VN. Also, when RL is connected and its value is var­

Z
from signal source to load.
(d) If terminal is grounded, find the voltage gain from X to
amplifier remained linear throughout this measurement, what

Z
with Z open-circuited. What is the output resistance of the
must the values of gm and ro be? source follower?
4.85 The source follower of Fig. 4.46(a) uses a MOSFET (e) If terminal X is grounded and terminal is connected to a
= =
biased to have g 5 mA!V and ro 20 kQ. Find the open­
m
current source delivering a signal current of 10 I.1A and hav­
ing a resistance of 100 ill, find the voltage signal that can be
circuit voltage gainAvo and the output resistance. What will the
gain become when a I-ill load resistance (RL) is connected? measured at Y. For simplicity, neglect the effect of ro o

4.86 Figure P4.86 shows a scheme for coupling and ampli­ +5 V

fying a high-frequency pulse signal. The circuit utilizes two
MOSFETs whose bias details are not shown and a 50-Q
RD

�Y
00

0------1
00

X 1-----1

�Z
00

Rs

-5 V
V; 0-----1
.t FIGURE P4.87
t
S mV ..-Il...SL
*4 . 8 8 (a) The NMOS transistor in the source-follower cir­
cuit of Fig. P4.88(a) has gm = 5 mAIV and a large roo Find the
FIGURE P4.86 open-circuit voltage gain and the output resistance.
372 C H A PT E R 4 M O S F I ELD- E F F ECT TRA N S I STO R S ( M O S F ETs)

5 kD

Vi o-------J
00

lO kD

F I G U R E P4.88
(a) (b)

(b) The NMOS transistor in the common-gate amplifier of 4 ,92 Starting from the definition of IT for a MOSFET,
Fig. P4.88(b) has gm = 5 mAN and a large roo Find the input
gm
resistance and the voltage gain. -
IT -
(c) If the output of the source follower in (a) is connected to 2n(Cgs + Cgd)
the input of the common-gate amplifier in (b), use the results and making the approximation that Cgs � Cgd and that the over­
of (a) and (b) to obtain the overall voltage gain V/ Vi ' lap component of Cgs is negligibly small, show that
*4,89 In this problem we investigate the large-signal opera­
IT = 1 .5 J.lnlD
tion of the source follower of Fig. 4.46(a). Specifically, con­ nL 2CoxWL
sider the situation when negative input signals are applied.
Let the negative signal voltage at the output be -V. The cur­ Thus note that to obtain a highlT from a given device it must
rent in RL will flow away from ground and will have a value be operated at a high current. Also note that faster operation
of VlRv This current will subtract from the bias current I, is obtained from smaller devices.
resulting in a transistor current of (I - VIRL). One can use this '
4 , 9 3 Starting from the expression for the MOSFET unity­
current value to determine VGS' Now the signal at the transis­ gain frequency,
tor source terminal will be -V, superimposed on the dc volt­
gm
age, which is -VGS (corresponding to a drain current of I). We IT --
can thus find the signal voltage at the gate Vi' For the circuit 2n(Cgs + Cgd)
analyzed in Exercise 4.34, find Vi for Vo = -1 V, -5 V, -6 V, and making the approximation that Cgs � Cgd and that the over­
and -7 V. At each point find the voltage gain Va/Vi and com­ lap component of Cgs is negligibly small, show that for an
pare to the small-signal value found in Exercise 4.34. What is n-channel device
the largest possible negative-output signal?
IT - 3 J.lnVo v
-
4nL2
S ECTION 4.8: T H E MOSFET INTERNAL CAPACITANCES
A N D H I G H - F R E Q U E N CY M O D E L
Observe that for a given device,fT can be increased by operat­
ing the MOSFET at a higher overdrive voltage. Evaluate iT
4 ,9@ Refer to the MOSFET high-frequency model in for devices with L = 1 .0 J.lm operated at overdrive voltages of
Fig. 4.47(a). Evaluate the model parameters for an NMOS 0.25 V and 0.5 V. Use J.ln = 450 cm2Ns.
transistor operating at ID = 100 ,uA, VSB = 1 V, and VDS = 1.5 V.
The MOSFET has W = 20 pm, L = 1 pm, tox = 8 nm, J.ln =
450 cm2Ns, r = 0.5 V I/Z, 2¢/= 0 .65 V, /\'= 0.05 vI , Vo = 0.7 V,
S E C T I O N 4 . 9 : F R E Q U E N CY R E S P O N S E
O F T H E CS AM P L I F I E R
CsbO = CdbO = 15 fF, and Lov = 0.05 J.lm. (Recall that gmb = Xgm'
where X = r/(2 J2¢/ + VSB ) ·) 4,94 In a particular MOSFET amplifier for which the mid­
band voltage gain between gate and drain is -27 VN, the
4,91 Find IT for a MOSFET operating at ID = 100 J.lA and NMOS transistor has Cgs = 0.3 pF and Cgd = 0.1 pF. What
Vov = 0.25 V. The MOSFET has Cgs = 20 fF and Cgd = 5 fF. input capacitance would you expect? For what range of
 PROBLEMS 373

signal-source resistances can you expect the 3-dB frequency value of Ccl must be chosen to place the corresponding
to exceed 10 MHz? Neglect the effect of Re. break frequency at 10 Hz? What value would you choose if
1lll 41 . � 5) In a FET amplifier, such as that in Fig. 4.49(a), the
available capacitors are specified to only one significant
resistance of the source Rsig 100 kQ, amplifier input resis­
==
digit and the break frequency is not to exceed 10 Hz? What
tance (which is due to the biasing network) Rin 100 kQ, Cgs== ==
is the break frequency, fPb obtained with your choice? If a
1 pF, Cgd 0.2 pF, gm 3 mAN, ro 50 ill , RD 8 kQ, and
== == == ==
designer wishes to lower this by raising Re, what is the most
RL 10 ill . Determine the expected 3-dB cutoff frequencyfH
==
that he or she can expect if available resistors are limited to
and the midband gain. In evaluating ways to double iH' a 10 times those now used?
designer considers the alternatives of changing either Rout or
Rin . To raise iH as described, what separate change in each The amplifier in Fig. P4.99 is biased to operate at
il) 41 0 � �

would be required? What midband voltage gain results in each ID 1 rnA and gm == 1 mAN Neglecting rO' find the midband
== .

case? gain. Find the value of Cs that placesiL at 10 Hz.

4. � 6 A discrete MOSFET common-source amplifier has Rin ==

2 MQ, gm 4 mAN, ro 1 00 ill , RD == 10 kQ, Cgs 2 pF,

== == ==

and Cgd 0.5 pF. The amplifier is fed from a voltage source
==

with an internal resistance of 500 ill and is connected to a

lO-kQ load. Find:
RD = 10 kf1
(a) the overall midband gain AM
(b) the upper 3-dB frequency iH
4.�" The analysis of the high-frequency response of the
common-source amplifier, presented in the text, is based on
the assumption that the resistance of the signal source, Rsig,
is large and, thus, that its interaction with the input capaci­
tance Cin produces the "dominant pole" that determines the
upper 3-dB frequency iH. There are situations, however,
when the CS amplifier is fed with a very low Rsig • To inves­ - Vss
tigate the high-frequency response of the amplifier in such
a case, Fig. P4.97 shows the equivalent circuit when the
CS amplifier is fed with an ideal voltage source Vsig having
RSig O. Note that CL denotes the total capacitance at the
==
Consider the amplifier of Fig. 4.49(a). Let RD
4 0 11 (IJ) @ ==

output node. By writing a node equation at the output, show 15 kQ, ro == 1 50 kQ, and RL 10 kQ. Find the value of Ccz,
==

that the transfer function VolVsig is given by specified to one significant digit, to ensure that the associ­
Vo 1_- s (_
C�gd / gm ) ated break frequency is at, or below, 10 Hz. If a higher­
== -gmRL c- �� �����
, __

VS1 g l + s(CL + Cgd)R� power design results in doubling ID, with both RD and ro
reduced by a factor of 2, what does the corner frequency
At frequencies OJ <:S (gmICgd)' the s term in the numerator (due to Cd become? For increasingly higher-power designs,
can be neglected. In such case, what is the upper 3-dB fre­ what is the highest corner frequency that can be associated
quency resulting? Compute the values of AM and iH for the with Ccz.
case: Cgd 0.5 pF, CL 2 pF, gm 4 mAN, and R{ 5 ill .
== == == ==

401 @1 The NMOS transistor in the discrete CS amplifier

Consider the common-source amplifier of Fig. 4.49(a).
[j) 41 . �$ circuit of Fig. P4. 101 is biased to have gm 1 mAN Find
== .

For a situation in which Rsig == 1 MQ and Re 1 MQ, what == AM' iP] , iP2, iP3' andfv

R�

F ! G U RIE 1'4.97
374 CHAPTER 4 MOS F I ELD- E F F ECT TRA N S I STORS ( M OS F ETs)

at least a decade lower. (Hint: In determining the pole due

to Cel> resistance Ro can be neglected.)

S E CT I O N 4 . 1 0 : T H E C M O S D I G I T A L L O G I C
I NV E R T E R

CMOS technology for which k� = 120 .uAIV2, k; = 60 .uN

4 . 1 0 5 For a digital logic inverter fabricated in a 0.8-.um

V2, Vtn = i Vtpl = 0.7 V, VDD 3 V, Ln = Lp 0.8 .urn, Wn

= = =

1 . 2 .um, and Wp = 2.4 .urn, find:

(a) the output resistance for Vo VOL and fur Vo = VOH
=
(b) the maximum current that the inverter can sink or source
while the output remains within 0. 1 V of ground or VDD,
respectively
(c) VIH' VI£> NMH, and NML
4 . 1 0 6 For the technology specified in Problem 4. 105,
investigate how the threshold voltage of the inverter, Vth, var­
FIGURE P4.1 01 ies with the degree of matching of the NMOS and PMOS
devices. Use the formula given in Exercise 4.44, and find Vth
circuit of Fig. P4. 10 1 is biased to have gm = 1 mAIV and To =
4 . 1 0 2 The NMOS transistor in the discrete CS amplifier
=
for the cases (WIL)p (WIL)n, (WIL)p = 2(WIL)n (the matched
=
100 kQ. Find AM. If Cgs = 1 pF and Cgd 0.2 pF, findfH· case), and (WIL)p = 4(WIL)n-

4 . 1 '0 1 For an inverter designed with equal-sized NMOS

amplifier of Fig. 4.49(a). Let Rsig = 0.5 MQ, Ro 2 MQ, gm
0 4 . 1 0 3 Consider the low-frequency response of the CS

= = = = and PMOS transistors and fabricated in the technology speci­

3 mA/V RD 20 ill , and RL 10 ill. Find AM. Also, design
, fied in Problem 4. 105 above, find VIL and VlH and hence the
the coupling and bypass capacitors to locate the three low­ noise margins.
frequency poles at 50 Hz, 10 Hz, and 3 Hz. Use a minimum
total capacitance, with capacitors specified only to a single
4 . 1 0 8 Repeat Exercise 4.41 for VDD = 10 V and 15 V.
significant digit. What value of!L results? 4 . 1 0 9 Repeat Exercise 4.42 for Vt = 0.5 V, 1 .5 V, and'2 V.
4 . 1 0 4 Figure P4. 1 04 shows a MOS amplifier whose bias
4.1 1 0 For a technology in which Vtn = 0.2VDD, show that the
design and midband analysis were performed in Example 4.10.
= low output level does not exceed 0.1 VDD is O.075k�(WIL)n V�D .
maximum current that the CMOS inverter can sink while its

gm = 0.725 mA/V and To = 47 ill. The midband analysis

Specifically, the MOSFET is biased at ID 1 .06 rnA and has

showed that VolV; = -3.3 VN and Rill = 2.33 MQ. Select appro­
= =
For VDD 3 V, k� = 1 2 0 .uAIV2, and Ln 0 . 8 .urn, find the
required transistor width to obtain a current of 1 rnA.
priate values for the two capacitors so that the low-frequency
response is dominated by a pole at 10 Hz with the other pole 4 . 1 1 1 For the inverter specified in Problem 4.105, find the
+ 15 V peak current drawn from the 3-V supply during switching.

4 . 1 1 2 For the inverter specified in Problem 4. 105, find the

value of tPHL when the inverter is loaded with a capacitance C =
0.05 pF. Use both Eq. (4. 156) and the approximate expression
in Eq. (4. 157), and compare the results .

.----lVIoI\r4--I I--_+_--() Va 4 . 1 1 3 Consider an inverter fabricated in the CMOS technol-

ogy specified in Problem 4.105 and having Ln = Lp = 0.8 .um
and (WIL)p = 2(WIL)n- It is required to limit the propagation
delay to 60 ps when the inverter is loaded with 0.05-pF capaci­
tance. Find the required device widths, Wn and Wp-

* 4 . 1 1 4 (a) In the transfer characteristic shown in Fig. 4.56,

the segment BC is vertical because the Early effect is
neglected. Taking the Early effect into account, use small-signal
FIGURE P4.1 04 analysis to show that the slope of the transfer characteristic at
 PROBLEMS 375

VI = Va = VDDI2 is on the bias of Q2 but provides an interesting function. R3 acts

as load resistor in the drain of Q2· Assume that Ql and Q2 are
(V DDI2) - VI fabricated together (as a matched pair, or as part of an IC) and
are identical. For each depletion NMOS, 1DSS = 4 rnA and
where VA is the Early voltage for QN and Qp. Assume QN and I V,I = 2 V. The voltage at the input is some value, say 0 V,
Qp to be matched. that keeps Ql in saturation. What is the value of k�(WIL) for
(b) A CMOS inverter with devices having k�(WIL)n = these transistors?
k '(WIL)p is biased by connecting a resistor RG = 10 Mn
:
Now, design Rl so that 1Dl = 1D2 = 1 mA Make R2 = R1 •
o

b tween input and output. What is the dc voltage at input and Choose R3 so that VE = 6 V. For VA = 0 V, what is the voltage vc?
output? What is the small-signal voltage gain and input Check what the voltage Vc is when VA = ±1 V. Notice the inter­
resistance of the resulting amplifier? Assume the inverter to esting behavior, namely, that node C follows node A. This cir­
have the characteristics specified in Problem 4. 105 with cuit can be called a source follower, but it is a special one, one
I VAI = 50 V. with zero offset! Note also that R2 is not essential, since node B
also follows node A but with a positive offset. In many applica­
S E C T I O N 4 . 1 1 : T H E D E P L E T I O N ·TYPE M O S F E T
tions, R2 is short-circuited. Now, recognize that as the voltage
4 . 1 1 5 A depletion-type n-channel MOSFET with k�W/L =
2 mA/V2 and V, = -3 V has its source and gate grounded. Find
the region of operation and the drain current for VD = 0. 1 V, 1 V,
on A rises, Q2 will eventually enter the triode region. At what
value of VA does this occur? Also, as VA lowers, Ql will enter its
triode region. At what value of VA? (Note that between these
3 V, and 5 V. Neglect the channel-length-modulation effect. two values of VA is the linear signal range of both VA and vc.)
4.1 1 6 For a particular depletion-mode NMOS device, V, =
-2 V, k�WIL = 200 f1AIV2, I
and A = 0.02 V- . When operated + lO V
at VGS = 0, what is the drain current that flows for VDS = 1 V, 2 V,
3 V, and 10 V? What does each of these currents become if the
device width is doubled with L the same? With L also doubled?
R3
* 4 . 1 1 7 Neglecting the channel-length-modulation effect
show that for the depletion-type NMOS transistor of Fig. P4. l l7
VE
the i-v relationship is given by

i = �k� ( W/L) ( v2 _ 2 V,v) , for V ;::: V, VA 0--1 Q2

VB
i = -�k� ( W/L) V;, for V S V,

2
(Recall that V, is negative.) Sketch the i-v relationship for the
case: V, = -2 V and k�(WIL) = 2 mA/V .
R2

+
Vc
Ql
VD
V
Rj

FIGURE P4. 1 1 7 - lO V
4 . 1 1 8 For the circuit analyzed in Exercise 4.5 1 (refer to
Fig. E4.5 l ), what does the voltage at the source become when
FIGURE P4. 1 20
the drain voltage is lowered to + 1 V?
G E N E RA L P R O B L E M S :
4 . 1 1 9 A depletion-type NMOS transistor operating in the
* * 4 . 1 2 1 The circuits shown in Fig. P4. 1 2 1 employ negative
saturation region with VDS = 5 V conducts a drain current of
1 mA at VGS = -1 V, and 9 rnA at VGS = +1 V. Find 1Dss and V,. feedback, a subject we shall study in detail in Chapter 8.
Assume A = o. Assume that each transistor is sized and biased so that gm =
1 mA/V and ro = 100 ill . Otherwise, ignore all dc biasing
0 4 . 1 2 0 Consider the circuit shown in Fig. P4. 120 in which detail and concentrate on small-signal operation resulting in
Q 1 with Rj establishes the bias current for Q2. R2 has no effect response to the input signal Vsig. For RL = 10 kn, Rl = 500 kn,
376 C H A P T E R 4 M O S F I ELD- E F F ECT TRA N S I STO RS ( M O S F ETs)

and R2 1 MQ, find the overall voltage gain VofVsig and the
= For NMOS transistors with V, = 0.6 V, find Vov, k�( WIL),
input resistance Rin for each circuit. Neglect the body effect. and VA to bias each device at ID = 0. 1 and to obtain the
rnA
Do these circuits remind you of op-arnp circuits? Comment. values of gm and ro specified in Problem 4.121 ; namely, gm ==

VDD 1 mAN and ro = 1 00 kQ. For R! 0.5 MQ, R2 = 1 MQ, and

=

RL = 10 kQ, find the required value of VDD.

* *4 . 1 2 3 In the amplifier shown in Fig. P4. 123, transistors
having V, = 0.6 V and VA = 20 V are operated at VGS 0.8 V=

using the appropriate choice of WIL ratio. In a particular

application, Q! is to be sized to operate at 10 !lA, while Q2 is
intended to operate at 1 rnA For RL = 2 kQ, the (R!, R2) net­
.

work sized to consume only 1 % of the current in Rv Vsig' having

zero dc component, and I! = 10 JiA, find the values of R! and
R2 that satisfy all the requirements. (Hint: Vo must be +2 V.)
What is the voltage gain vofv;? Using a result from a theorem
known as Miller's theorem (Chapter 6), find the input resis­
tance Rin as R21 ( 1 Vo I v;) . Now, calculate the value of the
-

overall voltage gain VofVsig. Does this result remind you of the
inverting configuration of the op amp? Comment. How would
you modify the circuit at the input using an additional resistor
and a very large capacitor to raise the gain VofVsig to -5 VN?
(a) Neglect the body effect.

Vi

(b)
r
FIGURE P4.1 23
FIGURE P4.1 2 1
4 . 1 2 4 Consider the bias design of the circuit of Problem 4.123
4 . 1 2 2 For the two circuits i n Problem 4 . 1 2 1 (shown in (shown in Fig. P4. 123). For k� = 200 JiNV2 and VDD = 3.3 V,
Fig. P4. 1 2 1), we wish to consider their dc bias design. Since find ( WIL) ! and ( WIL)2 to obtain the operating conditions
Vsig has a zero dc component, we short circuit its generator. specified in Problem 4. 1 23 .