Confidential

Security C

TSMC N65 PDK usage guide:

An introduction on the usage of TSMC
process design kits (PDK)
PDK Version: v1.5a Nov. 03

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z Introduction: Security C

„ This document describes the TSMC process design kits (PDK) parameterized cell (Pcell)
software, which provides a graphical user interface that lets user create parameterized cells for
placement in design layout.
„ It is assumed that the user is familiar with the development and design of integrated circuits and
with the cadence Virtuoso Layout Editor.
„ All the information and data contained hereunder constitute TSMC's proprietary and confidential
information. Unless TSMC agrees otherwise in writing, you can only use the information
contained herein for evaluation purpose. Further, you should treat the information as
confidential information and exercise due care to prevent its disclosure to any persons, provided
you may disclose it to your employees on a need to know basis in case they agree to similar
duty of confidentiality to protect the information herein. You cannot disclose such information to
any third party unless TSMC agrees in advance by writing. However, requirements hereunder
shall not serve to supersede or change any existing contracts regulating similar issues between
you and TSMC.

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z Overview: Security C

„ The Symbol Display Information.

This section describes the symbol display information include six terminal RF_NMOS symble, five
terminal RF_PMOS symbol, four terminal RF_NMOS symble, three terminal RF_PMOS symbol, four
terminal NMOS symble, four terminal PMOS symbol, three terminal NMOS symbol, three terminal PMOS
symbol, three terminal npn BJT symbol, three terminal pnp BJT symbol, two terminal diode symbol, two
terminal esd_diode symbol, three terminal esd_diode symbol, two terminal resister symbol, three terminal
resister symbol, three terminal varactor symbol and two terminal varactor symbol.
„ Device Table
This section show the total device in this PDK. The user can check the page number in the device table
to find out the CDF parameter and Pcell function.
„ MOS Parameterized Cell Function Introduction
„ BJT Parameterized Cell Function Introduction
„ Diode Parameterized Cell Function Introduction
„ Resistance Parameterized Cell Function Introduction
„ Inductor Parameterized Cell Function Introduction
„ Varactor Parameterized Cell Function Introduction
„ Capacitor Parameterized Cell Function Introduction
„ CDF Parameter Description

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z Appendix: Security C

„ Appendix A – Abutment Fast link

„ Appendix B – Stretch Handles Fast link

„ Appendix C – The three terminal MOS substrate pin Fast link

„ Appendix D – TSMC Utility Fast link
„ Appendix E – AS AD PS PD NRS NRD methodology Fast link
„ Appendix F – SA SB methodology Fast link
„ Appendix G – Multiple devices Abutment methodology Fast link
„ Appendix H – MOS pcell usage GA_CO_SP_INC Fast link
„ Appendix I – Sdshrink and Poly Gate position Fast link
„ Appendix J – SCA SCB SCC for Well Proximity Effect/WPE Fast link

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a six terminal RF_NMOS:

Device instance name

Model name
Device name
Finger number × width

Device width
Drain terminal
NW guard ring terminal

Gate terminal Bulk terminal

PW guard ring terminal

Device length
Source terminal
Finger number

Multiplier number

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a five terminal RF_PMOS:

Device instance name

Device name Model name

Finger number × width

Drain terminal Device width

Bulk terminal
Gate terminal
PW guard ring terminal

Device length
Source terminal
Finger number

Multiplier number

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a four terminal RF_NMOS:

Device instance name

Model name
Device name
Finger number × width

Device width
Drain terminal
Bulk terminal

Gate terminal Device length

Finger number
Source terminal Multiplier number
NW guard ring terminal
tie to VDD!

PW guard ring terminal

tie to VSS!

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a four terminal RF_PMOS:

Device instance name

Model name

Device name Finger number × width

Device width
Drain terminal
Bulk terminal

Gate terminal Device length

Finger number
Source terminal Multiplier number

PW guard ring terminal

tie to VSS!

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a four terminal NMOS:

Device name Device instance name

Model name

Drain terminal Channel width

Gate terminal Bulk terminal

Channel length

Numbers of poly fingers

Source terminal
Multiplier for simulation

Finger number × multiplier

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a four terminal PMOS:

Device name Device instance name

Model name

Drain terminal Channel width

Gate terminal Bulk terminal

Channel length

Numbers of poly fingers

Source terminal
Multiplier for simulation

Finger number × multiplier

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal NMOS :

Device name Device instance name

Model name

Drain terminal Channel width

Gate terminal

Channel length
Numbers of poly fingers

Multiplier for simulation

Source terminal
Finger number × multiplier

Bulk terminal

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal PMOS :

Device name Device instance name

Model name

Drain terminal Channel width

Gate terminal

Channel length
Numbers of poly fingers

Multiplier for simulation

Source terminal
Finger number × multiplier

Bulk terminal

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal npn BJT:

Device instance name

Device name

Model name

Emitter area
The net name that
connect to C terminal

The net name that

connect to B terminal Emitter length

Emitter width

Numbers of parallel
The net name that devices
connect to E terminal

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal pnp BJT:

Device instance name

Device name
Model name

Emitter area
The net name that
connect to E terminal

Emitter length
The net name that
connect to B terminal Emitter width

Numbers of parallel
devices
The net name that
connect to C terminal

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a two terminal esd_diode:

Device instance name

Model name
Device name
Diode area

PLUS terminal Diode periphery

Numbers of parallel
devices

Device width
MINUS terminal
Device length

Finger number

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal esd_diode:

Device instance name

Model name
Device name
Diode area

PLUS terminal Diode periphery

Numbers of parallel
BULK terminal devices

Device width
MINUS terminal
Device length

Finger number

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a two terminal diode:

Device name Device instance name

Model name

The net name that

connect to PLUS terminal Diode area

Diode periphery

Numbers of parallel
devices
The net name that
connect to MINUS terminal

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a two terminal resister:

Device instance name

Device name

Model name

Resister width
PLUS terminal

Resister length

Numbers of parallel
devices

MINUS terminal
Total resistance

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal resister:

Device name Device instance name

Model name

PLUS terminal BULK terminal

Resister width

Resister length

Numbers of parallel
MINUS terminal devices

Total resistance

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a two terminal varactor:

Device instance name

Device name

Model name

The net name that Varactor width

connect to PLUS terminal
Varactor length

Total capacitance

The net name that

connect to MINUS terminal

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a three terminal varactor:

Device instance name

Device name Model name

PLUS terminal Total capacitance

Varactor length
BULK terminal
Varactor width

MINUS terminal Finger number

Numbers of parallel
devices

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a Inverter gate :

P: P pin Pb: Pb pin PMOS length

inv PMOS width

PMOS fingers
IN: Input terminal

OUT: Output terminal

NMOS length

NMOS width

NMOS fingers

Numbers of parallel
devices G: G pin Gb: Gb pin

P. 22 inv_18 inv_25 inv_hvt inv_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a nand-2T gate :

P: P pin Pb: Pb pin PMOS length

nand2 PMOS width

PMOS fingers

A: First input terminal Y: Output terminal

B: Second input terminal
NMOS length

NMOS width

NMOS fingers

Numbers of parallel
devices G: G pin Gb: Gb pin

P. 23 nand_18 nand_25 nand_hvt nand_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a nand-3T gate :

P: P pin Pb: Pb pin PMOS length

nand3 PMOS width

PMOS fingers

A: First input terminal Y: Output terminal

B: Second input terminal
NMOS length
C: Third input terminal
NMOS width

NMOS fingers

Numbers of parallel
devices G: G pin Gb: Gb pin

P. 24 nand3_18 nand3_25 nand3_hvt nand3_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a nand-4T gate :

P: P pin Pb: Pb pin PMOS length

nand4
PMOS width

PMOS fingers

A: First input terminal Y: Output terminal

B: Second input terminal
NMOS length
C: Third input terminal
D: Fourth input terminal NMOS width

NMOS fingers

G: G pin Gb: Gb pin

P. 25 nand4_18 nand4_25 nand4_hvt nand4_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a nor-2T gate :

P: P pin Pb: Pb pin PMOS length

nor2 PMOS width

PMOS fingers

Y: Output terminal
A: First input terminal NMOS length
B: Second input terminal
NMOS width
G NMOS fingers

G: G pin Gb: Gb pin

P. 26 nor2_18 nor2_25 nor2_hvt nor2_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a nor-3T gate :

P: P pin Pb: Pb pin PMOS length

nor3 PMOS width

PMOS fingers

Y: Output terminal
A: First input terminal
B: Second input terminal NMOS length
C: Third input terminal NMOS width

NMOS fingers

G: G pin Gb: Gb pin

P. 27 nor3_18 nor3_25 nor3_hvt nor3_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a nor-4T gate :

P: P pin Pb: Pb pin PMOS length

nor4 PMOS width

PMOS fingers
A: First input terminal
B: Second input terminal Y: Output terminal
C: Third input terminal NMOS length
D: Fourth input terminal
NMOS width

NMOS fingers

G: G pin Gb: Gb pin

P. 28 nor4_18 nor4_25 nor4_hvt nor4_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a pass gate :

P: P pin Cb: Cb pin PMOS length

pass
PMOS width

PMOS fingers

Y: Output terminal

A: First input terminal

NMOS length

NMOS width

NMOS fingers

G: G pin C: C pin

P. 29 pass_18 pass_25 pass_hvt pass_lvt SM

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z The Symbol Display Information: Security C

„ The following figure shows the symbol for a Tri state inverter gate :

P: P pin Cb: Cb pin PMOS length

tir
PMOS width

PMOS fingers

Y: Output terminal

A: First input terminal NMOS length

NMOS width

NMOS fingers

G: G pin C: C pin

P. 30 tir_18 tir_25 tir_hvt tir_lvt SM

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z Device Table: Security C

„ The devices in this PDK are list as below table:

Categaries Device
nch, nch_dnw, nch_25ud18, nch_25_dnwud18, nch_25, nch_25_dnw, nch_25od33, nch_na25od33, nch_na25od33x,
nch_25_dnwod33, nch_hvt, nch_hvt_dnw, nch_lvt, nch_lvt_dnw, nch_mlvt, nch_mlvt_dnw, nch_na, nch_na25, pch,
pch_25ud18, pch_25, pch_25od33, pch_hvt, pch_lvt, pch_mlvt, nch_25ud18x, nch_25x, nch_25od33x, nch_hvtx,
MOS
nch_lvtx, nch_mlvtx, nchx, nch_25_dnwud18x, nch_25_dnwx, nch_25_dnwod33x, nch_hvt_dnwx, nch_lvt_dnwx,
nch_mlvt_dnwx, nch_dnwx, nch_nax, nch_na25x, pch_25ud18x, pch_25x, pch_25od33x, pch_hvtx, pch_lvtx, pch_mlvtx,
pchx, pch_hv25, nch_hv25
pch_25ud18_mac, pch_25ud18_macx, pch_25_mac, pch_25_macx, pch_25od33_mac, pch_25od33_macx, pch_hvt_mac,
:,pch_hvt_macx, pch_lvt_mac, pch_lvt_macx, pch_mac, pch_macx, pch_mlvt_mac, pch_mlvt_macx, nch_25ud18_mac,
nch_25ud18_macx, nch_25_mac, nch_25_macx, nch_25od33_mac, nch_25od33_macx, nch_hvt_mac, nch_hvt_macx,
MOS_MAC nch_lvt_mac, nch_lvt_macx, nch_mac, nch_macx, nch_mlvt_mac, nch_mlvt_macx, nch_25_dnwud18_mac,
nch_25_dnwud18_macx, nch_25_dnw_mac, nch_25_dnw_macx, nch_25_dnwod33_mac, nch_25_dnwod33_macx, nch_dnw_mac,
nch_dnw_macx, nch_hvt_dnw_mac, nch_hvt_dnw_macx, nch_lvt_dnw_mac, nch_lvt_dnw_macx, nch_mlvt_dnw_mac,
nch_mlvt_dnw_macx, nch_na_mac, nch_na25_mac, nch_na_macx, nch_na25_macx, nch_hv25_mac, pch_hv25_mac
nmos_rf, nmos_rf_25ud18, nmos_rf_25, nmos_rf_25od33, nmos_rf_hvt, nmos_rf_lvt, nmos_rf_mlvt, nmos_rf_nodnw,
nmos_rf_25_nodnwud18, nmos_rf_25_nodnw, nmos_rf_25_nodnwod33, nmos_rf_hvt_nodnw, nmos_rf_lvt_nodnw,
nmos_rf_mlvt_nodnw, pmos_rf, pmos_rf_25ud18, pmos_rf_25, pmos_rf_25od33, pmos_rf_hvt, pmos_rf_lvt, pmos_rf_mlvt,
pmos_rf_nw, pmos_rf_25_nwud18, pmos_rf_25_nw, pmos_rf_25_nwod33, pmos_rf_hvt_nw, pmos_rf_lvt_nw,
MOS_RF
pmos_rf_mlvt_nw, nmos_rf_25ud18_6t, nmos_rf_mlvt_6t, nmos_rf_6t, nmos_rf_hvt_6t, pmos_rf_25_5t, pmos_rf_25ud18_5t,
pmos_rf_25ud18_nw_5t, pmos_rf_lvt_5t, nmos_rf_25od33_6t, pmos_rf_mlvt_nw_5t, pmos_rf_25od33_5t, pmos_rf_nw_5t,
pmos_rf_hvt_5t, pmos_rf_mlvt_5t, nmos_rf_25_6t, pmos_rf_5t, pmos_rf_hvt_nw_5t, pmos_rf_25_nw_5t,
pmos_rf_25od33_nw_5t, nmos_rf_lvt_6t, pmos_rf_lvt_nw_5t, nmos_rf_33_6t, pmos_rf_33_5t, pmos_rf_33_nw_5t
BJT pnp, pnp_mis, npn, npn_mis, pnp_s, pnp_s_mis, npn_s, npn_s_mis

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z Device Table: Security C

ndio, ndio_18, ndio_25, ndio_33, ndio_hvt, ndio_lvt, ndio_mlvt, ndio_na, ndio_na25, nwdio, pwdnw, dnwpsub, dnwpsub,
Diode
ndio_esd, pdio, pdio_18, pdio_25, pdio_33, pdio_hvt, pdio_lvt, pdio_mlvt, ndio_hia_rf, pdio_hia_rf, sbd_rf, sbd_rf_nw
Resistor(1) rm1, rm2, rm3, rm4, rm5, rm6, rm7, rm8, rm9
rnod, rnod_m, rnodwo, rnodwo_m, rnpoly, rnpoly_m, rnpolywo, rnpolywo_m, rnwod, rnwod_m, rnwsti, rnwsti_m, rpod,
Resistor(2) rpod_m, rpodwo, rpodwo_m, rppoly, rppoly_m, rppoly_rf, rppolywo, rppolywo_m, rppolywo_rf, rnod_mx, rnodwo_mx,
rnpoly_mx, rnpolywo_mx, rnwod_mx, rnwsti_mx, rpod_mx, rpodwo_mx, rppoly_mx, rppolywo_mx
crtmom, crtmom_mx, crtmom_rf, mimcap, mimcap_3t, mimcap_um_rf, mimcap_woum_rf, mimcap_udc,
Capacitors
mimcap_udc_3t, mimcap_um_udc_rf, mimcap_woum_udc_rf
nmoscap, nmoscap_25, moscap_rf, moscap_rf_hvt, moscap_rf25, moscap_rf_nw, moscap_rf_hvt_nw, moscap_rf25_nw,
Varactors
xjvar, xjvar_nw, pmoscap_rf, pmoscap_rf25
spiral_std_MU_Z, spiral_sym_MU_Z, spiral_sym_ct_MU_Z, spiral_std_MZA_A, spiral_sym_MZA_A,
Inductors
spiral_sym_ct_MZA_A,
inv, inv_mac, inv_lvt, inv_lvt_mac, inv_hvt, inv_hvt_mac, inv_18, inv_18_mac, inv_25, inv_25_mac, inv_33, inv_33_mac, nand2,
nand2_mac, nand2_lvt, nand2_lvt_mac, nand2_hvt, nand2_hvt_mac, nand2_18, nand2_18_mac, nand2_25, nand2_25_mac,
nand2_33, nand2_33_mac, nand3, nand3_mac, nand3_lvt, nand3_lvt_mac,nand3_hvt, nand3_hvt_mac, nand3_18,
nand3_18_mac, nand3_25, nand3_25_mac, nand3_33, nand3_33_mac, nand4,nand4_mac, nand4_lvt, nand4_lvt_mac,
nand4_hvt, nand4_hvt_mac, nand4_18, nand4_18_mac, nand4_25, nand4_25_mac, nand4_33, nand4_33_mac, nor2,
Logic Gates nor2_mac, nor3, nor3_mac, nor3_lvt, nor3_lvt_mac, nor3_hvt, nor3_hvt_mac, nor3_18, nor3_18_mac, nor3_25,
nor3_25_mac, nar3_33, nar3_33_mac, nor4, nor4_mac, nor4_lvt, nor4_lvt_mac, nor2_lvt, nor2_lvt_mac, nor2_hvt,
nor2_hvt_mac, nor2_18, nor2_18_mac, nor2_25, nor2_25_mac, nar2_33, nar2_33_mac, nor4_hvt, nor4_hvt_mac, nor4_18,
nor4_18_mac, nor4_25, nor4_25_mac, nar4_33, nar4_33_mac, tri, tri_mac, tri_lvt, tri_lvt_mac, tri_hvt, tri_hvt_mac, tri_18,
tri_18_mac, tri_25, tri_25_mac, tri_33, tri_33_mac, pass, pass_mac, pass_lvt, pass_lvt_mac, pass_hvt, pass_hvt_mac,
pass_18, pass_18_mac, pass_25, pass_25_mac, pass_33, pass_33_mac

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z MOS Parameterized Cell Function Introduction: Security C

„ The schematic component description format (CDF) parameter in MOS are list as below:

‹Model name: Display Model name information.

‹Description: Display device description.
(These parameters can’t be modify in CDF form)

‹L (M): Channel length of the device.

‹W (M): Channel width of the device.

‹Total_width(M): Total channel width of this device, equal

to width x fingers.

‹Number of Fingers_(N): Numbers of poly fingers.

Check here for more information

‹Multiplier: Numbers of parallel MOS device.

Check here for more information

‹Total_m: Display numbers of parallel MOS device.

(This parameter can’t be modify in CDF form)

‹Well Proximity Effect Cal. Method: three entry methods

for WPE parameters:
model => use model default values.
auto => auto calculate WPE parameters.
custom => user input desire value by self.
‹SCA (M): WPE SCA parameter. - for simulate use
‹SCB (M): WPE SCB parameter. - for simulate use
‹SCC (M): WPE SCC parameter. - for simulate use
‹Hard_constrain: This function provides an option to constrain
Next page the value for each parameter in this device.
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z MOS Parameterized Cell Function Introduction: Security C

„ The schematic component description format (CDF) parameter in MOS are list as below:

‹S D swap: Enable this function to swap source and drain terminal.

Front page
‹ShareLeftShape: (normal, same, sameExt, small, smallExt,
large, largeExt, diff, diffExt) Preview the
left-shape abutment information.
‹ShareRightShape: (normal, same, sameExt, small, smallExt,
large, largeExt, diff, diffExt) Preview the
right-shape abutment information.
Check here for more information

‹Calc Diff Params: The switch provide to modify simulation

parameters.

‹Calc SA SB SD: The switch provide to modify simulation

SA, SB and SB.
‹Source_area: Source area (AS) - for simulate use.
‹Drain_area: Drain area (AD) - for simulate use.
‹Source_periphery: Source periphery (PS) - for simulate use.
‹Drain_periphery: Drain periphery (PD) - for simulate use.
‹NRS: Number of squares source resistance – for simulate use.
‹NRD: Number of squares drain resistance – for simulate use.
‹SA(LOD_effect)_(M): LOD effect parameter – for simulate use.
‹SA(LOD_effect)_(M): LOD effect parameter – for simulate use.
Check here for more information

Next page
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z MOS Parameterized Cell Function Introduction: Security C

„ The schematic component description format (CDF) parameter in MOS are list as below:

Front page ‹DFM_options: (minRule, DFM, DFM+DRMV11, custom) This

option provide user to select design rule in the layout is follow
minimum rule or DFM rule or custom self define.
Check here for more information

‹SD(Fingers_spacing)_(M): MOS finger spacing

- for simulate use.

‹Ldiff_ext: Increment of left side diffusion.

‹Rdiff_ext: Increment of right side diffusion.

‹LGA_CO_SP_INC(M): Increment of left side Gate to contact

spacing.

‹RGA_CO_SP_INC(M): Increment of Right side Gate to contact

spacing.
Check here for more information

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z MOS Parameterized Cell Function Introduction: Confidential
Security C

„ The layout component description format (CDF) parameter in MOS are list as below:
‹Model name: Display Model name information.

‹SCA (M): WPE SCA parameter. - for simulate use

‹SCB (M): WPE SCB parameter. - for simulate use

‹SCC (M): WPE SCC parameter. - for simulate use

‹Well_Proximity_Effect (M): Option for WEP - for simulate use

(These are the same parameter that in schematic CDF form)

‹Description: Display device description.

‹L (M): Channel length of the device.
‹W (M): Channel width of the device.
‹Total_width(M): Total channel width of this device, equal
to width x fingers.
‹Number of Fingers_(N): Numbers of poly fingers.

‹Total_m: Display numbers of parallel MOS device.

‹Hard_constrain: This function provides an option to constrain

the value for each parameter in this device.

‹S D swap: Enable this function to swap source and drain terminal.
‹ShareLeftShape: Display the left-shape abutment information.
‹ShareRightShape:Display the right-shape abutment information.
(These are the same parameter that in schematic CDF form)
‹Calc Diff Params: The switch provide to modify simulation
parameters.

‹Calc SA SB SD: The switch provide to modify simulation

SA, SB and SB.
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(These are the same parameter that in schematic CDF form) SM

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z MOS Parameterized Cell Function Introduction: Security C

„ The layout component description format (CDF) parameter in MOS are list as below:
‹Source_area: Source area (AS) - for simulate use.
‹Drain_area: Drain area (AD) - for simulate use.

Front page ‹Source_periphery: Source periphery (PS) - for simulate use.

‹Drain_periphery: Drain periphery (PD) - for simulate use.
‹NRS: Number of squares source resistance – for simulate use.
‹NRD: Number of squares drain resistance – for simulate use.

‹leftCnt: A option for drawing poly-left diffusion area metal1

connection.
‹RigthCnt: A option for drawing poly-right diffusion area metal1
connection. Check here for more information
‹RigthCnt: A option for drawing inter-poly diffusion metal1
connection.
The function only appears when Number of fingers_(N) > 1

‹routePolydir:(None, Top, Bottom, Both) A option for drawing

poly gate connection.
The function only appears when Number of fingers_(N) > 1
Check here for more information

‹route_Source_Drain:(Source, Drain, Both) A option for

drawing source and drain connection.
The function only appears when Number of fingers_(N) > 1
Check here for more information
‹bodytie_typeL: (None, Integred, Detached) A option for
drawing body connection.
‹bodytie_typeR: (None, Integred, Detached) A option for
drawing body connection.
Next page Check here for more information
P. 37
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 TSMCN65 PDK Usage Guide Confidential

z MOS Parameterized Cell function Introduction: Security C

„ The layout component description format (CDF) parameter in MOS are list as below:

‹DFM_options: (minRule, DFM, DFM+DRMV11, custom)

Front page
This option provide user to select design rule in the layout is follow
minimum rule or DFM rule or custom self define.
(This is the same parameter that in schematic CDF form)
‹fingers_SP_INC(M): The function is provided to modify poly
gate space.
The function only appears when Number of fingers_(N) > 1
Check here for more information

‹Ldiff_ext: Increment of left side diffusion.

‹Rdiff_ext: Increment of right side diffusion.
‹LGA_CO_SP_INC(M): Increment of left side Gate to contact
spacing.
‹RGA_CO_SP_INC(M): Increment of Right side Gate to contact
spacing.
(These are the same parameter that in schematic CDF form)
‹SDshrink: The function is provided to modify the metal
dimension on source or drain area.
Check here for more information

‹POshrink: The function provide a option for well implant.

Check here for more information

‹Text size: The function can modify the font value in layout view.
‹Imp layer: The function provide a option for well implant.

P. 38
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 TSMCN65 PDK Usage Guide Confidential

z RF_MOS(6t.5t) Parameterized Cell Function Introduction: Security C

„ The schematic component description format (CDF) parameter in MOS are list as below:

‹Model name: Display Model name information.

‹Total_width(M):Total channel width of this device, equal

to width x fingers.
(These parameters can’t be modify in CDF form)

‹Width_per_Finger (M): Channel length of the device.

‹Length_per_Finger (M): Channel width of the device.

‹Number of Fingers: Numbers of poly fingers.

Check here for more information

‹Well Proximity Effect Cal. Method:

three entry methods for WPE parameters:
off => use model default values.
auto => auto calculate WPE parameters.
custom => user input desire value by self.
‹SCA (M): WPE SCA parameter. - for simulate use
‹SCB (M): WPE SCB parameter. - for simulate use
‹SCC (M): WPE SCC parameter. - for simulate use

Next page
P. 39
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 TSMCN65 PDK Usage Guide Confidential

z RF_MOS(6t.5t) Parameterized Cell Function Introduction: Security C

„ The schematic component description format (CDF) parameter in MOS are list as below:

Front page

‹Create_Dummy_Poly: Display Model name information.

‹Multiplier: Numbers of parallel MOS device.

Check here for more information

‹Adding_DMEXCL_Layer:This function provides an option to

add dummy layer.
‹Hard_constrain: This function provides an option to constrain
the value for each parameter in this device.
‹With Mismatch Effect:This function provides an option for
mismatch effect..
‹Mismatch_Sigma: Mismatch factor in GUASS distribution.

P. 40
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 TSMCN65 PDK Usage Guide Confidential

z BJT Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in BJT are list as below:

‹Model name: Display model name information.

‹Description: Display device description.
(These parameter can’t be modify in CDF form)

‹EmitterSize: (2X2, 5X5, 10X10) Select the bjt dimension

in design layout.
Check here for more information

‹EmitterArea: Display the bjt emitter area.

(This parameter can’t be modify in CDF form)

‹Multiplier: Numbers of parallel MOS device.

Check here for more information

‹Hard_constrain: This function provides an option to constrain

the value for each parameter in this device.

‹lxUseCell: Display the layout cell name.

(This parameter can’t be modify in CDF form)

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 TSMCN65 PDK Usage Guide Confidential

z Diode Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in Diode are list as below:
‹Model name: Display model name information.
‹Description: Display device description.
‹Diode_area: Display the diode area.
‹Diode peri: Display the diode periphery.
(These parameter can’t be modify in CDF form)

‹Length_(M): Junction length of the device.

‹Width_(M): Junction Width of the device.

‹Multiplier: Numbers of parallel Diode device.

Check here for more information

‹Hard_constrain: This function provides an option to constrain

the value for each parameter in this device.

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 TSMCN65 PDK Usage Guide Confidential

z ESD_Diode Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in Diode are list as below:
‹Model name: Display model name information.
‹Description: Display device description.
‹Diode_area: Display the diode area.
‹Diode peri: Display the diode periphery.
(These parameter can’t be modify in CDF form)
‹Length_(M): Junction length of the device
(only support 0.6u/0.8u/1.6u three type )

‹Width_(M): Junction Width of the device.

(step size of width is 1u)

‹Multiplier: Numbers of parallel Diode device

‹Number of Fingers(N): Numbers of poly fingers..

‹Hard_constrain: This function provides an option to constrain

the value for each parameter in this device.
‹Esd_dioType: Display diode type.
‹Cap@0V(F): Device capacitance information.
‹Cap@ReverseVol(F): Device capacitance information.
(These parameter can’t be modify in CDF form)
‹ReverseVol_(V): Reverse voltage
‹Estimate_HBM: Human Body Mode Value for esd
‹Hiaflag: hiaflag=Model for model card default value;
hiaflag=0 for reverse RF simulation;
P. 43 hiaflag=1 for forward ESD high-current simulation. SM

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 TSMCN65 PDK Usage Guide Confidential

z Resistance (1) Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in resistance are list as below:
‹Model name: Display model name information.
‹Description: Display device description.
(These parameter can’t be modify in CDF form)

‹Total resistance(ohms): Device resistance value.

‹Segment width(M): Device segment width.

‹Segment length(M): Device segment length.

Check here for more information

‹Multiplier: Numbers of parallel Diode device.

Check here for more information

‹Rs(ohms/square): Display the device Rs value.

(This parameter can’t be modify in CDF form)

‹Hard_constrain: This function provides an option to constrain

the value for each parameter in this device.

‹Res_update_method: (l_&_W, Res_&_W) Res update

method, please review segment width
and segment length function.

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z Resistance(2) Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in resistance are list as below:
‹Model name: Display model name information.
‹Description: Display device description.
‹With Mismatch Effect: Option for run mismatch effect

‹Total resistance(ohms): Device resistance value.

‹Segment width(M): Device segment width.
‹Segment length(M): Device segment length.
Check here for more information

‹Total width(M): Display the device segment width.

‹Total length(M): Display the device segment length.
‹(These parameter can’t be modify in CDF form)

‹Multiplier: Numbers of parallel Diode device.

Check here for more information

‹Rs(ohms/square): Display the device Rs value.

(This parameter can’t be modify in CDF form)
‹Resistor connection: Device resistance value.
‹Number of segment: Device segment width.
‹Segment spacing(M): Device segment length.
Check here for more information

‹Cont columns: Device contact columns number.

Check here for more information
‹Hard_constrain: This function provides an option to constrain
the value for each parameter in this device.
‹Res_update_method: (l_&_W, Res_&_W) Res update
method, please review segment width
and segment length function.
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z Varactor Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in varactor are list as below:

‹Model name: Display model name information.

‹Description: Display device description.
(These parameter can’t be modify in CDF form)

‹CapValue@1.2V(F): Device capacitance information.

‹CapValue@0V(F): Device capacitance information.
‹CapValue@-1.2V(F): Device capacitance information.
(These parameter can’t be modify in CDF form)

‹With Mismatch Effect: Option for run mismatch effect

‹Width(M): Device width.
‹Length(M): Device length.

‹Multiplier: Numbers of parallel Varactor device.

Check here for more information

‹Hard_constrain: This function provides an option to constrain

the value for each parameter in this device.

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z LogicGate Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in inverter are list as below:

‹HspiceS: Display model name information.

‹InterfaceLastC..: Display device description.
‹partName: Display device description.
‹vendorName: Display device description.
‹viewNameList: Display device description.
(Cell information)

‹Model name: Display model name information.

‹Description: Display device description.
(These parameter can’t be modify in CDF form)

‹Length of PMOS(M): All pmos length.

‹Width of PMOS(M): All pmos width.
‹Fingers of PMOS(M): All pmos fingsers.

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 TSMCN65 PDK Usage Guide Confidential

z LogicGate Parameterized Cell Function Introduction:

Security C

„ The schematic component description format (CDF) parameter in varactor are list as below:

‹SA of PMOS(M): All pmos SA.

‹SB of PMOS(M): All pmos SB. .
‹SC of PMOS(M): All pmos SC.
‹SD of PMOS(M): All pmos SD.

‹Length of NMOS(M): All nmos length.

‹Width of NMOS(M): All nmos width.
‹Fingers of NMOS(M): All nmos fingsers.
‹SA of NMOS(M): All nmos SA.
‹SB of NMOS(M): All nmos SB. .
‹SC of NMOS(M): All nmos SC.
‹SD of NMOS(M): All nmos SD.

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CDF Parameter Description

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z The function of Number of Fingers_(N)

Security C

„ This parameter provide user to increment the poly finger numbers.

Number of Fingers_(N)=1 Number of Fingers_(N) =3

Number of Fingers_(N)=8 Number of Fingers_(N) =12

Check here to back to MOS

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z The function of Multiplier

Security C

„ This parameter provide user to increment the parallel device.

Multiplier = 1 Multiplier = 2

Check here to back to MOS

Check here to back to BJT
Check here to back to Diode
Check here to back to Resistance(1)
Check here to back to Resistance(2)
Check here to back to Varactor

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z The function of ShareLeftShape and ShareRightShape

Security C

„ These functions provide user to preview the device difference before and after
abutment. When the user abuts the devices in layout view, system will auto determine
the abutment type of the both device. These two function can be selected to preview
the layout but they can’t be used to determine abutment type. Please check Appendix A for the details

Abut the two device in

the layout view

system auto determine

User select for review only

Check here to back to MOS

Change the ShareRightShape
to large

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z The function of Calc Diff Params and Calc SA SB SD

Security C

„ It’s a switch for input simulation parameter that include area of source (AS), area of
drain (AD), periphery of source (PS), periphery of drain (PD), number of squares
source resistance (NRS), number of squares drain resistance (NRD) and LOD effect
parameter- SA , SB and SD. Modify those parameters only influence simulation
conditions, the design layout will not have any different.

Calc Diff Params is enable Calc Diff Params is disable

Parameters can’t be modify Parameters can be modify

Check here to back to MOS

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z The function of DFM_options

Security C

„ This option provides user to select design rule in the layout is follow minimum rule or DFM
rule1 or custom self define. When User selects the custom selection, the input spaces
appear below the DFM_options. DFM option will check PO.EX.1, PO.EN.1.R, PO.EN.2.R
and PO.EN.3.R rule.

CDF parameter V.S Design Rule number comparison table

DFM_options = custom
CDF Parameter TSMC N65 Design Rule
Upper_PO_EX_INC(M) PO.EX.1
Lower_PO_EX_INC(M) PO.EX.1
GA_GA_SP_INC(M) PO.S.11.R
GA_CO_SP_INC(M) CO.EN.3.R
OD_CO_EN_INC(M) CO.EN.1.R
M1_CO_EN_INC(M) M1.EN.1.R
GA_OD_SP_INC(M) PO.S.5.R
OD_GA_EN_INC(M) PO.EX.2.R
CO_CO_SP_INC(M) -
PO_CO_EN_INC(M) CO.EN.3.R
PO.EN.1.R
NW_GA_SP_INC(M)
PO.EN.3.R
OD2_GA_EN_INC(M) PO.EN.2.R
Design rule document number:T-N65-CL-DR-001
Check here to back to MOS

1
Design For Manufacturing (DFM) rule is a recommendation rule that TSMC provide customer to minimized
process variation and yield benefit. For the details, please review TSMC 65NM CMOS Design RULE.
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z The function of DFM_options

Security C

„ This option provides user to select design rule in the layout is follow minimum rule or DFM
rule1 or custom self define. When User selects the custom selection, the input spaces
appear below the DFM_options. The DFM+Analog will check PO.EN.1m, PO.EN.2m,
PO.EN.3m.

DFM+Analog option check the following rules:

DFM_options = DFM+Analog

PO.EN.1m >= 1.0um

PO.EN.2m >= 2.0um
PO.EN.3m >= 1.5um

Check here to back to MOS

1
Design For Manufacturing (DFM) rule is a recommendation rule that TSMC provide customer to minimized
process variation and yield benefit. For the details, please review TSMC 65NM CMOS Design RULE.
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z The function of Ldiff_ext, Rdiff_ext, LGA_CO_SP_INC(M)

Security C

and RGA_CO_SP_INC(M)
„ Those function provide user to increment the area of left and right diffusion and the
space form contact to poly.

Ldiff_ext RGA_CO_SP_INC(M)

LGA_CO_SP_INC(M)

Rdiff_ext

Check here to back to MOS

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z The function of leftCnt, RightCnt

Security C

„ The function provide a option for drawing poly-left (right) diffusion area metal1 connect
leftCnt is enable leftCnt is Disable

Check here to back to MOS

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z The function of bodytie_typeL and bodytie_typeR

Security C

„ The function provide a option for drawing body connection at the device left
(bodytie_typeL) or device right (bodytie_typeR).

bodytie_typeL is None bodytie_typeL is Integred bodytie_typeL is Detached

Check here to back to MOS

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z The function of SDshrink Confidential
Security C

„ The function is provided to modify the metal dimension on source or drain area. It’s a
list include five numbers. The first number is used to decide which metal user want to
modify. The second number is used to shrink the dimension of the metal top. The third
number is used to shrink the dimension of the metal bottom. The fourth number is used
to extend the dimension of the metal left and right. The fifth number is used to
increment the contact space in the metal. The number of these five numbers must be
positive and the unit is micrometer.

A=0 A=3 A=2 A=1 A=4

B

(A B C D E)
A:select metal
B:metal Top shrink
C:metal bottom shrink
D:metal side shrink D
E:contact space increment

Check here to back to MOS

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z The function of POshrink Confidential
Security C

„ The function is provided to modify the poly gate dimension. It’s a list include three
numbers. The first number is used to decide which metal user want to modify. The
second number is used to shrink the dimension of the poly gate top. The third number
is used to shrink the dimension of the poly gate bottom. The number of these three
numbers must be positive and the unit is micrometer.

A=1
B
A=4 A=3 A=2

(A B C)
A:select poly gate
B:poly gate top shrink
C:poly gate bottom shrink

Check here to back to MOS

C
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z The function of routePolydir Confidential
Security C

„ The function is provided to drawing poly gate connection. The space of poly gate
connection to the diffusion area can be modify by routeUPoly_SP_INC(M) and
routeDPoly_SP_INC(M) 2.

The poly Contacts will appear when routPolydir doesn’t

None. It is an option to draw contact on the poly gate.

PO.S.6(design rule)
+ routeDPoly_SP_INC

Check here to back to MOS

2
The routeUPoly_SP_INC(M) and routeDPoly_SP_INC(M) only appear when routePolydir doesn't None.

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z The function of routePolydir Confidential
Security C

„ The function is suggest to use in multi-finger. If customer use only one finger and turn
on the routePolydir none/top/bottom/both direction. It will shows the following layout.

Finger=1

none top bottom both

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z The function of routePolydir Confidential
Security C

„ Finger number=3. If customer use finger number=3 and turn on the routePolydir
none/top/bottom/both direction. It will shows the following layout.

Finger=3 none top

bottom both

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z The function of routePolydir Confidential
Security C

„ Finger number=3. Customer use finger number=3 and turn on the routePolydir
none/top/bottom/both direction. At the same time customer uses Poshrink option as
following : Finger=3

none bottom top both

none bottom top both

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection.

route_Source_Drain is Both

Check here to back to MOS

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection(it happens to nf >1).
User need to pay attention for the following case Nf=2; it means the mos has two
source and one drain. If you turn on this function your source-drain metal layer will
extend a distance.
M1 extend a distance

none source drain both

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection(it happens to nf >1).
User need to pay attention for the following case Nf=3; it means the mos has two
source and one drain. If you turn on this function your source-drain metal layer will
extend a distance.

M1 extend a distance M1 extend a distance M1 extend a distance

none source drain both

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection(it happens to nf >1).
User set SD shrink function, the mos layout will shrink the length as following.

1 2 3 1 2 3

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection(it happens to nf >1).
User set SD shrink function, the mos layout will shrink the length as following.

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection(it happens to nf >1).
User set SD shrink function+route_source_drain, the mos layout will shrink the length
as following.
M1 extend M1 extend M1 extend

none source drain both

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z The function of route_Source_Drain Confidential
Security C

„ The function is provided to drawing source and drain connection(it happens to nf >1).
User set SD shrink function+route_source_drain, the mos layout will shrink the length
as following.
M1 extend M1 extend M1 extend

none source drain both

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 z The function of route_Source_Drain Confidential
Security C
„ The function is provided to drawing source and drain connection(it happens to nf >1).
User set SD shrink function+route_source_drain+routePolydir, the mos layout will
shrink the length as following.Note with SD route, the poly will extend more length than
none SD route.

routePolydir:NONE

routePolydir:TOP

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Security C
„ The function is provided to drawing source and drain connection(it happens to nf >1).
User set SD shrink function+route_source_drain+routePolydir, the mos layout will
shrink the length as following.Note with SD route, the poly will extend more length than
none SD route.

routePolydir:Bottom

routePolydir:Both

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z The function of fingers_SP_INC(M) Confidential
Security C

„ The function provide user to modify poly gate space. Fingers_SP_INC(M) is a increase
value, it’s not a distance between poly gate.

fingers_SP_INC(M) = 0 fingers_SP_INC(M) = 0.5

Check here to back to MOS

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z The function of BJT_type

Security C

„ There are three dimension of pnp and npn are provided in this PDK, user can use this
function to choose those device layout.

BJT_type = 5X5 BJT_type = 10X10

Check here to back to BJT

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z The function of Total resistance(ohms), Segment width(M),

Security C

Segment length(M) and Res_update_method

„ In the resistance cell, we provide user two kinds of input method – l_&_W and Rec_&_W to
modify the device resistance. When the user select l_&_W method, the input parameter will
be segment length(M) and segment width(M), the other one is total resistance(ohms) and
segment width(M).

select l_&_W method

Check here to back to Resistance(1)

select Rec_&_W method
Check here to back to Resistance(2)

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z The function of Resistor connection, Number of segment,

Security C

Segment spacing(M)
„ Number of segment provide user a function to Increment the number of segment
resistance, user can use Resistor connection and Segment spacing(M) to modify
connection type – series or parallel and segment spacing.

Number of segment = 2
Resistor connection = series
Segment Spacing(M) = 2.4u
Segment Spacing(M)

Number of segment = 2
Resistor connection = parallel Check here to back to Resistance(2)
Segment Spacing(M) = 4.8u

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z The function of Cont columns

Security C

„ This function provide user to modify the contact columns.

Cont columns= 1 Cont columns= 3

Check here to back to Resistance(2)

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z The function of HVMOS (nch_hv25/pch_hv25)

Security C

„ This function provide user to modify the device layout

Length
Width
Total_width
NF

HVD (n_a)

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z The function of PMOSCAP_RF

Security C

„ This function provide user to modify the device layout

Width

Length
Finger of group
Group number
Add DMEXCL
layer

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z The function of CRTMOM

Security C

1. No problem to add different

metal layer connection
flexibility.
2. Allow right&left side for
connection but need to
consider improper metal
routing caused additional
parasitic capacitances.

Extra Parasitic devices

will be extracted in yellow
mark region. Need to
consider very careful.
TSMC don’t recommend
this kind connection.
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Appendix

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z Appendix A - Abutment
Security C

„ To make the user understand this function, we describe more details and examples
about abutment in this section. There are two point about this function is important, first
this function only support MOS device in this PDK, second there are the same type
MOS (ex: nch and nch_18, pch and pch_25) can be abutted only.
„ When user abut two device, the terminal B must connects certainly in the layout view
so it must be connected to the same net in the schematic view.
„ The system will auto determine abutment type of the both device. User can’t modify
abutment type.
„ The same devices abut case as show in below :(Case Ⅰ)

Device nch (W=0.2u) nch (W=0.2u)

The view in schematic
Abutment type

Before Abutment

After Abutment

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 Confidential
Security C

„ Abutment ability lets you overlap two MOS, to create a connection between two sets
of shapes overlapping each other. The two sets of shapes must include pins
connected to the same net. (Case Ⅱ)

Device nch (W=0.2u) nch (W=0.2u)

The view in schematic
Abutment type

Before Abutment

After Abutment

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„ This case show out the different width device have been abutted. (Case Ⅲ)

Device nch (W=0.2u) nch (W=0.4u)

The view in schematic
Abutment type

Before Abutment

After Abutment

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„ This case show out that the same type MOS also can be abutted. (Case Ⅳ)

Device nch (W=0.2u) nch_25 (W=0.4u)

The view in schematic
Abutment type

Before Abutment

After Abutment

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z Appendix B – Stretch Handles

Security C

„ This function lets user graphically change the value of those parameter for Pcell
instances after user place them. The only one device MOS is a stretchable Pcell in this
PDK.
„ The system default is not show out the stretch handles, user must be enable the
function manually. (Direct: in the layout view Options → Display option → Stretch
Handles )

Stretch Handles number Stretch direction

→ ←
11 1
→ ←
2
7 12 8 →
3, 5
←
4, 6
↑
7, 8
↓
9, 10
↓
11
1 3 4 5 6 2 ↑
13
↓ ↑
12

9 10
13

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„ A example to show out the stretch case when the user stretch the handle 12. Security C

Width = 2.0u →3.0u

Width = 3.0u

Width = 2.0u

Select handle 11 Release the handle

and move up the
handle.

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z Appendix C – The three terminal MOS substrate pin

Security C

„ In three terminal MOS, we create a parameter for substrate pin. The pin name is vss_sub in
NMOS and vdd_sub in PMOS. When user instances the three terminal MOS, all of the
devices substrate terminal will connect to vss_sub or vdd_sub. User doesn't need to draw
the wire to link the device. In the hierarchy structure, user can add a parameter in CDF form
to assign the substrate terminal name.

When user instances the nchx and nch_18x (three

terminal MOS), all of the devices substrate terminal
will connect to vss_sub (VSS!)

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„ In the hierarchy structure, user can add a parameter in CDF form to assign the substrate
terminal name.

Create cellview to build

up the symbol

Instance the symbol to other schematic view

and assign the vss_sub to V_sub

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z Appendix D – TSMC Utility

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z tsmcPdkUtility Tool „Change OD layer to N/P diffusion

„ VXL Fold and Chain setting „Create GuardRing utility
„ Switch DFM options „3T-diode utility
„ Switch instances for DFM options
„TSMC Layout Dependent Effect Utility
„ Switch instances between basic <-> mac
„ Switch instances for WPE options „Layout vs. Layout
„ Update design(instance)CDF „ZoomIn(sch/lay) with history
„ Add MOM license key „File Browser & Viewer

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„ Sometimes TSMC PDK user will use symbolic link to use the PDK, user will encounter a
problem - documents and technology file path missing. TSMC provide tsmcPdkDocumentView
function to solve this problem. The function will re-connect the document directory and replace
the default path setup.

Close window
Library select

File Browser

View PDK document

View Local document

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„ The function of tsmcPdkFC_set is a utility function fold and chain.

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„ The function of Switch DFM options will set the pcell to mimRule or DFM or DFM+Analog or
custom setup. User can specify own device list to decide which device(s) this utility applies to.

Select library

Description

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„ The function of Update design(instance)CDF will run TSMC CDF parameter update utility.

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„ The function of tsmcPdkChangeOD will change the N+OD and P+OD layer.

Select TSMC process

N+OD layer

P+OD layer

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„ The function of tsmcPdkZoomIn is a utility to help user easy to find the layout.

Input coordinates Create boundary

Coordinate history

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Way1
Select layout window input coordinates and check Apply Window zoom in

Way2
Select layout window

Double check coordinate history

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ztsmcPdkUtilityTool : Confidential
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„The function of Layout vs. Layout can be used to compare two layouts and show
differences between the.

First cell setup Second cell setup

Flatten option

Function description

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„ tsmcPdkLVL utility: Before LVL After LVL

Cell:testA

Cell:testA_xor_testB

Cell:testB

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„ tsmcPdkFileViewer – TSMC file browser tool, user can easily find the file they needs.

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„Create GuardRing utility – TSMC Guard-Ring utility. Allow user to easily create guard-ring
with flexibility. For more information please refer to “Guard Ring Utility Usage Guide”.

Guard-Ring utility for layout view

. DRC clean
. Create ring path by mouse draw
. Create ring box by mouse click
. Create ring box outside of the each selected instances
. Create ring box outside of the whole selection
. Flexibility for the ring box by specified distance
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zAbout this PDK Tool Confidential
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This function pops out a window that shows PDK information including:
„Library name
„PDK Version
„Metal Scheme, IO voltage, Process Type.
„Contact email.

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z Appendix E – AS AD PS PD NRS NRD methodology

Security C

„ In this section, we will description that the PDK how to calculate as, ad, ps, pd, nrs and nrd.

Case I
• Normal MOS with multi fingers
S Area _ total = ∑ sWidth_i × w AS = S Area _ total
i =1
fingers = 2
S Peri _ total = ∑ ( sWidth_i + w × N s ) × 2 PS = S Peri _ total
i =1
sWidth _ i dWidth _ i sWidth _ i
D Area _ total = ∑ dWidth_i × w AD = D Area _ total
i =1

DPeri _ total = ∑ ( dWidth_i + w × N d ) × 2 PD = DPeri _ total

i =1

N s : Number of Source N d : Number of Drain

W NRS = ( ∑ CG _ i _ s + SG _ s + DG _ s ) / fingers / w
i =1

NRD = ( ∑ CG _ i _ d + SG _ d + DG _ d ) / fingers / w
i =1

2 × CG _ i
CG _ i _ d : CG_i in Drain diffusion area
SG DG
CG _ i _ s : CG_i in Source diffusion area

SG _ d ( SG _ s ) : SG in Drain(Source) diffusion area

Half contact width DG _ d ( DG _ s ) : DG in Drain(Source) diffusion area

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Case II
• Dog Bone MOS with multi fingers
fingers = 2
AS = S Area _ total
sWidth _ i dWidth _ i sWidth _ i
PS = S Peri _ total

SG AD = D Area _ total
W
PD = DPeri _ total
2 × CG _ i
DG NRS = ( ∑ CG _ i _ s + SG _ s + DG _ s ) / fingers / w
dogBoneW _ i i =1

Half dogBoneW_i NRD = ( ∑ CG _ i _ d + SG _ d + DG _ d ) / fingers / w

i =1

CG _ i _ d : CG_i in Drain diffusion area

S Area _ total = ∑ sWidth_i × w + dogBoneW _ i × dogBoneW _ i × N s
i =1
CG _ i _ s : CG_i in Source diffusion area
D Area _ total = ∑ dWidth_i × w + dogBoneW _ i × dogBoneW _ i × N d
i =1
SG _ d ( SG _ s ) : SG in Drain(Source) diffusion area
S Peri _ total = ∑ sWidth_i × 2 + dogBoneW _ i × 4 × N s
i =1

DPeri _ total = ∑ dWidth_i × 2 + dogBoneW _ i × 4 × N d DG _ d ( DG _ s ) : DG in Drain(Source) diffusion area

i =1

N s : Number of Source N d : Number of Drain

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Case III
S Area _ total = ( ∑ sWidth_i + dsWidth ) × w
• Normal MOS with multi fingers after abut i =1

S Peri _ total = ( ∑ sWidth_i + dsWidth + w × N s ) × 2

i =1

D Area _ total = ( ∑ dWidth_i + ddWidth ) × w

fingers = 3 i =1

DPeri _ total = ( ∑ dWidth_i + ddWidth + w × N d ) × 2

dsWidth sWidth _ i dWidth _ i i =1

N s : Number of Source N d : Number of Drain

AS = S Area _ total PS = S Peri _ total

AD = D Area _ total PD = DPeri _ total

W
2 × CG _ i
DG NRS = ( ∑ CG _ i _ s + SG _ s + DG _ s ) / fingers / w
i =1

NRD = ( ∑ CG _ i _ d + SG _ d + DG _ d ) / fingers / w
SG i =1

CG _ i _ d : CG_i in Drain diffusion area

CG _ i _ s : CG_i in Source diffusion area

Half contact width
SG _ d ( SG _ s ) : SG in Drain(Source) diffusion area
DG _ d ( DG _ s ) : DG in Drain(Source) diffusion area

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z Appendix F – SA SB SD methodology
Security C

„ In this section, we will description that the PDK how to calculate sa and sb.

„ For post-layout simulation (netlists extracted from the layout):

Treat each finger of devices as an independent MOS. And
thus PDK assigns different SA/SB to each independent MOS. SA1 SB1
So the netlist will look like (if finger_number=3): SA2 SB2
m1 d g s b w=channel width l =channel length SA=SA1 SB=SB1 SA3 SB3

m2 d g s b w=channel width l =channel length SA=SA2 SB=SB2

m3 d g s b w=channel width l =channel length SA=SA3 SB=SB3

„ For pre-layout simultation (netlists estimated from schematic diagram):

PDK sets m=finger_number, SA=SA, SB=SB and SD=SD. So the netlist will look like
m0 d g s b w=channel width l =channel length m=1 SA=SA SB=SB SD=SD
Please refer next two page to understand the SA, SB and SD in layout

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„ In this page, we will description that the PDK how to calculate SA, SB and SD. Security C

Case I
• Normal MOS with multi fingers
fingers = 3 SA = sa : In the netlist, SA equal to sa
SB = sb : In the netlist, SB equal to sb
SB = sd : In the netlist, SB equal to sd

sa
sb
sd

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„ In this page, we will description that the PDK how to calculate SA, SB and SD. Security C

Case II
• Dog Bone MOS with multi fingers

fingers = 3
SA = sa : In the netlist, SA equal to sa
SB = sb : In the netlist, SB equal to sb
sa sd
sb SB = sd : In the netlist, SB equal to sd
l

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„ In this page, we will description that the PDK how to calculate SAeff and SBeff. Security C

Case III
• Normal MOS with multi fingers after abut

Sum1i = 1 /( Lwidth + i × ( sd + l ) + 0.5 × l )

fingers −1
fingers = 3 SAeff = fingers / ∑ Sum1 − 0.5 × l
i =0
i

Sum 2i = 1 /( Rwidth + i × ( sd + l ) + 0.5 × l )

Lwidth fingers −1
SBeff = fingers / ∑ Sum 2
i =0
i − 0 .5 × l

Rwidth SAeff = SAeff

sd
SBeff = SBeff
l
SA = SAeff : In the netlist, SA equal to SAeff
SB = SBeff : In the netlist, SB equal to SBeff

SA = sa : In the netlist, SA equal to sa

SB = sb : In the netlist, SB equal to sb
SB = sd : In the netlist, SB equal to sd

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z Appendix G – Multiple devices Abutment methodology

Security C

„ In this section, we will describe that the PDK how to use multiple devices abutment
with Ldiff_ext and Rdiff_ext

M1 M0

M1: M0: M0
M1
Ldiff_ext(M):10n Ldiff_ext(M): 0n (Ldiff_ext=10n) (Rdiff_ext=0n) (Ldiff_ext=0n) (Rdiff_ext=10n)
Rdiff_ext(M): 0n Rdiff_ext(M):10n 185n 175n 175n 185n

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„use multiple devices abutment with Ldiff_ext and Rdiff_ext

M1 M0 Abutment

(Ldiff_ext=10n)
185n (Rdiff_ext=10n)
185n
55n 55n

The contact to left-poly is equal to right-poly :55n

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z Appendix H – MOS pcell usage GA_CO_SP_INC

Security C

z Function introduction

z GA_CO_SP_INC : Add gate to contact spacing for DFM

„ Real spacing = GA_CO_SP_INC + Original spacing

z Ldiff_ext : extend left-hand side OD

z Rdiff_ext : extend right-hand side OD

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z Appendix H – MOS pcell usage GA_CO_SP_INC

Security C

z Problem description

z Mos pcell
„ When turning on bodytie as integred and set GA_CO_SP_INC to 700n,
mos pcell will fail.

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z Appendix H – MOS pcell usage GA_CO_SP_INC

Security C

z Problem solution

z Correct usage method :

„ Before setting GA_CO_SP_INC, Ldiff and Rdiff should extend first.
„ Let contacts have space to insert or contact will over-extend.

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z Appendix I
Security C
– Sdshrink and Poly Gate position

z Routing method : M1 will extend if route_source_drain option set to “both”.

Both to Source

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z Appendix J – SCA SCB SCC for Well Proximity Effect/WPE

Security C

„ In this section, we will describe that the PDK how to calculate parameters sca, scb and
scc for WPE.

¾ Input: GATE, WELL

¾ Output Property: SCA, SCB, SCC

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