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8 7 6 5 4 3 2 1
C12000
XW11101
XW11100
672 671 669 667 665 663 661 659 657 655 653 651 649 647 645 643 641 639 637 635 633 631 629 626 623 621 619 617 615 613 611 609 607
673 599
C10836
R10807
XR11101
XR11100
XR11102
C11121
C11134
C11101
C11100
C11133
C11106
C11102
C11120
XR12000
627 625 598 726
PP214_R
XW5011
668 666 664 662 660 658 656 654 652 650 648 646 644 642 640 638 636 634 632 630 620 618 616 614 612 610 608 605
628 624 622
674
670
606
597
675
PP203_R
PP208_R
PP12910
PP209_R PP206_R PP12800 PP221_R
SB12500 677 676

C324_R R319_R
C388_W R365_W C387_W
FD12513 FD12504 604
C6400
C334_R
C6420
J10800 678
J11100
FL302_R
C304_R 596
JUAT1 680 679
603
C301_W
681 L6400 C481_W C480_W
C6421
C315_R
602
R309_R
C314_R
C6401
683 682 R316_R 595
594
DPLXR_U_W
R4900
C482_W
600
C405_W
R301_W
684 C317_R 601
R306_R
C311_R
XR10821
FL10830
FLBPF8_R
R10804
C10823
C10826
C10827
C10822
R10803
C10831
C10821
C10816
C10824
C10819
C6436 593 591
C407_W
XR11130 686 685
XR11104
XR11105
XR11103
R5540
XR11110
C11104
C11105
C11130
C11103
C11110
C6402
C333_R
C479_W
C6430
C302_W
687
PP219_W PP218_W C301_R C323_R R318_R C406_W
C11024
PP200_R C6403 592 590
C10805
689 688
C10710
C10708
C10709
C10711
TP7507_S C11025 C11031 C12001
C6438
FD12510 FL11014
R5541
U_ROSE_R
FL301_R
C6423 C303_R
C6428
690 C332_R
C461_W
C408_W
R11024
C304_W
DZ11014 XR11039 XR11012 XR11013 XR11010
R311_W
XR11106
FL10501
C10903
C10904
C10905
C10902
C10900
C10901
C10501
589
R11107
C404_W
C10553
588
XW11000
692 691 U6400 C308_W
C6422
R308_R
C313_R
R317_R
C11034 R11023 C11023 C11039
C10502
DZ11012 DZ11013 DZ11010 PP213_R
C10503
693
C6429
C6437
C6435
R463_W
FD12502 587 586
695
C379_W
C381_W
C312_R C322_R
C6412
C10536
R307_R
R10550
694
U_2G_U_W
C10542
584 585
PP12907
698
C11022
R11021
R11020
C466_W
C10537 706 704 702 700
727
FL300_R
FL10410
709 708 707
J10900
C322_W
C380_W
C6411
696
C6410
C10550 FD12514
R5400
J11000 J10700
C302_R
R5851
583 581
R325_R
C10541
C206_R
697
705 703 701 799
U5940 U_5G_U_W
XR11004
C10551
R10100
C10120
C10100
C11004
C491_W
R315_R
C5941
C300_R
710 713
R5402 XR12711 582 580
C321_W
R5850
FLHPF6_R
C10410
C3934_E
C305_R
614
C10540
C5940
C10403 C362_W
C10552
C5391
R10540 578 579
J_INT_BOT C5397 C207_R C201_R C205_R R10703 C200_R
C202_R
R210_R
C5961
C203_R
C204_R
C10704 C10703
C323_W
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C3902_E
C10432
R5510
R5511
C10912
C10914
R10914
C10913
C10910
C10911
615
FL10500
R363_W
C382_W
C10544
C5304
R305_R
C10500
U5960
C10546
FL10110
FL10120
FL10100
XR11038
XR11037
DZ11015
FL10700
C10701
C10700
C10729
C10715
C10717
C10728
C10714
R10701
C10702
FL11015
C11020
C11032
C11003
C11002
C11038
C11001
C11037
C11033
C11030
R11030
C11041
C5305
C10104
C10103
C11021
C7547_I
C7566_I
FL10420 L3933_E
577
C10713
TP7508_I
C5311
PP12902
R200_R
XW12715
C10545 C310_R
C7012
C7001
C10554 C10421 616 R9930 C9910 576
R3903_E
C5960 C309_W
C389_W
C361_W C306_W
C7011
XR310_W
XR12712
C10543 C9911
R5960
C10431
711 717 U5300 C7000 575
C7548_S
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C5400
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PP211_R
C10534
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C7098
U9910 U11040 U4300 572
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R5530 R5401
L3904_E
C7096
C7547_S C10524 C10535 712 721 619 618 C3901_E R3904_E
J10500 L5300 573
C7567_I
FD12505
C3904_E
TP7508_S TP12616 TP12688 TP12711 TP12687 C10405 C10444
TP7507_I
C5310
XW7539_S
C5680
C5690
C5670
C5695
C7546_S C10525 622
J10400 C11040 C4300 574
PP12809
C10404 C10445 PP12808
723 720
J10100 C5610
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R9910 R11040 571
R9911
C10531
C7558_S C5611
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C10400 C10442
C10522
L7000 U7000 C9921 570
C7565_I
C10530 724
C5330 C5350 C5395 C5392 U2420 L3902_E R3901_E C3903_E L3903_E
C5693
U9920
C7093
C7094
C7541_S
C7542_S
C7514_S
C7512_S
C10401 C10443 C5303
FL10660
TP12713 TP12712
C2420
C10523
R2422
569
1
C5650
C10662
C10660
C10661
C10600
C10601
C10620
C10650
C10640
C10671
C10670
XR10620
XR10650
XR10640
XR10670
C10402 C5302 C5393 568
C5640
C5340
C5360
C5370
C5380
C5390
C7545_I
2
R5930
C10532
C10520
R10402 C10440
3
XR9920 C7503_I C7507_I 567
R5403
C7519_I
C5697
TP12710 TP12714
L7501_I
L7500_I
C7091
C7092
XW5300
C10533 C5911
XR12100
FL10130
566
C10105
C10106
C7568_I
C7543_I
C7542_I
C7541_I
C7551_I
C7513_I
C7510_I
C7550_I
C7514_I
C7512_I
C7515_I
C7548_I
C7546_I
R2423
C5301
C10441
C7010
C10447
4
R7509_I C7508_I
C10406 U5600 C5900 C7005 T7500_S
C10521
565
R2426
5
C5692
R2424
U5930
C10434
C5902
C7539_I C7506_I
C12100
C5930
10
127
C10446 6
XW
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127
PP12908
U5910
13
R5710
C10130 PP7580_I PP7581_I
C10110 R10110 564 563
J10600
XW7000
C10511
JUAT2 7 R2425
C10504
C7526_I
C7530_I
C7020
R5505
R5506
C7022
R5521
R5520
C7021
C7095
C7090
R7509_S C7551_S C7510_S R7508_S
U5900
C5320
C7097
8
C5931
PP209_W
C10512 C7524_I C7521_I
Y3602
C5912
C5300
561
XR12714 9 C7503_S C7513_S C7550_S C7507_S C7540_I C7525_I
R5860
C5903
C5910 562
C5901
C5914
C3654
R7503_S
10 C5604 C5700 C5691 R5720 R5861 PP12901
C7500_I
C10510 C7522_I 559
PP12900
FL10510
11 PP12903 PP12906 R7502_S
L7501_S L7500_S C7519_S
SB12501 SB12503 C7534_I
560
XR10651
XR10630
XR10691
FL10680
C10694
C10690
C10693
R10610
C10610
C10692
C10695
C10651
C10630
C10682
C10681
C10691
FL10690
PP12810 PP12905
12
NFC_F
R14200
C7504_S
R7501_S
R7500_S
C7524_S
PP212_R 59 C7509_I
64 558
C10513 13 C7539_S C7506_S
C7540_S
C7530_S
24 26 28 30 32
R14201
16 34
XW13900
R7510_I
C7536_I
C10611 XR10692 FD12500 FD12511 18 20 22 36 38 40 42 44 46 48 50 52 54 56 58 62 PP7543_S
65 66
C7526_S C7535_I 557 556
TP12650 TP12651 TP7506_I TP12686 TP12715 TP7506_S TP12661 TP12685 14 25 27 29 31 33 C7521_S
PP7580_S PP7581_S
23
PP7542_S
C7527_I
15 17 19 21 35 37 39 41 43 45 47 49 51 53 55 57 60 63 C7532_I
C7500_S
FL7500_I
C7525_S
555 554
67 C7528_I
68 C7522_S
C7537_I
C7529_S R7508_I
70
C7534_S
C7538_I 551 553
69
NFC_P
C7511_I
71 C7509_S
C7505_I
C7517_I
C2900
C2942
C2944
C2923
L7502_I
552
C7502_I
Y7500_S
C7536_S
C2902
PP7540_I
72 73
FL2923
C2908
C2906
C2907
C2955
C2957
R12513 R12514 R12504 R12505 R12506
C2946 C2924 R12507 R12508 R12509 74
C7535_S
R12511
548 550
C7532_S
75
R12510
C7537_S
C7528_S
R7569_I
549
C4409 C4406
76 C7531_S
R12512
FL7500_S
77 C7508_S
R12531
545 547
C7527_S
C7538_S
78
C7511_S
C7505_S
C7517_S
C2947
C4404
C4401
C4402
C4403
C4407
C4408
79
Q4400 546
R12532
R4401
80
C7573_S
R7571_S
C7571_S
81 L7502_S 541 544
C2952
C2960
82
C7572_S
R7572_S
C7502_S PP7508_S 543
83
C2935
C8122
C8120
C4410
C4422
C4424
C4427
C4426
C4411
C4437
C2959
PP12860
XW4410
84 PP12832
C4421
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540 542
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85
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86
539
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00
538
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89
C2941 535
C2945 90 C8124 C4428
C4433 534
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533
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91
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R12530
C2921
C4435
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92
531
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93 C4436
C2937
C2963
530
94 C8103
PP12897
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C4441
R2963 95
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C2951
528
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C8100
R2901 96
C4465
PP12894
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527
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C4463
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C2910 97
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XR4412
526
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C2911
PP12871
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C2940
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PP12865
99
C4461
PP12864
C4467
C2926
C4462
524
C4466
PP128A3
R7821
C7821 C7901
100
C7800
C7801
PP12899
TP12653 523
C4464
PP128A4
FL2925
101 522
C2901
PP128A11
C2925
102
PP12801 R2341 C7931 C7820 C7911 R7800 R7801 R7810 R4461 U4600 521
C4631
103 520
R2340
C2920 PP12895
104 519
C2909
C2922
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C2915
105 C4639 C4652 PP12893 518
106 517
C2903
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516
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C2943
C
108
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PP12835
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515
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109
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110
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C2954
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111
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C7925
C2916 112
PP12823
PP128A0 C4653 512
511
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113
C2938
PP12930 PP12931 510
R1260
PP128A10
114
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509
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C2918
C7932
C1700
C2929
C2919 115 PP12834
C2936
508
R1240
R2310
R0722
R0720
R0723
R2311
R1100
R1001
116 507
C7903 R0700
C2912
117
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PP12818
118
C7926
PP12855
C3525 505
R0721
PP12853
119 504
C2025
C3351
C2026
C3341
C3343
C3520
PP12852
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C2913
C7928
C3580
120 503
C2010
C1904
C2091
C2011
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PP12873
PP12804
PP12848
PP12856 PP12868
PP12850
PP12854
PP12805
PP12824 PP12876
123 PP12890 PP12866 PP12851
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PP12803 PP12826 PP12825 PP12849
PP12875
PP12874
PP12807 500 499
124
C2098 R2420 R2421 R1250 R1300 R12502 R1401 R1210 C1210 R12501 R1200 C1200 C3340 R0712 R0713 R1121 C2099 R1010 R1131
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497
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C3670
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126
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C3342
C1937
C1963
C2087
R3670
U9400 127 496
L3340 L3350
CN63 CN61 CN60 CN59 CN58 CN57 CN55 CN53 CN51 CN49 CN47 CN45 CN43 CN42 CN40 CN38 CN36 CN34 CN32 CN30 CN28 CN26 CN24 CN22 CN21 CN19 CN17 CN15 CN13 CN11 CN9 CN7 CN6 CN5 CN4 CN3 CN1
C1811 C3382 C9490 128 495
R10120
C1863
C1862
C2088
CM63 CM62 CM61 CM60 CM59 CM58 CM57 CM55 CM53 CM51 CM49 CM47 CM45 CM43 CM42 CM40 CM38 CM36 CM34 CM32 CM30 CM28 CM26 CM24 CM22 CM21 CM19 CM17 CM15 CM13 CM11 CM9 CM7 CM6 CM5 CM4 CM3 CM2 CM1
C3430 129
494
C2093 CL63 CL62 CL61 CL60 CL59 CL58 CL57 CL55 CL53 CL51 CL49 CL47 CL45 CL43 CL42 CL40 CL38 CL36 CL34 CL32 CL30 CL28 CL26 CL24 CL22 CL21 CL19 CL17 CL15 CL13 CL11 CL9 CL7 CL6 CL5 CL4 CL3 CL2 CL1
493
XW1902
XW3430
130
R2451 C9400
C1808
C3371
C2030
CK63 CK62 CK61 CK60 CK59 CK58 CK57 CK55 CK53 CK51 CK49 CK47 CK45 CK43 CK42 CK40 CK38 CK36 CK34 CK32 CK30 CK28 CK26 CK24 CK22 CK21 CK19 CK17 CK15 CK13 CK11 CK9 CK7 CK6 CK5 CK4 CK3 CK2 CK1
C3432 492
C1941 C1910 C3380 C1964 XW0711 C2080 131
L3400
CJ63 CJ62 CJ61 CJ60 CJ4 CJ3 CJ2 CJ1
491
C1809
132
00
C1908
C3300
49
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C3364
C2073
C1865
C1830
C1812 490
C1999
C1918
C1932
C1917
C1931
CH63 CH62 CH61 CH60 CH4 CH3 CH2 CH1
L3380
133
C3381
CG56 CG54 CG52 CG50 CG48 CG46 CG44 CG41 CG39 CG37 CG35 CG33 CG31 CG29 CG27 CG25 CG23 CG20 CG18 CG16 CG14 CG12 CG10 CG8
L3430 134
CF63 CF62 CF61 CF60
CE56 CE54 CE52 CE50 CE48 CE46 CE44 CE41 CE39 CE37 CE35 CE33 CE31 CE29 CE27 CE25 CE23 CE20 CE18 CE16 CE14 CE12 CE10 CE8
CF4 CF3 CF2 CF1 489
XW3340
135 CD63 CD62 CD61 CD60 CD4 CD3 CD2 CD1 488
C3301
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CC56 CC54 CC52 CC50 CC48 CC46 CC44 CC41 CC39 CC37 CC35 CC33 CC31 CC29 CC27 CC25 CC23 CC20 CC18 CC16 CC14 CC12
C1916
C1947
C1998
R3300
12
C1806
66
L3401
1
136 487
C2033 C1872
CB63 CB62 CB61 CB60 CB4 CB3 CB2 CB1
C3640 C2032 L3301
XW5010
C1807
CA52 CA50 CA39 CA37 CA35 CA33 CA31 CA29 CA27 CA25 CA23 CA20 CA18 CA16 CA14 CA12
486
XW3300 137 CY63 CY62 CY61 CY60 CY4 CY3 CY2 CY1
PP12887
XW3380
BW52 BW50 BW39 BW37 BW35 BW33 BW31 BW29 BW27 BW25 BW23 BW20 BW18 BW16 BW14 BW12
485
C3450 C3451 C3452 C3673 C3453 C3454 C3455 C3469 C1909 C1927 C3603 C1801 138 BV63 BV62 BV61 BV60 BV4 BV3 BV2 BV1
BU52 BU50 BU39 BU37 BU35 BU33 BU31 BU29 BU27 BU25 BU23 BU20 BU18 BU16 BU14 BU12 BU10 BU8 484
139
C3401
L3360 C1803 PP12879 BT63 BT62 BT61 BT60 BT4 BT3 BT2 BT1
XW3301
C3457
C1906
140 BR56 BR54 BR52 BR50 BR48 BR46 BR44 BR41 BR39 BR37 BR35 BR33 BR31 BR29 BR27 BR25 BR23 BR20 BR18 BR16 BR14 BR12 BR10 BR8 483
C1907 R1012 PP12880 BP63 BP62 BP61 BP60 BP4 BP3 BP2 BP1
482
C1805
141 BN56 BN54 BN52 BN50 BN48 BN46 BN44 BN41 BN39 BN37 BN35 BN33 BN31 BN29 BN27 BN25 BN23 BN20 BN18 BN16 BN14 BN12 BN10 BN8
BM63 BM62 BM61 BM60 BM4 BM3 BM2 BM1
R1011
C1804
C3456
C3302 142 481
L3300 BK63 BK62 BK61 BK60 BL56 BL54 BL52 BL50 BL48 BL46 BL44 BL41 BL39 BL37 BL35 BL33 BL31 BL29 BL27 BL25 BL23 BL20 BL18 BL16 BL14 BL12 BL10 BL8 BK4 BK3 BK2 BK1
C3493 480
C3504
143
C3362 BJ63 BJ62 BJ61 BJ60 BH56 BH54 BH39 BH37 BH35 BH33 BH31 BH29 BH27 BH25 BH23 BH20 BH18 BH16 BH14 BH12 BH10 BH8 BJ4 BJ3 BJ2 BJ1
R12503
PP128A8
C3458
144 479
C3403 BG63 BG62 BG61 BG60

BF56 BF54 BF39 BF37 BF35 BF33 BF31 BF29 BF27 BF25 BF23 BF20 BF18 BF16 BF14 BF12 BF10 BF8
BG4 BG3 BG2 BG1
XW
478
34
145
00
XW3360
C1802
C1810
80
C3492
BE63 BE62 BE61 BE60 BE4 BE3 BE2 BE1

35
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C3363
BD56 BD54 BD39 BD37 BD27 BD25 BD23 BD20 BD18 BD16 BD14 BD12 BD10 BD8
477
C3472
146
R3620
C3505
U1000
BC63 BC62 BC61 BC60 BC4 BC3 BC2 BC1
C3402
476
147 BB56 BB54 BB39 BB37 BB27 BB25 BB23 BB20 BB18 BB16 BB14 BB12 BB10 BB8
R3651
C1891
BA63 BA62 BA61 BA60 BA4 BA3 BA2 BA1

148 475
L3302
C1928
AY56 AY54 AY39 AY37 AY27 AY25 AY23 AY20 AY18 AY16 AY14 AY12 AY10 AY8
C3699
C3509
C1901
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AW63 AW62 AW61 AW60 AW4 AW3 AW2 AW1

474
149
C1945 AV56 AV54 AV39 AV37 AV35 AV33 AV31 AV29 AV27 AV25 AV23 AV20 AV18 AV16 AV14 AV12 AV10 AV8
C1902
C1948
C1895 150
AU63 AU62 AU61 AU60 AU4 AU3 AU2 AU1
473
C3460
C3521
XW3650 XW3646 AT56 AT54 AT52 AT50 AT48 AT46 AT44 AT41 AT39 AT37 AT35 AT33 AT31 AT29 AT27 AT25 AT23 AT20 AT18 AT16 AT14 AT12 AT10 AT8
C3540 U3300
XW1901
AR63 AR62 AR61 AR60 AR4 AR3 AR2 AR1 472
XW3410
C1894 151
AP56 AP54 AP52 AP50 AP48 AP46 AP44 AP41 AP39 AP37 AP35 AP33 AP31 AP29 AP27 AP25 AP23 AP20 AP18 AP16 AP14 AP12 AP10 AP8
C3491
471
C3412
152 AN63 AN62 AN61 AN60 AN4 AN3 AN2 AN1
C3459
C3507
C3610 C3361
AM56 AM54 AM52 AM50 AM48 AM46 AM44 AM41 AM39 AM37 AM35 AM33 AM31 AM29 AM27 AM25 AM23 AM20 AM18 AM16 AM14 AM12 AM10 AM8
C1893
153 AL63 AL62 AL61 AL60 AL4 AL3 AL2 AL1

00
C1892
50
470
XW
L3410
469
PP12881 154 AJ63 AJ62 AJ61 AJ60
AK56 AK54 AK52 AK50 AK48 AK46 AK44 AK41 AK39 AK37 AK35 AK33 AK31 AK29 AK27 AK25 AK23 AK20 AK18 AK16 AK14 AK12 AK10 AK8
AJ4 AJ3 AJ2 AJ1
XW5001
C3506
C3411
C3461
C1926
PP12882
C3360
155 AG63 AG62 AG61 AG60 AH56 AH54 AH52 AH50 AH48 AH46 AH44 AH41 AH39 AH37 AH35 AH33 AH31 AH29 AH27 AH25 AH23 AH20 AH18 AH16 AH14 AH12 AH10 AH8 AG4 AG3 AG2 AG1
467
R1014
156 AF63 AF62 AF61 AF60 AF4 AF3 AF2 AF1
AE56 AE54 AE52 AE50 AE48 AE46 AE44 AE41 AE39 AE37 AE35 AE33 AE31 AE29 AE27 AE25 AE23 AE20 AE18 AE16 AE14 AE12 AE10 AE8
Y3601 466
R3650
C3410 R1015
C3462
XW3310
157
C3651
AD63 AD62 AD61 AD60 AD4 AD3 AD2 AD1

AC56 AC54 AC52 AC50 AC48 AC46 AC44 AC41 AC39 AC37 AC35 AC33 AC31 AC29 AC27 AC25 AC23 AC20 AC18 AC16 AC14 AC12 AC10 AC8
L3411
465
XW3600
XW3420
C3490
158
C3407
C1905
Y3600 L3370
AB63 AB62 AB61 AB60 AB4 AB3 AB2 AB1
AA52 AA50 AA48 AA46 AA44 AA33 AA31 AA29 AA27 AA25 AA23 AA20 AA18 AA16 AA14 AA12 AA10 AA8 464
R3652
159
C3508
C3652
Y63 Y62 Y61 Y60 Y4 Y3 Y2 Y1

W52 W50 W48 W46 W44 W33 W31 W29 W27 W25 W23 W20 W18 W16 W14 W12 W10 W8 463
160
XW
33
20
C3370
C1942
V63 V62 V61 V60 V4 V3 V2 V1

462
C1860
C1874
161 U52 U50 U48 U46 U44 U33 U31 U29 U27 U25 U23 U20 U18 U16 U14 U12
C3535
C3653
R1960
T63 T62 T61 T60 T4 T3 T2 T1

461
C1900
XW3330 162 R56 R54 R52 R50 R48 R46 R44 R41 R39 R37 R35 R33 R31 R29 R27 R25 R23 R20 R18 R16 R14 R12
PP12885
L8900
460
C3310
C1996
P63 P62 P61 P60 P4 P3 P2 P1
163
C3523 C1933 C1935 C3468 C3467 C1955 C3466 C3470 C3463 C3483 C3464 C3465
PP12886 N56 N54 N52 N50 N48 N46 N44 N41 N39 N37 N35 N33 N31 N29 N27 N25 N23 N20 N18 N16 N14 N12
459
L3311
M63 M62 M61 M60 M4 M3 M2 M1
C1923
PP12888 164
XW12660
L56 L54 L52 L50 L48 L46 L44 L41 L39 L37 L35 L33 L31 L29 L27 L25 L23 L20 L18 L16 L14 L12 L10 L8
R1970 R2022 C2050 R2021 458
FL1950
C2086
C1920
C2020
K63 K62 K61 K60 K4 K3 K2 K1

C3522
C2090
C2082
C1936
C2085
C1946
C1970
C1950
C1922
C1997
C2081
165
C2092
70
C1873
XW1940
33
C1903 C1940 457

XW
J56 J54 J52 J50 J48 J46 J44 J41 J39 J37 J35 J33 J31 J29 J27 J25 J23 J20 J18 J14 J12 J8
R1961 H63 H62 H61 H60 H4 H3 H2 H1
C2000
C2052
C1938
166
C1995 C1921 PP128A7 C1831 G63 G62 G61 G60 G4 G3 G2 G1

456
C1924
167
C2001 PP12817
455
U8900
168 G63 G62 F61 F60 F59 F58 F57 F55 F53 F51 F49 F47 F45 F43 F42 F40 F38 F36 F34 F32 F30 F28 F26 F24 F22 F21 F19 F17 F15 F13 F11 F9 F7 F6 F5 F4 F3 F2 F1
C8906
PP12814
C1834
C1832
C3311
XW4910
454
169 F63 F62 E61 E60 E59 E58 E57 E55 E53 E51 E49 E47 E45 E43 E42 E40 E38 E36 E34 E32 E30 E28 E26 E24 E22 E21 E19 E17 E15 E13 E11 E9 E7 E6 E5 E4 E3 F2 F1
PP12812
XW4920
453
U9500
170
L3420 D63 D62 D61 D60 D59 D58 D57 D55 D53 D51 D49 D47 D45 D43 D42 D40 D38 D36 D34 D32 D30 D28 D26 D24 D22 D21 D19 D17 D15 D13 D11 D9 D7 D6 D5 D4 D3 D2 D1
L3330 L3390 L3320 171

452
L3310
C9561
C63 C62 C61 C60 C59 C58 C57 C55 C53 C51 C49 C47 C45 C43 C42 C40 C38 C36 C34 C32 C30 C28 C26 C24 C22 C21 C19 C17 C15 C13 C11 C9 C7 C6 C5 C4 C3 C2 C1
L3321 172
451
XW1000
B63 B61 B60 B59 B58 B57 B55 B53 B51 B49 B47 B45 B43 B42 B40 B38 B36 B34 B32 B30 B28 B26 B24 B22 B21 B19 B17 B15 B13 B11 B9 B7 B6 B5 B4 B3 B1
C3312 C1833 L9550 173

A63 A62 A61 A60 A59 A58 A57 A55 A53 A51 A49 A47 A45 A43 A42 A40 A38 A36 A34 A32 A30 A28 A26 A24 A22 A21 A19 A17 A15 A13 A11 A9 A7 A6 A5 A4 A3 A2 A1
450
449
C3390 C2097 174
C9551
PP128A5
448
C9562
PP12891
C3330 C3420 R3603 C3672 C9563 175
R1622
R1621
R1620
R1601
R2440
R2441
R3661
R11621
R1608
R2431
R8310
R8300
R2430
R1603
R1606
R1607
R1610
R1650
R1002
R4910
C3481
C2710
C3480
C2701
C2700
C3482
R1021
C1020
C1021
C2096
R2450
R1013
C1140
R1140
C2711
C1103
C1102
R12500
R11620
C1113
C1112
C3320 C9552
B
XW
B
PP12892 447
33
90
C3392 176
C9550
C3331 C3421 446

C8900
PP12858
C8902
177
C4012
445
178
C3391 444
C3321
C3423
C1864
C1866
179
C3334 C3422 PP12844 PP12889
C4025
C4044
443
C9601 R2461
C8903
180 PP12841
C4024
C4022
C4040
PP12843
C9603
R8900
442
C4200 C4023 U8910 181
PP12842
R2460
L4000 L4001 Y1000
C3590
441
C3510
C3332 182
C4090 PP12837
C4041
U9600
L9300
440
C3408
183
C4201
C4001
C1122
C4011
R3610 C4010 439

C3406
C4091
R3600 184
C1123
C3333 C4092
C4004
438
L9301
185
U4000
C3515
C9600
C4203 C3566 C3570 C3405 186 PP12813 C4204 C4202
437
C3471 C4210 C4042 C4003 C9602 436

187
C4005
PP12877
PP128A9 PP12878
435
XW4200
188
C8400
PP128A2
434
189 C4007 C4008
SH12501 L4200 433
FL11230
191
190 C4060 C4006
U4200 432
R2470
R2474
R2476
TP12643 TP12642
C4061
C2471
C11295
C11291
C11290
C11297
C11296
431
C9123
192
0
PP12821
84
PP12861
430
12
C8323
C4045
PP
C8325
C12541
C8322
C8321
C8320
C8300
193
C4062
XR9122
429
C4290
C9102
194 U2470 428
C11292
C9121
C8324
C8303
C4043
PP12845
C11294 195 PP12846
427
L9120 196
L9110 C11293 426
SB12504
C8309
197 PP12822
C11274 R11275 425
XW
C9104
83
C9192
C9101
R9120
R9121
00
PP12857
C12540
198
C9194
C8340
R11291 C11270 424
PP128A6
U8400
199
C9131
C9124
C11271 423
R11276
C8306
C11272
200
422
C11241
C9120
201 R8050 U8300 421
C11240
C11243
C9130
PP12820
R8301
C8307
202 PP9100
420
PP12838
C8330
C9125
XR11203
XW11560 203
XR11500
C11273
419
U9100
C11275
C11242
C11254 204
C8308
R8311
418
R9101
R11505
C9133
C11560
R9131
XR11253 205
C8008 417
XR11580
XW11570
206
R11290
XR11250
C11250
C9134
C11253 416
L9130 C8301 C8302
C8006
XR11511
C8007
L9100 C8304
C9122
207
XW12674
XW12672
C9132
C9111
C8004
C11211 415
XW11582
208
414
C11570
C11252
XR11252
C4310
FL11501 XR11211
U4310
C8009
209
413
C9110
C9193
C8022
C8020
C11213
C9100
C9106
C11513
J11200 210
C9105
00
412
80
XW
FL11502
C11206
PP12833
C11207
XR11550
C4311
C11504 211
R11213
R4311 C9117 R9130 411
PP12828
XR11509
C8000
PP12831
C8025
C11501 212
410
C9195
C11581
C11230
C11233
C9103
U8000
213 PP9101
C11503 409
C11502
XR11512
C11500
214 C8021 PP12830 C9112 408
C11583
C11236
215
C8023
PP12829
407
C9390
PP12839
C11550 C8003
C11580 PP12920
216
C8001 U9300 PP12884 406
C11507
J11500 C9391
R9102
C11582 XR11202 217
C11210
C11630
C8024
405
TP12671 TP12670 TP12673 TP12640 TP12680 TP12636
C8002
PP12883
C11512
C11511 C11264 218
C9395
U11640 U11630 404
C9330
C11509 C11263 219
C9310 PP12862
U11620 403
C11506
C11262
C11260
C8030 C8040
C11621
C11642
PP12921
TP012601 TP012600 TP12602 TP12603 TP12641 TP12635 R11210 220
402
R11283
C9301 R9301 C2470 R9100

XR11263
R11630
221
401
XR11260
PP128A1
L11540
L11520
222
400
TP12614 TP12672 TP12674 TP12675 TP12610 TP12638
354
398 396 394 392 390 388 386 384 382 380 378 376 374 372 370 368 366 364 362 360 358 356
XR11262
223
352
L11500
L11510
355
TP12613 TP12615 TP12681 TP12701 TP12660 TP12637 399 397 395 393 391 389 387 385 383 381 379 377 375 373 371 369 367 365 363 361 359 357
C11285
224
350
C11282 226
C11287
R11282
C11283
R11280
225
R11281
R2003_E R2009_E C2004_E C2009_E C2006_E C2007_E C2005_E C2003_E C2008_E C2201_E R2206_E R2203_E C2207_E XR2207_E R2205_E
348 349
R2204_E
C11280
C11286 228
227
346 347
XR2006_E
C2211_E
230
C2010_E
229 345
C2205_E
232
XW10000
XW10001
R2005_E
C2202_E
TP12639 TP12700 TP12630 343 344
231
C2203_E
233 342
R2002_E
C2206_E
TP12612 TP12611 TP12631 234
PA_LB_E PAUHBL_E
236
C2212_E
340 341
R4920
C2001_E
235
R2007_E
C2204_E
PP217_W 238 339
C2208_E
C10002
DZ10003 237
L2001_E
R2209_E
R4100
240 337 338
C10003
01
41
XW
C8901
A
239 XW4100
C10001
R2473
A
XR11507
L2002_E
336
R2008_E
C2210_E
XW11690 R11631
J10000 242
241
335 334
iPhone 12 Pro
C11691 C11603
C2301_E
C2312_E
C3603_E
XR11696
244 R2208_E
C2209_E
C3602_E
R2004_E R2305_E C2315_E C2303_E
SYNC_DATE=18/10/2021
XR2304_E
C2307_E
C11693 DZ10004 FD12503 R2308_E C2310_E
XR11610 243
333 332
C10004 246
R3601_E
C11608 C11610
R2391
DPLX7_E
DRAWING TITLE
R3602_E
R2301_E
C415_W
R2475 245 C471_W R473_W C476_W C492_W
D53AP EVT MLB LAYOUT

C11604 C11605 FD12515 331 330
R2472 248
J11600
C3601_E
R2390
C11641 C11600
C3604_E
R2302_E
R2306_E
247
329
R11611
XR11609
C11640 C11602
328
L3601_E
R3603_E
XR11697
C11694 C11609 249
C413_W
C416_W
C417_W
C2308_E
PA_LMB_E
C3605_E
327
R11616
XR11606
L3602_E
250 326
C11697 C11606
U_2G_L_W 323
PART NUMBER SIZE
R11601
251
C11601 C11607 PP231_W
C484_W
820-01955 D
C2306_E
R11608
252 322 325

PP230_W C483_W C485_W 321 324
XR11607
www.itesla.solutions REVISION
253
C418_W
https://paypal.me/Torsioniforums/
C486_W
254 320 315
FD12512
SB12505 255 319
C2309_E
256 C414_W
C489_W
R466_W
C490_W
A.1.0
R2307_E C2305_E C2314_E C2302_E C2313_E C2311_E 318 314
257 260 C2304_E
262
FD12501 264
258 259 261 317
263 266
316 313
NOTICE OF PROPRIETARY PROPERTY:

268 271 274 277 280 283 286 292 298 301 304 307
265
310 311 312 AUTHOR
Filip Pusca
725
267 270 273 276 279 282 285 288 291 294 297 300 303 306 309
269 272 275 278 281 284 287 290 293 296 299 302 305 308
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF ITESLA SOLUTIONS.
THE POSESSOR AGREES TO THE FOLLOWING: ASSEMBLY
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
A/B
PAGE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 0/1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
607 609 611 613 615 617 619 621 623 626 629 631 633 635 637 639 641 643 645 647 649 651 653 655 657 659 661 663 665 667 669 671 672 PP5910_E
599 673
726 598 625 627

PP5901_E PP5903_E
PP5902_E
605 608 610 612 614 616 618 620 630 632 634 636 638 640 642 644 646 648 650 652 654 656 658 660 662 664 666 668
622 624 628
XW5040
PP5905_E PP5904_E
674
670
606 PP5908_E
597 675 PP5909_E
PP5907_E
676 677
604 C3107_E
R12565 R12566 R12550 R12551 R12552 R12553 R12554 R12555 R12556 R12557 R12558 R12575 R12568 R12559 R12560 PP5906_E TM12500
FD12500 FD12515
678
R12569
R3104_E L3101_E R3101_E
C5902_E
R3103_E
596 679 680
603
L3102_E
602 681
R12582
CPLR_U_E J_SMYR_E
C3106_E
595 C3110_E
594 682 683
600
C3702_E
TPLX2_E 684
R3702_E
601
C3109_E
R3106_E
R12561
591 593
C3105_E
685 686
C3108_E
687
U_BG1_E
L3701_E
C3704_E
590 592
R12570
C4305_E C4306_E C3102_E 688 689
C3103_E
C3104_E
C5901_E
DPLX8_E
C3201_E
R3105_E
L3103_E
690
R3703_E
L3702_E
588 589
R12577
C4302_E 691 692
L1_LNA_E
R5040
C3701_E
C3101_E U4300_E 693
XR4302_E
586 587 C4301_E
C3705_E
695
R12562
XR4303_E
U_TAN_E
C3703_E
R3701_E
694
585 584 FD12517
C3202_E L3202_E R3201_E L3201_E 698

C4303_E C4304_E FL4301_E 700 702 704 706
707 727
708 709
R12571
696
R2505_E
581 583
697
C2702_E SH12511 799 701 703 705
713 710
FD12510
580 582 C2701_E
R12578
C5828_E
L2501_E
614
C5810_E
C5813_E
C5811_E
C5816_E
C5812_E
C5821_E
C5822_E
C5825_E
C5830_E
C5809_E
XW5813_E
579 578
DSM_LB_E C2503_E R7304
_E
XW5810_E
XW5811_E
J_INT_TOP
06
58
R12563
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615 PP4616_E
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PP4668_E PP4679_E
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PP235_W
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577
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576 616
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L2500_E
C2504_E
717 711
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575 R7315 C7303
XR2502_E
572 R7303
R12581
C5827_E
618 619 721 712
C7304
573
R2503_E R2501_E FD12521 U7340 U7310
574 C1807_E R12579 R12574 R12576 R12567 R12564 R12573 R12580 R7321 622
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571 C2502_E C2501_E C2904_E XR2905_E U_SMR_E C1806_E XR7317
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PP4652_E
570 C5806_E
724
C1808_E
PP4604_E
R6340
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PP4603_E PP4641_E
R2904_E
U_APTU_E
C5932_E
569
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1
FD12502
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U6300 ST12500
568
2 PP4619_E
C6591
C6342
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567
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FL5931_E
3
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C5914_E
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12
C7300
58
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XW
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XW5824_E
6
C5818_E
C5815_E
C5817_E
C5819_E
C5820_E
C5804_E
C5824_E
C5826_E
C5805_E
C5808_E
C5807_E
XW5814_E
XW5804_E
C1802_E
XW
563 564
58
05
C5801_E
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C5814_E C5823_E L1800_E 7
R2902_E
XW5803_E
L6340
C6341
8
561
C6505
U6500 9
562 C1800_E 10
SH12512
559
C6506 C6343
11
C5921_E
C5922_E
C2612_E C2613_E C2608_E R2601_E
560
59
12
J_FEZ_E
C2601_E
558 64
13
32 30 28 26 24
FL5921_E
34 16
62 58 56 54 52 50 48 46 44 42 40 38 36 22 20 18
556 557
R2709_E
66 65 33 31 29 27 25 14
23
PP12807
63 60 57 55 53 51 49 47 45 43 41 39 37 35 21 19 17 15
PP12801
PP12808
PP12803
PP12806
554 555
PP12800 PP12805 PP12804 PP12809 PP12802 PP12820
67
C2709_E
68
R2704_E
70
553 551
69
L2602_E
DSMUHB_E
C2602_E
71
R2702_E
552
73 72
DSM_HB_E
R2607_E
R2708_E
74
550 548
R2703_E
75
L2601_E
C2708_E
549 76
FD12507
R2701_E
FD12516
77
547 545
R2606_E
78
C2609_E
79
546
80
R2603_E C2704_E
C2723_E
C2706_E
C2604_E
C2606_E
C2603_E
C2605_E
544 541 81
R2604_E XR2705_E
82
XR2608_E
543 83
C2610_E R2609_E C2611_E R2610_E R2602_E R2605_E
84
542 540
85
C201_W R233_W C202_W C231_W R238_W C244_W R12589 C230_W R237_W C243_W C5912_E C5911_E 86
539
FD12518
87
FD12530
FL5911_E
537 88
538
89
R12596
535
90
533 534
91
532
R12597
C270_W 92
531
93
530
FL_ISG_U_W
C246_W
94
C232_W
R912_E
529
C326_W
95 PP4710_E
528
96 PP4630_E
PP221_W
527 FD12508
C250_W
R5635_E
C257_W
97 PP220_W
R910_E
R911_E
526
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PP4683_E
98 PP211_W
C907_E
525 C204_W
PP212_W
U_WLAN_W
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99 PP213_W
C252_W
C908_E
524
C203_W C254_W 100 PP236_W
523 PP215_W
PP205_WPP203_W
PP243_W
522 101 PP237_W

R914_E
R257_W
R913_E
C228_W
C241_W
R235_W
PP207_W PP239_W
102 PP214_W
521
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PP244_W
C245_W
520 103 PP4688_E
PP206_W
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519 104
PP201_W
R259_W 105 PP232_W PP202_W
517
518
C256_W 106
107
516 PP225_W
108
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L255_W
PP224_W
515
R202_W
PP223_W
109 PP226_W
R12586
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514 PP227_W
PP222_W
110
PP228_W
513
C205_W 111 PP229_W
C226_W R15001 C905_E C904_E R12587
R5030
C906_E
C730_E
R15000
C233_W
C247_W
C709_E
C712_E
C715_E
R12588
C714_E
C785_E
C738_E
C725_E
R907_E
R905_E
PP4704_E
512
C704_E C728_E 112 PP4669_E
C604_E C603_E C765_E
C789_E
511
R12583
113
510
PP4680_E
C
509 114
R12584
PP4664_E
PP4609_E
R904_E
508 115 PP4608_E
PP4645_E
XW604_E
507 116 PP4690_E
Y601_E UBBPMK_E PP4673_E
R12585
506 117 PP4656_E PP4647_E
C735_E
PP4651_E
PP4653_E
505 118 PP4610_E
PP12811
504 C752_E 119 PP4670_E
C605_E XW602_E
503 120
R678_E
C721_E
C758_E
PP4636_E
C602_E
R607_E
502 121 PP4637_E
501
C601_E
C746_E 122 PP4634_E
PP4635_E
C902_E
JDEBUG_E
123
PP241_W TP5702_E
C750_E
500 C903_E
499 124 PP240_W
C751_E
C755_E
125
C756_E TP5700_E
497 C701_E C759_E
126
PP4717_E
C760_E
496 127 TP5703_E
C775_E
C757_E
495
FD12506 C747_E 128
494
C754_E
U_BB_E 129
TP5701_E
R901_E
C705_E PP4706_E
493 130
492
C732_E C720_E
C718_E PP242_W
131 PP4705_E
PP4675_E
PP4698_E
C707_E
491 C749_E
C768_E
132
R5634_E
490
C713_E
C779_E 133
489 C783_E
C716_E 134
488 C781_E PP4693_E

135
R909_E
C710_E
R908_E
487
EEPROM_E C769_E 136
486 PP4658_E
137
485 C706_E C702_E 138

PP4685_E
PP4674_E
C901_E
PP4600_E
PP4695_E
484 C776_E 139
PP4696_E
C736_E PP4661_E PP4694_E
483
C722_E 140 PP4691_E
C742_E
PP4687_E
482
141 PP4649_E
R5610_E
R5611_E
481
C726_E 142
PP4681_E PP4650_E PP4684_E
C737_E
480
C734_E PP4666_E PP4686_E
143
479 C788_E C743_E

PP4665_E
R5605_E
R5604_E
144 PP4700_E
478
145
C787_E C774_E C724_E C723_E
C773_E
C782_E
C708_E
C780_E
C784_E
C711_E
C778_E
C740_E
C739_E
C786_E
C717_E
C744_E
C771_E
C719_E
C767_E
C772_E
C741_E
C770_E
C727_E
R903_E
R902_E
477 U7500 146
R5602_E
R5601_E
C731_E
476 C777_E C729_E
C748_E 147
PP4703_E
475
C764_E C761_E C733_E 148
474
C523_E
E
1_
149
70
C7501 C7500
C407_E
XW501_E
XW702_E
XW
473 150
C432_E
C414_E L401_E L406_E L405_E
E
5_
C413_E
40
472
XW
151
C762_E
C763_E
PP4623_E
471
152
C411_E
C433_E
C406_E
153
469 470
C1905_E C1904_E C412_E 154
XW401_E
XW5030 155
C518_E
C517_E
467
C401_E 156
PP4719_E
PP4676_E
C1900_E
C435_E
466
157
465 R5632_E PP4660_E
R601_E 158
464 C1901_E R5631_E
R602_E C522_E 159
PP4714_E
L407_E
R610_E
463 R5633_E
C513_E
XW601_E
160
C503_E
C1908_E
462
U_APTL_E 161
C608_E
C526_E
C402_E
461
UBBPMU_E 162
C410_E
460
C1907_E
XW406_E PP4715_E
L1900_E C408_E
XW605_E
163 PP4671_E
PP4622_E
459
XW408_E
164
C525_E
C528_E
458 C516_E PP4605_E PP4606_E

C1906_E
165
XW407_E
R631_E
C524_E
PP4632_E PP4663_E
457
C430_E
E
2_
PP4720_E
40
XW
C515_E 166 PP4677_E

PP4702_E
XW403_E R632_E PP4662_E
456
C502_E 167
455
C1903_E C514_E R630_E PP4709E
PP4707_E
C1902_E
168
C405_E
XW404_E
C501_E
454
C512_E 169
C427_E
C509_E
453 PP4613_E
C4403_E C4404_E 170
L403_E
PP4648_E PP4612_E
C403_E
452 FL4401_E
C511_E 171 PP4713_E
PP4646_E
PP4701_E
PP4639_E
451 C4401_E XW502_E
172
450 U4400_E L404_E L402_E
PP4638_E
C431_E
C429_E
173 PP4654_E
449
C404_E
174 PP4708_E
FD12520
C434_E C409_E
XW1163_E
448
175
447 XW1114_E
XW1231_E
PP4682_E
176
XW1185_E
XW
12
82
_E
XW1229_E
446 XW1181_E
XW
SH12510
XW1232_E
12
XW1187_E
XW1283_E
XW1101_E
85
177
_E
XW1102_E
XW1289_E
XW1233_E
XW1152_E
445 PP4721_E
XW1112_E
XW1113_E
178
XW1237_E
XW1184_E XW1182_E XW1201_E

XW1186_E
C1140_E
XW1166_E
444
C1136_E C1226_E
XW1189_E
C1141_E
179
XW1103_E
C1234_E
C1233_E
C1203_E
C1236_E
C1202_E
C1105_E
C1230_E
C1129_E
C1238_E
C1239_E
C1231_E
C1106_E
C1221_E
C1101_E
C1121_E
C1204_E
C1211_E
C1102_E
XW1230_E
XW1291_E
XW1287_E
XW1238_E
XW1151_E
XW1215_E
XW1216_E
443
XW1211_E
XW1208_E
XW1209_E
XW1210_E
C1135_E
XW1288_E
C1123_E C1401_E
C1218_E C1206_E XW1153_E R5636_E 180 PP4627_E
XW1202_E
442
XW1183_E
PP4626_E
181
XW
XW1223_E
11
15
441
_E
C1144_E
B
182
B
XW1156_E
440
C1201_E 183
FD12522 PP4633_E
439
438
C1103_E
XW1106_E U_SP3T_E 184
PP4642_E
C1205_E 185
XW1203_E
437
C1110_E 186
XW1107_E
436
C1126_E 187
C1132_E
C1138_E
XW1157_E
PP4611_E
435
FL1401_E
XW1164_E
188
C1219_E XW1224_E XW1117_E
434 C1118_E PP4624_E
189
C1220_E XW1225_E
C1120_E
433
XW1119_E
190
C1127_E
C1139_E
432 XW1158_E
C1117_E 191
PP4657_E
C1209_E
431 XW1204_E C1143_E PP4659_E
XW1120_E
192
U_SDR_E
XW1108_E
PP4601_E
430 C1114_E R12590
193 PP4602_E
429 C1400_E
C1142_E
R12591
194
428 C1228_E XW1236_E
C1116_E
195
427 C1104_E
_E
18
11
XW1109_E
XW
C1119_E PP4628_E
196
426 C1212_E
C1137_E
_E
PP4629_E
65
11
XW1205_E
XW
C1133_E 197
XW1212_E
PP208_W
XW1214_E
XW1213_E
425 C1130_E
XW1159_E
R12592 PP4644_E
198
424
C1222_E XW1226_E
R12593 199
PP4620_E
423 C1111_E
XW1110_E
R12594 200
XW1111_E
422
C1215_E PP210_W
XW1206_E
R12595 201
421
XW1227_E
XW1286_E
C1223_E 202
R1402_E
L1402_E
L1406_E
420
203
419
C1227_E
204
418
R1403_E
XW1281_E
L1403_E
L1407_E
XW1235_E
XW
C1210_E
C1128_E
C1235_E
C1207_E
C1237_E
C1145_E
C1112_E
C1213_E
C1131_E
C1225_E
C1115_E
C1217_E
C1229_E
C1134_E
C1107_E
C1216_E
C1125_E
C1113_E
C1232_E
C1122_E
C1108_E
C1224_E
C1208_E
C1109_E
C1214_E
C1124_E
C1712_E
C1713_E
11
XW1154_E
XW1217_E
XW1218_E
60
XW1240_E
XW1105_E
XW1104_E
_E
XW1162_E
XW1228_E
XW1239_E
XW
205
XW1161_E
11
55
417
_E
206
416 XW1207_E
207
415
208
414
C1718_E
C1615_E
C1716_E
C1612_E
C1717_E
209
C1708_E C1608_E C1613_E
R1713_E
413
L1701_E L1601_E
R1613_E
PP4699_E
210 PP4697_E
412
411 C1701_E 211
C1704_E C1604_E C1601_E 212

C1603_E
C1703_E
410 XW1702_E XW1602_E

C1707_E
XW1601_E 213
409 XW1701_E FD12519
C1607_E
C1705_E
214
408
215 PP4621_E
407 C1605_E PP4643_E
216
406
U_QET1_E U_QET0_E
L1703_E L1603_E
C1609_E
C1709_E
217
405
C1706_E C1606_E
C1614_E
C1714_E
PP4678_E
218
404
L1702_E L1602_E 219
C1610_E
C1710_E
403
C1715_E
C1711_E
C1611_E
R1712_E
R1612_E
220
402
221
401 PP4718_E
222 PP4716_E
400
354
356 358 360 362 364 366 368 370 372 374 376 378 380 382 384 386 388 390 392 394 396 398
223
352
355 357 359 361 363 365 367 369 371 373 375 377 379 381 383 385 387 389 391 393 395 397 399
PP4672_E
224
350
226
R3801_E C3801_E R2804_E R2801_E R2803_E R2802_E XR2107_E C2109_E C2103_E C2105_E C2107_E R2101_E R2102_E 225 PP4615_E
PP4614_E
349 348
XR2805_E
228
C3804_E
227
347 346
C2804_E
230
345
DPLX9_E 229
C2803_E
232
C3802_E
344 343
MIMO_L_E 231
C2801_E
C2110_E
R3802_E
342 233
C3805_E
C3803_E
R3803_E
L3802_E
L3801_E
234
341 340 236
C2802_E
R2110_E
235
R2106_E
339 XR364_W 238

C325_W
C324_W
C384_W
C2120_E
C371_W 237
C333_W C376_W R373_W
R2105_E
338 337 C2111_E
PA_HB_E 240
C318_W
C386_W R2108_E 239

C316_W
336 R2103_E
C385_W C2115_E 242
C2113_E
R2104_E
334 335 U_5G_L_W C314_W C383_W
R2111_E
241
C319_W
PP4631_E
244
C2101_E
C310_W
C311_W
C2121_E
243
332 333
BPF_L_W R312_W
246
245
330 331 C312_W R313_W
A
C313_W
C2108_E FD12511 FD12503
A
248
C3502_E
C3302_E
329
C315_W C3503_E R3502_E
C3010_E
247
iPhone 12 Pro
328 C3523_E
R3003_E
L3302_E
249
SYNC_DATE=19/10/2021
PP4711_E
R3522_E PP4625_E PP4607_E
327 C3007_E
326 250
C3522_E
323
C2102_E
L3301_E R3301_E C2114_E 251

TPLX3_E DRAWING TITLE
L3001_E
D53BB EVT MLB LAYOUT

325 322 252
324 321
DPLX1_E
C3301_E
R2109_E
R3004_E 253
315 320 254

L5_LNA_E CPLR_L_E
C3009_E
C2112_E
319 255
L3502_E R3005_E C3008_E
C3501_E
R3503_E
R3501_E
L3501_E
256
C3003_E
C3004_E
C3005_E
PART NUMBER SIZE

314 318 260 257
L3503_E C3504_E 262
C3006_E R3002_E
820-01970 D
264
317 261 259 258
www.itesla.solutions REVISION
266 263
313 316
https://paypal.me/Torsioniforums/
307 304 301 298 292 286 283 280 277 274 271 268
265
312 311 310
725
309 306 303 300 297 294 291 288 285 282 279 276 273 270 267
A.1.1
308 305 302 299 296 293 290 287 284 281 278 275 272 269
ST12501
SB12510
NOTICE OF PROPRIETARY PROPERTY:
XR12202
XR12200
XR12201
C4123_E
C4121_E
C4120_E
C4133_E
C4132_E
C4101_E
R4123_E
R4101_E
R4121_E
R4120_E
R4133_E
R4132_E
FL12205
C12203
C12200
C12205
C12202
AUTHOR
Filip Pusca
C4131_E
C4130_E
C4100_E
R4122_E
R4131_E
R4100_E
R4130_E

SB12511
PROPRIETARY PROPERTY OF ITESLA SOLUTIONS.
C4122_E
JLAT THE POSESSOR AGREES TO THE FOLLOWING: ASSEMBLY

J_SIM_E I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
A/B
R4140_E
FD12512

PAGE
FD12501
IV ALL RIGHTS RESERVED 1/1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK
D53 Top MLB

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
4 2020-04-03
EVT
LAST_MODIFICATION=Fri Apr 3 17:41:42 2020 LAST_MODIFICATION=Fri Apr 3 17:41:42 2020 LAST_MODIFICATION=Fri Apr 3 17:41:42 2020
D PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE D
1 1 TABLE OF CONTENTS 46 53 CAMERA: PMU 1: Power (1/2) D52_AP_MASTER_3.50.0 91 130 INTERPOSER: Symbol (1/2)
2 2 SYSTEM: BOM Tables D52_AP_MASTER_3.50.0 47 54 CAMERA: PMU 1: I/O (2/2) D52_AP_MASTER_3.50.0 92 131 INTERPOSER: Symbol (2/2)
3 3 CONSTRAINTS: Impedance Controlled 48 55 CAMERA: PMU 1: Aliases D52_AP_MASTER_3.50.0 93 132 INTERPOSER: Aliases (1/4)
4 4 CONSTRAINTS: Power 49 56 CAMERA: PMU 2: Power (1/2) D52_AP_MASTER_3.50.0 94 133 INTERPOSER: Aliases (2/4)
5 5 CONSTRAINTS: Misc. 50 57 CAMERA: PMU 2: I/O (2/2) D52_AP_MASTER_3.50.0 95 134 INTERPOSER: Aliases (3/4)
6 6 CONSTRAINTS: Stackup/Misc. (FF-Specific) 51 58 CAMERA: PMU 2: Aliases D52_AP_MASTER_3.50.0 96 135 INTERPOSER: Aliases (4/4)
7 7 SYSTEM: Bootstrapping D52_AP_MASTER_3.50.0 52 59 CAMERA: Discrete LDOs D52_AP_MASTER_3.50.0 97 139 INTERPOSER: Misc.
8 10 SOC: NAND + USB & Misc D52_AP_MASTER_3.50.0 53 64 CAMERA: Will D52_AP_MASTER_3.50.0 98 140 HIER: Arrow
9 11 SOC: PCIE D52_AP_MASTER_3.50.0 54 66 CAMERA: Will: Aliases D52_AP_MASTER_3.50.0 99 142 HIER: NFC
10 12 SOC: ISP D52_AP_MASTER_3.50.0 55 70 PEARL: VCSEL Driver D52_AP_MASTER_3.50.0 100 150 HIER: WiFi
11 13 SOC: Display D52_AP_MASTER_3.50.0 56 71 PEARL: Aliases D52_AP_MASTER_3.50.0 101 160 HIER: Radio
12 14 SOC: Serial D52_AP_MASTER_3.50.0 57 78 AUDIO: Codec: Analog (1/2) D52_AP_MASTER_3.50.0 102 1 FRONT PAGE
13 15 SOC: GPIO D52_AP_MASTER_3.50.0 58 79 AUDIO: Codec: Power & I/O (2/2) D52_AP_MASTER_3.50.0 103 2 MODULE
14 16 SOC: AOP & SMC & NUB D52_AP_MASTER_3.50.0 59 80 AUDIO: Bot Speaker Amp D52_AP_MASTER_3.50.0 104 3 FILTERS MATCHING
15 17 SOC: Ocelot D52_AP_MASTER_3.50.0 60 81 AUDIO: Top Speaker Amp D52_AP_MASTER_3.50.0 105 1 NFC: TABLE OF CONTENTS
16 18 SOC: Power (CPU/GPU & SRAM & SOC) D52_AP_MASTER_3.50.0 61 83 HAPTIC: Haptic Amp D52_AP_MASTER_3.50.0 106 74 NFC_P
17 19 SOC: Power (Fixed & 1V2) D52_AP_MASTER_3.50.0 62 84 HAPTIC: Sakonnet D52_AP_MASTER_3.50.0 107 75 NFC_P_FE
C 18 20 SOC: Power (DDR & AOP/AVE/ISP/USB) D52_AP_MASTER_3.50.0 63 89 TOP MODULE: Touch Power D52_AP_MASTER_3.50.0 108 76 NFC_F C
19 21 SOC: Power (GND) D52_AP_MASTER_3.50.0 64 91 TOP MODULE: Display Power D52_AP_MASTER_3.50.0 109 1 FRONT PAGE
20 23 SOC: Aliases: I2C AP/ISP D52_AP_MASTER_3.50.0 65 93 LIGHTNING: Lightning Controller D52_AP_MASTER_3.50.0 110 20 LB PAD 07/30/2019
21 24 SOC: Aliases: I2C AOP/SMC D52_AP_MASTER_3.50.0 66 94 LIGHTNING: USB-PD D52_AP_MASTER_3.50.0 111 22 UHB LAT PAD 07/30/2019
22 25 SOC: Aliases: GPIOs D52_AP_MASTER_3.50.0 67 95 LIGHTNING: Accessory Buck D52_AP_MASTER_3.50.0 112 23 LMB_2G_PAD 07/30/2019
23 26 SOC: Aliases: Misc D52_AP_MASTER_3.50.0 68 96 LIGHTNING: eUSB D52_AP_MASTER_3.50.0 113 36 LOWER ANTENNA FEEDS_ANT7 07/30/2019
24 27 SOC: Aliases: FF-Specific 69 97 LIGHTNING: Aliases D52_AP_MASTER_3.50.0 114 39 UPPER ANTENNA FEEDS_ANT4 07/30/2019
25 29 NAND D52_AP_MASTER_3.50.0 70 99 LVL SHIFT: Misc Nets D52_AP_MASTER_3.50.0 115 1 Table of Contents
26 31 NAND: Aliases D52_AP_MASTER_3.50.0 71 100 B2B: Battery 116 4 5G rFEM (UAT) D52_WIFI_MASTER_0.19.0
27 33 SYS PWR: PMU: Bucks (1/5) D52_AP_MASTER_3.50.0 72 101 B2B: Cyclone 117 7 2G4 rFEM (UAT) D52_WIFI_MASTER_0.19.0
28 34 SYS PWR: PMU: Bucks (2/5) D52_AP_MASTER_3.50.0 73 104 B2B: RCAM: Single-flex 118 8 2G4 rFEM (LAT) D52_WIFI_MASTER_0.19.0
29 35 SYS PWR: PMU: LDOs (3/5) D52_AP_MASTER_3.50.0 74 105 B2B: RCAM: Super-flex
30 36 SYS PWR: PMU: GPIO (4/5) D52_AP_MASTER_3.50.0 75 106 B2B: Jasper
31 37 SYS PWR: PMU: Misc (5/5) D52_AP_MASTER_3.50.0 76 107 B2B: FCAM
32
33
38
39
SYS PWR: PMU: Aliases: GPIO
SYS PWR: PMU: Aliases: Misc.
D52_AP_MASTER_3.50.0
D52_AP_MASTER_3.50.0
77
78
108
109
B2B: Pearl: Juliet
B2B: Pearl: Romeo
EEEE Codes TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

34 40 SYS PWR: Charger D52_AP_MASTER_3.50.0 79 110 B2B: Sensor TABLE_5_ITEM
B B
825-7691 1 EEEE FOR 639-08619 MRNT CRITICAL EEEE:08619
35 41 SYS PWR: VDD_MAIN Sense Resistor D52_AP_MASTER_3.50.0 80 111 B2B: Strobe TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10097 NY3J CRITICAL EEEE:10097

36 42 SYS PWR: Boost D52_AP_MASTER_3.50.0 81 112 B2B: Dock TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10099 NY47 CRITICAL EEEE:10099

37 43 SYS PWR: WiFi FEM Load Switches D52_AP_MASTER_3.50.0 82 115 B2B: Display TABLE_5_ITEM

38 44 SYS PWR: Wireless Charger D52_AP_MASTER_3.50.0 83 116 B2B: Touch 09/20/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10098 NY3W CRITICAL EEEE:10098

39 45 SYS PWR: Wireless Charger: Level Shifters D52_AP_MASTER_3.50.0 84 120 B2B: UAT1 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10100 NY4L CRITICAL EEEE:10100

40 46 SYS PWR: Wireless Charger: Boost D52_AP_MASTER_3.50.0 85 121 B2B: UAT2 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10101 NY4Y CRITICAL EEEE:10101

41 47 SYS PWR: Wireless Charger: Aliases D52_AP_MASTER_3.50.0 86 125 MECHANICAL: Standoffs, Fiducials, Etc. 10/17/2019 TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10103 NY5X CRITICAL EEEE:10103

42 48 SYS PWR: Aliases: FF Specific 87 126 TESTING: Test Points TABLE_5_ITEM

43 49 SYS PWR: NTCs (Top) D52_AP_MASTER_3.50.0 88 127 TESTING: Test Points (FF-Specific) TABLE_5_ITEM

44 50 SYS PWR: NTCs (Bottom) 89 128 TESTING: Probe Points TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10105 NY6M CRITICAL EEEE:10105

45 52 CAMERA: P/G Variant D52_AP_MASTER_3.50.0 90 129 TESTING: Probe Points (FF-Specific) TABLE_5_ITEM
825-7691 1 EEEE FOR 639-10108 NY7G CRITICAL EEEE:10108
APNs Sub-designs
TABLE_5_HEAD
Hierarchies
SOURCE PROJECT SUB-DESIGN NAME VERSION
HARD/
SYNC_DATE/TIME FORCE
Packaging Options
A
SOFT SUBDESIGN
A
TABLE_5_ITEM
051-05215 1 SCH,MLB_TOP,D53 SCH CRITICAL ?

TABLE_5_ITEM
D52 HIER_ARROW 0.42.0 S 2020_03_30_21:49:04 Y PACK_OPTIONS TO INCLUDE IN NETLIST TABLE OF CONTENTS
DRAWING TITLE
820-01955 1 PCB,MLB_TOP,D53 PCB CRITICAL ? D53
D53 HIER_NFC_TOP 0.29.0 S 2020_03_30_22:03:02 Y SCH,MLB,TOP,D53
D53 HIER_RADIO_MAV_TOP 1.26.0 S 2020_04_02_13:14:28 Y DRAWING NUMBER SIZE
051-05215 D
D53 HIER_WIFI_TOP 0.25.0 S 2020_03_30_21:47:34 Y Apple Inc. REVISION
4.6.0
Pages NOTICE OF PROPRIETARY PROPERTY: BRANCH
HARD/ THE INFORMATION CONTAINED HEREIN IS THE

SOURCE PROJECT SUB-DESIGN NAME SUB-DESIGN PAGES VERSION SOFT SYNC_DATE/TIME PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
D52 AP_MASTER 2,7,10-21,23-26,29,31,33-47,49,52-59,64,66,70-71,78-81,83-84,89,91,93-97,99 3.50.0 S 2020_04_02_13:16:58 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 1 OF 160
SHEET
IV ALL RIGHTS RESERVED 1 OF 118
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Multi-Vendor Criticals Capacitor Alternates Level Shifter Alternates

Capacitors 0.1uF, 01005 TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD
In descending order of value, then package size Capacitors (cont'd) PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT PART NUMBER CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT CRITICAL PART# COMMENT

TABLE_ALT_ITEM
132S0316 01005,0.1uF, 6.3V 311S00231 311S00232 ? ALL IC,74AVC2T45,XCVR,2 BIT,2 SPLY,X2SON8 311S00232 IC,74AVC2T45,XCVR,2 BIT,2 SPLY,X2SON8
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
132S00185 132S0316 ? ALL CAP,CER,X5R,0.1UF,20%,6.3V,01005
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S0979 131S00303 311S00230 311S00212 ? ALL 311S00212

CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM
TABLE_CRITICAL_ITEM
CAP,CER,NPO/COG,100PF,5%,16V,01005
TABLE_CRITICAL_ITEM
0.22uF, 01005
RefDes field intentionally left blank to allow selective single-sourcing
IC,74AVC1T45,XCVR,1 BIT,2 SPLY,X2SON6
TABLE_ALT_ITEM
IC,74AVC1T45,XCVR,1 BIT,2 SPLY,X2SON6
TABLE_CRITICAL_ITEM
138S0652 CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402 131S00323 CAP,CER,NPO/COG,56PF,5%,25V,01005 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

311S00261 311S00233 ? ALL IC,LSF0101,XCVR,2 BIT CFG,2 SPLY,X2SON6 311S00233 IC,LSF0101,XCVR,2 BIT CFG,2 SPLY,X2SON6
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
138S00070 CAP,X5R,4.7UF,20%,25V,0402 131S0643 CAP,CER,NP0/C0G,56PF,5%,25V,01005 PART NUMBER

TABLE_CRITICAL_ITEM
311S00235 IC,NVT0202,XCVR,2 BIT, 2 SPLY,BIDI,DFN8
D
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_ITEM
132S00014 01005,0.22uF, 6.3V
D
132S0663 CAP,CER,X5R,1UF,10%,25V,0402 131S0216 CAP,CER,NP0/C0G,47PF,5%,16V,01005 132S00233 132S00014 ? 01005,0.22uF,6.3V,Taiyo
138S0683 CAP,CER,X5R,1UF,10%,25V,0402
TABLE_CRITICAL_ITEM
131S0804 CAP,CER,27PF,5%,C0G,25V,0201
TABLE_CRITICAL_ITEM
132S00304 132S00014 ? 01005,0.22uF,6.3V,Kyocera

TABLE_ALT_ITEM
Power Inductor Alternates

0.47uF, 01005
138S0692 CAP,CER,X5R,1UF,20%,6.3V,0201 131S0223 CAP,CER,NP0/C0G,27PF,5%,16V,01005 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
138S00014 CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM 131S0215 CAP,CER,NP0/C0G,22PF,5%,16V,01005 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM
PART NUMBER
TABLE_ALT_ITEM
152S00876 Cyntec,IND
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
152S00721 152S00876 ? ALL Taiyo,IND,MLD,1UH,3.6A,60MO,2016

132S0304 CAP,CER,X5R,0.22UF,20%,6.3V,0201 131S0225 CAP,CER,NP0/C0G,15PF,5%,16V,01005 TABLE_ALT_ITEM
138S00128 01005,0.47uF, 6.3V TABLE_CRITICAL_ITEM
138S00133 138S00128 ? ALL 01005,0.47uF,6.3V,Murata

TABLE_ALT_ITEM
152S00897 Taiyo,IND
152S00930 152S00897 ? ALL Cyntec,IND,CPLD,0.1UH,6.1A,27MO,2016

132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402 131S0220 CAP,CER,NP0/C0G,12PF,5%,16V,01005 TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S00269 138S00128 ? ALL 01005,0.47uF,6.3V,Taiyo

TABLE_ALT_ITEM
152S00826 152S00821 ? ALL Taiyo,IND,MLD,1UH,2.2A,60MO,2012

132S0288 131S00353
CAP,CER,X5R,0.1UF,10%,16V,0201 CAP,CER,NPO/COG,10PF,5%,16V,01005
1uF, 0201
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
152S00831 152S00818 ? ALL Taiyo,IND,MLD,0.22UH,5.3A,40MO,1608

132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_CRITICAL_ITEM
Ferrites PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 152S00984 Cyntec.IND
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
PART NUMBER 152S00991 152S00984 ? ALL Taiyo,IND,MLD,0.47UH,3.5A,34MO,1614

132S0534 CAP,CER,X5R,0.1UF,10%,25V,0201 TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
TABLE_CRITICAL_HEAD TABLE_ALT_ITEM
138S0706 CAP,X5R,1UF,20%,10V,0201 TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT 138S0739 138S0706 ? ALL CAP,CER,X5R,1UF,20%,10V,0201,SAMSUNG 152S00992 152S00985 ? ALL Taiyo,IND,MLD,0.47UH,4.0A,45MO,2012
132S0664 CAP,CER,0.047UF,10%,25V,X5R,0201 TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005 138S0945 138S0706 ? ALL CAP,CER,X5R,1UF,20%,10V,0201,KYOCERA 152S00989 152S00982 ? ALL Taiyo,IND,MULT,0.47UH,2.8A,70MO,1608
132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005 TABLE_CRITICAL_ITEM
2.2uF, 0201
TABLE_CRITICAL_ITEM TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605 152S00824 152S00819 ? ALL Taiyo,IND,MLD,1UH,20%,2A,69MO,H=0.65,2012

132S00093 CAP,X5R,0.022UF,20%,6.3V,01005 RefDes field intentionally left blank to allow selective single-sourcing TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
152S00872 152S00918 ? ALL TDK,IND,MLD,0.47UH,5.6A,36MO,H=0.8,2016 Boost/Yeti (2117/0.8mm)

132S0245 CAP,CER,X5R,0.01UF,10%,6.3V,01005 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
TABLE_ALT_ITEM
Resistors 152S00847 152S00918 ? ALL

CYNTEC,IND,MLD,0.47UH,5.6A,26MO,H=0.8,2016
132S0396 CAP,CER,X5R,1000PF,10%,10V,01005 TABLE_ALT_ITEM
138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201
138S00049 138S0831 ? CAP,CER,X5R,2.2UF,20%,6.3V,0201
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM TABLE_CRITICAL_HEAD
152S01282 152S01255 ? ALL TAIYO,IND,MLD,0.47UH,5A,30MO,H=0.65,2117 Boost/Yeti (2117/0.65mm)

132S0296 CRITICAL PART# COMMENT
CAP,CER,X5R,1000PF,10%,6.3V,01005
3uF @ 1V, 0201
Misc. Alternates
132S0318 CAP,CER,X5R,820PF,10%,10V,01005 118S00068 RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER
132S0275 CAP,CER,X5R,470PF,10%,10V,01005 117S0055 RES,MF,1/20W,2M OHM,5,0201,SMD TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S00139 0201,3uF@1V
TABLE_CRITICAL_ITEM
138S00138 138S00139 ? ALL 0201,3uF@1V,KYOCERA

TABLE_ALT_HEAD
131S0883 CAP,CER,NP0/C0G,220PF,2%,50V,0201
Misc. PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_CRITICAL_HEAD
PART NUMBER CRITICAL PART# COMMENT
C C
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
138S00164 138S00139 ? ALL 0201,3uF@1V,TAIYO

131S00170 CAP,CER,C0G,220PF,5%,25V,01005 TABLE_CRITICAL_HEAD TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT

TABLE_ALT_ITEM
155S00437 155S00402 ? ALL FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201 155S00402 FERR BD,33OHM,25%,1.5A,55MOHM DCR,0201
TABLE_CRITICAL_ITEM
138S00280 138S00139 ? ALL 0201,3uF@1V,SAMSUNG

131S00053 CAP,CER,C0G,220PF,5%,10V,01005 TABLE_CRITICAL_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
377S0106 155S00194 155S00400 ALL 155S00400

132S0249 CAP,CER,X7R,220PF,10%,10V,01005
TABLE_CRITICAL_ITEM
SUPPR,TRANS,VARISTOR,12V,33PF,01005
TABLE_CRITICAL_ITEM
4uF, 0201
RefDes field intentionally left blank to allow selective single-sourcing
? FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005
TABLE_ALT_ITEM
FERR BD,150OHM,25%,200MA,0.7OHM DCR,01005
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005 TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
155S00414 155S0876 ? ALL FERR BD,10OHM,50%,1.1A,0.05OHM DCR,01005 155S0876 FERR BD,10OHM,50%,1.1A,0.05OHM DCR,01005
131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_ITEM
155S00131 155S0755 ? ALL FERR BD,240OHM,25%,200MA,1.0OHM DCR,01005 155S0755 FERR BD,240 OHM,25%,200MA,1.0 DCR,01005
138S00071 0201,X5R,4UF,0201,0.55MM,MURATA
2020 MLCCs
TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S00116 138S00071 ? CAP,X5R,4UF,0201,0.55MM,TAIYO 155S00583 155S00140 ? ALL FERR BD,33OHM,25%,400MA,0.20DCR,01005 155S00140 FERR BD,33OHM,25%,400MA,0.20DCR,01005
TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S00117 138S00071 ? 377S00070 377S00001 ALL 377S00001

16uF, 0402, 4V CAP,X5R,4UF,0201,0.55MM,KYOCERA ? TVS,BIDIR,5.8V,6PF,01005 TVS,BIDIR,5.8V,6PF,01005
4.7uF, 0402
TABLE_ALT_HEAD
377S00140 377S00001 ? ALL TVS,BIDIR,5V,6PF,01005 377S00129 SUPRESS,TRANS,6.8V,100PF,01005

PART NUMBER Primary: Murata TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 377S0168 377S00129 ? ALL SUPPRESS,TRANS,6.8V,100PF,AMOTECH,01005 107S0244 THERMISTOR,NTC,100K OHM,1%,B=4250,01005
PART NUMBER
TABLE_ALT_ITEM
138S00316 138S00313 ? ALL CAP,X5R,16UF,20%,4V,M,0402 Taiyo TABLE_CRITICAL_ITEM TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S0719 0402,4.7uF,10V 107S0245 107S0244 ? ALL THERMISTOR,NTC,100K OHM,1%,B=4250,01005

TABLE_ALT_ITEM
138S1103 138S0719 ? ALL CAP,CER,X5R,4.7UF,20%,10V,0402

138S00314 138S00313 ? ALL CAP,X5R,16UF,20%,4V,M,0402 Kyocera
15uF, 0402
ZRB Cap ALTs
TABLE_ALT_ITEM
138S00315 138S00313 ? ALL CAP,X5R,16UF,20%,4V,M,0402 Samsung All RefDes in ( ) are single-sourced from Murata
11uF, 0402, 4V
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER
TABLE_ALT_HEAD TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM
138S00003 0402,15uF,6.3V PART NUMBER

PART NUMBER Primary: Murata 138S00048 138S00003 ? 0402,15uF,6.3V, Kyocera
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
138S00175 CAP,X5R,4.7UF,20%,25V,0402
TABLE_ALT_ITEM
(C1805,C3321,C1872,C3371,C3382) 138S00240 138S00187 ? ALL CAP,X5R,4.7UF,20%,25V,0402

138S00318 138S00317 ALL Kyocera
?
18uF, 0402
TABLE_CRITICAL_ITEM
CAP,X5R,11UF,20%,4V,M,0402-3T
TABLE_ALT_ITEM
138S00185 CAP,X5R,2.2UF,20%,25V,0402
TABLE_ALT_ITEM
138S00246 138S00185 ? ALL CAP,X5R,2.2UF,20%,25V,0402

138S00319 138S00317 ? ALL CAP,X5R,11UF,20%,4V,M,0402-3T Samsung TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER
TABLE_ALT_ITEM
138S00320 138S00317 ? ALL Taiyo

0-ohm, 0201, 4.5A
TABLE_CRITICAL_ITEM
CAP,X5R,11UF,20%,4V,M,0402-3T
TABLE_ALT_ITEM
138S00146 CAP,CER,X5R,18UF,20%,6.3V,MUR,0402
138S00221 138S00146 ALL
2.7uF, 0201, 6.3V ? CAP,CER,X5R,18UF,20%,6.3V,MUR,0402
20uF, 0402
B B
TABLE_ALT_HEAD TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: All parts are single-sourced except for approved parts (listed below) PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER Primary: Murata TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
117S00012 RES,MF,0 OHM,1/10W,4.5A,0201

138S00326 138S00325 ? ALL CAP,X5R,2.7UF,20%,6.3V,M,0201 Kyocera PART NUMBER
TABLE_CRITICAL_ITEM
117S00040 117S00012 ? ALL RES,MF,0 OHM,1/10W,4.5A,0201
TABLE_ALT_ITEM TABLE_ALT_ITEM
138S0884 CAP,CER,X5R,20UF,20%,6.3V,0402,H=0.7MM
138S00327 138S00325 ? ALL CAP,X5R,2.7UF,20%,6.3V,M,0201 Samsung 138S00339 138S0884 ? Taiyo
2.7uF, 0201, 4V
TABLE_ALT_ITEM
138S00338 138S0884 ? Kyocera

TABLE_ALT_HEAD
C3302,C3312,C3333,C3350,C3364,C1893,C3412,C3423,C3525,C3535,C3403,C1807,C1866,C1874,C2030
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: C3302,C3312,C3333,C3350,C3364,C1893,C3412,C3423,C3525,C3535,C3403,C1807,C1866,C1874,C2030
PART NUMBER Primary: Murata
138S00324 138S00321 ? ALL CAP,X5R,2.7UF,20%,4V,M,0201

TABLE_ALT_ITEM
Taiyo
22uF, 0402
TABLE_ALT_ITEM
138S00322 138S00321 ? ALL CAP,X5R,2.7UF,20%,4V,M,0201 Kyocera PART NUMBER

TABLE_CRITICAL_ITEM
138S00279 CAP,X5R,26UF,20%,4V,MURATA,0402
138S00323 138S00321 ? ALL CAP,X5R,2.7UF,20%,4V,M,0201 Samsung 138S00144 138S00279 ? ALL CAP,X5R,26UF,20%,4V,MURATA,0402
TABLE_ALT_ITEM
138S00143 138S00279 ? ALL

MAV20 PDN Single-source
CAP,X5R,22UF,20%,4V,KYOCERA,0402
10uF @ 1V, 4-Term

0.22uF, 01005
All RefDes in ( ) are single-sourced from Murata PART NUMBER
TABLE_CRITICAL_ITEM
TABLE_ALT_HEAD TABLE_ALT_ITEM
138S00149 0402-3T,10.5uF@1V
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 138S00148 138S00149 ? ALL 0402-3T,10.5uF@1V, Kyocera
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S00150 138S00149 ? ALL 0402-3T,10.5uF@1V, SEMCO

132S00233 132S00014 ? [SEE BELOW] 01005,0.22uF,6.3V,Taiyo
TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S00151 138S00149 ? ALL 0402-3T,10.5uF@1V, TY

132S00304 132S00014 ? [SEE BELOW] 01005,0.22uF,6.3V,Kyocera
(C705_E-C720_E,C723_E-C725_E,C727_E,C730_E,C731_E,C734_E,C736_E-C742_E,C744_E,C749_E-C751_E,C754_E-C760_E,C766_E,C767_E,C770_E-C772_E,C774_E-C776_E,C778_E-C786_E) 22uF, 0402 3T (WiFi)

2.2uF, 0201
All RefDes in ( ) are single-sourced from Murata
(C705_E-C720_E,C723_E-C725_E,C727_E,C730_E,C731_E,C734_E,C736_E-C742_E,C744_E,C749_E-C751_E,C754_E-C760_E,C766_E,C767_E,C770_E-C772_E,C774_E-C776_E,C778_E-C786_E)

TABLE_ALT_HEAD
CRITICAL PART# COMMENT

TABLE_CRITICAL_HEAD
PART NUMBER
A
TABLE_ALT_HEAD TABLE_CRITICAL_ITEM
A
TABLE_ALT_ITEM
138S0986 CAP,CER,3-TERM,7.5UF,20%,4V,0402
PART NUMBER 138S00024 138S0986 ? ALL CAP,CER,3-TERM,7.5UF,20%,4V,0402
TABLE_ALT_ITEM
PAGE TITLE
138S00049 138S0831 ? [SEE BELOW]
SYSTEM: BOM Tables

CAP,CER,X5R,2.2UF,20%,6.3V,0201
Display Choke Alternates

(C701_E,C702_E,C704_E,C721_E,C722_E,C726_E,C728_E,C729_E,C732_E,C733_E,C735_E,C743_E,C745_E,C746_E,C747_E,C748_E,C752_E,C768_E,C769_E,C773_E,C777_E,C789_E)
4uF, 0201 DRAWING NUMBER
051-05215
SIZE
D
Apple Inc.
All RefDes in ( ) are single-sourced from Murata
REVISION
TABLE_ALT_HEAD TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM
4.6.0
155S00524 FLTR,NOISE,35 OHMZ,3 OHM,7GHZ,50MA,0403 NOTICE OF PROPRIETARY PROPERTY: BRANCH

138S00116 138S00071 ? [SEE BELOW] CAP,X5R,4UF,0201,0.55MM,TAIYO 155S00415 155S00524 ? ALL FLTR,NOISE,35 OHMZ,3 OHM,7GHZ,50MA,0403
PROPRIETARY PROPERTY OF APPLE INC.
TABLE_ALT_ITEM
138S00117 138S00071 ? [SEE BELOW] CAP,X5R,4UF,0201,0.55MM,KYOCERA THE POSESSOR AGREES TO THE FOLLOWING: PAGE
(C511_E-C518_E,C522_E,C524_E-C526_E,C702_E,C764_E,C768_E-C769_E,C777_E,C787_E,C788_E,C1135_E-C1142_E,C1226_E,C1227_E,C5801_E-C5803_E,C5823_E,C5827_E,C5828_E)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 2 OF 160
(C511_E-C518_E,C522_E,C524_E-C526_E,C702_E,C764_E,C768_E-C769_E,C777_E,C787_E,C788_E,C1135_E-C1142_E,C1226_E,C1227_E,C5801_E-C5803_E,C5823_E,C5827_E,C5828_E) II NOT TO REPRODUCE OR COPY IT
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Spacing CSet Definitions
DIELECTRIC BASED SPACING RULES
RULE DEFINITION LIST OF VALUES
EXAMPLE: 1,3-5,7L,8L-10L
A_DIELECTRIC_(N)X
Calculates dielectric distance from stackup,
shortest distance is used unless 'L'is defined
1.5,2,2.5,3,4
EXAMPLE: 2,1DL,3D-5D,7V,8VL-10VL
PLEASE USE HYBRID TABLE

A_DIELECTRIC_(N)XD XV,XVL,X
Calculates dielectric distance from Hybrid Table and
stackup, shortest distance is used unless 'L' defined
?
EXAMPLE: 2_4,3L_5L
A_DIELECTRIC_(N)XIN_(N)XOUT
Calculates dielectric distance from stackup,
shortest distance is used unless 'L' is defined
?
90-ohm
Electrical
Diff Pair Constraints
D CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
D
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
LPDP E_LPDP_WIDE E DIFF_PAIR DP:DP_90_LPDP*_WIDE* Y

E_LPDP_SUPERFLEX-CAM2 E DIFF_PAIR DP:DP_90_LPDP*_SUPERFLEX_CAM2* Y
E_LPDP_SINGLEFLEX_CAM E DIFF_PAIR DP:DP_90_LPDP*_SINGLEFLEX_CAM* Y
E_LPDP_FCAM E DIFF_PAIR DP:DP_90_LPDP*_FCAM* Y
E_LPDP_JASPER E DIFF_PAIR DP:DP_90_LPDP*_JASPER* Y
MIPI E_MIPI_DISPLAY E DIFF_PAIR_MIPI-D DP:DP_90_MIPI*DISPLAY* N
E_MIPI_IRCAM E DIFF_PAIR_MIPI-C DP:DP_90_MIPI*_IRCAM* N
PCIE E_PCIE_NAND E DIFF_PAIR DP:DP_90_PCIE*_NAND* Y
E_PCIE_WLAN E DIFF_PAIR DP:DP_90_PCIE*_WLAN* Y
E_PCIE_BB E DIFF_PAIR DP:DP_90_PCIE*_BB* Y
USB E_KRAKEN_DP E DIFF_PAIR DP:DP_90_KRAKEN* Y
E_MIKEYBUS_DP E DIFF_PAIR DP:DP_90_MIKEYBUS* Y
E_USB_DP E DIFF_PAIR DP:DP_90_USB* Y
E_EUSB_DP E DIFF_PAIR DP:DP_90_EUSB* Y
Physical
CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
DOMAIN
LPDP 90_LPDP_WIDE P A_90_OHM_DIFF DP:DP_90_LPDP*_WIDE* Y

90_LPDP_SUPERFLEX_CAM2 P A_90_OHM_DIFF DP:DP_90_LPDP*_SUPERFLEX_CAM2* Y
90_LPDP_SINGLEFLEX_CAM P A_90_OHM_DIFF DP:DP_90_LPDP*_SINGLEFLEX_CAM* Y
90_LPDP_FCAM P A_90_OHM_DIFF DP:DP_90_LPDP*_FCAM* Y
90_LPDP_JASPER P A_90_OHM_DIFF DP:DP_90_LPDP*_JASPER* Y
MIPI-D 90_MIPI_DISPLAY P A_90_OHM_DIFF DP:DP_90_MIPI*DISPLAY* Y
DP:DP_90_MIPI*_IRCAM*
C C
MIPI-C 90_MIPI_IRCAM P A_90_OHM_DIFF Y
PCIE (Gen4) 90_PCIE_NAND P A_90_OHM_DIFF DP:DP_90_PCIE*_NAND* Y
90_PCIE_BB P A_90_OHM_DIFF DP:DP_90_PCIE*_BB* Y
PCIE (Gen2) 90_PCIE_WLAN P A_90_OHM_DIFF DP:DP_90_PCIE*_WLAN* Y
USB 90_KRAKEN_DP P A_90_OHM_DIFF DP:DP_90_KRAKEN* Y
90_USB_DP P A_90_OHM_DIFF DP:DP_90_USB* Y
90_EUSB_DP P A_90_OHM_DIFF DP:DP_90_EUSB* Y
MIKEYBUS 90_MIKEYBUS_DP P A_90_OHM_DIFF DP:DP_90_MIKEYBUS* Y
Spacing
OVERRIDE
DOMAIN
LPDP 90_LPDP_WIDE S A_DIELECTRIC_3X = Y

90_LPDP_SUPERFLEX_CAM2 S A_DIELECTRIC_3X = Y
90_LPDP_SINGLEFLEX_CAM S A_DIELECTRIC_3X = Y
90_LPDP_FCAM S A_DIELECTRIC_3X = Y
90_LPDP_JASPER S A_DIELECTRIC_3X = Y
MIPI-D 90_MIPI_DISPLAY S A_DIELECTRIC_3X = Y
MIPI-C 90_MIPI_IRCAM S A_DIELECTRIC_2X = Y
PCIE (Gen4) 90_PCIE_NAND S A_DIELECTRIC_3X = Y
90_PCIE_BB S A_DIELECTRIC_3X = Y
PCIE (Gen2) 90_PCIE_WLAN S A_DIELECTRIC_3X = Y
USB 90_KRAKEN_DP S A_DIELECTRIC_3X = Y
90_USB_DP S A_DIELECTRIC_3X = Y
90_EUSB_DP S A_DIELECTRIC_3X = Y
MIKEYBUS 90_MIKEYBUS_DP S A_DIELECTRIC_2X = Y
Class-Class Spacing
B CLASS TO CLASS SPACING
B
CLASS NAME CLASS NAME CONSTRAINT SET
LPDP <-> LPDP 90_LPDP_WIDE 90_LPDP_WIDE A_DIELECTRIC_2X
90_LPDP_WIDE 90_LPDP_SUPERFLEX_CAM2 A_DIELECTRIC_2X
90_LPDP_WIDE 90_LPDP_SINGLEFLEX_CAM A_DIELECTRIC_2X
90_LPDP_WIDE 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_WIDE 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_SUPERFLEX_CAM2 90_LPDP_SUPERFLEX_CAM2 A_DIELECTRIC_2X
90_LPDP_SUPERFLEX_CAM2 90_LPDP_SINGLEFLEX_CAM A_DIELECTRIC_2X
90_LPDP_SUPERFLEX_CAM2 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_SUPERFLEX_CAM2 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_SINGLEFLEX_CAM 90_LPDP_SINGLEFLEX_CAM A_DIELECTRIC_2X
90_LPDP_SINGLEFLEX_CAM 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_SINGLEFLEX_CAM 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_FCAM 90_LPDP_FCAM A_DIELECTRIC_2X
90_LPDP_FCAM 90_LPDP_JASPER A_DIELECTRIC_2X
90_LPDP_JASPER 90_LPDP_JASPER A_DIELECTRIC_2X
MIPI-D 90_MIPI_DISPLAY 90_MIPI_DISPLAY A_DIELECTRIC_2X
PCIE (Gen2) 90_PCIE_WLAN 90_PCIE_WLAN A_DIELECTRIC_2X
USB 90_KRAKEN_DP 90_KRAKEN_DP A_DIELECTRIC_2X
90_KRAKEN_DP 90_USB_DP A_DIELECTRIC_2X
90_KRAKEN_DP 90_EUSB_DP A_DIELECTRIC_2X
90_USB_DP 90_USB_DP A_DIELECTRIC_2X
90_USB_DP 90_EUSB_DP A_DIELECTRIC_2X
90_EUSB_DP 90_EUSB_DP A_DIELECTRIC_2X
A A
PAGE TITLE
CONSTRAINTS: Impedance Controlled

DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Constraints Physical (continued)
Physical CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
DOMAIN
OVERRIDE
CLASS NAME
DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N Arc PWR_50UM P PWR_50UM PP1V2_ARCAMP_VD_FILT_INTERNAL Y
LX/CX Nodes PWR_SHAPE_LX P PWR_SHAPE LX*, !LX_DPMIC* Y PWR_50UM P PWR_50UM PP1V8_ARCAMP_VA_VL_INTERNAL Y
PWR_SHAPE_LX_GALENA P PWR_SHAPE LX_DPMIC* Y PWR_SHAPE P PWR_SHAPE PP_ARCAMP_VBOOST Y
PWR_SHAPE_LX P PWR_SHAPE CX* Y PWR_SHAPE P PWR_SHAPE ARCAMP_TO_SOLENOID_OUT* Y
System-Wide PWR_SHAPE P PWR_SHAPE PP_VDD_MAIN Y PWR_80UM P PWR_80UM AGND_ARCAMP Y
PWR_SHAPE P PWR_SHAPE PP_VDD_BOOST* Y Touch (DITO) PWR_100UM P PWR_100UM PP5V5_TOUCH_BOOST Y
PWR_50UM P PWR_50UM PP3V0_S2 Y PWR_100UM P PWR_100UM PP5V1_TOUCH_VDDH* Y
D
PWR_SHAPE P PWR_SHAPE PP1V8_IO Y PWR_80UM P PWR_80UM PP1V8_IO_TOUCH_EEPROM_CONN Y
D PWR_SHAPE P PWR_SHAPE PP1V8_S2
PP1V8_S4
Y Touch (Both) PWR_200UM P PWR_200UM PP1V8_TOUCH_S2*
PP7V3_DISPLAY_AVDDH*
Y
PWR_SHAPE P PWR_SHAPE Y Display PMIC PWR_SHAPE P PWR_SHAPE Y
PWR_200UM P PWR_200UM PP1V2_IO Y PWR_SHAPE P PWR_SHAPE PP4V6_DISPLAY_VDDEL* Y
PWR_200UM P PWR_200UM PP1V2_S2 Y PWR_SHAPE P PWR_SHAPE PNVAR_DISPLAY_VSSEL* Y
PWR_100UM P PWR_100UM PP1V2_S4 Y Kraken PWR_SHAPE P PWR_SHAPE PP_ACC_VAR Y
SoC:CPU/GPU PWR_SHAPE P PWR_SHAPE PP_CPU_PCORE Y PWR_80UM P PWR_80UM PP_VAR_USB_RVP Y
PWR_SHAPE P PWR_SHAPE PP_CPU_ECORE PWR_200UM P PWR_200UM PP_KRAKEN_ACC1* Y
Y
PWR_SHAPE P PWR_SHAPE PP_GPU Y PWR_SHAPE P PWR_SHAPE PP_KRAKEN_ACC2* Y
SoC:SRAM/SOC PWR_SHAPE P PWR_SHAPE PP_CPU_SRAM Y PWR_80UM P PWR_80UM ANALOG_VDD_MAIN_OV_R Y
PWR_SHAPE P PWR_SHAPE PP_SRAM_S1 Y Parrot PWR_80UM P PWR_80UM PP3V3_USB_S2 Y
PWR_SHAPE P PWR_SHAPE PP_SOC_S1 Y AF/OIS (Shared) PWR_SHAPE P PWR_SHAPE PPVAR_RCAM_PVDD Y
SoC:Fixed PWR_SHAPE P PWR_SHAPE PP0V78_SOC_FIXED_S1 Y Wide RCAM PWR_100UM P PWR_100UM PPVAR_WIDE_PVDD_CONN Y
PWR_80UM P PWR_80UM PP0V78_VDD_FIXED_XTAL Y PWR_80UM P PWR_80UM PP1V8_WIDE_SINGLEFLEX_CAM_VDDIO* Y
PWR_80UM P PWR_80UM PP0V78_SOC_FIXED_PCIE_REFBUF PWR_100UM P PWR_100UM PP2V85_WIDE_AVDD1* Y
Y
SoC:VDD12 PWR_80UM P PWR_80UM PP1V2_S1 Y PWR_200UM P PWR_200UM PPVAR_WIDE_AVDD2 Y
PWR_80UM P PWR_80UM PP1V2_S1_XTAL Y PWR_100UM P PWR_100UM PP1V1_WIDE_DVDD Y
PWR_200UM P PWR_200UM PP1V2_SOC Superflex-Cam2 PWR_100UM P PWR_100UM PP2V85_SUPERFLEX_CAM2_AVDD1* Y
Y
PWR_80UM P PWR_80UM PP1V2_SOC_FILT Y PWR_200UM P PWR_200UM PPVAR_SUPERFLEX_CAM2_AVDD2 Y
PWR_80UM P PWR_80UM PP1V2_VDD12_FMON PWR_100UM P PWR_100UM PP1V2_SUPERFLEX_CAM2_DVDD Y
Y
PWR_80UM P PWR_80UM PP1V2_VDD12_ULPPLL_S2 Y PWR_80UM P PWR_80UM PP1V8_SUPERFLEX_CAM2_VDDIO_CONN Y
PWR_80UM P PWR_80UM PP1V2_IO_GRP* Singleflex-Cam PWR_100UM P PWR_100UM PPVAR_SINGLEFLEX_CAM_PVDD_CONN Y
Y
SoC:DDR PWR_SHAPE P PWR_SHAPE PP_DCS_S1 Y PWR_80UM P PWR_80UM PP1V8_SINGLEFLEX_CAM_VDDIO_CONN,PP1V8_WIDE_VDDIO_CONN Y
PWR_200UM P PWR_200UM PP0V6_VDDQL_S1 Y PWR_100UM P PWR_100UM PP2V85_SINGLEFLEX_CAM_AVDD1 Y
PWR_SHAPE P PWR_SHAPE PP1V06_S2 Y PWR_200UM P PWR_200UM PPVAR_SINGLEFLEX_CAM_AVDD2 Y
SoC:Misc. PWR_SHAPE P PWR_SHAPE PP0V7_VDD_LOW_S2 PWR_100UM P PWR_100UM PP1V2_SINGLEFLEX_CAM_DVDD Y
Y
PWR_80UM P PWR_80UM PP0V7_VDD_LOW_*LPPLL Y FCAM PWR_80UM P PWR_80UM PP1V8_FCAM_IO_CONN Y
C PWR_SHAPE
PWR_SHAPE
P
P
PWR_SHAPE
PWR_SHAPE
PP_AVE_S1
PP_DISP_S1
Y
Y
PWR_200UM
PWR_200UM
P
P
PWR_200UM
PWR_200UM
PP2V85_FCAM_AVDD*
PP1V1_FCAM_DVDD
Y
Y
C
PWR_200UM P PWR_200UM PP0V6_VDDIO06_GRP1_* Y Juliet IRCAM PWR_80UM P PWR_80UM PP1V8_IRCAM_VDDIO_CONN Y
NAND PWR_100UM P PWR_100UM PP_NAND_VDDIO1_R Y PWR_80UM P PWR_80UM PP2V85_IRCAM_AVDD* Y
PWR_300UM P PWR_300UM PP_NAND_VDDIO1_F Y PWR_80UM P PWR_80UM PP1V2_IRCAM_DVDD Y
PWR_SHAPE P PWR_SHAPE PP0V83_NAND Y Jasper PWR_80UM P PWR_80UM PP1V8_JASPER_VDDIO_CONN Y
PWR_100UM P PWR_100UM PP0V83_NAND_PLL Y PWR_80UM P PWR_80UM PP3V0_JASPER_RX_AVDD* Y
PWR_SHAPE P PWR_SHAPE PP2V625_NAND Y PWR_80UM P PWR_80UM PP3V3_JASPER_TX_AVDD* Y
PMU PWR_SHAPE P PWR_SHAPE PP1V5_VLDOINT Y PWR_SHAPE P PWR_SHAPE PP1V1_JASPER_DVDD* Y
PWR_SHAPE P PWR_SHAPE PP0V9_S1 Y ALS PWR_80UM P PWR_80UM PP1V8_ALS_S2 Y
Yangtze PWR_SHAPE P PWR_SHAPE PP_VBUS1_E75 Y Compass PWR_80UM P PWR_80UM PP1V8_COMPASS_S2_CONN Y
PWR_SHAPE P PWR_SHAPE PP_VBUS2_DOTARA Y Penrose PWR_80UM P PWR_80UM PP3V0_PENROSE_SINGLEFLEX_CAM_SVDD, PP3V0_PENROSE_SVDD_CONN Y
PWR_SHAPE P PWR_SHAPE PP_CHARGER_PMID Y Dock PWR_80UM P PWR_80UM PP1V8_DOCK_S2_CONN Y
PWR_SHAPE P PWR_SHAPE PP_BATT_VCC_YANGTZE Y PWR_200UM P PWR_200UM PPVAR_EIGER_S2* Y
PWR_100UM P PWR_100UM CHARGER_BOOT* Y PWR_80UM P PWR_80UM PP1V2_EIGER_S2_CONN Y
PWR_SHAPE P PWR_SHAPE PP6V0_CHARGER_LDO_INTERNAL Y Display PWR_80UM P PWR_80UM PP1V2_DISPLAY_S2_CONN Y
PWR_80UM P PWR_80UM PP1V8_ALWAYS Y PWR_80UM P PWR_80UM PP1V8_DISPLAY_DVDD_CONN Y
Dotara PWR_SHAPE P PWR_SHAPE PAC_DOTARA_COIL1 Y PWR_SHAPE P PWR_SHAPE PP1VX_DISPLAY_S2* Y
PWR_SHAPE P PWR_SHAPE PAC_DOTARA_AC2 Y PWR_80UM P PWR_80UM PP3V0_DISPLAY_S2* Y
PWR_SHAPE P PWR_SHAPE DOTARA_TX_BANK_2 Y NFC/Ironman NFC PWR_80UM P PWR_80UM PP1V2_NFC_S2 Y
PWR_SHAPE P PWR_SHAPE PAC_DOTARA_COIL2 Y PWR_SHAPE P PWR_SHAPE PP_NFC_*_VDDBOOST Y
PWR_100UM P PWR_100UM DOTARA_COMM* Y PWR_100UM P PWR_100UM PP_NFC_*_VDDC Y
PWR_200UM P PWR_200UM DOTARA_CLAMP* Y PWR_100UM P PWR_100UM PP_NFC_*_MIX, PP_NFC_*_VCASCHI, PP_NFC_*_VCASLO Y
PWR_200UM P PWR_200UM DOTARA_BOOT* Y PWR_100UM P PWR_100UM PP_NFC_*_VDDNV Y
PWR_SHAPE P PWR_SHAPE PP_DOTARA_VMID Y PWR_100UM P PWR_100UM PP_NFC_*_TVDD Y
PWR_SHAPE P PWR_SHAPE PP_DOTARA_VRECT Y PWR_100UM P PWR_100UM PP_NFC_*_VDDPLL Y
B B
PWR_200UM P PWR_200UM PP1V8_DOTARA_LDO Y PWR_100UM P PWR_100UM PP_NFC_*_VHV Y
PWR_100UM P PWR_100UM PP5V0_VDD_DOTARA Y PWR_100UM P PWR_100UM PP_NFC_*_VREF Y
PWR_100UM P PWR_100UM PP5V0_DOTARA_VMID Y PWR_100UM P PWR_100UM PP_NFC_*_AVDD Y
PWR_DEFAULT P PWR_DEFAULT PP1V2_DOTARA_S2 Y PWR_SHAPE P PWR_SHAPE PP_NFC_*_VUP Y
Camera PMUs PWR_SHAPE P PWR_SHAPE PP1V3_CAM_PMU*_BUCK0 Y PWR_100UM P PWR_100UM PP_NFC_*_TXVCASC* Y
PWR_100UM P PWR_100UM PP_VDD_MAX_CAM_PMU* Y PWR_NFC_ANT P PWR_NFC_ANT NFC_*_ANT_POS, NFC_*_ANT_NEG, NFC_*_ANT_MATCH_* Y
PWR_100UM P PWR_100UM PP_VDD_RTC_CAM_PMU* Y PWR_NFC_ANT P PWR_NFC_ANT NFC_*_TXP, NFC_*_TXN, NFC_*_BAL*, NFC_*_PROBE_* Y
PWR_SHAPE P PWR_SHAPE PP1V8_CAM_PMU1_IO_SW Y PWR_80UM P PWR_80UM PP_SIMVCC1 Y
PWR_SHAPE P PWR_SHAPE PP1V8_CAM_PMU2_IO_SW Y Arrow PWR_SHAPE P PWR_SHAPE PP1V0_S4 Y
PWR_SHAPE P PWR_SHAPE PP1V2_INT_CAM_PMU* Y PWR_SHAPE P PWR_SHAPE PP1V0_R1_ANA_S4 Y
Will/Jasper PWR_100UM P PWR_100UM PP3V0_WILL_VDD Y QETs/APTs PWR_300UM P PWR_300UM PP_QET* Y
PWR_100UM P PWR_100UM PP1V8_CAM_PMU2_IO_SW Y PWR_SHAPE P PWR_SHAPE PP_APT* Y
PWR_100UM_HV P PWR_100UM PN_JASPER_VDDHV* Y Misc. Radio PWR_100UM P PWR_100UM PP_VDD_RF_1V2 Y
PWR_100UM P PWR_100UM PP_JASPER_VDDLAS* Y PWR_100UM P PWR_100UM PP_LDO6_VIO_1V8* Y
Rigel/Pearl PWR_SHAPE P PWR_SHAPE PP_VANA Y PWR_100UM P PWR_100UM PP_RFFE1_VIO_XCVR_1V8_R Y
PWR_SHAPE P PWR_SHAPE PP_RIGEL_VINCORE Y PWR_100UM P PWR_100UM UAT_SUBUS_*, UAT_SAWTOOTH_* Y
PWR_SHAPE P PWR_SHAPE PP_RIGEL_BUCK_BOOST_A Y GND P DEFAULT GND Y
PWR_SHAPE P PWR_SHAPE PP_RIGEL_BUCK_BOOST_B Y Spacing
PWR_SHAPE P PWR_SHAPE PP_ROMEO_CATHODE Y CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
PWR_SHAPE P PWR_SHAPE PP_ROMEO_DENSE_ANODE Y CLASS NAME

DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
PWR_SHAPE P PWR_SHAPE PP_ROMEO_SPARSE_ANODE Y GND S MSAP_YIELD GND Y

PWR_SHAPE P PWR_SHAPE PP_ROMEO_A_ANODE Y PWR_DEFAULT S DEFAULT = Y
PWR_SHAPE P PWR_SHAPE PP_ROMEO_B_ANODE Y PWR_50UM S DEFAULT = Y
PWR_SHAPE P PWR_SHAPE PP_BANE_ANODE Y PWR_80UM S DEFAULT = Y
PWR_100UM P PWR_100UM PP3V3_MAMABEAR_VDD Y PWR_100UM S DEFAULT = Y
Audio PWR_50UM P PWR_50UM PP1V8_AUDIO_VA_S2 Y PWR_200UM S DEFAULT = Y
A Mic Bias PWR_MIC

PWR_MIC
P
P
PWR_DEFAULT
PWR_DEFAULT
PP_CODEC_TO_MIC*_BIAS*
RET_CODEC_FROM_MIC*
Y
Y
PWR_300UM
PWR_SHAPE
S
S
DEFAULT
DEFAULT
=
=
Y
Y
A
PAGE TITLE
Codec PWR_200UM P PWR_200UM AGND_CODEC Y PWR_100UM_HV S HV_SPACING = Y
BotSpk PWR_50UM P PWR_50UM PP_VA_BOT_SPK_INTERNAL Y PWR_MIC S DEFAULT = Y CONSTRAINTS: Power
PWR_SHAPE P PWR_SHAPE PP_SPKRAMP_BOT_VBOOST Y PWR_NFC_ANT S DEFAULT = Y DRAWING NUMBER SIZE
SPKRAMP_BOT_TO_COIL_OUT_* = 051-05215 D
PWR_SHAPE
PWR_80UM
P
P
PWR_SHAPE
PWR_80UM AGND_BOT_SPK
Y
Y
PWR_SHAPE_LX
PWR_SHAPE_LX_GALENA
S
S
LX_SPACING
LX_SPACING =
Y
Y
Apple Inc. REVISION
TopSpk PWR_50UM P PWR_50UM PP_VA_TOP_SPK_INTERNAL Y 4.6.0

PWR_SHAPE P PWR_SHAPE PP_SPKRAMP_TOP_VBOOST Y NOTICE OF PROPRIETARY PROPERTY: BRANCH
PWR_SHAPE P PWR_SHAPE SPKRAMP_TOP_TO_COIL_OUT_* THE INFORMATION CONTAINED HEREIN IS THE
Class-Class on next page

Y PROPRIETARY PROPERTY OF APPLE INC.
PWR_80UM P PWR_80UM AGND_TOP_SPK Y THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Diff Pair
Electrical
Constraints Clocks
Physical
DOMAIN
OVERRIDE
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N DOMAIN
OVERRIDE
E_DP_GENERIC E GENERIC_DP DP:DP_CODEC_AOUT* Y
CLK P DEFAULT CLK_* Y
E_DP_GENERIC E GENERIC_DP DP:DP_MIC* Y
CLK_SPMI P DEFAULT SPMI*CLK* Y
E_DP_GENERIC E GENERIC_DP DP:DP_PENROSE* Y
CLK_I2S P DEFAULT I2S*MCLK*, I2S*BCLK* Y
E_DP_NTC E DIFF_PAIR_NTC DP:DP_NTC_* Y
CLK_SPI P DEFAULT SPI*SCLK* Y
E_DP_GENERIC E GENERIC_DP DP:DP_*MTR* Y
E_DP_GENERIC E GENERIC_DP DP:DP_ANALOG*SENSE* Y Spacing
E_DP_GENERIC E GENERIC_DP DP:DP_ANALOG_VIN_SAKONNET_FROM_HALL Y CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
D
DOMAIN
E_DP_GENERIC E GENERIC_DP DP:DP_PMU_VDD_MAIN_SENSE* Y CLASS NAME CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
D
E,P,S
E_DP_NC E GENERIC_DP DP:DP_NC* Y CLK S A_DIELECTRIC_1.5X = Y

CLK_SPMI S A_DIELECTRIC_1.5X = Y
Physical CLK_I2S S A_DIELECTRIC_1.5X = Y
OVERRIDE
CLK_SPI S A_DIELECTRIC_1.5X = Y
DOMAIN
CLASS NAME CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
Class-Class Spacing
E,P,S
DP_PWR P PWR_DP DP:DP_CODEC_AOUT* Y

DP_MIC P GENERIC_DP DP:DP_*MIC* Y CLASS TO CLASS SPACING
DP_PENROSE P GENERIC_DP DP:DP_PENROSE* Y CLASS NAME CLASS NAME CONSTRAINT SET
DP_NTC P GENERIC_DP DP:DP_NTC_* Y CLK GND DEFAULT
DP_GENERIC P GENERIC_DP DP:DP_*MTR* Y CLK_SPMI GND DEFAULT
DP_GENERIC P GENERIC_DP DP:DP_ANALOG*SENSE* Y CLK_I2S GND DEFAULT
DP_SAKONNET P GENERIC_DP DP:DP_ANALOG_VIN_SAKONNET_FROM_HALL Y CLK_SPI GND DEFAULT
DP_GENERIC P GENERIC_DP DP:DP_PMU_VDD_MAIN_SENSE* Y
Spacing
DP_NC P GENERIC_DP DP:DP_NC* Y
Grouping Constraints Used to clean up CM
Physical
DOMAIN
OVERRIDE
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N DOMAIN
OVERRIDE
DP_PWR S DEFAULT = Y
GRP_GPIO P DEFAULT GPIO*, IO_* Y
DP_MIC S A_DIELECTRIC_1.5X = Y
GRP_NC P DEFAULT NC_* Y
DP_PENROSE S A_DIELECTRIC_1.5X = Y
GRP_I2C P DEFAULT I2C* Y
DP_NTC S A_DIELECTRIC_1.5X = Y
GRP_I2S P DEFAULT I2S*LRCLK*, I2S*DOUT*, I2S*DIN* Y
DP_GENERIC S DEFAULT = Y
GRP_SPI P DEFAULT SPI*MOSI*, SPI*MISO*, SPI*CS* Y
DP_SAKONNET S DEFAULT = Y
GRP_UART P DEFAULT UART* Y
DP_NC S DEFAULT = Y
GRP_SWD P DEFAULT SWD* Y
Class-Class Spacing C
C
GRP_SPMI_DATA P DEFAULT SPMI*DATA* Y
GRP_PCIE_SIDE P DEFAULT PCIE*CLKREQ*, PCIE*PERST* Y
CLASS TO CLASS SPACING
GRP_LPDP_AUX P DEFAULT LPDP*AUX* Y
CLASS NAME CLASS NAME CONSTRAINT SET CODEC_*FILTP, CODEC_*FILTN
GRP_CODEC_FILT P PWR_200UM Y
DP_MIC GND DEFAULT
RFFE P DEFAULT SHIELD_RFFE* Y
DP_MIC PWR_MIC DEFAULT
DP_MIC DP_SAKONNET DEFAULT
Spacing
Sensitive
Physical
Analog CLASS DEFINITIONS
DOMAIN
COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
GRP_GPIO S DEFAULT = Y
OVERRIDE
CLASS NAME
DOMAIN
E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N GRP_NC S DEFAULT = Y
ANALOG_SAKONNET_BIAS P DEFAULT ANALOG_BIAS_SAKONNET*, ANALOG_RET_SAKONNET* Y GRP_I2C S DEFAULT = Y
ANALOG P DEFAULT ANALOG*DOTARA* Y GRP_I2S S DEFAULT = Y
ANALOG P DEFAULT ANALOG*DOMBRA* Y GRP_SPI S DEFAULT = Y
ANALOG P DEFAULT ANALOG*SENSE,ANALOG*SENSE_SE,ANALOG*SENSE_FILT Y GRP_UART S DEFAULT = Y
ANALOG P DEFAULT ANALOG_DDR*ZQ* Y GRP_SWD S DEFAULT = Y
ANALOG_NAND_ZQ P PWR_100UM ANALOG_NAND*ZQ* Y GRP_SPMI_DATA S DEFAULT = Y
ANALOG P DEFAULT ANALOG*REXT* Y GRP_PCIE_SIDE S DEFAULT = Y
ANALOG P DEFAULT ANALOG*CAL* Y GRP_LPDP_AUX S DEFAULT = Y
ANALOG P DEFAULT ANALOG_*REF* Y GRP_CODEC_FILT S DEFAULT = Y
ANALOG P DEFAULT ANALOG_FB* Y RFFE S A_DIELECTRIC_1.5X = Y
ANALOG P DEFAULT ANALOG_KRAKEN_BYPASS,ANALOG_KRAKEN_BI_CCG2B_CC Y
ANALOG P DEFAULT ANALOG_RIGEL_LSCP Y Class-Class Spacing
ANALOG_AMP_FILT P PWR_80UM ANALOG_*_SPK_FILT,ANALOG_ARCAMP_FILT Y CLASS TO CLASS SPACING
ANALOG_VSS_PMU_XTAL P DEFAULT VSS_PMU_XTAL Y CLASS NAME CLASS NAME CONSTRAINT SET
ANALOG_AMUX P DEFAULT AMUX* Y RFFE 50_TX0_THIN A_DIELECTRIC_3X
B ANALOG_NTC P DEFAULT NTC_NFC_UAT*_POS Y RFFE 50_TX1_THIN A_DIELECTRIC_3X B
ANALOG_NTC P DEFAULT NTC_PEARL_VCSEL_TO_RIGEL Y RFFE 50_TX2_THIN A_DIELECTRIC_3X
ANALOG_NTC P DEFAULT NTC_STROBE_MODULE* Y RFFE 50_RX_THIN A_DIELECTRIC_3X
ANALOG_SPKR_SENSE P DEFAULT COIL_TO_SPKRAMP_*_VSENSE_*, SOLENOID_TO_ARC_VSENSE_* Y RFFE RFFE DEFAULT
RFFE GND DEFAULT
Spacing
OVERRIDE
DOMAIN
ANALOG S A_DIELECTRIC_1.5X = Y
ANALOG_SAKONNET_BIAS S A_DIELECTRIC_1.5X = Y
ANALOG_AMP_FILT S A_DIELECTRIC_1.5X = Y
ANALOG_VSS_PMU_XTAL S A_DIELECTRIC_1.5X =
Power (cont'd from prev. page)

Y
ANALOG_AMUX S A_DIELECTRIC_1.5X = Y
ANALOG_NTC S A_DIELECTRIC_1.5X = Y
ANALOG_SPKR_SENSE S A_DIELECTRIC_1.5X = Y Class-Class Spacing
ANALOG_NAND_ZQ S A_DIELECTRIC_1.5X = Y CLASS TO CLASS SPACING CLASS TO CLASS SPACING
CLASS NAME CLASS NAME CONSTRAINT SET CLASS NAME CLASS NAME CONSTRAINT SET
Class-Class Spacing PWR_100UM GND MSAP_YIELD_PWR PWR_SHAPE_LX ANALOG_AMUX A_DIELECTRIC_3X
CLASS TO CLASS SPACING PWR_100UM PWR_100UM 100UM-249UM_SPACING PWR_SHAPE_LX ANALOG_SPKR_SENSE A_DIELECTRIC_3X
CLASS NAME CLASS NAME CONSTRAINT SET PWR_100UM PWR_200UM 100UM-249UM_SPACING PWR_SHAPE_LX CLK A_DIELECTRIC_3X
ANALOG GND DEFAULT PWR_100UM PWR_300UM 100UM-249UM_SPACING PWR_SHAPE_LX CLK_SPMI A_DIELECTRIC_3X
ANALOG_SAKONNET_BIAS GND DEFAULT PWR_100UM PWR_SHAPE 100UM-249UM_SPACING PWR_SHAPE_LX CLK_I2S A_DIELECTRIC_3X
ANALOG_AMP_FILT GND DEFAULT PWR_200UM GND MSAP_YIELD_PWR PWR_SHAPE_LX CLK_SPI A_DIELECTRIC_3X
ANALOG_VSS_PMU_XTAL GND DEFAULT PWR_200UM PWR_200UM 100UM-249UM_SPACING PWR_SHAPE_LX_GALENA GND A_DIELECTRIC_3X
ANALOG_AMUX GND DEFAULT PWR_200UM PWR_300UM 100UM-249UM_SPACING PWR_100UM_HV GND DEFAULT
A ANALOG_NTC
ANALOG_SPKR_SENSE
GND
GND
DEFAULT
DEFAULT
PWR_200UM
PWR_300UM
PWR_SHAPE
GND
100UM-249UM_SPACING
MSAP_YIELD_PWR
A
PAGE TITLE
ANALOG_SAKONNET_BIAS ANALOG_SAKONNET_BIAS DEFAULT PWR_300UM PWR_300UM 250UM+_SPACING
ANALOG_SAKONNET_BIAS DP_SAKONNET DEFAULT PWR_300UM PWR_SHAPE 250UM+_SPACING CONSTRAINTS: Misc.
DRAWING NUMBER SIZE
ANALOG_NAND_ZQ GND DEFAULT PWR_SHAPE GND MSAP_YIELD_PWR
051-05215 D
PWR_SHAPE
PWR_SHAPE_LX
PWR_SHAPE
GND
250UM+_SPACING
DEFAULT
Apple Inc. REVISION
PWR_SHAPE_LX PWR_SHAPE_LX DEFAULT 4.6.0

PWR_SHAPE_LX ANALOG A_DIELECTRIC_3X NOTICE OF PROPRIETARY PROPERTY: BRANCH

PWR_SHAPE_LX ANALOG_SAKONNET_BIAS A_DIELECTRIC_3X PROPRIETARY PROPERTY OF APPLE INC.
PWR_SHAPE_LX ANALOG_AMP_FILT A_DIELECTRIC_3X
PWR_SHAPE_LX ANALOG_VSS_PMU_XTAL A_DIELECTRIC_3X
SHEET
PWR_SHAPE_LX ANALOG_NTC A_DIELECTRIC_3X III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Hybrid RF CSets
50-Thin 50-Wide 50-ohm (Wide) Constraints
TRACE
HYBRID IMPEDANCE RULE
REFERENCE REQUIRED TRACE WIDTH TRACE
HYBRID IMPEDANCE RULE
REFERENCE REQUIRED TRACE WIDTH
Physical
LAYER LAYER(s) IMPEDANCE (OPTIONAL) LAYER LAYER(s) IMPEDANCE (OPTIONAL)
OVERRIDE
DOMAIN
RF SPACING VALUES= 2 RF SPACING VALUES= 2 CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
RULE NAME= 50_THIN ZONE NAME= PRIMARY RULE NAME= 50_WIDE ZONE NAME= PRIMARY Cellular 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT2_LB_LMB_MB_HB_L1 Y
ISL3 ISL2,ISL4 50 ISL3 TOP,ISL5 50
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT4_MB_HB_WLAN24_M Y
D
ISL6 ISL7,ISL5 50 ISL6 ISL8,ISL4 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT7_UHB_N79 Y
D ISL8 ISL9,ISL7 50 ISL7 ISL9,ISL5 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT7_UHB_N79_M Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_ANT8* Y
ISL9 BOTTOM,ISL8 50 BOTTOM ISL8 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_CPLR_U_* Y
BOTTOM ISL9 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_LB_PAD_* Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_LB_PORTB_TX_M Y
50-Wide w/ Thin on L1/L10 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_LB_PORTB_RX1_M Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_PAUHBL_UHB_ANT1_* Y
HYBRID IMPEDANCE RULE 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_PAUHBL_UHB_ANT2_* Y
TRACE REFERENCE REQUIRED TRACE WIDTH
LAYER LAYER(s) IMPEDANCE (OPTIONAL)
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_PAUHBL_N79_ANT2_TO_ANT9 Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_PAUHBU_N79_* Y
RF SPACING VALUES= 2
50_WIDE_SURFACE_THIN 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_PAUHBU_UHB_* Y
RULE NAME= ZONE NAME= PRIMARY
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_UHB_PAD_PORTB_* Y
ISL3 TOP,ISL5 50 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_UHB_PAD_N79_* Y
ISL6 ISL8,ISL4 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_IN_LMB_PAD_LMB_ANT Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_IN_LMB_PAD_LMB_ANT_M Y
ISL7 ISL9,ISL5 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_IN_LMB_PAD_2G_MB_* Y
BOTTOM ISL9 50 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_IN_LMB_PAD_2G_LB_OUT Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_IN_LMB_PAD_2G_LB_OUT_M Y
WiFi 50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_WLAN_G_BT_ANT3_NPLXR Y
P A_50_WIDE_SURFACE_THIN_SE 50_WLAN_G_BT_LAT
50-ohm (Thin) Constraints
50_TRX_WIDE_SURFACE_THIN Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_WLAN_G_BT_ANT4* Y
Physical Arrow 50_TRX_WIDE P A_50_WIDE_SE 50_TRX_R1_AOA2, 50_TRX_R1_AOA3 Y
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_R1_ANT2_CH5 Y
DOMAIN
OVERRIDE
50_TRX_WIDE P A_50_WIDE_SE 50_TRX_R1_AOA1, 50_TRX_R1_ANT2_CH9 Y
50_TRX_WIDE P A_50_WIDE_SE 50_R1_ANT* Y
Cellular 50_TX0_THIN P A_50_THIN_SE 50_TX_IN_*TX0_* Y
50_TRX_WIDE P A_50_WIDE_SE 50_UWB_ANT0 Y
C C
50_TX1_THIN P A_50_THIN_SE 50_TX_IN_*TX1_* Y
50_TX2_THIN P A_50_THIN_SE 50_TX_IN_*TX2_* Y
50_TRX_WIDE P A_50_WIDE_SE 50_UWB_ANT2_6G Y
50_RX_THIN P A_50_THIN_SE 50_RX_* Y
50_TRX_WIDE P A_50_WIDE_SE 50_UWB_ANT2_6G_FL_IN Y
50_RX_THIN P A_50_THIN_SE 50_LAA_RX_* Y
50_TRX_WIDE P A_50_WIDE_SE 50_UWB_ANT2_8G Y
50_RX_THIN P A_50_THIN_SE 50_RX_LMB_PAD_LMB_PRX_OUT_M Y
50_TRX_WIDE P A_50_WIDE_SE 50_UWB_ANT2_8G_FL_* Y
50_RX_THIN P A_50_THIN_SE 50_RX_LMB_PAD_LMB_PRX_OUT Y
50_TRX_THIN P A_50_THIN_SE 50_UHB_L_CPLR_OUT Y
50_TRX_WIDE P A_50_WIDE_SE 50_R1_WLAN_A_LAA_ANT6 Y
WiFi 50_TRX_THIN P A_50_THIN_SE 50_TRX_WLAN_A_C0* Y
50_TRX_WIDE P A_50_WIDE_SE 50_R1_WLAN_A_LAA_DPLXR* Y
50_TRX_THIN P A_50_THIN_SE 50_WLAN_A_UAT* Y
50_TRX_WIDE P A_50_WIDE_SE 50_R1_WLAN_A_LAA_M Y
50_TRX_THIN P A_50_THIN_SE 50_TRX_WLAN_G_C0* Y
50_TRX_WIDE_SURFACE_THIN P A_50_WIDE_SURFACE_THIN_SE 50_TRX_PAUHBL_N79_ANT1_TO_ANT7_M Y
50_TRX_THIN P A_50_THIN_SE 50_WLAN_G_UAT_TXRX_FEM Y
50_TRX_THIN P A_50_THIN_SE 50_TRX_WLAN_G_C1* Y Spacing
50_TRX_THIN P A_50_THIN_SE 50_WLAN_G_LAT_TXRX_FEM Y CLASS DEFINITIONS COMMA SEPARATED WITH WILDCARD SUPPORT: NET NAMES EX: DDR* CLEAR
OVERRIDE
DOMAIN
50_TRX_THIN P A_50_THIN_SE 50_TRX_LB_PORTB_RX1, 50_TRX_LB_PORTB_TX_ANT2 Y CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N
50_TRX_THIN P A_50_THIN_SE 50_TRX_PAUHBL_N79_ANT1_TO_ANT7 Y 50_TRX_WIDE S NA_DIELECTRIC_2XDS_50_WIDE_SE = Y

50_TRX_THIN P A_50_THIN_SE 50_TRX_ANT4_MB_HB_WLAN24 Y 50_TRX_WIDE_SURFACE_THIN S NA_DIELECTRIC_2XDS_50_WIDE_SURFACE_THIN_SE = Y
50_TRX_THIN P A_50_THIN_SE 50_UWB_ANT2_6G_FL_OUT Y
50_TRX_THIN P A_50_THIN_SE 50_UWB_ANT2_6G_T_MATCHING Y Class-Class Spacing
CLASS NAME CLASS NAME CONSTRAINT SET
Spacing GND 50_TRX_WIDE GND NA_DIELECTRIC_2X_50_WIDE_SE
50_TRX_WIDE_SURFACE_THIN GND NA_DIELECTRIC_2X_50_WIDE_SURFACE_THIN_SE
OVERRIDE
DOMAIN
CLASS NAME E,P,S CONSTRAINT SET DP NAMES EX: DP:DP_AA*,DP_BB* (LINE STARTS WITH FLAG DP:) Y/N Wide-Wide 50_TRX_WIDE 50_TRX_WIDE NA_DIELECTRIC_4XD_50_WIDE_SE
Everything 50_TX_IN_THIN S NA_DIELECTRIC_2XDS_50_THIN_SE = Y 50_TRX_WIDE_SURFACE_THIN 50_TRX_WIDE NA_DIELECTRIC_4XD_50_WIDE_SURFACE_THIN_SE
50_TX0_THIN S NA_DIELECTRIC_2XDS_50_THIN_SE = Y 50_TRX_WIDE_SURFACE_THIN 50_TRX_WIDE_SURFACE_THIN NA_DIELECTRIC_4XD_50_WIDE_SURFACE_THIN_SE
50_TX1_THIN S NA_DIELECTRIC_2XDS_50_THIN_SE = Y
50_TX2_THIN S NA_DIELECTRIC_2XDS_50_THIN_SE = Y
B 50_RX_THIN S NA_DIELECTRIC_2XDS_50_THIN_SE = Y B
50_TRX_THIN S NA_DIELECTRIC_2XDS_50_THIN_SE = Y
Class-Class Spacing
CLASS NAME
CLASS NAME CONSTRAINT SET Pin Delay Check
Same Class 50_TX0_THIN 50_TX0_THIN NA_DIELECTRIC_2X_50_THIN_SE
PIN DELAY MAPPING FILE
50_TX1_THIN 50_TX1_THIN NA_DIELECTRIC_2X_50_THIN_SE
REFERENCE DESIGNATOR PIN DELAY CSV FILE NAME
50_TX2_THIN 50_TX2_THIN NA_DIELECTRIC_2X_50_THIN_SE
U1000 SicilyPinDelay.csv
50_RX_THIN 50_RX_THIN NA_DIELECTRIC_2X_50_THIN_SE
J10800 D53-JulietPinDelay.csv
50_TRX_THIN 50_TRX_THIN NA_DIELECTRIC_2X_50_THIN_SE *Location: /physical/rule/pindelays
GND 50_TX0_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_TX1_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_TX2_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_RX_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
50_TRX_THIN GND NA_DIELECTRIC_2X_50_THIN_SE
Thin-Thin 50_TX0_THIN 50_TX1_THIN NA_DIELECTRIC_4XD_50_THIN_SE
50_TX0_THIN 50_TX2_THIN NA_DIELECTRIC_4XD_50_THIN_SE
50_TX0_THIN 50_RX_THIN NA_DIELECTRIC_4XD_50_THIN_SE
50_TX0_THIN 50_TRX_THIN NA_DIELECTRIC_4XD_50_THIN_SE
50_TX1_THIN 50_TX2_THIN NA_DIELECTRIC_4XD_50_THIN_SE
50_RX_THIN 50_TRX_THIN NA_DIELECTRIC_4XD_50_THIN_SE
A Thin-Wide 50_TX0_THIN
50_TX1_THIN
50_TRX_WIDE
50_TRX_WIDE
NA_DIELECTRIC_4XD_50_THIN_SE
A
PAGE TITLE
50_TX2_THIN 50_TRX_WIDE NA_DIELECTRIC_4XD_50_THIN_SE
50_RX_THIN 50_TRX_WIDE NA_DIELECTRIC_4XD_50_THIN_SE CONSTRAINTS: Stackup/Misc. (FF-Specific)
DRAWING NUMBER SIZE
50_TRX_THIN 50_TRX_WIDE NA_DIELECTRIC_4XD_50_THIN_SE
051-05215 D
50_TX0_THIN
50_TX1_THIN
50_TRX_WIDE_SURFACE_THIN
50_TRX_WIDE_SURFACE_THIN
Apple Inc. REVISION
50_TX2_THIN 50_TRX_WIDE_SURFACE_THIN NA_DIELECTRIC_4XD_50_THIN_SE 4.6.0

50_RX_THIN 50_TRX_WIDE_SURFACE_THIN NA_DIELECTRIC_4XD_50_THIN_SE NOTICE OF PROPRIETARY PROPERTY: BRANCH

50_TRX_THIN 50_TRX_WIDE_SURFACE_THIN NA_DIELECTRIC_4XD_50_THIN_SE PROPRIETARY PROPERTY OF APPLE INC.
6 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOTSTRAPPING
BOARD REV + BOARD ID + BOOT CONFIG
D D
R0723
GPIO_BOARD_REV3 1
1.00K 2 OMIT_TABLE PP1V2_IO
22 OUT 20 33
5%
1/32W
MF
01005
ROOM=SOC
Board Rev [3:0]
R0722 * Float = 0 | PU = 1
GPIO_BOARD_REV2 1
1.00K 2 OMIT_TABLE
22 OUT Note: iBoot uses the inverse of BOARD_REV[3:0], so that it counts up (Pre-Proto = 0x0, PVT = 0xF)
5% TABLE_5_HEAD
1/32W BOARD_REV[3:0] [3] [2] [1] [0] PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
MF
01005 TABLE_5_ITEM
ROOM=SOC Pre-Proto 4'b1111 1 1 1 1 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722,R0721,R0720 BOARD_REV:PROTO0 PROTO0

R0721 Proto 1 4'b1110 1 1 1 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722,R0721 BOARD_REV:PROTO1
TABLE_5_ITEM
PROTO1
GPIO_BOARD_REV1 1
1.00K 2 OMIT_TABLE
22 OUT
TABLE_5_ITEM
5%
Proto 1.5 4'b1101 1 1 0 1 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722,R0720 BOARD_REV:PROTO1.5 PROTO1.5
1/32W TABLE_5_ITEM
MF Proto 2 4'b1100 1 1 0 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0722 BOARD_REV:PROTO2 PROTO2

C
01005
ROOM=SOC
Proto 2.5 4'b1011 1 0 1 1 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0721,R0720 BOARD_REV:PROTO2.5
TABLE_5_ITEM
PROTO2.5 C
R0720 TABLE_5_ITEM
GPIO_BOARD_REV0 1
1.00K 2 OMIT_TABLE Pre-EVT 4'b1010 1 0 1 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0721 BOARD_REV:PRE-EVT PRE-EVT
22 OUT TABLE_5_ITEM
5%
1/32W
EVT 4'b1001 1 0 0 1 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723,R0720 BOARD_REV:EVT EVT
MF TABLE_5_ITEM
01005
ROOM=SOC Carrier 4'b1000 1 0 0 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0723 BOARD_REV:CRB CRB
TABLE_5_ITEM
(Allocate more as necessary in descending order) 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0720 BOARD_REV:DVT DVT
DVT 4'b0001 0 0 0 1 (PVT NOSTUFF ALL)
PVT 4'b0000 0 0 0 0
8 OUT
NC_GPIO_BOARD_ID4 NC_GPIO_BOARD_ID4
MAKE_BASE=TRUE
NO_TEST=1
XW0711 Board ID [4:0]

SHORT-20L-0.05MM-SM * Float = 0 | PU = 1
8 OUT GPIO_BOARD_ID3 GPIO_BOARD_ID3 2 1 TABLE_5_HEAD
MAKE_BASE=TRUE BOARD_ID[4:0] [4] Unused [3] 1=MAV20 [2] [1] [0] 0=MLB, 1=DEV PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
OMIT
ROOM=SOC TABLE_5_ITEM
MLB D52G 5'b01010 0 1 0 1 0 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0712 BOARD_ID:D52 D52 = 01

TABLE_5_ITEM
DEV D52G 5'b01011 0 1 0 1 1 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0713 BOARD_ID:D53G D53G = 10

R0713 TABLE_5_ITEM
GPIO_BOARD_ID2 GPIO_BOARD_ID2 1
1.00K 2 OMIT_TABLE 117S0156 1 RES,MF,1K OHM,5%,1/32W,01005 R0713,R0712 BOARD_ID:D53P D53P = 11
90 8 OUT MLB D53G 5'b01100 0 1 1 0 0
MAKE_BASE=TRUE
D54 = 00
B
5%
B
(D54 both NOSTUFF)
1/32W DEV D53G 5'b01101 0 1 1 0 1
MF
01005
ROOM=SOC
MLB D53P 5'b01110 0 1 1 1 0
R0712
1.00K 2 OMIT_TABLE DEV D53P 5'b01111 0 1 1 1 1
90 8 OUT
MAKE_BASE=TRUE
5%
1/32W MLB D54P 5'b01000 0 1 0 0 0
MF
01005
ROOM=SOC DEV D54P 5'b01001 0 1 0 0 1
8 OUT
MAKE_BASE=TRUE
Boot Config [2:0]

* Float = 0 | PU = 1
USAGE SPEED TEST [2] [1] [0]
SPI1 NOR -- 12MHz -- 0 0 0

25 23
89 OUT
SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2 No Connect
SPI1 NOR -- 12MHz Test 0 0 1
SPI0 NAND POR 12MHz -- 0 1 0 <-- POR

SPI0 NAND Proto 12MHz Test 0 1 1 <-- Proto Builds
R0701
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1 1
4.7K 2
SPI1 NOR -- 24MHz -- 1 0 0
25 23 OUT
1% SPI1 NOR -- 24MHz Test 1 0 1
A A
1/32W
MF
01005 SPI1 NOR -- 6MHz -- 1 1 0
ROOM=NAND PAGE TITLE
R0700
SPI1 NOR -- 6MHz Test 1 1 1
SYSTEM: Bootstrapping
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 1
4.7K 2
NOSTUFF DRAWING NUMBER SIZE
<--- Remove at EVT
25 23 OUT
051-05215 D
1%
1/32W Apple Inc. REVISION
MF
01005
ROOM=NAND
4.6.0

7 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC 24M XTAL Alternates

4GB DRAM
TABLE_ALT_HEAD

PART NUMBER
TABLE_5_HEAD

TABLE_ALT_ITEM
TABLE_5_ITEM
197S0612 197S00118 ? Y1000 XTAL, 24M, 1612
998-19672 1 Sicily,A0,4GB,M U1000 CRITICAL BOARD_ID:D52&BOARD_ID:D53G

TABLE_ALT_ITEM
197S00120 197S00118 ? Y1000 XTAL, 24M, 1612

TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
998-19673 998-19672 BOARD_ID:D52&BOARD_ID:D53G U1000 Sicily,A0,4GB,H
D 998-19674 998-19672 BOARD_ID:D52&BOARD_ID:D53G U1000 Sicily,A0,4GB,S

TABLE_ALT_ITEM
D
6GB DRAM
TABLE_5_HEAD

TABLE_5_ITEM
998-19675 1 Sicily,A0,6GB,M U1000 CRITICAL BOARD_ID:D53P&BOARD_ID:D54
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
998-19676 998-19675 BOARD_ID:D53P&BOARD_ID:D54 U1000 Sicily,A0,6GB,H

TABLE_ALT_ITEM
998-19677 998-19675 U1000 Sicily,A0,6GB,S
SOC: Misc
BOARD_ID:D53P&BOARD_ID:D54
998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 1 OF 21
OMIT_TABLE
7 IN
GPIO_BOARD_ID0 CN11 BOARD_ID0 THROTTLE_TRIGGER0 BJ61 NC_DEV_SOC_THROTTLE_TRIGGER0 23
90 7 IN
GPIO_BOARD_ID1 CM15 BOARD_ID1 THROTTLE_TRIGGER1 BJ60 IO_AP_FROM_PMU_SW_SHDN_L IN 23
GPIO_BOARD_ID2 CP9 BOARD ID
BG62 THROTTLE_TRIGGER[0:4]:
90 7 IN BOARD_ID2 THROTTLE_TRIGGER2 IO_AP_FROM_PMU_PRE_UVLO_L IN 23
GPIO_BOARD_ID3 CJ62 BG61 These need an internal pull-up enabled on SoC
7 IN BOARD_ID3 THROTTLE_TRIGGER3 NC_DEV_SOC_THROTTLE_TRIGGER3 23
7 IN
NC_GPIO_BOARD_ID4 CP11 BOARD_ID4 THROTTLE_TRIGGER4 BE62 NC_DEV_SOC_THROTTLE_TRIGGER4 23
REQUEST_DFUx: Legacy button detection BK61

PP1V2_IO REQUEST_DFU1 THROTTLERS
C
23
BE61 IO_SOC_TO_PMU_SOCHOT_RESET_L
C MLB: Hard tie to PP1V2_IO
DEV: Wire to PMU BUTTONO
23 PP1V2_IO BJ62 REQUEST_DFU2
SOCHOT1
CP15 SWD_AP_TO_MANY_SWCLK
OUT 23 89
IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU AN60 DFU SWD_TCK_OUT1 OUT 25 95 98

87 23 IN FORCE_DFU
89 IO_SOC_DFU_STATUS BK62 DFU_STATUS SWD_TMS2 CN15 SWD_AP_BI_NAND_SWDIO 25 89
OUT BI
SWD_TMS3 CP13 SWD_AP_BI_BB_SWDIO Clocked by SWD_TCK_OUT1
NC_DEV_AP_TMR32_PWM0 AG3 FPWM0 BI 93
23
SWD_TMS4 CK62 SWD_AP_BI_R1_SWDIO
PP (dev board only) 23 NC_DEV_AP_TMR32_PWM1 AG2 FPWM1 BI 98
FPWM MISC
NC_DEV_AP_TMR32_PWM2 AJ3 FPWM2 TST_CLKOUT BE60 CLK_AP_TO_PMU_TST_CLKOUT
23 OUT 23 89
PP0V6_VDDQL_S1
ANALOGMUX_OUT CN3 AMUX_SOC_TO_PMU_AMUX_OUT 33
89 TEST_PAD_MTR_ANALOG_P CB60 PAD_MTR_ANALOG_TEST_P OUT 23

OUT
89 OUT
TEST_PAD_MTR_ANALOG_N CB61 PAD_MTR_ANALOG_TEST_N CFSB CL7
F5
IO_PMU_TO_SOC_KRAKEN_ACTIVE_READY IN 33
1
R1010 1
R1011 1
R1012 1
R1013 1
R1014 1
R1015
CFSB_XTAL IO_AON_TO_AP_XTAL_CFSB IN 23 240 240 240 240 240 240
1% 1% 1% 1% 1% 1%
AG60 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
MTR HOLD_RESET GND 23 MF MF MF MF MF MF
AF62 01005 2 01005 01005 01005 01005 01005
CD60 TESTMODE GND 2ROOM=SOC ROOM=SOC 2ROOM=SOC 2ROOM=SOC 2ROOM=SOC 2ROOM=SOC
23 NC_DEV_PAD_MTR_VREF_P PAD_MTR_VREF_P
23
PP (dev board only) CD61 CJ3

23 NC_DEV_PAD_MTR_VREF_N PAD_MTR_VREF_N DDR0_RREF ANALOG_DDR0_RREF
DDR0_ZQ BM2 ANALOG_DDR0_ZQ
DDR1_RREF BV60 ANALOG_DDR1_RREF
DDR2_RREF K3 ANALOG_DDR2_RREF
DDR DDR3_RREF Y61 ANALOG_DDR3_RREF
DDR3_ZQ AB62 ANALOG_DDR3_ZQ
LP4_IN_RESET* V60 IO_PMU_TO_SYSTEM_RESET_L 23
IN
XI0 E9 CLK_AP_XTAL_24M_IN
XTAL XO0 D9 CLK_AP_XTAL_24M_OUT 197S00118
CRITICAL
ROOM=SOC_XTAL
Y1000
R1021 1.60X1.20MM-SM
B 1
499 2 CLK_AP_XTAL_24M_OUT_R
24MHZ-30PPM-9.5PF-60OHM
3 1
B
1% NC GND
1/32W
1 C1020 C1021 1
4
2
MF
01005
ROOM=SOC_XTAL
12PF 12PF
5% 5%
2 16V
NP0-C0G
16V
NP0-C0G 2
01005-1
ROOM=SOC_XTAL
01005-1
ROOM=SOC_XTAL
SOC_XTAL_GND
SOC: NAND + USB 2

XW1000
SHORT-20L-0.05MM-SM
OMIT
NO_XNET_CONNECTION
998-19672
U1000
ROOM=SOC_XTAL
ROOM=SOC
SICILY-4GB-1YNM-M
CSP
SYM 2 OF 21
R1001 OMIT_TABLE
CLK_AP_TO_NAND_24M 2
33.2 1 CLK_AP_TO_NAND_24M_R AR2 A28 90_EUSB_PARROT_BI_AP_P
25 OUT NAND_SYS_CLK USB_EDP BI 68 89
1% USB_EDM B28 90_EUSB_PARROT_BI_AP_N

1/32W 89 25 OUT
IO_AP_TO_NAND_RESET_L AJ62 SSD_RESET* NAND - IOS USB
BI 68 89
MF
01005 89 25 OUT
IO_AP_TO_NAND_FW_STRAP AL60 SSD_BFH USB_RESREF D28 ANALOG_SOC_USB_RESREF
ROOM=SOC
EUSB_VBUS_DETECT AG61 PP1V2_IO IN 23

1
R1002
200
1%
1/32W
MF
01005
SYNCING: D52, D53, D54
2ROOM=SOC
A A
PAGE TITLE
SOC: NAND + USB & Misc

DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

10 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: PCIe 33 9 PP1V2_IO
D 998-19672 1
R1100 D
ROOM=SOC U1000 5%
47.0K
SICILY-4GB-1YNM-M 1/32W
CSP MF
01005
2 ROOM=SOC
SYM 3 OF 21
OMIT_TABLE
TMLR67A0-C1
23 NC_DEV_PCIE_GP0_AP_CLKREQ_L CB3 GP_PCIE_CLKREQ0* ST_PCIE_CLKREQ0* CB2 PCIE_ST0_AP_BI_NAND_CLKREQ_L 25
BI
NC_DEV_PCIE_GP0_AP_RX_P B15 B11 90_PCIE_ST0_AP_FROM_NAND_C_RX_P
PCIE GEN4 - ST LINK 0

23 GP_PCIE_RX0_P ST_PCIE_RX0_P IN 24
NC_DEV_PCIE_GP0_AP_RX_N A15 A11 90_PCIE_ST0_AP_FROM_NAND_C_RX_N RX CAPS LIVE OFF-PAGE
23 GP_PCIE_RX0_N ST_PCIE_RX0_N IN 24
LINK0
GND_VOID
C1102
ROOM=SOC
2 0.22UF
1
23
NC_DEV_PCIE_GP0_AP_TX_P C17 GP_PCIE_TX0_P ST_PCIE_TX0_P C13 90_PCIE_ST0_AP_TO_NAND_C_TX_P CER-X5R 10% 6.3V 01005
90_PCIE_ST0_AP_TO_NAND_TX_P 25
OUT
GND_VOID
NC_DEV_PCIE_GP0_AP_TX_N D17 GP_PCIE_TX0_N ST_PCIE_TX0_N D13 90_PCIE_ST0_AP_TO_NAND_C_TX_N 90_PCIE_ST0_AP_TO_NAND_TX_N
C1103
23 ROOM=SOC OUT 25
2 0.22UF
1
CER-X5R 10% 6.3V 01005
C CF2 CD3
C
23 NC_DEV_PCIE_GP0_AP_RESET_L GP_PCIE_PERST0* ST_PCIE_PERST0* PCIE_ST0_AP_TO_NAND_PERST_L OUT 25
33 9 PP1V2_IO
1
R1130
1
R1101
47.0K
47.0K 5%
5% 1/32W
1/32W MF
MF 01005
2 ROOM=SOC
2 01005
ROOM=SOC
95 PCIE_GP1_AP_BI_WLAN_CLKREQ_L CB4 GP_PCIE_CLKREQ1* GP_PCIE_CLKREQ2* CD2 PCIE_GP2_AP_BI_BB_CLKREQ_L 95

BI BI
BB CLKREQ PULL-UP LIVES IN RADIO HIERARCHY
24 90_PCIE_GP1_AP_FROM_WLAN_C_RX_P B19 GP_PCIE_RX1_P GP_PCIE_RX2_P B22 90_PCIE_GP2_AP_FROM_BB_RX_P 24

IN IN
RX CAPS LIVE OFF-PAGE
PCIE GEN4 - LINK 2

90_PCIE_GP1_AP_FROM_WLAN_C_RX_N A19 GP_PCIE_RX1_N GP_PCIE_RX2_N A22 90_PCIE_GP2_AP_FROM_BB_RX_N RX CAPS LIVE OFF-PAGE
PCIE GEN2 - LINK 1
24 IN IN 24
LINK1
LINK2
GND_VOID GND_VOID
C1112 C1122
ROOM=SOC ROOM=SOC
2 0.1UF
1 2 0.22UF
1
X5R-CERM 20% 6.3V 01005 C21 C24 CER-X5R 10% 6.3V 01005
95 OUT
90_PCIE_GP1_AP_TO_WLAN_TX_P 90_PCIE_GP1_AP_TO_WLAN_C_TX_P GP_PCIE_TX1_P GP_PCIE_TX2_P 90_PCIE_GP2_AP_TO_BB_C_TX_P 90_PCIE_GP2_AP_TO_BB_TX_P OUT 95
GND_VOID GND_VOID
90_PCIE_GP1_AP_TO_WLAN_TX_N 90_PCIE_GP1_AP_TO_WLAN_C_TX_N D21 GP_PCIE_TX1_N GP_PCIE_TX2_N D24 90_PCIE_GP2_AP_TO_BB_C_TX_N 90_PCIE_GP2_AP_TO_BB_TX_N
C1113 C1123
95 OUT ROOM=SOC ROOM=SOC OUT 95
2 0.1UF
1 2 0.22UF
1
X5R-CERM 20% 6.3V 01005 CER-X5R 10% 6.3V 01005
B B
95 PCIE_GP1_AP_TO_WLAN_PERST_L CF4 GP_PCIE_PERST1* GP_PCIE_PERST2* CF3 PCIE_GP2_AP_TO_BB_PERST_L 95

OUT OUT
R1131 1 R1121 1
100K 100K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
ANALOG_PCIE_RCAL_POS E19 PCIE_RCAL_P GP_PCIE_REF_CLK0_P A7 NC_DEV_PCIE_GP0_AP_REFCLK_P 23
NO_XNET_CONNECTION=1 GP_PCIE_REF_CLK0_N B7 NC_DEV_PCIE_GP0_AP_REFCLK_N 23

1
R1140 GP_PCIE_REF_CLK1_P B5 90_PCIE_GP1_AP_TO_WLAN_REFCLK_P OUT 95
200 A5 90_PCIE_GP1_AP_TO_WLAN_REFCLK_N
1% GP_PCIE_REF_CLK1_N OUT 95
1/32W
MF B4
01005
2 ROOM=SOC GP_PCIE_REF_CLK2_P 90_PCIE_GP2_AP_TO_BB_REFCLK_P OUT 95
GP_PCIE_REF_CLK2_N A4 90_PCIE_GP2_AP_TO_BB_REFCLK_N
ANALOG_PCIE_RCAL_NEG F19 PCIE_RCAL_N
OUT 95
ST_PCIE_REF_CLK0_P B6 90_PCIE_ST0_AP_TO_NAND_REFCLK_P 25 89
OUT
1 C1140 ST_PCIE_REF_CLK0_N A6 90_PCIE_ST0_AP_TO_NAND_REFCLK_N OUT 25 89
10PF
5%
16V
2 NP0/C0G
01005
SYNCING: D52, D53, D54, DEV

ROOM=SOC
A A
PAGE TITLE
SOC: PCIE
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

11 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DO NOT SWIZZLE LPDP LANES UNLESS ROUTING NECESSITATES IT

LPDP Swizzle Options:
-P/N can be switched
-Non-sequential lanes can be grouped
(e.g. FCAM 0 -> SOC 5, FCAM 1 -> SOC 2)
SOC: ISP
998-19672
-AUX pin (one per device) doesn't have to match lane numbers
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 4 OF 21
OMIT_TABLE TMLR67A0-C1
24 90_LPDP_ISP_FROM_FCAM_RX_D1_N CP19 LPDPRX_RX_D0_P MIPI0C_DPCLK CP60 90_MIPI_ISP_FROM_IRCAM_CLK_P 77
IN IN
24 90_LPDP_ISP_FROM_FCAM_RX_D1_P CN19 LPDPRX_RX_D0_N MIPI0C_DNCLK CN60 90_MIPI_ISP_FROM_IRCAM_CLK_N 77
IN IN
24 90_LPDP_ISP_FROM_FCAM_RX_D0_N CN21 LPDPRX_RX_D1_P MIPI0C_DPDATA0 CN58 90_MIPI_ISP_FROM_IRCAM_D0_P 77

IN BI
MIPI-C
24 90_LPDP_ISP_FROM_FCAM_RX_D0_P CM21 LPDPRX_RX_D1_N MIPI0C_DNDATA0 CP58 90_MIPI_ISP_FROM_IRCAM_D0_N 77
IN BI
24 90_LPDP_ISP_FROM_WIDE_RX_D2_P CP22 LPDPRX_RX_D2_P MIPI0C_DPDATA1 CN59 90_MIPI_ISP_FROM_IRCAM_D1_P 77

IN IN
24 90_LPDP_ISP_FROM_WIDE_RX_D2_N CN22 LPDPRX_RX_D2_N MIPI0C_DNDATA1 CP59 90_MIPI_ISP_FROM_IRCAM_D1_N 77
IN IN
24 90_LPDP_ISP_FROM_WIDE_RX_D1_N CP26 LPDPRX_RX_D3_P MIPI0C_REXT CL55 ANALOG_MIPI_ISP_REXT

IN
90_LPDP_ISP_FROM_WIDE_RX_D1_P CN26 LPDPRX_RX_D3_N
R1250
24 IN 1
ISP_I2C0_SCL CL58 NC_I2C0_ISP_SCL
90_LPDP_ISP_FROM_WIDE_RX_D0_N CN28 LPDPRX_RX_D4_P
20
200
24 IN
ISP_I2C0_SDA CL57 NC_I2C0_ISP_SDA 1%
C
90_LPDP_ISP_FROM_WIDE_RX_D0_P CM28 20
C 24 IN
90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D2_N CP30
LPDPRX_RX_D4_N
ISP_I2C1_SCL CM6 NC_I2C1_ISP_SCL 20
PP (dev board only)
1/32W
MF
2 01005
LPDPRX_RX_D5_P CM4
Note: LPDP RX and AUX lanes need a series 0.1uF cap
24 IN
CN30 ISP_I2C1_SDA NC_I2C1_ISP_SDA ROOM=SOC
90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D2_P LPDPRX_RX_D5_N
20
I2C
24 IN
24 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D0_P CN32 LPDPRX_RX_D6_P

IN
24 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D0_N CM32 LPDPRX_RX_D6_N
IN
90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D1_N CP34 LPDPRX_RX_D7_P
LPDP-RX
24 IN
24 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D1_P CN34 LPDPRX_RX_D7_N
IN
24 90_LPDP_ISP_FROM_JASPER_RX_D0_P CN36 LPDPRX_RX_D8_P ISP_GPIO_0 CK59 GPIO_ISP_TO_CAM_PMU1_CAM_PMU2_RESET_L 47 50

IN OUT
24 90_LPDP_ISP_FROM_JASPER_RX_D0_N CM36 LPDPRX_RX_D8_N ISP_GPIO_1 CM7 NC_ISP_GPIO_1 23
IN
ISP_GPIO_2 CL59 NC_ISP_GPIO_2
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D0_P CN40 LPDPRX_RX_D9_P
23
24 IN
ISP_GPIO_3 CN5 GPIO_ISP_RCAM_TO_STROBE_KRAKEN_WLAN_FLASH_TRIG
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D0_N CM40 OUT 65 70 95
GPIO
24 IN LPDPRX_RX_D9_N
External flash trigger:
24 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D1_P CP42 LPDPRX_RX_D10_P Kraken sends signal to Lightning accessory
IN
24 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D1_N CN42 LPDPRX_RX_D10_N
IN
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D2_P CN43 LPDPRX_RX_D11_P

R1240
24 IN
24 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D2_N CM43 LPDPRX_RX_D11_N
IN
AL2 CLK_ISP_TO_CAM_PMU1_24M_R 1
33.2 2 CLK_ISP_TO_CAM_PMU1_24M
CM24 SENSOR0_CLK OUT 47
ANALOG_LPDP_ISP_RX0_RCAL_POS LPDPRX0_RCAL_P
1%
CN24 LPDPRX0_RCAL_N 1/32W
1
R1200 CN38
MF
01005
200 LPDPRX1_RCAL_P ROOM=SOC
1% CP38
1/32W LPDPRX1_RCAL_N
MF
2 01005
ROOM=SOC R1260
ANALOG_LPDP_ISP_RX0_RCAL_NEG AN4 33.2 CLK_ISP_TO_CAM_PMU2_24M
SENSOR1_CLK CLK_ISP_TO_CAM_PMU2_24M_R 1 2 OUT 50
B 1 C1200 24 BI
NC_LPDP_ISP_AUX_RX_D0P CL22 LPDPRX_AUX_D0_P 1%
B
SENSOR CLK
1/32W
NC_LPDP_ISP_AUX_RX_D1P CK24 LPDPRX_AUX_D1_P MF
10PF 24 BI
01005
5% 24 LPDP_ISP_BI_SUPERFLEX_CAM2_AUX_RX_D2P CL26 LPDPRX_AUX_D2_P ROOM=SOC
BI
2 16V CK28
NP0/C0G
01005 24 BI
NC_LPDP_ISP_AUX_RX_D3P LPDPRX_AUX_D3_P
PACK_OPTION=D53,D54,DEV
ROOM=SOC 24 NC_LPDP_ISP_AUX_RX_D4P CL30 LPDPRX_AUX_D4_P BOMOPTION=PRO
BI
24 LPDP_ISP_BI_SINGLEFLEX_CAM_AUX_RX_D5P CK32 LPDPRX_AUX_D5_P
BI
24 NC_LPDP_ISP_AUX_RX_D6P CL34 LPDPRX_AUX_D6_P SENSOR2_CLK AN3 NC_SENSOR2_CLK_AP 23
BI
ANALOG_LPDP_ISP_RX1_RCAL_POS CK36
24 BI
1
R1210 24 BI
NC_LPDP_ISP_AUX_RX_D8P CL38
CK40
LPDPRX_AUX_D8_P
200 24 BI
1% CL42
1/32W 24 BI
MF CK43
2 01005 24 BI
ROOM=SOC
ANALOG_LPDP_ISP_RX1_RCAL_NEG AR3
SENSOR3_CLK NC_SENSOR3_CLK_AP 23
1 C1210
10PF
5%
16V
2 NP0/C0G
01005
ROOM=SOC

A A
PAGE TITLE
SOC: ISP
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

12 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SOC: DISPLAY / ISP

998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
C C
CSP
SYM 5 OF 21
OMIT_TABLE
TMLR67A0-C1
SPMI Address Map
24 90_MIPI_AP_TO_DISPLAY_CLK_P CN51 MIPID_DPCLK ISP_SPMI0_SCLK BJ4 SPMI_ISP_TO_CAM_PMU1_CLK 47 90 BUS DEVICE ADDR LOCATION
OUT OUT
ISP_SPMI
24 90_MIPI_AP_TO_DISPLAY_CLK_N CP51 MIPID_DNCLK ISP_SPMI0_SDATA BJ2 SPMI_ISP_BI_CAM_PMU1_DATA 47 90
OUT BI
BK2 SPMI0 ISP Adams1 0x09 Top MLB
CN55 ISP_SPMI1_SCLK SPMI_ISP_TO_CAM_PMU2_CLK
90_MIPI_AP_TO_DISPLAY_D0_P MIPID_DPDATA0 BJ3
OUT 50 90
24 OUT
CP55 ISP_SPMI1_SDATA SPMI_ISP_BI_CAM_PMU2_DATA SPMI1 ISP Adams2 0x09 Top MLB
24 OUT
90_MIPI_AP_TO_DISPLAY_D0_N MIPID_DNDATA0 BI 50 90
NOTE: SPMI1 ISP is for D53P/D54 only

DWI_CLK CM3 NC_SOC_DWI_CLK
90_MIPI_AP_TO_DISPLAY_D1_P CP53 MIPID_DPDATA1 1.8V
23
DWI
24 OUT
DWI_DO CK5 NC_SOC_DWI_DATA
24 90_MIPI_AP_TO_DISPLAY_D1_N CN53 MIPID_DNDATA1
23
OUT
MIPI-D
24 NC_MIPI_AP_TO_DISPLAY_D2_P CP47 MIPID_DPDATA2 DISP_TOUCH_BSYNC0 CM11 GPIO_AP_CANARY4 24
OUT
24 NC_MIPI_AP_TO_DISPLAY_D2_N CN47 MIPID_DNDATA2 DISP_TOUCH_BSYNC1 CN6 NC_TOUCH_BSYNC1_DISP 23
OUT
DISP_TOUCH_EB CM9 NC_SOC_DISP_TOUCH_EB
24 90_MIPI_AP_TO_DISPLAY_D2_P CN49 MIPID_DPDATA3
23
OUT
90_MIPI_AP_TO_DISPLAY_D2_N CP49 MIPID_DNDATA3
24 OUT
DISP_TE F34 IO_AOP_FROM_DISPLAY_TE 82 DISPLAY_TE also provides WDG functionality
IN
ANALOG_MIPI_AP_REXT CL53 MIPID_REXT
DISP_MIPI_PWR_DWN D47 IO_AOP_TO_DISPLAY_MIPI_PWR_DWN 82
OUT
GPIOS
DISP_HPD CK61 NC_EDP_HPD_DISP
R1300 1 23
NC_DEV_LPDP_AP_TX0P A40 LPDP_TX0P

200 23
DISP_I2C_SCL CL13 NC_SOC_DISP_I2C_SCL
1% NC_DEV_LPDP_AP_TX0N B40 LPDP_TX0N
23
1/32W
23
DISP_I2C_SDA CL60 NC_SOC_DISP_I2C_SDA 23
MF A42
NC_DEV_LPDP_AP_TX1P
LPDP-TX
01005 2 LPDP_TX1P CL62
23
B42 DISP_POL NC_SOC_DISP_POL
ROOM=SOC
23 NC_DEV_LPDP_AP_TX1N LPDP_TX1N
23
23 NC_DEV_LPDP_AP_TX2P A43 LPDP_TX2P

23 NC_DEV_LPDP_AP_TX2N B43 LPDP_TX2N
DISP_AGPIO D45 NC_SOC_DISP_AGPIO
23 NC_DEV_LPDP_AP_TX3P A45 LPDP_TX3P
23
B B
Dev breaks out to baseboard LPDP header B45 BG3
23 NC_DEV_LPDP_AP_TX3N LPDP_TX3N DISP_EXT_HPD NC_SOC_DISP_EXT_HPD 23
DP_WAKEUP CK17 GPIO_AP_CANARY3 PP (dev board only)

23 NC_DEV_LPDP_AP_AUXP A47 LPDP_AUX_P
24
23 NC_DEV_LPDP_AP_AUXN B47 LPDP_AUX_N
LPDP_RCAL_P/N are for LPDP TX, NC if unused 23 NC_DEV_LPDP_AP_RCALP A49 LPDP_RCAL_P

23 NC_DEV_LPDP_AP_RCALN B49 LPDP_RCAL_N
23 NC_LPDP_EXT_AP_TX0_P A53 LPDP_EXT_TX0P

23 NC_LPDP_EXT_AP_TX0_N B53 LPDP_EXT_TX0N


External LPDP not used A58
23 NC_LPDP_EXT_AP_TX3_P LPDP_EXT_TX3P
23 NC_LPDP_EXT_AP_AUX_P A59 LPDP_EXT_AUX_P

23 NC_LPDP_EXT_AP_AUX_N B59 LPDP_EXT_AUX_N
23 NC_LPDP_EXT_AP_RCAL_P A60 LPDP_EXT_RCAL_P

23 NC_LPDP_EXT_AP_RCAL_N B60 LPDP_EXT_RCAL_N

A A
PAGE TITLE
SOC: Display
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

13 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AP Serial
998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
D
SYM 7 OF 21
D 89 23 UART0_AP_FROM_KRAKEN_DEBUG_RXD CH62 UART0_RXD

OMIT_TABLE
I2C0_SCL AG62 NC_I2C0_AP_SCL 24
IN
89 23 UART0_AP_TO_KRAKEN_DEBUG_TXD CP5 UART0_TXD I2C0_SDA AJ61 NC_I2C0_AP_SDA 24
OUT
23 NC_UART1_AP_CTS_L BP2 UART1_CTS* I2C1_SCL AG4 NC_I2C1_AP_SCL 24
23 NC_UART1_AP_RTS_L BM3 UART1_RTS* I2C1_SDA AF2 NC_I2C1_AP_SDA 24
I2C
NC_UART1_AP_RXD BK4 UART1_RXD
23
I2C2_SCL AF3 I2C2_AP_SCL
NC_UART1_AP_TXD BK3 UART1_TXD OUT 20
23
I2C2_SDA AD2 I2C2_AP_SDA 20
BI
NC_UART2_AP_CTS_L BT4 UART2_CTS*
23
I2C3_SCL CL5 I2C3_AP_SCL_1V8
NC_UART2_AP_RTS_L BT2 UART2_RTS* OUT 20
23
I2C3_SDA CL49 I2C3_AP_SDA_1V8 NOTE:
23 NC_UART2_AP_RXD BP4 UART2_RXD 1.8V BI 20
NC_UART2_AP_TXD BP3 CL4 I2C_DISPLAY_SCL_1V8 I2S DIN/DOUT are SOC-centric,

23 UART2_TXD I2C4_SCL OUT 20
Alt AP UART7 CL47 I2C_DISPLAY_SDA_1V8 SOC DIN routes to load DOUT and vice-versa
I2C4_SDA
UART
23 NC_UART3_AP_CTS_L CJ61 UART3_CTS* BI 20
24 GPIO_AP_CANARY6 CM13 UART3_RTS* I2S0_DIN P2 I2S0_AP_FROM_CODEC_ASP3_DIN 58 89

IN
23 NC_UART3_AP_RXD CP6 UART3_RXD I2S0_DOUT T4 I2S0_AP_TO_CODEC_ASP3_DOUT 58 89 AP I2S0
OUT
GPIO_AP_CANARY5 CL15 UART3_TXD I2S0_BCLK P4 I2S0_AP_FROM_CODEC_ASP3_BCLK Used for MikeyBus
R1410
24 IN 58 89
I2S0_LRCK M2 I2S0_AP_FROM_CODEC_ASP3_LRCLK 58 89 (MCLK to Top Spk)

IN
P3 I2S0_AP_TO_SPKRAMP_TOP_MCLK_R 1
33.2 2 I2S0_AP_TO_SPKRAMP_TOP_MCLK
I2S0_MCK OUT 60
1%
89 23 UART4_AP_FROM_KRAKEN_ACC_RXD AL61 UART4_RXD I2S1_DIN AB4 I2S1_AP_FROM_CODEC_ASP4_DIN 58 89 1/32W
IN IN
MF
89 23 UART4_AP_TO_KRAKEN_ACC_TXD AL62 UART4_TXD I2S1_DOUT AD3 I2S1_AP_TO_CODEC_ASP4_DOUT 58 89 01005 AP I2S1
OUT OUT ROOM=SOC
I2S1_BCLK Y3 I2S1_AP_FROM_CODEC_ASP4_BCLK Used for Mics
NC_UART6_AP_RXD_1V8 CK6 UART6_RXD IN 58 89
23
1.8V I2S1_LRCK Y2 I2S1_AP_FROM_CODEC_ASP4_LRCLK
I2S
Use UART6_TXD as 1.8V GPIO GPIO_AP_TO_TOUCH_RESET_L_1V8 CL2 UART6_TXD IN 58 89
83 OUT
I2S1_MCK AB3 NC_I2S1_AP_MCLK 23
I2S2_DIN V2 I2S2_AP_FROM_BB_DIN 95
IN
I2S2_DOUT Y4 I2S2_AP_TO_BB_DOUT
C
OUT 95
C SPI0: NAND
R1400
23 IN
SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1
AL3
AJ2
SPI0_MISO I2S2_BCLK T2
T3
I2S2_AP_FROM_BB_BCLK
I2S2_AP_FROM_BB_LRCLK
IN 95
23 OUT SPI0_MOSI I2S2_LRCK IN 95
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 1
0.00 2 SPI0_AP_TO_NAND_SCLK_R AL4 V3 NC_I2S2_AP_MCLK
23 OUT SPI0_SCLK I2S2_MCK 23
SPI
0%
1/32W SPI1_AP_FROM_TOUCH_MISO_1V8 CK47 SPI1_MISO AP_SPMI2_SCLK AB2 NC_AP_SPMI2_SCLK
R1401
24 IN 24
SPI1: Cumulus MF
SPI1_AP_TO_TOUCH_MOSI_1V8 CK49 AF4 NC_AP_SPMI2_SDATA
01005 24 OUT SPI1_MOSI AP_SPMI2_SDATA 24
D53 only SPI1_AP_TO_TOUCH_SCLK_1V8 1
0.00 2 ROOM=SOC
SPI1_SCLK_AP_1V8_R CL6 1.8V
24 OUT SPI1_SCLK
0% 24 SPI1_AP_TO_TOUCH_CS_L_1V8 CL51 SPI1_SSIN
OUT
1/32W
MF
01005 NC_SPI2_MISO_AP BE2 SPI2_MISO
R1402
24 IN
SPI2: Ada ROOM=SOC
NC_SPI2_MOSI_AP BC2
PACK_OPTION=D53,DEV 24 OUT SPI2_MOSI
D52/D54 only NC_SPI2_SCLK_AP 1
0.00 2 24 NC_SPI2_SCLK_AP BC3
24 OUT SPI2_SCLK
0% 24 NC_SPI2_CS_L_AP BA3 SPI2_SSIN
OUT
1/32W
MF
SPI3_AP_FROM_CODEC_MISO BG2
XR1402
SHORT-01005-NOSMXWEB PACK_IGNORE=TRUE
01005
ROOM=SOC
23
23
IN
SPI3_AP_TO_CODEC_MOSI BE4
SPI3_MISO
SPI3_MOSI
OUT
PACK_OPTION=D54,DEV
1 2 SPI3_SCLK_AP_R BE3 SPI3_SCLK
ROOM=SOC 23 SPI3_AP_TO_CODEC_CS_L BC4 SPI3_SSIN
OUT
998-19685
R1403
PACK_IGNORE=TRUE
PACK_OPTION=D52
SPI3_AP_TO_CODEC_SCLK 1
0.00 2
SPI3: Brighton 998-19672
OUT
0%
1/32W
Place series terminations close to SoC Pins
ROOM=SOC U1000
SICILY-4GB-1YNM-M
23
MF
01005
ROOM=SOC
CSP
SYM 8 OF 21
OMIT_TABLE
33 GPIO_PMU_TO_SOC_DOUBLE_CLICK_DET_L AW3 SGPIO0 SSPI0_MISO AW2 NC_SSPI0_MISO_AP 23
IN
SSPI
PP (dev board only) 23 NC_SOC_S_GPIO1 AW4 SGPIO1 SSPI0_MOSI AU4 NC_SSPI0_MOSI_AP 23
B 20 OUT
I2C0_S_SCL AU1 SI2C0_SCL
SSPI0_SCLK AU3 NC_SSPI0_SCLK_AP 23
B
20 I2C0_S_SDA AU2 SI2C0_SDA
BI

A A
PAGE TITLE
SOC: Serial
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

14 OF 160
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
D D
SOC: AP GPIO
998-19672
ROOM=SOC U1000
C SICILY-4GB-1YNM-M
CSP
C
SYM 6 OF 21
OMIT_TABLE
22 GPIO_BOARD_REV3 BT3 GPIO0 GPIO GPIO16 BC61 GPIO_AP_FROM_BT_AUDIO_SYNC 22
22 GPIO_BOARD_REV2 BV2 GPIO1 GPIO17 BC60 GPIO_AP_TO_AMUX_PMU_SYNC 22
22 GPIO_BOARD_REV1 BY2 GPIO2 GPIO18 AW62 NC_DEV_AP_GPIO18 22
22 GPIO_BOARD_REV0 BV3 GPIO3 GPIO19 AW61 NC_DEV_AP_GPIO19 22
22 GPIO_AP_CANARY1 BY3 GPIO4 GPIO20 AW60 NC_DEV_AP_GPIO20 22
22 GPIO_AP_CANARY2 BY4 GPIO5 GPIO21 AU62 NC_DEV_AP_GPIO21 22
22 GPIO_AP_BI_CCG2B_SWDIO CK58 GPIO6 GPIO22 AU61 NC_DEV_AP_GPIO22 22
22 GPIO_AP_TO_CCG2B_SWCLK CL11 GPIO7 GPIO23 AU60 NC_DEV_AP_GPIO23 22
22 GPIO_AP_FROM_DISPLAY_PANEL_ID CM5 GPIO8 GPIO24 AR62 NC_DEV_AP_GPIO24 22
22 GPIO_AP_FROM_WLAN_TIME_SYNC CK15 GPIO9 GPIO25 AR61 GPIO_AP_TO_BB_TIME_MARK 22
22 GPIO_AP_TO_BB_PEAK_PWR_IND CN9 GPIO10 GPIO26 AN61 NC_DEV_AP_GPIO26 22
22 GPIO_AP_TO_BB_COREDUMP CP7 GPIO11

22 GPIO_AP_FROM_BB_RESET_DETECT_L CK19 GPIO12
22 GPIO_AP_FROM_CODEC_INT_L CL17 GPIO13
22 NC_AP_GPIO14 CJ60 GPIO14
22 GPIO_AP_TO_SPKRAMP_TOP_RESET_L BC62 GPIO15
B B

A A
PAGE TITLE
SOC: GPIO
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

15 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: AOP
998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 9 OF 21
OMIT_TABLE
21 I2C0_AOP_SCL F61 AOP_I2CM0_SCL AOP_FUNC0 E62 GPIO_SCM_AOP_FROM_IMU_DATARDY 22
OUT
21 I2C0_AOP_SDA F62 AOP_I2CM0_SDA AOP_FUNC1 F60 GPIO_SCM_AOP_TO_IMU_SPI_CS_L 22
BI
NOTE: E43 GPIO_AOP_FROM_PEARL_B2B_DETECT
I2C
F45 AOP_FUNC2
I2C1_AOP_SCL AOP_I2CM1_SCL
22
E60 NC_DEV_AOP_FUNC3
D
21 OUT
I2S DIN/DOUT are SOC-centric, AOP_FUNC3
D I2C1_AOP_SDA D42 22
AOP_I2CM1_SDA K61
SOC DIN routes to load DOUT and vice-versa
21 BI
AOP_FUNC4 GPIO_SCM_AOP_FROM_R1_INT 22
SPI0_AOP_FROM_IMU_R1_MISO H60 AOP_SPI0_MISO AOP_FUNC5 D60 GPIO_AOP_TO_R1_COREDUMP_TRIGGER

R1601
98 96 IN 22
98 96 SPI0_AOP_TO_IMU_R1_MOSI H62 AOP_SPI0_MOSI AOP_FUNC6 D62 GPIO_AOP_TO_R1_TIME_SYNC_L 22

OUT
SPI0_AOP_TO_IMU_R1_SCLK 1
33.2 2 SPI0_AOP_TO_IMU_R1_SCLK_R G62 A36 GPIO_AOP_TO_CODEC_RESET_L
98 96 90 OUT AOP_SPI0_SCLK AOP_FUNC7 22
E42 GPIO_AOP_TO_BB_FORCE_PWM
SPI
1% SPI1_SCLK/SSIN: Use as AOP GPIO D55 AOP_FUNC8
1/32W I2C2_AOP_SCL AOP_SPI1_MISO AOP I2C2 SCL E59
22
MF
32 21 IN
D57 AOP_FUNC9 GPIO_AOP_FROM_IRCAM_B2B_DETECT
01005 I2C2_AOP_SDA AOP_SPI1_MOSI AOP I2C2 SDA F57
22
21 OUT
D58 AOP_FUNC10 GPIO_SCM_AOP_TO_R1_SPI_CS_L
ROOM=SOC
GPIO_AOP_TO_WLAN_CONTEXT_B AOP_SPI1_SCLK
22
R1603 F42 NC_AOP_FUNC11

23 OUT
E34 AOP_FUNC11
GPIO_AOP_TO_WLAN_CONTEXT_A 22
GPIO
AOP_SPI1_SSIN D40
1
33.2 2
23 OUT
AOP_FUNC12 GPIO_AOP_TO_ALS_COEX 22
AOP I2S0 58 OUT
I2S0_AOP_TO_CODEC_MCLK1
I2S0_AOP_FROM_CODEC_ASP1_DIN D59 F58 GPIO_AOP_TO_NFC_IRONMAN_EN
89 58 IN AOP_I2S0_DIN AOP_FUNC13 22
Penrose, LDCM, 1% MF
Borealis R1606 1/32W
01005
89 58 OUT
I2S0_AOP_TO_CODEC_ASP1_DOUT E49
D36
AOP_I2S0_DOUT AOP_FUNC14 F53
E58
GPIO_AOP_FROM_TOUCH_CTS 22
2
0.00 1
ROOM=SOC 89 58 IN
I2S0_AOP_FROM_CODEC_ASP1_BCLK AOP_I2S0_BCLK AOP_FUNC15 GPIO_SCM_AOP_BI_PROX_INT_L 22
(MCLK to Codec) 62 61 60 59 58 IN
I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN
I2S0_AOP_FROM_CODEC_ASP1_LRCLK E36 E40 GPIO_SCM_AOP_FROM_ALS_INT_L
AOP_I2S0_LRCK AOP_FUNC16
I2S
89 58 IN 22
0%
1/32W I2S0_AOP_TO_CODEC_MCLK1_R F36 AOP_I2S0_MCK AOP_FUNC17 F51 GPIO_SCM_AOP_FROM_EIGER_INT_L 22
MF
01005
R1607 I2S1_AOP_FROM_AMPS_CODEC_ASP2_DIN_R C36 AOP_I2S1_DIN
AOP_FUNC18 E57
F40
GPIO_SCM_AOP_FROM_COMPASS_INT 22
AOP I2S1
ROOM=SOC
0.00 B36 AOP_FUNC19 GPIO_SCM_AOP_FROM_JARVIS_INT
I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT 2 1 I2S1_AOP_TO_AMPS_CODEC_ASP2_DOUT_R_SOC AOP_I2S1_DOUT D38
22
Out to BotSpk,
61 60 59 58 OUT
E53 AOP_FUNC20 GPIO_AOP_FROM_TOUCH_INT_L
0% MF I2S1_AOP_AMPS_FROM_CODEC_ASP2_BCLK AOP_I2S1_BCLK
22
R1608 E55 NC_AOP_FUNC21

62 61 60 59 58 IN
TopSpk, Arc, 1/32W
I2S1_AOP_AMPS_FROM_CODEC_ASP2_LRCLK E51 AOP_FUNC21 22
01005 AOP_I2S1_LRCK E38
in from Sak. 0.00 62 61 60 59 58 IN
E47 AOP_FUNC22 NC_DEV_AOP_FUNC22
61 59 OUT
I2S1_AOP_TO_SPKRAMP_BOT_ARCAMP_MCLK 2 1
ROOM=SOC
I2S1_AOP_TO_SPKRAMP_BOT_ARCAMP_MCLK_R AOP_I2S1_MCK
22
(MCLK to Arc 0%
and BotSpk) 1/32W 93 UART1_AOP_FROM_BB_RXD K62 AOP_SPMI1_SDATA SUPPORTS UART
BI
MF
01005 93 UART1_AOP_TO_BB_TXD G61 AOP_SPMI1_SCLK ALT FUNC1
OUT
R1622
ROOM=SOC
99 93 SPMI0_EVENTS_AOP_BI_WLAN_NFC_DATA D43 AOP_SPMI0_SDATA SUPPORTS UART

IN
33.2
UART
99 93 SPMI0_EVENTS_AOP_TO_WLAN_NFC_CLK 1 2 SPMI0_EVENTS_AOP_TO_WLAN_NFC_CLK_R F47 AOP_SPMI0_SCLK ALT FUNC1
OUT
1%
1/32W UART2_AOP_FROM_TOUCH_RXD G60 AOP_UART2_RXD
C
83 IN
C
MF
SPMI Address Map 01005
ROOM=SOC
89 83 OUT
UART2_AOP_TO_TOUCH_TXD E45 AOP_UART2_TXD
SOC: SMC
BUS DEVICE ADDR LOCATION
Touch UART R1621 1 1
R1620
SPMI0 AOP WLAN 0x0E Bottom MLB D52/D54: WIRED TO ADA 1.00M 1.00M
5% 5%
D52/D53: Top MLB D53: WIRED TO TOUCH B2B 1/32W 1/32W
SPMI0 AOP Ceres (P) 0x0C D54: Bottom MLB MF MF 998-19672
SPMI0 AOP Ceres (F) 0x0B

D53/D54: Top MLB
D52: Bottom MLB
01005 2 2 01005 ROOM=SOC U1000
SICILY-4GB-1YNM-M
NOTE: Ceres (F) default address is 0x0C, programmed to 0x0B on SMT line CSP
SYM 10 OF 21
BUS DEVICE ADDR LOCATION OMIT_TABLE
21 I2C0_SMC_SCL G4 SMC_I2CM0_SCL I2C
OUT
SPMI0 NUB Cota 0x0F Top MLB F26
21 BI
I2C0_SMC_SDA SMC_I2CM0_SDA
SPMI0 NUB DotaraLV 0x0E Top MLB G2
90 21 OUT
I2C1_SMC_SCL SMC_I2CM1_SCL
90 21 I2C1_SMC_SDA H2 SMC_I2CM1_SDA
BI
21 I2C2_SMC_SCL G3 SMC_I2CM2_SCL
OUT
21 I2C2_SMC_SDA F2 SMC_I2CM2_SDA
BI
SOC: NUB
998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 11 OF 21
R1610 OMIT_TABLE
B 38 30 OUT
SPMI0_NUB_TO_PMU_DOTARA_CLK 2
33.2 1 SPMI0_NUB_TO_PMU_DOTARA_CLK_R D32 NUB_SPMI0_SCLK SPMI B
1% 38 30 SPMI0_NUB_BI_PMU_DOTARA_DATA D4 NUB_SPMI0_SDATA
BI
1/32W
MF
01005 89 23 SWD_NUB_TO_PMU_TOUCH_SWCLK F6 NUB_SWD_TCK_OUT0
OUT
ROOM=SOC
89 33 SWD_NUB_BI_PMU_SWDIO F13 NUB_SWD_TMS0 SWD
BI
Touch SWDIO: Wired to Touch B2B (D52/D54) 42 NC_SWD_NUB_BI_TOUCH_SWDIO F11 NUB_SWD_TMS1
BI
Touch SWDIO: No connect (D53) F30
89 65 IN
IO_NUB_FROM_KRAKEN_DOCK_CONNECT NUB_DOCK_CONNECT DOCK
89 65 IO_NUB_FROM_KRAKEN_INT E30 NUB_DOCK_ATTENTION
IN
89 66 GPIO_NUB_FROM_CCG2B_INT_L D2 NUB_GPIO_0
IN
Gecko IRQ needs SOC weak internal PU 89 67 GPIO_NUB_FROM_GECKO_IRQ_L E4 NUB_GPIO_1
IN
Parrot INT needs external or SOC pull-up 68 GPIO_NUB_FROM_PARROT_INT_L E3 NUB_GPIO_2
89 IN
89 67 GPIO_NUB_TO_GECKO_RESET_L F28 NUB_GPIO_3 GPIO
OUT
Can use Dotara GPIO for BBPMU Clock EN 95 GPIO_NUB_TO_BBPMU_CLK_EN_DOTARA E2 NUB_GPIO_4
OUT
23 NC_NUB_GPIO5 F3 NUB_GPIO_5
24 GPIO_AOP_CANARY7 E28 NUB_GPIO_6
89 65 SWD_DOCK_TO_AP_SWCLK E5 JTAG_TCK
IN
89 65 SWD_DOCK_BI_AP_SWDIO C34 JTAG_TMS
BI
23 GND D6 JTAG_SEL
JTAG
23 NC_DEV_JTAG_TDI B34 JTAG_TDI
23 NC_DEV_JTAG_TDO E6 JTAG_TDO
23 NC_DEV_JTAG_TRST_L D5 JTAG_TRST*
23 90_EUSB_DBG_PARROT_BI_AP_N B30 DBG_USB_EDM

BI
90_EUSB_DBG_PARROT_BI_AP_P A30 DBG_USB_EDP
23 BI
ANALOG_DBG_USB_RESREF D30 DBG_USB_RESREF DEBUG USB
A 1
R1650 23 PP1V2_S2 E32 DBG_PROBE_VALID A
200 MLB: DBG_PROBE_VALID=1 PAGE TITLE
XR1660
SHORT-01005-NOSMXWEB
1%
1/32W
MF
DEV: Jumper for DBG_PROBE_VALID to 0 or 1 SOC: AOP & SMC & NUB
01005 IO_PMU_TO_SYSTEM_RESET_L D51 COLD_RESET* DRAWING NUMBER SIZE
2 ROOM=SOC 23 IN
IO_PMU_TO_SYSTEM_RESET_L D53 CFSB_AON 051-05215 D
Apple Inc.
23 IN
ROOM=SOC
998-19685 89 30 CLK_PMU_TO_AOP_32K D49 RT_CLK32768 MISC REVISION
IN
PACK_IGNORE=TRUE
PACK_OPTION=D52 89 30 OUT
IO_SOC_TO_PMU_WDOG_RESET D34 WDOG 4.6.0
R1660 89 23 OUT
IO_AON_TO_AP_XTAL_CFSB A34 AON_SLEEP1_RESET* NOTICE OF PROPRIETARY PROPERTY: BRANCH
NC_CLK_NUB_TO_TOUCH_24M 2
0.00 1 NC_CLK_NUB_TO_TOUCH_24M F15 THE INFORMATION CONTAINED HEREIN IS THE
24 OUT
24 NUB_CLK_OUT0 PROPRIETARY PROPERTY OF APPLE INC.
0%
1/32W
MF
ROOM=SOC
23 GND CP4 KIS_DFU_SELECT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
16 OF 160
01005 KIS_DFU_SELECT: SHEET
PACK_OPTION=D54,DEV
PACK_IGNORE=TRUE
POR = 0 (GND): USB0 for DFU (legacy)
Debug = 1 (1V2): USB1 for DFU (Kanzi-in-System) IV ALL RIGHTS RESERVED 14 OF 118
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OCELOT
C PP1V8_IO 33
C
1 C1700
2.2UF
20%
2 6.3V
X5R-CERM
0201
A1
ROOM=SOC_AUX
VCC
U1700
STOCT
WLCSP-1
20 IN
I2C0_S_SCL A2 SCL VIO C2 PP1V2_IO 33
335S00487
I2C0_S_SDA B1 SDA NC A3 VIO=1: 1.2V I2C
20 BI
CRITICAL NC
NC C1 VIO=0: 1.8V I2C
ROOM=SOC_AUX NC
VSS
B2
B3
C3
B B

A A
PAGE TITLE
SOC: Ocelot
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

17 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: CPU/GPU
998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 12 OF 21
OMIT_TABLE
2020-MLCC
33 PP_CPU_PCORE AP56 VDD_PCPU CPU/GPU VDD_GPU AA27 PP_GPU 33
138S00317
AP48 AA31
1 C1802 1 C1803 1 C1801 1 C1807 1 C1805 ROOM=SOC_FILT ROOM=SOC_FILT VDD_PCPU VDD_GPU 1 C1831 1 C1832 1 C1833 1 C1834
2.2UF 2.2UF 20UF 20UF 15UF C1804 C1806 AP52
AT41
VDD_PCPU VDD_GPU AA44
AA48
2.2UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 11UF 14UF VDD_PCPU VDD_GPU 20% 20% 20% 20%
D
2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
X5R
0402-0.1MM-1
20%
4V
X5R
20%
4V
X5R
AT50 VDD_PCPU VDD_GPU AA52 2 6.3V
X5R-CERM
0201
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM PP_SOC_S1 33 D
AT54 AC25
VDD_PCPU VDD_GPU
C1860 C1861 C1830 C1862
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT 0402 0402-D2X-1 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
1 1 1 1
1 3 1 3 AV39 VDD_PCPU VDD_GPU AC33
PACK_OPTION=D52,D53,DEV PACK_OPTION=D52,D53,DEV 2.2UF 2.2UF 2.2UF 20UF
AY54 VDD_PCPU VDD_GPU AC41 20% 20% 20% 20%
2 4 2 4 BF39 AC50 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
CERM-X5R
VDD_PCPU VDD_GPU 0201 0201 0201 0402-0.1MM
BH54 VDD_PCPU VDD_GPU AE27 ROOM=SOC_FILT ROOM=SOC_FILT
PACK_IGNORE=TRUE ROOM=SOC_FILT ROOM=SOC_FILT
PACK_OPTION=D54
BL39 VDD_PCPU VDD_GPU AE35
BL48 VDD_PCPU VDD_GPU AE44
138S00313
BL52 AE48
BN37
VDD_PCPU
VDD_PCPU
VDD_GPU
VDD_GPU AE52
1 C1863 1 C1863 1 C1864 1 C1866
ROOM=SOC_FILT ROOM=SOC_FILT 20UF 16UF 20UF 20UF
BN41 VDD_PCPU VDD_GPU N31 20% 20% 20% 20%
C1805 C1807 BN46 VDD_PCPU VDD_GPU N35 2 6.3V
CERM-X5R 2 4V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
14UF 14UF BN50 N39
0402-0.1MM 0402-0.1MM-1 0402-0.1MM 0402-0.1MM
20% 20% VDD_PCPU VDD_GPU ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
4V 4V PACK_IGNORE=TRUE
X5R X5R BN54 VDD_PCPU VDD_GPU N44 PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV
0402-D2X-1 0402-D2X-1 2020-MLCC
BR44 R25
PACK_IGNORE=TRUE
PACK_OPTION=D54
1
2 4
3 1
2 4
3
PACK_IGNORE=TRUE
PACK_OPTION=D54
BR52
BU37
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_GPU
VDD_GPU
VDD_GPU
R33
R41 998-19672
SOC: SOC
BU50 VDD_PCPU VDD_GPU R50 ROOM=SOC U1000
BW39 VDD_PCPU VDD_GPU U27 SICILY-4GB-1YNM-M
BW52 VDD_PCPU VDD_GPU U31 CSP
SYM 13 OF 21
CA37 VDD_PCPU VDD_GPU U44
CA50 U48 OMIT_TABLE
VDD_PCPU VDD_GPU AY25 BF56
CC37 U52 VDD_SOC_S1 SOC VDD_SOC_S1
VDD_PCPU VDD_GPU AA14 BL18
CC44 W29 VDD_SOC_S1 VDD_SOC_S1
VDD_PCPU VDD_GPU AA18 BL23
CC52 W46 VDD_SOC_S1 VDD_SOC_S1
VDD_PCPU VDD_GPU AH20 BL31
AE31 VDD_SOC_S1 VDD_SOC_S1
BL37 VDD_GPU AM54 BN20
ANALOG_PCPU_SENSE_P VDD_PCPU_SENSE VDD_SOC_S1 VDD_SOC_S1
C
89 27 OUT
C PP_CPU_ECORE AT29
VDD_GPU_SENSE AH29 ANALOG_GPU_SENSE_P OUT 89 AH37
AH46
VDD_SOC_S1 VDD_SOC_S1 BN29
AE14
33 VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
AT33 AH54 BR18
1 C1895 1 C1894 1 C1893 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
20UF 2.2UF 20UF C1891 C1892 C1893 AT37
AV31
VDD_ECPU AK10
AK14
VDD_SOC_S1 VDD_SOC_S1 BR23
BR27
20% 20% 20% 14UF 14UF 14UF VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM 2 6.3V
CERM-X5R 20% 20% 20%
BB27 AK18 BR31
0402-0.1MM 0201 0402-0.1MM 4V 4V 4V VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
X5R X5R X5R
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT 0402-D2X-1 0402-D2X-1 0402-D2X-1 BD37 VDD_ECPU AK23 VDD_SOC_S1 VDD_SOC_S1 BR35
PACK_OPTION=D52,D53,DEV 1 3 1 3 1 3 BF31 VDD_ECPU AK27 VDD_SOC_S1 VDD_SOC_S1 BU25
PACK_IGNORE=TRUE BF35 VDD_ECPU AA23 VDD_SOC_S1 VDD_SOC_S1 BU33
2 4 2 4 2 4 PACK_OPTION=D54
BH37 AK31 BW35
VDD_ECPU VDD_SOC_S1 VDD_SOC_S1
AK35 VDD_SOC_S1 VDD_SOC_S1 CE44
ANALOG_ECPU_SENSE_SE BL33 VDD_ECPU_SENSE
89 OUT AK39 VDD_SOC_S1 VDD_SOC_S1 CE52
AK44 VDD_SOC_S1 VDD_SOC_S1 AE18
SOC: SRAM
998-19672
AK48
AK52
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
CG18
CG29
AK56 VDD_SOC_S1 VDD_SOC_S1 N14
ROOM=SOC U1000 AM16 VDD_SOC_S1 VDD_SOC_S1 N18
SICILY-4GB-1YNM-M AM25 N23
CSP VDD_SOC_S1 VDD_SOC_S1
SYM 14 OF 21 AM33 VDD_SOC_S1 VDD_SOC_S1 N27
OMIT_TABLE AC16 VDD_SOC_S1 VDD_SOC_S1 N37
2020-MLCC SRAM
33 PP_CPU_SRAM AT46 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AH50 PP_SRAM_S1 33 AM50 VDD_SOC_S1 VDD_SOC_S1 N56
138S00313 138S00317
AV27 AM12 AP10 R16
1 C1812 1 C1812 1 C1811 1 C1808 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
10UF 20UF 16UF 15UF C1809 C1810 C1808 CC48
AV35
VDD_CPU_SRAM VDD_SRAM_SOC_S1 AM20
AM29
AP14
BH25
VDD_SOC_S1 VDD_SOC_S1 U14
AE23
20% 20% 20% 20% 14UF 11UF 14UF VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
2 10V
X5R-CERM 2 6.3V
CERM-X5R 2 4V
X5R 2 6.3V
X5R 20% 20% 20%
BB39 AM37 AP23 U18
0402-0.1MM 0402-0.1MM 0402-0.1MM-1 0402-0.1MM-1 4V 4V 4V VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
X5R X5R X5R
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT 0402-D2X-1 0402 0402-D2X-1 BD54 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AM46 AP27 VDD_SOC_S1 VDD_SOC_S1 U23
B B
PACK_IGNORE=TRUE 2020-MLCC 1 3 1 3 1 3
PACK_OPTION=D52,D53,DEV PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV BH33 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AT16 AP31 VDD_SOC_S1 VDD_SOC_S1 W12
PACK_IGNORE=TRUE BL44 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AT25 N46 VDD_SOC_S1 VDD_SOC_S1 W20
2 4 2 4 2 4 PACK_OPTION=D54
BR39 AY12 BL27 AH12
VDD_CPU_SRAM VDD_SRAM_SOC_S1 VDD_SOC_S1 VDD_SOC_S1
BR48 VDD_CPU_SRAM VDD_SRAM_SOC_S1 AY20 AT12 VDD_SOC_S1 VDD_SOC_S1 AP39
CC39 VDD_CPU_SRAM VDD_SRAM_SOC_S1 BD16 CA12 VDD_SOC_S1
VDD_SOC_SENSE AP16 ANALOG_SOC_SENSE_P
VDD_SRAM_SOC_S1 BD25 AT20 VDD_SOC_S1
OUT 89
33 PP_SRAM_S1 R29 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BH12 AV10 VDD_SOC_S1

138S00313
R37 BH20 AV14
1 C1872 1 C1872 1 C1873 1 C1874 1 C1865 AC29
VDD_SRAM_GPU_S1
VDD_SRAM_GPU_S1
VDD_SRAM_SOC_S1
VDD_SRAM_SOC_S1 BN16 AV18
VDD_SOC_S1
VDD_SOC_S1
16UF 15UF 20UF 20UF 2.2UF
20% 20% 20% 20% 20% AC37 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BN25 AV23 VDD_SOC_S1
2 4V
X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R-CERM AC46 BN33 AY16
0402-0.1MM-1 0402-0.1MM-1 0402-0.1MM 0402-0.1MM 0201 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 VDD_SOC_S1
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT R46 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BN8 BB10 VDD_SOC_S1
PACK_IGNORE=TRUE
PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV PACK_OPTION=D52,D53 W25 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BU12 BB14 VDD_SOC_S1
2020-MLCC
W33 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BU20 BB18 VDD_SOC_S1
W50 VDD_SRAM_GPU_S1 VDD_SRAM_SOC_S1 BU29 BB23 VDD_SOC_S1
VDD_SRAM_SOC_S1 BU52 AE10 VDD_SOC_S1
VDD_SRAM_SOC_S1 CA16 BD12 VDD_SOC_S1
VDD_SRAM_SOC_S1 CA25 BD20 VDD_SOC_S1
VDD_SRAM_SOC_S1 CA33 BF18 VDD_SOC_S1
VDD_SRAM_SOC_S1 CE29 BF23 VDD_SOC_S1
VDD_SRAM_SOC_S1 CE50
VDD_SRAM_SOC_S1 AC12
VDD_SRAM_SOC_S1 AC20
VDD_SRAM_SOC_S1 AH16
VDD_SRAM_SOC_S1 AH25
VDD_SRAM_SOC_S1 AH33 SYNCING: D52, D53, D54, DEV
A VDD_SRAM_SOC_S1 AH41
AM56
A
VDD_SRAM_SOC_S1 PAGE TITLE
VDD_SRAM_SOC_S1 L25
SOC: Power (CPU/GPU & SRAM & SOC)
VDD_SRAM_SOC_S1 N52
DRAWING NUMBER SIZE
VDD_SRAM_SOC_S1 R20
051-05215 D
VDD_SRAM_SOC_S1 U12
W16
Apple Inc. REVISION
VDD_SRAM_SOC_S1
4.6.0

18 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SUBSYSTEM SPECIFIC BOM TABLES
2.2uF 0201 Capacitors (single-source Murata)
SOC: FIXED
TABLE_ALT_HEAD
998-19672
PART NUMBER
BOM OPTION REF DES COMMENTS:
ROOM=SOC U1000
TABLE_ALT_ITEM
SICILY-4GB-1YNM-M
138S00049 138S0831 ? (C1970) CAP,CER,X5R,2.2UF,20%,6.3V,0201
CSP OMIT
OMIT_TABLE
SYM 17 OF 21
XW1940
SHORT-20L-0.05MM-SM
33
PP0V78_SOC_FIXED_S1 AP8 VDD_FIXED_S1 VDD_FIXED_PCIE_REFBUF_S1 J12 PP0V78_SOC_FIXED_PCIE_REFBUF 2 1 PP0V78_SOC_FIXED_S1 33
AV56 VOLTAGE=0.8
1 C1901 1 C1907 1 C1908 1 C1909 CA52
VDD_FIXED_S1
VDD_FIXED_S1 FIXED
1 C1940 ROOM=SOC_FILT
2.2UF 220PF 220PF 220PF 0.1UF

D
20%
2 6.3V
X5R-CERM
5%
2 25V
COG
5%
25V
2 COG
5%
2 25V
COG
CE16
CG31
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_PCPU_S1 AP46 20%
2 6.3V
X5R-CERM D
0201
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
33 PP0V78_SOC_FIXED_S1 CG52 VDD_FIXED_MIPID_S1 VDD_FIXED_ECPU_S1 AY39
1 C1906 1 C1905
2.2UF 0.1UF
20% 20% CG56 VDD_FIXED_MIPIC_S1 VDD_FIXED_MTR_S1 CF60
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 01005 PP0V78_SOC_FIXED_S1 33
C1941 C1942 C1902

ROOM=SOC_FILT ROOM=SOC_FILT
1 1 1
CK55 VDD_FIXED_MIPID_PLL_S1 VDD_FIXED_PLL_GPU_S1 AE41
33 PP0V78_SOC_FIXED_S1 0.1UF 0.1UF 0.1UF
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V
1 C1910 X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
01005
0.1UF J20 VDD_FIXED_USB_S1 VDD_FIXED_PLL_DDR0_S1 CE12 ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
20%
2 6.3V VDD_FIXED_PLL_DDR1_S1 BP60
X5R-CERM
01005 VDD_FIXED_PLL_DDR2_S1 AC10
ROOM=SOC_FILT
J52 VDD_FIXED_LPDP_TX_S1 VDD_FIXED_PLL_DDR3_S1 P60
33 GND J56 VDD_FIXED_LPDP_TX_S1
(Not used for MLBs)
CE33 VDD_FIXED_LPDP_RX_S1 VDD_FIXED_PLL_SOC_S1 BH27
PP0V78_SOC_FIXED_S1
33
CE37 VDD_FIXED_LPDP_RX_S1
1 C1916 1 C1918 1 C1917 CE41 VDD_FIXED_LPDP_RX_S1
4UF 0.1UF 0.1UF CE46 VDD_FIXED_LPDP_RX_S1 VDD_FIXED_PLL_ANE_S1 CA35
20% 20% 20%
2 4V 2 6.3V 2 6.3V
X5R
0201
ROOM=SOC_FILT
X5R-CERM
01005
X5R-CERM
01005 R1970
L16 F9 PP0V78_VDD_FIXED_XTAL 1
20.0 2 PP0V78_SOC_FIXED_S1
VDD_FIXED_PCIE_S1 VDD_FIXED_XTAL_S1 33
L20 VOLTAGE=0.8
PP0V78_SOC_FIXED_S1 N16
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
1 C1970 5%
1/32W
MF
2.2UF
C
33
C
01005
20%
1 C1922 1 C1921 1 C1920 2 6.3V
X5R-CERM
ROOM=SOC_FILT
4UF 0.1UF 0.1UF 0201

20% 20% 20%
2 6.3V 2 6.3V
ROOM=SOC_FILT
2 4V
X5R X5R-CERM X5R-CERM
0201 01005 01005 [SS] MURATA
ROOM=SOC_FILT
PP1V2_S2
SOC: VDD12
33
33 PP1V2_IO
Place cap near pin 1 C1935
1 C1904 [LAYOUT] VDDIO12_GRPx: Isolation >= 2.5nH
2.2UF
0.1UF 998-19672 20% from other nets on the same domain
20% 2 6.3V
2 6.3V
X5R-CERM ROOM=SOC U1000 X5R-CERM
0201 OMIT
01005
ROOM=SOC_FILT
SICILY-4GB-1YNM-M ROOM=SOC_FILT
XW1901
SHORT-10L-0.1MM-SM
CSP
SYM 18 OF 21 PP1V2_IO_GRP3 2 1 PP1V2_IO 33
33 PP1V2_S2 VOLTAGE=1.2
OMIT_TABLE
Place cap near pin 1 C1900 F22 VDD12_USB VDDIO12_GRP1_S2 CG12
NO_XNET_CONNECTION
RADAR #: 54364908
VDD12 2.2UF
0.1UF F24 VDD12_USB_DEBUG_S2 20%
PLACE NEAR SOC 20% VDDIO12_GRP3 AY56 2 6.3V
6.3V
2 X5R-CERM X5R-CERM OMIT
OMIT To ANE VDDIO12_GRP3 BD56 0201
XW1930 17
01005
ROOM=SOC_FILT
VDDIO12_GRP3 BL56
ROOM=SOC_FILT
XW1902
SHORT-10L-0.1MM-SM
SHORT-20L-0.05MM-SM CG16 PP1V2_IO_GRP4 2 1 PP1V2_IO
1 2 AP44 VDDIO12_GRP4 33
PP1V2_SOC PP1V2_SOC_FILT VOLTAGE=1.2 VDD12_PLL_PCPU VOLTAGE=1.2
33
CG20
ROOM=SOC_FILT Place 01005 caps 1 C1926 1 C1927 1 C1928
VDDIO12_GRP4
VDDIO12_GRP4 CG23
NO_XNET_CONNECTION
near pins 2.2UF
2.2UF 0.1UF 0.1UF VDDIO12_GRP5 AH8 20%
(incl. ANE) 20% 20% 20%
AM8 2 6.3V
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM AY37 VDDIO12_GRP5 X5R-CERM
0201
0201 01005 01005 VDD12_PLL_ECPU AT8
VDDIO12_GRP5 ROOM=SOC_FILT
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
VDDIO12_GRP5 AY8
PP1V2_IO
VDDIO12_GRP5 BD8 33
B 33 PP1V2_S1 1
FL1950
2 PP1V2_S1_XTAL
VOLTAGE=1.2 AE39
1 C1948 B
1 C1946 240-OHM-25%-0.20A-1.0DCR 1 C1903 VDD12_PLL_GPU
VDD12_PCIE J14
2.2UF
20%
4UF 01005 0.1UF 2 6.3V
20% ROOM=SOC_FILT
155S0755 20% VDD12_PCIE J18 X5R-CERM
2 4V 2 6.3V 0201
X5R X5R-CERM ROOM=SOC_FILT
0201 01005
ROOM=SOC_FILT ROOM=SOC_FILT F7 VDD12_XTAL_S1 PP1V2_SOC 33
33 PP1V2_S2 CL9 VDD12_AMUX_S2 VDD12_MTR CH60 PP1V2_SOC 33
33 PP1V2_IO CG54 VDD12_MIPIC 1 C1937 1 C1955 1 C1950

PP1V2_S1 CK53 VDD12_MIPID_S1 2.2UF 0.1UF 4UF
33
VDD12_LPDP_TX L50 20% 20% 20%
2 6.3V 2 6.3V 2 4V
1 C1998 1 C1999 1 C1997 1 C1996 AM41 VDD12_TSADC_CPU0
VDD12_LPDP_TX L54 X5R-CERM
0201
X5R-CERM
01005
X5R
0201
2.2UF 0.1UF 2.2UF 0.1UF ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
20% 20% 20% 20% AT39 VDD12_TSADC_CPU1
6.3V
2 X5R-CERM 2 6.3V 2 6.3V 2 6.3V
X5R-CERM X5R-CERM X5R-CERM GND
0201 01005 0201 01005 33
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT AP35 VDD12_TSADC_SOC0
AC52 VDD12_TSADC_SOC1
VDD12_LPDP_RX CG35 PP1V2_IO
PP1V2_IO R12 VDD12_TSADC_SOC2
33
33
CG39
VDD12_LPDP_RX
VDD12_LPDP_RX CG44
1 C1931 1 C1932 1 C1933
PP1V2_S2 J27 VDDIO12_AOP_S2 0.01UF 0.1UF 4UF
33
VDD12_LPDP_RX CG48 10% 20% 20%
J31 2 6.3V 2 6.3V 2 4V
Place cap near pins 1 C1923 1 C1924 J35
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDD12_LPDP_RX CG37 X5R
01005
X5R-CERM
01005
X5R
0201
2.2UF 0.1UF ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
20% 20% J39 VDDIO12_AOP_S2 VDD12_EFUSE1 N50
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM J44 W18
0201 01005 VDDIO12_AOP_S2 VDD12_EFUSE2
ROOM=SOC_FILT
J48 VDDIO12_AOP_S2 VDD12_EFUSE3 AM39
ROOM=SOC_FILT
N48 Used for SoC fusing

BF27 VDD12_EFUSE4
VDD12_PLL_SOC_S1 AP37 GND on all systems
BH29 VDD12_EFUSE5
A R19602
PP1V2_S1 VDD12_PLL_SOC_S1
A
33
R14 49.9 1
1% MF
1 C1963 1 C1964 VDD12_FMON PP1V2_VDD12_FMON
VOLTAGE=1.2 01005 1/32W
PP1V2_IO 33
PAGE TITLE
2.2UF 0.1UF VDD12_PCIE_REFBUF L12 ROOM=SOC_FILT
PP1V2_SOC 33
20% 20% SOC: Power (Fixed & 1V2)
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM VDD12_ULPPLL_S2 L33 PP1V2_VDD12_ULPPLL_S2
49.9 1
R19612 1% MF
PP1V2_S2 DRAWING NUMBER SIZE
0201 01005 VOLTAGE=1.2
33
ROOM=SOC_FILT
ROOM=SOC_FILT 01005 1/32W
051-05215 D
K60
Apple Inc.
ROOM=SOC_FILT
VDD12_ADC_SOC_S1 PP1V2_S1 33
REVISION
PP1V2_S1 CE14 VDDIO12_PLL_DDR0_S1
33
Shares decap with other S1 rails BM60 VDDIO12_PLL_DDR1_S1 1 C1938 1 C1995 1 C1936 [LAYOUT] VDD12_PCIE_REFBUF: Inductance from 4.6.0
AC8 4UF 0.1UF 2.2UF C1995.1 to PP1V2_SOC plane >1.5nH @ 100MHz NOTICE OF PROPRIETARY PROPERTY: BRANCH
VDDIO12_PLL_DDR2_S1 20% 20% 20% THE INFORMATION CONTAINED HEREIN IS THE
M60 VDDIO12_PLL_DDR3_S1 2 4V 2 6.3V 2 6.3V PROPRIETARY PROPERTY OF APPLE INC.
X5R X5R-CERM X5R-CERM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0201 01005 0201
17 PP1V2_SOC_FILT CC35 VDD12_PLL_ANE
ROOM=SOC_FILT
ROOM=SOC_FILT ROOM=SOC_FILT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
19 OF 160
Share cap with VDD12_PLL_ECPU/_PCPU/_GPU III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: DDR
998-19672
ROOM=SOC U1000
SICILY-4GB-1YNM-M
CSP
SYM 16 OF 21
OMIT_TABLE
33 PP_DCS_S1 BR10 VDD_DCS_DDR0_S1 DDR VDD2_DDR0_S2 BA2 PP1V06_S2 33
138S00321 138S00321
CE10 BP1
1 C2088 1 C2087 1 C2086 1 C2085 VDD_DCS_DDR0_S1 VDD2_DDR0_S2
VDD2_DDR0_S2 BV1
1 C2080 1 C2081 1 C2082 1 C2083
4UF 4UF 2.7UF 2.7UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% BR54 VDD_DCS_DDR1_S1 VDD2_DDR0_S2 CB1 20% 20% 20% 20%
D
2 4V
X5R
0201
2 4V
X5R
0201
2 4V
X5R
0201
2 4V
X5R
0201
CE54 VDD_DCS_DDR1_S1 VDD2_DDR0_S2 CL3 2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201
2 6.3V
X5R-CERM
0201 D
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
2020-MLCC 2020-MLCC
AA10 VDD_DCS_DDR2_S1 VDD2_DDR1_S2 BA62
L10 VDD_DCS_DDR2_S1 VDD2_DDR1_S2 BM63
PLACE CAPS ON SOC CORNERS BT63 PLACE CAPS ON SOC CORNERS
VDD2_DDR1_S2
AC54 VDD_DCS_DDR3_S1 VDD2_DDR1_S2 BY63
R54 VDD_DCS_DDR3_S1 VDD2_DDR1_S2 CL61
ANALOG_DCS_SENSE_SE AD62 VDD_DCS_SENSE

89 OUT
VDD2_DDR2_S2 AB1
VDD2_DDR2_S2 AN2
PP0V6_VDDQL_S1 BE1 VDDQL_DDR0_S1
33
VDD2_DDR2_S2 D3
BJ1
1 C2093 1 C2092 1 C2091 1 C2090 BM1
VDDQL_DDR0_S1
VDDQL_DDR0_S1
VDD2_DDR2_S2 P1
2.2UF 2.2UF 2.2UF 2.2UF VDD2_DDR2_S2 V1
20% 20% 20% 20% BU8 VDDQL_DDR0_S1
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM CE8
0201 0201 0201 0201 VDDQL_DDR0_S1 AN62
CF1 VDD2_DDR3_S2
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
VDDQL_DDR0_S1 D61
CJ1 VDD2_DDR3_S2
VDDQL_DDR0_S1 M63
CL1 VDD2_DDR3_S2
PLACE CAPS ON SOC CORNERS VDDQL_DDR0_S1 T63
VDD2_DDR3_S2
VDD2_DDR3_S2 Y63
BC63 VDDQL_DDR1_S1
BG63 VDDQL_DDR1_S1
BK63 VDDQL_DDR1_S1
BR56 VDDQL_DDR1_S1
VDDIO11_RET_DDR0_S2 CJ4
CC56 VDDQL_DDR1_S1
VDDIO11_RET_DDR1_S2 BT60
CD63 VDDQL_DDR1_S1
VDDIO11_RET_DDR2_S2 K4
CH63 VDDQL_DDR1_S1
VDDIO11_RET_DDR3_S2 Y60
CK63 VDDQL_DDR1_S1
C AD1
C
VDDQL_DDR2_S1 BA1
AG1 VDD1_DDR0_S2 PP1V8_S2 33
VDDQL_DDR2_S1 CM2
AL1 VDDQL_DDR2_S1
VDD1_DDR0_S2 1 C2096 1 C2097 1 C2098 1 C2099
E1 VDDQL_DDR2_S1 0.22UF 0.22UF 0.22UF 0.22UF
VDD1_DDR1_S2 BA63 10% 10% 10% 10%
G1 VDDQL_DDR2_S1 2 6.3V 2 6.3V 2 6.3V 2 6.3V
VDD1_DDR1_S2 CM62 CER-X5R CER-X5R CER-X5R CER-X5R
K1 VDDQL_DDR2_S1 01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
01005
ROOM=SOC_FILT
L8 VDDQL_DDR2_S1
VDD1_DDR2_S2 AN1
W8 VDDQL_DDR2_S1
VDD1_DDR2_S2 C2 PLACE CAPS ON SOC CORNERS
AB63 VDDQL_DDR3_S1
VDD1_DDR3_S2 AN63
AE56 VDDQL_DDR3_S1
VDD1_DDR3_S2 C62
AF63 VDDQL_DDR3_S1
AJ63 VDDQL_DDR3_S1
D63 VDDQL_DDR3_S1
F63 VDDQL_DDR3_S1
H63 VDDQL_DDR3_S1
R56 VDDQL_DDR3_S1
89 ANALOG_VDDQL_SENSE_SE AD60 VDDQL_SENSE

OUT
PP0V7_VDD_LOW_S2
SOC: AOP/AVE/ISP/USB
33
1 C2000 1 C2001 998-19672

2.2UF 2.2UF
20%
2 6.3V
20%
2 6.3V
ROOM=SOC U1000
X5R-CERM X5R-CERM
1 C2020 0201 0201 SICILY-4GB-1YNM-M
R2021
CSP
0.1UF
B B
SYM 15 OF 21
10 20%
6.3V
1 2 2 X5R-CERM OMIT_TABLE
01005 PLACE AT SOC BALLS J25 CG10 PP1V8_IO
5%
1/32W 1 C2050 ROOM=SOC_FILT
L29
VDD_LOW_S2 VDDIO18_GRP1 33
MF
01005
20%
0.47UF
L37
VDD_LOW_S2
VDD_LOW_S2 VDDIO06_GRP1_1 CK9 PP0V6_VDDIO06_GRP1_1
1 C2073
4UF
R2022
ROOM=SOC_FILT
2 6.3V
X5R L41 VOLTAGE=0.6 20%
VDD_LOW_S2
49.9 01005 2 4V
1 2 ROOM=SOC_FILT L46 VDD_LOW_S2
LOW/AVE/DISP
VDDIO06_GRP1_2 CK11 PP0V6_VDDIO06_GRP1_2
VOLTAGE=0.6
1 C2010 X5R
0201
4UF ROOM=SOC_FILT
1%
1/32W
MF
1 C2052 J23 VDD_LOW_USB_DEBUG_S2 1 C2011
20%
2 4V
01005 4UF X5R
ROOM=SOC_FILT 20% PP0V7_VDD_LOW_FLPPLL VOLTAGE=0.7 J33 VDD_LOW_FLPPLL_S2 4UF 0201
ROOM=SOC_FILT
2 4V
X5R
20%
0201 L31 2 4V
X5R
ROOM=SOC_FILT
PP0V7_VDD_LOW_ULPPLL VOLTAGE=0.7 VDD_LOW_ULPPLL_S2 0201
ROOM=SOC_FILT
BW23 VDD_AVE_S1 VDDIO06_GRPx RADAR #: 48907718
BW27 VDD_AVE_S1 Cmin = 4.7uF
BW31 VDD_AVE_S1 Loop R < 0.2 ohm
33 PP_AVE_S1 CA29 VDD_AVE_S1 Loop L < 1nH
1 C2026 1 C2025 1 C2024 CC23 VDD_AVE_S1
20UF 20UF 15UF CC27 VDD_AVE_S1
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V CC31 VDD_AVE_S1
CERM-X5R CERM-X5R X5R
0402-0.1MM 0402-0.1MM 0402-0.1MM-1 CE20 VDD_AVE_S1
ROOM=SOC_FILT ROOM=SOC_FILT ROOM=SOC_FILT
PACK_IGNORE=TRUE CE25 VDD_AVE_S1
PACK_OPTION=D54
CG27 VDD_AVE_S1
33 PP_DISP_S1 BF10 VDD_DISP_S1

BF14
1 C2033 1 C2030 ROOM=SOC_FILT
BH16
VDD_DISP_S1
VDD_DISP_S1
20%
20UF
20%
20UF C2032 BH8 VDD_DISP_S1
A 2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM
14UF
20%
4V
BL10
BL14
VDD_DISP_S1
A
ROOM=SOC_FILT ROOM=SOC_FILT X5R VDD_DISP_S1 PAGE TITLE
0402-D2X-1
BN12 VDD_DISP_S1
1 3 SOC: Power (DDR & AOP/AVE/ISP/USB)
BR14 VDD_DISP_S1
DRAWING NUMBER SIZE
2 4 BU16 VDD_DISP_S1
051-05215 D
BW14
BW18
VDD_DISP_S1 Apple Inc. REVISION
VDD_DISP_S1
CA20 VDD_DISP_S1
4.6.0
CC14 NOTICE OF PROPRIETARY PROPERTY: BRANCH
VDD_DISP_S1
CC18 VDD_DISP_S1 PROPRIETARY PROPERTY OF APPLE INC.
20 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC: GND
998-19672 998-19672 998-19672
ROOM=SOC U1000 ROOM=SOC U1000 ROOM=SOC U1000
SICILY-4GB-1YNM-M SICILY-4GB-1YNM-M SICILY-4GB-1YNM-M
CSP CSP CSP
SYM 19 OF 21 SYM 20 OF 21 SYM 21 OF 21
OMIT_TABLE OMIT_TABLE
TMLR67A0-C1 OMIT_TABLE
TMLR67A0-C1
A13 VSS VSS BH10 BY62 VSS VSS CK13 D7 VSS VSS U29
D A17 VSS VSS BH14 C1 VSS VSS AF61 E11 VSS VSS U33 D
A61 VSS VSS BH18 C11 VSS VSS CK2 E13 VSS VSS U46
AP50 VSS VSS BH23 C15 VSS VSS CK21 E15 VSS VSS U50
AP54 VSS VSS AA33 C19 VSS VSS CK22 E17 VSS VSS V4
AR1 VSS VSS BH31 C22 VSS VSS CK26 AE16 VSS VSS V61
AR4 VSS VSS BH35 C26 VSS VSS CK3 E21 VSS VSS V62
AR60 VSS VSS BH39 C28 VSS VSS CK30 E22 VSS VSS V63
AR63 VSS VSS BH56 AC23 VSS VSS CK34 E24 VSS VSS AE8
AT10 VSS VSS BJ63 C3 VSS VSS CK38 E26 VSS VSS W10
AT14 VSS VSS BK1 C30 VSS VSS CK4 E61 VSS VSS W14
AT18 VSS VSS BK60 C32 VSS VSS CK42 E63 VSS VSS W23
AT23 VSS VSS CH2 C38 VSS VSS AC56 E7 VSS VSS W27
A62 VSS VSS BL12 C4 VSS VSS CK45 F1 VSS VSS W31
AT27 VSS VSS BL16 C40 VSS VSS CK51 F17 VSS VSS W44
AT31 VSS VSS AA46 C42 VSS VSS CK57 F21 VSS VSS W48
AT35 VSS VSS BL20 C43 VSS VSS CK60 AE20 VSS VSS Y1
AT56 VSS VSS BL25 C45 VSS VSS CK7 F32 VSS VSS Y62
AT44 VSS VSS AE33 C47 VSS VSS CL19 F38 VSS VSS A26
AT48 VSS VSS BL41 AC27 VSS VSS CL21 F4 VSS VSS AF1
CF61 VSS VSS BL46 C49 VSS VSS CL24 F43 VSS VSS AF60
AU63 VSS VSS BL50 C5 VSS VSS CL28 F49 VSS VSS AG63
AV12 VSS VSS BL54 C51 VSS VSS CL32 F55 VSS VSS AH10
AV16 VSS VSS BL8 C53 VSS VSS AD4 F59 VSS VSS AH14
A9 VSS VSS BM4 C55 VSS VSS CL36 G63 VSS VSS AH18
AV20 VSS VSS BM61 C57 VSS VSS CL40 H1 VSS VSS AH23
AV25 VSS VSS A2 C58 VSS VSS CL43 H3 VSS VSS BF29
C
AV29 AA50 C59 CL45 AE25 AH31
C AV33
VSS
VSS
VSS
VSS BM62 C6
VSS
VSS
VSS
VSS CL63 H4
VSS
VSS
VSS
VSS AH35
AV37 VSS VSS BN10 C60 VSS VSS CM1 H61 VSS VSS A3
AV54 VSS VSS BN14 AC31 VSS VSS CM17 J29 VSS VSS AH39
AV8 VSS VSS BN18 C61 VSS VSS CM19 J37 VSS VSS AH44
AW1 VSS VSS BN23 C63 VSS VSS CM22 J41 VSS VSS AH48
AW63 VSS VSS BN27 C7 VSS VSS CM26 J46 VSS VSS AH52
AY10 VSS VSS BN31 C9 VSS VSS BB25 J50 VSS VSS AH56
AA12 VSS VSS BN35 CA14 VSS VSS CM30 J54 VSS VSS AJ1
AY14 VSS VSS BN39 CA18 VSS VSS CM34 J8 VSS VSS AJ4
AY18 VSS VSS BN44 CA23 VSS VSS CM38 K2 VSS VSS AJ60
AY23 VSS VSS AA8 CA27 VSS VSS CM42 AE29 VSS VSS AK12
AY27 VSS VSS BN48 CA31 VSS VSS CM45 K63 VSS VSS AK16
BB56 VSS VSS BN52 CA39 VSS VSS CM47 L14 VSS VSS A32
B1 VSS VSS BN56 AC35 VSS VSS CM49 L18 VSS VSS AK20
B13 VSS VSS BP61 CB62 VSS VSS CM51 L23 VSS VSS AK25
B17 VSS VSS BP62 CB63 VSS VSS CM53 L27 VSS VSS AK29
B21 VSS VSS BP63 CC12 VSS VSS CM55 L35 VSS VSS AK33
B24 VSS VSS BR16 CC16 VSS VSS AT52 L39 VSS VSS AK37
AA16 VSS VSS BR20 CC20 VSS VSS CM57 L44 VSS VSS AK41
B26 VSS VSS BR25 CC25 VSS VSS CM58 L48 VSS VSS AK46
B32 VSS VSS AB61 CC33 VSS VSS CM60 AE37 VSS VSS AK54
B51 VSS VSS BR37 CC46 VSS VSS CM63 M1 VSS VSS A38
B61 VSS VSS BR41 A21 VSS VSS CN1 M3 VSS VSS AL63
B63 VSS VSS BR46 AC39 VSS VSS CN13 M4 VSS VSS AM10
B B9 VSS VSS BR50 CC50 VSS VSS CN17 M61 VSS VSS AM14 B
BA4 VSS VSS BR8 CC54 VSS VSS CN4 M62 VSS VSS AM18
BA60 VSS VSS BT1 CD1 VSS VSS W52 N12 VSS VSS AM23
AA20 VSS VSS BT61 CD4 VSS VSS CN45 N20 VSS VSS AM27
BA61 VSS VSS BT62 CD62 VSS VSS CN57 N25 VSS VSS AM31
BB12 VSS VSS BU10 CE18 VSS VSS CN61 N29 VSS VSS AM35
BB16 VSS VSS AB60 CE23 VSS VSS CN63 AE46 VSS VSS AP41
BB20 VSS VSS BU14 CE27 VSS VSS CN7 N33 VSS VSS AM44
BB37 VSS VSS BU18 CE31 VSS VSS CP17 N41 VSS VSS A51
BB54 VSS VSS BU23 CE35 VSS VSS CP2 N54 VSS VSS AM48
BB8 VSS VSS BU27 AC44 VSS VSS CP21 P61 VSS VSS AM52
BC1 VSS VSS BU31 CE39 VSS VSS CP24 P62 VSS VSS BF25
BD10 VSS VSS BU35 CE48 VSS VSS CP28 P63 VSS VSS AP12
BD14 VSS VSS BU39 CE56 VSS VSS AD63 R18 VSS VSS BL29
AA25 VSS VSS BV4 CF62 VSS VSS CP3 R23 VSS VSS AP20
BD18 VSS VSS BV61 CF63 VSS VSS CP32 R27 VSS VSS AP25
BD23 VSS VSS BV62 CG14 VSS VSS CP36 R31 VSS VSS AP29
BD27 VSS VSS AC14 CG25 VSS VSS CP40 AE50 VSS VSS AP33
BD39 VSS VSS BV63 CG33 VSS VSS CP43 R35 VSS VSS BR12
BE63 VSS VSS BW12 CG41 VSS VSS CP45 R39 VSS
VSS_SENSE AP18 ANALOG_SOC_SENSE_N
BF12 VSS VSS BW16 CG46 VSS VSS CP57 R44 VSS
OUT 89
BF16 BW20 AC48 CP61 R48 VSS_X: Corner ball test pins, GND on MLB
VSS VSS VSS VSS VSS CP1
BF20 BW25 CG50 CP62 R52 VSS_1 GND 23
VSS VSS VSS VSS VSS CP63
BF33 BW29 CG8 D1 T1 VSS_2 GND 23
VSS VSS VSS VSS VSS A1
VSS_3 GND
AA29 VSS VSS BW33 CH1 VSS VSS A24 T60 VSS
VSS_4 A63 GND
23
BF37 BW37 CH3 AE12 T61 23
A BF54
VSS
VSS
VSS
VSS BW50 CH4
VSS
VSS
VSS
VSS D11 T62
VSS
VSS AD61 ANALOG_DDR_SENSE_SE
A
BF8 BY1 CH61 D15 U16 VSS_DDR_SENSE OUT 89
PAGE TITLE
VSS VSS VSS VSS VSS
BG1
BG4
VSS VSS AC18
BY60
CJ2
CJ63
VSS VSS D19
D22
AE54
U20
VSS VSS_GPU_SENSE AH27 ANALOG_GPU_SENSE_N OUT 89 SOC: Power (GND)
VSS VSS VSS VSS VSS BL35 DRAWING NUMBER SIZE
VSS_PCPU_SENSE ANALOG_PCPU_SENSE_N
BG60 VSS VSS BY61 CK1 VSS VSS D26 U25 VSS
OUT 89
051-05215 D
Apple Inc. REVISION
VSS_DDR_SENSE: Common GND for VDD_DCS_SENSE
and VDDQL_SENSE
4.6.0

21 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP/ISP I2C
AP I2C0 (Unused)
D D
AP I2C1 (Unused)
AP I2C2
33 20 7
PP1V2_IO
R2340 1 R2341 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF MASTER AP NUMBER I2C2 DIAGS NUMBER 2 SPEED 1MHz
01005 2 01005 2
ROOM=SOC ROOM=SOC
DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
12 I2C2_AP_SCL MAKE_BASE=TRUE I2C2_AP_SCL OUT 60
Top Spk Amp 1.2V 0x40 0x80, 0x81 1MHz MLB
12 I2C2_AP_SDA MAKE_BASE=TRUE I2C2_AP_SDA BI 60
C 83 55 33 29
PP1V8_IO C
R2390 1 R2391 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
MASTER AP NUMBER I2C3 DIAGS NUMBER 3 SPEED 400kHz

12 I2C3_AP_SCL_1V8 MAKE_BASE=TRUE I2C3_AP_SCL_1V8 OUT 83
12 I2C3_AP_SDA_1V8 MAKE_BASE=TRUE I2C3_AP_SDA_1V8 BI 83 Touch EEPROM 1.8V 0x51 0xA2, 0xA3 400kHz Touch Flex
Babbage (TFE) 1.8V 0x4B 0x96, 0x97 1MHz Touch Flex D52/D54 only
NOTE: For D52/D54, bus can either be mastered by SoC or Ada
Roswell 1.8V 0x10 0x20, 0x21 400kHz Touch Flex D53 only
NOTE: Roswell is I2C for D53-only (AID for D52/D54)
AP I2C4 (Legacy 1.8V)

MASTER AP NUMBER I2C4 DIAGS NUMBER 4 SPEED 400kHz
12 I2C_DISPLAY_SCL_1V8 MAKE_BASE=TRUE I2C_DISPLAY_SCL_1V8 OUT 64 82
12 I2C_DISPLAY_SDA_1V8 MAKE_BASE=TRUE I2C_DISPLAY_SDA_1V8 BI 64 82 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
MAKE_BASE for Display PMIC intentional, test feature only Display PMIC 1.8V 0x50 0xA0, 0xA1 400kHz MLB
SI2C0 NOTE: SoC is master for FCT *ONLY*, DDIC is master for normal operation
B 33 20 7 PP1V2_IO
B
1
R2310 1
R2311
4.7K 4.7K
1% 1%
1/32W 1/32W
MF MF
2 01005
ROOM=SOC
2 01005
ROOM=SOC
12 I2C0_S_SCL MAKE_BASE=TRUE I2C0_S_SCL OUT 15
12 I2C0_S_SDA MAKE_BASE=TRUE I2C0_S_SDA BI 15
ISP I2C0
10 NC_I2C0_ISP_SCL MAKE_BASE=TRUE NC_I2C0_ISP_SCL NO_TEST=1
10 NC_I2C0_ISP_SDA MAKE_BASE=TRUE NC_I2C0_ISP_SDA NO_TEST=1

A ISP I2C1 (Unused) A
PAGE TITLE
10 NC_I2C1_ISP_SCL MAKE_BASE=TRUE NC_I2C1_ISP_SCL NO_TEST=1
SOC: Aliases: I2C AP/ISP
10 NC_I2C1_ISP_SDA MAKE_BASE=TRUE NC_I2C1_ISP_SDA NO_TEST=1
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

23 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP I2C0
AOP/SMC I2C
PP1V2_S2 PP1V8_S2
33 21
PP1V2_S2 21 33 21 33 79
MASTER AOP NUMBER I2C0 DIAGS NUMBER 5 SPEED 750kHz
R2422 1 C2420 R2424 R2425 1 1

R2426 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
R2420 1
R2421 1
33.2 U2420 0.1UF 33.2 2.2K 2.2K
4.7K 4.7K 1 2 20% 1 2 5% 5% Prox 1.8V 0x58 0xB0, 0xB1 1MHz Sensor Flex
1% 1% LSF0101 2 6.3V
X5R-CERM 1/32W 1/32W
1/32W 1/32W 1% 1% MF MF
MF MF 1/32W X2SON 01005 1/32W 01005 2 01005 ALS 1.8V 0x29 0x52, 0x53 1MHz Sensor Flex
01005 2 01005 2 MF MF 2
VBIAS 6 ROOM=LVL_SENSOR ROOM=LVL_SENSOR ROOM=LVL_SENSOR
D
ROOM=SOC ROOM=SOC 01005 01005
D
ROOM=LVL_SENSOR ROOM=LVL_SENSOR Grievous 1.8V 0x33 0x66, 0x67 1MHz Sensor Flex
14
I2C0_AOP_SDA MAKE_BASE=TRUE
R2423 I2C0_AOP_SDA_R 2 SDAA SDAB
311S00233
5 I2C0_AOP_SDA_1V8_R
I2C0_AOP_SDA_1V8 I2C0_AOP_SDA_1V8 BI 79 Compass 1.8V 0x0E 0x1C, 0x1D 1MHz Sensor Flex
I2C0_AOP_SCL 1
33.2 2
CKPLUS_WAIVE=I2C_PULLUP
I2C0_AOP_SCL_R 3 SCLA 4
I2C0_AOP_SCL_1V8 MAKE_BASE=TRUE
14 MAKE_BASE=TRUE SCLB I2C0_AOP_SCL_1V8 OUT 79
CKPLUS_WAIVE=I2C_PULLUP ROOM=LVL_CHARGER MAKE_BASE=TRUE
1%
1/32W GND
MF
01005
1
AOP I2C1 ROOM=LVL_SENSOR
33 21
PP1V2_S2
R2430 1 R2431 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC MASTER AOP NUMBER I2C1 DIAGS NUMBER 6 SPEED 400kHz
14
I2C1_AOP_SCL I2C1_AOP_SCL OUT 81 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
MAKE_BASE=TRUE
14
I2C1_AOP_SDA I2C1_AOP_SDA BI 81
MAKE_BASE=TRUE
Eiger 1.2V 0x76 0xEC, 0xED 1MHz Dock
I2C1_AOP_SCL OUT 81 Arc EEPROM 1.2V 0x50 0xA0, 0xA1 1MHz Arc Flex
I2C1_AOP_SDA BI 81
Jarvis 1.2V 0x0F 0x1E, 0x1F 1MHz MLB
I2C1_AOP_SCL OUT 95 97
I2C1_AOP_SDA BI 95 97
C C
AOP I2C2
33 21
PP1V2_S2
R2440 1 R2441 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
32 14
I2C2_AOP_SCL I2C2_AOP_SCL OUT 62
MAKE_BASE=TRUE
I2C2_AOP_SDA MASTER AOP NUMBER I2C2 DIAGS NUMBER 7 SPEED 1MHz
14
MAKE_BASE=TRUE
I2C2_AOP_SDA BI 62

I2C2_AOP_SCL OUT 61
Sakonnet 1.2V 0x08 0x10, 0x11 1MHz MLB
I2C2_AOP_SDA BI 61
SMC I2C0 I2C2_AOP_SCL OUT 59

Codec 1.2V 0x4A 0x94, 0x95 1MHz MLB
Arc Amp 1.2V 0x42 0x84, 0x85 1MHz MLB

33 21 PP1V2_S2 I2C2_AOP_SDA BI 59
Bot Spk Amp 1.2V 0x40 0x80, 0x81 1MHz MLB

R2450 1 R2451 1 I2C2_AOP_SCL OUT 58
2.2K 2.2K I2C2_AOP_SDA
5% 5% BI 58
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC
MASTER SMC NUMBER I2C0 DIAGS NUMBER 8 SPEED 400kHz
14 I2C0_SMC_SCL MAKE_BASE=TRUE I2C0_SMC_SCL OUT 66
14 I2C0_SMC_SDA MAKE_BASE=TRUE I2C0_SMC_SDA BI 66 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
B CCG2B 1.2V 0x12 0x24, 0x25 1MHz MLB

B
SMC I2C1
33 21 PP1V2_S2
R2460 1 R2461 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 01005
ROOM=SOC 2 ROOM=SOC 2
90 14 I2C1_SMC_SCL MAKE_BASE=TRUE I2C1_SMC_SCL OUT 65

90 14 I2C1_SMC_SDA MAKE_BASE=TRUE I2C1_SMC_SDA BI 65

I2C1_SMC_SCL OUT 68
I2C1_SMC_SDA BI 68 Kraken 1.2V 0x1A 0x34, 0x35 1MHz MLB

I2C1_SMC_SCL OUT 67 Parrot 1.2V 0x21 0x42, 0x43 1MHz MLB
I2C1_SMC_SDA BI 67 DEVICE VOLTAGE 7-BIT ADDR 8-BIT ADDR MAX SPEED LOCATION
Gecko2 1.2V 0x52 0xA4, 0xA5 1MHz MLB
Yangtze 1.8V 0x71 0xE2, 0xE3 400kHz MLB
SMC I2C2 Veridian 1.8V 0x0B 0x16, 0x17 400kHz Battery Flex
PP1V2_S2 21 PP1V8_S2
33 21 PP1V2_S2 33 21 33 79
ROOM=LVL_CHARGER
R2474 1 C2470 R2475 R2472 1 1

R2473
R2470 1 R2471 1 33.2 U2470 0.1UF 33.2 2.2K 2.2K
4.7K 4.7K 1 2 20% 1 2 5% 5%
1% 1% LSF0101 2 6.3V
X5R-CERM 1/32W 1/32W
1/32W
MF
01005
1/32W
MF
01005
1%
1/32W
MF
X2SON 01005 1%
1/32W
MF
MF
01005 2 2
MF
01005 SYNCING: D52, D53, D54
ROOM=SOC 2 ROOM=SOC 2 6 ROOM=LVL_CHARGER
A VBIAS
A
01005 01005 ROOM=LVL_CHARGER ROOM=LVL_CHARGER
ROOM=LVL_CHARGER
14 I2C2_SMC_SDA MAKE_BASE=TRUE
R2476 I2C2_SMC_SDA_R 2 SDAA SDAB
311S00233
5 I2C2_SMC_SDA_1V8_R
I2C2_SMC_SDA_1V8 I2C2_SMC_SDA_1V8
BI 34
PAGE TITLE
I2C2_SMC_SCL 1
33.2 2
I2C2_SMC_SCL_R 3 SCLA 4
I2C2_SMC_SCL_1V8 MAKE_BASE=TRUE I2C2_SMC_SCL_1V8 SOC: Aliases: I2C AOP/SMC

14 MAKE_BASE=TRUE SCLB OUT 34
CKPLUS_WAIVE=I2C_PULLUP ROOM=LVL_CHARGER MAKE_BASE=TRUE
1% DRAWING NUMBER SIZE
1/32W GND I2C2_SMC_SDA_1V8
MF BI 71
051-05215 D
01005 I2C2_SMC_SCL_1V8 Apple Inc.
1
OUT 71
ROOM=LVL_CHARGER REVISION
4.6.0

24 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AOP GPIOs
* All AOP GPIOs tie into SCM block
AP GPIOs
AP_GPIO0 13
GPIO_BOARD_REV3 GPIO_BOARD_REV3 7
IN
SPMI0 SPI AOP_FUNC0 14 GPIO_SCM_AOP_FROM_IMU_DATARDY GPIO_SCM_AOP_FROM_IMU_DATARDY IN 96
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO1 13
IN
SPMI0 SPI AOP_FUNC1 14 GPIO_SCM_AOP_TO_IMU_SPI_CS_L GPIO_SCM_AOP_TO_IMU_SPI_CS_L OUT 96
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO2 13
IN
SPMI0 SPI AOP_FUNC2 14 GPIO_AOP_FROM_PEARL_B2B_DETECT GPIO_AOP_FROM_PEARL_B2B_DETECT IN 78
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO3 13
IN
NC_DEV_AOP_FUNC3 NC_DEV_AOP_FUNC3
D
MAKE_BASE=TRUE
D
SPMI0 SPI AOP_FUNC3 14 24
AP_GPIO4 13
GPIO_AP_CANARY1 GPIO_AP_CANARY1 97
IN
SPMI1 SPI AOP_FUNC4 GPIO_SCM_AOP_FROM_R1_INT GPIO_SCM_AOP_FROM_R1_INT MAKE_BASE=TRUE
14
MAKE_BASE=TRUE
IN 98
GPIO_AP_CANARY2
AP_GPIO5 13 GPIO_AP_CANARY2 IN 95 97
SPMI1 SPI AOP_FUNC5 14 GPIO_AOP_TO_R1_COREDUMP_TRIGGER GPIO_AOP_TO_R1_COREDUMP_TRIGGER OUT 98

MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO6 13
GPIO_AP_BI_CCG2B_SWDIO GPIO_AP_BI_CCG2B_SWDIO 66 89
BI
SPMI1 SPI AOP_FUNC6 14 GPIO_AOP_TO_R1_TIME_SYNC_L GPIO_AOP_TO_R1_TIME_SYNC_L OUT 98
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO7 13
GPIO_AP_TO_CCG2B_SWCLK GPIO_AP_TO_CCG2B_SWCLK 66 89
OUT
SPMI1 SPI AOP_FUNC7 14 GPIO_AOP_TO_CODEC_RESET_L GPIO_AOP_TO_CODEC_RESET_L OUT 58 89
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO8 13
GPIO_AP_FROM_DISPLAY_PANEL_ID GPIO_AP_FROM_DISPLAY_PANEL_ID 82
IN
SPI AOP_FUNC8 14 GPIO_AOP_TO_BB_FORCE_PWM GPIO_AOP_TO_BB_FORCE_PWM OUT 93
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO9 13
GPIO_AP_FROM_WLAN_TIME_SYNC GPIO_AP_FROM_WLAN_TIME_SYNC 93
IN
SPI AOP_FUNC9 14 GPIO_AOP_FROM_IRCAM_B2B_DETECT GPIO_AOP_FROM_IRCAM_B2B_DETECT IN 77
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO10 13
GPIO_AP_TO_BB_PEAK_PWR_IND GPIO_AP_TO_BB_PEAK_PWR_IND 93
OUT
SPI AOP_FUNC10 14 GPIO_SCM_AOP_TO_R1_SPI_CS_L GPIO_SCM_AOP_TO_R1_SPI_CS_L OUT 98
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO11 13
GPIO_AP_TO_BB_COREDUMP GPIO_AP_TO_BB_COREDUMP 95
OUT
SPI AOP_FUNC11 14 NC_AOP_FUNC11 NC_AOP_FUNC11 23
MAKE_BASE=TRUE
AP_GPIO12 13
GPIO_AP_FROM_BB_RESET_DETECT_L GPIO_AP_FROM_BB_RESET_DETECT_L 93
IN
I2C0 SPI AOP_FUNC12 14 GPIO_AOP_TO_ALS_COEX GPIO_AOP_TO_ALS_COEX OUT 79
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO13 13
GPIO_AP_FROM_CODEC_INT_L GPIO_AP_FROM_CODEC_INT_L 58 89
IN
I2C0 SPI AOP_FUNC13 14 GPIO_AOP_TO_NFC_IRONMAN_EN GPIO_AOP_TO_NFC_IRONMAN_EN OUT 99
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO14 13
NC_AP_GPIO14 NC_AP_GPIO14 23
I2C0 SPI AOP_FUNC14 14 GPIO_AOP_FROM_TOUCH_CTS GPIO_AOP_FROM_TOUCH_CTS IN 24 83
AP_GPIO15 13
GPIO_AP_TO_SPKRAMP_TOP_RESET_L GPIO_AP_TO_SPKRAMP_TOP_RESET_L 60
OUT
I2C1, I2C0 SPI AOP_FUNC15 14 GPIO_SCM_AOP_BI_PROX_INT_L GPIO_SCM_AOP_BI_PROX_INT_L IN 70
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_GPIO16 13
GPIO_AP_FROM_BT_AUDIO_SYNC GPIO_AP_FROM_BT_AUDIO_SYNC 93
IN
I2C1 I2C0 AOP_FUNC16 GPIO_SCM_AOP_FROM_ALS_INT_L GPIO_SCM_AOP_FROM_ALS_INT_L MAKE_BASE=TRUE
C
14 IN 79
C GPIO_AP_TO_AMUX_PMU_SYNC
MAKE_BASE=TRUE
AP_GPIO17 13 GPIO_AP_TO_AMUX_PMU_SYNC OUT 24
I2C1 I2C0 AOP_FUNC17 14 GPIO_SCM_AOP_FROM_EIGER_INT_L GPIO_SCM_AOP_FROM_EIGER_INT_L IN 81

MAKE_BASE=TRUE
AP_GPIO18 13
NC_DEV_AP_GPIO18 NC_DEV_AP_GPIO18 24
I2C1 I2C0 AOP_FUNC18 14 GPIO_SCM_AOP_FROM_COMPASS_INT GPIO_SCM_AOP_FROM_COMPASS_INT IN 70

MAKE_BASE=TRUE
AP_GPIO19 13
I2C1 AOP_FUNC19 14 GPIO_SCM_AOP_FROM_JARVIS_INT GPIO_SCM_AOP_FROM_JARVIS_INT IN 89 95 Great Dane

MAKE_BASE=TRUE
AP_GPIO20 13
I2C1 AOP_FUNC20 14 GPIO_AOP_FROM_TOUCH_INT_L GPIO_AOP_FROM_TOUCH_INT_L IN 83

MAKE_BASE=TRUE
AP_GPIO21 13
I2C1 AOP_FUNC21 14 NC_AOP_FUNC21 NC_AOP_FUNC21 23
AP_GPIO22 13
I2C1 AOP_FUNC22 14 NC_DEV_AOP_FUNC22 NC_DEV_AOP_FUNC22 24
AP_GPIO23 13
AP_GPIO24 13
AP_GPIO25 13
GPIO_AP_TO_BB_TIME_MARK GPIO_AP_TO_BB_TIME_MARK 93
OUT
MAKE_BASE=TRUE
AP_GPIO26 13
B B

A A
PAGE TITLE
SOC: Aliases: GPIOs

DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

25 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Misc. SoC Aliases 65

UART: KRAKEN
UART0_AP_TO_KRAKEN_DEBUG_TXD UART0_AP_TO_KRAKEN_DEBUG_TXD
MAKE_BASE=TRUE
12 89 SOC: PCIe
65 UART0_AP_FROM_KRAKEN_DEBUG_RXD UART0_AP_FROM_KRAKEN_DEBUG_RXD 12 89 9
NC_DEV_PCIE_GP0_AP_CLKREQ_L NC_DEV_PCIE_GP0_AP_CLKREQ_L
MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=1
65 UART4_AP_TO_KRAKEN_ACC_TXD UART4_AP_TO_KRAKEN_ACC_TXD 12 89 9 NC_DEV_PCIE_GP0_AP_REFCLK_P NC_DEV_PCIE_GP0_AP_REFCLK_P

65 UART4_AP_FROM_KRAKEN_ACC_RXD UART4_AP_FROM_KRAKEN_ACC_RXD NO_TEST=1
MAKE_BASE=TRUE
12 89
9 NC_DEV_PCIE_GP0_AP_REFCLK_N NC_DEV_PCIE_GP0_AP_REFCLK_N
NAND + USB & MISC
MAKE_BASE=TRUE
NO_TEST=1
NC_DEV_PCIE_GP0_AP_RX_P
DISPLAY 9 NC_DEV_PCIE_GP0_AP_RX_P
D
MAKE_BASE=TRUE
D PP1V2_IO NO_TEST=1
8 PP1V2_IO NC_DEV_PCIE_GP0_AP_RX_N
MAKE_BASE=TRUE
23 29 33
9 NC_DEV_PCIE_GP0_AP_RX_N
8 PP1V2_IO MAKE_BASE=TRUE
NO_TEST=1
9
NC_DEV_PCIE_GP0_AP_TX_P NC_DEV_PCIE_GP0_AP_TX_P
MAKE_BASE=TRUE
NO_TEST=1
9
NC_DEV_PCIE_GP0_AP_TX_N NC_DEV_PCIE_GP0_AP_TX_N
MAKE_BASE=TRUE
87 8 IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU NC_DEV_PCIE_GP0_AP_RESET_L

NO_TEST=1
MAKE_BASE=TRUE
30
9 NC_DEV_PCIE_GP0_AP_RESET_L
MAKE_BASE=TRUE
IO_SOC_FROM_PMU_KRAKEN_FORCE_DFU 65 NO_TEST=1
8 NC_DEV_AP_TMR32_PWM0 NC_DEV_AP_TMR32_PWM0
MAKE_BASE=TRUE
SOC: Serial
NO_TEST=1
NC_UART1_AP_CTS_L NC_UART1_AP_CTS_L
8 NC_DEV_AP_TMR32_PWM1 NC_DEV_AP_TMR32_PWM1 12
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1 12
NC_UART1_AP_RTS_L NC_UART1_AP_RTS_L NO_TEST=1
8 NC_DEV_AP_TMR32_PWM2 NC_DEV_AP_TMR32_PWM2 NC_UART1_AP_RXD

MAKE_BASE=TRUE
MAKE_BASE=TRUE 12 NC_UART1_AP_RXD NO_TEST=1
NO_TEST=1 MAKE_BASE=TRUE
11 NC_SOC_DWI_CLK NC_SOC_DWI_CLK NC_UART1_AP_TXD
8 NC_DEV_PAD_MTR_VREF_P NC_DEV_PAD_MTR_VREF_P MAKE_BASE=TRUE 12 NC_UART1_AP_TXD NO_TEST=1
MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE

11 NC_SOC_DWI_DATA NC_SOC_DWI_DATA NC_UART2_AP_CTS_L
NO_TEST=1
NC_UART2_AP_CTS_L NO_TEST=1
8 NC_DEV_PAD_MTR_VREF_N NC_DEV_PAD_MTR_VREF_N MAKE_BASE=TRUE

NO_TEST=1
12
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1 12
NC_UART2_AP_RTS_L NC_UART2_AP_RTS_L NO_TEST=1
11 NC_TOUCH_BSYNC1_DISP NC_TOUCH_BSYNC1_DISP MAKE_BASE=TRUE
MAKE_BASE=TRUE 12
NC_UART2_AP_RXD NC_UART2_AP_RXD NO_TEST=1
PP1V2_IO PP1V2_IO 11 NC_EDP_HPD_DISP NC_EDP_HPD_DISP NO_TEST=1 MAKE_BASE=TRUE

8
MAKE_BASE=TRUE
23 29 33
MAKE_BASE=TRUE 12
NC_UART2_AP_TXD NC_UART2_AP_TXD NO_TEST=1
11 NC_SOC_DISP_I2C_SCL NC_SOC_DISP_I2C_SCL NC_UART3_AP_CTS_L
MAKE_BASE=TRUE 12 NC_UART3_AP_CTS_L NO_TEST=1
11 NC_SOC_DISP_I2C_SDA NC_SOC_DISP_I2C_SDA
87 30 IO_PMU_TO_SYSTEM_RESET_L IO_PMU_TO_SYSTEM_RESET_L 8 MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
MAKE_BASE=TRUE
11 NC_SOC_DISP_POL NC_SOC_DISP_POL NC_UART3_AP_RXD
C
IO_PMU_TO_SYSTEM_RESET_L 14
11 NC_SOC_DISP_AGPIO NC_SOC_DISP_AGPIO
MAKE_BASE=TRUE
NO_TEST=1
12 NC_UART3_AP_RXD
MAKE_BASE=TRUE C
IO_PMU_TO_SYSTEM_RESET_L 14 MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
11 NC_SOC_DISP_EXT_HPD NC_SOC_DISP_EXT_HPD NC_I2S1_AP_MCLK
MAKE_BASE=TRUE 12 NC_I2S1_AP_MCLK
11 NC_SOC_DISP_TOUCH_EB NC_SOC_DISP_TOUCH_EB
22 NC_AP_GPIO14 NC_AP_GPIO14 NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER0 MAKE_BASE=TRUE NC_DEV_SOC_THROTTLE_TRIGGER0 8

MAKE_BASE=TRUE
NO_TEST=1 NO_TEST=1
NC_DEV_PMU_CPU_TRIGGER0 MAKE_BASE=TRUE NC_DEV_PMU_CPU_TRIGGER0 30

11 NC_DEV_LPDP_AP_TX0P NC_DEV_LPDP_AP_TX0P
NO_TEST=1
11 NC_DEV_LPDP_AP_TX0N NC_DEV_LPDP_AP_TX0N MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
11 NC_DEV_LPDP_AP_TX1P NC_DEV_LPDP_AP_TX1P
89 IO_AP_FROM_PMU_SW_SHDN_L IO_AP_FROM_PMU_SW_SHDN_L NC_DEV_LPDP_AP_TX1N
8
11 NC_DEV_LPDP_AP_TX1N MAKE_BASE=TRUE
NC_I2S2_AP_MCLK
MAKE_BASE=TRUE NO_TEST=1
NC_I2S2_AP_MCLK
IO_AP_FROM_PMU_SW_SHDN_L NC_DEV_LPDP_AP_TX2P
MAKE_BASE=TRUE
NO_TEST=1
12
30
11 NC_DEV_LPDP_AP_TX2P NC_SSPI0_MISO_AP
MAKE_BASE=TRUE
NC_DEV_LPDP_AP_TX2N NC_SSPI0_MISO_AP NO_TEST=1
89 IO_AP_FROM_PMU_PRE_UVLO_L IO_AP_FROM_PMU_PRE_UVLO_L 8
11 NC_DEV_LPDP_AP_TX2N MAKE_BASE=TRUE
NO_TEST=1
12
MAKE_BASE=TRUE
NC_SSPI0_SCLK_AP NC_SSPI0_SCLK_AP NO_TEST=1
IO_AP_FROM_PMU_PRE_UVLO_L 30
11 NC_DEV_LPDP_AP_TX3P NC_DEV_LPDP_AP_TX3P NO_TEST=1 12
MAKE_BASE=TRUE
11 NC_DEV_LPDP_AP_TX3N NC_DEV_LPDP_AP_TX3N MAKE_BASE=TRUE
NO_TEST=1 12
NC_SSPI0_MOSI_AP NC_SSPI0_MOSI_AP NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER3 MAKE_BASE=TRUE NC_DEV_SOC_THROTTLE_TRIGGER3 8

11 NC_DEV_LPDP_AP_AUXP NC_DEV_LPDP_AP_AUXP NO_TEST=1
12 NC_UART6_AP_RXD_1V8 NC_UART6_AP_RXD_1V8 NO_TEST=1
NO_TEST=1
11 NC_DEV_LPDP_AP_AUXN NC_DEV_LPDP_AP_AUXN MAKE_BASE=TRUE MAKE_BASE=TRUE
NC_DEV_PMU_GPU_TRIGGER0 MAKE_BASE=TRUE NC_DEV_PMU_GPU_TRIGGER0 30

NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
11 NC_DEV_LPDP_AP_RCALP NC_DEV_LPDP_AP_RCALP NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER4 MAKE_BASE=TRUE
NO_TEST=1
NC_DEV_SOC_THROTTLE_TRIGGER4 8
11 NC_DEV_LPDP_AP_RCALN NC_DEV_LPDP_AP_RCALN MAKE_BASE=TRUE
NO_TEST=1 SOC: AOP
NC_DEV_PMU_GPU_TRIGGER1 MAKE_BASE=TRUE NC_DEV_PMU_GPU_TRIGGER1 30
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
IO_SOC_TO_PMU_SOCHOT_RESET_L IO_SOC_TO_PMU_SOCHOT_RESET_L 14 GPIO_AOP_TO_WLAN_CONTEXT_A GPIO_AOP_TO_WLAN_CONTEXT_A

89 8
MAKE_BASE=TRUE
30
11 NC_LPDP_EXT_AP_TX0_P NC_LPDP_EXT_AP_TX0_P MAKE_BASE=TRUE
93
89 8 CLK_AP_TO_PMU_TST_CLKOUT CLK_AP_TO_PMU_TST_CLKOUT 30 11 NC_LPDP_EXT_AP_TX0_N NC_LPDP_EXT_AP_TX0_N MAKE_BASE=TRUE

NO_TEST=1 14 GPIO_AOP_TO_WLAN_CONTEXT_B GPIO_AOP_TO_WLAN_CONTEXT_B 93
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
AMUX_SOC_TO_PMU_AMUX_OUT AMUX_SOC_TO_PMU_AMUX_OUT NC_LPDP_EXT_AP_TX1_P NC_LPDP_EXT_AP_TX1_P NO_TEST=1

NC_AOP_FUNC11 NC_AOP_FUNC11
B B
8 30 11 22
MAKE_BASE=TRUE
11 NC_LPDP_EXT_AP_TX1_N NC_LPDP_EXT_AP_TX1_N MAKE_BASE=TRUE MAKE_BASE=TRUE
14 GND NO_TEST=1
MAKE_BASE=TRUE 22 NC_AOP_FUNC21 NC_AOP_FUNC21 NO_TEST=1
11 NC_LPDP_EXT_AP_TX2_P NC_LPDP_EXT_AP_TX2_P NO_TEST=1 MAKE_BASE=TRUE
8 GND NO_TEST=1
11 NC_LPDP_EXT_AP_TX2_N NC_LPDP_EXT_AP_TX2_N MAKE_BASE=TRUE

NO_TEST=1
GND MAKE_BASE=TRUE
NUB
8
11 NC_LPDP_EXT_AP_TX3_P NC_LPDP_EXT_AP_TX3_P NO_TEST=1
11 NC_LPDP_EXT_AP_TX3_N NC_LPDP_EXT_AP_TX3_N MAKE_BASE=TRUE

NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 14 NC_NUB_GPIO5 NC_NUB_GPIO5
89 14 IO_AON_TO_AP_XTAL_CFSB IO_AON_TO_AP_XTAL_CFSB 8 11 NC_LPDP_EXT_AP_AUX_P NC_LPDP_EXT_AP_AUX_P MAKE_BASE=TRUE
MAKE_BASE=TRUE
CKPLUS_WAIVE=SINGLE_COMP_NET 11 NC_LPDP_EXT_AP_AUX_N NC_LPDP_EXT_AP_AUX_N MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1 14 GND
11 NC_LPDP_EXT_AP_RCAL_P NC_LPDP_EXT_AP_RCAL_P
NC_DEV_JTAG_TDI NC_DEV_JTAG_TDI
11 NC_LPDP_EXT_AP_RCAL_N NC_LPDP_EXT_AP_RCAL_N MAKE_BASE=TRUE 14
90_EUSB_DBG_PARROT_BI_AP_N 90_EUSB_DBG_PARROT_BI_AP_N NO_TEST=1 MAKE_BASE=TRUE

89 68 MAKE_BASE=TRUE 14 MAKE_BASE=TRUE
NC_DEV_JTAG_TDO NC_DEV_JTAG_TDO NO_TEST=1
89 68 90_EUSB_DBG_PARROT_BI_AP_P MAKE_BASE=TRUE 90_EUSB_DBG_PARROT_BI_AP_P 14

NO_TEST=1 14
MAKE_BASE=TRUE
ISP NC_DEV_JTAG_TRST_L NC_DEV_JTAG_TRST_L NO_TEST=1

14
12 NC_SOC_S_GPIO1 NC_SOC_S_GPIO1 MAKE_BASE=TRUE
MAKE_BASE=TRUE 14 PP1V2_S2 PP1V2_S2 NO_TEST=1

29 33 67 77 78 82 83 96 97 99
NO_TEST=1
10 NC_ISP_GPIO_1 NC_ISP_GPIO_1 MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=1
10 NC_ISP_GPIO_2 NC_ISP_GPIO_2 89 14 SWD_NUB_TO_PMU_TOUCH_SWCLK SWD_NUB_TO_PMU_TOUCH_SWCLK 30

NO_TEST=1
10 NC_SENSOR2_CLK_AP NC_SENSOR2_CLK_AP
MAKE_BASE=TRUE
NO_TEST=1
NC_SENSOR3_CLK_AP NC_SENSOR3_CLK_AP
VSS CORNER BALLS
10
MAKE_BASE=TRUE
NO_TEST=1

A
19 GND SPI (AP) A
19 GND
12 SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2 SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2 7 25 89
19 GND PAGE TITLE
19 GND 12
12
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0
SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1 MAKE_BASE=TRUE
SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 MAKE_BASE=TRUE
7 25
7 25
SOC: Aliases: Misc
MAKE_BASE=TRUE DRAWING NUMBER SIZE
SPI3_AP_FROM_CODEC_MISO 051-05215 D
12
SPI3_AP_TO_CODEC_MOSI
SPI3_AP_FROM_CODEC_MISO 58 89 Apple Inc. REVISION
12 SPI3_AP_TO_CODEC_MOSI MAKE_BASE=TRUE
12 SPI3_AP_TO_CODEC_SCLK SPI3_AP_TO_CODEC_SCLK MAKE_BASE=TRUE

58 89
58
4.6.0
12 SPI3_AP_TO_CODEC_CS_L SPI3_AP_TO_CODEC_CS_L MAKE_BASE=TRUE
58 89
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
26 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
12 NC_AP_SPMI2_SCLK NC_AP_SPMI2_SCLK
MAKE_BASE=TRUE
12 NC_AP_SPMI2_SDATA NC_AP_SPMI2_SDATA NO_TEST=1
MAKE_BASE=TRUE
NC_I2C0_AP_SCL NC_I2C0_AP_SCL NO_TEST=1
C2700
12
2 0.22UF
1 MAKE_BASE=TRUE
10% 6.3V NC_I2C0_AP_SDA NC_I2C0_AP_SDA NO_TEST=1
9 OUT
90_PCIE_ST0_AP_FROM_NAND_C_RX_P CER-X5R 01005 90_PCIE_ST0_AP_FROM_NAND_RX_P IN 25
12
MAKE_BASE=TRUE
90_PCIE_ST0_AP_FROM_NAND_C_RX_N ROOM=SOC
90_PCIE_ST0_AP_FROM_NAND_RX_N NC_I2C1_AP_SCL NC_I2C1_AP_SCL NO_TEST=1
C2701
9 OUT IN 25 12
2 0.22UF
1 MAKE_BASE=TRUE
10% 6.3V 12 NC_I2C1_AP_SDA NC_I2C1_AP_SDA NO_TEST=1
CER-X5R 01005 MAKE_BASE=TRUE

ROOM=SOC NO_TEST=1
90_PCIE_GP2_AP_FROM_BB_RX_P 90_PCIE_GP2_AP_FROM_BB_RX_P
D
9 OUT IN 95
D 90_PCIE_GP2_AP_FROM_BB_RX_N 90_PCIE_GP2_AP_FROM_BB_RX_N
MAKE_BASE=TRUE
9 OUT IN 95
MAKE_BASE=TRUE
C2710 2 0.1UF
1
20% 6.3V
95 IN
90_PCIE_GP1_AP_FROM_WLAN_RX_P X5R-CERM 01005 90_PCIE_GP1_AP_FROM_WLAN_C_RX_P OUT 9
90_PCIE_GP1_AP_FROM_WLAN_RX_N ROOM=SOC
90_PCIE_GP1_AP_FROM_WLAN_C_RX_N
C2711
95 IN OUT 9
2 0.1UF
1 22 NC_DEV_AOP_FUNC22 NC_DEV_AOP_FUNC22
20% 6.3V MAKE_BASE=TRUE
X5R-CERM 01005
ROOM=SOC
22 NC_DEV_AOP_FUNC3 NC_DEV_AOP_FUNC3
DISPLAY
MAKE_BASE=TRUE
NO_TEST=1
83 24 22 GPIO_AOP_FROM_TOUCH_CTS GPIO_AOP_FROM_TOUCH_CTS 22 24 83
MAKE_BASE=TRUE
11 90_MIPI_AP_TO_DISPLAY_CLK_P 90_MIPI_AP_TO_DISPLAY_CLK_P 82
11 90_MIPI_AP_TO_DISPLAY_CLK_N 90_MIPI_AP_TO_DISPLAY_CLK_N MAKE_BASE=TRUE
MAKE_BASE=TRUE
82
22 GPIO_AP_TO_AMUX_PMU_SYNC GPIO_AP_TO_AMUX_PMU_SYNC 30 89
MAKE_BASE=TRUE
11 90_MIPI_AP_TO_DISPLAY_D0_P 90_MIPI_AP_TO_DISPLAY_D0_P 82
11 90_MIPI_AP_TO_DISPLAY_D0_N 90_MIPI_AP_TO_DISPLAY_D0_N MAKE_BASE=TRUE

82
MAKE_BASE=TRUE

NC_DEV_AP_GPIO18
MAKE_BASE=TRUE
82
22 NC_DEV_AP_GPIO18
11 NC_MIPI_AP_TO_DISPLAY_D2_P NC_MIPI_AP_TO_DISPLAY_D2_P NC_DEV_AP_GPIO19
MAKE_BASE=TRUE
NO_TEST=1
NC_DEV_AP_GPIO19
11 NC_MIPI_AP_TO_DISPLAY_D2_N NC_MIPI_AP_TO_DISPLAY_D2_N
MAKE_BASE=TRUE
NO_TEST=1
22
MAKE_BASE=TRUE
MAKE_BASE=TRUE NC_DEV_AP_GPIO20 NC_DEV_AP_GPIO20
22
MAKE_BASE=TRUE

82 22
NC_DEV_AP_GPIO21 NC_DEV_AP_GPIO21
NC_DEV_AP_GPIO22 NC_DEV_AP_GPIO22 NO_TEST=1
LPDP
22
MAKE_BASE=TRUE
22
C
MAKE_BASE=TRUE
C 22
MAKE_BASE=TRUE
ISP: LPDP Lanes 22

MAKE_BASE=TRUE
NO_TEST=1
10 90_LPDP_ISP_FROM_FCAM_RX_D1_N CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_FCAM_RX_D1_N 76
SPI (AP)
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_FCAM_RX_D1_P CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_FCAM_RX_D1_P 76
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_FCAM_RX_D0_N CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_FCAM_RX_D0_N 76
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_FCAM_RX_D0_P 90_LPDP_ISP_FROM_FCAM_RX_D0_P
CKPLUS_WAIVE=DIFFPAIR_BADTERM
MAKE_BASE=TRUE
76
12 SPI1_AP_FROM_TOUCH_MISO_1V8 SPI1_AP_FROM_TOUCH_MISO_1V8 83
10 90_LPDP_ISP_FROM_WIDE_RX_D2_P 90_LPDP_ISP_FROM_WIDE_RX_D2_P 74 12 SPI1_AP_TO_TOUCH_MOSI_1V8 SPI1_AP_TO_TOUCH_MOSI_1V8 MAKE_BASE=TRUE

83
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_WIDE_RX_D2_N 90_LPDP_ISP_FROM_WIDE_RX_D2_N 74 12 SPI1_AP_TO_TOUCH_SCLK_1V8 SPI1_AP_TO_TOUCH_SCLK_1V8 MAKE_BASE=TRUE
83
MAKE_BASE=TRUE
12 SPI1_AP_TO_TOUCH_CS_L_1V8 SPI1_AP_TO_TOUCH_CS_L_1V8 MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_WIDE_RX_D1_N CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_WIDE_RX_D1_N 74 MAKE_BASE=TRUE

83
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_WIDE_RX_D1_P CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_WIDE_RX_D1_P 74 12 NC_SPI2_MISO_AP NC_SPI2_MISO_AP NO_TEST=1
MAKE_BASE=TRUE
12 NC_SPI2_MOSI_AP NC_SPI2_MOSI_AP MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_WIDE_RX_D0_N 90_LPDP_ISP_FROM_WIDE_RX_D0_N NO_TEST=1

MAKE_BASE=TRUE
74
NC_SPI2_SCLK_AP NC_SPI2_SCLK_AP MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_WIDE_RX_D0_P 90_LPDP_ISP_FROM_WIDE_RX_D0_P 12 NO_TEST=1

MAKE_BASE=TRUE
74
12 NC_SPI2_SCLK_AP MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D2_N CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D2_N 74 12 NC_SPI2_CS_L_AP NC_SPI2_CS_L_AP NO_TEST=1

MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D2_P CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D2_P 74
MAKE_BASE=TRUE
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D0_P 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D0_P 74
Ada 24MHz clock (not used for DITO)

MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D0_N 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D0_N 74
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D1_N CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D1_N 74
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D1_P CKPLUS_WAIVE=DIFFPAIR_BADTERM 90_LPDP_ISP_FROM_SUPERFLEX_CAM2_RX_D1_P 74 14 NC_CLK_NUB_TO_TOUCH_24M NC_CLK_NUB_TO_TOUCH_24M NO_TEST=1
10 90_LPDP_ISP_FROM_JASPER_RX_D0_P 90_LPDP_ISP_FROM_JASPER_RX_D0_P 75 14 NC_CLK_NUB_TO_TOUCH_24M

MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_JASPER_RX_D0_N 90_LPDP_ISP_FROM_JASPER_RX_D0_N 75
MAKE_BASE=TRUE
B 10
10
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D0_P
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D0_N MAKE_BASE=TRUE
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D0_N
73
73
Hacky NO_TEST fix B
MAKE_BASE=TRUE
NC_CAM_PMU2_BUCK0 NC_CAM_PMU2_BUCK0
10 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D1_P 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D1_P 73
51 NO_TEST=1
MAKE_BASE=TRUE
51
MAKE_BASE=TRUE
10 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D1_N 90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D1_N 73
MAKE_BASE=TRUE
10
10
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D2_N MAKE_BASE=TRUE
90_LPDP_ISP_FROM_SINGLEFLEX_CAM_RX_D2_N
73
73
Extra Canary
MAKE_BASE=TRUE
12
GPIO_AP_CANARY6 GPIO_AP_CANARY6 93 97
ISP: LPDP Aux 12

GPIO_AP_CANARY5 GPIO_AP_CANARY5
MAKE_BASE=TRUE
93 97
10 NC_LPDP_ISP_AUX_RX_D0P NC_LPDP_ISP_AUX_RX_D0P MAKE_BASE=TRUE
MAKE_BASE=TRUE 11 GPIO_AP_CANARY3 GPIO_AP_CANARY3 93 97

NC_LPDP_ISP_AUX_RX_D1P GPIO_AOP_CANARY7 GPIO_AOP_CANARY7

10 NC_LPDP_ISP_AUX_RX_D1P 14
MAKE_BASE=TRUE
94 97
MAKE_BASE=TRUE
NO_TEST=1 11 GPIO_AP_CANARY4 GPIO_AP_CANARY4 95 97
MAKE_BASE=TRUE
10 LPDP_ISP_BI_SUPERFLEX_CAM2_AUX_RX_D2P LPDP_ISP_BI_SUPERFLEX_CAM2_AUX_RX_D2P 74
MAKE_BASE=TRUE
10
NC_LPDP_ISP_AUX_RX_D3P NC_LPDP_ISP_AUX_RX_D3P
MAKE_BASE=TRUE
NO_TEST=1
10
MAKE_BASE=TRUE
NO_TEST=1
10 LPDP_ISP_BI_SINGLEFLEX_CAM_AUX_RX_D5P LPDP_ISP_BI_SINGLEFLEX_CAM_AUX_RX_D5P 73
MAKE_BASE=TRUE
10
MAKE_BASE=TRUE
A NC_LPDP_ISP_AUX_RX_D7P
NO_TEST=1
NC_LPDP_ISP_AUX_RX_D7P
A
10
PAGE TITLE
MAKE_BASE=TRUE
NO_TEST=1
SOC: Aliases: FF-Specific
10
NC_LPDP_ISP_AUX_RX_D8P NC_LPDP_ISP_AUX_RX_D8P DRAWING NUMBER SIZE
MAKE_BASE=TRUE
051-05215 D
Apple Inc.
NO_TEST=1
REVISION
10
MAKE_BASE=TRUE
NO_TEST=1
4.6.0
10
NC_LPDP_ISP_AUX_RX_D10P NC_LPDP_ISP_AUX_RX_D10P THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE INC.
NO_TEST=1 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10
27 OF 160
MAKE_BASE=TRUE SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5E NAND SUBSYSTEM SPECIFIC BOM TABLES

ZQ Resistor
TABLE_5_HEAD

TABLE_5_ITEM
I_VCC = 1150mA MAX (1us PEAK POWER) 118S0784 1 RES,300OHM,1%,1/32W,01005 R2901 CRITICAL S5E
29 PP2V625_NAND
Note: Dev Board adds an S4E option
1 C2913 1 C2916 1 C2919 1 C2921 1 C2949 1 C2950 1 C2951 1 C2952 1 C2953 1 C2954
15UF 15UF 15UF 15UF 2.2UF 2.2UF 2.2UF 2.2UF 330PF 330PF
20% 20% 20% 20% 20% 20% 20% 20% 10% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 16V 2 16V
D
X5R
0402-0.1MM-1
ROOM=NAND
X5R
0402-0.1MM-1
ROOM=NAND
X5R
0402-0.1MM-1
ROOM=NAND
X5R
0402-0.1MM-1
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
X5R-CERM
0201
ROOM=NAND
CER-X7R
01005
ROOM=NAND
CER-X7R
01005
ROOM=NAND
D
1 C2936 1 C2937 1 C2934 1 C2938 1 C2935 1 C2939

220PF 220PF 47PF 47PF 22PF 22PF
5% 5% 5% 5% 5% 5%
2 25V 2 25V 2 16V 16V
2 NP0-C0G 2 16V 2 16V
COG
01005
COG
01005
NP0-C0G
01005 01005
C0G
01005
C0G
01005 U2900
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND H23BFG8127AEQ-BC NOTES:
LGA
SYM 2 OF 2 INT PU = internal pull up to VDDIO_1
D3 A12 INT PD = internal pull down to VSS
E12 A2 Internal pulls are 40kOhm (min), 80kOhm (typ), 165kOhm (max)
G4 B1
VCC
L12 B13
R2
335S00436
C12 U2900
C2 H23BFG8127AEQ-BC
D1 LGA
SYM 1 OF 2
I_VDDIO1 (@ 1.2V) = 72mA MAX D13
ROOM=NAND CLK_AP_TO_NAND_24M M3 CLK_IN (INT PU)EXT_D0/BOOT0 B3 GPIO_PMU_TO_NAND_LOW_BATT_BOOT_L
PP1V2_IO F1 8 IN IN 32 89
33 26
(INT PD) EXT_D1/BOOT1 C4 IO_AP_TO_NAND_FW_STRAP
F11 L4 IN 8 89
1 C2941 1 C2924 1 C2926 1 C2910 1 C2911 1 C2955 J2 F13
89 8 IN
IO_AP_TO_NAND_RESET_L RESET*
EXT_D2/BOOT2/SPINAND_SCLK/SPI_SCLK B5 SPI0_AP_TO_S5E_SCLK_BOOT_CONFIG0 IN 7 23
2.2UF 2.2UF 2.2UF 0.1UF 220PF 220PF OMIT_TABLE GND G10 TRST* (INT PD) EXT_D3/SPINAND_MISO/SPI_MISO/SWD_UID C6 SPI0_AP_FROM_S5E_MISO_BOOT_CONFIG2
20% 20% 20% 20% 5% 5% K9 F7 26 OUT 7 23 89
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 25V 2 25V VDDIO_1 EXT_D4/SPI_CS B7 GND

X5R-CERM X5R-CERM X5R-CERM X5R-CERM COG COG T5 F9 335S00436
26
0201 0201 0201 01005 01005 01005 EXT_D5/SPINAND_MOSI/SPI_MOSI/SWD_UID1 C8 SPI0_AP_TO_S5E_MOSI_BOOT_CONFIG1
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND H1 IN 7 23
90_PCIE_ST0_AP_TO_NAND_REFCLK_P K11 PCIE_REFCLK_P EXT_D6/BOOT3 B9 GND

H11 89 9 IN 26
90_PCIE_ST0_AP_TO_NAND_REFCLK_N J12 PCIE_REFCLK_N EXT_D7/SPF_N B11 IO_PMU_TO_NAND_SYSTEM_ALIVE

H13 89 9 IN
ROOM=NAND IN 30 89
C FL2925
10-OHM-1.1A
H3
H5
9 BI
PCIE_ST0_AP_BI_NAND_CLKREQ_L P5 PCIE_CLKREQ* (INT PU) EXT_DQS/BCM_N D11 NC_DEV_NAND_BCM_L 26 C
(VCCQ_IO)
2 1 PP_NAND_VDDIO1_F J6 PCIE_AVDD_H H9 OMIT_TABLE
VOLTAGE=1.8 J10 M11 D7
C2956 C2957 C2958 C2925 90_PCIE_ST0_AP_TO_NAND_TX_P PCIE_RX0_P EXT_NRE/JTAG_TMS SWD_AP_BI_NAND_SWDIO
01005 (INT PU)
1 1 1 ROOM=NAND 1 9 IN BI 8 89
155S0876 K1 90_PCIE_ST0_AP_TO_NAND_TX_N N12 PCIE_RX0_N

330PF 47PF 22PF 2.2UF 9 IN
(INT PU) EXT_NWE/JTAG_TCK E6 SWD_AP_TO_MANY_SWCLK
10% 5% 5% 20% VSS K13 IN 8 95 98
2 16V
CER-X7R
16V
2 NP0-C0G 2 16V
C0G 2 6.3V
X5R-CERM K5 E4
EXT_RNB/JTAG_TDO GND
R2963
01005 01005 01005 0201 26
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND K7

2.0 90_PCIE_ST0_AP_FROM_NAND_RX_P R12 PCIE_TX0_P (INT PU) EXT_CLE/JTAG_TDI D5 NC_DEV_NAND_JTAG_TDI
2 1 PP_NAND_VDDIO1_R L2 AVDD1X_PLL L10 24 OUT 26
VOLTAGE=1.8 90_PCIE_ST0_AP_FROM_NAND_RX_N T11 PCIE_TX0_N

M1 24 OUT D9
5%
1/32W
MF
1 C2963 M13
(INT PD) EXT_ALE/JTAG_SEL GND 26
01005 2.2UF PCIE_ST0_AP_TO_NAND_PERST_L E8 EXT_NCE/PERST* DROOP* T3

ROOM=NAND 20% M5 9 IN
2 6.3V
X5R-CERM E10 M7 G2
0201 VDDIO_2 WP* PP1V2_IO 26
ROOM=NAND E2 VDDIO_2 N10

ANALOG_NAND_PCIE_RESREF H7 PCIE_RESREF
I_VDDIO2 (@ 1.2V) = 384mA MAX N2 VDDIO_2 (VCCQ_ANI) N4
(for dev)
26 PP1V2_IO P9 VDDIO_2 P1
P11
1
C2920
1
R2904
200
1 C2931 1 C2929 1 C2943 1 C2945 1 C2947 P13 10PF 0.5%
15UF 15UF 2.2UF 2.2UF 2.2UF 2
5%
16V
1/32W
TK C10 ZQ_0 ANI0_VREF G12 ANALOG_NAND_ANI0_VREF
20% 20% 20% 20% 20% P3 NP0/C0G
89
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 01005 2 01005 K3 ZQ_1 ANI1_VREF J4 ANALOG_NAND_ANI1_VREF
X5R X5R X5R-CERM X5R-CERM X5R-CERM P7 ROOM=NAND
ROOM=NAND 89
0402-0.1MM-1 0402-0.1MM-1 0201 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND G6 VDD R10
G8 VDD T1 Keep ZQ trace DCR < 200mOhm
L6 VDD T13
1 C2959 1 C2960 1 C2912 1 C2915 1 C2917 L8 VDD T7 ANALOG_NAND_ZQ_0
ANALOG_NAND_ZQ_1
330PF 330PF 220PF 47PF 22PF R6 VDD T9
10% 10% 5% 5% 5% (for dev)
2 16V 2 16V 2 25V 2 16V 2 16V R8 VDD U12
1
R2900 1
R2901
NAND Capacities
CER-X7R CER-X7R COG NP0-C0G C0G
B
01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
U2
1%
300
1%
300 B
A10 1/32W 1/32W
(VDD) MF MF
A4 2 01005-1 01005-1
2 ROOM=NAND
1 C2961 1 C2918 1 C2914 1 C2962 J8 PCIE_VDD A6
ROOM=NAND
OMIT_TABLE
TABLE_5_HEAD
220PF 47PF 22PF 2.2UF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
5% 5% 5% 20% M9 PCIE_VDD A8 TABLE_5_ITEM
2 25V
COG 2 16V
NP0-C0G 2 16V
C0G 2 6.3V
X5R-CERM N6 VSS_R U10 335S00436 1 HYNIX,3Dv5,64Gb,Ultimate U2900 CRITICAL NAND:ULTIMATE
01005 01005 01005 0201 PCIE_VDD
N8 U4
TABLE_5_ITEM
I_VDD = 820mA MAX ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND PCIE_VDD 335S00437 1 HYNIX,3Dv5,128Gb,Supreme U2900 CRITICAL NAND:SUPREME
PACK_IGNORE=TRUE U6
PP0V83_NAND PACK_OPTION=D52,D53 PACK_OPTION=D52,D53 PACK_OPTION=D52,D53 PACK_OPTION=D52 TABLE_5_ITEM
29
U8 335S00438 1 HYNIX,3Dv5,256Gb,Extreme U2900 CRITICAL NAND:EXTREME
1 C2948 1 C2902 1 C2905 FL2923

TABLE_5_ITEM
335S00439 1 HYNIX,3Dv5,512Gb,Max U2900 CRITICAL NAND:MAX

15UF 15UF 15UF 10-OHM-1.1A
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 1 PP0V83_NAND_PLL R4 VDD_PLL TABLE_ALT_HEAD
X5R X5R X5R VOLTAGE=0.83 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
0402-0.1MM-1 0402-0.1MM-1 0402-0.1MM-1 F3 NC_DEV_NAND_VPP 26
C2923 VPP
01005 PART NUMBER
ROOM=NAND ROOM=NAND ROOM=NAND 1 ROOM=NAND
2.2UF 155S0876 F5 GND 26
TABLE_ALT_ITEM
20% VQPS 335S00449 335S00436 NAND:ULTIMATE U2900 TOSHIBA,BiCS4,64Gb,Ultimate
2 6.3V
X5R-CERM
TABLE_ALT_ITEM
0201 VQPS used for fuse 335S00446 335S00437 NAND:SUPREME U2900 SAMSUNG,3Dv5,128Gb,Supreme
ROOM=NAND programming, GND in system TABLE_ALT_ITEM
335S00447 335S00438 NAND:EXTREME U2900 SAMSUNG,3Dv5,256Gb,Extreme

TABLE_ALT_ITEM
335S00450 335S00438 NAND:EXTREME U2900 TOSHIBA,BiCS4,256Gb,Extreme

1 C2900 1 C2901 1 C2922 1 C2927 1 C2940 1 C2942 1 C2944 1 C2946 TABLE_ALT_ITEM
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 335S00448 335S00439 NAND:MAX U2900 SAMSUNG,3Dv5,512Gb,Max
20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 0201 0201 0201 0201 0201 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

A A
1 C2907 1 C2903 1 C2908 1 C2904 1 C2909 1 C2906 PAGE TITLE
330PF
10%
16V
5%
220PF
5%
47PF
5%
22PF
10%
330PF
5%
220PF NAND
2 CER-X7R 2 25V
COG 2 16V
NP0-C0G 2 16V
C0G 2 16V
CER-X7R 2 25V
COG DRAWING NUMBER SIZE
01005 01005 01005 01005 01005 01005 051-05215 D
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND Apple Inc. REVISION
PACK_OPTION=D52,D53 PACK_OPTION=D52,D53
4.6.0

29 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEV BOARD COMPATIBILITY
25 GND
25 GND
D
25
25
GND
GND
D
25 GND
25 GND
MAKE_BASE=TRUE
25 NC_DEV_NAND_JTAG_TDI NC_DEV_NAND_JTAG_TDI
MAKE_BASE=TRUE
NO_TEST=1
25 NC_DEV_NAND_VPP NC_DEV_NAND_VPP
MAKE_BASE=TRUE
NO_TEST=1
25 NC_DEV_NAND_BCM_L NC_DEV_NAND_BCM_L
MAKE_BASE=TRUE
NO_TEST=1
VDDIO2 C
C
33 25 PP1V2_IO PP1V2_IO 25
PP1V2_IO 25
B B

A A
PAGE TITLE
NAND: Aliases
DRAWING NUMBER SIZE
051-05215 D
Apple Inc. REVISION
4.6.0

31 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
998-19244
CRITICAL
U3300 ROOM=PMU
TMLL69A0
L3340 WLCSP L3300
VOLTAGE=1.0625 (DEFAULT, DVC = 0.98V - 1.1V) 0.47UH-3.7A-0.034OHM SYM 2 OF 5 1UH-20%-3.6A-0.062OHM (0.528V - 1.061V) VOLTAGE=1.061
33
PP1V06_S2 2 1 LX_BUCK4 A10 BUCK4_LX BUCK0_LX0 F18 LX_BUCK0_P0 1 2 PP_CPU_PCORE 33 87
138S00313
B10
C3343 C3342 C3341 C3340 BUCK4_LX
C3300 C3301 C3302
PIJD16140H-SM PIWE20160H-SM
2.2A MAX
BUCK4
1 1 1 1 ROOM=PMU ROOM=PMU 1 1 1
152S00984 152S00876
20UF 20UF 20UF 220PF 220PF 16UF 20UF
20% 20% 20% 5%
OMIT
L3301
0.1UH-20%-6.1A-0.019OHM
5% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 25V 2 25V 2 4V 2 6.3V
BUCK4
CERM-X5R CERM-X5R CERM-X5R COG COG X5R CERM-X5R
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
01005
ROOM=PMU XW3340
SHORT-20L-0.05MM-SM BUCK0_LX1 B17
ROOM=PMU 01005
ROOM=PMU
0402-0.1MM-1
ROOM=PMU
0402-0.1MM
ROOM=PMU
1 3 2020-MLCC
2 1 ANALOG_FB_BUCK4 D10 BUCK4_FB BUCK0_LX1 B18 LX_BUCK0_P1
D ROOM=PMU
NO_XNET_CONNECTION
C10 BUCK4_VSS_FB
UPPER_COIL_IN UPPER_COIL_OUT
D
LOCAL FEEDBACK BUCK0_LX3 D17 LX_BUCK0_P3 2 4
LOWER_COIL_IN LOWER_COIL_OUT
BUCK0_LX3 D18
MTFE2016-2SM
13.8A MAX
152S00897
BUCK0
2 OMIT
L3350 L3302
0.1UH-20%-6.1A-0.019OHM XW3301
VOLTAGE=0.763 (0.614V - 0.763V) 0.47UH-3.7A-0.034OHM ROOM=PMU
SHORT-20L-0.05MM-SM
ROOM=SOC
33
PP_AVE_S1 2 1 LX_BUCK5 A12 BUCK5_LX BUCK0_LX2 H17 1
NO_XNET_CONNECTION
B12 H18 LX_BUCK0_P2 1 3

C3351 C3350 C3354 BUCK5_LX BUCK0_LX2
PIJD16140H-SM
2.0A MAX
BUCK5
I_LOAD = 1.7A (MAX) 1 1 1 ROOM=PMU UPPER_COIL_IN UPPER_COIL_OUT <--- ANALOG_FB_BUCK0_R

152S00984
15UF 15UF 220PF
BUCK5
BUCK0
20%
2 6.3V
20%
2 6.3V
5%
2 25V OMIT BUCK0_LX4 K17 LX_BUCK0_P4 2 4
1
R3300
X5R X5R COG 499
0402-0.1MM-1
ROOM=PMU
PACK_IGNORE=TRUE
0402-0.1MM-1
ROOM=PMU
PACK_IGNORE=TRUE
01005
ROOM=PMU XW3350
SHORT-20L-0.05MM-SM
BUCK0_LX4 K18 LOWER_COIL_IN
MTFE2016-2SM
LOWER_COIL_OUT
1%
1/32W
PACK_OPTION=D54 PACK_OPTION=D54
D12 152S00897 MF
2 1 ANALOG_FB_BUCK5 BUCK5_FB 01005
2 118S00026
OMIT
ROOM=PMU
NO_XNET_CONNECTION
C12 BUCK5_VSS_FB ROOM=PMU XW3300
SHORT-20L-0.05MM-SM
1 C3351 1 C3350 MID-PLANE FEEDBACK BUCK0_FB H15 ANALOG_FB_BUCK0 1 2 ANALOG_PCPU_SENSE_P IN 16 89
20UF 20UF BUCK0_VSS_FB J16 ROOM=SOC
20% 20% NO_XNET_CONNECTION
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0402-0.1MM 0402-0.1MM DIE SENSE; PLACE XW NEAR U1000.BL37
ROOM=PMU ROOM=PMU
PACK_OPTION=D52,D53,DEV PACK_OPTION=D52,D53,DEV
L3360
VOLTAGE=1.2 (DEFAULT) 0.47UH-3.7A-0.034OHM
99 98 93 33
PP1V2_S4 2 1 LX_BUCK6 A2 BUCK6_LX
C
B2
C C3364 C3363 C3362 C3361 C3360 BUCK6_LX
PIJD16140H-SM
1 1 1 1 1
2.1A MAX
ROOM=PMU
BUCK6
152S00984
20UF 20UF 20UF 2.2UF 220PF L3310
BUCK6
20% 20% 20% 20% 5%
6.3V
2 CERM-X5R 2 6.3V 2 6.3V 2 6.3V 2 25V OMIT 1UH-20%-3.6A-0.062OHM (0.542V - 1.044V) VOLTAGE=1.044
CERM-X5R CERM-X5R X5R-CERM COG
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0201
ROOM=PMU
01005
ROOM=PMU XW3360
SHORT-20L-0.05MM-SM
BUCK1_LX0 Y13 LX_BUCK1_P0 1 2 PP_GPU 33 87
C3310 C3311 C3312

PIWE20160H-SM
2 1 ANALOG_FB_BUCK6 D2 BUCK6_FB ROOM=PMU 1 1 1
152S00876
ROOM=PMU C2 BUCK6_VSS_FB 220PF 20UF 20UF
NO_XNET_CONNECTION 5% 20% 20%
LOCAL FEEDBACK L3311

0.1UH-20%-6.1A-0.019OHM
2 25V
COG
01005
2 6.3V
CERM-X5R
0402-0.1MM
2 6.3V
CERM-X5R
0402-0.1MM
ROOM=PMU ROOM=PMU
BUCK1
ROOM=PMU ROOM=PMU
BUCK1_LX1 W17
10.0A MAX
BUCK1_LX1 Y17 LX_BUCK1_P1 1 3
BUCK1
UPPER_COIL_IN UPPER_COIL_OUT
L3370 BUCK1_LX2 W15 LX_BUCK1_P2 2 4

VOLTAGE=0.769 (DEFAULT) 0.47UH-20%-4.0A-0.05OHM BUCK1_LX2 Y15 LOWER_COIL_IN LOWER_COIL_OUT
PP_SRAM_S1 T17 MTFE2016-2SM

33
2 1 LX_BUCK7 BUCK7_LX 152S00897
T18
1 C3371 1 C3371 1 C3370 PIJD2012-SM BUCK7_LX
XW3310
OMIT
2.2A MAX
ROOM=PMU
152S00985
BUCK7
20UF 15UF 220PF
BUCK7
20% 20% 5% SHORT-20L-0.05MM-SM

2 6.3V 2 6.3V 2 25V OMIT BUCK1_FB U13 ANALOG_FB_BUCK1 1 2
CERM-X5R X5R COG
0402-0.1MM
ROOM=PMU
0402-0.1MM-1
ROOM=PMU
01005
ROOM=PMU XW3370
SHORT-20L-0.05MM-SM
BUCK1_VSS_FB V13 ROOM=PMU
NO_XNET_CONNECTION
PACK_IGNORE=TRUE
T15 REMOTE FEEDBACK; PLACE NEAR SOC
PACK_OPTION=D52,D53,DEV PACK_OPTION=D54 2 1 ANALOG_FB_BUCK7 BUCK7_FB
T16 BUCK7_VSS_FB
L3320
ROOM=PMU
NO_XNET_CONNECTION
MID-PLANE FEEDBACK 1UH-20%-2.2A-0.06OHM (0.612V - 0.79V) VOLTAGE=0.79
BUCK2_LX0 Y9 LX_BUCK2_P0 1 2 PP_SOC_S1 33
C3320 C3321
PIJR20120H-SM
B ROOM=PMU
152S00821
1
220PF
1
15UF B
L3321 5%
2 25V
20%
2 6.3V
L3380 0.22UH-20%-5.8A-0.04OHM COG
01005
X5R
0402-0.1MM-1
VOLTAGE=0.75 (0.585V - 0.75V) 0.47UH-2.9A-0.072OHM A14 BUCK8_LX BUCK2_LX1 W11 LX_BUCK2_P1 1 2 ROOM=PMU
4.9A MAX
ROOM=PMU
PP_DISP_S1
BUCK2
33
2 1 LX_BUCK8 B14 BUCK8_LX BUCK2_LX1 Y11 1608
ROOM=PMU
152S00818
C3382 C3381 C3380
2.2A MAX
PIJD1608FE-SM
BUCK8
1 1 1 ROOM=PMU
152S00982
BUCK8
BUCK2
15UF 20UF 220PF OMIT OMIT
20% 20% 5%
2 6.3V
X5R 2 6.3V
CERM-X5R 2 25V
COG XW3380
SHORT-20L-0.05MM-SM
XW3320
SHORT-20L-0.05MM-SM
0402-0.1MM-1 0402-0.1MM 01005
ROOM=PMU
ROOM=PMU ROOM=PMU 2 1 ANALOG_FB_BUCK8 D14 BUCK8_FB BUCK2_FB U9 ANALOG_FB_BUCK2 1 2
ROOM=PMU C14 BUCK8_VSS_FB BUCK2_VSS_FB V9 ROOM=PMU
NO_XNET_CONNECTION NO_XNET_CONNECTION
MID-PLANE FEEDBACK MID-PLANE FEEDBACK
L3330
1UH-20%-2.2A-0.06OHM VOLTAGE=1.8
BUCK3_LX V3 LX_BUCK3 1 2 PP1V8_S4 100
L3390
33 37 93
98 99
1.2A MAX
W3
BUCK3_LX
C3330 C3331 C3332 C3333 C3334
PIJR20120H-SM
BUCK3
ROOM=PMU 1 1 1 1 1
VOLTAGE=1.1 1UH-20%-2.2A-0.06OHM BUCK3_LX Y3 152S00821
220PF 20UF 20UF 20UF 20UF
82 PP1VX_DISPLAY_S2 2 1 LX_BUCK9 Y5 BUCK9_LX 5% 20% 20% 20% 20%
2 25V
COG 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
C3392 C3391 C3390
PIJR20120H-SM
1 1 1 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
0.6A MAX
I_LOAD = 0.2A (MAX) ROOM=PMU

BUCK9
BUCK3
BUCK9
152S00821 ROOM=PMU
20UF 15UF 220PF OMIT OMIT
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
20% 20% 5%
2 6.3V
CERM-X5R 2 6.3V
X5R 2 25V
COG XW3390
SHORT-20L-0.05MM-SM
XW3330
SHORT-20L-0.05MM-SM
0402-0.1MM 0402-0.1MM-1 01005
ROOM=PMU ROOM=PMU ROOM=PMU 2 1 ANALOG_FB_BUCK9 V5 BUCK9_FB BUCK3_FB W1 ANALOG_FB_BUCK3 1 2 SYNCING: D52, D53, D54
W5 V1
A ROOM=PMU
NO_XNET_CONNECTION
BUCK9_VSS_FB BUCK3_VSS_FB ROOM=PMU
NO_XNET_CONNECTION
A
LOCAL FEEDBACK LOCAL FEEDBACK PAGE TITLE
BUCK9 NOTES:
1. Output is default OFF
SYS PWR: PMU: Bucks (1/5)
DRAWING NUMBER SIZE
2. Voltage adjusts dynamically based on display vendor and mode (~1.0V to ~1.15V)
051-05215 D
TABLE_ALT_HEAD Apple Inc. REVISION
PART NUMBER
4.6.0
TABLE_ALT_ITEM

138S00048 138S00003 ? (C3391) 0402,15uF,6.3V, Kyocera
All RefDes in ( ) are single-sourced from Murata PROPRIETARY PROPERTY OF APPLE INC.
33 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
998-19244
CRITICAL
U3300 ROOM=PMU
TMLL69A0
WLCSP L3400
PLACE IN VICINITY OF PMU FOR BULK CAP SYM 3 OF 5 1UH-20%-2.2A-0.06OHM (0.765V - 1.099V) VOLTAGE=1.099
BUCK10_LX0 A8 LX_BUCK10_P0 1 2 PP_CPU_SRAM
33 30 PP_VDD_MAIN A1 VDD_BUCK13_10_6_4
33
C3401 C3402 C3403

PIJR20120H-SM
1 10% B1 1 1 1
C3450
CRITICAL CRITICAL CRITICAL VDD_BUCK13_10_6_4 ROOM=PMU
152S00821
1 C3404 1 C3405 1 C3406 6.3V
CER-X5R
L3401 5%
220PF 20UF
20% 20%
20UF
15UF 15UF 15UF 01005
4.2A MAX
BUCK10
20% 20% 20% 0.22UF 2 ROOM=PMU A3 0.22UH-20%-5.8A-0.04OHM 2 25V
COG 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
VSS_BUCK13_6
2 6.3V 2 6.3V 2 6.3V B3 A6
01005 0402-0.1MM 0402-0.1MM
X5R X5R X5R LX_BUCK10_P1 1 2
0402-0.1MM-1 0402-0.1MM-1 0402-0.1MM-1 C3451 2 10% VSS_BUCK13_6 BUCK10_LX1 ROOM=PMU ROOM=PMU ROOM=PMU
D
D ROOM=PMU ROOM=PMU ROOM=PMU 6.3V B6
CER-X5R BUCK10_LX1 1608
ROOM=PMU
01005 152S00818
0.22UF 1 ROOM=PMU A5 VDD_BUCK13_10_6_4
BUCK10
1 10% B5 OMIT
CRITICAL CRITICAL C3452 6.3V
VDD_BUCK13_10_6_4
XW3400
1 C3407 1 C3408 0.22UF 2
CER-X5R
01005 SHORT-20L-0.05MM-SM
15UF 15UF ROOM=PMU A7 VSS_BUCK10 BUCK10_FB D8 ANALOG_FB_BUCK10 2 1
20% 20% 2
2 6.3V 2 6.3V B7 C8
X5R
0402-0.1MM-1
X5R
0402-0.1MM-1 C3459 10%
6.3V
CER-X5R
VSS_BUCK10 BUCK10_VSS_FB ROOM=PMU
NO_XNET_CONNECTION
ROOM=PMU ROOM=PMU MID-PLANE FEEDBACK
0.22UF 1 01005
ROOM=PMU A9
1 10% B9
VDD_BUCK13_10_6_4
L3410
PLACE ON PMU CORNERS TO FILL 01005 RING AROUND PMU
C3453 6.3V
CER-X5R
VDD_BUCK13_10_6_4 1UH-20%-2.2A-0.06OHM (0.519V - 0.828V) VOLTAGE=0.828
01005 BUCK11_LX0 M18 28 LX_BUCK11_P0 1 2 PP_CPU_ECORE 28 33
0.22UF 2 ROOM=PMU A11 VSS_BUCK5_4
C3410 C3411 C3412 C3412
PIJR20120H-SM
2 ROOM=PMU 1 1 1 1
B11 152S00821
1 C3480 1 C3481 1 C3482 1 C3483 C3454 10%
6.3V
VSS_BUCK5_4
5%
220PF 20UF
20% 20%
20UF 15UF
20%
BUCK INPUT
CER-X5R PACK_OPTION=D52,D53,DEV
0.22UF 0.22UF 0.22UF 0.22UF 1 01005 2 25V
COG 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R
0.22UF
3.8A MAX
BUCK11
ROOM=PMU A13
BUCK11
01005 0402-0.1MM 0402-0.1MM 0402-0.1MM-1
L3411
10% 10% 10% 10% VDD_BUCK8_5
2 6.3V 2 6.3V 2 6.3V 2 6.3V BUCK11_LX1 P17 ROOM=PMU ROOM=PMU ROOM=PMU
CER-X5R CER-X5R CER-X5R CER-X5R 1 10% B13 ROOM=PMU
01005
ROOM=PMU
01005
ROOM=PMU
01005
ROOM=PMU
01005
ROOM=PMU
C3455 6.3V
CER-X5R
VDD_BUCK8_5
BUCK11_LX1 P18 0.22UH-20%-5.8A-0.04OHM PACK_IGNORE=TRUE
PACK_OPTION=D54 PACK_OPTION=D52,D53,DEV
01005 LX_BUCK11_P1 1 2
0.22UF 2 ROOM=PMU A15 VSS_BUCK8 1608
ROOM=PMU
L3410
B15 VSS_BUCK8 152S00818 OMIT 1UH-20%-2A-0.069OHM
Buck0 Buck1 Buck11 XW3410
SHORT-20L-0.05MM-SM 28 LX_BUCK11_P0 1 2 PP_CPU_ECORE 28 33
2 M15 ANALOG_FB_BUCK11 1 2
C3456 BUCK11_FB
10% 2012
6.3V A16 VSS_BUCK0 ROOM=PMU
138S00325 138S00325 CER-X5R BUCK11_VSS_FB M16 ROOM=PMU 152S00819
A17
C3490 C3491 C3492 C3493 VSS_BUCK0 NO_XNET_CONNECTION
1 1 1 1 0.22UF 1 01005
ROOM=PMU REMOTE FEEDBACK
PACK_IGNORE=TRUE
PACK_OPTION=D54
A18 VSS_BUCK0
2.2UF 2.7UF 2.7UF 2.2UF
L3420
20% 20% 20% 20%
C 2 6.3V
X5R-CERM
0201
2 6.3V
X5R
0201
2 6.3V
X5R
0201
2 6.3V
X5R-CERM
0201 C17 VDD_BUCK11_7_0 0.47UH-3.7A-0.034OHM (DEFAULT) VOLTAGE=0.88
C
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU C18
1 10% W7 LX_BUCK12 1 2 PP0V9_S1 33
2020-MLCC 2020-MLCC
C3457 6.3V
VDD_BUCK11_7_0 BUCK12_LX
Y7
BUCK12_LX
C3420 C3421 C3422 C3423
CER-X5R PIJD16140H-SM
01005 ROOM=PMU 1 1 1 1
2.1A MAX
BUCK12
0.22UF 2 152S00984
ROOM=PMU E17 VSS_BUCK0 220PF 20UF 20UF 20UF
BUCK12
2 5% 20% 20% 20%
E18 2 25V 2 6.3V 2 6.3V 2 6.3V
C3469 10%
6.3V
CER-X5R
VSS_BUCK0
XW3420
OMIT COG
01005
CERM-X5R
0402-0.1MM
CERM-X5R
0402-0.1MM
CERM-X5R
0402-0.1MM
0.22UF 1 01005
ROOM=PMU
SHORT-20L-0.05MM-SM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
G17 VDD_BUCK11_7_0 BUCK12_FB U7 ANALOG_FB_BUCK12 2 1
1 10% G18 V7
C3458 6.3V
CER-X5R
VDD_BUCK11_7_0 BUCK12_VSS_FB ROOM=PMU
NO_XNET_CONNECTION
01005 LOCAL FEEDBACK; PLACE NEAR U3300.N1
0.22UF 2 ROOM=PMU J17
2 J18
VSS_BUCK0
L3430
C3460 10%
6.3V
CER-X5R
VSS_BUCK0 0.47UH-2.9A-0.072OHM (0.615V - 0.842V) VOLTAGE=0.842
BUCK13_LX A4 LX_BUCK13 1 2 PP_DCS_S1 33
0.22UF 1 01005
1.0A MAX
BUCK13
ROOM=PMU L17 VDD_BUCK11_7_0
C3432 C3430 C3431
PIJD1608FE-SM
ROOM=PMU 1 1 1
1 10% L18 152S00982 OMIT
C3470 6.3V
CER-X5R
VDD_BUCK11_7_0
XW3430 5%
220PF 20UF
20% 20%
20UF
01005 SHORT-20L-0.05MM-SM 2 25V 2 6.3V 2 6.3V
BUCK13
0.22UF 2 ROOM=PMU
COG CERM-X5R CERM-X5R
N17 VSS_BUCK11 BUCK13_FB C4 ANALOG_FB_BUCK13 1 2 01005 0402-0.1MM 0402-0.1MM
2 ROOM=PMU ROOM=PMU ROOM=PMU
N18
C3461 10%
6.3V
CER-X5R
VSS_BUCK11
BUCK13_VSS_FB B4 ROOM=PMU
NO_XNET_CONNECTION
1 01005 MID-PLANE FEEDBACK

0.22UF ROOM=PMU R17 VDD_BUCK11_7_0
1 10% R18
C3462 6.3V
CER-X5R
VDD_BUCK11_7_0
01005
0.22UF 2 ROOM=PMU U17 VSS_BUCK7
B U18 VSS_BUCK7
B
2
C3463 10%
6.3V
CER-X5R
V18 VSS_BUCK1
W18 VSS_BUCK1
0.22UF 1 01005
ROOM=PMU Y18 VSS_BUCK1
W16 VDD_BUCK12_2_1
1 10% Y16
C3464 6.3V
CER-X5R
VDD_BUCK12_2_1
01005
0.22UF 2 ROOM=PMU W14 VSS_BUCK1
2 Y14
C3471 10%
6.3V
CER-X5R
VSS_BUCK1
0.22UF 1 01005
ROOM=PMU W12 VDD_BUCK12_2_1
1 10% Y12
C3465 6.3V
CER-X5R
VDD_BUCK12_2_1
01005
0.22UF 2 ROOM=PMU W10 VSS_BUCK2
2 Y10
C3472 10%
6.3V
CER-X5R
VSS_BUCK2
0.22UF 1 01005
ROOM=PMU W8 VDD_BUCK12_2_1
1 10% Y8
C3466 6.3V
CER-X5R
VDD_BUCK12_2_1
01005
0.22UF 2 ROOM=PMU
2
W6 VSS_BUCK12_9 SYNCING: D52, D53, D54
Y6
A C3467 10%
6.3V
CER-X5R
VSS_BUCK12_9
A
0.22UF 1 01005
ROOM=PMU PAGE TITLE
W4 VDD_BUCK9_3
Y4 VDD_BUCK9_3
SYS PWR: PMU: Bucks (2/5)
1 10%
C3468 6.3V V4 VDD_BUCK9_3
DRAWING NUMBER
051-05215
SIZE
D
Apple Inc.
CER-X5R
01005
0.22UF 2 ROOM=PMU REVISION
V2 VSS_BUCK3 4.6.0
W2 VSS_BUCK3 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Y1 VSS_BUCK3 THE INFORMATION CONTAINED HEREIN IS THE
Y2 VSS_BUCK3 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
34 OF 160
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SUBSYSTEM SPECIFIC BOM TABLES
4uF 0201 Capacitors (single-source Murata)
PART NUMBER
TABLE_ALT_HEAD
TABLE_ALT_ITEM
PMU:LDOs
138S00116 138S00071 ? (C3515) CAP,X5R,4UF,0201,0.55MM,TAIYO
TABLE_ALT_ITEM
138S00117 138S00071 ? (C3515) CAP,X5R,4UF,0201,0.55MM,KYOCERA
15uF 0402 Capacitors (single-source Murata)

TABLE_ALT_HEAD

PART NUMBER
D 138S00048 138S00003 ? [SEE BELOW] 0402,15uF,6.3V, Kyocera

TABLE_ALT_ITEM
D
All RefDes in ( ) are single-sourced from Murata NOTES:
(C3509,C3510,C3520,C3530,C3540,C3545,C3555,C3566,C3570)
1. PP1V2_SOC is low noise SOC rail, PP1V2_IO is its noisy cousin
2. PPVAR_EIGER_S2 typical output is 1.8V, max 3.275V during calibration
998-19244
CRITICAL
U3300 ROOM=PMU 3. LDO3 and LDO8 are operating near-dropout by design (1.24Vin, 1.2Vout)
4. Max system load currents provided in power tree, radar # 43311246
TMLL69A0
WLCSP 5. OTP will disable LDO13 and LDO14 for all programs. Software must enable them for D52 and D54.
SYM 1 OF 5 PMU LDO Capability:
6. LDO6 is OTP programmed to be a load switch
PP_VDD_BOOST F5 VDD_BOOST_LDO LDO GROUP 1 VLDO1 J6 VOLTAGE=3.3 PP3V3_USB_S2
33 33
LDO1 200 mA MAX
H4 VDD_BOOST_LDO VLDO5 L1 VOLTAGE=2.625 PP2V625_NAND 25
LDO5 1200 mA MAX
1 C3504 1 C3505 J2 VDD_BOOST_LDO VLDO5 L2
2.2UF 2.2UF J4 VDD_BOOST_LDO VLDO5 L3
20% 20%
2 6.3V 2 6.3V J5 VDD_BOOST_LDO VLDO7 H3 VOLTAGE=3.0 PP3V0_S2
X5R-CERM X5R-CERM 33 94
LDO7 250 mA MAX
0201 0201 K1 VDD_BOOST_LDO VLDO10 J1 VOLTAGE=3.0 PP3V0_DISPLAY_S2
ROOM=PMU ROOM=PMU 82
LDO10 50 mA MAX
K2 VDD_BOOST_LDO VLDO13 J3 VOLTAGE=3.15 NC_PP3V1_TOUCH_S2 42
LDO13 150 mA MAX
K3 VDD_BOOST_LDO
1 C3510 1 C3570 1 C3515 1 C3545 1 C3546
15UF 15UF 4UF 15UF PACK_IGNORE=TRUE 10UF PACK_IGNORE=TRUE
20% 20% 20% 20% PACK_OPTION=D52,D54,DEV 20% PACK_OPTION=D52,D54,DEV
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
CER-X5R 2 6.3V
X5R
10V
2 X5R-CERM
0402-0.1MM-1 0402-0.1MM-1 0201 0402-0.1MM-1 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
(1) PP3V3_USB_S2 (7) PP3V0_S2

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8 7 6 5 4 3 2 1

SB12500 677 676

J10500 L5300 573

C4470 C4438 529

C7927 C7930 C7910

C1811 C3382 C9490 128 495

C3640 C2032 L3301

C3403 BG63 BG62 BG61 BG60

BE63 BE62 BE61 BE60 BE4 BE3 BE2 BE1

BA63 BA62 BA61 BA60 BA4 BA3 BA2 BA1

AW63 AW62 AW61 AW60 AW4 AW3 AW2 AW1

153 AL63 AL62 AL61 AL60 AL4 AL3 AL2 AL1

AD63 AD62 AD61 AD60 AD4 AD3 AD2 AD1

Y63 Y62 Y61 Y60 Y4 Y3 Y2 Y1

V63 V62 V61 V60 V4 V3 V2 V1

T63 T62 T61 T60 T4 T3 T2 T1

P63 P62 P61 P60 P4 P3 P2 P1

K63 K62 K61 K60 K4 K3 K2 K1

C1903 C1940 457

C1995 C1921 PP128A7 C1831 G63 G62 G61 G60 G4 G3 G2 G1

L3330 L3390 L3320 171

C3312 C1833 L9550 173

C3331 C3421 446

R3610 C4010 439

C3471 C4210 C4042 C4003 C9602 436

R4311 C9117 R9130 411

C9301 R9301 C2470 R9100

D53AP EVT MLB LAYOUT

C11694 C11609 249

252 322 325

NOTICE OF PROPRIETARY PROPERTY:

726 598 625 627

C3202_E L3202_E R3201_E L3201_E 698

565 C6520 C6593

522 101 PP237_W

C604_E C603_E C765_E

Y601_E UBBPMK_E PP4673_E

504 C752_E 119 PP4670_E

488 C781_E PP4693_E

485 C706_E C702_E 138

479 C788_E C743_E

C764_E C761_E C733_E 148

C1905_E C1904_E C412_E 154

458 C516_E PP4605_E PP4606_E

C515_E 166 PP4677_E

XW1184_E XW1182_E XW1201_E

434 C1118_E PP4624_E

411 C1701_E 211

C1704_E C1604_E C1601_E 212

410 XW1702_E XW1602_E

339 XR364_W 238

C386_W R2108_E 239

C2108_E FD12511 FD12503

L3301_E R3301_E C2114_E 251

D53BB EVT MLB LAYOUT

315 320 254

PART NUMBER SIZE

THE INFORMATION CONTAINED HEREIN IS THE

JLAT THE POSESSOR AGREES TO THE FOLLOWING: ASSEMBLY

II NOT TO REPRODUCE OR COPY IT

D53 Top MLB

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

825-7691 1 EEEE FOR 639-10097 NY3J CRITICAL EEEE:10097