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  • CAZ60 LA-E671P ITALIA Pilot MB r1.0

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    Dell XPS 9370 Schematic

    Original Title

    CAZ60_LA-E671P_ITALIA_Pilot_MB_r1.0

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    Dell XPS 9370 Schematic

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    31 views61 pages

    CAZ60 LA-E671P ITALIA Pilot MB r1.0

    Uploaded by

    tan_871714877
    Dell XPS 9370 Schematic

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 61

    A B C D E

    MODEL NAME : CAZ60


    PCB NO : LA-E671P
    BOM P/N : 43xxxxx
    ZZZ
    Vinafix.com
    1 1

    MB_PCB

    Dell/Compal Confidential
    2 2

    Schematic Document
    Italia
    @@@CXLRXEUUUUD67D
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    3
    2017-09-15 3
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    p
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    CIloP 232::
    o
    nl-tDCPPP2r
    n
    e

    Rev: 1.0 ( A00 )


    P@FDM2242E55C
    S @ C2322B00I

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    @@@@@UU@@@
    XE
    D

    e
    u

    t
    M
    C

    mSSSat

    e
    U
    2
    C

    o
    ::3@:
    U
    2
    C

    o
    U
    4
    C

    o
    2 G ::
    @ T
    Uo
    2

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    4 4
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    MMr
    Tf

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    D
    C
    I
    D
    e
    b
    u
    g

    Issued Date 2016/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P01-Cover Page
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 1 of 61
    A B C D E
    A B C D E

    eDP Panel Conn. eDP 1.3

    I2C Channel A
    + Touch Screen Memory Bus (LPDDR3) LPDDR3 8Gb or 16Gb (x32) * 2
    (IPT) P.37
    Vinafix.com Dual Channel P.21

    1 1.2V LPDDR3 1866 MHz Non-Interleave Channel B 1

    LPDDR3 8Gb or 16Gb (x32) * 2


    P.22
    DP 1.2 X2
    TI PD Alpine Ridge Intel
    USB TypeC Conn. Thunderbolt PCIe Gen3 X 4
    TPS65982 P.43 P.46
    P.41 Kaby Lake
    SPI SPI ROM
    TI PD USB TypeC Conn. DP 1.2 X1
    TPS65982 P.44 P.46 ULT 128/256Mb P.09

    USB3.0
    TI PD DP Switch
    USB TypeC Conn. TI TUSB546 USB2.0
    TPS65982 P.45 P.47
    P.31 TPM2.0
    Nuvoton P.27

    USB2.0 15W TDP


    IR Digital Camera
    P.37 DMIC
    SATA3 X1 / PCIE X4 M.2 Socket3 M-Key
    2 2
    SSD P.30

    USB2.0 WLAN1216
    CardReader PCIE Gen2
    uSD 4.0 PCIE WLAN
    P.29 RTS5242 P.29 BT4.0
    P.28

    Fingerprint USB2.0
    P.36
    Audio/B with FPC

    HDA Audio Codec Headphone Jack


    I2C ( iPhone & Nokia compatible)

    Precision Touch Pad ALC3271 P.26


    P.24
    P.36

    I2S
    3 SMBus 3
    DMIC
    Fan conn. x 2 Page 7 ~ 20 Audio AMP Int. Speaker
    P.30 ALC1309 P.25 P.25

    RTC conn. ESPI


    P.35

    User Interface
    DC/DC Interface CKT.
    P.34~35
    EC
    PS/2 MEC 5105 Battery Gauge LED
    P.38 P.32
    Power Circuit DC/DC
    P.49~61

    BCBUS

    KBC/B
    Keyboard Controller KSIO Int.KBD
    4
    ECE1117B 4

    Front Side LED + 4 MIC

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P02-Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 2 of 61
    A B C D E
    A B C D E

    2+2 CPU Option 2+3 CPU Option 4+2 CPU Option AR Option TPM Option
    UCPU1 QM6R_2+3_R3@
    UCPU1 QNB1_2+2@ UCPU1 QNEE_4+2_R3@ UCPU1 QNBF_4+2_R3@ UT2 AR_SLL42@ U7 TPM750@

    SA0000AHS1L
    SA0000B2Y0L SA0000AWS2L SA0000AWC2L SA00009ZV3L SA0000AQ200
    DSL6340 SLL42 B2 TPM750 - ES FW:7.1.0.0

    UCPU1 QLYJ_2+2_R3@ Vinafix.com UCPU1 QNEF_4+2_R3@ UCPU1 QNBE_4+2_R3@

    1 1

    SA0000A377L SA0000AWB3L SA0000AWR2L

    DRAM Option DRAM Config Option


    MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4
    UD41 M4G_1866@ UD42 M4G_1866@ UD43 M4G_1866@ UD44 M4G_1866@ RH51 M4G_1866@ RH54 M4G_1866@ RH56 M4G_1866@ RH57 M4G_1866@ RH60 M4G_1866@

    Micron 4G/1866
    SA00009XU1L
    SA00009XU1L SA00009XU1L SA00009XU1L SA00009XU1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    UD41 M8G_1866@ UD42 M8G_1866@ UD43 M8G_1866@ UD44 M8G_1866@ RH52 M8G_1866@ RH53 M8G_1866@ RH56 M8G_1866@ RH57 M8G_1866@ RH60 M8G_1866@

    Micron 8G/1866
    SA00009U71L
    SA00009U71L SA00009U71L SA00009U71L SA00009U71L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    UD41 M16G_1866@ UD42 M16G_1866@ UD43 M16G_1866@ UD44 M16G_1866@ RH51 M16G_1866@ RH53 M16G_1866@ RH56 M16G_1866@ RH57 M16G_1866@ RH60 M16G_1866@

    Mircon 16G/1866
    2 2
    SA00009ZN1L
    SA00009ZN1L SA00009ZN1L SA00009ZN1L SA00009ZN1L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD41 H4G_1866@ UD42 H4G_1866@ UD43 H4G_1866@ UD44 H4G_1866@ RH52 H4G_1866@ RH54 H4G_1866@ RH55 H4G_1866@ RH57 H4G_1866@ RH60 H4G_1866@

    Hynix 4G/1866
    SA00008G64L SA00008G64L SA00008G64L SA00008G64L SA00008G64L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    H9CCNNN8GTALAR-NUD H9CCNNN8GTALAR-NUD H9CCNNN8GTALAR-NUD H9CCNNN8GTALAR-NUD 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD41 H8G_1866@ UD42 H8G_1866@ UD43 H8G_1866@ UD44 H8G_1866@ RH51 H8G_1866@ RH54 H8G_1866@ RH55 H8G_1866@ RH57 H8G_1866@ RH60 H8G_1866@

    Hynix 8G/1866
    SA00008FJ4L
    SA00008FJ4L SA00008FJ4L SA00008FJ4L SA00008FJ4L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    H9CCNNNBJTALAR-NUD H9CCNNNBJTALAR-NUD H9CCNNNBJTALAR-NUD H9CCNNNBJTALAR-NUD 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    UD41 H16G_1866@ UD42 H16G_1866@ UD43 H16G_1866@ UD44 H16G_1866@ RH52 H16G_1866@ RH53 H16G_1866@ RH55 H16G_1866@ RH57 H16G_1866@ RH60 H16G_1866@

    Hynix 16G/1866
    SA0000AEN0L
    SA0000AEN0L SA0000AEN0L SA0000AEN0L SA0000AEN0L SD028100280 SD028100280 SD028100280 SD028100280 SD028100280
    H9CCNNNCLGALAR-NUD H9CCNNNCLGALAR-NUD H9CCNNNCLGALAR-NUD H9CCNNNCLGALAR-NUD 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D

    3 3

    4 4

    LA-E671P
    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P03-BoM Option
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 3 of 61
    A B C D E
    A

    Board ID Table for AD channel


    USB PORT# DESTINATION
    RE194 CE75 REV
    CPU 4+2 2+3 3+2
    240K 4700p X00 1 PD PORT3
    130K 4700p X01 PCH
    USB 2.0 2 NC
    62K 4700p
    33K 4700p
    X02
    X03 Vinafix.com
    Italia
    CAZ60 Port
    8.2K 4700p A00 3 NC
    Mapping
    4.3K 4700p
    2K 4700p 4 NC
    1K 4700p
    5 IR Camera & Cam
    BOARD_ID rise t i me i s meas ur ed fr o m5 %~68 %.
    6 NC
    SMBUS Control Table

    BATTERY Audio 7 NGFF WLAN BT


    SOURCE PD1 PD2 PWR_MON 5105 XDP eDP Touch Pad Touch S IR_THER_S
    Charger AMP
    8 NC
    SMB00_CLK
    SMB00_DATA
    MEC5105
    V
    9 NC
    SMB01_CLK
    SMB01_DATA
    MEC5105
    V
    10 Fingerprint
    SMB02_CLK
    SMB02_DATA
    MEC5105
    V
    1 DP MX (PS8743B)
    SMB04_CLK
    SMB04_DATA
    MEC5105
    V PCH
    USB 3.0 2
    SMB05_CLK
    SMB05_DATA
    MEC5105
    V Port
    Mapping
    SMB07_CLK
    SMB07_DATA
    MEC5105
    V
    SMB10_CLK
    SMB10_DATA
    MEC5105
    V
    PCH_SML1CLK
    PCH_SML1DATA
    PCH
    V DDI PORT# DESTINATION
    PCH
    SMBCLK
    SMBDATA
    PCH
    V DDI 1 Alpine Ridge
    1
    I2C0_CLK PCH
    V Port 1

    I2C2_DATA
    I2C0_DATA
    Mapping 2 Alpine Ridge
    I2C1_CLK
    I2C1_DATA
    PCH
    V
    I2C2_CLK
    I2C2_DATA
    PCH
    V

    DIFFERENTIAL CLK# DESTINATION PCI EXPRESS PORT# DESTINATION SATA PORT# DESTINATION
    CLKOUT_PCIE0 Alpine Ridge Lane 1 Card Reader
    SATA-0 NC
    CLKOUT_PCIE1 NGFF WLAN Lane 2 NC SATA-1A NC
    CLKOUT_PCIE2 NC Lane 3 NGFF WLAN
    SATA-1B NC
    CLK CLKOUT_PCIE3 M.2 SSD Lane 4 NC
    SATA-2 M.2 SSD
    CLKOUT_PCIE4 NC Lane 5 Alpine Ridge

    CLKOUT_PCIE5 Card Reader Lane 6 Alpine Ridge

    FLEX CLK# DESTINATION Lane 7 Alpine Ridge Symbol Note :

    CLKOUT_LPC_0 ESPI 5105 Lane 8 Alpine Ridge : means Digital Ground

    CLKOUT_LPC_1 NC Lane 9 M.2 SSD


    : means Analog Ground
    Lane 10 M.2 SSD

    Lane 11 M.2 SSD

    Lane 12 / SATA 2 M.2 SSD DELL CONFIDENTIAL/PROPRIETARY


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P04-Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 4 of 61
    A
    5 4 3 2 1

    SIO_SLP_S4# & SIO_SLP_S0# & CPU PWR


    SUS_ON_EC RUN_ON_P
    SY8210A TPS22961 PCH PWR
    (PU600) 5500mA +1.2V_DDR (UZ5) 260mA +VCCPLL_OC +1.0V_MPHYGT
    GPU PWR
    Peripheral Device PWR
    SM_PG_CTRL

    600mA +0.6VS +1.0V_MPHYAON


    Type C X 3
    Vinafix.com SIO_SLP_SUS# &
    SIO_SLP_SUS# SUS_ON_P
    D SY8286 TPS22961 D

    (PU700) 880mA +1.0VA (UZ3) 240mA +1.0V_VCCST

    SIO_SLP_S0# & SIO_SLP_S0# &


    RUN_ON_P RUN_ON_P
    TPS62134A TPS22961
    (PU1400) 3100mA +1.0VS_VCCIO (UZ4) 40mA +1.0V_VCCSTG
    ISL88738
    (PU300) TPS62134B SIO_SLP_SUS#
    RUN_ON_P
    (PU1401) 2570mA +1.0V_PRIM_CORE
    200mA +5VS

    ALWON AUD_PWR_EN
    SY8288C AOZ1331
    (PU501) 530mA +5VALW (U12) 3150mA +5VS_AUDIO
    B+
    BATTERY SIO_SLP_SUS#
    (JT100) TLV6215
    (PU800) 210mA +1.8VA

    C C

    AUD_PWR_EN
    AOZ1331
    (U14) 400mA +1.8VS_AUDIO
    SY8286B
    (PU500)
    +V1.8S_EDRAM
    ALWON
    ENVDD
    590mA +3VALW SY6288C
    (UZ2) 545mA +LCDVDD

    TP_PW _EN
    AP22850
    IMVP_VR_ON_P (U10) 35mA +3VS_TP
    TPS62134C
    (PU1500) 2500mA +VCC_EDRAM

    PCH_PWR_EN
    TPS62134C IMVP_VR_ON_P
    AOZ1331 (SIO_SLP_SUS#)
    (PU1501) 2000mA +VCC_EOPIO (U11) 535mA +3V_PCH
    RUN_ON_P
    B 2500mA +3.3VDX_SSD B

    AOZ1331 AUX_EN_W OW L
    (U13) 620mA +3VS_NGFF
    RUN_ON_P
    TLV62150R
    (PU900) 480mA +3VS
    3.3V_TS_EN
    TPS22961
    (UZ1) 300mA +3VS_TS
    SD_PWR_EN
    SUS_ON_P

    660mA

    1200mA +3VS_CR
    AUD_PWR_EN
    AOZ1331
    (U14) 50mA +3VS_AUDIO

    ISL95829 AP22850
    (PU1000)
    IMVP_VR_ON

    EN_INVPWR

    590mA
    5100mA

    IMVP_VR_ON

    IMVP_VR_ON
    64000mA

    29000mA

    A A

    +INV_PWR_SRC +1.8VU DELL CONFIDENTIAL/PROPRIETARY


    +VCC_SA +VCC_GT +VCC_CORE
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P05-Power rails
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 5 of 61
    5 4 3 2 1
    A B C D E F G H

    2.2K

    2.2K
    +3VS
    R7 MEM_SMBCLK 53

    R8 MEM_SMBDATA 51 XDP
    Vinafix.com
    1
    KBL-U 1

    R9
    W2
    W3 V3
    1K
    SML1_SMBDATA

    SML1_SMBCLK
    +3V_PCH
    1K

    E11 D8

    SMB03
    2.2K

    2.2K
    +3.3V_EC5105

    D7 UPD2_SMBCLK B5
    SMB00 TI PD2 TI PD address selection 0x70_TBD
    E7 UPD2_SMBDAT A1

    L2
    2.2K PD2_Debug PD_Debug address selection 0xEC_TBD
    +3.3V_EC5105 K2
    2
    2.2K 2
    B3
    B3 IR_THER_SEN_SMBCLK
    SMB01 C3 IR_THER_S
    E5 IR_THER_SEN_SMBDAT

    4.7K

    KBC 4.7K +3VS_TP


    8
    C12 CLK_TP_SIO
    SMB02 9 TP TP address :0x42_TBD
    E10 DAT_TP_SIO

    2.2K
    L2
    PD1_Debug PD_Debug address selection 0xEC_TBD
    +3.3V_EC5105 K2
    2.2K

    C3 UPD1_SMBCLK B5
    SMB04 TI PD1 TI PD address selection 0x70_TBD
    B4 UPD1_SMBDAT A1
    2.2K
    MEC 5105
    2.2K +DVDD
    3 3
    F7 0 ohm
    EC_I2C_CLK 7
    SMB05 0 ohm AMP I2C address selection L= 0x20H (L= 0x20H ; H= 0x22H)_TBD
    B6 EC_I2C_DAT 8

    6
    Audio
    7
    2.2K
    +3VS_PWRM
    2.2K
    0 ohm
    A12 PWR_MONITOR_EC_SMBCLK PWRM_SCL C4
    SMB06 0 ohm MAX34407
    N10 PWR_MONITOR_EC_SMBDAT PWRM_SDA D4

    2.2K
    +3.3V_EC5105
    2.2K
    M4 UPD3_SMBCLK B5
    SMB07 TI PD3
    M7 UPD3_SMBDAT A5

    2.2K

    +3.3V_EC5105
    2.2K
    100 ohm
    4 N2 PBAT_CHARGER_SMBCLK 8 4
    SMB10 100 ohm BATTERY
    M3 PBAT_CHARGER_SMBDAT 7
    CONN Battery address selection 0x16_TBD

    22
    Charger Charger address selection 0x12_TBD
    21
    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P06-SMBus block diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 6 of 61
    A B C D E F G H
    5 4 3 2 1

    +3VS
    @ UCPU1A SKL-U

    2 1 CPU_DP1_CTRL_CLK E55 C47


    RC1 2.2K_0402_5% <41> DDI1_PTX_TBRX_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 eDP_TXN_P0 <37>
    2 1 CPU_DP1_CTRL_DATA <41> DDI1_PTX_TBRX_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 eDP_TXP_P0 <37>
    RC3 2.2K_0402_5% <41> DDI1_PTX_TBRX_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 eDP_TXN_P1 <37>
    2 1 CPU_DP2_CTRL_CLK <41> DDI1_PTX_TBRX_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 eDP_TXP_P1 <37> Support QHD
    RC5

    RC7
    2
    2.2K_0402_5%
    1 CPU_DP2_CTRL_DATA
    2.2K_0402_5%
    Vinafix.com
    <41>
    <41>
    <41>
    DDI1_PTX_TBRX_N2
    DDI1_PTX_TBRX_P2
    DDI1_PTX_TBRX_N3
    G53
    F56
    G56
    DDI1_TXN[2]
    DDI1_TXP[2]
    DDI1_TXN[3]
    EDP_TXN[2]
    EDP_TXP[2]
    EDP_TXN[3]
    B45
    A47
    B47
    eDP_TXN_P2
    eDP_TXP_P2
    eDP_TXN_P3
    <37>
    <37>
    <37>
    <41> DDI1_PTX_TBRX_P3 DDI1_TXP[3] EDP_TXP[3] eDP_TXP_P3 <37>
    D C50 E45 +3VS D
    Alpine Ridge <41> DDI2_PTX_TBRX_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 eDP_AUXN <37>
    <41> DDI2_PTX_TBRX_P0 C52 DDI2_TXP[0] EDP_AUXP eDP_AUXP <37> 2 100K_0402_5% I2C2_IRQ_TS
    RH83 1
    <41> DDI2_PTX_TBRX_N1 D52 DDI2_TXN[1] B52
    <41> DDI2_PTX_TBRX_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
    <41> DDI2_PTX_TBRX_N2 B50 DDI2_TXN[2] G50
    <41> DDI2_PTX_TBRX_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DDI1_AUXN <41>
    <41> DDI2_PTX_TBRX_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DDI1_AUXP <41>
    <41> DDI2_PTX_TBRX_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DDI2_AUXN <41>
    DDI2_AUXP G46 CPU_DDI2_AUXP <41> EDP_HPD 2 1
    DISPLAY SIDEBANDS DDI3_AUXN F46 PAD~D @ T1
    100K_0402_5% RC2
    CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T2 CPU_DP1_HPD 2 1
    <41> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_DP1_HPD 100K_0402_5% RC4
    <41> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP2_HPD CPU_DP1_HPD <41> CPU_DP2_HPD 2 1
    CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <41>
    100K_0402_5% RC6
    <41> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 I2C2_IRQ_TS <37>
    <41> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD
    N11 GPP_E17/EDP_HPD EDP_HPD <37>
    N12 GPP_E22/DDPD_CTRLCLK R12
    GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 PANEL_BKLEN <37>
    RC8 1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <37>
    +1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <33,38>
    1 OF 20
    SKL-U_BGA1356
    COMPENSATION PU FOR eDP
    CAD Note:Trace width=5 mils, Isolat i on Spaci ng=25 m
    il, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
    Max length=600 mils.

    C C

    SKL_ULT
    @ UCPU1I

    CSI-2

    A36 C37
    B36 CSI2_DN0 CSI2_CLKN0 D37
    C38 CSI2_DP0 CSI2_CLKP0 C32
    D38 CSI2_DN1 CSI2_CLKN1 D32 Micron 4G Micron 8G Mircon 16G Hynix 4G Hynix 8G Hynix 16G Samsung 4G Samsung 8G Samsung 16G
    GPIO Pin Pin Name
    C36 CSI2_DP1 CSI2_CLKP1 C29
    D36 CSI2_DN2 CSI2_CLKN2 D29
    A38 CSI2_DP2 CSI2_CLKP2 B26 GPP_F13 MEM_CONFIG0 0 1 0 1 0 1 0 1 0
    B38 CSI2_DN3 CSI2_CLKN3 A26
    CSI2_DP3 CSI2_CLKP3
    C31 E13 CSI2_COMP 1 2 GPP_F14 MEM_CONFIG1 0 0 1 1 0 0 1 1 0
    D31 CSI2_DN4 CSI2_COMP B7 RC9 100_0402_1%
    C33 CSI2_DP4 GPP_D4/FLASHTRIG 1600 Mbps
    D33 CSI2_DN5
    GPP_F15 MEM_CONFIG2 0 0 0 0 1 1 1 1 0
    A31 CSI2_DP5 EMMC

    B31 CSI2_DN6 AP2 MEM_CONFIG0


    A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 MEM_CONFIG1 GPP_F16 MEM_CONFIG3 0 0 0 0 0 0 0 0 1
    B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 MEM_CONFIG2
    CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 MEM_CONFIG3
    A29 GPP_F16/EMMC_DATA3 AN1 MEM_CONFIG4 GPP_F17 MEM_CONFIG4 0 0 0 0 0 0 0 0 0
    B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
    C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
    D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
    B A27 CSI2_DP9 GPP_F20/EMMC_DATA7 GPIO Pin Pin Name Micron 4G Micron 8G Mircon 16G Hynix 4G Hynix 8G Hynix 16G Samsung 4G Samsung 8G Samsung 16G B
    B27 CSI2_DN10 AM2
    C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
    D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4 GPP_F13 MEM_CONFIG0 1 0 1 0 1 0 1 0 1
    CSI2_DP11 GPP_F12/EMMC_CMD
    AT1 EMMC_RCOMP 1 2
    EMMC_RCOMP RC10 200_0402_1% GPP_F14 MEM_CONFIG1 0 1 1 0 0 1 1 0 0
    SKL-U_BGA1356 9 OF 20
    1866 Mbps
    GPP_F15 MEM_CONFIG2 0 0 0 1 1 1 1 0 0

    GPP_F16 MEM_CONFIG3 1 1 1 1 1 1 1 0 0

    DDR Memory Conf i gur at i no Type St r ap pin GPP_F17 MEM_CONFIG4 0 0 0 0 0 0 0 1 1


    +1.8VA

    @ RH51 2 1 10K_0402_5% MEM_CONFIG0 @ RH52 2 1 10K_0402_5% GPIO Pin Pin Name Micron 4G Micron 8G Mircon 16G Hynix 4G Hynix 8G Hynix 16G Samsung 4G Samsung 8G Samsung 16G

    @ RH53 2 1 10K_0402_5% MEM_CONFIG1 @ RH54 2 1 10K_0402_5%


    GPP_F13 MEM_CONFIG0 0 1 0 1 0 1 0 1 0
    @ RH55 2 1 10K_0402_5% MEM_CONFIG2 @ RH56 2 1 10K_0402_5%

    @ RH57 2 1 10K_0402_5% MEM_CONFIG3 @ RH58 2 1 10K_0402_5% GPP_F14 MEM_CONFIG1 1 1 0 0 1 1 0 0 1


    @ RH59 2 1 10K_0402_5% MEM_CONFIG4 @ RH60 2 1 10K_0402_5% 2133 Mbps
    GPP_F15 MEM_CONFIG2 0 0 1 1 1 1 0 0 0

    GPP_F16 MEM_CONFIG3 0 0 0 0 0 0 1 1 1
    A A

    GPP_F17 MEM_CONFIG4 1 1 1 1 1 1 1 1 1

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P07-MCP(1/14)DDI,EDP,CSI2,EMMC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 7 of 61
    5 4 3 2 1
    5 4 3 2 1

    LPDDR3, Ballout for side by side(Non-Interleave)

    SKL-U
    @ UCPU1B SKL-U @ UCPU1C

    <21> DDR_A_D[0..15] DDR_A_D0


    DDR_A_D1
    AL71
    AL68 DDR0_DQ[0]
    Vinafix.com DDR0_CKN[0]
    DDR0_CKP[0]
    AU53
    AT53
    AU55
    DDR_A_CLK#0
    DDR_A_CLK0
    DDR_A_CLK#1
    DDR_A_CLK#0
    DDR_A_CLK0
    <21,23>
    <21>
    <21,23>
    DDR_A_D[16..31] DDR_A_D16
    DDR_A_D17
    AF65
    AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0]
    AN45
    AN46
    DDR_B_CLK#0
    DDR_B_CLK#1 DDR_B_CLK#0 <22,23>
    DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <21,23> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <22,23>
    D DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <21,23> DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <22,23> D
    DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <22,23>
    DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <21,23> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
    DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <21,23> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <22,23>
    DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 DDR_A_CKE2 <21,23> DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <22,23>
    DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] DDR_A_CKE3 <21,23> DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 DDR_B_CKE2 <22,23>
    DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] DDR_B_CKE3 <22,23>
    DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <21,23> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
    DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <21,23> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <22,23>
    DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT0 <21,23> DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <22,23>
    DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT0 <22,23>
    DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
    DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_CA1_0 <21,23> DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
    <21> DDR_A_D[32..47] DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_CA1_1 <21,23>
    <21> DDR_A_D[48..63] DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_CA1_0 <22,23>
    DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_CA1_2 <21,23> DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_CA1_1 <22,23>
    DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_CA1_3 <21,23> DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_CA1_2 <22,23>
    DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_CA1_4 <21,23> DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_CA1_3 <22,23>
    DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_CA1_5 <21,23> DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_CA1_4 <22,23>
    DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_CA1_6 <21,23> DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_CA1_5 <22,23>
    DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_CA1_7 <21,23> DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_CA1_6 <22,23>
    DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_CA1_8 <21,23> DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_CA1_7 <22,23>
    DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_CA1_9 <21,23> DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_CA1_8 <22,23>
    DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_CA1_9 <22,23>
    DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CA2_0 <21,23> DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
    DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_CA2_1 <21,23> DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CA2_0 <22,23>
    DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_CA2_2 <21,23> DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_CA2_1 <22,23>
    DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_CA2_3 <21,23> DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_CA2_2 <22,23>
    DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_CA2_4 <21,23> DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_CA2_3 <22,23>
    DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_CA2_5 <21,23> DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_CA2_4 <22,23>
    <22> DDR_B_D[0..15] DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_CA2_6 <21,23>
    <22> DDR_B_D[16..31] DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_CA2_5 <22,23>
    DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_CA2_7 <21,23> DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_CA2_6 <22,23>
    DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_CA2_8 <21,23> DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_CA2_7 <22,23>
    C DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_CA2_9 <21,23> DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_CA2_8 <22,23> C
    DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_CA2_9 <22,23>
    DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47
    DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
    DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS#0 <21> DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66
    DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS0 <21> DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS#2 <21>
    DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS#1 <21> DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS2 <21>
    DDR_B_D10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS1 <21> DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS#3 <21>
    DDR_B_D11 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS#4 <21> DDR_B_D27 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS3 <21>
    DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS4 <21> DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS#6 <21>
    DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS#5 <21> DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS6 <21>
    DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS5 <21> DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS#7 <21>
    DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS#0 <22> DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_A_DQS7 <21>
    <22> DDR_B_D[32..47] DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS0 <22> <22> DDR_B_D[48..63] DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS#2 <22>
    DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS#1 <22> DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS2 <22>
    DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS1 <22> DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS#3 <22>
    DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS#4 <22> DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS3 <22>
    DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS4 <22> DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS#6 <22>
    DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS#5 <22> DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS6 <22>
    DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_DQS5 <22> DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS#7 <22>
    DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <22>
    DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 PAD~D @ T3 DDR_B_D56 AT22 DDR1_DQ[55] AN43
    DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR PAD~D @ T4 DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 PAD~D @ T5
    DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 PAD~D @ T6
    DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 +V_DDR_REF_CA <23> DDR_B_D59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0 PAD~D @ T7
    DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 +V_DDR_REFA_R <23> DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
    DDR CH - A
    DDR_B_D45 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +V_DDR_REFB_R <23> DDR_B_D61 AP22 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] AU18 SM_RCOMP2
    DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
    DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
    DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]

    SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
    B B

    +1.2V_DDR
    LPDDR3 COMPENSATION SIGNALS
    UC9
    1 5 SM_RCOMP0 RC11 1 2 200_0402_1%
    NC VCC
    DDR_VTT_CNTL 2 SM_RCOMP1 RC12 1 2 80.6_0402_1%
    A 1
    4 @ +3VS
    3 Y CC92 SM_RCOMP2 RC13 1 2 162_0402_1%
    GND 0.1U_0402_10V7K
    1

    SN74AUP1G07DCKR_SC70 2 @
    @ RE241 CAD Note:
    100K_0402_5%
    Trace width=12~15 mil, Spacing=20 mils
    Max trace length= 500 mil
    2

    1 @ 2
    RC383 0_0402_1% SM_PG_CTRL <52>

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P08-MCP(2/14)LPDDR3
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 8 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    PVT_0008
    SPI_MOSI= SPI_IO0
    SPI_MISO= SPI_IO1 RC388 1 @ 2 0_0402_1%
    PCH EDS R0.7 p.235~236 SKL-U

    2
    @ UCPU1E
    SPI - FLASH
    SMBUS, SMLINK
    MEM_SMBCLK 6 1 DDR_XDP_SMBCLK
    PCH_SPI_CLK AV2 DDR_XDP_SMBCLK <15>
    PCH_SPI_SO AW3 SPI0_CLK R7 MEM_SMBCLK @ QC1A

    Vinafix.com SPI0_MISO GPP_C0/SMBCLK

    5
    PCH_SPI_SI AV3 R8 MEM_SMBDATA DMN66D0LDW-7_SOT363-6
    <15> PCH_SPI_SI PCH_SPI_IO2 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 PCH_SMB_ALERT#
    <15> PCH_SPI_IO2 PCH_SPI_IO3 AU4 SPI0_IO2 GPP_C2/SMBALERT# MEM_SMBDATA 3 4 DDR_XDP_SMBDAT
    PCH_SPI_CS0# AU3 SPI0_IO3 R9 DDR_XDP_SMBDAT <15>
    D AU2 SPI0_CS0# GPP_C3/SML0CLK W2 PWR_MONITOR_SMBCLK <35> D
    @ QC1B
    AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 PWR_MONITOR_SMBDAT <35>
    <27> PCH_SPI_CS2# DMN66D0LDW-7_SOT363-6
    SPI0_CS2# GPP_C5/SML0ALERT# +3VS
    W3 SML1_SMBCLK RC387 1 @ 2 0_0402_1%
    SPI - TOUCH GPP_C6/SML1CLK V3 SML1_SMBDAT SML1_SMBCLK <38>
    M2 GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDAT <38> DDR_XDP_SMBDAT 2 1
    M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# 2.2K_0402_5% RN1
    <27> TPM_PIRQ# J4 GPP_D2/SPI1_MISO DDR_XDP_SMBCLK 2 1
    V1 GPP_D3/SPI1_MOSI 2.2K_0402_5% RN2
    V2 GPP_D21/SPI1_IO2 CLKRUN# 2 1
    MEDIACARD_IRQ# M1 GPP_D22/SPI1_IO3 8.2K_0402_5% RC16
    LPC
    <29> MEDIACARD_IRQ# GPP_D0/SPI1_CS# AY13 ESPI_IO0_R RC3661 2 15_0402_5%
    GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <38,39>
    +3V_PCH RC3671 2 15_0402_5%
    C LINK GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <38,39>
    RC3681 2 15_0402_5% ESPI_IO2 <38,39>
    G3 GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3691 2 15_0402_5%
    MEDIACARD_IRQ# <28> CL_CLK CL_CLK GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <38,39>
    @ RC17 1 2 10K_0402_5% G2 BA12
    <28> CL_DAT G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <38,39>
    <28> CL_RST# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <38>
    +3.3V_1.8V_ESPI +3V_PCH
    SIO_RCIN# AW13 AW9 PCI_CLK_LPC0 RC19 1 2 15_0402_5% EMC@
    @ RC21 1 2 10K_0402_5% SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 RC22 1 2 22_0402_5% @ ESPI_CLK_5105 <38,39>
    ESPI_ALERT# AY11 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# MEM_SMBCLK 1 2
    ESPI_ALERT# <38> ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/CLKRUN#
    RC24 1 2 10K_0402_1% @ RC18 1K_0402_5%
    MEM_SMBDATA 1 2
    SKL-U_BGA1356 5 OF 20 @ RC20 1K_0402_5%
    SML1_SMBCLK 1 2
    RC23 1K_0402_5%
    SML1_SMBDAT 1 2
    RC25 1K_0402_5%

    C C

    RP1 ESPI_CLK_5105 2 1 +3V_PCH


    SPI_SI_VROM 1 8 PCH_SPI_SI_R 12P_0402_50V8J EMC@
    SPI_CLK_VROM 2 7 PCH_SPI_CLK_R CC2
    3 6
    <27>
    <27>
    PCH_SPI_CLK_TPM
    PCH_SPI_SI_TPM
    4 5 Reserve for RF PCH_SMB_ALERT# 1 2
    RC26 2.2K_0402_5%
    33_8P4R_5%
    PVT_0012 TLS CONFIDENTIALITY
    HIGH ENABLE
    +3V_PCH RP2
    1 8 PCH_SPI_SO_R LOW(DEFAULT) DISABLE
    <27> PCH_SPI_SO_TPM SPI_SO_VROM
    CC4 2 7
    SPI_IO2_VROM PCH_SPI_IO2_R
    ROM is Quad SPI
    1 2 3 6
    SPI_IO3_VROM 4 5 PCH_SPI_IO3_R
    0.1U_0402_25V6
    U1 33_8P4R_5% +3V_PCH
    PCH_SPI_CS0#_R 1 8
    SPI_SO_VROM 2 CS# VCC 7 SPI_IO3_VROM
    SPI_IO2_VROM 3 DO HOLD#_RESET# 6 SPI_CLK_VROM
    4 WP# CLK 5 SPI_SI_VROM GPP_C5 RC27 1 2 4.7K_0402_5%
    GND DI SPI_CLK_VROM
    +3V_PCH
    W25Q256FVEIQ_WSON8

    2
    33_0402_5%
    PCH_SPI_IO2 EC interface
    @ RC28
    @ RH61 1 2 1K_0402_5%~D

    B
    SPI ROM FOR ME ( 32 MByte ) @ RH62 1 2 1K_0402_5%~D PCH_SPI_IO3
    HIGH
    LOW(DEFAULT)
    ESPI
    LPC B
    1
    33P_0402_50V8J

    @ RH63 1 2 1K_0402_5%~D PCH_SPI_IO3


    2

    @ CC5

    +3V_PCH
    1

    @ RC29
    GPP_B23 1 2
    from CPU to SPI ROM
    JSPI1 Option 1: Implement a 1 k Ohm pull-down resistor on the signal and de-populate the 150K_0402_1%
    1 required 1 kOhm pull-up resistor(MOW WW5).
    2 1
    PCH_SPI_SI PCH_SPI_SI_R 2 In this case, customers must ensure that the SPI EXI BOOT STALL BYPASS
    RC30 1 @ 2 0_0402_1% 3
    4 3 flash device on the platform has HOLD functionality disabled by default.
    PCH_SPI_SO PCH_SPI_SO_R 4 HIGH ENABLE
    RC31 1 @ 2 0_0402_1% 5
    6 5 Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms LOW(DEFAULT) DISABLE
    PCH_SPI_CLK RC32 1 @ 2 0_0402_1% PCH_SPI_CLK_R 7 6
    8 7 with ES and SKL S/H platforms with pre-ES1/ES1 samples(MOW WW9).
    PCH_SPI_CS0# RC33 1 @ 2 0_0402_1% PCH_SPI_CS0#_R 9 8
    10 9
    PCH_SPI_IO2 PCH_SPI_IO2_R 10 RC29 DCI need pop 4.7 k ohm
    RC34 1 @ 2 0_0402_1% 11
    12 11
    PCH_SPI_IO3 RC35 1 @ 2 0_0402_1% PCH_SPI_IO3_R 13 12
    14 13
    15 14
    +3V_PCH 15
    RC36 1 @ 2 0_0402_1% 16
    RC37 1 2 0_0402_5% 17 16
    +3VALW 17
    @ 18
    19 18
    20 19
    Serial Peripheral Interface (SPI) Topology Guidelines 20
    A A
    21
    22 GND_1
    GND_2
    PCH SPI ACES_50696-0200M-P01
    CONN@
    DELL CONFIDENTIAL/PROPRIETARY
    TPM Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title
    P09-MCP(3/14)SPI,SMB,LPC
    JSPI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 9 of 61
    5 4 3 2 1
    5 4 3 2 1

    @ UCPU1F SKL-U

    LPSS ISH

    +3VS AN8
    <37> TS_I2C_RST# AP7 GPP_B15/GSPI0_CS# P2 +3VS

    Vinafix.com
    <37> DBC_EN AP8 GPP_B16/GSPI0_CLK GPP_D9 P3
    1 2 HOST_SD_WP# NRB_BIT AR7 GPP_B17/GSPI0_MISO GPP_D10 P4
    GPP_B18/GSPI0_MOSI GPP_D11 P1 DCI_CLK <31> DDR_CHA_EN 1 2 100K_0402_5%~D
    RC38 10K_0402_5% RH66
    TPM_DET AM5 GPP_D12 DCI_DATA <31>
    D 1 2 SIO_EXT_SCI# SIO_EXT_SCI# AN7 GPP_B19/GSPI1_CS# M4 DDR_CHB_EN RH67 1 2 100K_0402_5%~D D
    RC39 10K_0402_5% AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
    <33> 3.3V_TS_EN GPP_B22 AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL
    1 2 UART1_TXD GPP_B22/GSPI1_MOSI N1 DDR_CHA_EN @ RH68 1 2 SHORT PADS
    RH64 49.9K_0402_1% AB1 GPP_D7/ISH_I2C1_SDA N2
    AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL DDR_CHB_EN @ RH69 1 2 SHORT PADS
    1 2 UART1_RXD <39> SBIOS_TX W4 GPP_C9/UART0_TXD AD11
    RH65 49.9K_0402_1% HOST_SD_WP# AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
    <29> HOST_SD_WP# GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
    AD1
    AD2 GPP_C20/UART2_RXD U1 DDR_CHB_EN
    SIO_EXT_WAKE# AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 DDR_CHA_EN
    <38> SIO_EXT_WAKE# GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL BID_BC PVT_0011
    AD4 U3
    T8 @ PAD~D GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# PCH_TBT_PERST#
    change to net name ==> I2C0_SDA_TS and I2C0_SCK_TS U4
    GPP_D16/ISH_UART0_CTS#/SML0BALERT# PCH_TBT_PERST# <41> +3V_PCH
    U7 AC1 UART1_RXD
    <37> I2C0_SDA_TS GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD UART1_TXD
    TS U6 AC2 @ RC395
    <37> I2C0_SCK_TS GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 PCH_TBT_PERST# 2 1
    I2C1_SDA_TP U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 PCH_MUTE# <24>
    10K_0402_5%
    TP <36> I2C1_SDA_TP I2C1_SCK_TP U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# @
    <36> I2C1_SCK_TP GPP_C19/I2C1_SCL AY8 PCH_TBT_PERST# 1 2
    AH9 GPP_A18/ISH_GP0 BA8 PAD~D @ T9
    100K_0402_5%~D RH90
    +3V_PCH eDP <37> I2C2_SDA_EDP_PCH AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7 SUPPLIER_ID0
    <37> I2C2_SCK_EDP_PCH GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 SUPPLIER_ID1
    AH11 GPP_A21/ISH_GP3 AY7
    1 2 SIO_EXT_WAKE# PWRMONITOR <35> PWR_MONITOR_I2CSDA AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 TBT_PWR_EN
    RC40 10K_0402_5% <35> PWR_MONITOR_I2CCLK GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13
    AF11 GPP_A12/BM_BUSY#/ISH_GP6
    AF12 GPP_F8/I2C4_SDA +3V_PCH
    change to net name ==> I2C2_SDA_EDP_PCH and I2C2_SCK_EDP_PCH
    GPP_F9/I2C4_SCL

    2
    SKL-U_BGA1356 6 OF 20
    C RH84 XPS@ C

    100K_0201_5%

    1
    BID_BC

    2
    +3V_PCH
    2 1 TBT_PWR_EN RH85 L@
    RH70 100K_0402_5%~D TPM_DET 100K_0402_5% 2 1 RH71 Product POP STATUS 100K_0201_5%
    XPS RH84 High
    TPM_DET 100K_0402_5% 1 2 RH72 @ L RH85 Low

    1
    TPM BOM Optional +3.3V_1.8V_PGPPA +3.3V_1.8V_PGPPA
    TPM_DET
    +3V_PCH

    2
    TPM 1 = W/TPM
    1 2 NRB_BIT 0 = W/O TPM 100K_0402_5% 100K_0402_5%
    @ RC45 2.2K_0402_5% RH87 RH86

    1
    SUPPLIER_ID1 @ SUPPLIER_ID0 @
    NO REBOOT STRAP
    HIGH No REBOOT

    2
    B LOW(DEFAULT) REBOOT ENABLE B
    +5VS 100K_0402_5% 100K_0402_5%
    Weak IPD RH88 RH89
    JUART1

    1
    1
    UART1_TXD 2 1
    UART1_RXD 3 2
    4 3
    4
    5
    6 GND
    GND RH87 RH88 RH86 RH89 REV
    +3V_PCH
    CVILU_CI1804M1VRA-NH V V 00 Supplier A
    CONN@ *
    V V 01 Supplier B
    1

    @
    2.2K_0402_5% V V 10 Supplier C
    RC46
    V V 11 Supplier D
    2

    GPP_B22

    BOOT BIOS Dest i nat i on(Bi t 6


    )
    HIGH LPC
    LOW(DEFAULT) SPI

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P10-MCP(4/14)GSPI,I2C,UART,ISH
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 10 of 61
    5 4 3 2 1
    5 4 3 2 1

    @ UCPU1H SKL-U

    Vinafix.com PCIE/USB3/SATA
    SSIC / USB3

    USB3_1_RXN
    H8
    G8
    USB3RN1
    USB3RP1
    <31>
    <31>
    H13 USB3_1_RXP C13
    D <29> PCIE_PRX_CARDTX_N1
    G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
    USB3TN1 <31> USB3.0 DP MX (PS8743B) D
    Cardreader <29> PCIE_PRX_CARDTX_P1
    B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3TP1 <31>
    PCIe Gen2 x 1 <29> PCIE_PTX_CARDRX_N1
    A17 PCIE1_TXN/USB3_5_TXN J6
    <29> PCIE_PTX_CARDRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
    G11 USB3_2_RXP/SSIC_1_RXP B13
    F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
    D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
    C16 PCIE2_TXN/USB3_6_TXN J10
    PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
    H16 USB3_3_RXP/SSIC_2_RXP B15
    <28> PCIE_PRX_WLANTX_N3 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN
    G16 A15
    WLAN <28> PCIE_PRX_WLANTX_P3
    D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
    PCIe Gen2 x 1 <28> PCIE_PTX_WLANRX_N3
    C17 PCIE3_TXN E10
    <28> PCIE_PTX_WLANRX_P3 PCIE3_TXP USB3_4_RXN F10
    G15 USB3_4_RXP C15
    F15 PCIE4_RXN USB3_4_TXN D15
    B19 PCIE4_RXP USB3_4_TXP
    A19 PCIE4_TXN AB9
    PCIE4_TXP USB2N_1 USB20_N1 <45>
    AB10 USB2.0 for USB PD PORT3
    USB2P_1 USB20_P1 <45>
    F16
    <41> PCIE_PRX_TBTX_N5 PCIE5_RXN
    E16 AD6
    <41> PCIE_PRX_TBTX_P5 PCIE5_RXP USB2N_2
    C19 AD7
    <41> PCIE_PTX_TBRX_N5 PCIE5_TXN USB2P_2
    D19
    <41> PCIE_PTX_TBRX_P5 PCIE5_TXP AH3
    G18 USB2N_3 AJ3
    <41> PCIE_PRX_TBTX_N6 PCIE6_RXN USB2P_3
    F18
    <41> PCIE_PRX_TBTX_P6 PCIE6_RXP
    D20 AD9
    <41> PCIE_PTX_TBRX_N6 PCIE6_TXN USB2N_4
    C20 AD10
    <41> PCIE_PTX_TBRX_P6 PCIE6_TXP USB2P_4
    Alpine Ridge F20 AJ1
    PCIe Gen3 x 4 <41> PCIE_PRX_TBTX_N7
    E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2
    USB20_N5 <37>
    <41> PCIE_PRX_TBTX_P7
    B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <37> CAM & IR CAM
    <41> PCIE_PTX_TBRX_N7 USB2
    C A21 PCIE7_TXN/SATA0_TXN AF6 C
    <41> PCIE_PTX_TBRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
    G21 USB2P_6
    <41> PCIE_PRX_TBTX_N8 PCIE8_RXN/SATA1A_RXN
    F21 AH1
    <41> PCIE_PRX_TBTX_P8 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 <28>
    D21 AH2
    <41> PCIE_PTX_TBRX_N8
    C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <28> NGFF (WLAN)
    <41> PCIE_PTX_TBRX_P8 PCIE8_TXP/SATA1A_TXP AF8
    E22 USB2N_8 AF9
    <30> PCIE_PRX_SSDTX_N9 PCIE9_RXN USB2P_8
    E23
    <30> PCIE_PRX_SSDTX_P9 PCIE9_RXP
    B23 AG1
    <30> PCIE_PTX_SSDRX_N9 PCIE9_TXN USB2N_9
    A23 AG2
    <30> PCIE_PTX_SSDRX_P9 PCIE9_TXP USB2P_9
    F25 AH7
    <30> PCIE_PRX_SSDTX_N10 PCIE10_RXN USB2N_10 USB20_N10 <36>
    E25 AH8 Fingerprint
    <30> PCIE_PRX_SSDTX_P10 PCIE10_RXP USB2P_10 USB20_P10 <36>
    D23
    <30> PCIE_PTX_SSDRX_N10 PCIE10_TXN
    C23 AB6 USBCOMP RC47 1 2 113_0402_1%
    <30> PCIE_PTX_SSDRX_P10 PCIE10_TXP USB2_COMP USB2_ID
    AG3 RC48 1 @ 2 0_0402_1%
    M.2 SSD PCIE_RCOMPN F5 USB2_ID AG4 VBUSSENSE RC49 1 2 1K_0402_5%
    PCIe Gen3 x 4 PCIE_RCOMPN USB2_VBUSSENSE PVT_0008
    RC50 1 2 100_0402_1% PCIE_RCOMPP E5
    PCIE_RCOMPP A9 TBT_A_USB_OC0#
    D56 GPP_E9/USB2_OC0# C9 TBT_B_USB_OC1# TBT_A_USB_OC0# <43>
    <15> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 MUX_C_USB_OC2# TBT_B_USB_OC1# <44>
    <15> CPU_XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# MUX_C_USB_OC2# <45>
    GPP_A7/PIRQA# GPP_E12/USB2_OC3#
    E28 J1 @ RC389 1 2 0_0402_5%
    <30> PCIE_PRX_SSDTX_N11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 B+_CAM_EN <37,38>
    E27 J2
    <30> PCIE_PRX_SSDTX_P11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
    D24 J3
    <30> PCIE_PTX_SSDRX_N11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SSD_DEVSLP <30>
    C24
    <30> PCIE_PTX_SSDRX_P11 PCIE11_TXP/SATA1B_TXP
    E30 H2 @
    <30> SATA_PRX_SSDTX_N2 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1
    F30 H3 1 2
    <30> SATA_PRX_SSDTX_P2 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
    A25 G4 RC52 0_0201_5%
    SATA SSD <30> SATA_PTX_SSDRX_N2
    B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SSD_IFDET <30>
    B <30> SATA_PTX_SSDRX_P2 PCIE12_TXP/SATA2_TXP B
    H1
    GPP_E8/SATALED#

    SKL-U_BGA1356 8 OF 20
    +3V_PCH

    TBT_A_USB_OC0# 1 2
    RC53 10K_0402_5%
    TBT_B_USB_OC1# 1 2
    RC54 10K_0402_5%
    MUX_C_USB_OC2# 1 2
    RC55 10K_0402_5%
    USB_OC3# 1 2
    RC56 10K_0402_5%

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P11-MCP(5/14)PCIE,USB,SATA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 11 of 61
    5 4 3 2 1
    5 4 3 2 1

    CC6
    1 2
    SUSCLK 1 2
    @ RC57 1K_0402_5% U22U23@ U22U23@ 15P_0402_50V8J

    2
    1M_0402_1%
    U22U23@

    3
    4
    RC59
    @ UCPU1J SKL_ULT
    YC1
    CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H
    U22U23@

    1
    2
    D42
    Alpine Ridge--->
    <41>
    <41>
    <41>
    CLK0_PCIE_TBT#
    CLK0_PCIE_TBT
    CLKREQ_PCIE#0
    +3VS RC58 1
    Vinafix.com
    2 10K_0402_5%
    C42
    AR10
    CLKOUT_PCIE_N0
    CLKOUT_PCIE_P0
    GPP_B5/SRCCLKREQ0#
    XTAL24_IN
    XTAL24_OUT
    RC375
    RC376
    2
    2
    1 33_0201_1%
    1 33_0201_1%
    CC7
    1 2

    B42 U22U23@ 15P_0402_50V8J


    D <28> CLK1_PCIE_WLAN# A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N_R RC60 1 EMC@2 47_0402_5% U22U23@ D
    WLAN---> <28> CLK1_PCIE_WLAN AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P_R RC61 1 EMC@2 47_0402_5%
    CLK_ITPXDP_N <15>
    <28> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P <15>
    RC62 1 2 10K_0402_5%
    +3VS
    D41 BA17 SUSCLK
    C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <28,30>
    CC8
    @ RC63 1 2 10K_0402_5% AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN EMC@ CC93 2 1 0.1U 16V K X5R 0201 PCH_RTCX1 1 2
    +3VS GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT PCH_RTCX2
    E35
    D40 XTAL24_OUT 6.8P_0402_50V8J
    <30> CLK_PCIE_SSD# C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
    SDD---> <30> CLK_PCIE_SSD CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK

    1
    AT10 RC64 2.7K_0402_1%
    <30> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# PCH_RTCX1
    PVT_0011 RC65 1 2 10K_0402_5% AM18 RC66 YC2
    +3VS RTCX1 PCH_RTCX2
    B40 AM20 10M_0402_5% 9PF 20PPM 9H03280012
    A40 CLKOUT_PCIE_N4 RTCX2 ESR MAX=50k ohm
    <30> CLKREQ_PCIE#4

    2
    @ RC67 1 2 10K_0402_5% AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# RC68 1 2 20K_0402_5%
    +3VS +RTCVCC

    1
    GPP_B9/SRCCLKREQ4# SRTCRST# AM16 CC10
    E40 RTCRST# CC9 1 2 1U_0402_6.3V6K 1 @ 2 PCH_RTCX2_R 1 2
    <29> CLK_PCIE_MMI# E38 CLKOUT_PCIE_N5
    Card Reader ---> <29> CLK_PCIE_MMI AU7 CLKOUT_PCIE_P5 RC69 0_0402_1% 6.8P_0402_50V8J
    <29> CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5# PCH_RTCRST#
    RC70 1 2 10K_0402_5% RC71 1 2 20K_0402_5%
    +3VS
    PVT_0008
    CC11 1 2 1U_0402_6.3V6K

    +3VA_TBT SKL-U_BGA1356 10 OF 20

    1 2
    1 2 PCH_PCIE_WAKE# 1 2
    @ RC396 1K_0402_5%
    SHORT PADS~D
    @ CMOS1

    +3V_PCH_DSW CMOS1 must take care short & touch risk on layout placement
    C +3VS C

    1 2 PCH_PCIE_WAKE#
    RC73 1K_0402_5%

    5
    +3VS PVT_0002
    1 2 LAN_WAKE# 1 PCH_PLTRST#

    P
    RC74 10K_0402_5% 4 B
    <27,28,29,30,39,41> PCH_PLTRST#_EC O
    5

    UC10 2
    A

    G
    1
    1 UC2
    P

    <56> IMVP_VR_PG B

    2
    4 IMVP_VR_PG_R RC76 TC7SH08FU_SSOP5~D

    3
    2 O RC77 @
    A 100K_0402_5%
    G

    10K_0402_5%
    TC7SH08FU_SSOP5~D +RTCVCC
    3

    2
    PVT_0002

    1
    @ RC390 INTRUDER# 1 2
    1 2 RC78 1M_0402_5%
    0_0402_5%
    +1.0V_VCCST +3V_PCH_DSW +3V_PCH

    1 2 H_VCCST_PWRGD_P
    RC79 1K_0402_5% PCH_BATLOW# 1 2 VRALERT# 1 2
    1 2 IMVP_VR_PG_R RC80 8.2K_0402_5% RC81 10K_0402_5%
    +3V_PCH AC_PRESENT 1 2
    RC381 10K_0402_5% RC82 10K_0402_5%
    1 2 ME_SUS_PWR_ACK @ UCPU1K SKL-U
    @ RC83 10K_0402_5%
    SYSTEM POWER MANAGEMENT
    AT11 SIO_SLP_S0#
    GPP_B12/SLP_S0# AP15 SIO_SLP_S3# SIO_SLP_S0# <27,34,60>
    PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S4# SIO_SLP_S3# <36,38,39,41>
    SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S5# SIO_SLP_S4# <36,38>
    B PCH_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <38> B
    <15,38> PCH_RSMRST# RSMRST# AN15
    H_CPUPWRGD_R @ RC85 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <33,36,38,53,54,60>
    T10 @ PAD~D H_VCCST_PWRGD_P PROCPWRGD SLP_LAN# PAD~D @ T11
    RC86 1 2 60.4_0402_1% VCCST_PWRGD B65 BB17
    <15,36,38,39> H_VCCST_PWRGD_P VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_WLAN# <38>
    B6 GPD6/SLP_A# SIO_SLP_A# <38>
    <15,38> SYS_PWROK IMVP_VR_PG_R BA20 SYS_PWROK BA15
    SIO_PWRBTN# <12,15,38>
    APS CONN
    BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT
    H_CPUPWRGD H_VCCST_PWRGD_P <39> PCH_DPWROK_R DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# AC_PRESENT <38>
    JAPS1
    ME_SUS_PWR_ACKAR13 GPD0/BATLOW# 1
    <38> ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK +3V_PCH SIO_SLP_S3# 1
    100P_0402_50V8J~D

    100P_0402_50V8J~D

    AP11 2
    <38> SUSACK# GPP_A15/SUSACK# AU11 3 2
    PME#
    PCH_PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTRUDER# PAD~D @ T12 +3VALW SIO_SLP_S5# 4 3
    1 1 <38,39,41> PCH_PCIE_WAKE# LAN_WAKE# WAKE# INTRUDER# SIO_SLP_S4# 4
    CA1

    CA2

    AM15 5
    <38> LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 SIO_SLP_A# 6 5
    AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# MPHYP_PWR_EN <34> 7 6
    2 2 <33> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# +3V_PCH 7
    8
    PCH_RTCRST# 9 8
    <38> PCH_RTCRST# 10 9
    SKL-U_BGA1356 11 OF 20
    EMC@ EMC@ 11 10
    <12,15,38> SIO_PWRBTN# 12 11
    +3VS SYS_RESET# 13 12
    ESD Request:place near CPU side
    14 13
    SIO_SLP_S0# 14
    10K_0402_5%
    15
    15
    1

    16
    16
    RC88

    17
    RC90 18 17
    19 18
    POP NO Support Deep sleep 20 GND
    DE-POP Support Deep sleep
    2

    GND
    1 @ 2 SYS_RESET#_R 1 2 SYS_RESET# CONN@
    PCH_DPWROK_R1 2 PCH_RSMRST# <15> PM_SYS_RESET#
    RC87 0_0402_1% RC89 1K_0402_5% ACES_50506-01841-P01
    A @ RC90 0_0402_5% A
    1
    0.01U_0402_16V7K

    100K_0402_5%~D

    1
    CC12

    RC92

    2 DELL CONFIDENTIAL/PROPRIETARY
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P12-MCP(6/14)CLK,PM,RTC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 12 of 61
    5 4 3 2 1
    5 4 3 2 1

    Vinafix.com
    D D

    Service Mode Switch:


    Add a switch to ME_FWP signal to unlock the ME region and
    allow the ent ir e r egi on of t he SPI f l ash to be updat ed us i ng FPT.
    +3VS_AUDIO

    1
    RC110 @
    1K_0402_5%

    SW1 @

    2
    C HDA_SDOUT HDA_SDIN0 HDA_RST# 1 C
    HDA_SDOUT 1K_0402_5%~D 2 1 RH73 ME_EN 2
    3
    0_0402_1%2 @ 1 R1
    2 2 2 4 G
    RF@ RF@ RF@ 5
    <38> ME_FWP_EC G
    CR24 CR25 CR26
    2.2P_0201_25V 2.2P_0201_25V 2.2P_0201_25V SSAL120100_3P
    1 1 1
    ME_FWP PCH has internal 20K PD.
    FLASH DESCRIPTOR SECURITY OVERRIDE
    Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short
    @ UCPU1G SKL-U Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default posit i on)
    AUDIO

    RC111 1 2 33_0402_5% HDA_SYNC BA22


    <24> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
    RC112 33_0402_5%
    <24> HDA_BIT_CLK_R 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
    RC113 33_0402_5% SDIO/SDXC
    <24> HDA_SDOUT_R HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
    <24> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11 CAM_CBL_DET#
    HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_CBL_DET# <37>
    PAD~D @ T15
    J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
    <41> RTD3_USB_PWR_EN GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 TBT_CIO_PLUG_EVENT# <41>
    AY20 W12
    HDA_BIT_CLK_R AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 SSD_PWR_EN <33> +3VS
    I2S1_TXD GPP_G4/SD_DATA3 W10
    AK7 GPP_G5/SD_CD# W8 CAM_CBL_DET# 1 2
    1 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
    AK6 W7 RC114 100K_0402_5%~D
    AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP SPK_DET# <25>
    CC13
    B AK10 GPP_F2/I2S2_TXD BA9 B
    22P_0402_50V8J GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
    2 BB9
    GPP_A16/SD_1P8_SEL
    RC115 2 @ 1 0_0402_1% PCH_RTD3_CIO_PWR_ENH5 AB7 SD_RCOMPRC116 1 2 200_0402_1%
    <41> RTD3_CIO_PWR_EN 2 1 0_0402_1% PCH_TBT_FORCE_PWR D7 GPP_D19/DMIC_CLK0 SD_RCOMP
    Close to RC112 RC117 @
    <41> TBT_FORCE_PWR GPP_D20/DMIC_DATA0
    D8 AF13
    <41> TBT_BATLOW# KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
    <35> KB_DET# GPP_D18/DMIC_DATA1
    SPKR AW5
    <24> SPKR GPP_B14/SPKR

    +3V_PCH
    SKL-U_BGA1356 7 OF 20

    1 2 KB_DET#
    RC41 100K_0402_5%~D

    +3V_PCH +3V_PCH

    A 1 2 SPKR 1 2 HDA_SDOUT A
    @ RC118 2.2K_0402_5% @ RC119 4.7K_0402_5%

    TOP SWAP STRAP Flash Descriptor Security override DELL CONFIDENTIAL/PROPRIETARY


    HIGH ENABLE HIGH DISABLE Security Classification Compal Secret Data Compal Electronics, Inc.
    LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P13-MCP(7/14)MISC,JTAG,HDA,SDIO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 13 of 61
    5 4 3 2 1
    5 4 3 2 1

    Vinafix.com
    DG Note:
    CAZ60 layout at DVT2 remove it XDP nets
    D D

    <15> CFG[0..15]

    @ UCPU1S SKL-U
    @ UCPU1T SKL-U
    RESERVED SIGNALS-1
    1 2 CFG0 SPARE
    @ RC120 10K_0402_1% 10K_0402_1% T80@ CFG0 E68 BB68
    1 2PAD~D CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T16 AW69 F6
    CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T17 AW68 RSVD_AW69 RSVD_F6 E3 XTAL24_IN_RU
    @ RC121 T78@ PAD~D
    1 2 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 RSVD_E3 C11
    CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T18 AW48 RSVD_AU56 RSVD_C11 B11
    @ RC122 T81@ PAD~D
    C68 CFG[4] RSVD_TP_AK12 PAD~D @ T19 XTAL24_OUT_RU C7 RSVD_AW48 RSVD_B11 A11
    10K_0402_1% T79@ CFG5
    PAD~D CFG6 D68 CFG[5] BB2 U12 RSVD_C7 RSVD_A11 D12
    Stall reset sequence T82@ PAD~D
    CFG7 C67 CFG[6] RSVD_BB2 BA3 U11 RSVD_U12 RSVD_D12 C12
    T83@ PAD~D CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12
    CFG8 F71 H11 F52
    HIGH(DEFAULT) No stall(Normal Operat i on) T84@ PAD~D
    CFG9 G69 CFG[8] RSVD_H11 RSVD_F52
    LOW stall T85@ PAD~D CFG[9]
    CFG10 F70 AU5
    T86@ PAD~D
    CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T20
    T87@ PAD~D
    CFG12 H70 CFG[11] TP6 PAD~D @ T21
    <15> CFG12 SKL-U_BGA1356 20 OF 20
    CFG13 G71 CFG[12]
    T88@ PAD~D CFG[13]
    <15> CFG14 CFG14 H69 D5
    CFG15 G70 CFG[14] RSVD_D5 D4
    T89@ PAD~D CFG[15] RSVD_D4 B2 Support for KBL-R U4+2
    E63 RSVD_B2 C2 CC91
    <15> CFG16 CFG[16] RSVD_C2
    <15> CFG17 F63 1 2
    CFG[17] B3
    E66 RSVD_B3 A3 U42@ 15P_0402_50V8J
    <15> CFG18 CFG[18] RSVD_A3
    <15> CFG19 F66 U42@
    CFG[19]

    3
    4
    1M_0402_1%
    C 1 2 CFG4 AW1 C
    CFG_RCOMP E60 RSVD_AW1

    RC374
    RC123 1K_0402_5% 2 1 YC3
    RC124 49.9_0402_1% CFG_RCOMP E1 24MHZ_12PF_X3G024000DC1H
    2 1 E8 RSVD_E1 E2
    +1.0VA_XDP

    1
    2
    RC125 1.5K_0402_5% ITP_PMODE RSVD_E2 U42@

    1
    AY2 BA4 XTAL24_IN_RU RC377 2 1 33_0201_1% U42@ CC90
    AY1 RSVD_AY2 RSVD_BA4 BB4 XTAL24_OUT_RU RC378 2 1 33_0201_1% 1 2
    <15> XDP_ITP_PMODE RSVD_AY1 RSVD_BB4
    eDP enable D1 A4 U42@ 15P_0402_50V8J
    D3 RSVD_D1 RSVD_A4 C4
    HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4 U42@
    LOW Enabled K46 BB5
    K45 RSVD_K46 TP4 PAD~D @ T22
    RSVD_K45 A69
    AL25 RSVD_A69 B69
    AL27 RSVD_AL25 RSVD_B69
    RSVD_AL27 AY3
    C71 RSVD_AY3
    B70 RSVD_C71 D71
    RSVD_B70 RSVD_D71 C70
    F60 RSVD_C70
    RSVD_F60 C54
    A52 RSVD_C54 D54
    RSVD_A52 RSVD_D54
    BA70 AY4
    T23 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T24
    BA68 BB3
    T25 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T26
    J71 AY71
    J68 RSVD_J71 VSS_AY71 AR56
    RSVD_J68 ZVM# LPM_ZVM_N <61> ZVM# for SKYLAKE-U 2+3e
    VSS_F65_G65 F65 AW71
    G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T27
    B VSS_G65 RSVD_TP_AW70 PAD~D @ T28 B
    F61 AP56
    RSVD_F61 MSM# MSM_N <61> MSM# for SKYLAKE-U 2+3e
    2

    U42@ E61 C64 1 2


    RSVD_E61 PROC_SELECT# +1.0V_VCCST
    RC391 RC126 100K_0402_5%
    0_0201_5%
    SKL-U_BGA1356 19 OF 20
    1

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P14-MCP(8/14)CFG,RSVD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 14 of 61
    5 4 3 2 1
    5 4 3 2 1

    +1.0V_VCCST

    RC2181 2 1K_0402_1% H_THERMTRIP#_R

    @ RC2191 2 49.9_0402_1% H_CATERR# @ UCPU1D SKL-U

    D63 H_CATERR#
    +1.0V_VCCSTG A54 CATERR#
    <38> PECI_EC H_PROCHOT#RC2201 2 499_0402_1% H_PROCHOT#_R C65 PECI

    Vinafix.com
    H_PROCHOT# <38,50,56> H_PROCHOT# PROCHOT# JTA G
    RC2211 2 1K_0402_1% RC2221 2 60.4_0402_1% H_THERMTRIP#_R C63
    <39> H_THERMTRIP# THERMTRIP# CPU_XDP_TCK
    RC2232 @ 1 0_0402_5% SKTOCC# A65 B61
    +3V_PCH SKTOCC# PROC_TCK D60 CPU_XDP_TDI
    CPU MISC PROC_TDI
    XDP_BPM#0 C55 A61 CPU_XDP_TDO
    D RH81 1 2 10K_0201_5% SIO_EXT_SMI# XDP_BPM#1 D55 BPM#[0] PROC_TDO C60 CPU_XDP_TMS D
    T50 @ XDP_BPM#2_R B54 BPM#[1] PROC_TMS B59 CPU_XDP_TRST#
    +3VS T51 @ XDP_BPM#3_R C56 BPM#[2] PROC_TRST#
    BPM#[3] B56 PCH_JTAG_TCK
    @
    TOUCH_SCREEN_PD#
    PVT_0008 SIO_EXT_SMI# PCH_JTAG_TCK PCH_JTAG_TDI
    RH82 1 2 10K_0201_5% A6 D59
    TOUCH_SCREEN_PD# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO
    <37> TOUCH_SCREEN_PD# TOUCHPAD_INTR# GPP_E7/CPU_GP1 PCH_JTAG_TDO PCH_JTAG_TMS
    RC379 2 @ 1 0_0402_1% BA5 C59
    <36,38> TP_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST#
    <33> AUD_PWR_EN GPP_B4/CPU_GP3 PCH_TRST# A59 PCH_JTAGX
    PVT_0018 CPU_POPIRCOMP AT16 JTAGX
    PCH_POPIRCOMP AU16 PROC_POPIRCOMP
    EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
    EOPIO_RCOMP H65 OPCE_RCOMP
    OPC_RCOMP

    1
    49.9_0402_1%

    49.9_0402_1%

    49.9_0402_1%

    49.9_0402_1%
    RC106

    RC107

    RC108

    RC109
    SKL-U_BGA1356 4 OF 20

    +3V_PCH

    2
    RC2251 XDP@ 2 100K_0201_5% XDP_PRSENT#

    +1.0VA_XDP

    RC2261 XDP@ 2 1K_0402_5% XDP_RST#

    CPU_XDP_TDO RC2271 XDP@ 2 0_0201_5% XDP_TDO


    +1.0V_VCCSTG CPU_XDP_TCK RC2281 XDP@ 2 0_0201_5% XDP_TCK0
    CPU_XDP_TDI RC2291 XDP@ 2 0_0201_5% XDP_TDI
    CPU_XDP_PREQ#
    <To CPU JTAG> CPU_XDP_TMS XDP_TMS
    @ RC2302 1 51_0402_5% RC2311 XDP@ 2 0_0201_5%
    CPU_XDP_TRST# RC2321 XDP@ 2 0_0201_5% XDP_TRST#
    C C

    PCH_JTAG_TDO RC2331 XDP@ 2 0_0201_5% XDP_TDO


    PCH_JTAG_TDI RC2341 XDP@ 2 0_0201_5% XDP_TDI
    PCH_JTAG_TMS RC2351 XDP@ 2 0_0201_5% XDP_TMS
    PU/PD for CPU JTAG signals <To PCH JTAG> PCH_JTAG_TRST# XDP_TRST#
    RC2361 XDP@ 2 0_0201_5%
    PCH_JTAGX RC2371 XDP@ 2 0_0201_5% XDP_TCK0
    +1.0V_VCCSTG PCH_JTAG_TCK RC2381 XDP@ 2 0_0201_5% XDP_TCK1

    RC2392 1 51_0402_5% CPU_XDP_TMS Closed to CPU


    RC2402 1 51_0402_5% CPU_XDP_TDI RC3701 @ 2 0_0402_5%
    <12,38> SYS_PWROK
    <9> PCH_SPI_SI RC2411 XDP@ 2 1K_0201_5% RESET_OUT#_R
    R1 RC2421 2 100_0402_1% CPU_XDP_TDO RC2431 XDP@ 2 1K_0201_5% XDP_PRSENT#
    <9> PCH_SPI_IO2

    RC2442 1 51_0402_5% CPU_XDP_TCK


    R2 XDP_BPM#0 RC2451 XDP@ 2 0_0201_5% @ T70 XDP_OBS0
    @ RC2172 1 51_0402_5% CPU_XDP_TRST# XDP_BPM#1 RC2461 XDP@ 2 0_0201_5% @ T73 XDP_OBS1

    <XDP Misc.> +1.0VA +1.0VA_XDP +1.0VA_XDP


    RC2471 XDP@ 2 0_0201_5% XDP_PWRBTN# RC251
    <12,38> SIO_PWRBTN# XDP_DBRESET#
    <12> PM_SYS_RESET# RC2481 XDP@ 2 0_0201_5% 1 XDP@ 2
    RC2492 XDP@ 1 0_0402_5% XDP_RST# 0_0402_5%
    <14> XDP_ITP_PMODE PWRGD_XDP 1 1
    <12,38> PCH_RSMRST# RC2501 XDP@ 2 1K_0402_5% CC85 CC86
    @ RC3711 2 1K_0402_5% XDP@ XDP@

    PU/PD for PCH JTAG signals


    <12,36,38,39> H_VCCST_PWRGD_P
    XDP CONN 0.1U_0201_10V6K
    2 2
    0.1U_0201_10V6K

    Connect to XDP Conn.


    DG Note:
    +1.0V_VCCSTG (Option w/ CPU JTAG) CAZ60 layout at DVT2 remove it XDP nets +1.0VA_XDP +1.0VA_XDP
    RC253 JXDP1
    B RC2522 1 51_0402_5% PCH_JTAG_TMS CFG3_1 1 XDP@ 2 XDP_PIN1 1 2 B
    R5 CPU_XDP_PREQ# 1K_0402_1% 3 1 2 4
    <11> CPU_XDP_PREQ#
    R4 RC2542 1 51_0402_5% PCH_JTAG_TDI CPU_XDP_PRDY# 5 3 4 6 CFG17 <14>
    <11> CPU_XDP_PRDY#
    RC256 7 5 6 8 CFG16 <14>
    R3 RC2551 2 100_0402_1% PCH_JTAG_TDO CFG0_1 1 XDP@ 2 9 7 8 10 CFG8_1
    <14> CFG0 T112@ PAD~D CFG1_1 11 9 10 12 CFG9_1 PAD~D @ T102 CFG8 <14>
    1K_0402_1%
    <14> CFG1 T111@ PAD~D
    13 11 12 14 PAD~D @ T101 CFG9 <14>
    RC257 2 @ 1 51_0402_5% PCH_JTAGX CFG2_1 15 13 14 16 CFG10_1
    <14> CFG2 T113@ PAD~D CFG3_1 17 15 16 18 CFG11_1 PAD~D @ T122 CFG10 <14>
    PCH_JTAG_TCK <14> CFG3 T114@ PAD~D
    19 17 18 PAD~D @ T121 CFG11 <14>
    R6 RC258 2 @ 1 51_0402_5% 20
    XDP_OBS0_1 21 19 20 22
    T116@ PAD~D XDP_OBS1_1 23 21 22 24 CFG19 <14>
    T115@ PAD~D
    25 23 24 26 CFG18 <14>
    CFG4_1 27 25 26 28
    T117@ PAD~D
    <14> CFG4 CFG5_1 29 27 28 30 CFG13_1 CFG12 <14>
    <14> CFG5 T118@ PAD~D
    31 29 30 32 PAD~D @ T103 CFG13 <14>
    CFG6_1 33 31 32 34
    <14> CFG6 T120@ PAD~D CFG7_1 35 33 34 36 CFG15_1 CFG14 <14>
    2 1 RESET_OUT#_R <14> CFG7 T119@ PAD~D
    37 35 36 38 PAD~D @ T104 CFG15 <14>
    @ CC89 0.1U_0402_25V6 PWRGD_XDP 39 37 38 40
    XDP_PWRBTN# 41 39 40 42 CLK_ITPXDP_P <12>
    43 41 42 44 CLK_ITPXDP_N <12>
    Place near JXDP1.47 <XDP CLK>
    45 43 44 46 XDP_RST# From CPU
    RESET_OUT#_R 47 45 46 48 XDP_DBRESET#
    49 47 48 50
    51 49 50 52 XDP_TDO
    <9> DDR_XDP_SMBDAT
    <XDP SMBUS> 53 51 52 54 XDP_TRST#
    <9> DDR_XDP_SMBCLK
    Link to PCH SMB XDP_TCK1 55 53 54 56 XDP_TDI
    XDP_TCK0 57 55 56 58 XDP_TMS
    59 57 58 60 XDP_PRSENT#
    61 59 60
    XDP_DBRESET# XDP_PWRBTN# 61
    A 62 63 A
    GND GND
    0.1U_0201_10V6K
    CC87

    0.1U_0201_10V6K
    CC88

    Place near JXDP1.48 Place near JXDP1.41


    1 1 E-T_6601K-Y61N-04L
    CONN@
    XDP@

    XDP@

    2 2 DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P15-MCP(9/14)XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 15 of 61
    5 4 3 2 1
    5 4 3 2 1

    PSC(Primary side cap) : Place as close to the package as possible +VCC_CORE +VCC_CORE
    BSC(Backside cap) : Place on secondary side, underneath the package
    @ UCPU1L SKL-U
    CPU POWER 1 OF 4
    Component placement order: A30 G32
    Package edge > 0402 caps > 0805 caps > Bulk caps >Power source A34 VCC_A30 VCC_G32 G33
    A39 VCC_A34 VCC_G33 G35

    +VCC_CORE: 0.55~1.5V, 29A


    Vinafix.com A44
    AK33
    AK35
    VCC_A39
    VCC_A44
    VCC_AK33
    VCC_G35
    VCC_G37
    VCC_G38
    G37
    G38
    G40
    +1.8VA +V1.8S_EDRAM AK37 VCC_AK35 VCC_G40 G42
    PVT_0008
    D +VCC_EDRAM: 1V, 2.5A AK38 VCC_AK37
    VCC_AK38
    VCC_G42
    VCC_J30
    J30 D
    AK40 J33
    +V1.8S_EDRAM: 1.8V, 50mA R2 1 @ 2 0_0603_5% AL33 VCC_AK40
    VCC_AL33
    1.5V@29A VCC_J33
    VCC_J37
    J37
    +VCC_EOPIO: 0.8~1V, 2A AL37
    AL40 VCC_AL37 VCC_J40
    J40
    K33 +VCC_CORE
    AM32 VCC_AL40 VCC_K33 K35
    AM33 VCC_AM32 VCC_K35 K37
    VCC_AM33 VCC_K37

    100_0402_1%
    AM35 K38
    AM37 VCC_AM35 VCC_K38 K40
    VCC_AM37 VCC_K40
    Close CPU

    RC150
    AM38 K42
    G30 VCC_AM38 VCC_K42 K43
    VCC_G30 VCC_K43

    2
    +VCC_CORE_G0 K32 E32
    T29 @ PAD~D RSVD_K32 VCC_SENSE VCC_SENSE <56>
    E33
    +VCC_CORE_G1 AK32 VSS_SENSE VSS_SENSE <56>
    T30 @ PAD~D RSVD_AK32

    1
    B63 H_CPU_SVIDALRT#

    100_0402_1%
    AB62 VIDALERT# A63 VIDSCLK_R
    +VCC_EDRAM VCCOPC_AB62 VIDSCK D64 VIDSOUT_R

    RC151
    P62 1V@2.5A
    V62 VCCOPC_P62 VIDSOUT
    VCCOPC_V62 G20 +1.0V_VCCSTG

    2
    H63 VCCSTG_G20
    +V1.8S_EDRAM VCC_OPC_1P8_H63 1V@0.05A
    RC152 1 @ 2 0_0603_5% G61
    VCC_OPC_1P8_G61
    AC63
    <61> VCC_EDRAM_SENSE AE63 VCCOPC_SENSE
    <61> VSS_EDRAM_SENSE VSSOPC_SENSE +1.0V_VCCSTG_R 1 2 0_0603_5%
    RC153 @
    AE62
    +VCC_EOPIO VCCEOPIO
    AG62 1V@2A
    VCCEOPIO
    AL63 PVT_0008
    <61> VCC_EOPIO_SENSE AJ62 VCCEOPIO_SENSE
    C <61> VSS_EOPIO_SENSE VSSEOPIO_SENSE C

    SKL-U_BGA1356 12 OF 20

    VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e


    (w/ on package cache)

    +VCC_EDRAM Decoupling Requirment +VCC_EOPIO Decoupling Requirment


    Back Side (underneath the package): Back Side (underneath the package): +1.0V_VCCST
    10U_0402*1 pcs + 1U_0201*6 pcs 10U_0402*2 pcs
    SVID ALERT
    +VCC_EDRAM +VCC_EOPIO

    1
    56_0402_1%
    RC154
    BSC BSC CAD Note: Place the PU resistors close to CPU
    RC154 close to CPU 1000 - 1500mils
    10U_0402_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    2
    1 1 1 1 1 1 1 1 1 H_CPU_SVIDALRT#
    CC19

    CC20

    CC21

    CC22

    CC23

    CC24

    CC25

    CC26

    CC27

    2 1
    <56> VR_SVID_ALERT#
    220_0402_5% RC155
    2 2 2 2 2 2 2 2 2
    B B
    +1.0V_VCCST
    SVID DATA

    100_0402_1%
    1
    CAD Note: Place the PU resistors close to CPU

    RC156
    RC156close to CPU 1000 - 1500mils

    2
    0_0402_1% 2 @ 1 RC157 VIDSOUT_R
    <56> VR_SVID_DATA

    +1.0V_VCCST
    SVID CLK

    100_0402_1%
    1

    @ RC158
    CAD Note: Place the PU resistors close to CPU
    RC158close to CPU 1000 - 1500mils

    2
    0_0402_1% 2 @ 1 RC159 VIDSCLK_R
    <56> VR_SVID_CLK

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P16-MCP(10/14)PWR-VCC CORE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 16 of 61
    5 4 3 2 1
    5 4 3 2 1

    +VCCGT: 0.55~1.5V, 54A


    +VCCGTX : 0.55~1.5V, 7A
    Vinafix.com +VCCGT +VCCGT
    Note: 4+2 Co-layout Only can use SD00001VZ00
    D @ UCPU1M SKL-U D

    +VCCIA_GT CPU POWER 2 OF 4


    N70 +VCC_CORE +VCCIA_GT +VCCGT
    A48 VCCGT N71 U42@ R275 U22U23@ R276
    A53 VCCGT VCCGT R63 1/2W 0.0002 +-5% 1/2W 0.0002 +-5%
    A58 VCCGT VCCGT R64 1 2 1 2
    A62 VCCGT VCCGT R65
    A66 VCCGT VCCGT R66
    AA63 VCCGT VCCGT R67
    AA64 VCCGT VCCGT R68
    AA66 VCCGT VCCGT R69
    AA67 VCCGT 1.5V@54A VCCGT R70
    AA69 VCCGT VCCGT R71
    AA70 VCCGT VCCGT T62 U42@ R277 U22U23@ R278
    AA71 VCCGT VCCGT U65 1/2W 0.0002 +-5% 1/2W 0.0002 +-5%
    AC64 VCCGT VCCGT U68 1 2 1 2
    AC65 VCCGT VCCGT U71
    AC66 VCCGT VCCGT W63
    AC67 VCCGT VCCGT W64
    AC68 VCCGT VCCGT W65
    AC69 VCCGT VCCGT W66
    AC70 VCCGT VCCGT W67
    AC71 VCCGT VCCGT W68
    J43 VCCGT VCCGT W69
    J45 VCCGT VCCGT W70
    J46 VCCGT VCCGT W71
    J48 VCCGT 1.5V@7A VCCGT Y62 +VCCIA_GT
    J50 VCCGT VCCGT
    J52 VCCGT
    J53 VCCGT AK42 +VCCGT +VCCIA_GT
    J55 VCCGT VCCGTX_AK42 AK43 @
    C J56 VCCGT VCCGTX_AK43 AK45 AK52 R279 1 2 0_0402_5% C
    J58 VCCGT VCCGTX_AK45 AK46
    J60 VCCGT VCCGTX_AK46 AK48 +VCCGT
    K48 VCCGT VCCGTX_AK48 AK50 @
    K50 VCCGT VCCGTX_AK50 AK52 AK52 K52 R280 1 2 0_0402_5%
    K52 K52 VCCGT VCCGTX_AK52 AK53
    K53 VCCGT VCCGTX_AK53 AK55
    K55 VCCGT VCCGTX_AK55 AK56
    K56 VCCGT VCCGTX_AK56 AK58
    K58 VCCGT VCCGTX_AK58 AK60
    K60 VCCGT VCCGTX_AK60 AK70 KBL-R U42 Only Design Do not Connect AK52 and K52 Balls,
    L62 VCCGT VCCGTX_AK70 AL43 Keep as NC
    L63 VCCGT VCCGTX_AL43 AL46
    L64 VCCGT VCCGTX_AL46 AL50
    L65 VCCGT VCCGTX_AL50 AL53 KBL-R U42 Compatible Design for Do not Connect AK52 and K52 Balls,
    L66 VCCGT VCCGTX_AL53 AL56 (KBL-R U42/KBL U22/KBL U23e) support Keep as NC
    L67 VCCGT VCCGTX_AL56 AL60
    L68 VCCGT VCCGTX_AL60 AM48
    +VCCGT L69 VCCGT VCCGTX_AM48 AM50
    L70 VCCGT VCCGTX_AM50 AM52 AK52 and K52 Kaby Lake Silicon Ball Connectivity Recap from PDG (568813_KBL_R_U42_PDG_Addendum_Rev0p9, Page 12)
    L71 VCCGT VCCGTX_AM52 AM53
    M62 VCCGT VCCGTX_AM53 AM56
    VCCGT VCCGTX_AM56
    1

    100_0402_1%
    N63 AM58
    N64 VCCGT VCCGTX_AM58 AU58
    VCCGT VCCGTX_AU58
    RC160

    Close CPU N66 AU63


    N67 VCCGT VCCGTX_AU63 BB57
    N69 VCCGT VCCGTX_BB57 BB66
    VCCGTX for SKYLAKE-U 2+3e
    Merged the GT and GTx rail
    2

    VCCGT VCCGTX_BB66
    J70 AK62 T31 PAD~D @
    <56> VCCGT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61 T32 PAD~D @
    <56> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
    1

    100_0402_1%

    B SKL-U_BGA1356 13 OF 20 B
    RC161
    2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P17-MCP(11/14)PWR-VCCGT
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 17 of 61
    5 4 3 2 1
    5 4 3 2 1

    +1.2V_DDR: 1.2V, 3.5A


    +1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
    +1.0V_VCCSTG: 1V, 40mA
    +1.2V_DDR +1.0VS_VCCIO
    +VCCPLL_OC: 1.2V, 260mA
    +1.0VS_VCCIO: 0.85~0.95V, 3.1A Vinafix.com @ UCPU1N
    CPU POWER 3 OF 4
    SKL-U

    D
    +VCC_SA: 1.15V, 5.1A AU23
    AU28 VDDQ_AU23 0.95V@3.1AVCCIO
    AK28
    AK30 D
    AU35 VDDQ_AU28 VCCIO AL30
    AU42 VDDQ_AU35 VCCIO AL42
    BB23 VDDQ_AU42 VCCIO AM28
    +1.2V_DDR +1.2V_MEM_CPUCLK BB32 VDDQ_BB23 VCCIO AM30
    1.2V@3.5A
    BB41 VDDQ_BB32 VCCIO AM42 +VCCSA
    +1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
    1 @ 2 BB51 VDDQ_BB47 AK23
    RC162 0_0402_1% VDDQ_BB51 VCCSA AK25
    VCCSA G23
    AM40 VCCSA G25
    PVT_0008 VDDQC VCCSA G27
    A18 VCCSA G28 +1.0VS_VCCIO
    1V@0.12A
    VCCST
    1.15V@5.1A VCCSA J22
    1V@0.04A A22 VCCSA J23
    VCCSTG_A22 VCCSA J27
    VCCSA

    100_0402_1%
    1.2V@0.26A AL23 VCCPLL_OC VCCSA
    K23

    RC163
    K25
    +1.0V_VCCST 1V@0.12A K20 VCCSA K27
    VCCPLL_K20 VCCSA
    Close CPU
    K21 K28
    VCCPLL_K21 VCCSA K30
    PSC

    2
    VCCSA
    close to package AM23 VCCIO_SENSE
    VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <60>
    +1.0V_VCCSTG VSSIO_SENSE

    1U_0402_6.3V6K

    0.1U_0402_10V7K
    1 1

    CC97
    H21
    VSSSA_SENSE

    CC28
    H20
    BSC VCCSA_SENSE

    1
    100_0402_1%
    2 2

    @
    underneath the package RC165

    RC164
    SKL-U_BGA1356 14 OF 20 0_0201_5%

    1U_0402_6.3V6K
    1 1 2
    +VCCPLL_OC +1.0V_VCCST +VCCSA

    @ CC29
    RC166 100_0402_1%

    2
    C C

    PVT_0009 2 PSC PSC


    close to package close to package

    1U_0201_6.3V6M

    0.1U_0402_10V7K

    1U_0402_6.3V6K
    1 1 1 VSSSA_SENSE <56>

    CC30

    CC96

    CC31
    VCCSA_SENSE <56>

    2 2 2

    @
    PVT_0009

    +1.0VS_VCCIO Decoupling Requirment +1.2V_MEM_CPUCLK (VDDQC) Place on CPU


    +1.2_DDR Decoupling Requirment Back Side (underneath the package): Back Side (underneath the package):
    Back Side (underneath the package): 10U_0402*2 pcs + 1U_0201*4 pcs (@) 1U_0201*1 pcs (@)
    10U_0402*2 pcs + 1U_0201*4 pcs (@) Primary Side (close to package): Primary Side (close to package):
    Primary Side (close to package): 1U_0402*4 pcs 10U_0402 * 1 pcs
    10U_0402*4 pcs + 22U_0603*3 pcs

    +1.0VS_VCCIO +1.2V_DDR
    B +1.2V_DDR B

    PSC BSC
    PSC
    PSC

    10U_0402_6.3V6M

    1U_0201_6.3V6M
    1 1
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    CC43

    @ CC44
    1 1 1 1
    1 1 1 1 1 1 1
    CC32

    CC33

    CC34

    CC35

    CC36

    CC37

    CC38

    CC39

    CC40

    CC41

    CC42
    2 2
    2 2 2 2
    2 2 2 2 2 2 2

    BSC BSC
    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1 1 1 1 1 1 1 1 1 1 1 1
    @ CC45

    @ CC46

    @ CC47

    @ CC48

    @ CC49

    @ CC50

    @ CC51

    @ CC52

    @ CC53

    @ CC54

    @ CC55

    @ CC56
    2 2 2 2 2 2 2 2 2 2 2 2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P18-MCP(12/14)PWR-VCCIO,MEM
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 18 of 61
    5 4 3 2 1
    5 4 3 2 1

    PCH PWR +3V_PCH +3.3V_PGPP


    RC167
    0_0603_5%

    Vinafix.com 1 @ 2 close UC1.AG15 and <120mil


    close UC1.Y16 and <400mil
    1
    close UC1.T16 and <400mil
    1 1

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    PVT_0008

    @ CC57

    @ CC58

    @ CC59
    D D
    +3VALW +1.8VA +1.0VA +1.0V_PRIM_CORE 2 2 2
    47U_0603_6.3V

    47U_0603_6.3V

    47U_0603_6.3V

    47U_0603_6.3V
    1 1 1 1
    +1.0V_MPHYAON +1.0V_PRIM_CORE +1.0VA +1.8VA +3.3V_1.8V_PGPPA +3.3V_1.8V_ESPI
    CC60

    CC61

    CC62

    CC63
    RC384 RC386
    1 @ 2 1 @ 2
    2 2 2 2
    close UC1.AB19 and <400mil
    0_0402_1% 0_0402_1%

    1 1 1 1

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    @ CC66

    @ CC67
    CC64

    CC65
    @ UCPU1O SKL-U
    2 2 2 2 +3.3V_1.8V_PGPPA +3.3V_PGPP +3V_PCH +1.8VA
    CPU POWER 4 OF 4

    1.0V@0.696A AB19
    AB20 VCCPRIM_1P0 AK15
    P18 VCCPRIM_1P0 VCCPGPPA AG15 1.0V@0.085A

    4.7P_0402_50V8C
    VCCPRIM_1P0 VCCPGPPB Y16 1

    1U_0402_6.3V6K
    1
    +1.0VA AF18 VCCPGPPC Y15
    close UC1.AF18 and <400mil 1.0V@2.57A

    CC68
    AF19 VCCPRIM_CORE VCCPGPPD T16
    PVT_0008

    CC69
    V20 VCCPRIM_CORE VCCPGPPE AF16 1.0V@0.161A +1.8V_PGPP

    2
    +1.0V_MPHYAON V21 VCCPRIM_CORE VCCPGPPF AD15 2
    VCCPRIM_CORE VCCPGPPG +3.3V_PGPP
    RC168
    0_0603_5% close UC1.AL1 and <120mil AL1 V19 close UC1.V19 and <120mil
    1 @ 2 DCPDSW_1P0 VCCPRIM_3P3_V19
    +1.0V_MPHYGT close UC1.K17 and <120mil 1.0V@0.022A K17 T1
    VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS +3V_PCH
    RC169 +1.0V_DTS L1
    0_0603_5% VCCMPHYAON_1P0 AA1
    VCCATS_1P8
    1.8V@0.006A close UC1.AA1 and <400mil
    1 @ 2 close UC1.N15 and CC210 <400mil, CC211 <120mil 1.0V@2.1A N15
    N16 VCCMPHYGT_1P0_N15 AK17 3.3V@0.001A close UC1.AK17 and <120mil
    VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3

    47U_0603_6.3V
    1 1 N17

    1U_0402_6.3V6K
    VCCMPHYGT_1P0_N17

    CC70
    P15 AK19 3.0V@0.001A close UC1.AK19 and <120mil +RTCVCC
    P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14

    CC71
    1 1

    1U_0402_6.3V6K
    0.1U_0402_10V7K
    VCCMPHYGT_1P0_P16 VCCRTC_BB14

    CC74
    1 1

    1U_0402_6.3V6K
    0.1U_0402_10V7K
    2 @ 2 1.0V@0.088A K15 BB10 close UC1.BB10 and <120mil

    CC75
    C +1.0V_AMPHYPLL C
    L15 VCCAMPHYPLL_1P0 DCPRTC

    CC72

    CC73
    VCCAMPHYPLL_1P0 A14 2 2
    1.0V@0.135A +1.0V_CLK 1

    0.1U_0402_10V7K
    +3V_PCH +3.3V_SPI VCCCLK1 2 2
    RC170 1.0V@0.026A V15

    CC76
    +1.0V_APLL VCCAPLL_1P0
    0_0603_5% K19
    1 @ 2 AB17 VCCCLK2
    +1.0VA VCCPRIM_1P0_AB17 2
    Y18 L21
    VCCPRIM_1P0_Y18 VCCCLK3
    PVT_0008 3.3V@0.118A AD17 N20
    +3V_PCH_DSW VCCDSW_3P3_AD17 VCCCLK4
    AD18
    +3V_PCH RA65 AJ17 VCCDSW_3P3_AD18 L19
    BLM18EG221TN1D_2P~D VCCDSW_3P3_AJ17 VCCCLK5
    1 2 close UC1.AJ19 and <400mil VCCHDA 3.3V@0.068A AJ19 A10
    VCCHDA VCCCLK6
    +1.0V_SRAM 3.3V@0.011A AJ16 AN11
    2 +3.3V_SPI VCCSPI GPP_B0/CORE_VID0 CORE_VID0 <60>
    1

    +1.0V_MPHYGT RF@ AN13


    GPP_B1/CORE_VID1 CORE_VID1 <60>
    R3 RF@ CC95 close UC1.AF20 and <400mil 1.0V@0.642A AF20 VCCSRAM_1P0
    0_0201_5% 2.2P_0201_25V 1 AF21
    RC171 +1.0V_SRAM 1 1U_0402_6.3V6K T19 VCCSRAM_1P0
    @ CC78

    0_0603_5% T20 VCCSRAM_1P0


    2

    1 @ 2 VCCSRAM_1P0
    2 3.3V@0.075A AJ21
    1 2.2P_0201_25V +3V_PCH VCCPRIM_3P3_AJ21
    +1.0V_APLLEBB
    RC172 +1.0V_APLLEBB CC77 AK20
    RF@ +1.0VA VCCPRIM_1P0_AK20
    0_0603_5%
    1 @ 2 2 1.0V@0.033A N18
    close UC1.N18 and <120mil VCCAPLLEBB
    1
    1U_0402_6.3V6K

    SKL-U_BGA1356 15 OF 20
    PVT_0008
    CC79

    2
    +3V_PCH

    1
    0.1U_0402_10V7K

    Place near AJ19


    RF@ CC94

    B B
    2

    +1.0V_MPHYGT +1.0V_AMPHYPLL +3VALW RC174 +3V_PCH_DSW


    RC173 0_0603_5% +1.0VA RC175 +1.0V_CLK
    0_0603_5% +1.0VA RF@ RC177 +1.0V_APLL 1 @ 2 0_0603_5%
    1 @ 2 +1.8VA RC176 +1.8V_PGPP BLM18EG221TN1D_2P~D 1 @ 2
    close UC1.K15 and <120mil 0_0603_5% 1 2

    22U_0603_6.3V6M
    @ CC81

    22U_0603_6.3V6M
    @ CC82
    1 1 @ 2 PVT_0008 1 1 1 close UC1.A10 and <120mil
    1U_0402_6.3V6K

    1U_0402_6.3V6K
    PVT_0008 close UC1.V15 and <100mil PVT_0008
    @ CC80

    @ CC83
    1

    2
    PVT_0008 2 2 2
    R4 RF@
    1 2.2P_0201_25V 0_0201_5%
    CE96
    2

    RF@
    2
    1 2.2P_0201_25V
    CE84 RF@

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P19-MCP(13/14)PCH PWR
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 19 of 61
    5 4 3 2 1
    5 4 3 2 1

    Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

    @ UCPU1P SKL-U @ UCPU1Q SKL-U


    @ UCPU1R SKL-U
    GND 1 OF 3 GND 2 OF 3
    GND 3 OF 3
    A5 AL65 AT63 BA49 F8 L18
    A67
    A70
    AA2
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    AL66
    AM13
    AM21
    AT68
    AT71
    AU10
    Vinafix.com
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    BA53
    BA57
    BA6
    G10
    G22
    G43
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    L2
    L20
    L4
    AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
    D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
    AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
    AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
    AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
    AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
    AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
    AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
    AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
    AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
    AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
    AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
    AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
    AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
    AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
    AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
    AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
    AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
    AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
    AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
    AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
    AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
    AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
    AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
    AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
    AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
    AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
    AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
    AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
    AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
    AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
    AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
    AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
    C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
    AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
    AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
    AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
    AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
    AH64 VSS VSS AR15 AY66 VSS VSS E11
    AH67 VSS VSS AR16 B10 VSS VSS E15
    AJ15 VSS VSS AR20 B14 VSS VSS E18
    AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
    AJ20 VSS VSS AR28 B22 VSS VSS E46
    AJ4 VSS VSS AR35 B30 VSS VSS E50
    AK11 VSS VSS AR42 B34 VSS VSS E53
    AK16 VSS VSS AR43 B39 VSS VSS E56
    AK18 VSS VSS AR45 B44 VSS VSS E6
    AK21 VSS VSS AR46 B48 VSS VSS E65
    AK22 VSS VSS AR48 B53 VSS VSS E71
    AK27 VSS VSS AR5 B58 VSS VSS F1
    AK63 VSS VSS AR50 B62 VSS VSS F13
    AK68 VSS VSS AR52 B66 VSS VSS F2
    AK69 VSS VSS AR53 B71 VSS VSS F22
    AK8 VSS VSS AR55 BA1 VSS VSS F23
    AL2 VSS VSS AR58 BA10 VSS VSS F27
    AL28 VSS VSS AR63 BA14 VSS VSS F28
    AL32 VSS VSS AR8 BA18 VSS VSS F32
    AL35 VSS VSS AT2 BA2 VSS VSS F33
    AL38 VSS VSS AT20 BA23 VSS VSS F35
    AL4 VSS VSS AT23 BA28 VSS VSS F37
    AL45 VSS VSS AT28 BA32 VSS VSS F38
    AL48 VSS VSS AT35 BA36 VSS VSS F4
    AL52 VSS VSS AT4 F68 VSS VSS F40
    AL55 VSS VSS AT42 BA45 VSS VSS F42
    AL58 VSS VSS AT56 VSS VSS BA41
    B AL64 VSS VSS AT58 VSS B
    VSS VSS

    SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P20-MCP(14/14)VSS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 20 of 61
    5 4 3 2 1
    5 4 3 2 1

    +1.8VU +1.8VU +1.8VU +1.8VU

    +1.8VU UD42 @ +1.8VU UD41 @


    DDR_A_D21 DDR_A_D61

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    A3 P9 A3 P9
    A4 VDD1 DQ0 N9 DDR_A_D16 A4 VDD1 DQ0 N9 DDR_A_D56
    <8> DDR_A_DQS#[0..7] 1 1 1 1

    1
    VDD1 DQ1 DDR_A_D19 VDD1 DQ1 DDR_A_D59

    CD9

    CD10

    CD1

    CD2

    CD12

    CD3
    A5 N10 A5 N10
    A6 VDD1 DQ2 N11 DDR_A_D18 A6 VDD1 DQ2 N11 DDR_A_D58
    <8> DDR_A_DQS[0..7] VDD1 DQ3 DDR_A_D17 VDD1 DQ3 DDR_A_D60
    A10 M8 A10 M8

    2
    2 2 U3 VDD1 DQ4 M9 DDR_A_D20 2 2 U3 VDD1 DQ4 M9 DDR_A_D57
    <8> DDR_A_D[0..63] VDD1 DQ5 DDR_A_D23 VDD1 DQ5 DDR_A_D62
    U4 M10 U4 M10

    Vinafix.com U5 VDD1 DQ6 M11 DDR_A_D22 U5 VDD1 DQ6 M11 DDR_A_D63


    <8,23> DDR_A_CA1_[0..9] VDD1 DQ7 DDR_A_D24 VDD1 DQ7 DDR_A_D55
    U6 F11 U6 F11
    U10 VDD1 DQ8 F10 DDR_A_D25 U10 VDD1 DQ8 F10 DDR_A_D49
    <8,23> DDR_A_CA2_[0..9] +1.2V_DDR VDD1 DQ9 DDR_A_D31 +1.2V_DDR VDD1 DQ9 DDR_A_D54
    F9 F9
    DQ10 F8 DDR_A_D27 DQ10 F8 DDR_A_D50
    D
    A8 DQ11 E11 DDR_A_D29 A8 DQ11 E11 DDR_A_D53 D
    A9 VDD2 DQ12 E10 DDR_A_D28 A9 VDD2 DQ12 E10 DDR_A_D48
    D4 VDD2 DQ13 E9 DDR_A_D30 +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 DDR_A_D52
    +1.2V_DDR +1.2V_DDR D5 VDD2 DQ14 D9 DDR_A_D26 D5 VDD2 DQ14 D9 DDR_A_D51
    D6 VDD2 DQ15 T8 DDR_A_D15 D6 VDD2 DQ15 T8 DDR_A_D45
    G5 VDD2 DQ16 T9 DDR_A_D14 G5 VDD2 DQ16 T9 DDR_A_D40
    VDD2 DQ17 DDR_A_D11 VDD2 DQ17 DDR_A_D43

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H5 T10 H5 T10
    VDD2 DQ18 DDR_A_D12 VDD2 DQ18 DDR_A_D42
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H6 T11 1 1 1 H6 T11

    1
    VDD2 DQ19 DDR_A_D13 VDD2 DQ19 DDR_A_D44

    CD6

    CD7

    CD8

    CD14
    1 1 1 H12 R8 H12 R8
    VDD2 DQ20 VDD2 DQ20
    1

    DDR_A_D10 DDR_A_D41
    CD4

    CD5

    CD11

    CD13
    J5 R9 J5 R9
    J6 VDD2 DQ21 R10 DDR_A_D8 J6 VDD2 DQ21 R10 DDR_A_D46

    2
    K5 VDD2 DQ22 R11 DDR_A_D9 2 2 2 K5 VDD2 DQ22 R11 DDR_A_D47
    2

    2 2 2 K6 VDD2 DQ23 C11 DDR_A_D6 K6 VDD2 DQ23 C11 DDR_A_D33


    K12 VDD2 DQ24 C10 DDR_A_D7 K12 VDD2 DQ24 C10 DDR_A_D38
    L5 VDD2 DQ25 C9 DDR_A_D2 L5 VDD2 DQ25 C9 DDR_A_D39
    P4 VDD2 DQ26 C8 DDR_A_D0 P4 VDD2 DQ26 C8 DDR_A_D35
    P5 VDD2 DQ27 B11 DDR_A_D1 P5 VDD2 DQ27 B11 DDR_A_D34
    P6 VDD2 DQ28 B10 DDR_A_D3 P6 VDD2 DQ28 B10 DDR_A_D37
    U8 VDD2 DQ29 B9 DDR_A_D4 U8 VDD2 DQ29 B9 DDR_A_D32
    U9 VDD2 DQ30 B8 DDR_A_D5 U9 VDD2 DQ30 B8 DDR_A_D36
    +1.2V_DDR VDD2 DQ31 +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31

    +1.2V_DDR +1.2V_DDR +1.2V_DDR DDR_A_CA1_0


    Closed to UD41 DDR_A_CA2_0
    A11 R2 A11 R2
    C12 VDDQ CA0 P2 DDR_A_CA1_1 C12 VDDQ CA0 P2 DDR_A_CA2_1
    Closed to UD42 VDDQ CA1 DDR_A_CA1_2 VDDQ CA1 DDR_A_CA2_2

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D
    E8 N2 E8 N2
    E12 VDDQ CA2 N3 DDR_A_CA1_3 E12 VDDQ CA2 N3 DDR_A_CA2_3
    1 1 1 1 1 1

    1
    VDDQ CA3 DDR_A_CA1_4 VDDQ CA3 DDR_A_CA2_4
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D

    CD22

    CD23

    CD24

    CD25

    CD26
    G12 M3 G12 M3
    VDDQ CA4 DDR_A_CA1_5 VDDQ CA4 DDR_A_CA2_5

    CD27

    CD28
    1 1 1 1 1 1 H8 F3 H8 F3
    1

    VDDQ CA5 DDR_A_CA1_6 VDDQ CA5 DDR_A_CA2_6


    CD15

    CD16

    CD17

    CD18

    CD19

    CD20

    H9 E3 H9 E3

    2
    VDDQ CA6 DDR_A_CA1_7 2 2 2 2 2 2 VDDQ CA6 DDR_A_CA2_7
    CD21

    H11 E2 H11 E2
    J9 VDDQ CA7 D2 DDR_A_CA1_8 J9 VDDQ CA7 D2 DDR_A_CA2_8
    2

    2 2 2 2 2 2 J10 VDDQ CA8 C2 DDR_A_CA1_9 J10 VDDQ CA8 C2 DDR_A_CA2_9


    K8 VDDQ CA9 K8 VDDQ CA9
    K11 VDDQ K11 VDDQ
    L12 VDDQ L10 DDR_A_DQS2 L12 VDDQ L10 DDR_A_DQS7
    N8 VDDQ DQS0 G10 DDR_A_DQS3 N8 VDDQ DQS0 G10 DDR_A_DQS6
    N12 VDDQ DQS1 P10 DDR_A_DQS1 N12 VDDQ DQS1 P10 DDR_A_DQS5
    R12 VDDQ DQS2 D10 DDR_A_DQS0 R12 VDDQ DQS2 D10 DDR_A_DQS4
    C C
    U11 VDDQ DQS3 U11 VDDQ DQS3
    +1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
    L11 DDR_A_DQS#2 L11 DDR_A_DQS#7
    F2 DQS0# G11 DDR_A_DQS#3 F2 DQS0# G11 DDR_A_DQS#6
    +1.2V_DDR +1.2V_DDR G2 VDDCA DQS1# P11 DDR_A_DQS#1 G2 VDDCA DQS1# P11 DDR_A_DQS#5
    VDDCA DQS2# DDR_A_DQS#0 VDDCA DQS2# DDR_A_DQS#4

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H3 D11 H3 D11
    L2 VDDCA DQS3# L2 VDDCA DQS3#
    1 1

    1
    VDDCA VDDCA

    CD29

    CD30

    CD31
    M2 M2
    VDDCA VDDCA
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    L8 L8
    DM0 G8 DM0 G8
    1 1

    2
    1

    DM1 2 2 DM1
    CD32

    CD33

    CD34

    A1 P8 A1 P8
    A2 NC DM2 D8 A2 NC DM2 D8
    A12 NC DM3 A12 NC DM3
    2

    2 2 A13 NC A13 NC
    B1 NC B3 DDR_A0_ZQ0 RD1 1 2 240_0402_1% B1 NC B3 DDR_A1_ZQ0 RD2 1 2 240_0402_1%
    B13 NC ZQ0 B4 DDR_A0_ZQ1 RD3 1 2 240_0402_1% B13 NC ZQ0 B4 DDR_A1_ZQ1 RD4 1 2 240_0402_1%
    C4 NC ZQ1 C4 NC ZQ1
    K9 NC K9 NC
    R3 NC K3 R3 NC K3
    NC CKE0 DDR_A_CKE0 <8,23> NC CKE0 DDR_A_CKE2 <8,23>
    T1 K4 DDR_A_CKE1 <8,23> T1 K4 DDR_A_CKE3 <8,23>
    T13 NC CKE1 T13 NC CKE1
    U1 NC U1 NC
    U2 NC L3 DDR_A_CS#0 U2 NC L3 DDR_A_CS#0
    NC CS0# DDR_A_CS#1 DDR_A_CS#0 <8,23> NC CS0# DDR_A_CS#1
    U12 L4 U12 L4
    NC CS1# DDR_A_CS#1 <8,23> NC CS1#
    U13 U13
    NC NC
    J3 DDR_A_CLK0 <8,23> J3 DDR_A_CLK1 <8,23>
    P3 CK J2 P3 CK J2
    VSSCA CK# DDR_A_CLK#0 <8,23> All VREF traces should VSSCA CK# DDR_A_CLK#1 <8,23>
    M4 have 10 mil trace width M4
    J4 VSSCA J4 VSSCA
    G4 VSSCA J8 DDR_A_ODT0 G4 VSSCA J8 DDR_A_ODT0
    VSSCA ODT DDR_A_ODT0 <8,23> VSSCA ODT
    G3 G3
    F4 VSSCA F4 VSSCA
    D3 VSSCA J11 D3 VSSCA J11
    VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
    C3 H4 +VREFCA C3 H4 +VREFCA
    VSSCA Vref_CA VSSCA Vref_CA

    B B
    T12 B2 T12 B2
    T6 VSSQ VSS B5 T6 VSSQ VSS B5
    VSSQ VSS Closed to DRAM VSSQ VSS Closed to DRAM
    R6 C5 R6 C5
    P12 VSSQ VSS E4 +VREFDQ_A +VREFCA P12 VSSQ VSS E4 +VREFDQ_A +VREFCA
    N6 VSSQ VSS E5 N6 VSSQ VSS E5
    M12 VSSQ VSS F5 M12 VSSQ VSS F5
    VSSQ VSS VSSQ VSS
    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D
    M6 H2 M6 H2
    L9 VSSQ VSS J12 L9 VSSQ VSS J12
    K10 VSSQ VSS K2 K10 VSSQ VSS K2
    VSSQ VSS 1 1 VSSQ VSS 1 1
    CD35

    CD36

    CD37

    CD38
    H10 L6 H10 L6
    G9 VSSQ VSS M5 G9 VSSQ VSS M5
    G6 VSSQ VSS N4 G6 VSSQ VSS N4
    F12 VSSQ VSS N5 2 2 F12 VSSQ VSS N5 2 2
    F6 VSSQ VSS R4 F6 VSSQ VSS R4
    E6 VSSQ VSS R5 E6 VSSQ VSS R5
    D12 VSSQ VSS T2 D12 VSSQ VSS T2
    C6 VSSQ VSS T3 C6 VSSQ VSS T3
    B12 VSSQ VSS T4 B12 VSSQ VSS T4
    B6 VSSQ VSS T5 B6 VSSQ VSS T5
    VSSQ VSS VSSQ VSS

    H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D

    Decoupling per DRAM device


    VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF +1.2V_DDR +1.8VU
    VDDCA 2x 0402 1uF 1x 0603 10uF
    VDD2 3x 0402 1uF 1x 0603 10uF
    VDD1 2x 0402 1uF 1x 0603 10uF
    10U_0603_6.3V6M~D

    10U_0603_6.3V6M~D

    intel uesd 0201 for 0.1uF


    1

    1
    CD39

    CD40
    2

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P21-DDRIII Channel A
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 21 of 61
    5 4 3 2 1
    5 4 3 2 1

    <8> DDR_B_DQS#[0..7] +1.8VU +1.8VU +1.8VU +1.8VU


    <8> DDR_B_DQS[0..7] +1.8VU +1.8VU
    UD44 @ UD43 @
    <8> DDR_B_D[0..63] DDR_B_D27 DDR_B_D61

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    A3 P9 A3 P9
    A4 VDD1 DQ0 N9 DDR_B_D26 A4 VDD1 DQ0 N9 DDR_B_D57
    <8,23> DDR_B_CA1_[0..9] 1 1 1 1

    1
    VDD1 DQ1 DDR_B_D29 VDD1 DQ1 DDR_B_D63

    CD44

    CD45

    CD41

    CD47

    CD48

    CD42
    A5 N10 A5 N10
    A6 VDD1 DQ2 N11 DDR_B_D24 A6 VDD1 DQ2 N11 DDR_B_D59
    <8,23> DDR_B_CA2_[0..9] VDD1 DQ3 DDR_B_D30 VDD1 DQ3 DDR_B_D60
    A10 M8 A10 M8

    2
    2 2 U3 VDD1 DQ4 M9 DDR_B_D31 2 2 U3 VDD1 DQ4 M9 DDR_B_D56
    U4 VDD1 DQ5 M10 DDR_B_D25 U4 VDD1 DQ5 M10 DDR_B_D62

    Vinafix.com
    U5 VDD1 DQ6 M11 DDR_B_D28 U5 VDD1 DQ6 M11 DDR_B_D58
    U6 VDD1 DQ7 F11 DDR_B_D2 U6 VDD1 DQ7 F11 DDR_B_D39
    U10 VDD1 DQ8 F10 DDR_B_D1 U10 VDD1 DQ8 F10 DDR_B_D38
    +1.2V_DDR VDD1 DQ9 F9 DDR_B_D4 +1.2V_DDR VDD1 DQ9 F9 DDR_B_D34
    DQ10 F8 DDR_B_D6 DQ10 F8 DDR_B_D33
    D
    A8 DQ11 E11 DDR_B_D0 A8 DQ11 E11 DDR_B_D32 D
    A9 VDD2 DQ12 E10 DDR_B_D5 A9 VDD2 DQ12 E10 DDR_B_D37
    +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 DDR_B_D7 +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 DDR_B_D35
    D5 VDD2 DQ14 D9 DDR_B_D3 D5 VDD2 DQ14 D9 DDR_B_D36
    D6 VDD2 DQ15 T8 DDR_B_D14 D6 VDD2 DQ15 T8 DDR_B_D55
    G5 VDD2 DQ16 T9 DDR_B_D10 G5 VDD2 DQ16 T9 DDR_B_D50
    VDD2 DQ17 DDR_B_D9 VDD2 DQ17 DDR_B_D48
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H5 T10 H5 T10
    H6 VDD2 DQ18 T11 DDR_B_D8 H6 VDD2 DQ18 T11 DDR_B_D49
    1 1 1 1 1 1
    1

    1
    VDD2 DQ19 DDR_B_D15 VDD2 DQ19 DDR_B_D54
    CD43

    CD49

    CD46

    CD50

    CD51

    CD52

    CD53

    CD54
    H12 R8 H12 R8
    J5 VDD2 DQ20 R9 DDR_B_D11 J5 VDD2 DQ20 R9 DDR_B_D51
    J6 VDD2 DQ21 R10 DDR_B_D13 J6 VDD2 DQ21 R10 DDR_B_D53
    2

    2
    2 2 2 K5 VDD2 DQ22 R11 DDR_B_D12 2 2 2 K5 VDD2 DQ22 R11 DDR_B_D52
    K6 VDD2 DQ23 C11 DDR_B_D18 K6 VDD2 DQ23 C11 DDR_B_D46
    K12 VDD2 DQ24 C10 DDR_B_D23 K12 VDD2 DQ24 C10 DDR_B_D44
    L5 VDD2 DQ25 C9 DDR_B_D22 L5 VDD2 DQ25 C9 DDR_B_D45
    P4 VDD2 DQ26 C8 DDR_B_D21 P4 VDD2 DQ26 C8 DDR_B_D41
    P5 VDD2 DQ27 B11 DDR_B_D19 P5 VDD2 DQ27 B11 DDR_B_D47
    P6 VDD2 DQ28 B10 DDR_B_D16 P6 VDD2 DQ28 B10 DDR_B_D43
    U8 VDD2 DQ29 B9 DDR_B_D17 U8 VDD2 DQ29 B9 DDR_B_D42
    U9 VDD2 DQ30 B8 DDR_B_D20 U9 VDD2 DQ30 B8 DDR_B_D40
    +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31 +1.2V_DDR VDD2 DQ31
    +1.2V_DDR +1.2V_DDR +1.2V_DDR
    A11 R2 DDR_B_CA1_0 A11 R2 DDR_B_CA2_0
    Closed to UD44 VDDQ CA0 DDR_B_CA1_1 VDDQ CA0 DDR_B_CA2_1
    C12 P2 Closed to UD43 C12 P2
    VDDQ CA1 DDR_B_CA1_2 VDDQ CA1 DDR_B_CA2_2
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D

    E8 N2 E8 N2
    VDDQ CA2 DDR_B_CA1_3 VDDQ CA2 DDR_B_CA2_3

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    0.1U_0402_16V7K~D

    0.1U_0402_16V7K~D
    1 1 1 1 1 1 E12 N3 E12 N3
    1

    VDDQ CA3 DDR_B_CA1_4 VDDQ CA3 DDR_B_CA2_4


    CD55

    CD56

    CD57

    CD58

    CD59

    G12 M3 1 1 1 1 1 1 G12 M3
    VDDQ CA4 VDDQ CA4

    1
    DDR_B_CA1_5 DDR_B_CA2_5
    CD60

    CD61

    CD62

    CD63

    CD64

    CD65

    CD66
    H8 F3 H8 F3
    VDDQ CA5 DDR_B_CA1_6 VDDQ CA5 DDR_B_CA2_6

    CD67

    CD68
    H9 E3 H9 E3
    2

    2 2 2 2 2 2 H11 VDDQ CA6 E2 DDR_B_CA1_7 H11 VDDQ CA6 E2 DDR_B_CA2_7

    2
    J9 VDDQ CA7 D2 DDR_B_CA1_8 2 2 2 2 2 2 J9 VDDQ CA7 D2 DDR_B_CA2_8
    J10 VDDQ CA8 C2 DDR_B_CA1_9 J10 VDDQ CA8 C2 DDR_B_CA2_9
    K8 VDDQ CA9 K8 VDDQ CA9
    K11 VDDQ K11 VDDQ
    L12 VDDQ L10 DDR_B_DQS3 L12 VDDQ L10 DDR_B_DQS7
    N8 VDDQ DQS0 G10 DDR_B_DQS0 N8 VDDQ DQS0 G10 DDR_B_DQS4
    N12 VDDQ DQS1 P10 DDR_B_DQS1 N12 VDDQ DQS1 P10 DDR_B_DQS6
    R12 VDDQ DQS2 D10 DDR_B_DQS2 R12 VDDQ DQS2 D10 DDR_B_DQS5
    C C
    U11 VDDQ DQS3 U11 VDDQ DQS3
    +1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
    +1.2V_DDR +1.2V_DDR L11 DDR_B_DQS#3 L11 DDR_B_DQS#7
    F2 DQS0# G11 DDR_B_DQS#0 F2 DQS0# G11 DDR_B_DQS#4
    G2 VDDCA DQS1# P11 DDR_B_DQS#1 G2 VDDCA DQS1# P11 DDR_B_DQS#6
    VDDCA DQS2# DDR_B_DQS#2 VDDCA DQS2# DDR_B_DQS#5

    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D
    H3 D11 H3 D11
    VDDCA DQS3# VDDCA DQS3#
    10U_0603_6.3V6M~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    L2 1 1 L2

    1
    VDDCA VDDCA

    CD72

    CD73

    CD74
    1 1 M2 M2
    1

    VDDCA VDDCA
    CD69

    CD70

    CD71

    L8 L8
    DM0 G8 DM0 G8

    2
    A1 DM1 P8 2 2 A1 DM1 P8
    2

    2 2 A2 NC DM2 D8 A2 NC DM2 D8
    A12 NC DM3 A12 NC DM3
    A13 NC A13 NC
    B1 NC B3 DDR_B0_ZQ0 RD5 1 2 240_0402_1% B1 NC B3 DDR_B1_ZQ0 RD6 1 2 240_0402_1%
    B13 NC ZQ0 B4 DDR_B0_ZQ1 RD7 1 2 240_0402_1% B13 NC ZQ0 B4 DDR_B1_ZQ1 RD8 1 2 240_0402_1%
    C4 NC ZQ1 C4 NC ZQ1
    K9 NC K9 NC
    R3 NC K3 R3 NC K3
    NC CKE0 DDR_B_CKE0 <8,23> NC CKE0 DDR_B_CKE2 <8,23>
    T1 K4 DDR_B_CKE1 <8,23> T1 K4 DDR_B_CKE3 <8,23>
    T13 NC CKE1 T13 NC CKE1
    U1 NC U1 NC
    U2 NC L3 DDR_B_CS#0 U2 NC L3 DDR_B_CS#0
    NC CS0# DDR_B_CS#1 DDR_B_CS#0 <8,23> NC CS0# DDR_B_CS#1
    U12 L4 U12 L4
    NC CS1# DDR_B_CS#1 <8,23> NC CS1#
    U13 U13
    NC NC
    J3 DDR_B_CLK0 <8,23> J3 DDR_B_CLK1 <8,23>
    P3 CK J2 P3 CK J2
    VSSCA CK# DDR_B_CLK#0 <8,23> All VREF traces should VSSCA CK# DDR_B_CLK#1 <8,23>
    M4 have 10 mil trace width M4
    J4 VSSCA J4 VSSCA
    G4 VSSCA J8 DDR_B_ODT0 G4 VSSCA J8 DDR_B_ODT0
    VSSCA ODT DDR_B_ODT0 <8,23> VSSCA ODT
    G3 G3
    F4 VSSCA F4 VSSCA
    D3 VSSCA J11 D3 VSSCA J11
    VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B
    C3 H4 +VREFCA C3 H4 +VREFCA
    VSSCA Vref_CA VSSCA Vref_CA

    B B
    T12 B2 T12 B2
    T6 VSSQ VSS B5 T6 VSSQ VSS B5
    VSSQ VSS Closed to DRAM VSSQ VSS Closed to DRAM
    R6 C5 R6 C5
    P12 VSSQ VSS E4 +VREFDQ_B +VREFCA P12 VSSQ VSS E4 +VREFDQ_B +VREFCA
    N6 VSSQ VSS E5 N6 VSSQ VSS E5
    M12 VSSQ VSS F5 M12 VSSQ VSS F5
    VSSQ VSS VSSQ VSS
    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D

    0.047U_0402_10V7K~D
    M6 H2 M6 H2
    L9 VSSQ VSS J12 L9 VSSQ VSS J12
    K10 VSSQ VSS K2 K10 VSSQ VSS K2
    VSSQ VSS 1 1 VSSQ VSS 1 1
    CD75

    CD76

    CD77

    CD78
    H10 L6 H10 L6
    G9 VSSQ VSS M5 G9 VSSQ VSS M5
    G6 VSSQ VSS N4 G6 VSSQ VSS N4
    F12 VSSQ VSS N5 2 2 F12 VSSQ VSS N5 2 2
    F6 VSSQ VSS R4 F6 VSSQ VSS R4
    E6 VSSQ VSS R5 E6 VSSQ VSS R5
    D12 VSSQ VSS T2 D12 VSSQ VSS T2
    C6 VSSQ VSS T3 C6 VSSQ VSS T3
    B12 VSSQ VSS T4 B12 VSSQ VSS T4
    B6 VSSQ VSS T5 B6 VSSQ VSS T5
    VSSQ VSS VSSQ VSS

    H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D

    Decoupling per DRAM device


    VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
    VDDCA 2x 0402 1uF 1x 0603 10uF
    VDD2 3x 0402 1uF 1x 0603 10uF
    VDD1 2x 0402 1uF 1x 0603 10uF
    intel uesd 0201 for 0.1uF

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P22-DDRIII Channel B
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 22 of 61
    5 4 3 2 1
    5 4 3 2 1

    +1.2V_DDR

    M3 M1

    1
    VREF traces should be at least 20 mils wide
    with 20 mils spacing to other signals/planes.
    RD9
    8.2K_0402_1%

    2
    RD10
    <8> +V_DDR_REF_CA
    Vinafix.com 1
    CD79
    1

    4.99_0402_1%~D
    2
    +VREFCA

    0.022U_0402_16V7K~D

    1
    D 2 D

    RD11

    1
    8.2K_0402_1%
    RD12

    2
    24.9_0402_1%

    2
    +1.2V_DDR +1.2V_DDR

    M3 M1 M3 M1

    1
    RD13 RD14
    8.2K_0402_1% 8.2K_0402_1%

    2
    RD15 RD16
    1 2 1 2
    <8> +V_DDR_REFA_R +VREFDQ_A <8> +V_DDR_REFB_R +VREFDQ_B

    1 10_0402_1%~D 1 10_0402_1%~D

    CD80 CD81

    1
    0.022U_0402_16V7K~D 0.022U_0402_16V7K~D
    2 2
    RD17 RD18

    1
    8.2K_0402_1% 8.2K_0402_1%
    1

    RD20

    2
    RD19 24.9_0402_1%
    24.9_0402_1%
    C C

    2
    2

    +0.6VS +0.6VS

    RD21 1 2 68_0201_1% RD22 1 2 68_0201_1%


    <8,21> DDR_A_CA1_0 <8,22> DDR_B_CA1_0
    RD23 1 2 68_0201_1% RD24 1 2 68_0201_1%
    <8,21> DDR_A_CA1_1 1 2 <8,22> DDR_B_CA1_1 1 2
    RD25 68_0201_1% RD26 68_0201_1%
    <8,21> DDR_A_CA1_2 <8,22> DDR_B_CA1_2
    SD000012L80 S RES 1/20W 37.4 +-1% 0201 RD27 1 2 68_0201_1% RD28 1 2 68_0201_1%
    <8,21> DDR_A_CA1_3 1 2 <8,22> DDR_B_CA1_3 1 2
    SD00000TS00 S RES 1/20W 80.6 +-1% 0201 RD29 68_0201_1% RD30 68_0201_1%
    <8,21> DDR_A_CA1_4 <8,22> DDR_B_CA1_4
    SD00000Z900 S RES 1/20W 68 +-1% 0201 RD31 1 2 68_0201_1% RD32 1 2 68_0201_1%
    <8,21> DDR_A_CA1_5 <8,22> DDR_B_CA1_5
    RD33 1 2 68_0201_1% RD34 1 2 68_0201_1%
    <8,21> DDR_A_CA1_6 1 2 <8,22> DDR_B_CA1_6 1 2
    RD35 68_0201_1% RD36 68_0201_1%
    <8,21> DDR_A_CA1_7 <8,22> DDR_B_CA1_7
    RD37 1 2 68_0201_1% RD38 1 2 68_0201_1%
    <8,21> DDR_A_CA1_8 1 2 <8,22> DDR_B_CA1_8 1 2
    RD39 68_0201_1% RD40 68_0201_1%
    <8,21> DDR_A_CA1_9 <8,22> DDR_B_CA1_9

    RD41 1 2 68_0201_1% RD42 1 2 68_0201_1%


    <8,21> DDR_A_CA2_0 <8,22> DDR_B_CA2_0
    RD43 1 2 68_0201_1% RD44 1 2 68_0201_1%
    <8,21> DDR_A_CA2_1 <8,22> DDR_B_CA2_1
    RD45 1 2 68_0201_1% RD46 1 2 68_0201_1%
    <8,21> DDR_A_CA2_2 1 2 <8,22> DDR_B_CA2_2 1 2
    RD47 68_0201_1% RD48 68_0201_1%
    <8,21> DDR_A_CA2_3 <8,22> DDR_B_CA2_3
    RD49 1 2 68_0201_1% RD50 1 2 68_0201_1%
    <8,21> DDR_A_CA2_4 1 2 <8,22> DDR_B_CA2_4 1 2
    RD51 68_0201_1% RD52 68_0201_1%
    <8,21> DDR_A_CA2_5 <8,22> DDR_B_CA2_5
    RD53 1 2 68_0201_1% RD54 1 2 68_0201_1%
    <8,21> DDR_A_CA2_6 <8,22> DDR_B_CA2_6
    RD55 1 2 68_0201_1% RD56 1 2 68_0201_1%
    <8,21> DDR_A_CA2_7 1 2 <8,22> DDR_B_CA2_7 1 2
    RD57 68_0201_1% RD58 68_0201_1%
    <8,21> DDR_A_CA2_8 <8,22> DDR_B_CA2_8
    RD59 1 2 68_0201_1% RD60 1 2 68_0201_1%
    <8,21> DDR_A_CA2_9 <8,22> DDR_B_CA2_9

    B B

    RD61 1 2 80.6_0201_1%~D RD62 1 2 80.6_0201_1%~D


    <8,21> DDR_A_CS#0 <8,22> DDR_B_CS#0
    <8,21> DDR_A_CS#1 RD63 1 2 80.6_0201_1%~D <8,22> DDR_B_CS#1 RD64 1 2 80.6_0201_1%~D

    +0.6VS
    RD65 1 2 80.6_0201_1%~D RD66 1 2 80.6_0201_1%~D
    <8,21> DDR_A_CKE0 <8,22> DDR_B_CKE0
    RD67 1 2 80.6_0201_1%~D RD68 1 2 80.6_0201_1%~D
    <8,21> DDR_A_CKE1 <8,22> DDR_B_CKE1
    <8,21> DDR_A_CKE2 RD69 1 2 80.6_0201_1%~D <8,22> DDR_B_CKE2 RD70 1 2 80.6_0201_1%~D
    RD71 1 2 80.6_0201_1%~D RD72 1 2 80.6_0201_1%~D
    <8,21> DDR_A_CKE3 <8,22> DDR_B_CKE3
    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    22U_0603_6.3V6M~D
    1 1 1 1 1

    CD104
    CD100 CD101 CD102 CD103 RD73 1 2 80.6_0201_1%~D RD74 1 2 80.6_0201_1%~D
    <8,21> DDR_A_ODT0 <8,22> DDR_B_ODT0

    2 2 2 2 2

    +0.6VS +0.6VS

    <8,21> DDR_A_CLK0 RD75 1 2 37.4_0201_1%~D <8,22> DDR_B_CLK0 RD76 1 2 37.4_0201_1%~D

    <8,21> DDR_A_CLK#0 RD77 1 2 37.4_0201_1%~D <8,22> DDR_B_CLK#0 RD78 1 2 37.4_0201_1%~D

    +0.6VS
    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    1U_0402_6.3V6K~D

    22U_0603_6.3V6M~D

    1 1 1 1 1
    CD109

    CD105 CD106 CD107 CD108


    +0.6VS +0.6VS

    2 2 2 2 2

    A <8,21> DDR_A_CLK1 RD79 1 2 37.4_0201_1%~D <8,22> DDR_B_CLK1 RD80 1 2 37.4_0201_1%~D A

    <8,21> DDR_A_CLK#1 RD81 1 2 37.4_0201_1%~D <8,22> DDR_B_CLK#1 RD82 1 2 37.4_0201_1%~D

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P23-DDRIII Vref & Termination
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 23 of 61
    5 4 3 2 1
    5 4 3 2 1

    HD Audio Codec

    LA1 +PVDD2
    BLM15PX600SN1D_2P Placement near Audio Codec
    50mil
    +5VS_AUDIO
    Vinafix.com 2 1
    moat

    0.1U_0402_16V7K~N
    Place next to CODEC +AVDD1 +5VS_AUDIO

    10U_0603_10V6M

    10U_0603_10V6M

    0.1U_0402_16V7K~N
    +AVDD1

    10U_0603_6.3V6M~D
    +3VS_AUDIO
    1 2 +DVDD 1 1 2 1

    0.1U_0402_10V7K

    10U_0603_10V6M
    CA5

    CA8
    LA2

    0.1U_0402_10V7K

    CA3

    CA6
    D BLM15BB220SN1D_2P 2 1 1 2 HCB1005KF-600T25_2P LA3 D

    CA7

    CA9

    CA10
    1 2
    2 @ 2 1@ 2

    CA4

    10U_0603_10V6M

    AZ5125-01H.R7G_SOD523-2
    1

    1
    1 2 2 1

    EMC@ U4
    CA11
    moat 2

    AGND AGND

    2
    +AVDD2
    Near Codec RA1
    1 @ 2 +1.8VS_AUDIO
    In order to prevent the built?in LDO damaged from

    10U_0603_6.3V6M~D
    0_0402_1% over?voltage on +5VD or Standby power line, we
    suggested using this Voltage suppressing device.

    0.1U_0402_10V7K
    1 2
    10U_0603_6.3V6M~D

    CA12
    +3VS_AUDIO
    1 2 +DVDDIO

    CA13
    LA4 0.1U_0402_10V7K
    BLM15BB220SN1D_2P 2 1
    2 1
    CA15
    CA14

    1 2 Beep sound moat

    CA16
    +DVDDIO AGND RA2
    1 2 1 2 MONO_IN
    <38> BEEP
    RA3 1 @ 2 0_0402_1% 1K_0402_1%
    +DVDD +RTCVCC 0.1U_0402_10V7K

    100P_0402_50V8J
    Near Codec
    1
    RA4

    CA17
    PVT_0008 <13> SPKR 1 2

    1
    2 1K_0402_1% 1
    R17 @ CA18

    18

    41

    46

    40

    20

    33
    3
    U5 1K_0402_1% 100P_0402_50V8J~D

    DVDD-IO

    PVDD1

    PVDD2

    AVDD1

    CPVDD/AVDD2

    5VSTB/AUX MODE
    DVDD
    2

    2
    C C
    DMIC_DAT12_CODEC RA5 1 2 22_0402_5% DMIC_DAT12_CODEC_R 4
    <35> DMIC_DAT12_CODEC GPIO_0/DMIC DATA12 MONO_IN
    34
    DMIC_CLK_CODEC RA6 1 2 22_0402_5% DMIC_CLK_CODEC_R 5 PCBEEP
    <35> DMIC_CLK_CODEC GPIO_1/DMCI CLK Close to U5 Pin2
    2 RA7 1 2 1K_0402_5%
    DMIC_DAT34_CODEC RA61 1 2 22_0402_5% DMIC_DAT34_CODEC_R 1 PDB
    <35> DMIC_DAT34_CODEC GPIO_2/DMIC DATA34

    23
    AMP_I2C_DAT 6 CBP
    <25> AMP_I2C_DAT I2C DATA 24 CA19 1 2 2.2U_0603_6.3V6K~D
    AMP_I2C_CLK 7 CBN 0603 package size +DVDD
    <25> AMP_I2C_CLK I2C CLK for 16 Ohm THD+N
    AMP_I2S_IN 8
    3271'S I2C supports master mode only. I2S IN 29 MIC2_VREFO_R <26>

    2
    AMP_I2S_OUT 9 Mic2-VrefO-R
    I2S OUT 28 RA8
    AMP_I2S_BCLK Mic2-VrefO-L MIC2_VREFO_L <26>
    10 100K_0201_5%
    +DVDD I2S BCLK 31
    AMP_I2S_MCLK Mic2-R/Sleeve SLEEVE <26>
    11 D7

    1
    I2S MCLK 30 2 1
    AMP_I2C_DAT AMP_I2S_LRCK Mic2-L/Ring2 RING2 <26> <25> AMP_MUTE# NB_MUTE# <38>
    RA9 1 2 2.2K_0402_5% 12

    1
    I2S LRCK
    AMP_I2C_CLK RB751V40_SC76-2
    RA10 1 2 2.2K_0402_5% @
    +DVDD RA11 1 2 100K_0402_1%~D 47 RA12 D8
    HDA_BIT_CLK_R I2S_IN/I2S_OUT JD 36 1K_0201_5% 2 1
    JACK_PLUG Line1-L LINE1_L <26> PCH_MUTE# <10>
    <26> JACK_PLUG RA13 1 2 200K_0402_1% 48

    2
    JACK_PLUG HP/Line 1 JD
    EMC@ CA21

    35 LINE1_R <26>
    Line1-R RB751V40_SC76-2
    @ CA20 1 2 0.1U_0402_10V7K
    100P_0402_50V8J

    D9
    HP2_D_R CODEC_MUTE#
    47P_0402_50V8J~D

    1 1 26 2 1
    HDA_BIT_CLK_R HPOut-R HP2_D_R <26>
    @ CA22

    14
    <13> HDA_BIT_CLK_R AUDIOLINK: BCLK HP2_D_L
    27 HP2_D_L <26>
    HPOut-L RB751V40_SC76-2
    15
    2 2 <13> HDA_SYNC_R AUDIOLINK:SYNC
    RA14 1 2 33_0201_1% HDA_SDIN0_R 16
    <13> HDA_SDIN0 AUDIOLINK:SDATA-IN +DVDD
    Near Codec 32 CA23 1 2 10U_0402_6.3V6M
    MIC2-CAP AGND
    <13> HDA_SDOUT_R 17 100K is used to speed up
    AUDIOLINK:SDATA-OUT 39 the discharge for LDO1.
    LDO1-CAP RA15 1 2 100K_0201_5% CODEC_MUTE#

    100K_0402_1%~D

    10U_0603_6.3V6M~D
    1
    38 CA24 1 2 2.2U_0402_6.3V6M 1
    DMIC_CLK_CODEC VREF

    RA16

    CA26
    1 42
    SPK-OUT-LP 21 CA25 2 1 10U_0603_6.3V6M~D
    B B
    EMC@ CA28 43 LDO2-CAP
    SPK-OUT-LN 13 CODEC_MUTE# 2

    2
    10P_0201_25V9 2 DMIC_CLK_CODEC 44 DC DET/EAPD AGND
    SPK-OUT-RN 19 CA27 2 1 10U_0603_6.3V6M~D
    DMIC_DAT12_CODEC DMIC_DAT34_CODEC LDO3-CAP
    TVNST52302AB0_SOT523-3

    TVNST52302AB0_SOT523-3

    45
    DMIC_DAT12_CODEC SPK-OUT-RP
    1
    3

    AGND
    Thermal Pad

    EMC@ CA29

    10P_0201_25V9 2
    CPVEE
    AVSS2

    AVSS1

    EMC@ D10 EMC@ D73


    1

    DMIC_DAT34_CODEC
    1
    ALC3271-CG_MQFN48_6X6
    22

    37

    25

    49

    EMC@ CA83 Need update CIS symbol(31 30 revese)


    2.2U_0603_6.3V6K~D

    10P_0201_25V9 2 1
    CA30

    HP2_D_R moat
    Reserved for EMI AGND
    2

    330P_0402_50V7K
    1

    CA31
    0603 package size @ JPA1
    for 16 Ohm THD+N 2 1

    2
    AGND
    JUMP_43X39
    @ JPA2
    POST I2S interface 2 1
    HP2_D_L JUMP_43X39
    AMP_I2S_IN

    330P_0402_50V7K
    RA17 1 2 33_0402_5% GND AGND
    AMP_I2S_IN_R <25>

    1
    AMP_I2S_OUT

    CA32
    RA18 1 2 33_0402_5% AMP_I2S_OUT_R <25> Near AVDD1 and AVDD2 power source input
    AMP_I2S_BCLK RA19 1 2 33_0402_5% AMP_I2S_BCLK_R <25> <JPA1> Place at Codec bot t o m si de.

    2
    AMP_I2S_MCLK RA20 1 2 33_0402_5%
    <JPA2> Place near audio connector.
    AMP_I2S_MCLK_R <25> Don't short this pad to USB digital ground,
    AMP_I2S_LRCK RA21 1 2 33_0402_5% AMP_I2S_LRCK_R <25>
    and should be far away from any power traces.
    A A
    33P_0402_50V8J

    33P_0402_50V8J

    33P_0402_50V8J

    33P_0402_50V8J

    33P_0402_50V8J

    Vendor Suggested
    1

    1
    CA33

    CA34

    CA35

    CA36

    CA37
    2

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P24-Audio Codec3271
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 24 of 61
    5 4 3 2 1
    5 4 3 2 1

    SMART AMP
    B+_AMP B+_AMP

    10U_0603_25V6M

    10U_0603_25V6M

    0.1U_0402_25V6K~D

    1000P_0402_25V8J

    0.1U_0402_25V6K~D

    10U_0603_25V6M
    1 1 1 1 1

    1
    Vinafix.com

    CA40

    CA41

    CA42

    CA43
    CA38

    CA39
    PVT_0008

    2
    B+ B+_AMP 2 2 2 2 2

    D D
    R18 1 @ 2 0_0603_5% PVT_0008
    RA22
    B+_AMP
    1 @ 2 +1.8VS_AUDIO

    10U_0603_25V6M

    0.1U_0402_25V6K~D

    1000P_0402_25V8J

    0.1U_0201_6.3V6K

    1U_0201_6.3V6M
    1 1 1 1

    1
    CA44

    CA45

    CA46
    0_0402_1%

    CA47

    CA48
    2
    2 2 2 2

    RA23
    +DVDD

    0.1U_0402_16V7K~N 0.1U_0402_16V7K~N

    1U_0201_6.3V6M
    B+_AMP @ 1 1

    2
    0.1U_0402_25V6K~D

    1000P_0402_25V8J

    CA49
    1

    1
    10U_0603_25V6M

    CA51

    CA52

    CA53
    1

    CA50
    RA24 2 2

    2
    2 1 2

    0_0402_5%
    1
    2
    100K_0402_5%
    +1.8VS_AUDIO

    1U_0201_6.3V6M
    1 1

    CA55
    1U_0603_25V6

    1U_0603_25V6

    CA56
    B+_AMP

    1
    10U_0603_25V6M

    10U_0603_25V6M

    CA57

    CA54
    2 2

    0.1U_0402_25V6K~D

    1000P_0402_25V8J
    1 1 1

    1
    CA60

    CA61

    2
    CA58

    CA59
    PVT_0004

    2
    2 2 2
    RA25 1 @ 2 0_0402_5% EC_I2C_DAT <38>

    56

    51

    48

    43

    42

    37

    21

    40

    16

    17
    1

    3
    U6 RA26 1 @ 2 0_0402_5% EC_I2C_CLK <38>

    AVDD1

    AVDD2

    PGVdd
    PVDD-C

    PVDD-D

    PVDD-D

    GVDD-CD

    DVDD
    DVDD-IO
    PVDD-A

    PVDD-A

    PVDD-B

    GVDD-AB
    C 7 AMP_I2C_DAT_R RA27 1 @ 2 0_0402_1% C
    AMP_OUT_L- SDA AMP_I2C_DAT <24> +DVDD
    CA62 1 2 0.22U 25V K X5R 2
    RA28 10K_0402_0.1% BST-A 8 AMP_I2C_CLK_R RA33 1 @ 2 0_0402_1%
    AMP_OUT_P_L-_R AMP_OUT_L+ SCL AMP_I2C_CLK <24>
    1 2 CA63 1 2 0.22U 25V K X5R 50
    BST-B AMP_ADDR_SEL

    10K_0402_5%
    @ RA30
    RA29 10K_0402_0.1% 18
    ASEL

    1
    1 2 SPK_OUT_L-_R AMP_OUT_R- CA64 1 2 0.22U 25V K X5R 49
    BST-C PVT_0008
    RA31 10K_0402_0.1% 39
    1 2 SPK_OUT_L+_R AMP_OUT_R+ CA65 1 2 0.22U 25V K X5R 41 SYNC-IN
    RA32 10K_0402_0.1% BST-D 38
    1 2 AMP_OUT_P_R-_R SYNC-OUT

    2
    RA34 10K_0402_0.1% CA66 1 2 10U_0402_6.3V6M 22
    1 2 SPK_OUT_R-_R LDO A1.5 55 AMP_OUT_L- AMP_ADDR_SEL
    RA36 10K_0402_0.1% AMP_OUT_P_L- RA35 1 2 39K +-0.1% 0402 AMP_OUT_P_L-_R 25 OUT-A
    SPK_OUT_R+_R LISENDE_P AMP_OUT_L+

    10K_0402_5%
    1 2 52
    OUT-B

    1
    SPK_OUT_L- RA37 1 2 39K +-0.1% 0402 SPK_OUT_L-_R 26
    LISENDE_N/LVSENSE_P AMP_OUT_R-

    RA38
    47
    SPK_OUT_L+ RA39 1 2 39K +-0.1% 0402 SPK_OUT_L+_R 27 OUT-C
    LVSENSE_N 44 AMP_OUT_R+
    OUT-D I2C Address Selection

    2
    RA40 1 2 22.6K_0402_1% 5 Low : 0x20
    OC_ADJ Hi : 0x22
    23 CA67 1 2 0.1U_0402_25V6K~D
    AMP_OUT_P_R- RA41 1 2 39K +-0.1% 0402 AMP_OUT_P_R-_R 28 VREF
    RISENSE_P
    SPK_OUT_R- RA42 1 2 39K +-0.1% 0402 SPK_OUT_R-_R 29 9
    RISENSE_N/RVSENSE_P MCLK AMP_I2S_MCLK_R <24>
    SPK_OUT_R+ RA43 1 2 39K +-0.1% 0402 SPK_OUT_R+_R 30 10
    RVSENSE_N BCLK AMP_I2S_BCLK_R <24>
    11 AMP_I2S_LRCK_R <24>
    LRCK
    32 12 AMP_I2S_OUT_R <24>
    NC DACDAT
    31 13
    NC SPDIF_IN
    36 14 AMP_I2S_IN_R <24>
    NC SPDIF OUT/I2S DATOUT
    35 15 AMP_MUTE# <24>
    NC PDBJD

    Thermal Pad
    B B

    PGND-CD

    PGND-CD

    PGND-AB

    PGND-AB
    Int. Speaker Conn.

    DGND
    AGND

    AGND

    AGND

    AGND
    GND
    4

    34

    33

    24

    20

    19

    46

    45

    54

    53

    57
    ALC1309-CG_QFN56_7X7

    Use 120 ohm bead 40mil = For 4ohm 3W Speaker

    1
    (SM01000L300, MURATA BLM15PX121SN1D) EVT1.1 use SA00009JZ10

    10K_0402_5%
    EMC@ LA5 BLM15PX121SN1D_2P RA44 0.2_0805_ 1%
    AMP_OUT_L- 1 2 AMP_OUT_P_L- 1 2 SPK_OUT_L-

    RA66
    EMC@ LA6 BLM15PX121SN1D_2P

    2
    AMP_OUT_L+ 1 2 SPK_OUT_L+
    EMC@ LA7 BLM15PX121SN1D_2P RA45 0.2_0805_ 1%
    AMP_OUT_R- 1 2 AMP_OUT_P_R- 1 2 SPK_OUT_R-
    EMC@ LA8 BLM15PX121SN1D_2P
    AMP_OUT_R+ 1 2 SPK_OUT_R+
    330P_0201_50V7K

    330P_0201_50V7K

    330P_0201_50V7K

    330P_0201_50V7K

    680P_0402_50V7K~D

    680P_0402_50V7K~D

    680P_0402_50V7K~D

    680P_0402_50V7K~D
    CA68 EMC@

    CA69 EMC@

    CA70 EMC@

    CA71 EMC@

    1 1 1 1
    1

    CA72

    CA73

    CA74

    CA75

    JSPK1
    SPK_OUT_L+ 1 SPK_OUT_L+ SPK_OUT_R+
    2

    2 2 2 2 SPK_OUT_L- 2 1 SPK_OUT_L- SPK_OUT_R-


    SPK_OUT_R+ 3 2
    PVT_0008 SPK_OUT_R- 3
    4
    4

    EMC@ DA1
    ESD203-B1-02EL_TSLP-2-20-2

    EMC@ DA2
    ESD203-B1-02EL_TSLP-2-20-2

    EMC@ DA3
    ESD203-B1-02EL_TSLP-2-20-2

    EMC@ DA4
    ESD203-B1-02EL_TSLP-2-20-2
    5
    5
    1

    1
    AMP_I2C_CLK_R RA64 1 2 0_0402_1% SPK_CLK 6
    RA46 EMC@

    RA47 EMC@

    RA48 EMC@

    RA49 EMC@

    @
    10_0402_1%

    10_0402_1%

    10_0402_1%

    10_0402_1%

    AMP_I2C_DAT_R RA63 1 @ 2 0_0402_1% SPK_DAT 7 6


    SPK_VDD 8 7
    8
    SPK_DET# @ RA62 1 2 0_0402_5% 9
    <13> SPK_DET#
    2

    10 GND

    2
    RA50 1 2 0_0402_5% GND
    +3VS_AUDIO
    ACES_50208-00801-003
    A CONN@ A

    Function RA50 RA62

    EEPROM Speaker 0 ohm NC


    DELL CONFIDENTIAL/PROPRIETARY
    Speaker Detection 10K 0 ohm Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P25-Smart AMP / Speaker
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 25 of 61
    5 4 3 2 1
    5 4 3 2 1

    Universal Audio Jack

    Vinafix.com
    D D

    RA51
    2.2K_0402_5%~D
    <24> MIC2_VREFO_L 1 2

    JAUDIO1
    RA521 2 BLM15PX330SN1D_2P RING2_R JACK_PLUG 1 2 RING2_R
    <24> RING2 HP2_D_L HP2_D_L_R1 LA9 1 HP2_D_L_C 1 2
    1 2 2 BLM15PX330SN1D_2P 3 4
    <24> HP2_D_L HP2_D_L_C 3 4
    RA53 5.6_0402_5% 5 6
    HP2_D_R_C 7 5 6 8
    JACK_PLUG SLEEVE_R 9 7 8 10 SLEEVE_R
    HP2_D_R HP2_D_R_R1 LA10 1 <24> JACK_PLUG HP2_D_R_C 9 10
    RA54 1 2 5.6_0402_5% 2 BLM15PX330SN1D_2P
    <24> HP2_D_R SLEEVE_R
    1 2
    <24> SLEEVE
    RA55 BLM15PX330SN1D_2P 11 13
    12 GND GND 14
    GND GND
    HRS_BM20B(0P8)10DS0P4V(51)
    40mil

    EMC@ DA9
    AZ5123-01F.R7G_DFN1006P2X2
    <24> MIC2_VREFO_R 1 2 CONN@

    EMC@ DA5
    AZ5123-01F.R7G_DFN1006P2X2

    EMC@ DA6
    AZ5123-01F.R7G_DFN1006P2X2

    EMC@ DA7
    AZ5123-01F.R7G_DFN1006P2X2

    EMC@ DA8
    AZ5123-01F.R7G_DFN1006P2X2
    RA56
    2.2K_0402_5%~D AGND

    680P_0402_50V7K~D

    680P_0402_50V7K~D

    680P_0402_50V7K~D

    680P_0402_50V7K~D
    CA76

    CA77

    CA78

    CA79

    1
    1

    1
    1 1 1 1

    2 2 2 2

    2
    PCB trace width of MIC2-R(SLEEVE)/MIC2-L(RING2) are

    2
    required at least 40 mil for HP crosstalk consideration
    and, its length should be as short as possible.

    AGND

    C C
    PVT_0008

    CA80 1 2 10U_0603_6.3V6M LINE1_L_C RA57 1 @ 2 0_0402_1% HP2_D_L


    <24> LINE1_L
    CA81 1 2 10U_0603_6.3V6M LINE1_R_C RA58 1 @ 2 0_0402_1% HP2_D_R
    <24> LINE1_R

    1
    @ RA59 @ RA60
    9.09K_0402_1% 9.09K_0402_1%

    2
    AGND AGND

    B B

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P26-Audio CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 26 of 61
    5 4 3 2 1
    5 4 3 2 1

    NOTE:
    Follow the SPI topology layout guidelines
    in the relevant Intel Platform Design Guide TPM NOTE:
    Place 0.1 uF capacitors as close as
    possible to the device power pins

    D
    Vinafix.com +3VS_TPM +TPM_VSB
    D
    For NPCT650x: connect to +3V_PCH

    +3VS +3V_PCH +3VS_TPM


    650@ R19
    1 2 0_0603_5% C27 C28 C29 C30

    0.1U_0201_10V6K
    1 1 1 1 C1081 1 1 C1082

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    10U_0603_6.3V6M
    750@ R5838
    1 2 0_0603_5%

    For NPCT750x: connect to S0 power well (+3VS) 2 2 2 2 2 2 4.7U_0402_6.3V6M

    +3V_PCH

    RH75 1 2 10K_0201_5% TPM_PIRQ#


    +TPM_VSB +3VALW
    C C
    U7 RC382
    750@ 1 2 @ 1
    RE2 1 2 0_0402_5% 29 VSB
    <12,34,60> SIO_SLP_S0# GPIO0/SDA/XOR_OUT +TPM_LPM
    30 8 0_0603_5%
    1 2 3 GPIO1/SCL VDD 14
    GPIO2/GPX VDD +3VS_TPM
    RE104 0_0402_5%~D 6 22 PVT_0008
    GPIO3/BADD VDD @
    650@ +TPM_LPM
    24 2 2 1
    <9> PCH_SPI_SO_TPM LAD0/MISO NC +3VS_TPM
    21 7 0_0402_5% RC178
    <9> PCH_SPI_SI_TPM TPM_PIRQ# LAD1/MOSI NC
    18 10
    <9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 0_0402_1%2 @ 1 RC179
    PVT_0008 LAD3 NC +3VS
    25
    PCH_SPI_CLK_TPM RE263 1 @ 2 0_0402_1% PCH_SPI_CLK_TPM_R 19 NC 26
    <9> PCH_SPI_CLK_TPM PCH_SPI_CS2# PCH_SPI_CS2#_R LCKL/SCLK NC
    RE262 1 @ 2 0_0402_1% 20 31
    <9> PCH_SPI_CS2# LFRAME#/SCS# NC
    <12,28,29,30,39,41> PCH_PLTRST#_EC 17 PVT_0008
    R22 2 650@ 1 27 LRESET#/SPI_RST#/SRESET# 9
    10K_0201_5% 13 SERIRQ GND 16
    28 CLKRUN#/GPIO4/SINT# GND 23
    LPCPD# GND 32
    4 GND 33 +TPM_LPM
    +3VS_TPM 5 PP PGND 12 close to U7.8
    TEST Reserved C31 CA82

    4.7U_0402_6.3V6M
    1 1

    0.1U_0201_10V6K
    1

    B NPCT750JAAYX QFN ES B
    RE27
    @ 4.7K_0402_5%
    2 2
    1 2

    SA0000AQ200 :
    @
    RE29
    10K_0402_5%
    S IC NPCT750JAAYX QFN 32P TPM F/W is 7.1.0.0 - ES
    SA0000AQ220 :
    2

    S IC NPCT750JAAYX QFN 32P TPM F/W is 7.2.0.0 - QS

    @EMC@ C32
    2 1 PCH_SPI_CLK_TPM_R

    0.1U_0201_10V6K
    Reserve for EMI please close to U7
    A A
    1. Pin14&Pin22 (+3VS_TPM):
    For NPCT650x: connect to same power well with host SPI interface (it should be +3V_PCH)
    For NPCT750x: connect to S0 power well (+3VS)
    DELL CONFIDENTIAL/PROPRIETARY
    2. Pin27:
    For NPCT650x: pop R22
    Security Classification Compal Secret Data Compal Electronics, Inc.
    For NPCT750x: de-pop R22 2015/12/16 2016/12/13 Title
    3. SLP_S0# connection: Issued Date Deciphered Date
    For NPCT650x: pop RE104, de-pop RE2
    For NPCT750x: pop RE2, de-pop RE104 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P27-TPM
    4. RC180 can be just deleted for both NPCT650x and NPCT750x AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    5. TPM_PIRQ# is recommended that pull-up to same GPIO power well at host side DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 27 of 61
    5 4 3 2 1
    A B C D E

    M.2 Slot-A Key-A (WLAN)

    1.1A @ Peak current from 3.3 V supply,


    including Wi-Fi and BT. Averaged over 25 usecase.
    +3VS_NGFF
    +3VS_NGFF WL1

    Vinafix.com Close to JNGFF RF Reserved.


    4
    5
    72
    3.3V
    3.3V
    3.3V PEWAKE#
    29 PCIE_WAKE# <39>

    22U_0603_6.3V6M~D

    0.1U_0402_10V7K

    15P_0402_50V8J
    C35
    73 30
    3.3V CLKREQ# CLKREQ_PCIE#1 <12>
    1 1 1 31
    1 PERST# PCH_PLTRST#_EC <12,27,29,30,39,41> 1

    C34

    C33

    EMC@
    1
    2 UIM_POWER_SRC/GPIO1 27 @ 0_0402_5%~D 2 1 R23
    EXC24CH900U_4P 2 2 2 3 UIM_POWER_SNK SUSCLK(32KHZ) SUSCLK <12,30>
    4 3 USB20_P7_CONN UIM_SWP
    <11> USB20_P7
    14
    11 SYSCLK/GNSS0 15
    1 2 USB20_N7_CONN 12 COEX1 TX_BLANKING/GNSS1
    <11> USB20_N7 COEX2
    13
    L2 EMC@ COEX3 7
    NFC_RESET#

    2
    16
    D74 EMC@ 18 RESERVED/VDDIO18
    PESD5V0U2BT_SOT23-3 19 RESERVED/ISH2_UART_RXD(I)(0/1.8V) 6
    66 RESERVED/ISH2_UART_TXD(O)(0/1.8V) GND 17
    AZC199-02SPR7G_SOT23-3 67 RESERVED/ISH2_UART_RTS(O)(0/1.8V) GND 20
    RESERVED/ISH2_UART_CTS(I)(0/1.8V) GND 23

    1
    21 GND 26
    22 ISH1_UART_CTS(I)(0/1.8V) GND 32
    24 ISH1_UART_RTS(O)(0/1.8V) GND 35
    25 ISH1_UART_RXD(I)(0/1.8V) GND 38
    ISH1_UART_TXD(O)(0/1.8V) GND 41
    GND 62
    33 GND 68
    <12> CLK1_PCIE_WLAN# REFCLKN0 GND
    <12> CLK1_PCIE_WLAN 34 71
    CLK1_PCIE_WLAN REFCLKP0 GND 74
    CLK1_PCIE_WLAN# CH1 1 2 0.1U_0402_10V7K~D PCIE_PRX_WLANTX_N3_C 36 GND 75
    <11> PCIE_PRX_WLANTX_N3 PCIE_PRX_WLANTX_P3_C PETN0 GND
    <11> PCIE_PRX_WLANTX_P3 CH2 1 2 0.1U_0402_10V7K~D 37 76
    @EMC@ @EMC@ PETP0 GND 77
    CH4 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N3_C 39 GND 78
    1 1 <11> PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3_C PERN0 GND
    15P_0402_50V8J
    C36

    15P_0402_50V8J
    C37

    CH5 1 2 0.1U_0402_10V7K~D 40 79
    <11> PCIE_PTX_WLANRX_P3 PERP0 GND 80
    GND 81
    2 2 L@ R24 1 2 0_0402_5%~D CL_CLK_R 42 GND 82
    <9> CL_CLK CL_DAT_R CLINK_CLK GND
    L@ R25 1 2 0_0402_5%~D 43 83
    <9> CL_DAT CL_RST#_R CLINK_DATA GND
    L@ R26 1 2 0_0402_5%~D 44 84
    <9> CL_RST# CLINK_RESET GND 85
    GND 86
    2 CLINK use for Intel only 2
    45 GND 87
    46 SDIO_RESET#(I) GND 88
    47 SDIO_WAKE#(O) GND 89
    Commodity WLAN CPN SDIO_DATA3(IO)/WIGIG_UART_RXD(I) GND
    48 90
    49 SDIO_DATA2(IO)/WIGIG_UART_TDX(O) GND 91
    Italia XPS Killer1435-S PK32000HO0L R24~R26 de-pop
    50 SDIO_DATA1(IO)/WIGIG_UART_RTS(O) GND 92
    51 SDIO_DATA0(IO)/WIGIG_UART_CTS(I) GND 93
    Italia-L Intel 8265 PK32000GH0L R24~R26 pop
    52 SDIO_CMD(IO) GND 94
    SDIO_CLK(I) GND 95
    53 GND 96
    WL1 L@ WL1 XPS@ 54 UART WAKE#(3.3V) GND 97
    55 LPSS_UART_CTS GND 98
    56 LPSS_UART_TXD GND 99
    57 LPSS_UART_RXD GND 100
    LPSS_UART_RTS GND 101
    GND 102
    PK32000GH0L PK32000HO0L 58 GND 103
    59 PCM_SYNC/I2S_WS GND 104
    8265D2WML.NVQ_108P U69H025.10 KILLER1435-S PCM_IN/I2S_SD_IN GND
    60 105
    61 PCM_OUT/I2S_SD_OUT GND 106
    PCM_CLK/I2S_SCK GND 107
    +3VS_NGFF GND 108
    DZ2
    1 2 WLAN_WIGIG60GHZ_DIS#_R 28 GND
    <38> WLAN_WIGIG60GHZ_DIS# 63 W_DISABLE1#
    2.2K_0201_5% 2 @ 1 RC181 WLAN_WIGIG60GHZ_DIS#_R W_DISABLE2#
    2 1 RC182 BT_RADIO_DIS#_R RB751V40_SC76-2
    2.2K_0201_5% @ DZ3
    1 2 BT_RADIO_DIS#_R 65
    <38> BT_RADIO_DIS# LED1#
    64
    LED2#
    RB751V40_SC76-2
    USB20_N7_CONN 69
    USB20_P7_CONN 70 USB_D-
    USB_D+
    8
    9 ALERT#
    10 I2C_CLK
    I2C_DATA
    3 3
    8265D2WML.NVQ_108P
    @

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P28-WLAN / BT
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 28 of 61
    A B C D E
    5 4 3 2 1

    Card Reader +ODR_PW R

    SD_D2
    SD_D3
    1
    2
    JCR1
    DAT2
    SD_CMD 3 CD/DAT3 Close to JCR1
    4 CMD
    SD_CLK 5 VDD1 +ODR_PW R +SD_VDD2
    +3VS +3VS_CR +3VS_CR 6 CLK
    1.DAT2 4.VDD1 SD_RCLK_P 7 VSS

    Vinafix.com
    RT70 1 @ 2 0_0603_5%
    2.DAT3
    3.CMD
    15.VDD2
    +SD_VDD2
    SD_RCLK_M
    SD_CD#
    8
    9
    DAT0/RCLK+
    DAT1/RCLK-
    CD
    CR1 CR2 1 CR3 1 CR4 1

    1
    C39 1 C40 5.CLK

    1
    D EMC@ EMC@ 7.RCLK+ 15 D
    VDD2

    10U_0402_6.3V6M

    0.1U_0201_10V6K

    4.7U_0402_6.3V6M

    0.1U_0201_10V6K
    8.RCLK- 16

    2
    SWIO 2 2 2

    100P_0201_50V8J

    22P_0402_50V8J
    PVT_0008 9.CD 17

    2
    2 16. NC SD_LN0_P 18 VSS
    6.VSS SD_LN0_M 19 D0+
    17.VSS 20 D0- 10
    20.VSS SD_LN1_M 21 VSS GND 11
    23.VSS SD_LN1_P 22 D1- GND 12
    18.D0+ 10 23 D1+ GND 13
    19.D0- 11 VSS GND 14
    21.D1- 12 GND
    22.D1+ 13 T-SOL_158-1160902600
    14 CONN@

    Tom0114:wait CIS symbol


    TAISOL 158-1160902600 Use LTCX007ZY00
    VDD1=ODR_PWR=3.3V
    VDD2=SD_VDD2=1.8V
    changed footprint & CPN

    +3VS_CR +3VS_CR

    C CR5 1 CR6 1 CR7 CR8 1 C

    1
    0.1U_0201_10V6K

    4.7U_0402_6.3V6M

    10U_0402_6.3V6M

    0.1U_0201_10V6K
    2
    2 2 2

    27
    11
    UR1
    +ODR_PW R

    3V3aux
    3V3_IN
    <12,27,28,30,39,41> PCH_PLTRST#_EC 1 12
    2 PERST# CARD_3V3 18 DV33_18 CR9 2 1 1U_0201_6.3V6M
    MEDIACARD_IRQ# <12> CLKREQ_PCIE#5 CLK_REQ# DV33_18
    +3VS_CR RR1 2 1
    10K_0201_5% <12> CLK_PCIE_MMI 5
    6 REFCLKP 15 SD_RCLK_M
    <12> CLK_PCIE_MMI# REFCLKN SP1 SD_RCLK_P
    16
    CR23 1 2 0.1U_0201_10V6K PCIE_PTX_CARDRX_P1_C 3 RTS5242 SP2 17 SD_CLK_L RR4 1 @ 2 0_0201_5% SD_CLK
    <11> PCIE_PTX_CARDRX_P1 PCIE_PTX_CARDRX_N1_C HSIP SP3 SD_CMD
    <11> PCIE_PTX_CARDRX_N1 CR22 1 2 0.1U_0201_10V6K 4 19
    CR10 1 2 0.1U_0201_10V6K PCIE_PRX_CARDTX_P1_C 7 HSIN SP4 20 SD_D3
    <11> PCIE_PRX_CARDTX_P1 PCIE_PRX_CARDTX_N1_C HSOP SP5 SD_D2
    <11> PCIE_PRX_CARDTX_N1 CR11 1 2 0.1U_0201_10V6K 8 21
    HSON SP6 29 SP7_SDW P
    SP7 1
    EMC@ CR17
    MEDIACARD_IRQ#

    2.2P_0402_50V8C
    <9> MEDIACARD_IRQ# 32
    31 WAKE#
    SD_CD# MS_INS# PVT_0008 2
    Support Runtime D3 mode => DE-POP RR1 30
    B SD_CD# B
    No Support Runtime D3 mode => POP RR1 22 SD_LN1_P
    SD_LN1_P 23 SD_LN1_M
    CR18 1 2 DV12S 10 SD_LN1_M
    0.1U_0201_10V6K 14 AV12 26 SD_LN0_P
    DV12S SD_LN0_P 25 SD_LN0_M
    CR19 13 SD_LN0_M
    1 CR21 1 +SD_VDD2 SD_VDD2 24 SD_REG2 CR20 2 1 1U_0201_6.3V6M
    E-PAD

    RR8 1 2 RREF 9 SDREG2 28 RR9 2 1 10K_0201_5%


    RREF GPIO +3VS_CR
    0.1U_0201_10V6K

    4.7U_0402_6.3V6M

    6.2K_0402_1%
    2 2
    Close to UR1 RTS5242-GR_QFN32_4X4 If GPIO not use for LED function,
    33

    must be pull-high (Layout guide)

    QR1 +3VS_CR
    1)Placing the RTS5242 chip and flash card socket locate to suit trace routing for SI / EMI / ESD. For GPIO control SD_WP
    2)Keep bulk and de-coupling capacitors as close as possible to the RTS5242 chip and flash card socket. L2N7002W T1G_SC-70-3
    ■ Bulk capacitor for Card_3V3 place closed to flash card socket.

    1
    SP7_SDW P 1 3

    S
    ■ Bulk capacitor for 3V3_IN / 3V3aux / DV12S place closed to RTS5242 chip.
    RR10
    3)Keep damping resistor (ex, for SD CLK / MS CLK) as close as possible to the RTS5242 chip. @
    4)Keep these capacitors for SD card / MS card signals as close as possible to flash card socket. 10K_0201_5%

    G
    2
    <10> HOST_SD_W P#

    2
    SP7_SDW P
    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P29-Card Reader - RT5242
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 29 of 61
    5 4 3 2 1
    5 4 3 2 1

    M.2 Slot-C Key-M (SSD)

    Vinafix.com +3.3VDX_SSD
    D D

    JNGFF1 RF Reserved.
    1 2
    3 GND 3.3V 4 EMC@ EMC@
    GND 3.3V

    4.7U_0402_6.3V
    C41

    .1U_0402_16V7K~D
    C42

    0.01U_0402_16V7K~D
    C43

    47P_0402_50V8J~D
    C44

    15P_0402_50V8J
    C45
    <11> PCIE_PRX_SSDTX_N9 5 6 R5827 SCP@ 1 1 1 1 1
    7 PERn3 NC 8 1 2
    <11> PCIE_PRX_SSDTX_P9 PERp3 NC SSD_SCP <38>
    9 10
    CD92 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N9_C 11 GND DAS/DSS#/LED# 12 0_0402_5%~D
    <11> PCIE_PTX_SSDRX_N9 PCIE_PTX_SSDRX_P9_C PETn3 3.3V 2 2 2 2 2
    CD93 1 2 0.22U_0402_10V6K 13 14
    <11> PCIE_PTX_SSDRX_P9 PETp3 3.3V
    15 16
    17 GND 3.3V 18
    <11> PCIE_PRX_SSDTX_N10 PERn2 3.3V
    <11> PCIE_PRX_SSDTX_P10 19 20
    21 PERp2 NC 22
    CD94 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N10_C 23 GND NC 24
    <11> PCIE_PTX_SSDRX_N10 PCIE_PTX_SSDRX_P10_C PETn2 NC
    <11> PCIE_PTX_SSDRX_P10 CD95 1 2 0.22U_0402_10V6K 25 26 Use SE00000SO00
    27 PETp2 NC 28
    29 GND NC 30
    PCIe SSD <11> PCIE_PRX_SSDTX_N11
    31 PERn1 NC 32
    <11> PCIE_PRX_SSDTX_P11 PERp1 NC
    33 34
    CD96 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N11_C 35 GND NC 36 @ R29 2 1 10K_0402_5%~D
    <11> PCIE_PTX_SSDRX_N11 PCIE_PTX_SSDRX_P11_C PETn1 NC +3.3VDX_SSD
    CD97 1 2 0.22U_0402_10V6K 37 38
    <11> PCIE_PTX_SSDRX_P11 PETp1 DEVSLP SSD_DEVSLP <11>
    39 40
    R30 1 @ 2 0_0402_1% SATA_PRX_SSDTX_P2_C 41 GND NC 42
    <11> SATA_PRX_SSDTX_P2 SATA_PRX_SSDTX_N2_C PERn0/SATA-B+ NC
    R31 1 @ 2 0_0402_1% 43 44
    <11> SATA_PRX_SSDTX_N2 PERp0/SATA-B- NC
    45 46
    SATA SSD CD98 1 2 0.22U_0402_10V6K SATA_PTX_SSDRX_N2_C 47 GND NC 48
    <11> SATA_PTX_SSDRX_N2 SATA_PTX_SSDRX_P2_C PETn0/SATA-A- NC
    <11> SATA_PTX_SSDRX_P2 CD99 1 2 0.22U_0402_10V6K 49 50
    PETp0/SATA-A+ PERST#/NC PCH_PLTRST#_EC <12,27,28,29,39,41>
    51 52
    GND CLKREQ#/NC SSD_PCIE_WAKE# CLKREQ_PCIE#3 <12>
    53 54 R32 1 2 10K_0402_5%~D
    <12> CLK_PCIE_SSD# REFCLKn PEWAKE#/NC +3.3VDX_SSD
    <12> CLK_PCIE_SSD 55 56
    57 REFCLKp NC 58 @ R264 1 2 0_0402_5%~D
    GND NC PCIE_WAKE#_R <38,39,41>

    Solt M & Key M


    C
    Platform Pin-out C

    59 67 68 60 @ R33 1 2 0_0402_5%~D
    61 NC SUSCLK SUSCLK <12,28>
    R34 1 2 10K_0402_5%~D 69 70 62
    +3VS PEDET (NC-PCIe/GND-SATA) 3.3V +3.3VDX_SSD
    63 71 72 64
    65 73 GND 3.3V 74 66
    67 75 GND 3.3V
    GND
    69 77 76 68
    GND GND

    LOTES_APCI0146-P004A
    CONN@
    R35 1 @ 2 0_0402_1%
    <11> SSD_IFDET
    Use SP07001FKA0
    SATA -> GND SATA -> GND
    PCIe -> HI PVT_0008 PCIe -> HI

    FAN 1 FAN 2
    B B

    PVT_0016 PVT_0016
    +3VS +5VS +3VS +5VS
    10U_0603_25V6M

    10U_0603_25V6M
    2 2
    10K_0402_5%~D

    10K_0402_5%~D
    2

    2
    C1124

    C1125
    0.1U_0402

    0.1U_0402
    10K_0402_5%~D

    10K_0402_5%~D

    10K_0402_5%~D

    10K_0402_5%~D
    2

    2
    R38

    C46

    R41

    C47
    R36

    R37

    R39

    R40
    1

    1
    1 1
    JFAN1 JFAN2
    1

    1
    6 6
    1

    1
    LT6 5 G2 LT7 5 G2
    1 2 4 G1 1 2 4 G1
    HCB2012KF-121T50_0805 3 4 HCB2012KF-121T50_0805 3 4
    <38> FAN1_PWM D11 <38> FAN2_PWM D12
    2 1 2 3 2 1 2 3
    <38> FAN1_TACH 1 2 <38> FAN2_TACH 1 2
    1

    1
    1 1
    RB751V40_SC76-2 RB751V40_SC76-2
    D79 @ ACES_50224-00401-001 D78 @ ACES_50224-00401-001
    BAT54LPS-7 CONN@ BAT54LPS-7 CONN@
    2

    2
    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P30-SSD(M.2) / FAN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 30 of 61
    5 4 3 2 1
    A B C D E

    +3VS_MUX

    +3VS +3VS_MUX_L +3VS_MUX_L +3VS_MUX


    @ R42 LA11

    2
    0_0603_5% BLM15PX600SN1D_2P Close U30 PIN 1, 6 , 20 ,28
    1 2 2 1
    C1128 C48 C1127 C1126 C50 @ C51 MUX_I2C_CLK_R 1 6 UPD3_SMBCLK
    UPD3_SMBCLK <38,45>
    +3V_LDO
    Vinafix.com
    1 1 1 1 1 1

    10U_0402_6.3V6M

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    0.01U_0402_16V7K
    @ QC2A

    5
    R272 DMN66D0LDW-7_SOT363-6
    1 @ 2
    2 2 2 2 2 2 MUX_I2C_DATA_R 4 3 UPD3_SMBDAT
    1 UPD3_SMBDAT <38,45> 1
    0_0603_5%
    @ QC2B
    DMN66D0LDW-7_SOT363-6
    PVT_0008

    DCI @
    FLIP/SCL MUX_I2C_CLK_R R55 1 2 0_0402_5% UPD3_SMBCLK
    CTL0/SDA MUX_I2C_DATA_R R56 1 2 0_0402_5% UPD3_SMBDAT

    DCI @

    +3VS_MUX

    2
    DCI @
    +3VS_MUX
    R5807
    1K_0402_5%

    1
    I2C_EN

    2
    1 @
    If use PS8743B need pop CEXT @ @DCI_NC
    R5808 0_0402_5% U30 C49 R5834 R5802
    @ C70 1 2 CEXT NC 1 2 CEXT 1 35 PD3_USBC_EN EQ1 0.1U_0201_10V6K 20K_0402_5% 1K_0402_5%
    6 VCC EQ1 38 PD3_USBC_POL EQ0 2
    PD3_USBC_POL <45>

    1
    2.2U_0402_6.3V6M 20 VCC EQ0
    28 VCC 17 I2C_EN
    VCC I2C_EN
    2 DPEQ1 DPEQ1 DCI @
    C52 1 2 0.1U_0201_10V6K TBT_DP_ML0_P_C 9 DPEQ1 14 DPEQ0 DPEQ0/A1 R51 1 2 22_0402_5%
    <41> TBT_DP_ML0_P TBT_DP_ML0_N_C DP0p DPEQ0/A1 DCI_CLK <10>
    <41> TBT_DP_ML0_N C53 1 2 0.1U_0201_10V6K 10
    DP0n 3 ADDR DCI @
    C54 1 2 0.1U_0201_10V6K TBT_DP_ML1_P_C 12 SSEQ1 11 SSEQ0 SSEQ0/A0 R5836 1 2 22_0402_5%
    <41> TBT_DP_ML1_P TBT_DP_ML1_N_C DP1p SSEQ0/A0 DCI_DATA <10>
    2 <41> TBT_DP_ML1_N C56 1 2 0.1U_0201_10V6K 13 2
    DP1n @DCI_NC +3VS_MUX
    C58 1 2 0.1U_0201_10V6K TBT_DP_ML2_P_C 15 21 MUX_I2C_CLK_R R5811 1 2 0_0402_5%
    <41> TBT_DP_ML2_P TBT_DP_ML2_N_C DP2p FLIP/SCL MUX_FLIP_SEL <45>
    C59 1 2 0.1U_0201_10V6K 16
    <41> TBT_DP_ML2_N DP2n MUX_I2C_DATA_R MUX_I2C_CLK_R
    22 R5809 1 @DCI_NC 2 0_0402_5% Input From 65982 R57 1 @ 2 4.7K_0402_5%
    TBT_DP_ML3_P_C CTL0/SDA MUX_USB_SEL <45>
    <41> TBT_DP_ML3_P C60 1 2 0.1U_0201_10V6K 18
    C61 1 2 0.1U_0201_10V6K TBT_DP_ML3_N_C 19 DP3p 23 PD3_USBC_AMSEL_R CTL R5835 1 2 0_0402_5% MUX_I2C_DATA_R R58 1 @ 2 4.7K_0402_5%
    <41> TBT_DP_ML3_N DP3n CTL1 PD3_USBC_AMSEL <45>

    MUX_USB3_RX0_N 31 34 MUX_USB3_TX0_N_C 0.1U_0201_10V6K 1 2 C57 MUX_PD_SBU1 R62 1 2 2M_0201_5%


    <47> MUX_USB3_RX0_N MUX_USB3_RX0_P RX1n TX1n MUX_USB3_TX0_P_C MUX_USB3_TX0_N <47>
    <47> MUX_USB3_RX0_P 30 33 0.1U_0201_10V6K 1 2 C55
    RX1p TX1p MUX_USB3_TX0_P <47> MUX_PD_SBU2 R63 1 2 2M_0201_5%
    MUX_USB3_RX1_N 39 37 MUX_USB3_TX1_P_C 0.1U_0201_10V6K 1 2 C62
    <47> MUX_USB3_RX1_N MUX_USB3_RX1_P RX2n TX2p MUX_USB3_TX1_N_C MUX_USB3_TX1_P <47>
    40 36 0.1U_0201_10V6K 1 2 C63
    <47> MUX_USB3_RX1_P RX2p TX2n MUX_USB3_TX1_N <47>

    C68 1 2 0.1U_0201_10V6K USB3TP1_C 8 5 USB3RP1_C 0.1U_0201_10V6K 2 1 C66


    <11> USB3TP1 USB3TN1_C SSTXp SSRXp USB3RN1_C USB3RP1 <11>
    <11> USB3TN1 C69 1 2 0.1U_0201_10V6K 7 4 0.1U_0201_10V6K 2 1 C67 USB3RN1 <11>
    SSTXn SSRXn +3VS_MUX

    CAD_SNK 29 27 MUX_PD_SBU1 R46 1 @ 2 0_0402_1%


    TBT_DP_HPD_R RESVD1 SBU1 MUX_PD_SBU2 MUX_C_SBU1 <45,47> TBT_DP_AUX_N_C R44
    R50 1 2 0_0402_5% 32 26 R47 1 @ 2 0_0402_1% 2 1 100K_0201_5%
    <41,45> TBT_DP_HPD RESVD2 SBU2 MUX_C_SBU2 <45,47>
    24 TBT_DP_AUX_P_C 0.1U_0201_10V6K 2 1 C64 TBT_DP_AUX_P_C R45 2 1 100K_0201_5%
    AUXp TBT_DP_AUX_N_C TBT_DP_AUX_P <41,45>
    41 25 0.1U_0201_10V6K 2 1 C65
    PAD AUXn TBT_DP_AUX_N <41,45>

    TUSB546_QFN40_4X6 PVT_0003 PVT_0008

    SA00009R720 New CPN for DCI TUSB546A

    3 3

    @ R5833 2 1 0_0402_5%~D PD3_USBC_AMSEL_R PIN23 +3VS_MUX +3VS_MUX +3VS_MUX +3VS_MUX +3VS_MUX


    <41,45> TBT_DP_HPD +3VS_MUX +3VS_MUX
    DCI @ RC394 1 2 22_0402_5% CAD_SNK PIN29
    <10> DCI_DATA

    1
    @
    2

    1
    DCI @ RC393 1 2 22_0402_5% TBT_DP_HPD_R PIN32 @ @ R5797
    <10> DCI_CLK 1K_0402_5% 1K_0402_5% 1K_0402_5%
    R49 @ 1K_0402_5%
    1K_0402_5% 1K_0402_5% R5801 R48 @ R5798 @
    4.7K_0402_5%
    TI TUSB546 DCI function to add it R5804 R5806

    2
    1

    2
    DPEQ1 DPEQ0 ADDR SSEQ0
    CAD_SNK PD3_USBC_EN PD3_USBC_POL <DPEQ1> <DPEQ0> <SSEQ1> <SSEQ0>

    1
    <EQ1> <EQ0> @
    1

    1
    PIN DCI NON-DCI CAD_SNK/ RSVD1 R54
    1

    1K_0402_5% 20K_0402_5% 20K_0402_5%


    1K_0402_5% 1K_0402_5% 20K_0402_5%
    DP ENABLE IN GPIO mode DP ENABLE IN GPIO mode R5800 R53 @ R5839 @
    1K_0402_5% R5803 R5805
    23 HPD in I2C mode Unused in I2C mode

    2
    CTL1/HPDIN R5812
    2

    2
    AUX Snoop EN in GPIO mode AUX Snoop EN in GPIO mode @DCI_NC
    2

    29 DCI_DAT in I2C mode EN in I2C mode


    CAD_SNK/DCI_DAT

    HPD in GPIO mode


    32 DCI_CLK in I2C mode HPD
    DCI_CLK

    TUSB546 MUX default H/W setting


    Bring up summary LEVEL SETTINGS
    CTL1 CTL0 FLIP
    POL
    1. DCI Tools : Frequency HostConfig.xml file change to Clk133MHz = 2 Option 1:Tie 1K ohm 5% to GND EN
    (Pin 23)
    AMSEL
    (Pin 22) (Pin 21)
    TUSB456 Configuration VESA DisplayPot Alt Mode
    DFP_D Configuration
    0 Option 2:Tie directly to GND
    2. EC updated TUSB546 reg[0x0A] bit 4 for EQ controlled by I2C. L L L Power Down
    3. Pop DCI @ HW parts and Depop @ DCI_NC / PCH RC29 up to 4.7K ohm R Tie 20K ohm 5% to GND L
    L
    L
    H
    H
    L
    Power Down
    One Port USB 3.1 - No Flip
    4 4. For DCI BIOS F Float (leave pin open) L H H One Port USB 3.1 - With Flip 4
    H L L 4 Lane DP - No Flip C and E
    Option 1:Tie 1K ohm 5% to VCC H L H 4 Lane DP - With Flip C and E
    1 Option 2:Tie directly to VCC H H L One Port USB 3.1 + 2Lane DP -No Flip D and F
    H H H One Port USB 3.1 + 2Lane DP -With Flip D and F

    Device Configuration in GPIO Mode

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P31-DP MUX
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 31 of 61
    A B C D E
    A B C D E F G H

    Power Button +LED

    Vinafix.com
    1 1

    +5VALW

    1
    R288
    300_0402_5%

    2
    EC GPIO set to OD output

    PVT_0008
    LED6
    BREATH_LED# RE275 1 @ 2 0_0402_1% 1 2
    <38> BREATH_LED#
    PWR_LED# HT-F196BP5_WHITE

    PBTN_SW# SW3
    3 4
    <39> PBTN_SW#
    +5VALW

    1 2
    SKRBAAE010_4P
    B
    a
    t
    t
    e
    r
    y
    G
    a
    u
    g
    e
    L
    E
    D

    2
    +3VALW

    LED5

    LED4

    LED3

    LED2

    LED1
    2 2

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D

    27-11-T1D-CP1Q1RY-3C_WHITE~D
    PVT_0013

    1
    5
    QH1A

    G
    BATT_LED#_LV5 4 3 R67 1 2 820_0402_5%~D BAT_LED#_LV5
    <38> BATT_LED#_LV5

    D
    DMN66D0LDW-7_SOT363-6

    2
    BATT_LED#_LV4
    <38> BATT_LED#_LV4
    QH1B

    G
    1 6 R68 1 2 820_0402_5%~D BAT_LED#_LV4
    BATT_LED#_LV3

    D
    <38> BATT_LED#_LV3 DMN66D0LDW-7_SOT363-6

    5
    BATT_LED#_LV2 QH2A

    G
    <38> BATT_LED#_LV2 BAT_LED#_LV3
    4 3 R69 1 2 820_0402_5%~D

    D
    DMN66D0LDW-7_SOT363-6
    BATT_LED#_LV1
    <38> BATT_LED#_LV1
    2

    QH2B
    G

    1 6 R70 1 2 820_0402_5%~D BAT_LED#_LV2


    S

    DMN66D0LDW-7_SOT363-6
    2
    G

    3 1 R71 1 2 820_0402_5%~D BAT_LED#_LV1


    S

    +3VALW Q4
    L2N7002WT1G_SC-70-3

    2 1 BATT_LED#_LV5
    100K_0402_5% RE284
    3

    100K_0402_5%
    2

    2
    1

    1
    RE285
    BATT_LED#_LV4

    BATT_LED#_LV3
    NB LID SW 3

    100K_0402_5% RE283
    2 1 BATT_LED#_LV2
    100K_0402_5% RE286
    2 1 BATT_LED#_LV1 +3VALW
    100K_0402_5% RE287

    1
    +3VALW
    R274

    47K_0201_5%

    2
    NB_LID# <38>
    1
    C1077
    B
    a
    t
    t
    e
    r
    y
    G
    a
    u
    g
    e
    B
    u
    t
    t
    o
    n

    0.1U_0201_10V6K

    3
    2

    VCC

    VOUT
    GND
    TCS40DLR_SOT23F3
    U26
    SW2

    1
    <38> BATBTN# 2 4
    1
    BATBTN#
    C71
    0.1U_0402_10V7K
    2 1 3
    TBFD12KQR

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P32-Battery LED / LID
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 32 of 61
    A B C D E F G H
    5 4 3 2 1

    Css, Soft start setting


    +3VALW 1nF, rise time = 12uS +3VS_TP
    Touch Pad Load Switch 10nF, rise time = 100uS C1069
    100nF, rise time = 1000uS 1
    Touch Screen Load Switch
    EMC@
    60mil +3VALW
    +3VS_TS

    1U_0603_25V6K
    22P_0201_25V8J

    1
    C1070 2
    C1071 1 2 0.01UF_0402_25V7K PVT_0008
    60mil UZ1 1

    2
    +3VS_TP C76 2 1 1U_0402_6.3V6K~D 1 +3VS_TS

    Vinafix.com
    U10 R268 2 VIN1 R73 C74
    9 1 @ 2 VIN2 0_0603_5%
    VOUT 0.1U_0402_10V7K
    1 R269 +5VALW R5823 7 6 1 @ 2 2
    SS 1 VIN thermal VOUT
    8 1 2 0_0603_5% C1072 0_0402_1%
    TP_PW_EN 2 DIS 240_0402_1% 1 @ 2 3
    D <38> TP_PW_EN EN VBIAS D
    7 PVT_0008 0.1U_0402_25V6

    2
    3 PG 2 3.3V_TS_EN 4 5
    VIN1 <10> 3.3V_TS_EN ON GND
    R270 6 +3VALW
    4 VBIAS
    100K_0402_5%~D VIN2 5 +3VALW +3VALW TPS22961DNYR_WSON8
    GND R271

    1
    AP22850SH8-7_W-DFN2020-8 1 @ 2 R76 2 1 100K_0402_5%~D 3.3V_TS_EN
    1
    10K_0201_5% C1073

    0.1U_0201_10V6K
    2

    Deeper Sleep, SSD Load Switch 5V_Run, 5V_Audio Load Switch


    +3VALW +3V_PCH +3V_PCH +5VALW +5VS +5VS
    C80 R79 C81 R80
    1U_0402_6.3V6K~D U11 0_0603_5% 1U_0402_6.3V6K~D U12 0_0603_5%
    2 1 1 14 1 @ 2 1 2 1 1 14 1 @ 2 1
    2 VIN1 VOUT1 13 C83 2 VIN1 VOUT1 13 C84
    VIN1 VOUT1 1000P_0402_50V7K~D C82 VIN1 VOUT1 2200P_0402_25V7K~D C85
    PCH_PWR_EN 3 12 1 2 RUN_ON_P 3 12 1 2
    ON1 CT1 0.1U_0402_10V7K <34,36,52,55> RUN_ON_P ON1 CT1 0.1U_0402_10V7K
    2 2
    4 11 C87 4 11 C86
    SSD_PWR_EN VBIAS GND +5VALW VBIAS GND
    1 2 0_0402_5% 2200P_0402_25V7K~D 220P_0402_50V8K
    <13> SSD_PWR_EN AUD_PWR_EN
    @ R81 5 10 1 2 5 10 1 2
    RUN_ON_P 1 @ 2 0_0402_1% ON2 CT2 +3.3VDX_SSD +3.3VDX_SSD C89 ON2 CT2 +5VS_AUDIO +5VS_AUDIO
    R82 6 9 R83 1U_0402_6.3V6K~D 6 9 R84
    2 1 7 VIN2 VOUT2 8 0_0603_5% 2 1 7 VIN2 VOUT2 8 0_0603_5%
    C88 1U_0402_6.3V6K~D VIN2 VOUT2 1 @ 2 VIN2 VOUT2 1 @ 2
    1 1
    15 +3VS 15
    GPAD C90 GPAD C91
    R85 1 2 100K_0402_5%~D PCH_PWR_EN AOZ1331_DFN_14P R86 2 1 100K_0402_5%~D AUD_PWR_EN AOZ1331_DFN_14P
    0.1U_0402_10V7K 0.1U_0402_10V7K
    R87 1 2 100K_0402_5%~D SSD_PWR_EN 2 @ R88 1 2 100K_0402_5%~D RUN_ON_P 2
    @ R89 2 1 100K_0402_5%~D AUD_PWR_EN
    C @ R90 1 2 0_0402_5% PCH_PWR_EN C
    <38> PCH_ALW_ON
    R91 1 @ 2 0_0402_1%
    <12,36,38,53,54,60> SIO_SLP_SUS# +3.3VDX_SSD_IN+ <35>

    +3VS_NGFF_IN+ <35>
    WiFi, 3V_RUN Load Switch 3V_Audio, 1.8V_Audio Load Switch
    +3VALW +3VS_NGFF +3VS_NGFF +3VALW +3VS_AUDIO +3VS_AUDIO
    C92 R92 C93 R93
    1U_0402_6.3V6K~D U13 0_0603_5% 1U_0402_6.3V6K~D U14 0_0603_5%
    2 1 1 14 1 @ 2 1 2 1 1 14 1 @ 2 1
    2 VIN1 VOUT1 13 C94 2 VIN1 VOUT1 13 C97
    VIN1 VOUT1 2200P_0402_25V7K~D C95 VIN1 VOUT1 1000P_0402_50V7K~D C96
    AUX_EN_WOWL_R 3 12 1 2 AUD_PWR_EN 3 12 1 2
    ON1 CT1 0.1U_0402_10V7K <15> AUD_PWR_EN ON1 CT1 0.1U_0402_10V7K
    2 2
    4 11 C98 4 11 C99
    VBIAS GND 4700P_0402_25V7K VBIAS GND 4700P_0402_25V7K
    RUN_ON_P 5 10 1 2 AUD_PWR_EN 5 10 1 2
    C100 ON2 CT2 +3VS +3VS ON2 CT2 +1.8VS_AUDIO +1.8VS_AUDIO
    1U_0402_6.3V6K~D 6 9 R94 +1.8VA 6 9 R95
    2 1 7 VIN2 VOUT2 8 0_0603_5% C101 7 VIN2 VOUT2 8 0_0603_5%
    VIN2 VOUT2 1 @ 2 1U_0402_6.3V6K~D VIN2 VOUT2 1 @ 2
    1 1
    15 2 1 15
    GPAD C102 GPAD C103
    AOZ1331_DFN_14P 0.1U_0402_10V7K AOZ1331_DFN_14P 0.1U_0402_10V7K
    2 2

    +3VALW

    +LCDVDD +LCDVDD
    2

    +3VALW
    R5837 @ R97
    10K_0402_5% UZ2 0_0603_5% 1
    FROM EC GPIO035 5 1 1 @ 2
    B
    @ D13 IN OUT C104
    B
    1

    RE290 1 2
    <38> LCD_VCC_TEST_EN
    2 2 0.1U_0402_10V7K
    <38> SLP_WLAN#_GATE GND 2
    QE23 @ 0_0402_5%
    2

    1 ENVDD 4 3
    G

    FROM PCH GPD9/SLP_WLAN# @ D75 EN OC


    SIO_SLP_WLAN# 1 3 2 3 SY6288C20AAC_SOT23-5
    <12> SIO_SLP_WLAN# <7,38> ENVDD_PCH
    D

    1 AUX_EN_WOWL_R +LCDVDD_IN+ <35>


    FROM EC GPIO210/ADC08 L2N7002WT1G_SC-70-3 BAT54CW_SOT323-3
    3
    <38> AUX_EN_WOWL
    2

    BAT54CW_SOT323-3
    R96
    PVT_0006 1 2 100K_0402_5%~D R99 1 2 100K_0402_5%~D ENVDD
    RE291 0_0402_5%
    1

    Camera

    QZ1
    +3VS DMG2301U-7_SOT23-3 +3VS_CAM +3VS_CAM LCD Load Switch
    R98
    0_0603_5%
    +3VALW
    S

    3 1 1 @ 2 1

    1 C106 1
    G

    1U_0402_6.3V6K
    2

    C107 2 C105
    0.1U_0402_10V7K 1U_0402_6.3V6K~D
    A 2 2 A

    3.3V_CAM_EN#
    3.3V_CAM_EN# <12>

    +3VS

    @
    3.3V_CAM_EN# R100 1 2 100K_0402_5%
    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P33-DC/DC Interface 1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 33 of 61
    5 4 3 2 1
    A B C D E

    +1.0V_VCCST source +1.0V_VCCST


    +1.0V_VCCSTG source
    +1.0VA
    Vinafix.com +1.0VA

    0.1U_0402_10V7K
    1
    UZ3 PVT_0008
    1

    @ CZ1
    UZ4 PVT_0008
    1
    2 VIN1 R101 1 1
    VIN2 0_0603_5% 2 2 VIN1 R102
    7 6 1 @ 2 VIN2 0_0603_5%
    1 VIN thermal VOUT +1.0V_VCCST +5VALW
    1U_0402_6.3V6K

    7 6 1 @ 2 +1.0V_VCCSTG
    VIN thermal VOUT
    CZ2

    +5VALW 3
    VBIAS 3
    2 4 5 VBIAS
    <36> VCCST_EN ON GND 1

    1U_0402_6.3V6K

    0.1U_0402_10V7K
    1 4 5
    ON GND +1.0V_VCCSTG

    CZ3

    CZ4
    TPS22961DNYR_WSON8
    2 TPS22961DNYR_WSON8
    2

    0.1U_0402_10V7K
    BEAVER CREEK: 1
    4.4mohm/6A BEAVER CREEK:

    @ CZ5
    TR=12.5us@Vin=1.05V 4.4mohm/6A
    TR=12.5us@Vin=1.05V 2

    VCCSTG_EN

    +3VALW
    PVT_0002
    +VCCPLL_OC source

    5
    1

    P
    +VCCPLL_OC <12,27,60> SIO_SLP_S0# B VCCSTG_EN
    4 VCCSTG_EN <60>
    2 O
    <33,36,52,55> RUN_ON_P A

    G
    +1.2V_DDR UC4

    1
    TC7SH08FU_SSOP5~D

    0.1U_0402_10V7K
    2 1 2

    RZ1
    100K_0402_5%
    UZ5 PVT_0008

    CZ6
    1
    2 VIN1 R103
    VIN2 0_0603_5% 2

    2
    1 7 6 1 @ 2 +VCCPLL_OC
    VIN thermal VOUT
    1U_0402_6.3V6K
    CZ7

    3
    +5VALW VBIAS S0 S0Ix S3
    2 4 5
    ON GND
    PVT_0008 SIO_SLP_S0# high low low
    TPS22961DNYR_WSON8
    VCCSTG_EN RZ2 1 @ 2
    0_0402_1%
    RUN_ON_EC high high low

    +1.0V_MPHYGT source
    +1.0V_MPHYGT

    3 +1.0VA
    PVT_0008 3
    R104
    0.1U_0402_10V7K

    1
    0_0603_5%
    1 2
    @ CZ8

    @ +1.0V_MPHYGT
    2
    1U_0402_6.3V6K

    1
    CZ9

    2
    2 1
    MPHYP_PWR_EN <12>
    @ RH77 100K_0402_5%~D

    4 4

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P34-DC/DC Interface 2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 34 of 61
    A B C D E
    A B C D E

    Keyboard Controller board + DMIC +3VS_PWRM

    Power Monitor
    @
    MON_PDN# 1 2
    RE239 10K_0402_5%
    @
    MON_SLOW 1 2
    RE240 10K_0402_5%

    Vinafix.com PWRM_SCL
    RE232
    1
    @

    @
    2
    2.2K_0402_5%
    PWRM_SDA 1 2
    1 1
    RE233 2.2K_0402_5%

    +3V_PCH @ R282 +3VS_PWRM


    0_0603_5%
    JKB1 1 2
    1
    +5VALW 1
    2
    +3VALW
    +3VS
    3 2 Place close to JKB1
    4 3
    <13> KB_DET# 5 4 +3VALW +5VALW +3VS
    <38> BC_INT#_ECE1117 5
    <38> BC_DAT_ECE1117 6
    7 6
    <38> BC_CLK_ECE1117 7
    8 +3VS_PWRM
    White<38> BAT2_LED#
    9 8
    Amber<38> BAT1_LED#
    10 9 1 1 1
    <24> DMIC_DAT12_CODEC 11 10 C375 C376 C377
    <24> DMIC_CLK_CODEC 11 1 1
    12 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D @ @
    <24> DMIC_DAT34_CODEC 13 12 2 2 2 C1075 C1076
    @ U24
    14 13 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
    15 14 +INV_PWR_SRC A3 A4 2 2
    15 16 <37> +INV_PWR_SRC_IN+ IN1+ VDD
    GND 17 LCD_BL A2 B2
    GND IN1- VIO
    E-T_6710K-Y15M-31L
    CONN@ +LCDVDD A1
    <33> +LCDVDD_IN+ IN2+ C4 PWRM_SCL
    LCD LOGIC B1 SCL
    Use SP010027G00 IN2- PWRM_SDA
    D4
    SDA
    +3.3VDX_SSD D1
    <33> +3.3VDX_SSD_IN+ IN3+
    SSD C1 B3 MON_PDN#
    IN3- PDN#
    C3 MON_SLOW
    +3VS_NGFF D3 SLOW
    <33> +3VS_NGFF_IN+ IN4+ C2
    WLAN D2 ADDR
    2 2

    2
    IN4- B4
    GND RE234 @
    0_0402_5%
    MAX34407EWE+T_WLP16

    1
    @
    PWRM_SCL R5820 1 2 0_0201_5%
    PWR_MONITOR_I2CCLK <10>
    R283 1 @ 2 0_0201_5%
    PWR_MONITOR_SMBCLK <9>
    R285 1 @ 2 0_0201_5%
    PWR_MONITOR_EC_SMBCLK <38>
    PWRM_SDA R5821 1 @ 2 0_0201_5%
    PWR_MONITOR_I2CSDA <10>
    R284 1 @ 2 0_0201_5%
    PWR_MONITOR_SMBDAT <9>
    R286 1 @ 2 0_0201_5%
    PWR_MONITOR_EC_SMBDAT <38>

    SCREW Hole
    RTC Battery With Charge Function
    @ S3
    FD1 FD2 FD3 FD4 H22 H26
    @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
    H_1P8N H_1P8X2P3N
    @ @
    For PCB

    1
    Locating holes

    1
    3
    shielding 3

    +3VLP @ S1
    RTCD1 H13 H14 H18 H19 H20
    1 2 W=20mils
    H_2P0 H_2P0N H_2P0N H_1P8 H_1P8
    RB751V40_SC76-2 @ @ @ @ @
    Screw For AR

    1
    +RTCBATT
    shielding
    1

    JRTC1
    +RTCVCC 1 RTCR2
    2 1 @ S2
    2 200_0402_0.5% H11 H12 H21 H10
    1

    CLRP1 W=20mils
    2

    @ 3 +RTCVCC +RTCBATT H_2P0 H_2P0 H_2P0 H_2P6


    G1 RTCR1
    SHORT PADS 4 @ @ @ @
    Bracket Standoff For PCB
    2

    1
    G2 1 2 W=20mils
    ACES_50278-00201-001 1 for WLAN shielding
    CONN@ CH3 1.3K_0402_5%~D

    1U_0402_6.3V6K
    2 H16 H17 H23 H1 H2
    H25
    H_2P0 H_2P0 H_2P0 H_3P3 H_3P3
    @ @ @ @ @ H_1P2X1P7N
    Bracket Standoff
    1

    1
    @

    1
    for eDP

    H3 H4 H5 H6 H7 H24

    H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 CLIP_C6-PM


    @ @ @ @ @ @
    Standoff for Standoff
    1

    1
    CPU Cooller for SSD
    4 4

    H8 H9

    H_2P6 H_2P6
    @ @
    Standoff
    1

    for FAN
    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P35-SCREWH/KB/RTC/IR_T/PWRM
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 35 of 61
    A B C D E
    5 4 3 2 1

    +3VALW

    5
    U16 @
    1

    G VCC
    <12,38,39,41> SIO_SLP_S3# B 4 +3VALW

    Vinafix.com
    Y H_VCCST_PWRGD_P <12,15,38,39>
    2 PVT_0002
    <38> H_VCCST_PWRGD A

    5
    MC74VHC1G09DFT2G_SC70-5
    SIO_SLP_S3# 1

    P
    D B D
    4 RUN_ON_P <33,34,52,55>
    2 O
    <38,39> RUN_ON_EC A

    G
    UC5

    1
    2 1

    3
    @ RE4 0_0402_5%~D TC7SH08FU_SSOP5~D RE5
    100K_0402_5%

    2
    2 1
    @ RE6 0_0402_5%~D

    +3VALW

    5
    1

    P
    <12,33,38,53,54,60> SIO_SLP_SUS# B 4 VCCST_EN <34>
    2 O
    A

    G
    UC6

    1
    3
    TC7SH08FU_SSOP5~D RE7
    100K_0402_5%

    PVT_0002

    2
    +3VALW
    +3VALW PVT_0002
    PVT_0002

    5
    5

    SIO_SLP_S3# 1

    P
    1 B 4
    P

    <12,38> SIO_SLP_S4# B O IMVP_VR_ON_P <61>


    4 SUS_ON_P <52,54,55>
    2
    O <39,56> IMVP_VR_ON A

    G
    2 UC8
    <38> SUS_ON_EC A
    G

    1
    UC7

    3
    1

    C TC7SH08FU_SSOP5~D RE9 C
    3

    TC7SH08FU_SSOP5~D RE8 100K_0402_5%


    100K_0402_5%

    2
    2 1
    2

    2 1 @ RE10 0_0402_5%~D
    @ RE11 0_0402_5%~D

    Fingerprint CONN Touchpad CONN


    +3VS_TP

    +1.8VA Discharge
    PVT_0015
    PVT_0008
    R113 1 2 4.7K_0402_5%

    RH79 1 @ 2 0_0402_1% I2C1_SDA


    <10> I2C1_SDA_TP

    R114 1 2 4.7K_0402_5%

    RH80 1 @ 2 0_0402_1% I2C1_SCK


    <10> I2C1_SCK_TP

    PVT_0008 +3VS_TP
    JFP2
    RE274 1 @ 2 0_0402_1% FPR_GPIO_DET# 1
    <38> FPR_DET# 1 +3VS_TP
    1 2 0_0402_1% 2
    C121

    C122

    RE273 @ EMC@
    15P_0402_50V8J
    1U_0402_6.3V6K~D

    B <38> FPR_SCAN# 2 1 1 B
    3 +3VS_TP +1.8VA
    RE255 1 @ 2 FGND 4 3
    +3VS_FP USB20_P10_CONN 0_0402_1% 5 4
    5

    1
    USB20_N10_CONN 6 2 2
    7 6 R117 JTP1
    7

    1
    8 100K_0402_5%~D 1
    8 I2C1_SDA 2 1 R115
    9 I2C1_SCK 3 2 B+
    PVT_0013 80.6_0402_1%~D
    2
    FPR_GPIO_DET# 10 GND 4 3
    GND 5 4
    <15,38> TP_INTR#

    2
    5

    1
    ACES_50521-00841-P01 PTP_DIS# 6
    <38> PTP_DIS# 6
    3

    EMC@ DAT_TP_SIO 7 R116


    CONN@ <38> DAT_TP_SIO CLK_TP_SIO 7
    MD3 8 200K_0402_1%
    <38> CLK_TP_SIO 8

    3
    DMN66D0LDW-7_SOT363-6
    PESD5V0U2BT_SOT23-3
    9

    2
    GND1

    QE2B
    10
    +3VS GND2 5
    1

    2
    R281 +3VS_FP EMC@ EMC@ ACES_50506-00841-P01
    MD1 MD2 CONN@

    4
    6
    2.2U_0402_6.3V6M

    DMN66D0LDW-7_SOT363-6
    2 1 PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
    0.1U_0201_10V6K

    1
    C1079

    QE2A
    0438.500WR 0.5A 32V UL/CSA 1 SIO_SLP_SUS# 2
    C1080

    1
    2

    EXC24CH900U_4P DAT_TP_SIO
    4 3 USB20_N10_CONN
    <11> USB20_N10 CLK_TP_SIO

    USB20_P10_CONN
    680P_0402_50V7K~D

    EMC@

    680P_0402_50V7K~D

    EMC@
    1 2 1 1
    <11> USB20_P10
    C123

    C124
    A A
    ML1 EMC@
    TVNST52302AB0_SOT523-3

    D20
    3

    2 2

    EMC@
    DELL CONFIDENTIAL/PROPRIETARY
    1

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P36-TP/FP/PWERGD
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 36 of 61
    5 4 3 2 1
    5 4 3 2 1

    IR Digital CAM / eDP Backlight


    Css, Soft start setting
    Css, Soft start setting 1nF, rise time = 12uS B+_CAM
    1nF, rise time = 12uS +INV_PWR_SRC 10nF, rise time = 100uS
    10nF, rise time = 100uS B+ 100nF, rise time = 1000uS C1119 1
    B+ 100nF, rise time = 1000uS C1049 1 EMC@
    60mil
    60mil EMC@
    Vinafix.com +INV_PWR_SRC

    1U_0603_25V6K
    B+_CAM_F 22P_0201_25V8J

    1
    2
    1U_0603_25V6K
    22P_0201_25V8J C1120 +3VS_CAM
    1

    C1051 2 C1121 1 2 0.01UF_0402_25V7K B+_CAM


    C312 1 2 0.1U_0402_25V6K 60mil C1053 1 1 C1054
    60mil

    2
    D B+_CAM D
    R6 EMC@
    2

    10U_0402_6.3V6M

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    68P_0402_50V8J
    EMC@ C21
    R253 +INV_PWR_SRC U31 0_0603_5% 1 1 1

    10U_0603_25V6M

    0.1U 16V K X5R 0201


    U22 0_0603_5% 9 1 @ 2 C1068 1
    VOUT 2 2

    C18

    C19

    C20
    9 1 @ 2 1 R5824 1
    1 VOUT R251 SS 8 1 2 C1122
    1

    2
    SS DIS 2 2 2

    10U_0603_25V6M
    8 1 2 C1052 2 240_0402_1%
    DIS <11,38> B+_CAM_EN EN 2
    2 240_0402_1% 7 0.1U_0402_25V6
    <38> EN_INVPWR EN PG 2
    7 0.1U_0402_25V6 3
    3 PG 2 VIN1 6
    VIN1 6 4 VBIAS
    4 VBIAS VIN2 5
    VIN2 5 +INV_PWR_SRC_IN+ <35> GND +3VALW +3VALW
    GND +3VALW +3VALW AP22850SH8-7_W-DFN2020-8 R5825
    AP22850SH8-7_W-DFN2020-8 R252 B+ @ R5826 B+_CAM 1 @ 2 B+_CAM
    1
    1 @ 2 1 0_0603_5% 10K_0201_5% C1123
    10K_0201_5% C1050 1 2 JCAM1
    0.1U_0201_10V6K 1
    +3VALW 2 1
    +3VALW 0.1U_0201_10V6K CAM & IR CAM 2
    2 3 2
    +INV_PWR_SRC 3
    4
    5 4
    6 5
    LCD BL Power LCD_GPIO1 7 6
    LCD_GPIO2 8 7
    L1 EMC@ BL_PWMO 9 8
    1 2 USB20_P5_CONN DISPOFF# 10 9
    <11> USB20_P5 10
    11
    +3VS_CAM 11
    12
    USB20_N5_CONN <13> CAM_CBL_DET# USB20_P5_CONN 12

    AZ5B25-01F_DFN0603P2Y2

    AZ5B25-01F_DFN0603P2Y2
    4 3 CAM & IR CAM 13
    <11> USB20_N5 TVNST52302AB0_SOT523-3 USB20_N5_CONN 13
    14
    EXC24CH900U_4P D2 15 14
    3

    1
    D3 D4 16 15
    16

    AZ5B25-01F_DFN0603P2Y2
    D72 17
    18 17
    18

    EMC@
    19
    20 19
    EMC@ 21 20
    1

    EMC@ EMC@ 22 G1
    C C
    23 G2
    2

    2
    24 G3
    G4

    ACES_50406-02071-001
    CONN@

    eDP Conn +LCDVDD


    C1055 1 2 0.1U_0201_10V6K eDP_TXN_P0_C R14 1 @ 2 0_0201_5% eDP_TXN_P0_CONN JEDP1
    <7> eDP_TXN_P0
    <10> DBC_EN 40 45
    39 40 G5 44
    C1058 1 2 0.1U_0201_10V6K eDP_TXP_P0_C R15 1 @ 2 0_0201_5% eDP_TXP_P0_CONN C1067 1 C1065 1 C1066 1 C1018 1 +LCDVDD 38 39 G4 43
    <7> eDP_TXP_P0 <38> LCD_TST EDP_HPD_R 38 G3
    EMC@ EMC@ 37 42
    36 37 G2 41
    36 G1

    1
    eDP_TXN_P3_CONN

    0.1U_0201_10V6K

    10U_0603_6.3V6M

    22P_0402_50V8J

    100P_0201_50V8J
    @ RR21 35
    2 2 2 2 eDP_TXP_P3_CONN 34 35
    C1064 1 2 0.1U_0201_10V6K eDP_TXN_P1_C R256 1 @ 2 0_0201_5% eDP_TXN_P1_CONN 10K_0402_5% 33 34
    <7> eDP_TXN_P1 eDP_TXN_P2_CONN 33
    32
    eDP_TXP_P2_CONN 31 32

    2
    C1063 1 2 0.1U_0201_10V6K eDP_TXP_P1_C R259 1 @ 2 0_0201_5% eDP_TXP_P1_CONN 30 31
    <7> eDP_TXP_P1 eDP_TXN_P1_CONN 30
    RR22 RR23 29
    1 @ 2 1 @ 2 EDP_HPD_R eDP_TXP_P1_CONN 28 29
    <7> EDP_HPD 28
    27
    0_0402_1% 0_0402_1% eDP_TXN_P0_CONN 26 27
    C1056 1 2 0.1U_0201_10V6K eDP_TXN_P2_C R260 1 @ 2 0_0201_5% eDP_TXN_P2_CONN eDP_TXP_P0_CONN 25 26
    <7> eDP_TXN_P2 25
    24
    +3VS_TS eDP_AUXP_CONN 23 24
    C1061 1 2 0.1U_0201_10V6K eDP_TXP_P2_C R261 1 @ 2 0_0201_5% eDP_TXP_P2_CONN eDP_AUXN_CONN 22 23
    <7> eDP_TXP_P2 I2C0_SDA_TS
    PVT_0008 22
    RC183 1 2 4.7K_0402_5% 21
    RC184 1 2 4.7K_0402_5% I2C0_SCK_TS 20 21
    19 20
    +LCDVDD 19
    18
    B
    C1062 1 2 0.1U_0201_10V6K eDP_TXN_P3_C R262 1 @ 2 0_0201_5% eDP_TXN_P3_CONN 17 18 B
    <7> eDP_TXN_P3 +LCDVDD 17
    16
    RR20 1 @ 2 0_0201_5% 15 16
    eDP_TXP_P3_C eDP_TXP_P3_CONN I2C2_SDA_EDP_PCH <10> TS_I2C_RST# 15
    <7> eDP_TXP_P3 C1059 1 2 0.1U_0201_10V6K R255 1 @ 2 0_0201_5% RC372 1 2 4.7K_0402_5% 14
    RC373 1 2 4.7K_0402_5% I2C2_SCK_EDP_PCH I2C2_SDA_EDP_PCH @ RR18 0_0201_5% 1 2 13 14
    <10> I2C2_SDA_EDP_PCH I2C2_SCK_EDP_PCH 13
    <10> I2C2_SCK_EDP_PCH @ RR19 0_0201_5% 1 2 12
    11 12
    C1060 1 2 0.1U_0201_10V6K eDP_AUXN_C R257 1 @ 2 0_0201_5% eDP_AUXN_CONN INV_PWM_R 10 11
    <7> eDP_AUXN BL_PWMO 10
    9
    LCD_GPIO2 8 9
    C1057 1 2 0.1U_0201_10V6K eDP_AUXP_C R258 1 @ 2 0_0201_5% eDP_AUXP_CONN LCD_GPIO1 7 8
    <7> eDP_AUXP 7
    6
    5 6
    <15> TOUCH_SCREEN_PD# 5
    PVT_0008 4
    +3VS_TS EDP_3 4
    <10> I2C0_SDA_TS RR15 0_0402_1% 1 @ 2 3
    RR16 0_0402_1% 1 @ 2 EDP_2 2 3
    <10> I2C0_SCK_TS EDP_1 2
    RR17 0_0402_1% 1 @ 2 1
    <7> I2C2_IRQ_TS 1
    Use I2CI for General Touch Module EDP
    +3VS_TS PVT_0008 CONN@
    BackLight PWM Control

    1
    AZ5B25-01F_DFN0603P2Y2
    D18

    10U_0402_6.3V6M

    0.1U_0201_10V6K

    0.1U_0201_10V6K

    EMC@
    1 1 1

    C131

    C132

    C133
    D5
    <7> PANEL_BKLEN 2

    2
    2 2 2
    1 DISPOFF#
    1

    3
    <38> PANEL_BKEN_EC
    R13
    220K_0402_5%~D
    BAT54CW_SOT323-3
    2

    A A

    D6
    2
    <7> EDP_BIA_PWM
    1 INV_PWM_R
    2

    3
    <38> BIA_PWM_EC
    R16
    1
    DELL CONFIDENTIAL/PROPRIETARY
    @ MC1
    BAT54CW_SOT323-3
    4.7K_0402_5%
    2
    680P_0402_50V7K~D Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2041/09/08 Deciphered Date 2013/10/28 Title
    1

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P37-eDP+TS & CAM+BL CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 37 of 61
    5 4 3 2 1
    5 4 3 2 1

    +RTCVCC +3.3V_EC5105
    PVT_0008 UPD1_SMBDAT
    +RTC_CELL 1 2
    RE106 2 @ 1 +RTC_CELL_VBAT RE105 2.2K_0402_5%
    0_0402_1% UPD1_SMBCLK 1 2

    0.1U_0201_10V6K
    1 RE107 2.2K_0402_5%
    UPD1_ALERT#

    CE42
    1 2
    +3.3V_EC5105 RE252 2 @ 1 0_0402_1% RE108 100K_0402_5%
    UPD2_ALERT# 1 2
    2

    0.1U_0201_10V6K

    1U_0402_6.3V6K

    0.1U_0201_10V6K
    @ JP2 RE109 100K_0402_5%
    1 2 UPD3_ALERT# 1 2
    +3VALW 1 1

    1
    CE43

    CE44

    CE45
    RE231 100K_0402_5%

    10U_0603_6.3V6M
    PAD-OPEN1x1m

    2
    2 2

    CE46
    Vinafix.com

    2
    UE3 PBAT_CHARGER_SMBDAT 1 2
    F2 TYPE_ID RE111 2.2K_0402_5%
    GPIO033/RC_ID0 PANEL_ID TYPE_ID <39> PBAT_CHARGER_SMBCLK
    A2 J10 PANEL_ID <39>
    1 2
    +3.3V_EC5105 VBAT GPIO034/RC_ID1/SPI0_CLK J13 BOARD_ID RE112 2.2K_0402_5%
    D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT BOARD_ID <39> D
    B7 E7
    VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_SMBCLK UPD2_SMBDAT <44>
    +3.3V_EC5105
    2 1 D7 PD 2
    GPIO004/SMB00_CLK/SPI0_MOSI UPD2_SMBCLK <44>
    0.1U_0201_10V6K

    0.1U_0201_10V6K

    100_0402_1% RE113 K2
    VREF_ADC

    22U_0603_6.3V6M

    0.1U_0201_10V6K
    1 1 1 1 G3 RUNPWROK
    +3.3V_EC_PLL GPIO057/VCC_PWRGD SSD_SCP
    CE50

    CE51

    @ CE47
    F1 H5
    VTR_PLL GPIO060/KBRST/48MHZ_OUT SSD_SCP <30>

    CE48
    G11
    GPIO104/UART0_TX HOST_DEBUG_TX <39>
    H1 G12 RPE4
    2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FWP_EC <13> UPD3_SMBDAT
    B13 1 8
    GPIO127/A20M/UART0_CTS# UPD1_ALERT# ME_SUS_PWR_ACK <12> UPD3_SMBCLK
    G8 F10 2 7
    M9 VTR1 GPIO225/UART0_RTS# UPD1_ALERT# <43> UPD2_SMBCLK 3 6
    +VSS_PLL +3.3V_EC5105 VTR2 PCIE_WAKE#_R UPD2_SMBDAT
    close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 4 5
    VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <30,39,41>
    GPIO026/TIN1 SIO_SLP_S4# <12,36>
    +3.3V_EC5105
    F8 M11 2.2K_0804_8P4R_5%
    <39> PCH_DPWROK_EC RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <12>
    RF Request E8 H9 TP_PW_EN <33>
    <36,39> RUN_ON_EC GPIO045 GPIO030/TIN3
    0.1U_0201_10V6K

    1 M12
    +3VALW <10> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120
    C2 L9
    <28> BT_RADIO_DIS# PBAT_PRES# GPIO166 GPIO017/GPTP-IN5 BEEP <24>
    CE49

    F9 M10
    <49,50> PBAT_PRES# GPIO175 GPIO151/ICT4 DCIN1_EN <49>
    RE115 1 2 N4 N9
    2 <12,33,36,53,54,60> SIO_SLP_SUS# PCH_ALW_ON GPIO230 GPIO152/GPTP-OUT3 DCIN2_EN <49>
    43K_0402_1% M8
    <33> PCH_ALW_ON GPIO231 EC_I2C_DAT
    K8 C11 PWR_LED# 1 2
    <12> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <32>
    D10 @ RE242 2.2K_0402_5%
    GPIO157/LED1 BAT1_LED# <35> EC_I2C_CLK
    <9> SML1_SMBDAT
    E11 D11 1 2
    GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <35>
    Close to pin H1 D8 E1 @ RE243 2.2K_0402_5%
    <9> SML1_SMBCLK GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <33>
    12P_0402_50V8J
    RF@ CE52

    68P_0402_50V8J
    RF@ CE53

    1 1 M13
    <32> BATT_LED#_LV5 GPIO110/PS2_CLK2 FPR_SCAN#
    K12 E5
    <12> SUSACK# WLAN_WIGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 FPR_DET# FPR_SCAN# <36>
    <33> SLP_WLAN#_GATE B3 GPIO006 RE281 2 1 33_0201_1%
    <28> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 UPD3_SMBDAT FPR_DET# <36>
    K11 M7
    2 2 <12,15> SIO_PWRBTN# GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 UPD3_SMBCLK UPD3_SMBDAT <31,45>
    1 2 K10 M4 PD 3
    <12,15,36,39> H_VCCST_PWRGD_P LID_CL_SIO# GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT UPD3_SMBCLK <31,45> WLAN_WIGIG60GHZ_DIS#
    @ RE118 0_0402_5% RE237 2 @ 1 N11 M3 1 2
    <32> NB_LID# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <49,50>
    0_0402_1% E10 N2 CHARGER RE119 100K_0402_5%
    <36> CLK_TP_SIO GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <49,50>
    C12 N10
    <36> DAT_TP_SIO GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA PWR_MONITOR_EC_SMBDAT <35>
    A12 POWER MONITOR
    JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 EC_I2C_DAT PWR_MONITOR_EC_SMBCLK <35>
    <39> JTAG_TDI JTAG_TDO GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# EC_I2C_CLK EC_I2C_DAT <25>
    F6 F7
    <39> JTAG_TDO JTAG_CLK GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# UPD1_SMBDAT EC_I2C_CLK <25>
    C8 B4 THERMATRIP1# 1 2
    <39> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <43>
    C5 C3 PD 1 RE124 10K_0402_5%
    <39> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <43>
    G13
    JTAG_RST# J4 I_BATT_R RE125 1 2 300_0402_5%
    GPIO200/ADC00 I_SYS_R I_BATT <50> PCIE_WAKE#_R
    E3 J5 RE126 1 2 300_0402_5% 1 2
    +3VS_TP <30> FAN1_TACH GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 I_SYS <50,56>
    D1 J6 RE127 10K_0402_5%
    <30> FAN2_TACH LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 PTP_INT#_EC H_VCCST_PWRGD <36>
    M2 G2 RE251 1 @ 2 0_0402_1%
    CLK_TP_SIO <37> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 TP_INTR# <15,36>
    RE235 1 2 4.7K_0402_5%~D
    <30> FAN1_PWM
    L10 H2
    C DAT_TP_SIO GPIO053/PWM0/GPWM0 GPIO204/ADC04 UPD3_ALERT# <45> BC_DAT_ECE1117 C
    RE236 1 2 4.7K_0402_5%~D
    <30> FAN2_PWM
    L11 J2
    PRODUCT_ID_EC <39>
    1 2
    SHD_CS# M5 GPIO054/PWM1/GPWM1 GPIO205/ADC05 J3 GPIO206 RE130 100K_0402_5%
    SHD_CLK GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 PAD~D @ T62
    J8 K3
    T57 @ PAD~D GPIO056/PWM3/SHD_CLK GPIO207/ADC07 DCIN3_EN <49>
    <37> BIA_PWM_EC N1 D3
    TBT_RESET_N_EC_R GPIO001/PWM4 GPIO210/ADC08 AUX_EN_WOWL <33> BT_RADIO_DIS#
    RE132 1 @ 2 L8 D2 1 2
    <41> TBT_RESET_N_EC ACAV_IN_NB GPIO002/PWM5 GPIO211/ADC09 SUS_ON_EC <36>
    ESPI only support 1.8V 0_0402_1% T52 @ PAD~D
    N6 E2 RE133 100K_0402_5%
    J9 GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 G5 HRESET_PD3_EC BC_INT#_ECE1117 <35>
    <37> PANEL_BKEN_EC GPIO015/PWM7 GPIO213/ADC11 UPD2_ALERT# HRESET_PD3_EC <45>
    H11 F5
    T124 @ PAD~D GPIO035/PWM8/CTOUT1 GPIO214/ADC12 HRESET_PD1_EC UPD2_ALERT# <44>
    JP3 <32> SIO_SLP_WLAN# D9 K4 HRESET_PD1_EC <43>
    1 2 H12 GPIO133/PWM9 GPIO215/ADC13 L1 PCH_PCIE_WAKE#
    +1.8VA +1.8V_3.3V_ALW_VTR3 <32> BATT_LED#_LV3
    G10 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 L3
    PCH_PCIE_WAKE# <12,39> +RTCVCC
    1 <32> BATT_LED#_LV2 GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <12>
    @ PAD-OPEN1x1m MSCLK H10
    <39> MSCLK GPIO170/TFDP_CLK/UART1_TX
    CE54 MSDATA G9 H8 BATBTN# 1 2
    <39> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ PAD~D @ T69
    0.1U_0201_10V6K 1 CE55 J7 BATT_LED#_LV4 <32> RE137 100K_0402_5%
    2 0.1U_0201_10V6K A4 GPIO223/SHD_IO0 L6 HRESET_PD2_EC VCI_IN2# 1 2
    <24> NB_MUTE# EN_INVPWR GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 SHD_IO2 HRESET_PD2_EC <44>
    B2 L7 RE142 100K_0402_5%
    <37> EN_INVPWR PRIM_PWRGD_GPIO024 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 SHD_IO3 VCI_IN3#
    C1 M6 1 2
    2 IMVP_VR_ON_EC GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 PAD~D @ T56
    Close to pin N5 N7 RE244 100K_0402_5%
    <39> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6
    <12,36,39,41> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 PAD~D @ T58 +PECI_VREF
    N8 C7 2 @ 1
    <12> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <50> +1.0V_VCCST
    A5 RE147 0_0402_1%
    VCI_OUT ALWON <51> +3.3V_EC5105

    0.1U_0201_10V6K
    F13 D5
    <49> VBUS1_ECOK GPIO121/PVT_IO0 GPIO163/VCI_IN0# POWER_SW_IN# <39>
    E13 B5 BATBTN# RE147 close to UE3 at least 250mils
    <49> AC_DISC# BATBTN# <32>

    1
    GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2#

    CE56
    C13 D4
    RPE6 <49> VBUS2_ECOK E12 GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# E4 VCI_IN3# FPR_DET# 1 2
    8 1 <49> VBUS3_ECOK GPIO126/PVT_IO3 GPIO000/VCI_IN3# RE280 10K_0402_5%

    2
    7 2 IMVP_VR_ON_EC RTCRST_ON F11
    6 3 PCH_ALW_ON F12 GPIO122/BCM0_DAT/PVT_IO1 C6 AC_DIS FPR_SCAN# 1 2
    RUN_ON_EC <32> BATT_LED#_LV1 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 AC_DIS <50>
    5 4 D12 RE272 10K_0402_5%
    <35> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
    D13 F3 CE57 1 2 10P_0402_50V8J
    <35> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT FPR_SCAN#
    100K_0804_8P4R_5% 1 2
    @ F4 @ RE254 100K_0402_5%
    <36> PTP_DIS# GPIO041/SYS_SHDN# +PECI_VREF
    RE152 2 1 1K_0402_5% B1 J11
    +3VLP SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
    <11,37> B+_CAM_EN RE261 1 @ 2 0_0402_1% K7 K13 RE153 1 2 43_0402_5%
    PECI_EC <15>
    1

    N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 GPIO043 @ T68


    GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N 2PAD~D REM_DIODE1_N
    100K_0402_5%

    K6 A8 CE58 1 2200P_0402_50V7K
    <9> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_P REM_DIODE1_N <39>
    RE154

    H7 A7
    <9> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE2_N REM_DIODE1_P <39> I_BATT_R
    K1 A10 CE59 1 2 2200P_0402_50V7K CE60 1 2 2200P_0402_50V7K
    <39> PCH_PLTRST#_5105 ESPI_CLK_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_P REM_DIODE2_N <39>
    G7 A9
    REM_DIODE2_P <39>
    2

    <9,39> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE3_N CE90 1 2 2200P_0402_50V7K I_SYS_R CE61 1 2 2200P_0402_50V7K
    <9,39> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8 REM_DIODE3_P REM_DIODE3_N
    <9,39> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N REM_DIODE3_P REM_DIODE3_N <39>
    B L4 A11 CE62 1 2 2200P_0402_50V7K B
    <9,39> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE3_P <39>
    +3VALW G6 B10
    <9,39> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP
    L5 C10
    100K_0402_5%

    <9,39> ESPI_IO3 GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 REM_DIODE4_N PCH_RSMRST#


    L2 C9 VSET_5105 <39>
    1 2
    REM_DIODE4_N <39>
    2

    M1 GPIO067/CLKRUN# VSET B11 REM_DIODE4_P RE155 10K_0402_5%


    I_ADP <50> REM_DIODE4_P <39>
    RE156

    SYS_PWROK G4 GPIO100/nEC_SCI VCP H3 THERMATRIP2# SYS_PWROK 1 2

    VSS_ANALOG
    <12,15> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# THERMATRIP2# <39>
    L12 B12 THERMATRIP1# @ RE157 10K_0402_5%
    <7,33> ENVDD_PCH GPIO107/nSMI THERMTRIP1# H_PROCHOT#_R1 I_SYS_R
    VSS_ADC
    H13 RE158 1 2 100_0402_1% 1 2

    VSS_PLL
    VR_CAP
    MEC_XTAL1 GPIO160/PWM11/PROCHOT# H_PROCHOT# <15,50,56>

    @
    A1 RE159 10K_0402_5%
    1

    MEC_XTAL2_R A3 XTAL1 LCD_TST 1 2


    VSS1

    VSS2

    VSS3

    XTAL2 RE160 100K_0402_5%


    JTAG_RST# EN_INVPWR 1 2
    MEC5105_WFBGA169_11X11 RE161 100K_0402_5%
    A6

    A13

    E6

    H4

    1+VR_CAP J1

    C4

    G1
    1U_0402_6.3V6K

    TBT_RESET_N_EC_R 1 2
    Use SA00009GL30(MEC5105K-D2-TN-TR WFBGA 169P)
    1

    1U_0402_6.3V6K

    RE162 100K_0402_5%
    1
    100_0402_1%

    +VSS_PLL
    1

    B+_CAM_EN
    @SHORT PADS~D
    JTAG2 CONN@

    @ RE164

    1 2
    CE63

    RE260 100K_0402_5%
    2

    CE64
    2
    2

    RE253 1 2 100K_0402_5%
    +3V_PCH
    2

    SHD_IO2 RE245 1 @ 2 0_0402_1%


    1.8VA_PWROK <54> +3VS
    1.8V_PRIM_PWRGD For EMI request SUS_ON_EC 1 2
    2

    +3VALW ESPI_CLK_5105
    10K_0402_5% DMN65D8LDW-7_SOT363-6

    RE282 100K_0402_5%
    PRIM_PWRGD_GPIO024 RE247 1 2 100K_0402_5%
    +3VALW
    RE168

    PVT_0013 RE171

    33_0402_5%
    1
    1 2

    EMC@
    GPIO024 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI) 75_0402_5% PCH_RTCRST# <12>
    PVT_0014
    100K_0402_5%

    RE172
    1
    2

    1
    RUNPWROK D
    RTCRST_ON 2 QE10
    RE174

    MEC_XTAL2_R G L2N7002WT1G_SC-70-3

    2
    1
    S

    3
    6

    SHD_CS#

    33P_0402_50V8J
    RE177 1 @ 2 0_0402_1% RE176 +3.3V_EC5105
    1

    PCH_RSMRST# <12,15>
    QE11A

    EMC@
    1

    1
    GPIO055 use for SHD_CS# (LPC) or PCH_RSMRST#(eSPI) 100K_0201_5%
    RUN_ON# 2 SSD_SCP

    CE65
    RE178 1 2
    32 KHz Clock
    2

    A @ 0_0402_1% RE289 10K_0402_5% A

    2
    DMN65D8LDW-7_SOT363-6

    @
    1

    SSD_SCP 1 2
    2

    RE288 100K_0402_5%
    YE2
    QE11B

    MEC_XTAL1 1 2 MEC_XTAL2
    5
    <39> RUN_ON
    32.768KHZ_9PF_X1A000141000200
    4
    1

    CE66 CE67
    12P_0402_50V8J 12P_0402_50V8J DELL CONFIDENTIAL/PROPRIETARY
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P38-MEC5105 ESPI EC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 38 of 61
    5 4 3 2 1
    5 4 3 2 1

    PCIE_WAKE# <28>
    PVT_0008

    RE185
    +RTCVCC 2 @ 1 1 2
    +1.8V_3.3V_ALW_VTR3 <30,38,41> PCIE_WAKE#_R PCH_PCIE_WAKE# <12,38>
    0_0402_5% @ RE186
    0_0402_1%

    1
    +3VALW

    100K_0402_5%
    2

    RE184
    UE5 Stuff RE185 and no stuff RE186 keep E5 design
    RE183 Stuff RE186 and no stuff RE185 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
    1 5 10K_0402_5%
    NC VCC

    2
    2

    1
    <12,27,28,29,30,41> PCH_PLTRST#_EC A 4 RE187 1 2 1K_0402_5% 2 1
    3 Y PCH_PLTRST#_5105 <38> <38> POWER_SW_IN# PBTN_SW# <32>
    0_0402_5% @ RE188

    Vinafix.com
    GND
    1
    74AUP1G07SE-7 SOT353

    1U_0402_6.3V6K
    1
    CE69 +3VALW

    CE68
    Use SA00007WE00 2.2U_0402_6.3V6M @ CE70
    2 1 2

    2
    UE7 +3VALW

    @
    D 0.1U_0402_25V6K D

    5
    1 5
    IMVP_VR_ON_EC 1 NC VCC

    P
    <38> IMVP_VR_ON_EC B IMVP_VR_ON
    4 2
    SIO_SLP_S3# 2 O A 4
    <12,36,38,39,41> SIO_SLP_S3# A Y H_VCCST_PWRGD_P <12,15,36,38>

    G
    UE6 3
    TC7SH08FU_SSOP5~D GND

    3
    74AUP1G07SE-7 SOT353
    Use SA00007WE00
    LPC 80Port RF Request
    Debug LPC ESPI IMVP_VR_ON <36,56>
    +3VALW
    PVT_0002
    1 2
    1 +3VS +3VS 0_0402_5% @ RE191
    JESPI1 +3VS
    2 +3VS +3VS

    68P_0402_50V8J
    1
    1
    1 RUN_ON_EC

    RF@ CE72
    3 LPC_LAD0 ESPI_IO0 2 2 1
    2 <36,38> RUN_ON_EC RUN_ON <38>
    3 ESPI_IO0 <9,38> 0_0402_5% @ RE192
    4 LPC_LAD1 ESPI_IO1 3 4 2
    4 ESPI_IO1 <9,38>
    5 ESPI_IO2 <9,38>
    5 LPC_LAD2 ESPI_IO2 5 6 +3VALW
    6 7 ESPI_IO3 <9,38> @ CE73
    7 8 20_0402_5% PCH_PLTRST#_EC ESPI_CS# <9,38>
    6 LPC_LAD3 ESPI_IO3 @ RE193 1 1 2
    8 9
    7 LPC_FRAME# ESPI_CS# 9 10 0.1U_0402_25V6K
    10 ESPI_CLK_5105 <9,38>

    5
    8 PCH_PLTRST# NA 11 1

    P
    GND1 12 B 4
    9 GND GND GND2 2 O
    A

    G
    JXT_FP225H-010G1AM UE8
    10 LPC_CLK ESPI_CLK
    @CONN@ TC7SH08FU_SSOP5~D

    3
    PVT_0002
    +3VALW +3VALW
    +3VALW +3VALW
    PVT_0001

    1
    RE194 RE195

    2
    8.2K_0402_5% 4.3K_0402_5%

    2
    U22@
    100K_0402_5% RE196

    2
    RE249 240K_0402_5% BOARD_ID PANEL_ID
    <38> BOARD_ID <38> PANEL_ID
    XPS@

    1
    1
    PRODUCT_ID_EC
    CE75 CE76
    <38> PRODUCT_ID_EC
    4700P_0402_25V7K 4700P_0402_25V7K

    2
    TYPE_ID
    <38> TYPE_ID

    2
    C C

    100K_0402_5% RE196 U23@ RE196 U42@ RE194 CE75 REV RE195 CE76 PANEL SIZE

    1
    RE250
    L@ CE78
    240K 4700p X00 240K 4700p

    1
    4700P_0402_25V7K

    2
    130K 4700p X01 130K 4700p
    SD034130380 SD028620280
    130K_0402_1% 62K_0402_5% 62K 4700p X02 33K 4700p
    33K 4700p X03 * 4.3K 4700p Italia 13
    RE249 RE250 REV RE196 CE78 REV 8.2K 4700p A00 PVT_0001
    *
    @ Italia XPS 240K 4700p U2+2 4.3K 4700p
    *
    @ Italia-L 130K 4700p U2+3e 2K 4700p
    PVT_0008 U4+2
    62K 4700p 1K 4700p PANEL_ID rise t i mei s meas ur ed fr o m5 %~68 %.
    PCH_DPWROK_EC PCH_DPWROK_R
    33K 4700p
    RE248 1 @ 2
    <38> PCH_DPWROK_EC
    0_0402_1%
    PCH_DPWROK_R <12>
    8.2K 4700p BOARD_ID rise t i mei s meas ur ed fr o m5 %~68 %.
    4.3K 4700p VSET_5105
    2K 4700p VSET_5105 <38>

    0.1U_0402_25V6
    1K 4700p

    1
    1.58K_0402_1%
    1

    CE79

    RE199
    2

    2
    Rest=1.58K , Tp=96 degree

    +3VALW

    PVT_0008
    1

    8
    7
    6
    5
    10K_8P4R_5%

    RE200
    RPE7

    0_0402_1% @

    1
    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    100K_0402_5%
    B B

    @ RE204
    2

    1
    2
    3
    4

    RE201

    RE202

    RE203
    JDEG1 DP1/DN1 for CPU
    1 +EC_DEBUG_VCC
    1 2 JTAG_TDI Place CE83 close to the QE12 as possible
    JTAG_TDI <38> Thermal diode mapping

    2
    2 3 JTAG_TMS
    3 4 JTAG_CLK JTAG_TMS <38> REM_DIODE1_P <38>

    LMBT3904WT1G SC70-3
    4 JTAG_TDO JTAG_CLK <38>
    5
    5
    JTAG_TDO <38>
    RE205 5105 Channel Locat i on

    3
    100P_0402_50V8J

    100P_0402_50V8J
    QE20
    6 MSCLK 10K_0402_5%
    E
    6

    1
    @ CE93
    7 MSDATA 1 2 B
    2 C
    7 HOST_DEBUG_TX

    @ CE83
    8
    8
    9 DEBUG_TX DP1/DN1 OTP (QE12) C B
    2

    1
    9 10 E QE12

    3
    10
    11 <10> SBIOS_TX
    1
    @ RE206
    2 SEN4 DN1a/DP1a Charger (QE20) LMBT3904WT1G SC70-3
    GND1 12 REM_DIODE1_N <38>
    0_0402_5%
    GND2
    JXT_FP225H-010G1AM
    HOST_DEBUG_TX <38> SEN1 DP2/DN2 DDR (QE14) DN1a/DP1a for VR
    CONN@
    MSDATA <38> Place QE20 close to chock & CE93 close to the QE20
    MSCLK <38>
    1 @ 2 SEN5 DN2a/DP2a SKIN (QE21)
    RE209
    0_0402_1% SEN6 DP3/DN3 SKIN (QE22) DP2/DN2 for DDR on QE14, place QE14 close
    PVT_0008 to DDR and CE87 close to QE14
    SEN2 DN3a/DP3a SSD (QE15) REM_DIODE2_P <38>

    LMBT3904WT1G SC70-3
    3

    1
    100P_0402_50V8J

    100P_0402_50V8J
    SEN3

    QE21
    E C
    DP4/DN4 WLAN (QE19)

    1
    @ CE94

    @ CE87
    B
    2 2
    B
    DN4a/DP4a C E QE14

    3
    LMBT3904WT1G SC70-3

    REM_DIODE2_N <38>

    DN2a/DP2a for SKIN.


    Place CE94 close to QE21

    DP4/DN4 for WLAN on QE19, place QE19 close to DP3/DN3 for SSD
    WLAN & QE19 close to CE89. Place CE91 close to the QE15 as possible

    LMBT3904WT1G SC70-3
    RE215 8.2K_0402_5%
    0.1U_0402_25V6

    1 2
    +1.0VS_VCCIO +3VALW THERMATRIP2# <38> REM_DIODE4_P <38> REM_DIODE3_P <38>

    SIO_SLP_S3# <12,36,38,39,41>
    1

    1
    LMBT3904WT1G SC70-3

    CE86

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J
    @ QE13 C
    E
    2

    1
    @ CE91

    @ CE95
    C B
    2 2
    G

    2
    @CE89
    C 2 B
    2

    QE15
    QE16

    1 3 1 2 2 B C E QE22

    3
    A RE219 2.2K_0402_5% B E QE19 LMBT3904WT1G SC70-3 A
    D

    3
    +1.0V_VCCST E LMBT3904WT1G SC70-3
    3

    L2N7002WT1G_SC-70-3
    REM_DIODE4_N <38> REM_DIODE3_N <38>
    1 @ 2
    <15> H_THERMTRIP# DN3a/DP3a for TBD.
    RE222 Place CE95 close to QE22
    0_0402_1%

    PVT_0008

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P39-MEC5105 Support
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 39 of 61
    5 4 3 2 1
    A B C D E F G H

    Reference [ BAX02-PWR Sequence_KBL-U22_DDR4_Volume_S0iX ]

    G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5


    +3VL_RTC +3VL_RTC
    tPCH01_Min : 9 ms
    SOC_RTCRST# SOC_RTCRST#

    1
    +19VB

    +3VLP/+5VLP
    Vinafix.com +19VB

    +3VLP/+5VLP 1

    EC_ON EC_ON
    tPCH04_Min : 9 ms
    +5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
    Pull-up to DSW well if not implemented.
    PM_BATLOW# PM_BATLOW#

    PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

    +3V_PRIM +3V_PRIM

    +1.8V_PRIM +1.8V_PRIM

    EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#


    gate may choose to completely ignore it

    +1.0V_MPHYPLL +1.0V_MPHYPLL

    +1.0V_PRIM_CORE +1.0V_PRIM_CORE
    tPCH34_Max : 20 ms
    +1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM

    SUSACK# SUSACK#
    tPCH02_Min : 10 ms
    PCH_DPWROK PCH_DPWROK
    tPCH03_Min : 10 ms
    EC_RSMRST# EC_RSMRST#
    tPLT02_Min : 0 ms Max : 90 ms
    2 2
    AC_PRESENT AC_PRESENT

    ON/OFF ON/OFF

    PBTN_OUT# PBTN_OUT#
    Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

    PM_SLP_S5# PM_SLP_S5#
    tPCH18_Min : 90 us
    ESPI_RST# ESPI_RST#

    PM_SLP_S4# PM_SLP_S4#

    SYSON SYSON

    +1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR

    +1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC

    PM_SLP_S3# PM_SLP_S3#

    SUSP# SUSP#
    tCPU04 Min : 100 ns
    +1.0VS_VCCSTG +1.0VS_VCCSTG
    tCPU10 Min : 1 ms
    3
    +1.0VS_VCCIO +1.0VS_VCCIO 3

    +5VS/+3VS/+1.5VS/+1.05VS
    +5VS/+3VS/+1.5VS/+1.05VS
    T4 = Min : 20ms Max : 30ms(EC Control)
    EC_VCCST_PG EC_VCCST_PG

    VR_ON VR_ON
    tCPU19 Max : 100 ns
    SM_PG_CTRL SM_PG_CTRL
    tCPU18 Max : 35 us
    +0.675VS_VTT +0.675VS_VTT
    tCPU09 Min : 1 ms
    +VCC_SA +VCC_SA

    +VCC_CORE +VCC_CORE

    +VCC_GT +VCC_GT

    VR_PWRGD VR_PWRGD
    tCPU16 Min : 0 ns
    PCH_PWROK PCH_PWROK

    H_CPUPWRGD H_CPUPWRGD

    SYS_PWROK SYS_PWROK
    4 4

    SUS_STAT# SUS_STAT#

    SOC_PLTRST#
    SOC_PLTRST#

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2013/07/04 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P40-Power Sequence
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 40 of 61
    A B C D E F G H
    5 4 3 2 1

    @ UT2A
    +3VA_TBT_LC
    <11> PCIE_PTX_TBRX_P5 CT1 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P5_C Y23 V23 PCIE_PRX_TBTX_P5_C CT2 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_P5 <11>
    VCC3V3_LC
    <11> PCIE_PTX_TBRX_N5 CT3 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N5_C Y22 PCIE_RX0_P PCIE_TX0_P V22 PCIE_PRX_TBTX_N5_C CT4 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_N5 <11>
    PCIE_RX0_N PCIE_TX0_N

    CPU PCIE RX
    1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P6_C T23 PCIE_PRX_TBTX_P6_C

    CPU PCIE TX
    <11> PCIE_PTX_TBRX_P6 CT5 2 P23 CT19 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_P6 <11>
    CT20 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N6_C T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_TBTX_N6_C CT21 2 1 0.22U_0201_6.3V6M
    <11> PCIE_PTX_TBRX_N6 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_TBTX_N6 <11>
    1

    1
    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%
    CT22 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P7_C M23 K23 PCIE_PRX_TBTX_P7_C CT6 2 1 0.22U_0201_6.3V6M
    <11> PCIE_PTX_TBRX_P7 PCIE_PRX_TBTX_P7 <11>
    CT7 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N7_C M22 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_TBTX_N7_C CT8 2 1 0.22U_0201_6.3V6M

    PCIe GEN3
    <11> PCIE_PTX_TBRX_N7 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_TBTX_N7 <11>
    RT6

    RT5

    RT4

    RT3
    <11> PCIE_PTX_TBRX_P8 CT9 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_P8_C H23 F23 PCIE_PRX_TBTX_P8_C CT10 2 1 0.22U_0201_6.3V6M PCIE_PRX_TBTX_P8 <11>
    2

    2
    CT11 2 1 0.22U_0201_6.3V6M PCIE_PTX_TBRX_N8_C H22 PCIE_RX3_P PCIE_TX3_P F22 PCIE_PRX_TBTX_N8_C CT12 2 1 0.22U_0201_6.3V6M
    TBT_JTAG_TDI <11> PCIE_PTX_TBRX_N8 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_TBTX_N8 <11>
    TBT_JTAG_TMS PVT_0008 TBT_PERST_N R164 2
    V19 L4 1 0_0402_5%
    TBT_JTAG_TCK <12> CLK0_PCIE_TBT PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_EC <12,27,28,29,30,39>
    <12> CLK0_PCIE_TBT#
    T19 RT428 2 @ 1 0_0402_5% PCH_TBT_PERST# <10>
    TBT_JTAG_TDO RT71 2 @ 1 0_0201_5% CLKREQ_PCIE#0_N AC5 PCIE_REFCLK_100_IN_N N16 PCIe_RBIAS RT7 2 1 3.01K_0402_1%
    <12> CLKREQ_PCIE#0 PCIE_CLKREQ_N PCIE_RBIAS PVT_0011
    1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P0_C

    Vinafix.com
    <7> DDI1_PTX_TBRX_P0 CT13 2 AB7 R2 TBT_DP_ML0_P <31> PVT_0011
    <7> DDI1_PTX_TBRX_N0 CT14 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N0_C AC7 DPSNK0_ML0_P DPSRC_ML0_P R1 TBT_DP_ML0_N <31>
    DPSNK0_ML0_N DPSRC_ML0_N +3VA_TBT
    <7> DDI1_PTX_TBRX_P1 CT23 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P1_C AB9 N2 TBT_DP_ML1_P <31>
    <7> DDI1_PTX_TBRX_N1 CT15 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N1_C AC9 DPSNK0_ML1_P DPSRC_ML1_P N1 TBT_DP_ML1_N <31>
    TBT_TMU_CLK_OUT
    DPSNK0_ML1_N DPSRC_ML1_N PCIE_WAKE#_AR @ RT430 2 1 10K_0201_1%

    SOURCE PORT 0
    1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P2_C

    CPU DDI1

    100P_0201_50V8J
    D
    <7> DDI1_PTX_TBRX_P2 CT16 2 AB11 L2 TBT_DP_ML2_P <31> 1
    D
    1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N2_C DPSNK0_ML2_P DPSRC_ML2_P PCH_PCIE_WAKE#

    SINK PORT 0
    <7> DDI1_PTX_TBRX_N2 CT24 2 AC11 L1
    TBT_DP_ML2_N <31> @ RT429 2 1 10K_0201_1%
    DPSNK0_ML2_N DPSRC_ML2_N

    C1083
    CT17 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_P3_C AB13 J2
    <7> DDI1_PTX_TBRX_P3 TBT_DP_ML3_P <31>
    <7> DDI1_PTX_TBRX_N3 CT18 2 1 0.1U_0201_6.3V6K DDI1_PTX_TBRX_N3_C AC13 DPSNK0_ML3_P DPSRC_ML3_P J1 TBT_DP_ML3_N <31>
    2
    DPSNK0_ML3_N DPSRC_ML3_N
    CT25 2 1 0.1U_0201_6.3V6K CPU_DDI1_AUXP_C Y11 W19
    <7> CPU_DDI1_AUXP TBT_DP_AUX_P <31,45>
    CT26 2 1 0.1U_0201_6.3V6K CPU_DDI1_AUXN_C W11 DPSNK0_AUX_P DPSRC_AUX_P Y19 TBT_DP_AUX_N <31,45>
    <7> CPU_DDI1_AUXN DPSNK0_AUX_N DPSRC_AUX_N
    CPU_DP1_HPD AA2 G1 TBT_SRC_HPD RT8 1 @ 2 0_0201_5%
    <7> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD TBT_DP_HPD <31,45>
    CPU_DP1_CTRL_CLK PVT_0011
    @ RT91 2 1 0_0201_5% TBT_SNK0_DDC_CLK Y5 N6 DPSRC_RBIAS RT9 2 1 14K_0402_1%
    <7> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA @ RT92 2 1 0_0201_5% TBT_SNK0_DDC_DATA R4 DPSNK0_DDC_CLK DPSRC_RBIAS
    <7> CPU_DP1_CTRL_DATA TBT_I2C_DATA PCIE_WAKE#_AR
    DPSNK0_DDC_DATA U1 RT431 2 1 0_0402_5% PCIE_WAKE#_R
    TBT_I2C_DATA <43,44> PCIE_WAKE#_R <30,38,39>
    <7> DDI2_PTX_TBRX_P0 CT27 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P0_C AB15 GPIO_0 U2 TBT_I2C_CLK
    TBT_I2C_CLK <43,44>
    <7> DDI2_PTX_TBRX_N0 CT28 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_ROM_WP# @ RT432 2 1 0_0402_5% PCH_PCIE_WAKE# PCH_PCIE_WAKE# <12,38,39>
    DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT
    PVT_0011
    <7> DDI2_PTX_TBRX_P1 CT29 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P1_C AB17 GPIO_3 W1 PCIE_WAKE#_AR @ RT433 2 1 0_0402_5% CLKREQ_PCIE#4 CLKREQ_PCIE#4 <12>
    <7> DDI2_PTX_TBRX_N1 CT30 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N1_C AC17 DPSNK1_ML1_P GPIO_4 W2 TBT_CIO_PLUG_EVENT#
    TBT_CIO_PLUG_EVENT# <13>
    DPSNK1_ML1_N GPIO_5 TBT_DDC_DATA

    CPU DDI2
    Y1

    LC GPIO
    CT31 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P2_C AB19 GPIO_6 Y2 TBT_DDC_CLK
    <7> DDI2_PTX_TBRX_P2
    CT32 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N2_C AC19 DPSNK1_ML2_P GPIO_7 AA1 TBT_SRC_CFG1

    SINK PORT 1
    <7> DDI2_PTX_TBRX_N2 DPSNK1_ML2_N GPIO_8 TBT_A_I2C_INT#
    J4
    TBT_A_I2C_INT# <43>
    CT33 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_P3_C AB21 POC_GPIO_0 E2 TBT_B_I2C_INT#
    <7> DDI2_PTX_TBRX_P3 TBT_B_I2C_INT# <44>
    CT34 2 1 0.1U_0201_6.3V6K DDI2_PTX_TBRX_N3_C AC21 DPSNK1_ML3_P POC_GPIO_1 D4 RTD3_USB_PWR_EN
    <7> DDI2_PTX_TBRX_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR RTD3_USB_PWR_EN <13>
    H4
    TBT_FORCE_PWR <13>
    CT35 2 1 0.1U_0201_6.3V6K CPU_DDI2_AUXP_C Y12 POC_GPIO_3 F2 TBT_BATLOW#
    TBT_BATLOW# <13>
    <7> CPU_DDI2_AUXP
    CT36 2 1 0.1U_0201_6.3V6K CPU_DDI2_AUXN_C W12 DPSNK1_AUX_P POC_GPIO_4 D2 TBT_SLP_S3_N RT16 1 @ 2 0_0201_5% SIO_SLP_S3# <12,36,38,39>
    <7> CPU_DDI2_AUXN

    POC GPIO
    DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN
    CPU_DP2_HPD POC_GPIO_6 RTD3_CIO_PWR_EN <13>
    Y6
    <7> CPU_DP2_HPD DPSNK1_HPD TBT_TEST_EN
    E1 2 1
    CPU_DP2_CTRL_CLK @ RT93 2 1 0_0201_5% TBT_SNK1_DDC_CLK Y8 TEST_EN 100_0201_1% RT18 RT69 2 1 0_0201_5%
    <7> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA @ RT94 2 TBT_RESET_N_EC <38>
    1 0_0201_5% TBT_SNK1_DDC_DATA N4 DPSNK1_DDC_CLK AB5 TBT_TEST_PWRG 2 1
    <7> CPU_DP2_CTRL_DATA DPSNK1_DDC_DATA TEST_PWR_GOOD

    Misc
    100_0201_1% RT21
    2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N_R @ RT17 2 1 0_0201_5%
    DPSNK_RBIAS RESET_N TBT_A_RESET_N <43>
    RT23 14K_0402_1%
    TBT_JTAG_TDI Y4 D22 XTAL_25_IN
    TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT @ RT15 2 1 0_0201_5%
    TBT_JTAG_TCK TMS XTAL_25_OUT TBT_B_RESET_N <44>
    AR/PPS COMMON FLASH T4
    TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI
    TDO MISC EE_DI AC4 TBT_ROM_DO @ RT12 2 1 0_0201_5%
    MUX_C_RESET_N <45>
    VCC3V3_TBT_LDO_A TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS#
    1 2 TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK
    RT28 4.75K_0402_0.5% RSENSE EE_CLK RT22 2 1 0_0201_5% UPD_MRESET <43,44,45>
    A15 B7
    <46> TBT_USB3_RX1_P PA_RX1_P PB_RX1_P TBT_USB3_RX3_P <46>
    B15 A7
    <46> TBT_USB3_RX1_N PA_RX1_N PB_RX1_N TBT_USB3_RX3_N <46>
    1
    1 0.22U_0201_6.3V6M TBT_USB3_TX1_P_C A17 TBT_USB3_TX3_P_C
    1

    CT39 2 A9 CT40 1 2 0.22U_0201_6.3V6M


    2.2K_0201_1%

    2.2K_0201_1%

    2.2K_0201_1%

    2.2K_0201_1%

    <46> TBT_USB3_TX1_P TBT_USB3_TX3_P <46>


    0.1U_0201_6.3V6K

    1 0.22U_0201_6.3V6M TBT_USB3_TX1_N_C B17 PA_TX1_P PB_TX1_P TBT_USB3_TX3_N_C


    CT51

    CT41 2 B9 1 2 0.22U_0201_6.3V6M
    RT47

    RT46

    RT45

    RT44

    <46> TBT_USB3_TX1_N CT42 TBT_USB3_TX3_N <46>


    PA_TX1_N PB_TX1_N
    C 2 CT43 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_P_C A19 A11 TBT_USB3_TX2_P_C CT44 1 2 0.22U_0201_6.3V6M C
    <46> TBT_USB3_TX0_P TBT_USB3_TX2_P <46>
    <46> TBT_USB3_TX0_N CT45 2 1 0.22U_0201_6.3V6M TBT_USB3_TX0_N_C B19 PA_TX0_P PB_TX0_P B11 TBT_USB3_TX2_N_C CT46 1 2 0.22U_0201_6.3V6M TBT_USB3_TX2_N <46>
    2

    PA_TX0_N PB_TX0_N
    TBT PORT A

    TBT PORT B
    B21 A13

    PORT A

    PORT B
    <46> TBT_USB3_RX0_P PA_RX0_P PB_RX0_P TBT_USB3_RX2_P <46>
    UT3 A21 B13
    TBT_ROM_CS# <46> TBT_USB3_RX0_N PA_RX0_N PB_RX0_N TBT_USB3_RX2_N <46>
    1 8
    TBT_ROM_DO 2 CS# VCC 7 TBT_ROM_HOLD# CT47 2 1 0.1U_0201_6.3V6K TBT_A_AUX_P_C Y15 Y16 TBT_B_AUX_P_C CT48 1 2 0.1U_0201_6.3V6K
    <43> TBT_A_AUX_P TBT_B_AUX_P <44>

    TBT PORTS
    TBT_ROM_WP# 3 DO(IO1) HOLD#(IO3) 6 TBT_ROM_CLK CT49 2 1 0.1U_0201_6.3V6K TBT_A_AUX_N_C W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 TBT_B_AUX_N_C CT50 1 2 0.1U_0201_6.3V6K
    WP#(IO2) CLK TBT_ROM_DI <43> TBT_A_AUX_N PA_DPSRC_AUX_N PB_DPSRC_AUX_N TBT_B_AUX_N <44>
    4 5
    GND DI(IO0) 9 E20 E19
    thermal pad <43> TBT_A_USB2_D_P PA_USB2_D_P PB_USB2_D_P TBT_B_USB2_D_P <44>
    <43> TBT_A_USB2_D_N
    D20 D19 TBT_B_USB2_D_N <44>
    W25Q64FVZPIQ PA_USB2_D_N PB_USB2_D_N
    TBT_A_LSTX A5 B4 TBT_B_LSTX
    <43> TBT_A_LSTX TBT_B_LSTX <44>

    POC

    POC
    TBT_A_LSRX A4 PA_LS_G1 PB_LS_G1 B5 TBT_B_LSRX
    <43> TBT_A_LSRX TBT_A_HPD PA_LS_G2 PB_LS_G2 TBT_B_HPD TBT_B_LSRX <44>
    RT44,RT47 use 3.3K ohm
    <43> TBT_A_HPD
    M4 G2 TBT_B_HPD <44>
    PA_LS_G3 PB_LS_G3
    Use SA00008WH00 for MP (1M) PA_USB2_RBIAS PB_USB2_RBIAS 2
    2 1 H19 F19 1
    PA_USB2_RBIAS PB_USB2_RBIAS
    +3VA_TBT RT42 AC23 D6 RT43
    499_0201_1% AB23 THERMDA MONDC_SVR 499_0201_1%
    THERMDA A23
    TBT_DDC_CLK ATEST_P PVT_0005
    RT11 2 1 2.2K_0201_5% PVT_0005 V18 B23
    PCIE_ATEST ATEST_N
    TBT_DDC_DATA RT13 2 1 2.2K_0201_5% AC1 E18
    TEST_EDM DEBUG USB2_ATEST
    L15 W13
    N15 FUSE_VQPS_64 MONDC_DPSNK_0
    FUSE_VQPS_128 W18
    TBT_SNK0_DDC_CLK RT80 2 1 100K_0201_5% C23 MONDC_DPSNK_1
    C22 MONDC_CIO_0 AB2
    TBT_SNK0_DDC_DATA RT81 2 1 100K_0201_5% MONDC_CIO_1 MONDC_DPSRC
    AR-4C_BGA337
    RTD3_CIO_PWR_EN @ RT34 2 1 10K_0201_1%
    TBT_SNK1_DDC_CLK RT82 2 1 100K_0201_5%
    TBT_SNK1_DDC_DATA RT83 2 1 100K_0201_5%

    +3VA_TBT

    CLKREQ_PCIE#0_N @ RT10 2 1 10K_0201_1%


    NOTE: XTAL
    ASSEMBLE R165, R166 if DPSRC
    RTD3_CIO_PWR_EN NOT IN USE YT1
    RT19 2 1 10K_0201_1% RT24 33_0201_1%
    4 3 XTAL_25_OUT_R 1 2 XTAL_25_OUT
    TBT_RESET_N_R @ RT14 2 1 10K_0201_1% RT72 33_0201_1%
    B TBT_SRC_CFG1 R165 1 2 1M_0201_1% XTAL_25_IN 2 1 XTAL_25_IN_R 1 2 B
    TBT_I2C_DATA RT25 2 1 2.2K_0201_5%
    TBT_SRC_HPD 1
    R166 1 2 100K_0201_5% 1
    TBT_I2C_CLK RT26 2 1 2.2K_0201_5% 25MHZ_20PF_FL2500123Z CT37
    NOTE: CT38 27P_0201_25V8
    PCIE_WAKE#_R @ RT27 2 1 10K_0201_1% 27P_0201_25V8 2
    TBT_SRC_CFG1 = 0 for DP mode. 2
    TBT_CIO_PLUG_EVENT# RT29 2 1 10K_0201_1%
    TBT_SLP_S3_N RT84 2 1 10K_0201_1%
    TBT_BATLOW# RT30 2 1 10K_0201_1%
    TBT_A_I2C_INT# RT31 2 1 10K_0201_1%
    TBT_B_I2C_INT# RT100 2 1 10K_0201_1%
    RTD3_USB_PWR_EN RT20 2 1 10K_0201_1%

    TBT_TMU_CLK_OUT RT32 2 1 100K_0201_5%


    TBT_FORCE_PWR RT33 2 1 10K_0201_1%
    TBT_B_HPD RT39 2 1 100K_0201_5%
    TBT_A_HPD RT36 2 1 100K_0201_5%
    TBT_A_LSRX RT38 2 1 1M_0201_1%
    TBT_B_LSRX RT41 2 1 1M_0201_1%
    TBT_B_LSTX RT40 2 1 1M_0201_1%
    TBT_A_LSTX RT37 2 1 1M_0201_1%
    RTD3_USB_PWR_EN @ RT35 2 1 100K_0201_5%

    A A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2014/09/08 Deciphered Date 2012/07/25

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P41-AR_TBT (1/2) DP / PCIE
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 41 of 61
    5 4 3 2 1
    5 4 3 2 1

    Vinafix.com close to UT2.R13

    +3V_TBT_S0
    close to UT2.H9

    +3VA_TBT

    D D

    39P_0201_50V8J
    EMC@ C1089

    100P_0201_50V8J
    EMC@ C1090

    39P_0201_50V8J
    EMC@ C1113

    100P_0201_50V8J
    EMC@ C1114
    1 1 1 1

    2 2 2 2

    close to UT2.F8

    +3VA_TBT +3VA_TBT

    RT88 1 @ 2 0_0402_5%~D
    close to UT2.R6

    39P_0201_50V8J
    EMC@ C1091

    100P_0201_50V8J
    EMC@ C1092
    PVT_0008 +3VA_TBT_LC +3VA_TBT_LC
    1 1
    +3VALW +3VA_TBT +3V_TBT_S0 close to UT2.A2,A3,B3 +3V_TBT
    LT2
    PVT_0008
    RT49 1 @ 2 0_0603_5% 1 1 2
    2 2

    39P_0201_50V8J
    EMC@ C1093

    100P_0201_50V8J
    EMC@ C1094

    0.1U_0201_10V6K
    CT59

    1U_0201_6.3V6M
    CT60

    1U_0201_6.3V6M
    +3V_TBT +3VS

    47U_0603_6.3V

    47U_0603_6.3V

    39P_0201_50V8J
    EMC@ C1095

    100P_0201_50V8J
    EMC@ C1096

    1U_0201_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    LQM18PN1R0MFHD_2P
    +3VS
    1 1 1 1 1 1 TDP=520mA

    CT91

    CT92

    CT93
    1 1 1 1 1 1 1
    2

    CT62

    CT63

    CT64

    CT65
    CT61
    RT89 1 @ 2 0_0603_5% RT50 2 @ 1 0_0603_5%
    2 2 2 2 2 2
    2 2 2 2 2 2 2 +3VALW

    R13
    +VCC0V9_PCIE +VCC0V9_DP +VCC0V9_DP RT90 1 2 0_0603_5%

    R6

    H9
    @

    F8
    close to UT2 close to UT2 @ UT2B
    L8 A2

    VCC3P3_LC

    VCC3P3_SX

    VCC3P3A
    VCC3P3_S0
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    L11 VCC0P9_DP VCC3P3_SVR A3
    L12 VCC0P9_DP VCC3P3_SVR
    39P_0201_50V8J
    EMC@ C1099

    100P_0201_50V8J
    EMC@ C1100

    39P_0201_50V8J
    EMC@ C1097

    100P_0201_50V8J
    EMC@ C1098

    1 1 1 1 1 1 1 B3
    M8 VCC0P9_DP VCC3P3_SVR
    CT52

    CT53

    CT54

    CT55

    CT56

    CT57

    CT58
    1 1 1 1
    T11 VCC0P9_DP
    T12 VCC0P9_DP L9 VCC0V9_SVR

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    2 2 2 2 2 2 2 L6 VCC0P9_DP VCC0P9_SVR M9
    2 2 2 2 M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12 1 1 1 1 1 1 1
    V11 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA E13

    CT72

    CT73

    CT74

    CT75

    CT76

    CT77

    CT78
    V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11 close to UT2 close to UT2
    +VCC0V9_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
    VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2 VCC0V9_SVR TBT_SVR_IND
    M13 VCC0P9_SVR_ANA F15
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    M15 VCC0P9_PCIE VCC0P9_SVR_ANA

    39P_0201_50V8J
    EMC@ C1101

    100P_0201_50V8J
    EMC@ C1102

    39P_0201_50V8J
    EMC@ C1115

    100P_0201_50V8J
    EMC@ C1116
    J9
    1 1 1 1 M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
    1 1 1 1
    +VCC0V9_USB L19 VCC0P9_PCIE LT1
    CT67

    CT68

    CT69

    CT70

    VCC
    C close to UT2.R15,R16 N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2 0.60UH +-20% MND-04ABIR60M-XGL C
    L18 VCC0P9_ANA_PCIE_1 SVR_IND C2
    2 2 2 2 M18 VCC0P9_ANA_PCIE_2 SVR_IND 2 2 2 2

    47U_0603_6.3V

    47U_0603_6.3V

    47U_0603_6.3V
    D1 1 1 1
    N18 VCC0P9_ANA_PCIE_2 SVR_IND
    39P_0201_50V8J
    EMC@ C1103

    100P_0201_50V8J
    EMC@ C1104

    CT79

    CT80

    CT81
    +VCC0V9_USB VCC0P9_ANA_PCIE_2
    1 1
    R15 A1
    R16 VCC0P9_USB SVR_VSS B1 2 2 2
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    VCC0P9_USB SVR_VSS B2
    2 2 R8 SVR_VSS
    1 1
    R9 VCC0P9_CIO
    CT71

    CT66

    R11 VCC0P9_CIO
    R12 VCC0P9_CIO F18
    2 2 VCC0P9_CIO VCC0P9_LVR H18 close to UT2
    VCC_3V3_PCIE L16 VCC0P9_LVR J11
    VCC_3V3_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11 VCC0V9_LVR_OUT VCC0V9_LVR_OUT

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE

    10U_0402_6.3V6M

    10U_0402_6.3V6M
    +VCC0V9_CIO

    39P_0201_50V8J
    EMC@ C1105

    100P_0201_50V8J
    EMC@ C1106
    A6 V5 1 1 1 1
    +VCC0V9_CIO A8 VSS_ANA VSS_ANA

    CT85

    CT86
    close to UT2.R8,R9,R11,R12 V6

    CT87

    CT88
    1 1
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    A10 VSS_ANA VSS_ANA V8


    1 1 A12 VSS_ANA VSS_ANA V9
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    A14 VSS_ANA VSS_ANA 2 2 2 2


    39P_0201_50V8J
    EMC@ C1107

    100P_0201_50V8J
    EMC@ C1108

    V15
    A16 VSS_ANA VSS_ANA
    CT89

    CT90

    V16 2 2
    1 1 1 1 1
    A18 VSS_ANA VSS_ANA V20
    CT82

    CT83

    CT84

    2 2 A20 VSS_ANA VSS_ANA W5


    A22 VSS_ANA VSS_ANA W6
    2 2 2 2 2 B6 VSS_ANA VSS_ANA W8
    B8 VSS_ANA VSS_ANA W9
    B10 VSS_ANA VSS_ANA W20
    B12 VSS_ANA VSS_ANA W22
    B14 VSS_ANA VSS_ANA W23
    B16 VSS_ANA VSS_ANA Y9
    close to UT2.L16 close to UT2.J16 B18 VSS_ANA VSS_ANA Y13
    B20 VSS_ANA VSS_ANA Y20
    VCC_3V3_PCIE VCC_3V3_USB2 B22 VSS_ANA VSS_ANA AA22
    D8 VSS_ANA VSS_ANA AA23
    D9 VSS_ANA VSS_ANA
    39P_0201_50V8J
    EMC@ C1109

    100P_0201_50V8J
    EMC@ C1110

    39P_0201_50V8J
    EMC@ C1111

    100P_0201_50V8J
    EMC@ C1112

    AB6
    1 1 1 1 D11 VSS_ANA VSS_ANA AB8
    D12 VSS_ANA VSS_ANA AB10
    D13 VSS_ANA VSS_ANA AB12
    D15 VSS_ANA VSS_ANA AB14
    2 2 2 2 D16 VSS_ANA VSS_ANA AB16
    D18 VSS_ANA VSS_ANA AB18
    E8 VSS_ANA VSS_ANA AB20
    E9 VSS_ANA VSS_ANA AB22
    E11 VSS_ANA VSS_ANA AC6
    E15 VSS_ANA VSS_ANA AC8
    E16 VSS_ANA VSS_ANA AC10
    GND

    E22 VSS_ANA VSS_ANA AC12


    E23 VSS_ANA VSS_ANA AC14
    F9 VSS_ANA VSS_ANA AC16
    B F16 VSS_ANA VSS_ANA AC18 B
    F20 VSS_ANA VSS_ANA AC20
    G22 VSS_ANA VSS_ANA AC22
    G23 VSS_ANA VSS_ANA D5
    H1 VSS_ANA VSS E4
    H2 VSS_ANA VSS E5
    H12 VSS_ANA VSS E6
    H13 VSS_ANA VSS F5
    H15 VSS_ANA VSS F6
    H16 VSS_ANA VSS H5
    H20 VSS_ANA VSS H8
    J5 VSS_ANA VSS J8
    J18 VSS_ANA VSS J12
    J19 VSS_ANA VSS J13
    J20 VSS_ANA VSS J15
    J22 VSS_ANA VSS L13
    J23 VSS_ANA VSS M11
    K1 VSS_ANA VSS M12
    K2 VSS_ANA VSS N8
    L5 VSS_ANA VSS N9
    L20 VSS_ANA VSS N11
    L22 VSS_ANA VSS N12
    L23 VSS_ANA VSS N13
    M1 VSS_ANA VSS T6
    M2 VSS_ANA VSS T8
    M5 VSS_ANA VSS T9
    M19 VSS_ANA VSS T13
    M20 VSS_ANA VSS T15
    N5 VSS_ANA VSS T16
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA
    VSS_ANA

    N20 VSS_ANA VSS T18


    N22 VSS_ANA VSS AB1
    N23 VSS_ANA VSS AC2
    VSS_ANA VSS
    AR-4C_BGA337
    P1
    P2
    R5
    R18
    R19
    R20
    R22
    R23
    T1
    T2
    T5
    T20
    U23
    U22

    A A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2014/09/08 Deciphered Date 2012/07/25

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P42-AR_TBT (2/2) PWR / VSS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 42 of 61
    5 4 3 2 1
    5 4 3 2 1

    TBT_LDO_BMC_A VCC3V3_TBT_SX_A VCC3V3_TBT_LDO_A

    +5VALW
    1 1 1
    CT96 C141 C142
    2.2U_0402_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
    2 2 2
    1 1 1 1
    C143 C144 C145 C146

    2 Vinafix.com
    22U_0603_6.3V6M
    2
    22U_0603_6.3V6M
    2
    22U_0603_6.3V6M
    2
    22U_0603_6.3V6M

    +3V_LDO +3V_VC_A VCC1V8A_TBT_LDO_A VCC1V8D_TBT_LDO_A +VBUS1_PD_20V


    D D

    R5746 1 @ 2
    1 1

    1
    +3VALW 0_0402_1%
    CT94 CT95 C140
    @ R265 1 2 0_0402_5% 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 1U_0603_25V6K

    2
    +3V_VC_A 2 2
    VCC3V3_TBT_LDO_A

    @ R5747 1 2 0_0402_5% 1

    VIN_3V3 source for dead battery C139


    Placement in bottom side 10U_0402_6.3V6M
    2 U19

    R5794 1 @ 2 A6 B10
    A7 PP_HV SENSEP A10
    0_0402_1% A8 PP_HV SENSEN
    VCC3V3_TBT_LDO_A B7 PP_HV
    PP_HV B9
    A11 HV_GATE1 A9 TBT_A_VBUS_L +VBUS1_PD_20V
    +5VALW PP_5V0 HV_GATE2
    1 C11 EMC@ LT3
    B11 PP_5V0
    C1087 D11 PP_5V0 H11 1 2
    PP_5V0 VBUS J10
    0.1U_0201_10V6K VBUS
    2 H10 J11 HCB2012KF-121T50_0805

    2
    PP_CABLE VBUS

    BAT54LPS-7
    K11
    VBUS

    D21
    B1 C148
    VDDIO 1U_0603_25V6K EMC@ DI1

    2
    +3V_VC_A H1 H2 VCC3V3_TBT_SX_A AZ4024-02S_SOT23-3~D
    VIN_3V3 VOUT_3V3 G1
    VCC3V3_TBT_LDO_A

    2
    VCC3V3_TBT_LDO_A LDO_3V3 K1
    VCC1V8A_TBT_LDO_A

    1
    D1 LDO_1V8A A2
    PD1_EE_CS# <41,44> TBT_I2C_DATA I2C_SDA1 LDO_1V8D VCC1V8D_TBT_LDO_A
    R167 1 2 4.7K_0201_5% D2 E1
    PD1_EE_DO <41,44> TBT_I2C_CLK I2C_SCL1 LDO_BMC TBT_LDO_BMC_A
    R168 1 2 4.7K_0201_5% <41> TBT_A_I2C_INT# C1 Use SCS0000AO00
    R169 1 2 4.7K_0201_5% PD1_EE_WP# I2C_IRQ1_N
    R170 1 2 4.7K_0201_5% PD1_HOLD# UPD1_SMBDAT A5
    <38> UPD1_SMBDAT UPD1_SMBCLK I2C_SDA2
    C <38> UPD1_SMBCLK B5 C
    B6 I2C_SCL2 L9
    <38> UPD1_ALERT# I2C_IRQ2_N C_CC1 TBT_A_CC1 <46>
    L10 TBT_A_CC2 <46>
    C_CC2
    VCC3V3_TBT_LDO_A PD1_EE_CLK R5777 1 @ 20_0201_5% PD1_EE_CLK_F A3 K9 1 1

    220P_0402_50V8K

    220P_0402_50V8K
    <44> PD1_EE_CLK PD1_EE_DI R5774 SPI_CLK RPD_G1
    1 @ 20_0201_5% PD1_EE_DI_F B4 K10

    C149

    C150
    <44> PD1_EE_DI PD1_EE_DO R5775 SPI_MOSI RPD_G2
    1 @ 20_0201_5% PD1_EE_DO_F A4
    <44> PD1_EE_DO PD1_EE_CS# R5776 SPI_MISO
    <44> PD1_EE_CS# 1 @ 20_0201_5% PD1_EE_CS#_F B3
    UT4 SPI_SS_N K6 EMC@ 2 2 EMC@
    PD1_EE_CS# C_USB_TP TBT_A_USB2_T_P <46>
    1 8 PVT_0008 L6
    PD1_EE_DO /CS VCC PD1_HOLD# C_USB_TN TBT_A_USB2_T_N <46>
    2 7 <41> TBT_A_USB2_D_P L5
    PD1_EE_WP# 3 DO(IO1) /HOLD(IO3) 6 PD1_EE_CLK K5 USB_RP_P
    <41> TBT_A_USB2_D_N
    DAP

    4 /WP(IO2) CLK 5 PD1_EE_DI USB_RP_N K7


    GND DI(IO0) C_USB_BP TBT_A_I2C_B_P <46>
    L7
    TBT_A_AUX_P C_USB_BN TBT_A_I2C_B_N <46>
    J1
    <41> TBT_A_AUX_P
    9

    W25Q64FVZPIQ TBT_A_AUX_N J2 AUX_P


    <41> TBT_A_AUX_N AUX_N TBT_A_SBU1
    K8
    C_SBU1 TBT_A_SBU2 TBT_A_SBU1 <46>
    Use SA00008WH00 for MP (1M) L8 TBT_A_SBU2 <46>
    @ TC1 G4 C_SBU2
    @ TC2 F4 SWD_CLK
    R5748 1 2 1M_0402_5% UART_MISO SWD_DATA B2 PD1_GPIO0 @ TC3 PD1_GPIO2 1 2
    GPIO0 C2 PD1_GPIO1 R173 1 @ 2 0_0201_5% R5749 1M_0402_5%
    UART_MOSI UART_MOSI GPIO1 PD1_GPIO2 EN_PD_HV1 <49> PD1_GPIO1
    R5750 1 2 1M_0402_5% <44> UART_MOSI E2 D10 @ TC48 1 @ 2
    UART_MISO F2 UART_TX GPIO2 G11 R5751 1M_0402_5%
    <44> UART_MISO UART_RX GPIO3 PD1_GPIO4 AC1_DISC# <49,50>
    C10 R175 1 @ 2 0_0201_5%
    TBT_A_LSTX TBT_A_LSTX_R GPIO4 PD1_GPIO5 TBT_A_HPD <41>
    <41> TBT_A_LSTX R187 1 @ 2 0_0201_5% L4 E10 @ TC5
    TBT_A_LSRX R189 1 @ 2 0_0201_5% TBT_A_LSRX_R K4 LSTX/R2P GPIO5 G10 PD1_GPIO6 @ TC49
    <41> TBT_A_LSRX LSRX/P2R GPIO6 PD1_GPIO7
    D7 R176 1 @ 2 0_0201_5% TBT_A_USB_OC0# <11>
    R177 1 2 10K_0402_5% TBT_A_DBG_CTL1 E4 GPIO7 H6 PD1_GPIO8 R178 1 @ 2 0_0201_5% PD1_GPIO8_EXT
    VCC3V3_TBT_LDO_A TBT_A_DBG_CTL2 DEBUG_CTL1 GPIO8
    R179 1 2 10K_0402_5% D5 PVT_0008
    DEBUG_CTL2
    UPD1_SMBCLK R180 1 @ 2 0_0402_1% USBC_MCP23017_SMBCLK_R_A L2 PD_MRESET_A @ R181 1 2 0_0201_5%
    UPD1_SMBDAT DEBUG1 UPD_MRESET <41,44,45>
    R182 1 @ 2 0_0402_1% USBC_MCP23017_SMBDAT_R_A K2 E11 R183 1 2 100K_0402_5%
    DEBUG2 MRESET
    TBT_A_LSTX @ R191 1 20_0201_5% TBT_A_DEBUG3 L3 F11
    TBT_A_LSRX TBT_A_DEBUG4 DEBUG3 RESET_N TBT_A_RESET_N <41>
    @ R192 1 20_0201_5% K3
    DEBUG4 F10 @ RT52 1 2 0_0402_5%
    BUSPOWER_N VCC1V8A_TBT_LDO_A
    F1
    B I2C_ADDR G2 @ RT51 1 2 0_0402_5% B
    R_OSC VCC3V3_TBT_LDO_A
    VCC3V3_TBT_LDO_A H7
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    1

    SS
    100K_0201_5%

    100K_0201_5%

    15K_0402_1%
    1

    1
    RT53

    RT54

    0.22U_0201_6.3V6M
    RT55 1
    TBT_A_AUX_N

    C151

    R184
    R185 1 2 100K_0402_5% @ 0_0402_1% TPS65982D_BGA96 RT56
    A1
    D6
    E5
    E6
    E7
    F5
    G5
    H4
    H5
    B8
    D8
    E8
    F6
    F7
    F8
    G6
    G7
    G8
    H8
    L1
    L11
    R186 1 2 100K_0402_5% TBT_A_AUX_P @ 0_0402_1% HRESET_PD1_EC
    VCC3V3_TBT_LDO_A HRESET_PD1_EC <38>
    2

    RT95 2

    2
    1 2

    @
    0_0402_5%

    1
    HRESET_PD1

    0_0201_5%
    R5753
    R5752

    @
    10K_0402_1%

    2
    PD1_GPIO8_EXT HRESET_PD1

    TBT_A_LSTX TBT_A_SBU2

    100K_0201_5%
    R5757
    @ R5754 1 2 0_0201_5%

    2
    TBT_A_LSRX @ R5755 1 2 0_0201_5% TBT_A_SBU1
    R5756
    100K_0402_1%

    1
    A A

    Factory Set Device Configurations 7


    Infinite boot retry from Flash to Host I/F cycles.
    DIV=RT106/(RT105+RT106)
    between 0.7~1.0

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P43-PD CONTROL 1
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 43 of 61
    5 4 3 2 1
    5 4 3 2 1

    +5VALW

    1 1 1 1
    C156 C157 C158 C159 TBT_LDO_BMC_B VCC3V3_TBT_SX_B VCC3V3_TBT_LDO_B
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2 2 2 2
    1 1 1

    Vinafix.com 2
    CT99
    2.2U_0402_6.3V6M
    2
    C154
    1U_0201_6.3V6M
    2
    C155
    10U_0402_6.3V6M

    D D
    +3V_VC_B

    VCC1V8A_TBT_LDO_B VCC1V8D_TBT_LDO_B +VBUS2_PD_20V


    1
    C152
    10U_0402_6.3V6M 1 1

    1
    2
    CT97 CT98 C153
    4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 1U_0603_25V6K

    2
    2 2

    PVT_0008
    U20
    R5795
    2 @ 1 0_0402_1% A6 B10
    A7 PP_HV SENSEP A10
    PVT_0008 PP_HV SENSEN
    A8
    +3V_LDO +3V_VC_B B7 PP_HV
    PP_HV B9
    R5758 1 @ 2 0_0402_1% A11 HV_GATE1 A9 TBT_B_VBUS_L +VBUS2_PD_20V
    +5VALW PP_5V0 HV_GATE2
    C11 EMC@ LT4
    +3VALW B11 PP_5V0
    D11 PP_5V0 H11 1 2
    @ R266 1 2 0_0402_5% PP_5V0 VBUS J10
    H10 VBUS J11 HCB2012KF-121T50_0805

    2
    VCC3V3_TBT_LDO_B PP_CABLE VBUS

    BAT54LPS-7
    K11
    VBUS

    D22
    B1 C161
    @ R5759 1 2 0_0402_5% VDDIO 1U_0603_25V6K EMC@ DI2

    2
    H1 H2 AZ4024-02S_SOT23-3~D
    +3V_VC_B VIN_3V3 VOUT_3V3 VCC3V3_TBT_SX_B
    VIN_3V3 source for dead battery G1 VCC3V3_TBT_LDO_B

    2
    LDO_3V3 K1
    Placement in bottom side VCC1V8A_TBT_LDO_B

    1
    D1 LDO_1V8A A2
    <41,43> TBT_I2C_DATA I2C_SDA1 LDO_1V8D VCC1V8D_TBT_LDO_B
    C <41,43> TBT_I2C_CLK D2 E1 TBT_LDO_BMC_B C
    C1 I2C_SCL1 LDO_BMC
    <41> TBT_B_I2C_INT# I2C_IRQ1_N Use SCS0000AO00
    UPD2_SMBDAT A5
    <38> UPD2_SMBDAT UPD2_SMBCLK I2C_SDA2
    B5
    <38> UPD2_SMBCLK I2C_SCL2
    <38> UPD2_ALERT# B6 L9 TBT_B_CC1 <46>
    I2C_IRQ2_N C_CC1 L10
    C_CC2 TBT_B_CC2 <46>
    PD1_EE_CLK @ R5778 1 20_0201_5% PD2_EE_CLK A3 K9 1 1

    220P_0402_50V8K

    220P_0402_50V8K
    <43> PD1_EE_CLK PD1_EE_DI PD2_EE_DI SPI_CLK RPD_G1
    1 20_0201_5% B4 K10

    C162

    C163
    <43> PD1_EE_DI @ R5779
    PD1_EE_DO @ R5780 1 20_0201_5% PD2_EE_DO A4 SPI_MOSI RPD_G2
    <43> PD1_EE_DO PD1_EE_CS# PD2_EE_CS# SPI_MISO
    @ R5781 1 20_0201_5% B3
    <43> PD1_EE_CS# SPI_SS_N 2 2
    K6 TBT_B_USB2_T_P <46>EMC@ EMC@
    C_USB_TP L6
    VCC3V3_TBT_LDO_B C_USB_TN TBT_B_USB2_T_N <46>
    L5
    <41> TBT_B_USB2_D_P USB_RP_P
    <41> TBT_B_USB2_D_N K5
    USB_RP_N K7
    PD2_EE_CS# C_USB_BP TBT_B_I2C_B_P <46>
    R5782 1 2 3.3K_0402_0.5% L7 TBT_B_I2C_B_N <46>
    R5783 1 2 100K_0201_5% PD2_EE_CLK TBT_B_AUX_P J1 C_USB_BN
    PD2_EE_DI <41> TBT_B_AUX_P TBT_B_AUX_N AUX_P
    R5784 1 2 100K_0201_5% J2
    PD2_EE_DO <41> TBT_B_AUX_N AUX_N
    R5785 1 2 100K_0201_5% K8 TBT_B_SBU1 <46>
    C_SBU1 L8
    C_SBU2 TBT_B_SBU2 <46>
    @ TC6 G4
    @ TC7 F4 SWD_CLK
    SWD_DATA B2 PD2_GPIO0 @ TC8
    GPIO0 C2 PD2_GPIO1 R201 1 @ 2 0_0201_5%
    UART_MISO GPIO1 PD2_GPIO2 EN_PD_HV2 <49>
    E2 D10 @ TC46
    <43> UART_MISO UART_MOSI UART_TX GPIO2
    <43> UART_MOSI F2 G11 AC2_DISC# <49,50>
    UART_RX GPIO3 C10 PD2_GPIO4 R203 1 @ 2 0_0201_5%
    TBT_B_LSTX TBT_B_LSTX_R GPIO4 PD2_GPIO5 TBT_B_HPD <41> PD2_GPIO2
    <41> TBT_B_LSTX R215 1 @ 2 0_0201_5% L4 E10 @ TC10 1 2
    TBT_B_LSRX R216 1 @ 2 0_0201_5% TBT_B_LSRX_R K4 LSTX/R2P GPIO5 G10 PD2_GPIO6 @ TC47 R5760 1M_0402_5%
    <41> TBT_B_LSRX LSRX/P2R GPIO6 PD2_GPIO7 PD2_GPIO1
    D7 R204 1 @ 2 0_0201_5% 1 @ 2
    TBT_B_DBG_CTL1 GPIO7 PD2_GPIO8 TBT_B_USB_OC1# <11>
    VCC3V3_TBT_LDO_B R205 1 2 10K_0402_5% E4 H6 R206 1 @ 2 0_0201_5% PD2_GPIO8_EXT R5761 1M_0402_5%
    R207 1 2 10K_0402_5% TBT_B_DBG_CTL2 D5 DEBUG_CTL1 GPIO8
    DEBUG_CTL2 PVT_0008
    UPD2_SMBCLK R208 1 @ 2 0_0402_1% USBC_MCP23017_SMBCLK_R_B L2 PD_MRESET_B @ R209 1 2 0_0201_5%
    UPD2_SMBDAT DEBUG1 UPD_MRESET <41,43,45>
    R210 1 @ 2 0_0402_1% USBC_MCP23017_SMBDAT_R_B K2 E11 R211 1 2 100K_0402_5%
    DEBUG2 MRESET
    B TBT_B_LSTX @ R218 1 20_0201_5% TBT_B_DEBUG3 L3 F11 B
    TBT_B_LSRX TBT_B_DEBUG4 DEBUG3 RESET_N TBT_B_RESET_N <41>
    @ R220 1 20_0201_5% K3
    DEBUG4 F10 @ RT58 1 2 0_0402_5%
    BUSPOWER_N VCC1V8A_TBT_LDO_B
    F1
    I2C_ADDR G2 @ RT57 1 2 0_0402_5%
    R_OSC VCC3V3_TBT_LDO_B
    @ H7
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    SS
    1

    1
    100K_0201_5%

    100K_0201_5%

    0_0402_5%

    15K_0402_1%
    1

    1
    RT59

    RT60

    RT61

    0.22U_0201_6.3V6M
    1

    C164

    R213
    VCC3V3_TBT_LDO_B TPS65982D_BGA96 RT62 VCC3V3_TBT_LDO_B
    A1
    D6
    E5
    E6
    E7
    F5
    G5
    H4
    H5
    B8
    D8
    E8
    F6
    F7
    F8
    G6
    G7
    G8
    H8
    L1
    L11

    @ 0_0402_1% HRESET_PD2_EC
    HRESET_PD2_EC <38>
    2

    R212 1 2 100K_0402_5% TBT_B_AUX_N RT96 2

    2
    R214 1 2 100K_0402_5% TBT_B_AUX_P 1 2

    1
    @ R5762

    1
    HRESET_PD2 0_0402_5% 10K_0402_1%

    0_0201_5%
    R5763
    @

    2
    2
    PD2_GPIO8_EXT

    HRESET_PD2
    TBT_B_LSTX @ R5764 1 2 0_0201_5% TBT_B_SBU1
    TBT_B_LSRX @ R5765 1 2 0_0201_5% TBT_B_SBU2

    1
    100K_0201_5%
    R5745
    R5744

    2
    100K_0402_1%

    2
    1
    A A

    Factory Set Device Configurations 7


    Infinite boot retry from Flash to Host I/F cycles.
    DIV=RT106/(RT105+RT106)
    between 0.7~1.0

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P44-PD CONTROL 2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 44 of 61
    5 4 3 2 1
    5 4 3 2 1

    +5VALW

    PVT_0008 VCC3V3_TBT_SX_C VCC3V3_TBT_LDO_C VCC1V8A_TBT_LDO_C VCC1V8D_TBT_LDO_C TBT_LDO_BMC_C +VBUS3_PD_20V

    +3V_LDO
    R5766
    +3V_VC_C
    1
    Vinafix.com 1 1 1 1 1 1 1 1

    1
    1 @ 2 C169 C170 C171 C172
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M C167 C168 CT100 CT101 CT102 C166
    D +3VALW 1U_0603_25V6K D
    0_0402_1% 1U_0201_6.3V6M 10U_0402_6.3V6M 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 2.2U_0402_6.3V6M

    2
    2 2 2 2 2 2 2 2 2
    @ R267 1 2 0_0402_5%

    VCC3V3_TBT_LDO_A

    @ R5767 1 2 0_0402_5%

    VIN_3V3 source for dead battery PVT_0008


    Placement in bottom side U21
    +3V_VC_C R5796
    1 @ 2 A6 B10
    A7 PP_HV SENSEP A10
    0_0402_1% A8 PP_HV SENSEN
    1 PP_HV
    B7
    C165 PP_HV B9
    A11 HV_GATE1 A9 MUX_C_VBUS_L +VBUS3_PD_20V
    10U_0402_6.3V6M +5VALW PP_5V0 HV_GATE2
    2 C11 EMC@ LT5
    B11 PP_5V0
    D11 PP_5V0 H11 1 2
    PP_5V0 VBUS J10
    H10 VBUS J11 HCB2012KF-121T50_0805

    2
    PP_CABLE VBUS

    BAT54LPS-7
    K11
    VBUS

    D23
    +3V_VC_C B1 C174
    VDDIO 1U_0603_25V6K EMC@ DI3

    2
    H1 H2 AZ4024-02S_SOT23-3~D
    USB20_P1 VIN_3V3 VOUT_3V3 VCC3V3_TBT_SX_C
    <11> USB20_P1 G1 VCC3V3_TBT_LDO_C

    2
    USB20_N1 LDO_3V3 K1
    <11> USB20_N1 VCC1V8A_TBT_LDO_C

    1
    R5771 1 @ 2 0_0402_5% I2C_DAT1_PD3 D1 LDO_1V8A A2
    I2C_SDA1 LDO_1V8D VCC1V8D_TBT_LDO_C
    R5772 1 @ 2 0_0402_5% I2C_SCL1_PD3 D2 E1
    I2C_SCL1 LDO_BMC TBT_LDO_BMC_C
    R5773 1 @ 2 0_0402_5% I2C_IRQ1_PD3 C1 Use SCS0000AO00
    I2C_IRQ1_N
    UPD3_SMBDAT A5
    <31,38> UPD3_SMBDAT UPD3_SMBCLK I2C_SDA2
    <31,38> UPD3_SMBCLK B5
    VCC3V3_TBT_LDO_C B6 I2C_SCL2 L9
    <38> UPD3_ALERT# I2C_IRQ2_N C_CC1 MUX_C_CC1 <47>
    L10
    C_CC2 MUX_C_CC2 <47>
    C C
    @ R5814 1 2 100K_0402_5% MUX_C_AUX_N PD3_EE_CLK A3 K9 1 1

    220P_0402_50V8K

    220P_0402_50V8K
    @ R5815 1 2 100K_0402_5% MUX_C_AUX_P PD3_EE_DI B4 SPI_CLK RPD_G1 K10

    C175

    C176
    PD3_EE_DO A4 SPI_MOSI RPD_G2
    PD3_EE_CS# B3 SPI_MISO
    SPI_SS_N K6 2 2
    C_USB_TP TOP_MUX_P <47>
    L6
    USB20_P1 C_USB_TN TOP_MUX_N <47>
    L5
    USB20_N1 K5 USB_RP_P
    USB_RP_N K7 EMC@ EMC@
    C_USB_BP BOT_MUX_P <47>
    L7 BOT_MUX_N <47>
    @ C1117 1 2 0.1U_0201_10V6K MUX_C_AUX_P J1 C_USB_BN
    <31,41> TBT_DP_AUX_P MUX_C_AUX_N AUX_P
    <31,41> TBT_DP_AUX_N @ C1118 1 2 0.1U_0201_10V6K J2
    AUX_N K8 MUX_C_PD_SBU1 R227 1 @ 2 0_0201_5%
    C_SBU1 MUX_C_PD_SBU2 MUX_C_SBU1 <31,47>
    L8 R228 1 @ 2 0_0201_5%
    C_SBU2 MUX_C_SBU2 <31,47>
    @ TC11 G4
    @ TC12 F4 SWD_CLK R5818 1 2 0_0201_5% MUX_FLIP_SEL PD3_GPIO1 1 @ 2
    SWD_DATA PD3_GPIO0 PD3_USBC_POL MUX_FLIP_SEL <31>
    B2 R5786 1 @ 2 0_0201_5% PD3_USBC_POL <31> R5769 1M_0402_5%
    GPIO0 C2 PD3_GPIO1 R229 1 @ 2 0_0201_5% PD3_GPIO2 1 2
    GPIO1 PD3_GPIO2 EN_PD_HV3 <49>
    R5789 2 1 100K_0201_5% E2 D10 R5768 1M_0402_5%
    R230 1 @ 2 0_0201_5% F2 UART_TX GPIO2 G11
    UART_RX GPIO3 PD3_GPIO4 AC3_DISC# <49,50>
    C10 R5770 1 @ 2 0_0201_5%
    TBT_C_LSTX_R GPIO4 PD3_GPIO5 TBT_DP_HPD <31,41>
    L4 E10 R5791 1 @ 2 0_0201_5%
    VCC3V3_TBT_LDO_C @ TC50 TBT_C_LSRX_R K4 LSTX/R2P GPIO5 G10 PD3_GPIO6 @ TC45
    LSRX/P2R GPIO6 D7 PD3_GPIO7 R232 1 @ 2 0_0201_5%
    TBT_C_DBG_CTL1 GPIO7 PD3_GPIO8 PD3_GPIO8_EXT MUX_C_USB_OC2# <11>
    R233 1 2 10K_0402_5% E4 H6 R234 1 @ 2 0_0201_5%
    R235 1 2 10K_0402_5% TBT_C_DBG_CTL2 D5 DEBUG_CTL1 GPIO8
    MUX_FLIP_SEL R5819 1 @ 2 0_0201_5% DEBUG_CTL2 VCC3V3_TBT_LDO_C
    PD3_USBC_POL R5816 1 @ 2 0_0201_5% UPD3_SMBCLK R236 1 @ 2 0_0201_5% TBT_C_DEBUG1 L2 PD_MRESET_C R237 1 @ 2 0_0201_5%
    MUX_USB_SEL DEBUG1 UPD_MRESET <41,43,44>
    R5817 1 @ 2 0_0201_5% UPD3_SMBDAT R238 1 @ 2 0_0201_5% TBT_C_DEBUG2 K2 E11 1 2
    DEBUG2 MRESET R239 1M_0402_5%
    MUX_DP_SEL R5787 1 @ 2 0_0201_5% TBT_C_DEBUG3 L3 F11
    <31> PD3_USBC_AMSEL DEBUG3 RESET_N MUX_C_RESET_N <41>

    1
    MUX_USB_SEL R5788 1 @ 2 0_0201_5% TBT_C_DEBUG4 K3
    <31> MUX_USB_SEL DEBUG4 F10 @ RT63 1 2 0_0402_5% R5792
    BUSPOWER_N VCC3V3_TBT_LDO_C
    F1 10K_0402_1%
    I2C_ADDR G2 @ RT64 1 2 0_0402_5%
    R_OSC VCC1V8A_TBT_LDO_C

    2
    H7
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    1

    B TBT_C_LSTX_R SS B

    15K_0402_1%
    R5790 1 2 1K_0201_5%

    1
    0.22U_0201_6.3V6M
    RT67 1 PD3_GPIO8_EXT

    C177

    R240
    @ 0_0402_1% TPS65982D_BGA96 RT68
    A1
    D6
    E5
    E6
    E7
    F5
    G5
    H4
    H5
    B8
    D8
    E8
    F6
    F7
    F8
    G6
    G7
    G8
    H8
    L1
    L11
    VCC3V3_TBT_LDO_C @ 0_0402_1%
    2

    R223 1 2 4.7K_0201_5% PD3_EE_CS# RT97 2

    2
    R224 1 2 4.7K_0201_5% PD3_EE_DO 1 2

    1
    R225 1 2 4.7K_0201_5% PD3_EE_WP#
    R226 1 2 4.7K_0201_5% PD3_HOLD# @ R5793
    HRESET_PD3 0_0402_5%
    100K_0402_1%

    2
    VCC3V3_TBT_LDO_C VCC3V3_TBT_LDO_C HRESET_PD3_EC
    HRESET_PD3_EC <38>

    UT6 1
    PD3_EE_CS# 1 8
    PD3_EE_DO 2 /CS VCC 7 PD3_HOLD# C1088
    DO(IO1) /HOLD(IO3)

    1
    PD3_EE_WP# 3 6 PD3_EE_CLK
    0.1U_0201_10V6K
    DAP

    /WP(IO2) CLK PD3_EE_DI 2

    0_0201_5%
    RT98
    4 5
    GND DI(IO0)

    @
    9

    2
    W25Q64FVZPIQ

    HRESET_PD3

    voltage rating is 1.8v 100K_0201_5%


    RT99
    2
    1

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P45-PD CONTROL 3
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 45 of 61
    5 4 3 2 1
    5 4 3 2 1

    PVT_0017 D24 EMC@ D25 EMC@


    TBT_USB3_TX0_P 1 2 TBT_USB3_RX0_P 1 2

    Vinafix.com PESD5V0C1BSF

    D26 EMC@
    PESD5V0C1BSF

    D27 EMC@
    D TBT_USB3_TX0_N 1 2 TBT_USB3_RX0_N 1 2 D

    PESD5V0C1BSF PESD5V0C1BSF

    D28 EMC@ D29 EMC@


    TBT_A_CC1 1 2 TBT_A_SBU2 1 2

    ESD8011MUT5G ESD8011MUT5G

    D30 EMC@ D31 EMC@


    +VBUS1_PD_20V
    TBT_A_SBU1 1 2 TBT_A_CC2 1 2

    10U_0603_25V6M

    0.1U_0402_25V6
    1 1 ESD8011MUT5G ESD8011MUT5G

    CT103

    C1085
    D32 EMC@ D33 EMC@
    +VBUS1_PD_20V +VBUS1_PD_20V
    TBT_VBUS 2 2 TBT_USB3_RX1_N 1 2 TBT_USB3_TX1_N 1 2

    JUSBC1 PESD5V0C1BSF PESD5V0C1BSF


    A1 B12
    GND GND D34 EMC@ D35 EMC@
    TBT_USB3_TX1_P A2 B11 TBT_USB3_RX1_P
    <41> TBT_USB3_TX1_P TBT_USB3_TX1_N SSTXP1 SSRXP1 TBT_USB3_RX1_N TBT_USB3_RX1_P <41> TBT_USB3_RX1_P TBT_USB3_TX1_P
    ML3 EMC@ A3 B10 1 2 1 2
    TBT_A_USB2_T_P_R <41> TBT_USB3_TX1_N SSTXN1 SSRXN1 TBT_USB3_RX1_N <41>
    <43> TBT_A_USB2_T_P 1 2
    C178 1 2 A4 B9 2 1 C179
    0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K PESD5V0C1BSF PESD5V0C1BSF
    4 3 TBT_A_USB2_T_N_R TBT_A_CC2 A5 B8 TBT_A_SBU1
    <43> TBT_A_USB2_T_N <43> TBT_A_CC2 CC1 SUB2 TBT_A_SBU1 <43>
    D36 EMC@ D37 EMC@
    EXC24CH900U_4P TBT_A_I2C_B_P_R A6 B7 TBT_A_USB2_T_N_R
    TBT_A_I2C_B_N_R A7 DP1 DN2 B6 TBT_A_USB2_T_P_R TBT_A_USB2_T_P_R 1 2 TBT_A_I2C_B_N_R 1 2
    DN1 DP2

    Bottom
    C
    TBT_A_SBU2 A8 B5 TBT_A_CC1 C
    <43> TBT_A_SBU2 SUB1 CC2 TBT_A_CC1 <43>
    ESD8011MUT5G ESD8011MUT5G

    TOP
    C180 1 2 A9 B4 2 1 C181
    0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K D38 EMC@ D39 EMC@
    TBT_USB3_RX0_N A10 B3 TBT_USB3_TX0_N
    <41> TBT_USB3_RX0_N TBT_USB3_RX0_P SSRXN2 SSTXN2 TBT_USB3_TX0_P TBT_USB3_TX0_N <41> TBT_A_USB2_T_N_R TBT_A_I2C_B_P_R
    <41> TBT_USB3_RX0_P A11 B2 TBT_USB3_TX0_P <41> 1 2 1 2
    ML2 EMC@ SSRXP2 SSTXP2
    1 2 TBT_A_I2C_B_N_R A12 B1
    <43> TBT_A_I2C_B_N GND GND ESD8011MUT5G ESD8011MUT5G

    4 3 TBT_A_I2C_B_P_R 1 4
    <43> TBT_A_I2C_B_P GND GND
    EXC24CH900U_4P 2 3
    5 GND GND 6
    GND GND
    JAE_DX07SD24JJ3
    CONN@

    D40 EMC@ D41 EMC@


    JUSBC1 and JUSBC2 use SP060009R0L TBT_USB3_TX2_P TBT_USB3_RX2_P
    1 2 1 2

    PESD5V0C1BSF PESD5V0C1BSF
    +VBUS2_PD_20V
    D42 EMC@ D43 EMC@
    TBT_USB3_TX2_N 1 2 TBT_USB3_RX2_N 1 2

    10U_0603_25V6M

    0.1U_0402_25V6
    1 1

    CT104

    C1086
    PESD5V0C1BSF PESD5V0C1BSF
    +VBUS2_PD_20V +VBUS2_PD_20V
    2 2 D44 EMC@ D45 EMC@
    TBT_B_CC1 1 2 TBT_B_SBU2 1 2
    JUSBC2
    B B
    A1 B12
    GND GND ESD8011MUT5G ESD8011MUT5G
    TBT_USB3_TX3_P A2 B11 TBT_USB3_RX3_P
    <41> TBT_USB3_TX3_P TBT_USB3_TX3_N SSTXP1 SSRXP1 TBT_USB3_RX3_N TBT_USB3_RX3_P <41>
    ML5 EMC@ A3 B10 D46 EMC@ D47 EMC@
    TBT_B_USB2_T_P_R <41> TBT_USB3_TX3_N SSTXN1 SSRXN1 TBT_USB3_RX3_N <41>
    <44> TBT_B_USB2_T_P 1 2
    C182 1 2 A4 B9 2 1 C183 TBT_B_SBU1 1 2 TBT_B_CC2 1 2
    0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K
    4 3 TBT_B_USB2_T_N_R TBT_B_CC2 A5 B8 TBT_B_SBU1
    <44> TBT_B_USB2_T_N <44> TBT_B_CC2 CC1 SUB2 TBT_B_SBU1 <44>
    ESD8011MUT5G ESD8011MUT5G
    EXC24CH900U_4P TBT_B_I2C_B_P_R A6 B7 TBT_B_USB2_T_N_R
    TBT_B_I2C_B_N_R A7 DP1 DN2 B6 TBT_B_USB2_T_P_R D48 EMC@ D49 EMC@
    DN1 DP2
    Bottom

    TBT_B_SBU2 A8 B5 TBT_B_CC1 TBT_USB3_RX3_N 1 2 TBT_USB3_TX3_N 1 2


    <44> TBT_B_SBU2 SUB1 CC2 TBT_B_CC1 <44>
    TOP

    C184 1 2 A9 B4 2 1 C185
    0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K PESD5V0C1BSF PESD5V0C1BSF
    TBT_USB3_RX2_N A10 B3 TBT_USB3_TX2_N
    <41> TBT_USB3_RX2_N TBT_USB3_RX2_P SSRXN2 SSTXN2 TBT_USB3_TX2_P TBT_USB3_TX2_N <41>
    <41> TBT_USB3_RX2_P A11 B2 TBT_USB3_TX2_P <41> D50 EMC@ D51 EMC@
    ML4 EMC@ SSRXP2 SSTXP2
    1 2 TBT_B_I2C_B_N_R A12 B1 TBT_USB3_RX3_P 1 2 TBT_USB3_TX3_P 1 2
    <44> TBT_B_I2C_B_N GND GND

    4 3 TBT_B_I2C_B_P_R 1 4 PESD5V0C1BSF PESD5V0C1BSF


    <44> TBT_B_I2C_B_P GND GND
    EXC24CH900U_4P 2 3 D52 EMC@ D53 EMC@
    5 GND GND 6
    GND GND TBT_B_USB2_T_P_R 1 2 TBT_B_I2C_B_N_R 1 2
    JAE_DX07SD24JJ3
    CONN@
    ESD8011MUT5G ESD8011MUT5G

    D54 EMC@ D55 EMC@


    TBT_B_USB2_T_N_R 1 2 TBT_B_I2C_B_P_R 1 2

    ESD8011MUT5G ESD8011MUT5G
    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P46-PD USB TYPE-C TBT 1 & 2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 46 of 61
    5 4 3 2 1
    5 4 3 2 1

    +VBUS3_PD_20V

    1
    CT105

    Vinafix.com 2
    1U_0402_25V6K

    D D
    +VBUS3_PD_20V +VBUS3_PD_20V

    JUSBC3
    A1 B12
    GND GND
    EXC24CH900U_4P MUX_USB3_TX0_P A2 B11 MUX_USB3_RX0_P
    TOP_MUX_P_R <31> MUX_USB3_TX0_P MUX_USB3_TX0_N SSTXP1 SSRXP1 MUX_USB3_RX0_N MUX_USB3_RX0_P <31>
    <45> TOP_MUX_P 4 3 <31> MUX_USB3_TX0_N A3 B10 MUX_USB3_RX0_N <31>
    SSTXN1 SSRXN1
    C186 1 2 A4 B9 2 1 C187
    1 2 TOP_MUX_N_R 0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K
    <45> TOP_MUX_N MUX_C_CC1 MUX_C_SBU2
    A5 B8
    ML6 EMC@ <45> MUX_C_CC1 CC1 RFU2 MUX_C_SBU2 <31,45>
    TOP_MUX_P_R A6 B7 BOT_MUX_N_R
    TOP_MUX_N_R A7 DP1 DN2 B6 BOT_MUX_P_R
    DN1 DP2

    Bottom
    MUX_C_SBU1 A8 B5 MUX_C_CC2
    <31,45> MUX_C_SBU1 RFU1 CC2 MUX_C_CC2 <45>

    TOP
    C188 1 2 A9 B4 2 1 C189
    0.47U_0402_25V6K VBUS VBUS 0.47U_0402_25V6K
    ML7 EMC@ MUX_USB3_RX1_N A10 B3 MUX_USB3_TX1_N
    BOT_MUX_P_R <31> MUX_USB3_RX1_N MUX_USB3_RX1_P SSRXN2 SSTXN2 MUX_USB3_TX1_P MUX_USB3_TX1_N <31>
    1 2 A11 B2
    <45> BOT_MUX_P <31> MUX_USB3_RX1_P SSRXP2 SSTXP2 MUX_USB3_TX1_P <31>
    A12 B1
    4 3 BOT_MUX_N_R GND GND
    <45> BOT_MUX_N
    EXC24CH900U_4P 1 4
    GND GND
    2 3
    GND GND

    JAE_DX07SA24XJ2
    CONN@

    Use DC23300LM0L
    C C

    PVT_0017
    D56 EMC@ D57 EMC@
    MUX_USB3_TX0_P 1 2 MUX_USB3_RX0_P 1 2

    PESD5V0C1BSF PESD5V0C1BSF

    D58 EMC@ D59 EMC@


    MUX_USB3_TX0_N 1 2 MUX_USB3_RX0_N 1 2

    PESD5V0C1BSF PESD5V0C1BSF

    D60 EMC@ D61 EMC@


    MUX_C_CC1 1 2 MUX_C_SBU2 1 2

    ESD8011MUT5G ESD8011MUT5G

    D62 EMC@ D63 EMC@


    MUX_C_SBU1 1 2 MUX_C_CC2 1 2

    ESD8011MUT5G ESD8011MUT5G

    D64 EMC@ D65 EMC@


    MUX_USB3_RX1_N 1 2 MUX_USB3_TX1_N 1 2
    B B

    PESD5V0C1BSF PESD5V0C1BSF

    D66 EMC@ D67 EMC@


    MUX_USB3_RX1_P 1 2 MUX_USB3_TX1_P 1 2

    PESD5V0C1BSF PESD5V0C1BSF

    D68 EMC@ D69 EMC@


    TOP_MUX_P_R 1 2 BOT_MUX_N_R 1 2

    ESD8011MUT5G ESD8011MUT5G

    D70 EMC@ D71 EMC@


    TOP_MUX_N_R 1 2 BOT_MUX_P_R 1 2

    ESD8011MUT5G ESD8011MUT5G

    A A

    DELL CONFIDENTIAL/PROPRIETARY
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2015/12/16 Deciphered Date 2016/12/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P47-PD USB TYPE-C 3
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 47 of 61
    5 4 3 2 1
    5 4 3 2 1

    +3VALW: TDC 5.5A


    B+ (PU500: SY8286BRAC)

    Vinafix.com
    USB Type C x3
    D +5VALW: TDC 7.9A D

    (PU501: SY8288CRAC)

    +1.2V_DDR: TDC 4.1A


    (PU600: SY8210A)
    Power path

    +1.0V_A: TDC 2.6A


    (PU700: SY8286)
    CHARGER
    (PU300:ISL88738)
    2S Battery (buck- boost) +1.8VA:TDC 0.4A
    (PU800: TLV62150A)
    C C

    +1.8VU:TDC 0.46A
    (PU900: TLV62150A)
    Battery Low Detect

    +VCC_CORE:
    U22/U23:TDC 21A, U42: TDC 42A
    (PU1000: ISL95829A)

    +VCCGT:
    U22: TDC 31A, U23: TDC 64A, U42: TDC 28A
    (PU1000: ISL95829A)
    B B

    +VCCSA: TDC 5A
    (PU1000: ISL95829A)

    BOM Structure list +1.0VS_VCCIO: TDC 2.2A


    (PU1400: TPS62134ARGT)
    U22@ For U22 config component need POP
    U23@ For U23 config component need POP
    U42@ For U42 config component need POP +1.0V_PRIM_CORE: TDC 1.8A
    (PU1401T: PS62134DRGTR)
    EMC@ For EMC component need POP
    @EMC@ For EMC component need NC
    A
    +VCC_EDRAM: TDC 1.75A A

    +VCC_EOPIO: TDC 1.4A


    (PU1500/PU1501: TPS62134CRGTR)

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2015/12/10 Deciphered Date 2015/12/10 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    POWER BLOCK DIAGRAM
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 48 of 61
    5 4 3 2 1
    5 4 3 2 1

    Function feild：
    Power Path(37.1), EMC Part(47.1)

    S1b S3b
    PD108 PD110
    SE30AFB-M3-6A_SMA2 SE30AFB-M3-6A_SMA2

    Type C adapter input_1


    +VBUS1_PD_20V
    S1a
    2 1
    Type C adapter input_3
    +VBUS3_PD_20V
    S3a 2 1

    Pilot-003 Pilot-003
    +VBUS1_20V
    PQ100 PQ101 +CHG_VIN_20V +VBUS3_20V
    PQ153 PQ155
    AON7405_DFN8-5 AON7405_DFN8-5 AON7405_DFN8-5 AON7405_DFN8-5 +CHG_VIN_20V

    Vinafix.com
    @ PT101 @ PT106 @ PT107 EMC@ PL100 1 1 @ PT103 @ PT108 @ PT109 EMC@ PL104 1 1
    HCB2012KF-121T50_0805 2 2 HCB2012KF-121T50_0805 2 2
    PD1_LPS2 PD3_LPS2
    1 2 3 5 5 3 1 2 3 5 5 3

    1
    300K_0402_1%

    1
    S TR AO7401 1P SC70-3

    S TR AO7401 1P SC70-3
    300K_0402_1%

    300K_0402_1%
    2200P_0402_50V7K

    2200P_0402_50V7K

    1000P_0402_50V7K

    2200P_0402_50V7K
    0.1U_0402_25V6

    100P_0402_50V8J

    100P_0402_50V8J

    0.1U_0402_25V6

    0.1U_0402_25V6

    100P_0402_50V8J

    100P_0402_50V8J

    0.1U_0402_25V6
    0.01U_0402_25V7K

    0.01U_0402_25V7K
    S TR AO7401 1P SC70-3

    300K_0402_1%
    PR213

    4
    1

    S TR AO7401 1P SC70-3
    EMC@ PC100

    EMC@ PC103

    PC101

    EMC@ PC102

    EMC@ PC108

    EMC@ PC104

    PC105

    PC106

    PC107

    PR101

    EMC@ PC294

    EMC@ PC289

    PC284

    EMC@ PC292

    EMC@ PC290

    EMC@ PC288

    PC283

    PC293

    PC285

    PR269

    PR268
    1M_0402_1%

    1M_0402_1%
    1U_0603_25V6K

    10U_0603_25V6M

    2200P_0402_50V7K

    1000P_0402_50V7K

    1U_0603_25V6K

    10U_0603_25V6M

    PR264
    D D
    1

    1
    PC133

    @ PR218

    PC295
    499K_0402_1%

    499K_0402_1%
    0.22U_0402_25V6K

    0.22U_0402_25V6K
    499K_0402_1%

    499K_0402_1%
    3

    1
    S

    680P_0402_50V7K

    680P_0402_50V7K
    2

    3
    S S S
    2
    G

    PQ133

    PC109

    @ PC111

    PR103

    PC286

    @PC291

    PR261
    2

    PD3_LPS1 2

    2
    PR100

    PR263
    EMC@

    EMC@

    EMC@

    EMC@

    EMC@

    EMC@

    EMC@

    EMC@

    @
    PQ104
    G
    2 2
    G G
    2

    PQ158

    PQ150
    PD1_LPS1
    2

    2
    D

    2
    D D D

    1
    1

    1
    49.9K_0402_1%

    49.9K_0402_1%
    SB000006O00

    300K_0402_1%

    300K_0402_1%
    1

    1
    Use SB000004A0L footpin

    100K_0402_1%

    100K_0402_1%
    PR214

    PR262
    PR109

    PR107

    PR274

    PR273
    49.9K_0402_1%

    49.9K_0402_1%
    2

    2
    1

    1
    +3V_LDO +3V_LDO

    2
    PR106

    PR260
    PR215 PR276

    SB00000PV00

    SB00000PV00
    6

    6
    200K_0402_1% D 200K_0402_1% D
    Pilot-004

    L2N7002WT1G_SC70-3
    1 2 2 1 2 2

    PQ134A

    PQ151A
    @ PR114

    L2N7002WT1G_SC70-3
    +3V_LDO +3V_LDO

    1
    G D 0_0402_5% G @ PR267

    200K_0402_1%
    2

    2
    VBUS1_ECOK

    1
    2 1 2 D

    PQ108

    PR270
    @ PR259 0_0402_5%

    200K_0402_1%
    VBUS3_ECOK

    3
    2 1 2

    PQ157
    PR115
    0_0402_5% D

    SB00000PV00
    S G S

    1
    1 2 5

    PQ151B
    @ PR217
    SB00000PV00

    S G

    3
    <45> EN_PD_HV3
    3

    DMN66D0LDW-7_SOT363-6

    DMN66D0LDW-7_SOT363-6
    0_0402_5% D G
    Pilot-004 S

    6
    1 2 5
    PQ134B

    SB00000PV00

    SB00000PV00
    Pilot-004

    2
    <43> EN_PD_HV1

    6
    1 2 2

    PQ149A
    G D S

    4
    2 1 2

    PQ109A
    G
    PR178 G 1 2
    Pilot-004 S 1M_0402_1%
    4

    PR277
    1M_0402_1% S

    1
    1 2 PR266
    Pilot-004 S Pilot-004

    1
    1M_0402_1%

    DMN66D0LDW-7_SOT363-6
    PR228

    DMN66D0LDW-7_SOT363-6
    1M_0402_1% @ PR123 @ PR278

    3
    0_0402_5% D 0_0402_5% D

    SB00000PV00

    SB00000PV00
    AC1_DISC# AC3_DISC#
    1 2 5 1 2 5

    PQ109B

    PQ149B
    G G

    S S

    4
    PR176 PR272
    1M_0402_1% 1M_0402_1%
    1 2 1 2
    Pilot-004 PQ199
    Pilot-004
    @ PR108 L2N7002WT1G_SC70-3 @ PR122
    Pilot-004 PQ201
    Pilot-004

    1
    0_0402_5% 0_0402_5% D @ PR126 L2N7002WT1G_SC70-3 @ PR271

    1
    D
    S

    1 2 3 1 1 2 2 PQ106 0_0402_5% 0_0402_5%


    <38> DCIN1_EN

    D
    G L2N7002WT1G_SC70-3 1 2 3 1 1 2 2 PQ156
    <38> DCIN3_EN
    From EC S G L2N7002WT1G_SC70-3

    3
    1
    G

    From EC
    1000P_0402_50V7K

    S
    2

    3
    1

    1
    PR166

    @ PC136
    1M_0402_1%

    1000P_0402_50V7K
    1M_0402_1%
    2

    1
    @ PC287
    100K_0201_1%
    Pilot-004

    PR275
    1
    100K_0201_1%

    Pilot-004
    2
    1

    PR112
    0_0402_5%

    100K_0201_1%

    100K_0201_1%
    2

    2
    1

    1
    PR110

    @ PR111

    0_0402_5%

    2
    PR140

    @ PR137

    PR141
    2
    2

    2
    C +3VALW C
    +3V_LDO +3VALW
    +3V_LDO

    Pilot-004
    S2b Pilot-004 1
    @ PR192
    0_0402_5%
    2 AC_DIS#
    +3VALW

    1
    PD109 @ PR138 +3VALW

    200K_0402_1%
    6
    SE30AFB-M3-6A_SMA2 0_0402_5% D

    SB00000PV00

    PR175
    S2a 2 1 1 2 2

    PQ122A
    Type C adapter input_2 <38> VBUS1_ECOK G
    Pilot-004

    1
    @ PR208

    200K_0402_1%

    2
    +VBUS2_PD_20V S 0_0402_5%

    PR174
    1
    PQ113 PQ114 +3VALW 1 2
    +VBUS2_20V Pilot-004 Pilot-004 AC_DISC_OUT# <50>
    @ PT102
    EMC@ PL101 1
    AON7405_DFN8-5 AON7405_DFN8-5
    1
    +CHG_VIN_20V +3VALW @ PR230 @ PR202

    SB00000PV00
    2
    1

    6
    HCB2012KF-121T50_0805 2 2 0_0402_5% 0_0402_5% D

    200K_0402_1%

    Pilot-004
    PD2_LPS2 5 <38> AC_DISC# AC_DIS#
    1 2 3 5 3 1 2 1 2 2

    PQ129A
    PR142
    1

    1
    G

    0_0402_5%
    Pilot-004

    200K_0402_1%

    @ PR207
    PR124
    1

    1
    S TR AO7401 1P SC70-3
    @ PR209

    300K_0402_1%
    S
    0.1U_0402_25V6

    100P_0402_50V8J

    100P_0402_50V8J

    0.1U_0402_25V6

    300K_0402_1%

    1
    1

    S TR AO7401 1P SC70-3
    EMC@ PC120

    EMC@ PC122

    EMC@ PC116

    EMC@ PC114

    EMC@ PC117

    EMC@ PC119

    EMC@ PC118

    EMC@ PC121

    EMC@ PC115

    PR129

    @ PC140
    0_0402_5%
    2200P_0402_50V7K

    2200P_0402_50V7K

    1000P_0402_50V7K

    1U_0603_25V6K

    10U_0603_25V6M

    1000P_0402_50V7K
    0.01U_0402_25V7K

    PR220
    1

    1M_0402_1%

    1
    1 2
    PC134

    499K_0402_1%
    @PR219

    0.22U_0402_25V6K

    CHG_PROCHOT# <50>
    499K_0402_1%

    2
    1

    3
    D

    SB00000PV00
    Pilot-004
    680P_0402_50V7K
    3

    3
    S S
    5

    PQ127B
    PC123

    @PC124

    PR130

    @ PR206
    2

    PD2_LPS1 2

    2
    PR128

    3
    2
    G G
    2
    PQ135

    PQ115

    @ PR201 G D 0_0402_5% D

    SB00000PV00
    2

    6
    5 1 2 5

    PQ129B
    0_0402_5% D

    SB00000PV00
    2

    1 2 2

    PQ127A
    D D S G G
    1

    4
    <43,50> AC1_DISC# G
    S PQ122B
    Pilot-004 S

    4
    S SB00000PV00

    1
    1

    49.9K_0402_1%
    300K_0402_1%

    1
    100K_0402_1%
    PR221

    @ PR203
    PR134

    PR118
    0_0402_5%
    1 2
    49.9K_0402_1%
    2

    +3V_LDO
    Pilot-004
    2

    2
    PR133

    PR222
    Pilot-004
    6

    200K_0402_1% D @ PR170
    SB00000PV00

    L2N7002WT1G_SC70-3

    1 2 2
    PQ136A

    @ PR135 0_0402_5%
    +3V_LDO Pilot-004 AC_DIS#
    1

    G D 0_0402_5% 1 2
    200K_0402_1%
    2

    VBUS2_ECOK
    2 1 2
    PQ119

    PR139

    @ PR224 @ PR195
    Pilot-004
    3

    3
    0_0402_5% D 0_0402_5% D
    SB00000PV00

    SB00000PV00
    S G
    1

    EN_PD_HV2
    1 2 5 1 2 5
    PQ136B

    PQ128B
    S @ PR200
    3

    <44> EN_PD_HV2 <38> VBUS3_ECOK


    DMN66D0LDW-7_SOT363-6
    G 0_0402_5% G
    Pilot-004
    2

    AC_DIS#
    6

    D 1 2
    SB00000PV00

    1 2 2
    PQ121A

    @ PR145
    Pilot-004 S S
    4

    4
    6
    G 0_0402_5% D

    SB00000PV00
    1 2 PR179 VBUS2_ECOK
    1 2 2
    +3VALW

    PQ128A
    1M_0402_1% <38> VBUS2_ECOK
    S G
    1

    PR229
    B 1M_0402_1% Pilot-004 +3VALW B

    1
    S

    200K_0402_1%
    1
    +3VALW
    DMN66D0LDW-7_SOT363-6

    @ PR136

    PR173
    3

    0_0402_5% D +3VALW
    SB00000PV00

    AC2_DISC#

    1
    1 2 5
    PQ121B

    200K_0402_1%
    1
    G

    200K_0402_1%

    PR171

    2
    PR143
    1
    S

    200K_0402_1%
    4

    3
    PR177 D

    SB00000PV00
    Pilot-004

    PR127

    2
    5

    PQ117B
    1M_0402_1%

    2
    1 2 @ PR196 G

    6
    0_0402_5% D

    SB00000PV00
    2
    AC3_DISC#

    3
    1 2 2

    PQ117A
    D

    SB00000PV00
    Pilot-004 Pilot-004 Pilot-004 S

    4
    <45,50> AC3_DISC#
    5

    PQ120B
    PQ200 G
    @ PR117 L2N7002WT1G_SC70-3 @ PR132 @ PR144 G
    1

    6
    0_0402_5% 0_0402_5% D 0_0402_5% D

    SB00000PV00
    S

    1
    AC2_DISC#
    S

    1 2 3 1 1 2 2 1 2 2

    PQ120A
    PQ118 S

    4
    <38> DCIN2_EN <44,50> AC2_DISC#
    G L2N7002WT1G_SC70-3 G
    @ PR205
    From EC S
    3
    1

    0_0402_5%
    G

    1000P_0402_50V7K

    S
    1M_0402_1%
    2

    1
    1

    1 2
    @ PC137
    PR172
    Pilot-004

    @ PR204
    100K_0201_1%

    100K_0201_1%

    2
    1

    0_0402_5%
    0_0402_5%

    1 2
    PR119

    @ PR120

    PR121
    2

    +3VALW
    PQ123
    +3V_LDO S TR AO7401 1P SC70-3

    1 3

    S
    +3V_LDOP
    PR148
    1M_0402_1%

    G
    2
    1 2
    PD103

    10K_0402_1%
    1
    EMC@ PL105 RB751V-40_SOD323-2 PU101 PC125
    LDO_IN
    +BATT HCB2012KF-121T50_0805 +BAT_TABLET 2 1 1 5 0.01U_0402_16V7K

    PR150
    1 2 +VBUS1_20V VCC OUT +3V_LDOP 1 2
    2
    1U_0402_16V6K

    EMC@ PL102 GND

    2
    PQ124
    1

    HCB2012KF-121T50_0805 PD106 PC128 3 4 S TR AO7401 1P SC70-3


    PC129

    1 2 RB751V-40_SOD323-2 1U_0603_25V6K NC EN
    2 1 1 2 1 3 +3V_LDO

    S
    +VBUS2_20V +3VALW
    2

    DMN66D0LDW-7_SOT363-6
    EMC@ PL103 RT9069-33GB_SOT23-5
    HCB2012KF-121T50_0805
    1 2 PR155

    G
    2
    3
    PD107 PR149 D

    SB00000PV00
    100K_0402_1%
    5 1 2

    PQ125B
    RB751V-40_SOD323-2 300K_0402_5%
    1000P_0402_50V7K

    0.01U_0402_25V7K

    2 1 1 2
    @EMC@ PC126

    @EMC@ PC127

    G
    1M_0603_1%

    +VBUS3_20V
    1

    PR102

    Pilot-004
    1

    1
    S
    TVNST52302AB0_SOT523-3

    TVNST52302AB0_SOT523-3

    4
    1

    @EMC@ PC132 @ PR156


    2

    1U_0603_25V6K
    EMC@ PD104

    EMC@ PD105

    A 2200P_0402_50V7K 0_0402_5% A
    2

    300K_0402_5%

    1 2 PD111 D
    PR153

    ALW_PWRGD_3V_5V
    PC131

    RB751V-40_SOD323-2 2
    SMART

    6 2
    2 1 ALW_PWRGD_3V_5V <51>
    G @ PR151
    +CHG_VIN_20V
    2

    Battery: 14 S 0_0402_5% D
    2

    GND ALW_PWRGD_3V_5V
    12:BATT4+ 13
    GND
    @ PQ126 1 2 2 PQ125A
    12 DMN65D8LW-7_SOT323-3 G DMN66D0LDW-7_SOT363-6
    11:BATT3+ 12 11 PR152 100_0402_1% PBAT_SMBCLK SB00000PV00
    Pilot-004

    0.1U_0402_25V6
    10:BATT2+ 11 10 1 2 S

    1
    10 PBAT_CHARGER_SMBCLK <38,50>

    1
    09:BATT1+ 9

    PC130
    9 CLK_SMB
    08:CLK_SMB 8 PR154 100_0402_1%
    8 7 DAT_SMB 1 2
    07:DAT_SMB

    2
    7 6 BATT_PRS# PBAT_CHARGER_SMBDAT <38,50>
    06:BATT_PRS# 6 5 PR157 100_0402_1% PBAT_SMBDAT
    5
    05:SYS_PRES# 4
    4 1 2
    3 PBAT_PRES# <38,50>
    04:GND 4 3 2
    03:GND 3 2 1 PR158
    02:GND 2 1 100K_0402_1%
    01:GND 1 ACES_50278-01201-001 1 2
    CONN@ JT101 +3VALW
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DCIN/Power Path
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    Use LTCX007MM00 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date : Tuesday, October 17, 2017 Sheet 49 of 61
    5 4 3 2 1
    A B C D

    Charger controller(40.1), Support component(40.2)

    @ PT100
    +CHG_VIN_20V
    1
    Vinafix.com PR300
    0.02_1206_1%
    EMC@ PL302
    1UH_MMD-04BZ-1R0M-V1_3.75A_20%
    +CHG_SRC_20V
    1

    1 4 1 2

    2200P_0402_50V7K
    4.3V 2 3

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    @EMC@ PC303
    0.1U_0402_25V6

    0.1U_0402_25V6

    PC306
    1

    1
    442K_0402_1%

    @PC301

    1
    PR305

    PC304

    PC305

    PC307

    @ PC310

    PC302

    PC308

    PC309
    2

    @EMC@
    2

    2
    1

    1
    2

    3.3_0402_1%

    3.3_0402_1%
    PR302

    PR301
    CHG_ACIN

    2
    PC312
    4.7U_0603_25V6K

    1U_0402_25V6K

    1U_0402_25V6K
    1 2

    1
    100K_0402_1%
    0.1U_0402_25V6
    1

    1
    PC331
    B+

    PR307

    PC313

    PC314
    2

    2
    2
    top

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    2200P_0402_50V7K
    @EMC@ PC321

    @EMC@ PC329
    0.1U_0402_25V6
    1

    1
    PC317

    PC319

    @ PC324

    @ PC325

    @ PC326

    PC315

    PC316

    PC318

    PC320
    0.22U_0603_25V7K
    1
    2.2_0603_5%

    2
    1
    PC330
    PR306
    PR303

    2
    2_1206_5%

    2
    2 2
    1 2
    +CHG_VIN_20V

    1U_0603_25V6K
    1
    PC332

    CHG_ADP

    CHG_CSIP

    CHG_CSIN

    CHG_BST1

    CHG_UG1

    CHG_LX1

    CHG_LG1

    CHG_UG2
    PD300 PC333

    CHG_UG1
    2
    RB751V-40_SOD323-2 1U_0603_25V6K

    AON6992_DFN5X6D-8-7

    AON6992_DFN5X6D-8-7
    2 1 1 2 PR308
    +CHG_VIN_20V 4.7_0402_5%

    16

    15

    14

    13

    12

    11

    10

    33
    9
    PD301 PR309 1 2 VDD

    PQ302

    PQ307
    RB751V-40_SOD323-2 2_1206_5% 5V

    ADP

    CSIP

    ASGATE

    BOOT1

    UGATE1

    PHASE1

    LGATE1
    CSIN

    PAD
    B+
    2 1 1 2 PC334
    6.6 * 7.3 *3 +BAT_TABLET

    2
    1U_0402_6.3V6K
    PC335 CHG_DCIN 17 8 CHG_VDDP 1 2 PL301

    D1

    G1

    G1

    D1
    VDD DCIN VDDP
    1U_0402_6.3V6K 2.2UH_MHCB06030-2R2M-C1L_10A_20%
    1 2 18 PU300 7 CHG_LG2 PR304 PQ304
    5V VDD LGATE2 7 CHG_LX1 1 2 CHG_LX2 7
    ISL88738HRTZ-T_TQFN32_4X4 .01_2512_1% AON7405_DFN8-5
    Pilot-004 CHG_ACIN 19 6 CHG_LX2 1
    PR311
    2 D2/S1 D2/S1 1 2 +8.4V_BATT+ 1
    ACIN PHASE2 2
    CHG_CMIN 20 CHG_UG2 2.2_0603_5%
    @ PR334 1 2 0_0402_5% 5 SD036100D80 3 5

    G2

    G2
    S2

    S2

    S2

    S2

    S2

    S2
    OTGEN/CMIN UGATE2

    10U_0603_25V6M
    CHG_MCP23017_SMBDAT PC336

    1
    CHG_DAT 21 CHG_BST2

    10U_0603_25V6M
    @EMC@ PR316
    4.7_1206_5%

    @EMC@ PR317
    4.7_1206_5%
    @ PR313 1 2 0_0402_5% 4 1 2

    3
    <38,49> PBAT_CHARGER_SMBDAT SDA BOOT2

    1
    PC323
    Change part number to

    4
    CHG_CLK 22

    PC322
    @ PR314 1 2 0_0402_5% SA00009VW0L 3 0.22U_0603_25V7K
    <38,49> PBAT_CHARGER_SMBCLK SCL VSYS

    2200P_0402_50V7K
    CHG_LG2

    4700P_0402_25V7K
    OTGPG/CMOUT

    1
    CHG_MCP23017_SMBCLK PR315 1 2 75_0402_5% 23 2 CHG_CSOP @ PR318

    PC340
    CHG_LG1

    1 SNUB_CHG1 2

    1 SNUB_CHG2 2
    AMON/BMON

    PROCHOT# CSOP

    1
    <15,38,56> H_PROCHOT#

    CHG_BGATE
    0_0402_5%

    PC339
    BATGONE

    24 1 1 2 B+

    2
    <49> CHG_PROCHOT# ACOK CSON

    CHG_CSON
    BGATE

    2
    CMOP
    PROG

    PSYS

    VBAT

    VDD Pilot-004

    680P_0402_50V7K

    680P_0402_50V7K
    0.1U_0402_25V6
    1

    1
    @EMC@ PC343
    @ PC341

    @EMC@ PC342

    2.2_0402_1%
    25

    26

    27

    28

    29

    30
    CHG_VBAT1 31

    32
    1

    2.2_0402_1%
    PR323
    PR319 PR325

    PR324
    2
    CHG_BGATE
    CHG_PSYS
    CHG_AMON

    100K_0402_1% 100K_0402_1%

    2
    3
    1 2 3

    2
    <38,49> PBAT_PRES#
    PQ300
    2

    2
    ACAV_IN1 L2N7002WT1G_SC70-3 2-CELL
    1

    PC352
    10P_0402_50V8J

    @ PR326
    1M_0402_1% PC345 PC346 PC347
    1

    D 1U_0402_25V6K 1U_0402_25V6K
    4.7U_0603_25V6K
    2

    93.1K_0402_1%

    2 PR320 1 2 1 2 1 2
    2

    <38> AC_DIS G 154K_0402_1%


    1

    PR322

    S
    3

    PR340
    2

    1M_0402_1%
    Pilot-004
    Pilot-004
    1

    0_0402_5%

    @ PR332
    2

    @ PR329

    0_0402_5%
    2

    1 2
    <49> AC_DISC_OUT#
    2

    @ PT104 CHG_COMP
    P_SYS
    0.01U_0402_16V7K 499_0402_1%

    560P_0402_50V7K
    1

    @ PC348

    Pilot-004
    1

    1
    100K_0402_1%

    10K_0402_5%
    PR327

    @ PR333

    +3V_LDO
    1

    PR328 PR330
    PR336

    @ PR321 PD305 @ PT105 1K_0402_1% 100_0402_1%


    2

    0_0402_5% BAT54CW_SOT323-3 1 2 +BAT_TABLET


    2

    1 2 2
    2

    <43,49> AC1_DISC#
    2

    @ PR343 1
    0_0402_5% @ PC351
    0.1U_0402_25V6

    1 2 3 0.1U_0402_25V6
    Pilot-004

    2
    1

    <44,49> AC2_DISC#
    0_0402_5%

    0_0402_5%
    PC337

    0.1U_0402_25V6
    PC349

    @ PR342

    @ PR341
    PC350

    @ PR344 PD306
    2

    0_0402_5% BAT54CW_SOT323-3
    2

    1 2 2
    2

    <45,49> AC3_DISC#
    1
    4
    Pilot-004 4
    5

    3
    1
    1M_0402_1%

    @ PR345
    VCC

    <38> I_BATT
    @ PR335

    1 0_0402_5%
    IN1 4 1 2
    OUT ACAV_IN <38>
    2
    GND

    IN2 <38> I_ADP


    100K_0402_1%
    2

    1
    0_0402_5%
    @ PR346

    PR331

    PU301
    3

    MC74VHC1G08DFT2G_SC70-5 <38,56> I_SYS


    Pilot-004 Security Classification Compal Secret Data Compal Electronics, Inc.
    ACAV_IN1 1

    Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR_Charger (ISL88738)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 50 of 61
    A B C D
    5 4 3 2 1

    @ PJP500
    JUMP_43X118
    1 2
    EMC@ PL500 PU500 PR500 PC504 +3VALWP 1 2 +3VALW
    HCB2012KF-121T50_0805 SY8286BRAC_QFN20_3X3 0_0402_5% 0.1U_0603_25V7K
    1 2 B+_3V BST_3V 1 2 1 2
    B+

    2200P_0402_50V7K

    10U_0603_25V6M

    10U_0603_25V6M
    0.1U_0402_25V6
    3VALWP

    1
    Vinafix.com

    EMC@ PC500

    EMC@ PC501

    PC502

    PC503
    TDC 5.2A

    IN

    IN

    IN

    IN

    BS
    D D
    Peak Current 7.5A

    2
    LX_3V 6 20 PL501
    LX LX
    7 19 LX_3V
    1.5UH_MMD-05CZN1R5M-V1L_7.2A_20%
    1 2
    OCP Current 8.0A (fix)
    GND LX
    5.5 * 5.2 * 3 +3VALWP
    8 18 3.3V LDO
    GND GND
    150mA~300mA

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    1
    9 17

    @EMC@ PR501
    4.7_1206_5%
    +3VLP

    1
    PG LDO

    PC505

    PC506

    PC507

    PC508

    PC526
    1
    10 16
    Non AR

    2
    NC NC PC509

    OUT
    EN2

    EN1
    21 3VALWP

    NC
    4.7U_0603_6.3V6M

    FF

    2
    GND
    TDC 5.5A

    1 3V_SN 2
    PR502

    11

    12

    13

    14

    15
    100K_0402_5%
    1 2
    Peak Current 7.5A
    +3VALWP OCP Current 8.0A (fix)

    680P_0603_50V7K
    Vout is 3.37V

    @EMC@ PC510
    ENLDO_3V5V
    Fsw=600KHz
    <49> ALW _PW RGD_3V_5V

    2
    Check pull up resistor of
    @ PR503 PC511 PR504
    C SPOK at HW side 0_0402_5% 1000P_0402_25V8J 1K_0402_5%
    C

    1 2 3V_FB 1 2 1 2
    <38,51> ALW ON

    @ PJP501
    Pilot-004 JUMP_43X118
    1 2
    +5VALWP 1 2 +5VALW

    EMC@ PL502 PR505 PC512


    HCB2012KF-121T50_0805 PU501 0_0402_5% 0.1U_0603_25V7K
    1 2 B+_5V SY8288CRAC_QFN20_3X3 BST_5V 1 2 1 2 5VALWP
    B+ TDC 7.9A
    EMC@ PL503
    HCB2012KF-121T50_0805 Peak Current 11.0A
    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    2200P_0402_50V7K
    0.1U_0402_25V6

    1 2 OCP Current 13.0A


    1

    1
    EMC@ PC513

    EMC@ PC514

    PC515

    PC516

    PC528

    PC529

    IN

    IN

    IN

    IN

    BS
    2

    LX_5V 6 20 PL504
    LX LX 1.5UH_PCMC063T-1R5MN_9A_20%
    7 19 LX_5V 1 2
    B
    GND LX +5VALWP B
    8 18 7 X 7 X 3
    GND GND PC517

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    1
    ALW _PW RGD_3V_5V 1 2 9 17 1 2

    @EMC@ PR507
    4.7_1206_5%
    1
    PG VCC

    PC518

    PC519

    PC520

    PC521

    PC522

    PC527
    @ PR506 10 16

    2
    0_0402_5% NC NC 4.7U_0603_6.3V6M
    OUT

    LDO
    EN2

    EN1

    PR508 21
    FF

    499K_0402_1% GND

    5V_SN 2
    1 2 ENLDO_3V5V
    B+
    11

    12

    13

    14

    15

    VL
    5V LDO 150mA~300mA

    680P_0603_50V7K
    Vout 5.1V
    1

    @EMC@ PC524
    ENLDO_3V5V

    PC523
    Fsw=600KHz

    1
    PR509 4.7U_0603_6.3V6M
    499K_0402_1%
    Pilot-004
    2

    @ PR512
    2

    2
    0_0603_5%
    1 2

    @ PR510 PC525 PR511


    0_0402_5% 1000P_0402_25V8J 1K_0402_5%
    1 2 5V_FB 1 2 1 2
    <38,51> ALW ON

    A Pilot-004 A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    3V/5V controller(35.1), Support component(35.2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +3VALW_+5VALW
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 51 of 61
    5 4 3 2 1
    5 4 3 2 1

    @ PR600
    100K_0402_5%
    EMC@ PL600 1 2
    HCB2012KF-121T50_0805 +3VS
    1 2 @ PR601
    B+ 100K_0402_5%
    Vinafix.com

    2200P_0402_25V7K
    10U_0603_25V6M

    10U_0603_25V6M

    EMC@ PC602

    EMC@ PC603
    0.1U_0402_25V6
    1 2
    +3VS

    1
    PC600

    PC601
    PU600
    D D
    +3VALW
    10 19 1.2V_DDR_OT @EMC@ PR602 @EMC@ PC604

    2
    IN OT 4.7_0603_5% 680P_0402_50V7K
    1.2V_DDR_PG
    13
    BYP PG
    18
    PC605 .1U_0402_16V7K PR612
    1 2 1 2
    +1.2V_DDRP

    1U_0402_6.3V6K
    14 12 1 2 1 2 PL601
    VCC BS 0_0603_5% 1UH_MMD-05CZ-1R0M-M7L_7A_20%

    1
    LX_DDR

    PC606

    2.2U_0402_6.3V6M
    PC607
    4 11 1 2
    VTTGND LX
    +3VALW 5 X 5 X 3

    330P_0402_50V7K
    9 16
    R1

    2
    PGND FB

    1
    100K_0402_1%
    1
    +1.2V_DDRP

    PC609

    PR603
    15 8 PC608
    SGND VDDQSNS

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1 22U_0603_6.3V6M
    7 1 2

    2
    VLDOIN

    1
    PC610

    PC611

    PC612

    PC613
    @ PR604

    2
    0_0402_5% ILMT_DDR 17 6
    ILMT VTT +0.6VSP

    2
    1 5
    2

    S5 VTTSNS

    1
    ILMT_DDR

    100K_0402_1%
    R2

    PR605
    2 3
    S3 VTTREF

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    1
    1U_0402_10V6K
    PC614
    Pilot-004

    PC615

    PC616
    @ PR606 SY8210AQVC_QFN19_4X3

    EN_1.2V

    2
    0_0402_5%

    2
    C C

    EN_0.6V
    2

    The current limit is set to 8A, 12A or 16A when VFB=0.6V


    this pin is pull low, floating or pull high
    +1.2V_DDR OCP set 8A @ PR607
    Vout=0.6V* (1+R1/R2)
    0_0402_5%
    1 2
    Vout=1.2V
    <36,54,55> SUS_ON_P
    0.1U_0402_10V7K

    Fsw=600KHz
    1

    1
    1M_0402_1%

    @ PC617

    Pilot-004
    PR608

    2
    2

    Pilot-004
    @ PR609
    0_0402_5%
    1 2
    <8> SM_PG_CTRL +1.2V_DDRP +1.2V_DDR +0.6VSP +0.6VS
    0.1U_0402_10V7K

    B B
    1
    1M_0402_1%

    @ PJP600 @ PJP601
    1
    PR610

    @ PC618

    @ PR611 JUMP_43X118 JUMP_43X39


    0_0402_5% 1 2 1 2
    1 2 1 2 1 2
    <33,34,36,55> RUN_ON_P
    2
    2

    +1.2V_DDR 0.6Volt +/- 5%


    TDC 4.1A TDC 0.4A
    Mode S3 S5 VOUT VTT Peak Current 5.8A Peak Current 0.6A
    Normal H H on on
    Stadby L H on off OCP Current 8A OCP Current 2A (fix)
    Shutdown L L off off

    Note: S3 - sleep ; S5 - power off


    DDR controller(35.3), Support component(35.4)

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +1.2V_DDR/0.6VS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 52 of 61
    5 4 3 2 1
    5 4 3 2 1

    +1.0VA
    TDC 2.6A
    D Peak Current 3.3A D

    Vinafix.com OCP current 6.0A

    @ PJP700
    JUMP_43X79
    7.2*1/.9/9=0.89A +1.0VAP 1
    1 2
    2 +1.0VA
    @EMC@ PR700 @EMC@ PC700
    4.7_1206_5% 680P_0603_50V7K
    1 2 SNUB_1.0V 1 2
    EMC@ PL700 PU700
    HCB2012KF-121T50_0805 SY8286RAC_QFN20_3X3
    B+_1.0V
    B+ 1 2 2
    IN PG
    9
    BST_1.0V
    PR701
    0_0402_5%
    BST_1.0V_R
    PC703
    0.1U_0201_10V6K
    3 1 1 2 1 2 PL701

    2200P_0402_50V7K

    0.1U_0402_25V6
    IN BS 1UH_MMD-05CZ-1R0M-M7L_7A_20%

    EMC@ PC701

    @EMC@ PC702

    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    LX_1.0V
    4 6 1 2
    +1.0VAP

    PC704

    @ PC705
    C IN LX C

    5 19 5 X 5 X 3

    14K_0402_1%

    330P_0402_50V7K

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    2
    IN LX

    1
    7 20

    PR702

    PC706

    PC707

    PC708

    PC709

    PC710
    GND LX
    8 14 FB_1.0V R1
    Pilot-004

    2
    GND FB

    2
    @ PR703 18 17 LDO_1.0V 3V
    0_0402_5% GND VCC
    1 2 EN_1.0V 11 10
    EN NC

    1
    <12,33,36,38,54,60> SIO_SLP_SUS#
    FB=0.6V

    1
    ILMT_1.0V 13 12 PC711
    ILMT NC
    1

    @ PC712 2.2U_0402_6.3V6M

    2
    PR704 15 16 PR705
    1M_0402_1%
    0.1U_0402_25V6 +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
    +3VALW
    2

    footprint 21 =0.6*(1+(14/20))

    2
    PAD
    2

    SY8286RAC_QFN20_3X3
    Vout=1.02V

    1
    PC713
    1

    1U_0402_6.3V6K
    @ PR706

    2
    0_0402_5%
    EN :H>0.8V ; L<0.4V
    B B
    2

    EN pin don't floating


    If have pull down resistor at HW side,
    please delete PR604. Pilot-004
    1

    @ PR707
    0_0402_5%
    2

    The current limit is set to 6A, 9A or 12A when this pin


    is pull low, floating or pull high.

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    1.05V controller(35.5), Support component(35.6) Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +1VALW (SY8288)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 53 of 61
    5 4 3 2 1
    A B C D

    1
    Vinafix.com 1

    @ PR800

    <36,52,55> SUS_ON_P
    0_0402_5%
    1 2 +1.8VAP
    @ PR801
    0_0402_5%
    1 2
    <12,33,36,38,53,60> SIO_SLP_SUS#

    0.1U_0402_25V6
    Pilot-004

    EN_1.8VA
    1
    @ PC800

    2
    @ PJP800
    B+=NVDC 2S +1.8VAP 1 2
    +1.8VA

    13

    14

    15

    16

    17
    1 2
    3.2 * 2.5 *1.2 JUMP_43X39

    EN

    PGND

    PGND
    VOS

    TP
    EMC@ PL800 PL801
    HCB1608KF-121T30_0603 2.2UH_HEI322512A-2R2M-Q8_2.7A_20%
    SW_1.8VA
    +1.8VAP
    2 2
    1 2 12 1 1 2
    B+ PVIN SW

    412K_0402_1%

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    22P_0402_50V8J
    1

    1
    PR802

    PC801

    PC802

    PC809
    11 2
    2200P_0402_50V7K

    PVIN SW
    10U_0603_25V6M

    10U_0603_25V6M
    0.1U_0402_25V6

    Rup
    1

    1
    EMC@ PC803

    PC805

    PC808

    PU800
    EMC@PC804

    2
    TLV62150ARGTR_QFN16_3X3

    2
    10 footprint 3
    2

    AVIN SW
    TLV62150RGTR_QFN16_3X3-S

    1
    +1.8VA

    1
    SS_1.8VA 9 4 1.8VA_PWROK
    SS/TR PG Rdown TDC 0.4A
    3300P_0402_50V7-K

    @EMC@ PR803
    4.7_0603_5% PR804
    1

    Peak Current 0.6A

    AGND

    100K_0402_5%
    324K_0402_1%

    FSW
    PC806

    DEF

    2
    1
    OCP setting 1.4A(Fix)

    FB

    2
    @ PR805
    2

    Pilot-004 6

    1
    @EMC@ PC807
    680P_0402_50V7K

    2
    VFB=0.8V

    2
    1
    0_0402_5%

    FB_1.8VA
    @ PR806

    3 Fsw=1.25MHz @ Fsw net to 3V Vout=0.8V* (1+Rup/Rdown) 3

    Css=Tss*(2.5uA/1.25V) (F) +3VS Vout=1.817V


    Tss=1.65mS
    2

    Fsw=1.25MHz
    +1.8VAP

    1.8VA_PWROK
    1.8VS controller(35.15), Support component(35.16) 1.8VA_PWROK <38>

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +1.8VS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 54 of 61
    A B C D
    A B C D

    Vinafix.com
    1 1

    Pilot-004
    @ PR900

    <36,52,54> SUS_ON_P
    0_0402_5%
    1 2 +1.8VUP
    @ PR901
    0_0402_5%
    1 2
    <33,34,36,52> RUN_ON_P

    0.1U_0402_25V6

    EN_1.8VU
    1
    @ PC900

    2
    @ PJP900
    B+=NVDC 2S +1.8VUP 1 2
    +1.8VU

    13

    14

    15

    16

    17
    1 2
    2
    3.2 * 2.5 *1.2 JUMP_43X39 2

    EN

    VOS

    PGND

    PGND

    TP
    EMC@ PL900 PL901
    HCB1608KF-121T30_0603 2.2UH_HEI322512A-2R2M-Q8_2.7A_20%
    SW _1.8VU
    B+ 1 2 12
    PVIN SW
    1 1 2
    +1.8VUP

    412K_0402_1%

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1

    22P_0402_50V8J
    1

    1
    2200P_0402_50V7K

    PR902

    PC902

    PC908
    11 2
    10U_0805_25V6K

    PVIN SW
    0.1U_0402_25V6

    PC901
    Rup
    1

    1
    EMC@ PC903

    PC905

    PU900
    PC904

    2
    TLV62150ARGTR_QFN16_3X3

    2
    10 footprint 3
    2

    AVIN SW
    EMC@

    TLV62150RGTR_QFN16_3X3-S
    +1.8VU

    1
    SS_1.8VU 9 4 1.8VU_PW ROK @EMC@ PR903 TDC 0.46A
    SS/TR PG 4.7_0805_5%
    Rdown
    3300P_0402_50V7-K

    Peak Current 0.66A

    1
    100K_0402_5%
    PR904
    1

    AGND
    324K_0402_1% OCP setting 1.4A(Fix)

    FSW
    DEF

    2
    PC906

    @ PR905
    FB

    2
    2

    Pilot-004 6

    1
    @EMC@ PC907
    680P_0402_50V7K

    0_0402_5%
    VFB=0.8V

    2
    1
    @ PR906

    FB_1.8VU
    Fsw=1.25MHz @ Fsw net to 3V Vout=0.8V* (1+Rup/Rdown)
    Css=Tss*(2.5uA/1.25V) (F) 2
    +3VS Vout=1.817V
    Tss=1.65mS Fsw=1.25MHz
    3 3

    +1.8VUP

    1.8VU controller(35.17), Support component(35.18)

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P52-PWR_+1.8VU
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 55 of 61
    A B C D
    5 4 3 2 1

    +1.0V_VCCST +5VS Vcore_B+


    +VCCST

    PR1000 Pilot-004
    8.25K_0402_1%

    1
    1 2

    0.1U_0402_10V7K

    1_0402_5%
    @ PR1002

    PR1001
    PC1001
    0_0402_5% PC1002

    45.3_0402_1%
    PC1000

    100_0402_1%
    4700P_0402_25V7K

    2
    1

    1
    PR1006 U23@ 1 2

    PR1003

    PR1004
    1U_0402_16V6K

    2
    Vinafix.com
    1 2
    D U22@ D
    PR1006

    2
    93.1K_0402_1% PR1005
    SD034887280 1 2 10_0402_1% 1 2
    88.7K_0402_1% <16> VR_SVID_DATA 1 2 VR_SVID_DATA_C PR1015
    @ PR1007 Pilot-004 PC1003 ICCMAX of IA
    70A for U42
    0_0402_5% 0.22U_0603_16V7K 33A for U22 & U23e
    PR1006 U42@ PC1004 PH1000 <16> VR_SVID_ALERT#
    1 2VR_SVID_ALERT#_C
    330P_0402_50V7K 470K_0402_5%_ TSM0B474J4702RE NTC of GT at 100 deg
    1 2 1 2 <16> VR_SVID_CLK 1 2VR_SVID_CLK_C
    PR1008 49.9_0402_1%
    PR1010 PR1011
    27.4K_0402_1% 10.2K_0402_1% <15,38,50> H_PROCHOT#
    1 2
    SD034931280 1 2 1 2 PR1009 100_0402_1%
    93.1K_0402_1%
    PC1005 +3VS PR1012

    1
    34K_0402_1%
    165K_0402_1%

    150K_0402_1%
    1000P_0402_50V7K 1.91K_0402_1%
    1 2 1 2

    PR1013

    PR1014

    PR1015
    PC1006 PR1016
    47P_0402_50V8J @ PR1017 110K_0402_1%
    1 2 0_0402_5%

    2
    1 2
    U22@ PC1008 PR1019 <12> IMVP_VR_PG OCP of SA at 10A
    820P_0402_25V7 2K_0402_1% @ PR1020 PR1021
    1 2 1 2 1 2 1 2 0_0402_5% 665_0402_1% RC Match of SA
    <36,39> IMVP_VR_ON 1 2 PR1014 1 2 ISUMN_SA <58>
    PR1018 FB to GND of GT ICCMAX of GT
    PC1007

    1
    VR_ON 70A for U23e
    PC1008 U42@ 8200P_0402_25V7K 3.6K_0402_1%
    Pilot-004 PU1000
    33A for U22 & U42
    PC1010 PR1024 PH1001

    0.01UF_0402_25V7K
    PC1009 PR1022 <38,50> I_SYS ISL95829AHRTZ-T_TQFN48_6X6 2200P_0402_50V7K 1K_0402_1% 10K_0402_5%_B25/50 4250K
    680P_0402_50V7K 1K_0402_1% PR1023 PR1023

    48
    47
    46
    45
    44
    43
    42
    41
    40
    39
    38
    37

    0.033U_0402_16V7K

    11K_0402_1%
    1
    1 2 1 2 P_SYS 34K_0402_1% ICCMAX of SA is 7A 1 2 1 2

    2
    1

    1
    1 2

    PC1012

    PC1013

    PR1025
    VCC
    VIN
    VR_HOT#

    ALERT#

    PROG1
    PROG2
    PROG3
    PROG4
    VR_ENABLE
    VR_READY

    SCLK

    SDA
    SE000008980 PR1027 U23@ PR1027 U42@ U22@

    1
    820P_0402_25V7 PR1027 PWM_SA <58> PC1011

    1
    1.91K_0402_1% .1U_0402_16V7K

    2
    PC1008 U23@ <17> VCCGT_SENSE 1 2 FCCM_SA <58> PR1026

    2
    C 1 36 2.61K_0402_1% C
    Droop of GT at 2.65mV/A 2 PSYS PROG5 35
    <17> VSSGT_SENSE IMON_B PWM_C
    SD034255180 SD000009O80 3 34

    2
    NTC_B FCCM_C
    1

    2.55K_0402_1% 1.91K_0402_1% 4 33
    5 COMP_B ISUMN_C 32
    PC1014 FB_B ISUMP_C ISUMP_SA <58>
    SE074681K80 0.01UF_0402_25V7K 6 31
    VSSSA_SENSE <18>
    2

    7 RTN_B RTN_C 30 1 2 1 2
    680P_0402_50V7K ISUMP_B FB_C VCCSA_SENSE <18>
    8 29
    ISUMN_B COMP_C

    1
    9 28 PR1028 PC1015
    10 ISEN1_B IMON_C 27 316_0402_1% 470P_0402_50V7K Comp of SA
    <57,58> ISUMP_GT ISEN2_B PWM3_A
    PC1016
    11 26

    2.43K_0402_1%
    PWM3_VCORE 0.01UF_0402_25V7K

    2K_0402_1%

    2
    FCCM_B PWM2_A

    1
    12 25 1 2
    PWM1_B PWM1_A
    1
    2.61K_0402_1%

    PR1032

    @ PR1033
    Cn of GT PWM2_VCORE <57>
    IMON of SA PR1029
    PR1030

    0.047U_0402_25V7K

    0.047U_0402_25V7K
    10K_0402_5%_B25/50 4250K

    330P_0402_50V7K
    PC1018 U23@ PC1018 U42@ U22@ 1.69K_0402_1%

    ISUMN_A
    ISUMP_A
    PWM2_B

    COMP_A

    ISEN1_A
    ISEN2_A
    ISEN3_A
    FCCM_A
    1

    IMON_A
    49 set the LL of SA at 10.3mV/A

    68P_0402_50V8J
    PR1034

    NTC_A

    RTN_A

    2
    11K_0402_1%

    EP
    1

    1
    +5VS PWM1_VCORE <57>

    115K_0402_1%
    FB_A
    PC1018

    PC1017

    PR1035

    PC1020
    2

    1
    PC1021
    PR1031 PC1019

    8200P_0402_25V7K

    680P_0402_50V7K
    1K_0402_1% 2200P_0402_50V7K FCCM_VCORE <57>
    2

    2
    1

    1 2 1 2
    2

    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24

    2
    1

    1
    PH1002

    @ PC1022
    SE102104K00 SE00000MJ00

    PC1023
    2
    0.1U_0402_10V7K 0.047U_0402_25V7K U22@ PR1050 U23@
    U22@ PR1048 PR1048 U42@

    2
    PR1036 0_0402_5%
    2

    360_0402_1% PC1031 U23@ PC1031 U42@


    Pilot-004

    2
    1 2
    <57,58> ISUMN_GT
    1 2
    OCP of GT at 66.71A 0_0402_5% @ PR1049
    +5VS SD028000080
    .1U_0402_16V7K

    PR1036 U23@ PR1036 U42@ SD028000080 0_0402_5%


    PC1024
    1

    U23@ PC1026 0_0402_5% U22@ Comp of SA


    0.022U_0402_25V7K 1 2 SE00000MJ00 SE076333K80
    ISEN2_GT <57,58>
    1 2 0_0402_5% PR1050 U42@ 0.047U_0402_25V7K 0.033U_0402_16V7K
    2

    1 2

    SD034442080 SD034360080 PC1027 0.022U_0402_25V7K ISUMN_VCORE <57>


    442_0402_1% 360_0402_1% U23@ PC1029 <57> ISEN2_VCORE
    0.022U_0402_25V7K ISEN1_GT <57,58> 1 2 Cn of IA

    1
    .1U_0402_16V7K
    B 1 2 B

    1
    U22@ PC1028 0.022U_0402_25V7K PH1003

    PC1030

    0.047U_0402_25V7K

    0.047U_0402_25V7K
    <57,58> FCCM_GT PR1037 383_0402_1%<57> ISEN1_VCORE U42@ 10K_0402_5%_B25/50 4250K

    11K_0402_1%
    1
    1 2

    1
    U22@

    U22@
    PC1031

    PC1032

    PR1038
    <58> PWM1_GT

    2
    OCP of Vcore at 83.2A
    <57> PWM2_GT 1 2 1 2

    1
    2
    PC1033 PR1039 PR1040
    2200P_0402_50V7K 1K_0402_1% 5.49K_0402_1%
    DVT2-006 RC Comp of IA

    2
    ISUMP_VCORE <57>
    NTC of CORE at 100 deg
    VSS_SENSE <16>
    PR1041
    10.2K_0402_1% 1 2 1 2 VCC_SENSE <16>
    1 2 PC1032 U23@

    1
    U22@ PR1042 Comp of IAU22@ PC1034 PC1036
    316_0402_1% 1500P_0402_50V7K PR1042 U23@ PR1042 U42@ 0.01UF_0402_25V7K
    470K_0402_5%_ TSM0B474J4702RE
    1

    330P_0402_50V7K

    U22@

    2K_0402_1%

    2
    27.4K_0402_1%
    1

    1
    PR1043 1 2
    PC1035

    100K_0402_1%
    PH1004
    PR1044

    PR1045
    1

    PR1037 U23@ U22@ PR1046 U23@ SE00000MJ00


    2

    PR1047 PR1046
    68P_0402_50V8J

    0.047U_0402_25V7K
    2

    2.26K_0402_1% 1.54K_0402_1% SD000003480 SD034100180


    2

    2
    1
    PC1037

    316_0402_1% 1K_0402_1%
    Droop of CORE at 1.8mV/A PC1032 U42@
    2

    680P_0402_50V7K
    2

    PR1043 U23@ SD034383080 SD034154180 PC1034 U23@ PC1034 U42@


    1

    U22@ 383_0402_1% 1.54K_0402_1%


    PC1038
    1

    PC1039
    2200P_0402_50V7K PR1037 U42@ PR1046 U42@
    2

    SE102104K00
    2

    Comp of IA 0.1U_0402_10V7K
    SD034100380 SE074152K80 SE074471K80
    100K_0402_1% 1500P_0402_50V7K 470P_0402_50V7K
    A A
    PC1039 U23@ PC1039 U42@ SD034475080 SD00000J380
    PR1043 U42@ 475_0402_1% 3.09K_0402_1%

    SE074222K80 SE000000680
    SD034887280 2200P_0402_50V7K 8200P_0402_25V7K
    88.7K_0402_1%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    CPU_Vcore controller(36.1),Drivers(36.2), Support component(36.3) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VCORE_ISL95829
    Size Document Number Rev
    Acoust i c Noi s e B+ Bul k CAP( 37. 2) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 56 of 61
    5 4 3 2 1
    5 4 3 2 1

    +5VS

    PC1100
    4.7U_0603_10V6K PU1100 Vcore_B+
    1 2 AOZ5049QI_QFN24_5X3P5 +VCC_CORE
    13 6
    14 NC VIN 12
    <56> PWM1_VCORE 1 VCC VIN CHILI_MHCB06030-2R2M-C1L_2P
    2 PWM
    B+ Vcore_B+ <56,57> FCCM_VCORE FCCM
    1 2 1 2 3 10 PL1100

    Vinafix.com 4 BOOT GL 9 0.15UH_HPPC06030-R15M-Q8_35A_20%


    GH GL 8 1 2
    5 VSWH
    EMC@ PL1101
    VSWH 11
    HCB2012KF-121T50_0805 PC1101 PR1100
    7x7x3
    1 2 0.1U_0402_25V7K 0_0402_5% PGND 7

    @EMC@ PR1101
    D PGND D

    1
    EMC@ PL1102 AOZ5049QI_QFN24_5X3P5-S

    10_1206_5%
    HCB2012KF-121T50_0805
    1 2

    EMC@ PL1106
    100U_D_20VM_R55M

    100U_D_20VM_R55M

    2
    2200P_0402_50V7K
    HCB2012KF-121T50_0805 1 1 1 1 1

    33U_B3_16VM_R45M

    33U_B3_16VM_R45M

    100U_D2_16VM_R50M
    1 2

    0.1U_0402_25V6
    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    EMC@ PC1106

    EMC@ PC1107
    + + + + +
    PC1102

    PC1103

    @ PC1104

    @ PC1105

    PC1117

    PC1118

    PC1108

    @EMC@ PC1109
    47P_0603_50V8J
    1
    2

    2
    2 2 2 2 2

    100K_0402_1%

    100K_0402_1%
    2

    U42@ PR1104

    U42@ PR1107
    2.2_0402_1%
    3.65K_0603_1%

    1
    1

    1
    PR1106
    PR1105

    2
    2

    2
    <56> ISEN1_VCORE

    <56> ISUMP_VCORE

    Polymer cap for noise issue


    <56> ISUMN_VCORE

    ISEN2_VCORE
    U23@ PR1102
    0_0402_5% +5VS
    1 2
    <56> PWM2_GT
    U42@ PR1103 PC1110 U42@
    0_0402_5% 4.7U_0603_10V6K PU1101 Vcore_B+
    1 2 1 2 AOZ5049QI_QFN24_5X3P5
    C <56> PWM2_VCORE 13 6 C
    U23@ PR1108 14 NC VIN 12
    0_0402_5% 1 VCC VIN
    1 2 2 PWM NEC_MPCH0730LR15_2P
    <56,58> FCCM_GT FCCM
    1 2 1 2 3 10 U42@ PL1103
    U42@ PR1111 4 BOOT GL 9 0.15UH_HPPC06030-R15M-Q8_35A_20%
    0_0402_5% PR1109 GH GL 8 PWM2_PH 1 2
    1 2 0_0402_5% 5 VSWH

    @EMC@ PR1110
    <56,57> FCCM_VCORE

    1
    PC1111 VSWH 11
    7x7x3

    10_1206_5%
    0.1U_0402_25V7K PGND 7
    PGND
    AOZ5049QI_QFN24_5X3P5-S PL1103 & PL1107 change footprint to
    NEC_MPCH0730LR15_2P for co-lay

    2
    PU1101 U23@

    47P_0603_50V8J
    @EMC@ PC1116

    100K_0402_1%

    100K_0402_1%
    1

    U42@ PR1113

    U42@ PR1116
    U42@ PR1114

    PR1115
    2.2_0402_1%
    3.65K_0603_1%

    1
    1

    1
    2
    2200P_0402_50V7K

    SA00009RK00
    EMC@ PC1114

    EMC@ PC1115
    0.1U_0402_25V6

    U42@
    AOZ5049QI_QFN24_5X3P5
    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    1
    1

    1
    @ PC1121

    @ PC1120

    @ PC1119

    PC1112

    @ PC1113

    2
    2

    2
    2
    2

    <56> ISEN2_VCORE

    ISUMP_VCORE

    ISUMN_VCORE

    ISEN1_VCORE

    B B
    +VCCGT
    NEC_MPCH0730LR15_2P
    U23@ PL1107
    0.15UH_HPPC06030-R15M-Q8_35A_20%
    PWM2_PH 1 2

    7x7x3

    100K_0402_1%
    U23@ PR1117

    U23@ PR1118

    U23@ PR1119
    U23@ PR1112

    2.2_0402_1%

    100K_0402_1%
    3.65K_0603_1%
    1

    1
    2

    2
    <56,58> ISUMP_GT

    <56,58> ISEN2_GT

    <56,58> ISUMN_GT

    <56,58> ISEN1_GT

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    CPU_Vcore controller(36.1),Drivers(36.2), Support component(36.3), THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VCORE_VCORE
    Size Document Number Rev
    CPU_Core output CAP(36.4),Acoust i c Noi s e B+ Bul k CAP( 37. 2) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 57 of 61
    5 4 3 2 1
    5 4 3 2 1

    VCC_GT (U-line 22) VCC_GT Merged(GT+GTx)(U-line 23e)


    TDC 18A TDC 35A
    Peak Current 31A Peak Current 64A
    OCP current 37A OCP current 74A

    +5VS
    Vinafix.com
    D D

    PC1150
    4.7U_0603_10V6K PU1150 Vcore_B+
    1 2 AOZ5049QI_QFN24_5X3P5
    13 6
    14 NC VIN 12 +VCCGT
    <56> PWM1_GT 1 VCC VIN
    2 PWM CHILI_MHCB06030-2R2M-C1L_2P
    <56,57> FCCM_GT FCCM
    1 2 1 2 3 10 PL1150
    4 BOOT GL 9 0.15UH_HPPC06030-R15M-Q8_35A_20%
    Vcore_B+ PC1151 PR1150 GH GL 8 1 2
    0.1U_0402_25V7K 0_0402_5% 5 VSWH
    VSWH 11

    @EMC@ PR1151
    PGND 7
    7x7x3

    4.7_1206_5%
    PGND

    1
    AOZ5049QI_QFN24_5X3P5-S

    2
    2200P_0402_50V7K
    0.1U_0402_25V6
    EMC@ PC1154

    EMC@ PC1155
    10U_0603_25V6M

    10U_0603_25V6M
    1
    1

    1
    PC1152

    PC1153

    @EMC@ PC1156
    680P_0603_50V7K
    1
    2
    2

    PR1153

    PR1155
    2.2_0402_1%
    100K_0402_1%

    100K_0402_1%
    3.65K_0603_1%
    1

    1
    1

    1
    2

    PR1154
    PR1152

    U23@

    U23@
    2

    2
    2

    2
    <56,57> ISUMP_GT

    C C
    <56,57> ISEN1_GT
    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    PC1157

    PC1158

    <56,57> ISUMN_GT
    2

    <56,57> ISEN2_GT

    B+ SA_B+ VCC_SA
    EMC@ PL1108 TDC 5A
    HCB2012KF-121T50_0805
    1 2 Peak Current 5.1A
    OCP current 7A
    2200P_0402_50V7K
    @EMC@ PC1159

    @EMC@ PC1160
    0.1U_0402_25V6

    10U_0603_25V6M

    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    1

    1
    PC1161

    PC1162

    PC1163

    +5VS
    2

    2
    2

    PC1164
    B B
    4.7U_0603_6.3V6M
    1 2

    PU1151
    13 6
    14 NC VIN 12
    VCC VIN
    <56> PWM_SA
    1
    2 PWM +VCCSA
    <56> FCCM_SA 1 2 3 FCCM 10 PL1151
    PC1165 0.1U_0603_25V7K 4 BOOT GL 9 0.47UH_MMD05CZR47M_12A_20%
    GH GL 8 1 2
    1 2 5 VSWH
    VSWH 11
    @EMC@ PR1157

    PR1156 PGND 7
    4.7_1206_5%

    2.2_0603_1% PGND
    AOZ5029QI_QFN24_5X3P5

    Pilot-004
    3.65K_0603_1%
    1

    1
    @ PR1159
    0_0402_5%
    2

    PR1158
    @EMC@ PC1166
    680P_0603_50V7K

    2
    2 1

    <56> ISUMP_SA

    <56> ISUMN_SA

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    CPU_Vcore controller(36.1),Drivers(36.2), Support component(36.3), THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VCORE_VGT,VSA
    Size Document Number Rev
    GFX output CAP(36.5) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 58 of 61
    5 4 3 2 1
    5 4 3 2 1

    +VCCGT
    +VCC_CORE U22_Normal cap U23_low noise cap_H=0.8 U23_low noise cap_H=1.2
    U23_Normal cap
    BTM low noise cap__H=1.2

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    U23@ PC1218

    U23@ PC1257

    U23@ PC1331

    U23@ PC1247

    U23@ PC1356

    U23@ PC1344

    U23@ PC1346

    U23@ PC1333

    U23@ PC1355

    U23@ PC1357

    U23@ PC1359

    U23@ PC1379
    1

    1
    U22@ PC1206

    U22@ PC1207

    U22@ PC1236

    U22@ PC1382

    U22@ PC1238

    U22@ PC1204

    U22@ PC1214

    U22@ PC1202

    U22@ PC1201

    U22@ PC1212

    U22@ PC1233

    U22@ PC1232

    U22@ PC1234

    U22@ PC1235

    U22@ PC1239

    U22@ PC1231

    U22@ PC1383

    U22@ PC1242

    U22@ PC1387

    U22@ PC1216

    U22@ PC1205

    U22@ PC1255

    U22@ PC1211

    U22@ PC1243

    PC1244

    U22@ PC1226

    U22@ PC1250

    U22@ PC1245

    U23@ PC1334

    U23@ PC1246

    U23@ PC1220

    U23@ PC1336

    U23@ PC1217

    U23@ PC1351

    U23@ PC1227

    U23@ PC1223

    U23@ PC1254

    U23@ PC1253

    U23@ PC1219

    U23@ PC1228

    U23@ PC1225

    PC1378
    PC1250 @U23@

    2
    U23_low noise cap_H=0.8
    Vinafix.com PC1245 @U23@ PC1205 @U23@
    SE00000M020
    22U_0603_6.3V6M

    PC1255 @U23@
    D U22_Normal cap D

    PC1206 U23@ PC1207 U23@ PC1236 U23@ PC1382 U23@ PC1238 U23@ PC1204 U23@ PC1214 U23@ PC1202 U23@ PC1201 U23@ PC1212 U23@
    PC1334 U22@ PC1246 U22@ PC1220 U22@ PC1336 U22@ PC1217 U22@ PC1351 U22@
    VCC_GT Place on VR
    22U_0603 * 44 pcs
    SE00000M020 SE00000M020 SE00000M020
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M (U22: 22u_NC 25pcs)
    SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0
    (U23: 22u_NC 7pcs)
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PC1211 @U23@ PC1243 @U23@ PC1226 @U23@ SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000 (U42: 22u_NC 26pcs)
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    PC1233 U23@ PC1232 U23@ PC1234 U23@ PC1235 U23@ PC1239 U23@ PC1231 U23@ PC1383 U23@ PC1242 U23@ PC1387 U23@ PC1216 U23@
    PC1227 U22@ PC1223 U22@ PC1254 U22@ PC1219 U22@ PC1228 U22@ PC1253 U22@ 330u_B2*3 pcs
    (330u_NC 1pcs)
    SE00000M020 SE00000M020 SE00000M020
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M020 SE00000M020 SE00000M020 SE00000M020 SE00000M020 1U_0201*14pcs
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

    U42_Normal cap U42_low noise cap_H=0.8 PC1245 @U42@ PC1205 @U42@ PC1255 @U42@ PC1211 @U42@ U42_Normal cap
    PC1204 U42@ PC1214 U42@ PC1202 U42@ PC1201 U42@ PC1212 U42@ PC1334 U42@ PC1246 U42@ PC1220 U42@ PC1336 U42@ PC1253 U42@ PC1217 U42@

    SE00000M020 SE00000M020 SE00000M020 SE00000M020


    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


    1

    1
    @U42@ PC1200

    @U42@ PC1203

    @U42@ PC1230

    U42@ PC1237

    U42@ PC1381

    SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 PC1243 @U42@ PC1226 @U42@ PC1250 @U42@ SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    2

    PC1233 U42@ PC1232 U42@ PC1234 U42@ PC1235 U42@ PC1239 U42@ PC1351 U42@ PC1227 U42@ PC1223 U42@ PC1219 U42@ PC1228 U42@ PC1254 U42@

    SE00000M020 SE00000M020 SE00000M020


    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M H=1.2
    U42_Normal cap SE00000M020
    U42_low noise cap_H=1.2_SE00000M020
    PC1206 @U42@ PC1207 @U42@ PC1236 @U42@ PC1382 @U42@ PC1238 @U42@ U22 & U23 use U23 & U42 use
    PC1231 U42@ PC1383 U42@ PC1242 U42@ PC1387 U42@ PC1216 U42@ PC1221 U22@ PC1358 U22@ PC1337 U22@ PC1248 U22@ PC1256 U22@ PC1258 U22@

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000

    U23@ PC1221

    U23@ PC1337

    U23@ PC1358

    U23@ PC1361
    1

    1
    C C

    U23@ PC1248

    U23@ PC1256

    U23@ PC1258

    U23@ PC1360

    U23@ PC1349

    U23@ PC1330

    U23@ PC1229
    SE00000M020 SE00000M020 SE00000M020 SE00000M020 SE00000M020 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M SE00000M020 SE00000M020 SE00000M020 SE00000M000 SE00000M000 SE00000M000
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

    2
    PC1361 U42@ PC1360 U42@ PC1349 U42@ PC1330 U42@ PC1229 U42@
    PC1306 U23@ PC1306 @U22@
    330_B2_2.5VM_R9M

    330_B2_2.5VM_R9M

    330_B2_2.5VM_R9M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    1 1 1
    1

    + + +
    PC1309

    PC1529

    U42@ PC1306

    @ PC1208

    @ PC1241

    @ PC1380

    @ PC1384

    @ PC1385

    @ PC1209

    @ PC1386

    @ PC1210

    @ PC1213

    @ PC1215

    @ PC1240

    H=1.2
    SE00000M020 SE00000M000 SE00000M000 SE00000M000 SE00000M000
    2

    2 2 2 SGA00004500 SGA00008M00 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M


    220U_B2_2.5VM_R15M 330_B2_2.5VM_R9M
    H=1.2

    330_B2_2.5VM_R9M

    330_B2_2.5VM_R9M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    1 1
    1 1 1 1 SE00000M020

    1
    + +

    PC1307

    PC1329

    @ PC1308

    @ PC1345

    @ PC1353

    @ PC1224

    @ PC1249

    @ PC1332

    @ PC1362
    Pilot-002

    2
    2 2 2 2 2 2
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1

    1
    PC1259

    PC1260

    PC1261

    PC1262

    PC1263

    PC1264

    PC1265

    PC1266

    PC1267

    PC1268

    PC1269

    PC1270

    PC1271

    PC1272

    PC1273

    PC1274

    PC1275

    PC1288
    2

    VCC_CORE

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    22U_0603 * 44 pcs

    1
    PC1280

    PC1281

    PC1282

    PC1283

    PC1284

    PC1285

    PC1286

    PC1339

    PC1340

    PC1373

    PC1374

    PC1375

    PC1376

    PC1377
    (U22 & U23: 22u_NC 16pcs)
    (U42:22u_NC 11pcs)

    2
    330u_B2 * 3 pcs
    (330u_NC 1pcs)
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    1

    1U_0201*32pcs
    PC1289

    PC1290

    PC1291

    PC1292

    PC1293

    PC1294

    PC1295

    PC1296

    PC1297

    PC1298

    PC1299

    PC1300

    PC1301

    PC1302

    PC1303

    PC1304

    PC1305
    2

    +VCCSA
    B B

    +VCCIA_GT

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    U23_Normal cap 1 1 1 1 1 1 1 1 1 1 1 1

    PC1310

    @ PC1311

    PC1312

    @ PC1313

    PC1314

    PC1315

    PC1316

    @ PC1317

    PC1318

    PC1319

    PC1320

    PC1321
    VCCIA_GT Place under CPU
    22U_0603 * 9pcs 2 2 2 2 2 2 2 2 2 2 2 2
    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    1 1 1 1 1 1 1
    1U_0201 * 19pcs
    1

    (U22: 22u_NC 4pcs)


    U23@ PC1222

    U23@ PC1251

    U23@ PC1335

    U23@ PC1350

    U23@ PC1352

    U23@ PC1252

    U23@ PC1347

    U23@ PC1348

    U23@ PC1354
    2

    2 2 2 2 2 2 2

    VCC_SA Place on CPU


    TOP Side.

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M
    22U_0603 * 10 pcs + 1U_0201*7 pcs
    U22_Normal cap

    1
    Bottom Side.

    PC1322

    PC1323

    PC1324

    PC1325

    PC1326

    PC1327

    PC1328
    PC1222 U22@ PC1251 U22@ PC1335 U22@ PC1350 U22@ PC1352 U22@ 22U_0603 * 2 pcs

    2
    SE00000M000 SE00000M000 SE00000M000 SE00000M000 SE00000M000
    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

    U42_low noise cap_H=0.8


    PC1222 U42@ PC1251 U42@ PC1335 U42@ PC1350 U42@ PC1352 U42@

    SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0


    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    PC1252 U42@ PC1347 U42@ PC1348 U42@ PC1354 U42@

    A A

    SE00000M0M0 SE00000M0M0 SE00000M0M0 SE00000M0M0


    22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    1U_0201_6.3V6M

    VCC_CORE output cap(36.4), VCC_GT output cap(36.5), VCC_SA output cap(36.6), VCC_IAGT out cap(36.7)
    1

    1
    PC1287

    PC1341

    PC1342

    PC1343

    PC1277

    PC1278

    PC1338

    PC1276

    PC1279

    PC1363

    PC1364

    PC1365

    PC1366

    PC1367

    PC1368

    PC1369

    PC1370

    PC1371

    PC1372
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CPU BACK SIDE MLCC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E671P
    Date: Tuesday, October 17, 2017 Sheet 59 of 61

    5 4 3 2 1
    5 4 3 2 1

    +3VALW LPM VID1 VID0 Vout

    0 X X 0.000

    1
    (LPM)
    @ PR1423
    Pilot-004 10K_0402_1% 0.850
    @ PR1400
    1 0 0

    2
    0_0402_5%
    1 2
    <12,27,34,60> SIO_SLP_S0# TPS62134A
    <34>
    Vinafix.com
    VCCSTG_EN
    @ PR1401
    1 2
    VCCIO 1 0 1 0.8750

    0.1U_0402_25V6
    0_0402_5%
    1 1 0

    1
    D D
    Pilot-004 0.950

    EN_VCCIO
    1
    @ PC1400
    @ PR1402
    0_0402_5%
    1 1 1

    2
    0.975

    13

    14

    15

    16

    17
    PU1400
    Vin=6~9V

    EN

    PGND

    PGND

    TP
    LPM
    EMC@ PL1400
    HCB1608KF-121T30_0603
    VIN_VCCIO
    B+ 1 2 12
    PVIN VOS
    1
    +1.0VS_VCCIOP
    +3VALW PL1401
    1UH_HEI322512A-1R0M-Q8_3.7A_20%
    Vout=0.95V

    10U_0603_25V6M

    10U_0603_25V6M
    1

    1
    LX_VCCIO
    11 2 1 2
    +1.0VS_VCCIOP

    PC1401

    PC1402
    PVIN SW
    3.2 * 2.5 *1.2

    22U_0603_6.3V6M

    22U_0603_6.3V6M

    22U_0603_6.3V6M
    2

    2
    TPS62134ARGT_QFN16_3X3 CHILI_HEI322512A-2R2M-Q8_2P

    1
    10 3

    PC1403

    PC1404

    @ PC1405
    2200P_0402_50V7K
    AVIN SW

    0.1U_0402_25V6
    footprint

    1
    EMC@ PC1408

    EMC@ PC1409

    2
    1
    TPS62134ARGT_QFN16_3X3-S
    1

    VID0_VCCIO 9 4

    2
    VID0 PG @EMC@ PR1403
    PR1404 @ PR1405 4.7_0603_5%

    AGND
    10K_0402_1% 10K_0402_1%

    VID1

    2
    FBS

    SNUB_VCCIO
    SS
    Fsw=1.2MHz
    2

    VID0_VCCIO

    100_0402_1%
    8

    1
    VID1_VCCIO @ PJP1400
    JUMP_43X79

    @ PR1408
    1 2
    +1.0VS_VCCIOP +1.0VS_VCCIO
    1

    1
    VID1_VCCIO @EMC@ PC1410 1 2

    1 SS_VCCIO
    680P_0402_50V7K

    2
    @ PR1406 PR1407

    2
    10K_0402_1% 10K_0402_1%
    C C

    470P_0402_50V7K
    2

    @ PR1409
    0_0402_5%
    VCCIO

    PC1411
    1 2
    VCCIO_SENSE <18> TDC 2.2A

    2
    Pilot-004 Peak Current 3.1 A
    OCP Current 4.2 A Fix by IC
    MIN:3.6A
    MAX:4.9A
    Choke DCR 34.0mohm
    +3VALW

    1
    @ PJP1401
    JUMP_43X79
    PR1424 1 2
    @ PR1411 10K_0402_1% +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
    0_0402_5%

    2
    1 2
    <12,27,34,60> SIO_SLP_S0#
    PR1412
    130K_0402_1%
    1 2
    <12,33,36,38,53,54> SIO_SLP_SUS# PRIM_CORE
    EN_PRIM_CORE

    TDC 1.8A
    0.1U_0402_25V6
    1

    Peak Current 2.6 A


    1
    PC1412

    @ PR1413
    0_0402_5% OCP Current 4.2 A Fix by IC

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