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4.6.1
User’s Manual
Revision Date
2.13 November 2009
simnow@amd.com
AMD
AMD‟s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other
application in which the failure of AMD‟s product could create a situation
where personal injury, death, or severe property or environmental damage
may occur. AMD reserves the right to discontinue or make changes to its
products at any time without notice.
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, AMD Opteron, ATI Radeon and
combinations thereof, SimNow, 3DNow!, AweSim, AMD-8111, AMD-8131, AMD-
8132 and AMD-8151 are trademarks of Advanced Micro Devices, Inc.
HyperTransport is a trademark of the HyperTransport Technology Consortium.
Microsoft, Windows and DirectX are registered trademarks of Microsoft Corporation.
PCI-X and PCIe are registered trademarks of PCI-SIG.
Sysmark is a registered trademark of Business Applications Performance Corp.
SPECint2000 and SPECfp2000 are registered trademarks of the Standard Performance
Evaluation Coorporation (SPEC).
MMX is a trademark of Intel Corporation.
Linux is a registered trademark of Linus Torvalds.
Other product names used in this publication are for identification purposes only and may
be trademarks of their respective companies.
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Contents
Figures................................................................................................................................ ix
Tables ............................................................................................................................... xiii
1 Overview ..................................................................................................................... 1
2 Installation................................................................................................................... 3
2.1 System Requirements.......................................................................................... 3
2.2 Installation Procedure ......................................................................................... 3
2.3 Directory Structure and Executable .................................................................... 4
2.4 Setting® up Linux for the Simulator ................................................................... 4
2.5 Configuration File ............................................................................................... 5
2.6 Updates and Questions ........................................................................................ 6
3 Graphical User Interface ............................................................................................. 7
3.1 Tool Bar Buttons ................................................................................................. 7
3.2 Device Window .................................................................................................. 9
3.2.1 Add a New Device ........................................................................................ 10
3.2.2 Workspace Popup Menu ............................................................................... 10
3.2.2.1 Add Connection .................................................................................. 10
3.2.2.2 Configure Device ................................................................................ 12
3.2.2.3 Disconnect Device ............................................................................. 12
3.2.2.4 Delete Device...................................................................................... 12
3.2.3 Example Computer Description .................................................................... 12
3.2.4 Device Window – Quick Reference ............................................................. 14
3.3 Device Groups .................................................................................................. 15
3.3.1 Terms ............................................................................................................ 15
3.3.2 Concept Diagrams ......................................................................................... 16
3.3.3 Working with Device Groups ....................................................................... 17
3.3.4 Shell Automation Commands for Device Groups ........................................ 18
3.3.4.1 Device Tree ......................................................................................... 18
3.3.4.2 Enabled vs. Disabled vs. Mixed ....................................................... 19
3.3.5 Device Group Examples ............................................................................... 20
3.3.5.1 Example: 1GB DDR2 memory ......................................................... 20
3.3.5.2 Example: Quad-Core Node .............................................................. 21
3.3.5.3 Example: SuperIO device ................................................................. 23
3.3.6 Creating a Device Group (GUI) .................................................................... 23
3.3.7 Creating a Device Group (Automation Commands) .................................... 26
3.3.8 Ungrouping a created device group .............................................................. 27
3.4 Main Window ................................................................................................... 28
3.4.1 SimStats and Diagnostic Ports ...................................................................... 28
3.4.2 CPU-Statistics Graphs .................................................................................. 29
3.4.2.1 Translation Graph............................................................................... 29
3.4.2.2 Real MIPS Graph ............................................................................... 29
3.4.2.3 Invalidation Rate Graph .................................................................... 30
3.4.2.4 Exception Rate Graph ....................................................................... 30
3.4.2.5 PIO Rate Graph .................................................................................. 30
Contents iii
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Contents v
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Contents vii
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Figures
Figures ix
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x Figures
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Figures xi
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Tables
Table 1-1: Feature Overview Public Release versus Full Release ..................................... 2
Table 2-1: Software and Hardware Requirements .............................................................. 3
Table 3-1: Cheetah_1p.bsd Devices ................................................................................. 14
Table 3-2: Device Window - Quick Reference................................................................. 14
Table 3-3: Image Types .................................................................................................... 32
Table 5-1: Command-Line Arguments ............................................................................. 40
Table 5-2: Newmachine Command Arguments ............................................................... 46
Table 7-1: Supported Devices ........................................................................................... 54
Table 7-2: Supported Standard VESA Modes .................................................................. 67
Table 7-3: Supported Custom VESA Modes .................................................................... 68
Table 7-4: Matrox G400 VESA Modes ............................................................................ 75
Table 7-5: Supported Resolutions in Power Graphics Mode............................................ 75
Table 7-6: Supported Guest Operating Systems ............................................................... 76
Table 7-7: Execution Control Flags ................................................................................ 120
Table 7-8: Internal Execution Control Flags .................................................................. 121
Table 7-9: Mediator Command Line Switches ............................................................... 131
Table 7-10: MAC Address Assignments ........................................................................ 132
Table 7-11: Client-Server: Simulator Server .................................................................. 132
Table 7-12: Client-Server: Simulator Client 1 ................................................................ 132
Table 7-13: Isolated Client-Server: Simulator Server .................................................... 132
Table 7-14: Isolated Client-Server: Simulator Client 1 .................................................. 133
Table 10-1: Debugger Breakpoint Command Examples ................................................ 152
Table 10-2: Debugger Memory Dump Command Examples ......................................... 153
Table 10-3: Debugger AMD-V™ Memory Dump Command Examples....................... 154
Table 10-4: MSR Read Examples................................................................................... 154
Table 10-5: MSR Write Example ................................................................................... 155
Table 10-6: Find Pattern Example .................................................................................. 155
Table 10-7: Debugger Commands and Definitions ........................................................ 159
Table 15-1: Computer Platform Files (BSD) .................................................................. 184
Table 15-2: Product Files ................................................................................................ 185
Table 15-3: Hard-Disk Images........................................................................................ 186
Table 15-4: Memory SPD Files ...................................................................................... 186
Table 15-5: Supported Guest Operating Systems ........................................................... 187
Table 15-6: CPUID Standard Feature implementation ................................................... 188
Table 15-7: CPUID Extended Feature implementation .................................................. 189
Table 15-8: General-Purpose Instruction Reference....................................................... 226
Table 15-9: System Instruction Reference ...................................................................... 228
Table 15-10: 3DNow!™ Instruction Reference ............................................................. 230
Table 15-11: Extension to 3DNow! Instruction Reference ............................................ 231
Table 15-12: Prescott New Instruction Reference .......................................................... 232
Table 15-13: CodeGen Command Overview ................................................................. 249
Table 15-14: Prefix Sequences (keyboard.text) .............................................................. 255
Tables xiii
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1 Overview
The AMD SimNow™ simulator is an AMD64 technology-compatible x86 platform
simulator for AMD's family of processors. It is designed to provide an accurate model of
a computer system from the program, OS, and programmer's point of view. It allows fast
simulation of an entire computer system, plus standard debugging features such as break-
pointing, memory-viewing, and single-stepping. The simulator allows such work as BIOS
and OS development, memory-parameter tuning, and multi-processor system simulation.
The simulator has between a 10:1 and 100:1 slowdown rate from the host CPU,
depending on whether the workload is in the CPU core or accessing simulated devices
intensively.
The simulator is designed to create an accurate model of a system from the program‟s
view. Device models contain all the program-visible state but the actual functionality is
abstracted. In many cases only the functionality needed to satisfy the software is
implemented. Software may be run on the simulator in an unmodified form. This includes
BIOS, drivers, O/S, and applications.
The simulator has a concept of time, but it is not a cycle-accurate simulator. The basic
timing mechanism is an instruction; all instructions execute in the same amount of time
and are one tick in length. This "tick" time is scaled and used by the rest of the system.
Long-latency events, like disk or floppy access, have some minimum latency built in
because we found legacy software that relied on the physical latency of these peripherals.
The simulator contains all the classic pieces of a PC system (CPU, memory, Northbridge,
Southbridge, display, IDE drives, floppy, keyboard, and mouse support). Images (hard
disk, DVD/CD-ROM, and floppy) can be created in custom sizes with the DiskTool
program (Section 13, “DiskTool”, on page 167) that is provided with the simulator. A
simulation can be saved at any point in the simulation to a media file, from which the
simulation can be re-run at a later time.
A simple diagnostic port model (known as "Port80" device) displays values written by
the BIOS in a pane of the simulator's main window. Other panes display guest (simulated
machine) and simulator host processor times. The simulator requires several files to be
specified. Binary files containing the BIOS and disk images are stored in the images
directory. The simulator home directory stores “*.bsd” files which contain the
configuration of the system (how models are connected together and their settings) and
the logical state of all the devices in the simulator. When starting a simulation from reset,
the “*.bsd” file is rather small and only contains the configuration information. When the
simulation starts, the simulated memory is allocated. When the simulation is halted and
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saved, the “*.bsd” file will have grown significantly, slightly larger than the size of
simulated memory.
The graphics device supplied with the simulator is a 2D and 3D graphics card with linear
frame buffer and DirectX® 6 support. AMD currently plans to provide a graphics model
with the simulator which will also have modern 3D hardware acceleration, including
Microsoft® DirectX 9/10 support.
The simulator is available in two versions: Public Release and Full Release. Table 1-1
shows the detailed feature matrix:
1
Support of up to two cores.
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2 Installation
2.1 System Requirements
The AMD SimNow™ simulator runs on both Linux® 64 for AMD systems and
Windows® for 64-bit AMD systems.
The simulator may stress the system more than most applications, including the base
operating system. AMD has received reports that the simulator has caused some systems
to crash, and in general this has been traced to unstable hardware. Hardware instability
can also crash applications or operating systems inside the simulator.
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begin the installation, as follows. To install under Windows, double-click on the self-
extracting executable. To install under Linux, extract the zipped tar file as shown below:
The install program will create the following subdirectories under the install directory:
Contains the simulator’s executable, DiskTool, libraries, and BSD files.
analyzers Contains CPU analyzers.
devices Contains the simulator's device models.1
doc Contains the latest versions of the simulator documentation.
help Contains the simulator’s help files.
icons Contains icons used by the simulator’s GUI components.
images Contains image files.
productfile Contains processor-id files.
reg Contains register script files used to register simulator components.
devel Contains the Emerald BIOS changes, analyzer header files, and monitor module example.
radeon Contains the ATI Radeon™ board configuration files.
1
Under Windows each model is a Windows DLL. Under Linux each model is a Linux library. Each model has a ".bsl"
extension.
# This line doesn't need to be here for newer Linux kernels, but some
# early AMD64 Linux kernels would log SEGVs even if a process had a
# handler for them, which is what SimNow does.
debug.exception-trace = 0
Example 2-1: Setting up Linux for the Simulator
Then run "sysctl -p", or make sure the boot sequence does this if you don't want to run it
at each reboot.
Newer Linux distributions may set a per-process memory limit by default. SimNow
allocates a large amount of memory that is never touched. This untouched memory will
not be backed by DRAM or swap, but Linux counts it against SimNows process memory
limit when it comes to resource limits.
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You can unset the per-process memory limits by running the following commands as
root.
ulimit -m unlimited
ulimit -v unlimited
If you are using Windows as host operating system the configuration file is located in:
If you are using Linux as host operating system the configuration file is located in:
$HOME/.qt/simnowrc
[General]
[UserKeys]
CTL-ESC=Sends a CTL-ESC to the application,1D 01 81 9D
ALT-F4=Sends an ALT-F4 to the application,38 3e be b8
[UserBottons]
BUTTON0=”MyIconPath\MyIcon.png”,“cpu.name”
The configuration file is divided into sections, with each section title enclosed in square
brackets. This particular example includes three sections, named [General], [UserKeys]
and [UserBottons].
All user key definitions are stored in the [UserKeys] section. Each user key definition is
defined by a single line. This example defines two user keys. The string to the left of the
equal sign is the string that will be placed in the menu. To the right of the equal sign are
two strings, separated by a comma. The first string is the text that is displayed when the
user clicks on the "What's This" help button, and the second string is the list of scan codes
that are sent when this menu item is selected.
The two examples shown can also be generated by the “Generate Key Codes” menu item
on the “Special Keyboard” menu, see Section 5.2.3, “Interaction with the Simulated
Machine”, on page 45.
All user button definitions are stored in the [UserButtons] section. Each user button
definition is defined by a single line. This example defines one user button (BUTTON0).
The string to the left of the equal sign is the path including the file name of the icon that
will be placed in the toolbar menu. To the right of the equal sign is the string that
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Note that minimal parsing of the text is done, so it is important that no spaces exist
around the separating comma.
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The simulation can be stopped by clicking on the “Stop” button ( ). To reset the entire
simulator, stop the simulation first by clicking on the “Stop” button and then click on the
“Reset” button ( ).
The power-management “Soft Power” button ( ) and “Soft Sleep” button ( ) are
available only on simulated systems that have an Advanced Configuration and Power
Interface (ACPI) BIOS.
Clicking on the “Soft Power” button puts the simulated system in a very low power
consumption mode. The working context can be restored if it is stored on nonvolatile
media. The simulated system appears to be off.
Clicking on the “Soft Sleep” button simulates a power-consumption reduction. The power
consumption is reduced to one of several levels, depending on how the system is to be
used. The lower the level of power consumption, the more time it takes the system to
return to the working state.
To close a previously loaded system simulation definition file click on the “Close BSD”
button ( ). This button is only enabled when a system definition file has been loaded or
created earlier. Please make sure you save any changes that you make to the system
configuration before clicking on the “Close BSD” button ( ) to close the system
definition file. Otherwise all changes will be lost.
The “Save BSD” button ( ) is only enabled/active when a system definition (BSD file)
has been loaded or created. To save your current system definition click on the “Save
BSD” button ( ) or click on the "File" menu item and select "Save BSD".
To open a system definition file (BSD file) click on the “Open BSD” button ( ) and
select the desired BSD file from the Open File Dialog Window. The "Open BSD" button
is only enabled/active when no other system definition file has been open yet.
To create a blank or new system definition file click on the “New BSD” button ( ). This
button is disabled when a system definition file has been loaded or created earlier. In this
case you must close your current system definition file, click on the “Close BSD” button
( ) or click on the "File" menu item and select "Close BSD". Please make sure you save
any changes that have been made to the system definition file before you click on the
“Close BSD” button ( ). Note, when closing the BSD file all changes will be lost.
If you want to modify the current system definition use the “Show Device Window”
button ( ) to display the current system configuration. The “Show Device Window”
button is disabled when the simulation is currently running. To stop the simulation click
on the “Stop Simulation” button ( ).
To open the simulator's integrated debugger click on the “Show Debugger” button ( ).
The “Show Debugger” button is disabled when the simulation is currently running. To
stop the simulation click on the “Stop Simulation” button ( ).
Click on the “Best Fit To Window” button ( ) to reduce or enlarge the size of the
simulated display area so that the entire simulated display area will fit into the simulators
main window. If you hold down the CTRL key when clicking on the “best fit” button, it
“locks” into a state where the simulated display area is resized whenever the simulated
graphics display resolution changes. To clear this locked condition, click on the “best fit”
button again.
This section describes the main components of the Device Window and shows how to
build up and configure a simulated computer. It explains the interface using some of the
most-often used simulation components. Please also see the walkthrough of building a
single-processor system in Section 6, “Create a Simulated Computer”, on page 49.
Represents Device
Message Routing Window
System
Configuration
The Device List, located on the left side of the Device Window, describes all devices
available in the simulator along with their configuration options. For further information
please refer to Section 7, “Device Configuration”, on page 53.
The Show Deprecated Devices checkbox is not checked by default. This checkbox gives
the user the opportunity to show or hide deprecated devices. It is not recommended to use
deprecated devices in simulation. To show deprecated devices this checkbox must be
checked. The Show Deprecated Devices checkbox does not disable the ability to connect
or create deprecated devices. Also the automation interface of deprecated devices and
loading BSDs which contain deprecated devices are both unaffected.
Some devices produce additional windows or dialogs when you add them to the
workspace. These windows provide an interface to the device during simulation. For
example, adding the Winbond WB83627HF SIO device (see Section 7.5 on page 69) to
the workspace adds the floppy byte counts numeric window to the Main Window screen.
When you add a device to the workspace, the shell sends a reset message to all of the
devices in the workspace. The global reset is equivalent to power-cycling the simulated
computer system.
Right-clicking on any icon in the workspace produces a popup menu as shown in Figure
3-3.
"Add Connection", and then click on the device to connect to. Then click Finish. The
connection enables simulator-level message exchanges between the connected devices.
All connections enable bidirectional message transfers.
Some devices contain more than one interface to which a connection can be made. A
multi-interface device routes messages out different interfaces, based on the type of
message being sent. When you make a connection with a multi-interface device, an
interface list dialog appears which enables you to select the appropriate interface. You
must choose an interface on either device, even if one or both of the devices has only one
interface type.
Generally, you shouldn't connect different types of interfaces. For example, interface
Type A of Device 1 should only be connected to interface Type A of Device 2.
When you add a connection, the simulator shell sends a reset message to all of the
devices in the workspace. The global reset is equivalent to power-cycling the simulated
computer system.
Selecting the “Connections” tab in the Device Properties window will display a list of all
connections between the specified device and any other devices in the workspace.
Right-clicking on any icon brings up a Workspace Popup menu (Figure 3-3) that allows
access to the Device Property window, which includes a list of all components that the
selected component is connected to. An example Device Property window is shown in
Figure 3-4. The right-click Workspace Popup menu also allows you to delete or
disconnect the selected device from all its connections.
Table 3-1 lists each component in the “cheetah_1p.bsd” computer. For more information
about devices and possible device configuration, please refer to Section 7, “Device
Configuration” on page 53.
Device groups are a particular class of devices. They have the same properties and
characteristics as traditional devices, but also allow the user to extend and tailor specific
device(s) to meet a particular hardware implementation or configuration. Device groups
provide a method that allows the user to group or collect one or more devices, libraries or
groups into one composite device. To the user, the composite device will look and feel no
different than a normal device library and, for the most part, the two should be
indistinguishable.
A device group can consist of one or more child devices, with some optional initialization
state associated with each child device, and those devices can optionally be connected to
each other. It may be helpful to think of a device group as a BSD within a BSD.
However, a device group also has its own identity as a device, and it can support external
connection ports that allow it be connected to other devices in the same manner as a
traditional device library.
3.3.1 Terms
If any of the language and wording used in these Device Groups sections is unclear, it
may help to refer to this list of terms.
Device: A device library or device group (also, a known device or created device).
Device Group: Grouping of one or more devices (libraries and groups) into a single
device; gets its functionality through aggregation of its children, and from its group-
specific properties/aspects; associated with a “*.bsg” file.
Known Device: A device that the shell knows about (i.e., the shell has all the necessary
information to create an instance of this device). Known devices appear in the left hand
pane of the Device Viewer window; and on the console using shell.KnownDevices.
Created Device: An instantiation of a known device. All devices in a BSD are created
devices. Created devices appear in the right hand pane of the Device Viewer window; and
on the console using “shell.CreatedDevices”.
Device grouping tree node relationships: Because of device grouping, created devices
in a BSD are nodes in a tree, with parents and children, siblings, and end/root tree node
relationships.
Machine Device Group: Just a device group, but it is special since it is the root node of
a machine tree (it has no parent, it can't be deleted, it has no ports, and it has no sibling
devices); each machine in a BSD has a single machine created device group.
Archive Data or Device State: A known device group has archive data for its child
devices, which specifies the default and initial state for when a known device group is
instantiated as a created device. A known device library also has default and initial state
for when it is instantiated as a created device. When a BSD is saved, each device's current
state (archive data) (which may be different than the original known device's archive
data) is saved to the “*.bsd” file.
External Connection: A connection between a device's parent group and a sibling of the
parent group. Under-the-hood, a connection to a device group is routed to one of its
children, via an internal-to-external port mapping between the child device's port and the
parent device's port.
Machine
Machine
Group
Group
Library
Group
Library Library
y
Library Library
Library
Figure 3-7: Device group (different conceptual view – devices are inside groups)
The previous diagrams show child devices inside device groups. On the standard top
level view (the context of inside the machine device), we would more simply just see
three devices, see Figure 3-8 (arrows represent possible port connections between the
devices).
Machine
Device
Device
Device
Click on "Modify Group (Show Devices)". This will open a separate show device viewer
window.
1 simnow> shell.createddevices
"4 core Node #0"
"4 core Node #1"
1 simnow> shell.modules
xtrsvc:0
shell:0
Cpu:0
sledgeldt:0
sledgenb:1
sledgenb:0
Cpu:1
Cpu:2
Cpu:3
sledgeldt:1
Cpu:4
Cpu:5
Cpu:6
Cpu:7
Notice the “shell.modules” list is flat, but the devices are in a tree structure that allows
us to have both a "-> Machine #1 -> 4 core Node #0 -> AweSim Processor #0"
and a "-> Machine #1 -> 4 core Node #1 -> AweSim Processor #0". Also notice that our default
view ignores the tree, and just shows us two devices: "4 core Node #0" and "4 core
Node #1".
In this example, all other child devices of "4 core Node #0" are "Disabled" for all log
options.
Device groups offer us a potentially simpler alternative - for the user to instantiate a
preconfigured device group. For example, we could have a device group “Dimm DDR2
1GBx2”, which has (inside it) only one child and default archive data (state) for that
child. The figure below shows that the (theoretical) known device “Dimm DDR2 1GBx2”
has inside it a single child device “Dimm Bank #0” that is configured with two dimm‟s
(type DDR2, 1GB each).
Configured as DDR2,
2 dimm (1GB each)
The device GUI for the children of “Dimm DDR2 1GBx2 #0” would look like this:
If we looked at the options and configuration of the device library “-> Machine #1 ->
Dimm DDR2 1GBx2 #0 -> Dimm Bank #0” (either from the GUI or from the console),
we would see that it is already configured as DDR2 with 2 dimm slots (1GB each).
This example demonstrates a broad concept. An existing device that has a more generic
and abstract definition (such as a non-configured “Dimm Bank”) can be wrapped in a
device group to give it an identity as a particular hardware implementation (such as an
already configured “Dimm DDR2 1GBx2”). More generally, any device can be wrapped
by a device group, to give an alternate default configuration for the device‟s state
(archive data).
Building a processor node in SimNow has traditionally been a multi-step process. First
the user would add the "AMD 8th Generation Northbridge Device", and then add one
"AweSim Processor" device for each processing core in the node. These devices then
need to be connected together along the respective "CPU Bus" and "Interrupt / IOAPIC"
connection ports. Once the devices are connected, a user would then need to load a
product ID file so that the simulated devices would represent a real and planned piece of
hardware. In summary, building a Quad-core node in SimNow could take as many as 14
individual steps, and these steps would need to be repeated each time a processor node is
to be added.
A device group can both simplify adding a quad-core node, and present the user with a
hierarchical view. So we will give some examples with quad-core processor nodes.
A device group is not required to specify archive data for its child devices. When such a
known device group is instantiated as a created device, it simply lets its children use their
own default and initial configuration state. We can create an abstract or generic “4 core
Node” device group that does not represent a particular hardware implementation (just
like a non-configured “Dimm Bank” does not represent a particular hardware
implementation, until it is configured).
A device group can optionally specify initial and default archive data (device state) for
each of its child devices. A device group with five children could specify archive data for
0, 1, 2, 3, 4, or all 5 children. We could have an “AMD 4-core CPU xxxx” that specifies
archive data for all five of its children (configured with the (theoretical) product ID file
“amd-xxxx.id”).
This is not the only way we could create a (theoretical) “AMD 4-core CPU xxxx”. A
cleaner idea would be to reuse the non-configured abstract and generic “4 core Node”.
This device group would (externally) be functionally the same as our previous “AMD 4-
core CPU xxxx” example, although it has the additional layer where it cleanly reuses “4
core Node”. We could also reuse “4 core Node” for other device groups that represent a
particular hardware implementation of a 4-core node, such as the (theoretical) “AMD 4-
core CPU yyyy” configured with the (theoretical) product ID file “amd-yyyy.id”. Or a
“DeerHound RevB QuadCore Socket L1” configured with the product ID file
“Family10hDR-L1_B0.id”.
icon file, help file, flags). You specify a file path to save the known device group,
because the wizard will create both a known device group *.bsg file, and an instance of
the known device as a created device inside your current BSD (replacing the devices that
you selected for grouping). The internal preview (left side) shows the child devices inside
the group; the external preview (right side) shows the group as a device. This preview
only shows each device icon, name, number, and internal device connections.
Preview of inside Preview of outside
the device group the device group
Device
Identity
Properties
Figure ?
In the second step, we specify options relative to each child device. For each child's
device state, the resulting known device group can either save the child device's current
state, or it can specify no default device state and thus inherit the default device state for
the particular child device. For example, if a child device is an "AweSim Processor", we
can either save the current configuration for that "AweSim Processor" as the default state
for the known device group we are creating. Or the group's child can just inherit the
defaults of the "AweSim Processor" known device.
For each child device, we can specify internal to external port mappings. This maps an
internal port name to an external port name (a port for the device group). Since existing
external connections are maintained, we automatically require an internal to external port
mapping for an existing external connection. To finish, the wizard requires that the
external port names are unique to the device group, since a device must have unique port
names.
Child Device Name External Port Names
Internal
Port
Names
Figure ?
The "external ports, device state" page shows you all the internal to external port
mappings which are currently specified for the device group. You can also click the
"Add/Remove Ports" button for a particular child device, to open a sub-page that allows
you to add and remove particular port mappings for the child device.
In a child device sub-page, each checkbox turns a particular port mapping on or off. If a
checkbox is grayed out, it is because the device has an existing external connection, thus
requiring the port to be mapped for the device group.
Turn This Row's Port Internal Port Names External Port Names
Mapping On/Off
Figure ?
Clicking "OK" causes the "external ports, device state" page to regenerate its list of ports.
So if you add a port using the checkbox, it will show up on the "external ports, device
state" page.
When you are done defining the device group then simply click the "Finish" button. This
causes the device group to get created. A known device group file is created using the
*.bsg file you specified for "Export to file", and loaded as a known device. The devices
you grouped are swapped (deleted and replaced) with a created device instance of your
new device group. Its internal connections and device state come from the known device.
External connections from the devices you grouped are recreated as connections to your
new created device group. All of this is done automatically by the wizard when you click
"Finish".
You can specify devices to get grouped into an “Unnamed Group” device:
shell.GroupDevices[devices]
Specifically, we can add, remove, and rename the internal-to-external port mappings
between a device child and its parent device group:
And we can specify whether or not to use the created device child‟s device state for each
child device (for if/when the group is exported as a known device):
There is also a shell command to get the options (ie – to print them to the console/stdout).
This can print the values for either options (ExternalPortMap or ExportDeviceState):
We can export a created device group (including the options we set) to a known device
file. To do this, we also specify values for the known device‟s identity as a device:
The previous command only exports the created device group to a file as a known device;
it does not change our existing created device group. However, after we export our
created device to a file, we can then replace our created device with an instance of the
device we exported. By doing this, we give our device a new device identity:
the show devices GUI, right-click a device group, click “Ungroup Device”. Or, in the
console, execute the command:
Million of
Exceeds 100 Instructions per
MIPS. Host CPU second.
Exceeds what
can be
displayed.
Figure 3-19: CPU Invalidation Graph
Write PIO’s.
Exceeded
what can be
displayed.
Read PIO’s.
You can also allow the simulator to take complete control of the mouse and keyboard by
selecting “Special Keyboard→Grab Mouse and keyboard”. To return from this mode,
press and hold Ctrl then Alt, and then release them in reverse order.
In addition to any other support channel you may have, we encourage feedback on any
problems encountered. Please send an email to simnow.support@amd.com.
4 Disk Images
The simulator uses hard-drive images to provide simulated hard disks to the simulated
computer. There are several ways to obtain hard drive-images.
Install your OS onto a hard drive in a real system, then move it to the secondary
drive in a system and use DiskTool to copy the contents of the drive to an “.hdd”
image file.
Make a blank hard-drive image and a DVD-/CD-ROM “ISO” image, and install a
fresh operating system onto the hard-drive image. To make the hard drive and
DVD-/CD-ROM images, refer to Section 4.1, "Creating A Blank Hard-Drive
Image" and Section 13, “DiskTool”, on page 167.
To use a physical DVD-/CD-ROM:
Click on the button or select “View→Show Devices” to open the Device
Window (Figure 3-2, on page 9).
Open the Southbridge's properties window by double-clicking on it, and
choose the “HDD Secondary Channel” tab.
On a Windows host type “\\.\D:” where “D:” is the drive letter for the DVD-
/CD-ROM, and on a Linux host type “/dev/cdrom” in the “Master Drive -
Image Filename” field.
Check the DVD-ROM check box below the Filename field.
Please refer to Section 13, “DiskTool”, on page 167 to find out how to set up a Windows
or Linux hard-drive image for the simulator.
window, as shown in Figure 4-1. It will also open a shell window, as shown in Figure
4-2, that is used to inform the user about all physical drives which DiskTool has detected.
To create a blank disk image click on the "Create Blank Disk Image" button on the right
side of the DiskTool dialog window (see Figure 4-1). A "Save As" dialog will ask you for
the location and image filename that will be created. Choose the location where you want
to store the blank image file and then enter the image filename. Click on the "Save"
button. An additional dialog, see Figure 4-3, is presented that allows you to select how
large the blank image file should be.
Argument Description
-l <path> Directory to load devices from. If used, it
must be first.
-f <file> Open the .bsd file <file>.
-e <file> Execute commands in <file> on startup.
-i <path> Image search path for loading image files.
-m <path> Mediator connection string for network
adapters to use.
Argument Description
-n --novga Disable VGA Window.
-c --nogui Disable GUI (console mode).
-d Disable mouse and keyboard inputs to
simulator.
-r --register Register the simulator with the O/S as an
automation server.
-h --help -? Print this help message.
Table 5-1: Command-Line Arguments
For instance, to open the cheetah_1p.bsd when starting the simulator you can enter the
following:
C:\SimNow\simnow –f cheetah_1p.bsd
You can view the configuration of the simulated machine by clicking on . A window
appears with a graphical representation
Simulator status
of the simulated machine, as shown
CPU Graph
in Figure
Simulation 5-3.
Display
Area Area
Assign the first OS installation ISO image to the IDE Secondary Master Channel of the
hard-disk controller by selecting “File→Set IDE Secondary Master Image...“.
If you don't have access to any ISO images you have two options:
You can download Linux ISO images from fedora.redhat.com. If you are a
MSDN Subscription member you can also download Windows ISO images from
Microsoft's MSDN Subscription Webpage.
You can assign a physical host DVD-/CD-ROM drive to the simulators IDE
Secondary Master Channel and use your host‟s physical DVD-/CD-ROM drive to
install from a CD or DVD media. Section 4, "Disk Images", on page 35 describes
how to assign a physical DVD-/CD-ROM drive
When the OS installation prompts you, eject the current ISO image using "File→Clear
IDE Secondary Master" and insert the next ISO image using "File→Set IDE Secondary
Master". In case you are using a physical DVD/-CD-ROM drive for the OS installation,
eject the media and insert the next media.
The disk-images are now assigned to the device that is connected to the IDE Primary
Master and IDE Secondary Master connector of the hard disk controller, as shown in
Figure 7-25 on page 97.
All disk devices (Primary Master, etc.) by default have the disk journaling feature
turned on, which allows simulations to write to the disk image during normal
operation and not affect the contents of the real disk image. This is useful for
being able to kill a simulation in the middle, for multiple copies of the simulator
running at the same time, etc. Journal contents are saved in BSD checkpoint files
but lost if you don't save a checkpoint before exiting. To change journal settings
or commit journal contents to the hard disk image, go to the Device View Window,
then the AMD-8111™ Southbridge, then the configuration for the hard disk in
question on either the Primary or Secondary IDE controller. Here you can either
commit the contents of the journal to the hard-disk image or turn off journaling
for the hard disk image in question. Turning off journaling is recommended
during the installation process for an operating system.
Copying files into the simulator corresponds to putting data into some media on the Host
which will be inserted into the simulation. The choices for doing this are:
Create an ISO image with the data inside it then get it into your guest OS. Use the
"File→Set IDE Secondary Master Image" item in the Main Window Menu to
insert it into the DVD-ROM simulation, which is by default on the secondary
master position in all BSDs. Finally, mount it in your guest OS.
Use a raw floppy-disk image in a manner similar to the above. It's a lot smaller
and a bit more hassle, so we don't recommend it.
Mount a hard-disk image on the host. (On a Linux host, you can use the
"loopback device").
Use the JumpDrive USB device to copy files into the simulator and out of the
simulator, see. Section A.7.27, “JumpDrive”, on page 254.
Copying files out of the simulator corresponds to putting some data into some media in
the guest which will then be extracted on the host. To do this, mount a hard-drive image
on the host after placing the data on it in the guest. (On a Linux host, you can use the
"loopback device").
The default shell provided with the simulator includes three new commands that allow
the user access to the multiple machine functionality.
The „newmachine‟ command creates a new „emtpy‟ simulation machine. The created new
machine is in no way related to the current machine. Tou can load BSDs, edit device
configurations, etc., in the new machine, and they are completely independent of any
other „machine‟ currently loaded.
The leading number before the prompt identifies which machine is currently the active
machine. All subsequent automation commands typed into the console window are
directed to the current machine.
Argument Description
--nogui Disable Graphical User Interface (GUI).
--gui Enable Graphical User Interface (GUI).
-c Enable console mode.
--novga Disable VGA Window.
--vga Enable VGA Window.
-n Disable VGA Window.
-d Disable mouse and keyboard inputs to
simulator.
+d Enable mouse and keyboard inputs to
simulator.
-i <path> Image search path for loading image files.
-m <path> Mediator connection string for network
adapters to use.
-l <path> Directory to load devices from. If used, it
must be first.
Table 5-2: Newmachine Command Arguments
Usage:
1 simnow> newmachine
2 simnow>
The „switchmachine n‟ command switches the console window to the machine identified
by „n‟. All subsequent automation commands typed into the console window are directed
to the given machine „n‟.
2 simnow> switchmachine 1
1 simnow>
2 simnow>
VGA Window is enabled.
See also Section 5.1, “Command-Line Arguments”, on page 39 for further information
regarding available command-line arguments.
.
To exit a created simulated machine enter „exit‟, as shown in the following example:
1 simnow> exit
2 simnow>
Figure 6-1 shows the layout of the existing “solo.bsd” Device Window. The device
position is not important because the connections between devices are completely
represented by the lines between devices.
3. Select “View→Show Devices” or click on the button to show the blank Device
Window.
4. For each item added, click and drag the icon from the device list on the left side
into the workspace area on the right side of the window.
5. Add the Debugger device. This device needs no connections drawn.
6. Add the AweSim Processor and the AMD 8th Generation Integrated Northbridge.
When you add the AweSim Processor, CPU Simulation Stats are added to the
Main Window.
7. Connect the AweSim Processor and the AMD 8th Generation Integrated
Northbridge by shift-click-dragging from one to the other. When the
“Connections” tab of Device Properties Window appears (shown in Figure 6-2),
choose the CPU Bus 0 for both devices, and click on Ok. The connection appears
as a line between the two devices on the Device Window. Then create an
additional connection between the two devices using the Interrupt/IOAPIC Bus on
each device. The Device Window shows only one line for the two connections
between these devices. You can view the connections for each device by right-
clicking on the device and looking at the “Connections” tab in the Device
Properties Window.
11. Add the Southbridge Device. Connect it to AMD-8151 AGP Tunnel using AMD-
8151 AGP Tunnel HyperTransport Bus 1 and HyperTransport Bus 0. Also,
connect AMD-8111™ to the DIMM device using AMD-8111 System
Management Bus 0 and DIMM‟s Generic Bus.
12. Add the Winbond W83627HF SIO device. This is a Super IO device that supports
keyboard, mouse, and floppy disk. Connect it to Southbridge using Winbond's
Generic Bus and Southbridge's LPC Bus.
13. Add the PCI Bus. Connect it to AMD-8111 Southbridge using both devices' PCI
Bus 0.
14. Add the Memory Device. This will contain the System BIOS image. Connect it to
AMD-8111 Southbridge device using AMD-8111 LPC Bus and the Memory
Device's Generic Bus.
7 Device Configuration
Each section in this chapter provides a description of how to configure device models in
the simulator‟s Device Properties window. These device models include the CPU, CPU
debugger, Northbridge, DIMM memory modules, AMD graphics device, Southbridge,
Super IO, memory device, PCA9548- and PCA9556-SMB, PCI bus, AMD-8131™
PCI-X® device, PCI-X test device, AMD-8132™ PCI-X2 device, Raid device, SMB Hub
device, EXDI server and the USB keyboard and mouse devices. These sections should be
considered as a reference for how to configure a device model and are not intended to
document how to use the model within the simulator.
The full release version of the simulator ships with more devices then the public release
version. Table 7-1 gives an overview of supported devices depending on the simulators
version.
Interfaces
Three interfaces are used in the AweSim device:
CPU Bus 0. This interface is used to issue memory and I/O read and write requests, as
well as cache control and input/output signal messages. This interface is generally
connected to the Northbridge device.
Interrupt Bus. This interface is used to communicate interrupt request and acknowledge
messages. This interface is connected to whichever device is used to generate and control
interrupts - typically the Southbridge device.
System Messages Interface. This interface is used by the processor device to output
ASCII and binary log information.
When the processor device receives a reset, the device resets its internal state in a manner
consistent with a standard x86 processor. No configuration information is modified.
Contents of a BSD
The BSD file contains the current state of all internal processor registers, state variables,
etc. It also contains all configuration information. Any memory configured locally to the
processor is saved in the BSD.
Configuration Options
The Device Properties Window is used to set various processor identification and
behavior options. Figure 7-1 shows the Processor Type tab for the AweSim processor
device. Here you can specify which member of the AMD microprocessor family should
be simulated. The default is a standard AMD microprocessor. See Section A.2.3, Product
Files (*.ID), on page 184.
Check the Log Disassembly check box to log the disassembly of the instructions executed
by the processor model.
Check the Log Register State Changes check box to log all the processor model register
state changes.
Check the Log I/O Read/Writes check box to log all real I/O (not memory I/O) generated
by the processor model.
Check the Log Linear Memory Accesses check box to log all memory accesses based on
linear memory. This logs all 'data' memory accesses generated by the processor model.
This does not log code fetch memory accesses, nor “physical” memory accesses (for
example, page table access-and dirty-bit updates).
Check the Log Exceptions check box to log all exceptions generated by the processor
model.
Log Messages
This device produces log messages to the Message Log Window as specified by the
options in the Message Log Windows (see Section 9 “Logging”, on page 145).
Interfaces
The debugger has no interfaces; the debugger is present if it is in the Device Window. To
add the Debugger Device follow these steps:
Configuration Options
In the Main Window, select “View→Show Debugger”. Click the Attach button to
configure which processor is being debugged.
To use the CPU Debugger, please refer to Section 10.1, “Using the CPU Debugger”, on
page 151.
Log Messages
This device does not create log messages.
The RAM array for each DIMM is sized based on parameters contained in the SPD array.
SPD array bytes 5 and 31 are used to calculate the size of the DIMM's RAM array. If
byte 0 in the SPD array has a value of zero, then the DIMM device does not respond to
any SMBUS read attempts on the module. This indicates to the reading device that an
SPD ROM is not available on the DIMM module. By appropriately setting bytes 5 and
31, and clearing byte 0, the model simulates a valid DIMM that contains no SPD ROM.
Dual data rate (DDR) DIMMs use bidirectional data strobe signals to latch data on
transfers. The Northbridge device contains Programmable Delay Lines (PDLs) that are
used to delay the Data Qualification Signal (DQS) signals so that the edges are centered
on the valid data window. BIOS algorithms are used to locate the valid data window and
adjust the PDLs accordingly.
Physical DIMMs provide 8 bytes of data per access. On the module, the 8 bytes of data
are stored across several memory devices. The data width of the memory devices on the
DIMM (SPD byte 13) determines how many PDLs are used. DIMMs that use 8-bit or 16-
bit memory devices use one PDL per byte of width (eight total PDLs). DIMMs that use
4-bit devices use one PDL per nibble (16 total PDLs).
The memory controller in the AMD Opteron™ processor includes two DDR channels
that are ganged into a single effective 128-bit interface. Each access to memory hits a pair
of 64-bit DIMMs, where one DIMM supplies the lower 64 bits while the other DIMM
supplies the upper 64 bits. Each DIMM must have the same arrangement in size and
number of banks.
For each valid access to DRAM, the memory controller will assert one of eight bank-
select lines (CS7:0). Each bank-select line selects one “virtual bank.” A virtual bank is
the combination of one bank on the lower DIMM, and the corresponding bank on the
upper DIMM. Row and column addresses select the data offset within the virtual bank.
Once the simulation is started, the DIMM Device allocates memory arrays to hold the
DRAM data. One array is allocated for each bank or virtual bank. In the case of 64-bit
memory interfaces, memory arrays are allocated to match the size of the physical banks
on each DIMM. If the memory interface is 128 bits, then the memory arrays are sized to
the sum of the physical bank pairs that make up the virtual banks. For example:
Virtual bank0 is the combination of physical bank0 on DIMM0 and physical bank0 on
DIMM1. If physical bank0 on each DIMM is 32MB in size, then the array allocated for
virtual bank0 is sized at 64MB.
Each virtual bank is handled like it is one large bank, rather than two combined smaller
banks. The model does not distinguish between addresses that hit in the upper physical
bank and addresses that hit in the lower physical bank.
Memory read- and write-messages sent to the DIMM Device use the same structure for
both 128-bit and 64-bit interfaces. Each message includes a bank select field, an address
field, and a data size field. The bank select field implements the CS7:0 lines while the
address field specifies the beginning offset within the bank/virtual bank, and the data size
field specifies the size of the datum.
Interfaces
The DIMM device is implemented as a single-interface device. However, the device
accepts two distinct classes of messages: RAM read/write messages, and SMBUS reads
of SPD data. In most system configurations, the DIMM device is connected to a
Northbridge device's DIMM interface as well as a Southbridge device's SMBUS
interface.
Initialization/Reset State
On creation of the DIMM device, all RAM arrays are set to all ones, and SPD ROM
arrays are cleared. Reset initializes the RAM arrays to all ones, but does not alter the SPD
ROM arrays. Configuration options are not affected by reset.
Contents of a BSD
The RAM arrays, SPD ROM arrays, and all configuration option settings are saved in the
BSD.
Configuration Options
The PDL Error Simulation Control section specifies the type of error that the DIMM
device will generate, when a memory read is attempted and when a Northbridge PDL is
set outside the valid response range. These settings apply to all four simulated DIMMs.
If Enable PDL Error Simulation is selected, then the DIMM device monitors PDL
settings for all RAM reads. The 0xFF option specifies that the return data should be
forced to all ones. The Invert option specifies that the return data should be a bitwise
inversion of the valid data.
The SMB Base Address entry selects the 8-bit address that this DIMM device responds to.
The SMB address is used for the reading of DIMM SPD data
The upper part of the dialog lists some summary information. This information, which is
derived from the SPD data, gives a quick indication of the type of device being
simulated.
The center section of the dialog lists all 256 bytes of data held in the simulated SPD
ROM. The list box provides a description of each byte index in the ROM. If a description
is selected, the corresponding data byte is displayed in the text box to the right.
The Import SPD and Export SPD buttons provide the option of loading and saving SPD
ROM data. The file format is an unformatted binary image, with an extension of “*.spd”.
The bottom section of the dialog is used to configure DDR PDL Response ranges for the
simulated DIMM. PDL response ranges can be individually set for each of 16 PDLs.
Adjusting the Low and High value modifies the response range for a particular PDL.
When an appropriate response range is set for one PDL, the same range can be applied to
all 16 PDLs by clicking on the Match PDLs button. The Reset PDLs button sets all 16
PDL response ranges to their maximum range (0 - 255).
Log Messages
This device does not produce log messages.
The Emerald graphics device is comprised of a standard VGA and the Emerald Graphics
sub device. The graphics display engine automatically switches between the Emerald
Graphics sub device and the VGA as necessary to display the selected video modes, with
only one being able to display at a time. The VGA sub device provides an industry-
standard VGA interface used by BIOS and DOS. The Emerald Graphics device provides
an AGP and PCI graphics device interface controllable either by VESA BIOS extensions
or a video driver. In addition to the VGA standard modes, Emerald Graphics supports a
wide range of graphics modes from 320x200 at 16-bit color up to 2048x1536 at 32-bit
color with either the VESA BIOS extensions or a video driver.
Interfaces
The Emerald graphics device has a PCI slot, PCIe and an AGP bus connection, only one
of which can be used at any time to connect to PCI slots, PCIe or AGP bus ports in other
devices.
A reset will re-load the default PCI configuration registers and place default values in the
Chip and FIFO configuration for the Emerald Graphics device.
Contents of a BSD
The data saved in the BSD depends on the mode the graphics controller was in when the
BSD was saved. If the graphics controller was in VGA mode, the BSD file contains the
contents of all VGA registers, a copy of the 256-Kbyte VGA frame buffer, and all
configuration information. If the graphics controller was in a high-resolution mode (non-
VGA in Windows) the frame buffer, Emerald Graphics registers, and PCI configuration
registers are saved in the BSD. When the BSD file is reloaded, all registers and the frame
buffer are restored, and a display image is captured and displayed in the display window.
Configuration Options
In Figure 7-7, the BIOS File option enables you to load different VGA BIOS ROMs into
the device. The VGA ROM is assumed to be a maximum of 32-Kbytes, and is assigned to
ISA bus address 0x000C0000 - 0x000C7FFF, which is the industry-standard location.
This file must be a standard binary file, with the correct header and checksum
information already incorporated.
The VGA enabled checkbox enables or disables the VGA registers. If it is not checked,
the VGA registers are not updated and the display window will not display from the
VGA frame buffer.
The Accelerator Enabled checkbox enables or disables the graphics accelerator. The
accelerator is enabled by default.
The VESA BIOS Extensions Enabled checkbox enables or disables the VESA BIOS
support. The VESA BIOS Extensions are enabled by default.
When the VGA display window has the focus, any keyboard messages and mouse-click
messages received by the window are routed via a DEVCWINDOWMSG message
through the simulators I/O subsystem. The keyboard or mouse device accepts these
messages and simulates key-presses and key-releases to match the keys. While certain
key combinations do not result in the generation of keyboard messages by the OS, this
does enable you to use the real keyboard to interact with the simulation in many cases.
Table 7-2 shows the subset of "standard" VESA mode numbers supported.
High performance device drivers are available for most operating systems (Windows,
Linux, and Solaris). The Matrox G400 supports full acceleration of all GDI and
DirectDraw functions.
Figure 7-9 shows the integrated components of the Matrox G400 graphics device.
Features and components which are currently not supported by the Matrox G400 graphics
device model have a symbol in the following block diagram.
Up to 2056 x 1536 at
32 bpp
Not Supported!
Primary CRTC
Programmable CPU Graph Area
Ultra-pipelined
Video Scaling
Unit
MAFC Port Advanced 3D Texturing and
Rendering Engine
2D Engine
Color Space
Conversion
32bit VGA
CRTC
128-bit Frame Buffer Memory PCI or AGP
Interface 2x/4x Interface
16- or 32-Mbytes
Figure 7-9: Matrox G400 Block Diagram
SGRAM or SDRAM
Interfaces Local Frame Buffer Memory
The Matrox G400 graphics device has both a PCI bus and an AGP bus connection, only
one of which can be used at any time to connect to PCI bus or AGP bus ports in other
devices.
A reset will re-load the default PCI configuration registers and place default values in the
Chip and FIFO configuration for the Matrox G400 graphics device.
Contents of a BSD
The data saved in the BSD depends on the mode the graphics controller was in when the
BSD was saved. If the graphics controller was in VGA mode, the BSD file contains the
contents of all VGA registers, a copy of the 256-Kbyte VGA frame buffer, and all
configuration information. If the graphics controller was in Matrox Power Graphics
Mode (non-VGA in Windows) the linear frame buffer, Power Graphics registers, and PCI
configuration registers are saved in the BSD. When the BSD file is reloaded, all registers
and the frame buffer are restored, and a display image is captured and displayed in the
display window.
Configuration Options
Figure 7-10 shows the Information tab. The following information describes the active
configuration of the Matrox G400 graphics device.
The Graphics Hardware Model can be set to one of the following models:
Currently there is only support for the Matrox G400 chip with SingleHead feature
support available.
The Graphics BIOS version is the version of the BIOS that is assigned and used by the
graphics device. If you flash the BIOS the version number will change. For more
information about flashing the graphics device BIOS see Figure 7-11.
The Graphics Memory section shows information about the current memory
configuration of the graphics device. Currently supported memory configurations are:
The Configuration tab displays details about the active configuration of the Matrox G400
graphics device.
If you want to change the active configuration, click on the Configuration Tab (see
Figure 7-11).
The Matrox G400 ROM has a maximum size of 32-Kbytes, and is assigned to ISA bus
address 0x000C0000 - 0x000C7FFF, which is the industry-standard location.
The Configuration tab lets you choose from six different Matrox G400 graphics adapters.
For instance, if you prefer to use a Matrox Millennium G400, SingleHead, 16 Mbytes of
SDRAM, with a 300 MHz RAMDAC, instead of the default adapter then select this
adapter from the Millennium G400 Adapters list. To apply the new configuration, click
on the „Ok‟ button.
Note if you make any changes in the Configuration tab you must restart or reset your
simulation before the new configuration will take effect!
to timing, such as the vertical retrace time, will be different. Any software that depends
on exact timing behavior may not function correctly.
The following features are only partially implemented. Any software that depends on
these features may not function correctly.
Supported 2D Features
Bus-Mastering (PCI/AGP)
Raster Operations: 0, ~(D | S), D & S, D & ~S, ~S, (~D) & S, ~D, D ^ S, ~(D
& S), D & S, ~(D ^ S), D, D | ~S, S, (~D) | S, D | S, 1
Hardware Clipping
Software-/Hardware-Cursor
a. Three-Color Cursor
b. XGA Cursor
c. X-Windows Cursor
d. 16-Color Palletized Cursor
Bitblts
a. Two-Operand
b. Transparent Two-Operand
c. With Expansion (Character Drawing) 1bpp
Image Load (ILOAD)
a. Two-operand
b. With Expansion (Character Drawing) 1bpp
Rectangles
a. Patterned Fills
b. Constant Shaded
c. Gouraud Shaded (partially)
d. Texture Mapping (partially)
Trapezoids
a. Constant Shaded
Lines
a. Auto-Lines (line open/line close)
b. Solid-Lines (line open/line close)
8, 15, 16, 24, and 32 Bits Per Pixel video modes
ILOAD Pseudo- DMA Window Transfers
Programmable, transparent BLTer
Linear packed pixel frame buffer
In Power Graphics Mode, the resolution depends on the amount of available memory.
Table 7-5 shows the memory configuration for each standard VESA resolution in pixel
depth.
Or:
Also make sure you have installed the Matrox G400 graphics device drivers. You can
download the latest Matrox Millennium G400 graphic device drivers for Windows and
Linux at http://www.matrox.com/mga/support/drivers/latest/home.cfm.
This device model implements a small subset of 3D features which are used by operating
systems to render graphical user interface components and it does not support enough
features to run most modern 3D applications and games correctly.
Interfaces
The ATI Radeon HD 3870 device has a PCIe connection point. The PCIe port is used for
connectivity upstream to a compatible Northbridge Device. See Section 7.28, "ATI
RS480/RS780/RD790/RD890 Northbridge Devices", on page 138 for more information
A reset will re-load the default GPU and PCI configuration registers. The internal GPU
state will be also set to the ATI Radeon HD 3870 default values.
Contents of a BSD
The data saved in the BSD depends on the mode the graphics controller was in when the
BSD was saved. If the graphics controller was in VGA mode, the BSD file contains a
copy of the 256-Kbyte VGA frame buffer, and all configuration information. If the
graphics controller was in an accelerated graphics mode the entire linear frame buffer, is
saved in the BSD. All modified GPU and PCI configuration registers, and the current
GPU state of all blocks are saved in the BSD. Display device data and display device
connection information are saved as well in the BSD.
When the BSD file is reloaded, the internal GPU state, registers and the frame buffer are
restored, and a display image is captured and displayed in the display window.
1
ATI Radeon HD 3870 device model supports DirectX 9 version (including DirectX 9Ex) and earlier
versions of DirectX. DirectX 10 and DirectX 10.1 are not supported.
Configuration Options
It is recommended to install the latest available ATI Radeon HD 3870 device drivers if
you want to enable and use full DirectX and OpenGL support. Please refer to
http://www.ati.com/drivers for more information about available device drivers.
In most cases the simulated graphics perfromance can be improved by reducing the
simulated video resolution to 800x600 or 1024x768.
To obtain detailed information about this device model and its hardware configuration,
such as memory size and general BIOS information, please open the GUI device property
dialog and then click on the Information tab (see Figure 7-13).
Figure 7-14 shows detailed information about the connected display device, such as
“Basic Display Parameters”, “Standard Timings”, “Color / Estabilished Timings”, and
“Raw Data” (see Figure 7-15).
Additional display devices can be added and used by importing Extended Display
Identification Data (EDID). To import EDID open the GUI device property dialog and
then click on the “Import EDID” button. Automation commands can be used
alternatively, see section A.7.32, ATI Radeon HD 3870, on page 259. EDID versions up
to version 1.3 are supported. EDID files contain 128 byte of user defined EDID
information in binary format.
Note that SimNow does not provide any tools to create EDID binary files.
The Display Device drop down list can be used to select a different display device. By
default the ATI Radeon HD 3870 is connected to the AMD SimNow Display Device.
The following features are not supported in this version of the ATI Radeon HD 3870
device model. Any software that depends on these features may not function correctly.
Interfaces
The Super IO device model has a single interface connection, and is connected to the
LPC connection of the Southbridge device.
The floppy is initialized with no drive image present. Reset clears the controller to an idle
state. If an image is loaded, reset does not unload the image.
COM1 and COM2 are initialized with 9600 Baud, no parity, 8-bit words, 1 stop bit, and
interrupts off.
The parallel port initializes with the data and control ports set to zero. Reset clears these
ports to their initial values.
The following devices have no functionality behind them at this time, with the exception
of their configuration registers. These registers are initialized and reset to the values
specified in the Super I/O specification:
IR
GPIO
MIDI
Joystick
Fan
Contents of a BSD
Floppy
COM1 and COM2
LPT1
IR
GPIO
MIDI
Joystick
Fan
All devices store their current state in the BSD files, as well as any data that may be
buffered at the time of the save. Register content is also saved for all devices.
Configuration Options
The Super I/Os have the capability of setting device breakpoints on an event basis. In this
case, the event is the sequence of writes to access the Super I/O's device configuration
registers. Selecting the PNP Lock/Unlock Registers option in Figure 7-16 activates the
breakpoint anytime the lock and unlock sequence is hit. The other option is to set
breakpoints to trigger whenever any of the device configuration registers are accessed.
The default values of the control registers are read-writable or read only as defined by the
appropriate Super IO specification.
The memory device can also be configured as a LPC flash device. It currently models
2Mb (SST49LF020A), 4Mb (SST49LF040A), 8Mb (SST49LF080A) and 16Mb
(SST49LF160C) flash memory devices. Note that we support two command sequences
used generally by flash memory - SST and ATMEL. User should configure the flash
memory to the appropriate command sequence to get desired results. The SST49LF160C
device uses the ATMEL command sequence while
SST49LF020A/SST49LF040A/SST49LF080A use the SST command sequence.
Interfaces
The memory device has a general-purpose interface that you can connect to any other
type of port. No selection is necessary when connecting this memory device to another
device.
After a reset, the memory device reverts back to the initialization file contents.
Contents of a BSD
The contents of memory, as well as all configuration information, are stored in the BSD.
Configuration Options
The first field of the Memory Configuration tab, shown in Figure 7-17, is the base
address of the device in a hexadecimal value.
The second field is the total size of the memory device, given in decimal value for the
number of 32-Kbyte blocks you would like created (32-Kbyte blocks are used because
non-initialized memory is dynamically allocated when addressed in 32-Kbyte chunks).
The third field is the name of the binary file you use to initialize the memory contents.
The device initializes memory for the content length of the file. If you specify a 512-
Kbyte ROM and use a 256-Kbyte image file, the first 256 Kbytes are initialized. The Init
File selection comes with a browse button for easier selection.
Selecting the Read-Only option turns the memory device into a ROM. Writes to the
device are ignored when the Read-Only option is selected.
Selecting the System BIOS ROM option tells the memory device it is the system BIOS.
The memory device only responds to memory address ranges accompanied by a chip-
select that is generated by the Southbridge device.
Selecting Flash Mode option tells the memory device that it is configured as a flash
memory device. There are two command sequences supported by our flash memory
device - SST and ATMEL, which can be selected by the drop down below.
Selecting the Memory Address Masking option indicates that the address received by the
memory device is masked by a bit mask with the same number of bits as the size of the
memory device (e.g., a 256-Kbyte ROM uses an 18-bit mask, or it is masked by
0x003FFFF). This enables the ROM to be remapped dynamically into different memory
address ranges in conjunction with the aforementioned chip-select.
Selecting the Initialized unwritten memory to (hex): option initializes otherwise not
initialized memory, with a separate field for specifying the byte to use for initialization.
Selecting the Memory is non-cacheable option tells the system if the memory described
by the device is non-cacheable.
Interface
The PCA9548 has one input port and eight output ports, as well as a programmable
interface that directs the switch which output port to forward messages to.
Contents of a BSD
The PCA9548 saves its SMB base address and input pin value.
Configuration Options
Interfaces
The PCA9556 has one output port.
Contents of a BSD
The PCA9556 saves its SMB base address and input pin value.
Configuration Options
The PCA9556 allows you to set its SMB base address and input pin values.
Interface
The Northbridge device has several connection points. It has multiple HyperTransport
bus ports that connects to the other AMD 8th Generation Integrated Northbridge devices,
or to HyperTransport link-capable devices (e.g., AMD-8131 PCI-X device). These ports
are mutually exclusive, and should be connected to only one other device. The
Northbridge also has a memory bus to the DIMM devices. The CPU bus gives connection
points for the CPU. The final port is a system-message bus port for connection with a
Log device. A 940-pin 8th generation processor part (AMD Opteron) has three
HyperTransport ports; a 754-pin 8th generation processor part (AMD Athlon 64) has one
HyperTransport port.
When reset, the Northbridge device takes on all default register values.
Contents of a BSD
The BSD file contains the contents of all Northbridge registers. It also saves the contents
of any tables and the states of all internal devices (the memory controller,
HyperTransport table contents, etc.). When the BSD file is read in, all tables are filled
with past data, and all states are restored to their saved states.
Configuration Options
Figure 7-20 and Figure 7-21 show configuration options for the Northbridge.
If Log HyperTransport Message Routing is selected, the device will log HyperTransport
messages.
Each HyperTransport link can be enabled separately. Each link can be 8- or 16-bits wide.
Only the 940-pin AMD Opteron processor can have three links; a 754-pin AMD Athlon
64 has one HyperTransport port.
The DDR2 Training Properties Dialog contains the lowest and highest values that the
BIOS can program into these registers. While these registers are programmed out of
bounds DRAM access will be corrupted.
Note the DDR2 Training Properties Dialog is only useful for BIOS developer and the
values should only be modified and used by BIOS developers.
Log Messages
If Log PCI Configuration Cycles is selected, the device produces log messages whenever
the PCI configuration data register (0xCFC) is accessed. Log files can get very large.
Reads from this I/O-mapped register produce PCI CONFIG READ messages, and writes
to the register produce PCI CONFIG WRITE messages. The formats of the PCI CONFIG
READ and PCI CONFIG WRITE messages are as follows:
The data value, e, is always one byte (two hex digits) in width. The device will log
multiple messages for PCI configuration accesses that are greater than one byte in width.
For example, a dword read of 0x11223344 from PCI configuration register 0x40 of
device 7, function 1 on bus 0 would produce the following log messages:
Interfaces
The Southbridge devices have several connection points. Possible connection points
include a PCI bus, a SMB bus, a LPC bus, an INT/IOAPIC bus for interrupt signaling,
and ISA and HyperTransport ports depending on the device type. The PCI bus acts as a
host bus (AMD-8111). The SMB connects to devices such as the DIMM or the SMB hub.
The LPC bus provides connectivity to devices such as Super IO's and BIOS ROMs. A
HyperTransport port is used for main connectivity for the AMD-8111 device to the reset
of the system.
When reset, a Southbridge device takes on all default register values as above. The
exception to this is that the CMOS contents remain the same.
Contents of a BSD
The BSD file contains the contents of all registers. It also saves the contents of any
buffers, and states of all internal devices (HDD controllers, PIT, PIC, etc.). When the
BSD file is read in, all buffers are filled with past data, and all states are restored to their
saved states.
For instance, in Figure 7-23 the USB Port 0 is disabled and USB Port 1 and 2 are
enabled.
The CMOS dialogue window, shown in Figure 7-24, gives the user the ability to change
the contents of CMOS. When first created, the CMOS contains all zeroes to force a
CMOS checksum error, resulting in the default settings being loaded by BIOS. The
alternative to this is loading a binary file containing the CMOS desired data. The user can
create this file by entering changes and using the save feature to create the binary file.
All disk devices (Primary Master, etc.) by default have the disk journaling feature turned
on, which allows simulations to write to the disk image during normal operation and not
affect the contents of the real disk image. This is useful for being able to kill a simulation
in the middle, for multiple copies of the simulator running at the same time, etc. Journal
contents are saved in BSD checkpoint files but lost if you don't save a checkpoint before
exiting. To change journal settings or commit journal contents to the hard disk image, go
to the Device View Window, then the AMD-8111 Southbridge, then the configuration for
the hard disk in question on either the Primary or Secondary IDE controller. Here you can
either commit the contents of the journal to the hard-disk image or turn off journaling for
the hard disk image in question.
Turning off journaling is recommended during the installation process for an operating
system.
The Default Base Unit ID is a way of telling the device of the strapping option for ID
selection.
The Generate HT Messages for Interrupts selection specifies whether interrupts go out
the HyperTransport port in a HyperTransport format, or out the INT/IOAPIC bus as a
classic interrupt pin.
Interfaces
The PCI Bus device has two types of interfaces, a bus interface and one or more slot
interfaces. The bus interface connects to a device that provides a PCI bus, such as a
Northbridge. Each PCI-slot interface is capable of connecting to a PCI device, such as a
PCI video controller.
The PCI bus behaves somewhat differently than other AMD SimNow devices. First, the
connection points are not all centered in the middle of the icon; instead each connection
point has a discrete location around the perimeter of the icon to provide a visual
indication that each PCI device is connected to a different PCI slot. Second, the
connection points are exclusive; that is, only one device can connect to each connection
point on the PCI bus, because in a real system one cannot install two PCI cards into a
single PCI slot. It is planned that these new behaviors will be used in other devices when
required.
Since the PCI Bus device does not include any state that is altered during the course of a
simulation, after a reset, the PCI Bus device remains unchanged
Contents of a BSD
The configuration of the PCI bus, including which slots are enabled, the device ID for
each slot and the base IRQ-routing pin for each slot, and the connection points, are saved
in the BSD.
Configuration Options
Figure 7-28 shows the PCI-Bus configuration options.
The third field is an Enable Slot. By default, all slots are disabled. One cannot disable a
slot that has a device connected to it.
Interfaces
The AMD-8131 has two types of interfaces, HyperTransport and PCI buses. It has two
HyperTransport links, HT0 and HT1, that can connected to other non-coherent
HyperTransport link-capable devices. The PCI bus interfaces in the AMD-8131 must be
connected to a PCI bus device, which provides the Slot interfaces with which to connect
devices for simulation.
Contents of a BSD
The entire configuration of the AMD-8131 device, including all state and registers for its
sub devices, is saved in the BSD.
Configuration Options
The only configuration options for AMD-8131 are to enable or disable hot-plug for each
of its PCI-X bridges, as shown in Figure 7-29. You cannot enable or disable hot-plug
after a simulation has already begun.
Interface
AMD-8132 has two types of interfaces, HyperTransport and PCI buses. It has two
HyperTransport links, HT0 and HT1 that can connect to other HyperTransport link-
capable devices. Either HyperTransport link can be set to be the upstream
HyperTransport link. The PCI bus interfaces in the AMD-8132 must be connected to a
PCI Bus device, which provides the Slot interfaces with which to connect devices for
simulation.
Contents of a BSD
The entire configuration of the AMD-8132 chipset, including all state and registers for its
sub devices, is saved in the BSD.
Configuration Options
The Hot Plug tab options for AMD-8132 are to enable or disable hot-plug for each of its
PCI-X bridges, as shown in Figure 7-30. You cannot enable or disable hot-plug after a
simulation has already begun.
Interface
The interface varies from system to system. In the AMD Athlon 64 or AMD Opteron
processor-based system configurations, it can be connected to AMD-8131 PCI-X or
AMD-8111 Southbridge devices.
Contents of a BSD
PCI-X register and interrupt signals are saved in the BSD.
Interrupt can be de-asserted by doing an I/O transaction. Interrupts can also be de-
asserted manually by using the debugger.
Interface
The AMD-8151 has three types of interfaces, HyperTransport, AGP, and INT/IOAPIC
buses. The AMD-8151 has two HyperTransport links, HT0 and HT1, that can connect to
other non-coherent HyperTransport link-capable devices. HT0 should be connected to the
upstream link (the one closest to the host bridge) and HyperTransport1 should be
connected to the downstream link. The AGP interface should be connected to an AGP
graphics device. The INT_IOAPIC bus should be connected to the Southbridge; it routes
interrupt signals from the AGP bus to the Southbridge.
Contents of a BSD
The current state of all PCI configuration registers and any internal state variables are
saved in the BSD.
Configuration Options
The AMD-8151 device allows you to set its Revision number as shown in Figure 7-32.
A simulated volume in the RAID device is represented by an image file and one or more
optional journals. The combination of an image and zero or more optional journals is
used to hold the contents of a simulated volume. While creating a volume assign a disk-
image file to it (e.g., “raid.image 0 imagefilename”). One or more additional journals can
be added to the image file. The image file uses a data block to store the data, and the
journal files use sparse indexing to hold just the blocks that have been changed. Not only
does journaling provide an efficient way to access the data blocks in the simulated
volume, but it also gives the user the flexibility to change the data-block size.
Journals grow in size as the volumes associated with them are accessed (writes of data-
blocks which haven‟t been written before). File-based journals are preferred over in-
memory Journaling if a large number of writes are going to be made to the simulated
volume.
The journal architecture is index-based, consisting of super blocks, index blocks, and data
blocks. This provides a hierarchical indexing mechanism, in which data blocks are
accessed by their LBA (logical block address).
Several performance mechanisms are implemented in the RAID device, including Disk
Block Cache and Last Sector Hit, which can be viewed at any time using the “raid.status
–v” command.
AMD tested the RAID device both on SUSE Linux-64 and a 32-bit version of Windows
2003 Enterprise Server, using stock drivers to drive this model. This model emulates
devices at the volume level, so that the files used to represent the data correspond to
logical volumes, not disks. This model associates one logical volume with one image file.
The model does not represent the timing of any real system, because data becomes
available almost immediately.
The SMB hub device models the combination of two physical devices manufactured by
Philips Semiconductors: the PCA9516 5-channel I2C hub, and the PCA9556 Octal
SMBus and I2C registered interface. In the simulator‟s device model the two devices are
configurable via GPIO x enables segment x, as shown in Figure 7-33.
Interface
The SMB hub has five SMBus interfaces. SMB0 can be connected within the SMB hub
to any of the four other SMBuses (SMB[1..3]). Typically, SMB0 is connected to a
SMBus connection on a Southbridge device, and the other SMBus ports are connected to
other devices in the system.
Contents of a BSD
The current state of all internal registers and any internal state variables are saved in the
BSD.
Configuration Options
The SMB Hub device allows you to enable up to eight GPIO segments (GPIO0 – GPIO7)
to connect SMB devices to SMB hub device, as shown in Figure 7-33.
Interface
The AT24C device has a SMB interface. For example, this device can be connected to a
PCA9548 or PCA9556 device (see Section 7.9, "PCA9548 SMB Device", on page 88 or
Section 7.10, "PCA9556 SMB Device", on page 89).
Contents of a BSD
The current state of all internal registers and any internal state variables are saved in the
BSD.
Configuration Options
The AT24C device can be configure to store an AT24C16A (16Kb), AT24C32A (32Kb),
or AT24C64A (64Kb), 2-Wire Bus serial EEPROM.
The simulator provides a special device known as the EXDI Server Device. This device
can be added to any BSD. When a BSD containing the EXDI Server Device is loaded, the
EXtended Debugging Interface becomes available. This allows client debugging
software, such as CmdeXdi and the Windows kernel debugger, to interact with the
platform being simulated, as if it were a real hardware platform.
The installation of the simulator should provide all the COM registration hooks that are
required. If it does not, here are the steps to manually register the EXDI server:
When running the Windows kernel debugger, you must provide command line
information that tells the debugger how to attach to the EXDI Server. The command line
for this is:
kd -kx exdi:clsid={F65E71B3-FEDC-4FA7-A818-5959CD30DD41}
By default, the simulator uses the keyboard device model to send user‟s keystrokes to the
simulation. For example, when the user presses Enter with the host mouse on the graphics
display window, the simulator sends the internal command, keyboard.key 0x10 0x80, to
its command interpreter. If the user has a USB keyboard or mouse in his simulation, he
can redirect the simulator to use these USB devices for keyboard and mouse input. He
does this by modifying the following simulator registry keys: Gui_Key_Device=usbkey
and Gui_Mouse_Device=usbmouse (from the top-level View→Registry). With these
changes, when the user presses the Enter key in simulation, the simulator will send the
internal command, usbkey.key 0x10 0x80 to its command interpreter. When the user
moves the mouse around the simulator display, the simulator will send commands, such
as usbmouse.mousemouve 10 10 to the interpreter.
XTR has two files, a binary file which has the memory dump of the system and an XML
based text file which contains the log of the events or messages that go in and out a non-
coherent port of the Northbridge, including the DMA signals from devices on the (host‟s)
secondary bus to the DIMM. XTR playback mechanism essentially replaces all the
devices including the Northbridge and downwards and feeds the processor with the data
present in the XTR XML file. The structure of both binary file and XML file is discussed
below.
There are two modes of XTR, XTR Record and XTR Playback. The simulator supports
both modes and one mode does not necessitate the other. The simulator could be used to
record XTR traces only or playback XTR traces generated from other sources as far as
the XTR specification is followed correctly (see Section 7.23.4, “Limitations”, on page
121).
An XTR XML file contains Initialization Data, Events and Instructions. XTR
Initialization data stores the state of CPU just before XTR recording is initiated. This data
is used to initialize the CPU and memory parameters during Playback (the memory itself
is initialized from the contents of the binary file). Any register that does not have
corresponding initialization data in XTR XML file will be initialized with zero. XTR
events fall into two categories:
Dormant Events, which record an event occurrence but do not trigger an event
during playback.
Active events that are recorded in XTR file and are actively triggered during
playback.
IOR, IOW, MEMR, MEMW, RDMSR are examples of dormant events and INTR, APIC,
DMAW, EOT are examples of Active events. XTR Instructions are commands that are
injected in the XTR trace to give special instructions during XTR playback. FJMP (Force
Jump) is an XTR Instruction.
The XTR XML file can easily exceed five Gbytes in size. Please make sure you have
enough physical storage before you start XTR Record.
To playback XTR, please enter the following commands in the simulator‟s console
window:
new
adddevice "Debugger"
adddevice "Awesim Processor"
cpu.type K8
cpu.setname Athlon64
cpu.setnumcores 1
cpu.forcefinegrainedevents 1
cpu.SetStartUpFID 12
adddevice xtrnb
connect "Awesim Processor #0" "CPU Bus 0" "xtrnb #2" "CPU Bus 0"
connect "Awesim Processor #0" "Interrupt / IOAPIC Bus" "xtrnb #2"
"Interrupt / IOAPIC Bus"
cpu.type K8
modifyregistry "System Bus Frequency" "100"
xtrnb.xtrfile <filename.xml>
xtrnb.debug 1
xtrnb.xtrlogfile <filename-playback.log>
SetLogFile <filename.log>
SetLogFileEnabled 1
SetErrorLogFile <filename.errlog>
Reset
The XTR file handle is closed. All the queued events are flushed. Simulated DIMM
memory is flushed and unallocated.
Contents of a BSD
XTR Record contains xtrsvc, which is described below, in addition to modules in the
simulation. For XTR Playback, the BSD is composed of following modules:
In persisted BSD, XTRNB, which is only used during XTR Playback, saves and restores
events that have been queued but not triggered yet, DIMM image and internal states of
the XTRNB. Complete XTR Playback setup also includes AweSim and optionally the
AMD Debugger. Please refer to the documentation of AweSim and AMD Debugger for
their respective contents in the BSD file.
XTR Record does not store any contents in the persistent BSD file.
Log Messages
Messages are logged only by XTRNB, which is only used during XTR Playback. Some
of the following may only be logged when xtrnb.debug is set to enable. Some of the Log
messages are:
Interfaces
XTRNB has eight CPU interfaces and an IO Interrupt / APIC interface to connect to the
AweSim‟s CPU Bus and IO Interrupt / APIC interface respectively. For XTR-UP, only
one CPU interface may be used.
All values in the XML are in hexadecimal except for ICount and Length values which are
always in decimal. Exceptions will be stated as necessary.
.
.
.
</Init>
APIC initialization information.
Currently XTR only supports page size of 4096 bytes. Both the DIMM and MMIO may
be present in the XTR Binary file. The last record in the binary file must have a count of
zero to indicate end of memory image.
7.23.3 ModeFlags
ModeFlags defines some of the states of the CPU that are important for execution. The
upper 32 bits store the Execution Control flags e.g. HLT and <ignore interrupts for 1
instruction when we change stack segment>. The lower 32 bits is redundant from other
initialization values in the XTR initialization but is there to maintain code consistency.
7.23.4 Limitations
Any line in XTR XML file cannot be greater than 255 characters.
Comment start tag "<!--" should start on a new line and end tag "-->" should be
last characters on a line.
The XML attributes are case sensitive but the values are not.
XTR cannot be used to playback BIOS bring-ups.
Currently XTR does not support AMD-V™ platform.
Currently XTR traces recorded off SimNow cannot be played back in other XTR
playback environments.
Although not needed, XTR traces recorded by SimNow might contain data
written by the CPU, e.g. IOW.
The image file used by the JumpDrive is very different from any other image files that
the simulator supports. The only image files that can be loaded are those image files that
are saved by the JumpDrive itself.
Interface
The JumpDrive device has an USB interface that can connect to any USB controller, e.g.,
you can connect the JumpDrive device to the AMD-8111 I/O Hub.
Contents of a BSD
The JumpDrive device saves its entire state, including the contents of its memory, to the
BSD. Any data that exists on the JumpDrive device will be restored when the BSD is
reloaded.
Configuration Options
Most of the automation commands will return an error if the JumpDrive is "plugged into"
the simulated computer, i.e., if the JumpDrive device is connected to a USB controller.
The device must be "not connected", i.e., unplugged, to issue commands that alter the
JumpDrive image.
The mediator is a background daemon task, whose purpose is to bridge the NIC model to
the real network or other SimNow BSDs. The level of network visibility for each
simulator session depends on the format of the MAC address that is used for the
simulated NIC model.
Figure 7-35 shows depicts four simulator sessions communicating via a mediator.
HostName: “thehost”
Simulator 4
Simulator Simulator
1 3
Simulator
2
Alternatively a multi-machine approach can be used in which multiple BSD‟s are loaded
in the same process space. This architecture allows the simulator sessions to pass packets
back and forth without the need for a mediator. Running without a mediator isolates the
simulator sessions from the real network. For more information on running multiple
simulator instances in the same process, see Section 5.3, Multi-Machine Support, on page
45.
Simulator Process
BSD #2 (Machine 2)
04:00:00:00:0:04
10.0.0.2
When a new mediator connection string has been specified, a one-shot link negotiation
will take place within the simulator. Depending on whether a connection was made with
the mediator, the link will appear to be connected or disconnected on the guest. If the
mediator was killed and has since been restarted, then the user will need to perform a
“linkConnect auto”, to restart link negotiation.
Similarly, in a multi-machine setup, the first simulator session will also need to perform a
“linkConnect auto” to ensure that the initial guest sees that other simulator peers have
been connected.
When neither of the above conditions is met, the link appears disconnected in the guest.
It may be necessary to re-start link negotiation via “linkConnect auto”. This will cause
the NIC model to retry a mediator connection or search for any simulator peers, running
in the same process.
Access to real network resources (DHCP servers, etc.). Note that the mediator
will need to be run with supervisor privileges in order to snoop network traffic on
its host.
Bridge communication to other simulator sessions.
Group individual sessions into domains so that identical BSD‟s (with identical
MAC/IP pairs) can be run simultaneously in separate domains.
Provides an optional gateway to block broadcast traffic and to perform Network
Address Translation (NAT) on identical BSD‟s in different domains.
The mediator can route traffic to and from the real network. This operation requires low-
level kernel actions, so the mediator must be run by a supervisor with sufficient OS
privileges. Users may want to have one machine on the subnet dedicated to running the
mediator in this mode. Client machines that connect to the mediator will not require
supervisor privileges.
The mediator is capable of grouping certain simulator sessions into domains. Domains
isolate groups of simulator sessions from each other. This can be useful when the user
wants to run replicated groups of BSD‟s simultaneously. The user need to ensure that
each group of BSD‟s are using unique domains in the mediator by passing an appropriate
connect string to the mediator or supplying it on the command line using the “-m” option,
see Section 5.1, Command-Line Arguments, on page 39.
The mediator can provide one or more gateways to isolate broadcast traffic from your
simulation environment. A gateway will perform NAT in order to ensure that BSD‟s in
different domains get their packets routed appropriately. The simulator sessions using the
mediator‟s gateway can continue to access network resources, but are essentially hidden
from the real network.
Table 7-9 shows command line switches that the mediator accepts:
Switch Description
-p portNum Dictates what port number the mediator will be listening on for
incoming traffic. It specifies the base port address used by the
mediator, and port usage is based off of this number. The
mediator's listening thread uses portNum + 4.
-l Lists possible host adapters that the mediator can use to snoop real
network traffic.
-s Tells the mediator to snoop real network traffic. Requires
supervisor privileges.
-d DeviceNum Tells the mediator which host adapter to use when snooping real
MAC Address beginning with “FA:CD” and having a third byte between 0x00 and 0x20,
are classified as “absolute”. Simulated adapters using this class of MAC Address are
logically equivalent to plugging a real computer into a real network. These sessions can
see real network traffic and are visible to all simulator sessions running via the mediator.
In addition, all broadcast traffic, including ARP‟s are routed to this class of MAC
addresses. Allocations of “absolute” MAC addresses need to be coordinated such that
they are not replicated on the same host subnet.
MAC addresses beginning with “FA:CD” and having a third byte between 0x21 and 0x80
are classified as “fixed”. The simulator adapters using this class of MAC address can
access the real network, but cannot be seen by other simulator sessions outside of its
domain. This class of MAC address allows a user to simultaneously run identical BSD‟s
using unique domains. This class of MAC addresses will not receive broadcast traffic
such as ARP‟s. Allocations of “fixed” MAC addresses need to be coordinated such that
they are not replicated in the same mediator domain.
Visibility: Can only communicate with BSD‟s in the same simulator process
using multiple machines.
Mediator String: N/A
Table 7-14: Isolated Client-Server: Simulator Client 1
Notice also that domains one and two are using identical BSDs that are running
simultaneously. To prevent collisions on the external network, the mediator will not route
broadcast packets to these sessions as they are using a fixed MAC classification. The
gateway will be able to do network address translation (NAT) for each BSD in each
domain to make sure that there are no collisions between the two domains.
The Plug and Play monitor device supports the DDC1 and DDC2B standards. DDC1 is
primitive and a point to point interface. The monitor is always put at transmit-only mode
(DDC1). The monitor will continuously transmit data until the monitor will be turned off
or switched to the bi-directional mode (DDC2). In DDC2 mode the I2C protocol is being
used for data transfers.
Interface
The Plug and Play Monitor device model has a VGA and DVI interface connection.
Connections can be only made to the VGA or DVI interface. It can be connected to the
VGA or DVI connection of a video card device.
Contents of a BSD
The current state of all internal registers and any internal state variables are saved in the
BSD.
The Page Write, Acknowedge Polling, and the Write Protection feature are currently not
supported.
Configuration Options
The Plug and Play Monitor device gives you the opportunity to choose from different
Plug and Play Monitor device models, as shown in Figure 7-38.
Interface
The Southbridge devices have several connection points. Possible connection points
include a PCI bus, an SMB bus, an LPC bus, and an upstream PCIe link. The PCI bus
acts as a host bus, and should connect to a "PCI Bus Device". The SMB connects to
devices such as the DIMM, an SMB hub device, or another SMB compatible endpoint.
The LPC bus provides connectivity to devices such as Super IO chips and BIOS ROMs.
The PCIe port is used for connectivity upstream to a compatible Northbridge Device. See
Section 7.28, "ATI RS480/RS780/RD790/RD890 Northbridge Devices", on page 138 for
more information.
When reset, a Southbridge device takes on all default register values as above. The
exception to this is that the CMOS contents remain the same.
Contents of a BSD
The BSD file contains the contents of all registers. It also saves the contents of any
buffers, and states of all internal devices (HDD controllers, PIT, PIC, etc.). When the
BSD file is read in, all buffers are filled with past data, and all states are restored to their
saved states.
Configuration Options
These Southbridge devices share many configuration properties with the AMD-8111
Southbridge. For more information please refer to Section 7.12, “AMD-8111™
Southbridge Devices – IO Hubs”, on page 94.
Log Messages
These SouthBridge devices have the ability to log messages to the Message Log Window
as specified by the options in the Logging Option tab. These devices can log I/O-mapped
Transactions, Memory-mapped Transactions, and SMI and SCI assertions.
Interface
These Northbridge devices provide an upstream HyperTransport interface for
communication with the Host. The Downstream link is a 2x or 4x PCIe link used for
communication with a SouthBridge device. Several PCIe slot interfaces are also
available. The number of slots varies by part and platform specifications.
Contents of a BSD
The current state of all PCI configuration registers and any internal state variables are
saved in the BSD.
Configuration Options
No configuration options currently.
Log Messages
No logging is provided, other than the global options provided by each device. See
Section 9.3, “I/O Logging”, on page 148 for more information.
For more information on Group Devices, see Section 3.3, “Device Groups", on page 3.3.
Interface
AMD “Istanbul” Device has several connection ports. It has 4 HyperTransport links split
to form 8 sub-links. Each sub-link can connect to a coherent HyperTransport device (such
as another AMD “Istanbul” Device) or a non-Coherent HyperTransport device (such as
AMD-8131™ PCI-X® Controller). These ports are mutually exclusive, and should be
connected to only one other device. “Istanbul” also exposes two DRAM channel
interfaces "DCT0" and "DCT1" to interface with system memory.
Contents of a BSD
See the following sections:
Configuration Options
See the following sections:
Log Messages
See the following sections:
For more information on Group Devices, see Section 3.3, “Device Groups", on page 3.3.
Interface
AMD "Sao Paulo" has several connection ports. It has 4 HyperTransport links split to
form 8 sub-links. Each sub-link can connect to a coherent HyperTransport device (such
as another AMD “Istanbul” Device) or a non-Coherent HyperTransport device (such as
AMD-8131™ PCI-X® Controller). These ports are mutually exclusive, and should be
connected to only one other device. "Sao Paulo" also exposes two DRAM channel
interfaces "DCT0" and "DCT1" to interface with system memory.
Contents of a BSD
See the following sections:
Configuration Options
See the following sections:
Log Messages
See the following sections:
For more information on Group Devices, see Section 3.3, “Device Groups", on page 3.3.
Interface
AMD "Magny-Cours" has several connection ports. It has 4 HyperTransport links split to
form 8 sub-links. Each sub-link can connect to a coherent HyperTransport device (such
as another AMD “Istanbul” Device) or a non-Coherent HyperTransport device (such as
AMD-8131™ PCI-X® Controller). These ports are mutually exclusive, and should be
connected to only one other device. "Magny-Cours" also exposes four DRAM channel
interfaces "DCT0", "DCT1", "DCT2" and "DCT3" to interface with system memory.
Contents of a BSD
See the following sections:
Configuration Options
See the following sections:
Log Messages
See the following sections:
For more information on Group Devices, see Section 3.3, “Device Groups", on page 3.3.
Interface
AMD “DeerHound” Device has several connection ports. It has 4 HyperTransport links
split to form 8 sub-links. Each sub-link can connect to a coherent HyperTransport device
(such as another AMD “Istanbul” Device) or a non-Coherent HyperTransport device
(such as AMD-8131™ PCI-X® Controller). These ports are mutually exclusive, and
should be connected to only one other device. "DeerHound" also exposes two DRAM
channel interfaces "DCT0" and "DCT1" to interface with system memory.
Contents of a BSD
See the following sections:
Configuration Options
See the following sections:
Log Messages
See the following sections:
PCI bus
number
PCI
device
number
List of all PCI
devices
PCI
function
number
The columns
show the low
nibble (0-Fh)
of the PCI
configuration-
space register
The rows
show the high
nibble (00-
F0h) of the
PCI
configuration- PCI
space register configuration-
space
Figure 8-1: PCI Configuration Viewer
Read-only bits cannot be modified using the PCI Config Viewer. Modified values appear
in red in the PCI configuration register list until you click on the „Apply Register
Modifications‟ button or close the PCI Config Viewer dialog.
To change the byte view of the PCI configuration registers to a dword view, check the
„DWORD PCI Access‟ check box.
9 Logging
The simulator provides support for three types of logging:
A message log that can provide detailed text data from simulator devices and
modules.
An error log that provides text messages in response to critical errors or
unexpected conditions.
I/O Logging that provides detailed information about PCI Configuration, I/O and
Memory Space accesses.
The informational log is controlled via the "Message Log Window" dialog box. To view
this dialog, select the "View→Message Log" entry from the Main Window shell menu.
The top-right window contains three checkboxes which allow the user to control whether
messages are displayed in the log window, written to a file, or logged to the AMD
SimNow console. The bottom right window is used to display the informational message
if the "Log to Window" option is selected.
To open the log file the first time a simulation is started, check the "Log To File" box is
checked. The log file will remain open until one of the following events occurs:
The most-recent error log entries may be viewed by selecting the "View→Error Log"
entry from the Main Window menu, shown in Figure 9-2.
The error log file is enabled by checking the "Log to File" check box in the Message log
dialog (Figure 9-2) and setting a filename for the error log. This file is created (or
truncated to zero length if it already exists) and opened whenever a BSD file is opened or
a new BSD is created. The error log is closed whenever the BSD is closed.
Caveat: Currently, devices which route to other devices may appear as if they are
responding to the messages themselves, so bridge devices will likely log
everything that is behind them.
This item, checked by default, disables the Fastpath Memory mechanism when Memory
Space Accesses logging is enabled. If this is unchecked, accesses may not appear in the
log.
What is then logged are slow-path Memory Space Accesses and Fastpath Memory handle
requests. Actual calls to Fastpath Memory, i.e. usage of Fastpath Memory handles, are
not logged.
10 CPU Debugger
10.1 Using the CPU Debugger
The CPU Debugger provides a list of commands and their descriptions when the “?”
command is typed in the bottom line of the debug window, shown in Figure 10-1.
CPU Attach Button
CPU Registers
Disassembly
Instruction
Opcode
cs:[r][e]ip
Memory Dump
Memory Dump
in ASCII
Memory Dump
Address
4. After setting up and enabling the breakpoint(s), enter G on the command line to
resume CPU execution. This will execute the debugger's Go command, returning
the CPU to continuous execution. If a breakpoint is hit, the simulation will pause,
and the debugger will gain attention.
Command Description
Break on the next execution of the instruction located
BX 1234abcd
at linear address, 0x1234ABCD.
Break on the third execution of the instruction located
BX 1234ABCD 2
at linear address, 0x1234ABCD.
Break on the fourth read of the memory location,
BM abcd1234 r 3
0xABCD1234 (linear).
Break on the fourth access (read or write) of the
BM abcd1234 3
memory location, 0xABCD1234 (linear).
BR c001001f r V1 Break on write of value 1 to the MSR C001_001F
BI 80 w 3 Break on the fourth write to I/O address, 0x80.
Table 10-1: Debugger Breakpoint Command Examples
Command Description
Dump memory in byte format, starting at physical
DB 010,p
address, 0x00000010.
Dump memory in word format, starting at linear
DW abcd1234,L
address, 0xABCD1234.
Dump memory in quad word format, starting at linear
DQ c001c0de,L
address, 0xC001C0DE.
Table 10-2: Debugger Memory Dump Command Examples
When using AMD-V™ Virtualization Technology in simulation, the user can tell the
debugger to access memory for either the guest or the host. If multiple guests are running
under a hypervisor, the debugger will acess memory for the last guest that has run. The
user can further qualify an input address using the 'G' (Guest) and 'H' (Host) specifiers.
For example:
Command Description
Dump the SVM host linear memory starting at address
Dd c001c0de,HL
0xC001C0DE.
Dump the last SVM guest linear memory starting at
Dd c001c0de,GL
address 0xC001C0DE.
Dump the SVM host physical memory starting at
Dd c001c0de,HP
address 0xC001C0DE.
Dump the last SVM guest physical memory starting at
Dd c001c0de,GP
address 0xC001C0DE.
Table 10-3: Debugger AMD-V™ Memory Dump Command Examples
If the user omits the 'G' or the 'H' specifier, the debugger will access memory from the
perspective of the attatched CPU's current state.
Command Description
Displays the contents of the MSR with an address of
R M00000250
0x0250.
Displays the contents of the MSR with an address of
R MC001001A
0xC001001A.
Table 10-4: MSR Read Examples
4. MSR registers can be modified by adding a "= Value" suffix on the above
command syntax. Value will be assigned to the MSR register only if the value
does not modify any reserved bits in the MSR. If an attempt is made to modify
any reserved bits, the MSR write is ignored. An example MSR write is shown in
Table 10-5:
5. This command may not allow access to all MSRs that are supported by the CPU
model. To view a list of all registers supported by the R command, enter R? on the
debugger command line.
Command Description
Assigns a value of
R MC001001A = 0000000004000000 0x0000000004000000 to the MSR
with an address of 0xC001001A.
Table 10-5: MSR Write Example
Command Description
Finds the first occurrence of ASCII
q1 0x1000,L 0x2000 "PCI" pattern "PCI" in the given memory
range, 0x1000 - 0x2000.
Same as above but finds all occurrence
qa noncase 0x1000,L 0x2000 "PCI" of the ASCII pattern "PCI" using the
none case-sensitive search algorithm.
Finds all occurrences of the binary-
pattern 0x55 0xAA in the given memory
qa 0xF0000,P 0xFFFF 0x55 0xAA
range, starting at physical address
0xF0000 and ends at 0xF0000+0xFFFF.
Table 10-6: Find Pattern Example
Address values may be suffixed by „,L‟ to specify a linear address (the default) or „,P‟ to
specify a physical address. Addresses may also be specified by their symbol name.
Precede the symbol name with a # character to distinguish it from a hex constant.
11 Debug Interface
The simualtor supports Linux and Windows® based debugging. It is recommended to use
the GDB interface to debug on Linux based hosts. The kernel debugger interface can be
used to debug on Windows based hosts.
EXDI interface (see Section 7.21, "EXDI Server Device", on page 112).
Serial port connection.
The serial ports can be configured so that any data read from or written to the simulated
serial ports is made available to the host machine. The serial ports can each be configured
to do this using either a named-pipe, or the actual serial port hardware.
The automation commands "GetCommPort" and "SetCommPort" are used for this
purpose, see Section A.7.11, “Serial”, on page 243.
Use the serial ports "SetCommPort" command to set the simulated serial port to use a
specific COM port. For example, to set the second serial port in the simulation to use
COM4 for its communication, you would type
The simulator will program the appropriate COM port (COM4 in the above example) to
57600 baud, 8 bits, no parity, 1 stop bit, no flow control.
All characters transmitted by the simulation through the serial port (second serial port in
the above example) will be sent out to the given COM port (COM4 in the above
example). In the same manner, all data received by the simulator through the given COM
port (COM4 in the above example) will appear as received data in the simulated COM
port.
To set the simulated serial port (COM1) to use a named-pipe you would type
Serial:1.SetCommPort pipe
The simulator will program the appropriate COM port (COM1 in the above example) to
use the named-pipe “\\.\pipe\SimNow.Com1” on the host to transfer data between host
and the simulated machine.
The pipe is not created until the first “go” command will be executed. This can be
achieved by clicking on the “go” button followed by a click on the “stop” button. This
command sequence will setup the named-pipe.
If you try to connect the kernel debugger without setting up the named-pipe as described
the kernel debugger will return an error message.
Serial:1.SetMultiplier 1
By default, the multiplier is 100 which means the modeled rate is unchanged. The user
may set it in the range 1 to 100. When set to 1, the modeled rate is 100 times faster than
the baud rate, so the system delays will be that much shorter. See also Section A.7.11,
“Serial”, on page 243.
The following command will connect the kernel debugger to the simulator using a pipe as
communication channel:
We recommend not starting the kernel debugger too early. To achieve best results launch
the kernel debugger after the O/S kernel has loaded and it is trying to establish a
connection with the kernel debugger.
It has been observed that after shutting down the simulator, the port used by the gdb
interface may not become immediately available for reuse. If this happens just shut down
both the simualtor and gdb and start again and the problem should go away.
Start gdb
gdb> set architecture i386:x86-64 <ENTER>
gdb> target remote:2222 <ENTER>
Start gdb
gdb> simnow <ENTER>
Start gdb
gdb> set architecture i386:x86-64 <ENTER>
gdb> target remote:2233 <ENTER>
Note that it is not possible for two simualtor sessions to communicate with each other on
the same host using named-pipes. This is an issue that will be fixed in a future version of
the simulator.
When the simaultor serial port has been configuired to use the host serial port, the
simualtor will open "/dev/ttyS0" or "/dev/ttyS1" (depending on wether it is COM1
or COM2). Note that the user will need to be running the simulator with root privelages
to avoid an access denied error when the simualtor attempts to open the device. The
simulator can communicate with external applications, such as a kernel debugger in this
mode.
12 Command API
The CMDAPI (cmdapi.dll) gives Windows users a way to script the simulator using any
scripting language that can interface with the Microsoft Component Object Model
(COM). It gives you the opportunity to create scripts that instantiate a simulator object.
You can use this instantiated object to execute any of the SimNow™ automation
commands, see Section A.7, “Automation Commands”, on page 233.
CMDAPI is installed and registered whenever a SimNow release package has been
installed successfully.
After instantiating a SimNow.Command object, you can use the following methods to
execute automation commands, and retrieve status.
Exec
The Exec method executes the automation command that arg1 contains.
Parameters
arg1
A string that contains the SimNow automation command to execute. For
example, "debug:0.execcmd t".
arg2
An input string buffer in which SimNow is to place the response from the
command in arg1.
Return Value
Returns true if command completed successfully; otherwise it returns false.
GetLastError
The GetLastError method returns the last error code. If Exec returns false
you can call GetLastError to retrieve the error code.
void GetLastError(arg1);
Parameters
arg1
An input string buffer, in which SimNow will place the last error that was
recorded from the automation interface.
The Perl code in Example 12-1 shows how to instantiate a SimNow.Command object and
how to interact with the SimNow™ CMDAPI interface.
#!perl -w
$Win32::OLE::Warn = 3;
$cmd = Win32::OLE->new('SimNow.Command')
or die "Cannot open SimNow.Command\n";
do {
print "simnow> ";
$CmdLine = <>;
chomp($CmdLine);
if ($CmdLine)
{
if ($cmd->Exec($CmdLine, $MyResponse))
{
print "$MyResponse\n";
}
else
{
$cmd->GetLastError($MyResponse);
print "Cannot Exec: $MyResponse\n";
}
}
} while ($CmdLine);
print "\ndone\n";
Example 12-1: Perl Sample CMDAPI Source Code
13 DiskTool
Use the DiskTool utility to create hard-disk images. DiskTool copies, byte-for-byte, the
contents of a secondary hard disk into an .hdd file. This .hdd file can be loaded as a disk
image in the simulator.
DiskTool runs in two modes, GUI mode, and command-line mode. Double-clicking on
the DiskTool icon, or running DiskTool from the command line with no command line
options, starts DiskTool in GUI mode. If you run DiskTool from the command line and
include any command-line parameters, DiskTool runs in command line mode. To get a
list of the command-line options, run "DiskTool -help".
Option:
G = Copy a physical device to the given image file.
Syntax:
{/G|-G} <DeviceName> <ImageName> [ImageSize]
[ImageSize] = # of sectors of data to copy from the device to the image file
0 = All sectors (this is the default value)
1 = All data to the end of physical partition 1
2 = All data to the end of physical partition 2
3 = All data to the end of physical partition 3
4 = All data to the end of physical partition 4
<Any Other Valid Number> = The number of sectors specified
Example:
disktool –g /dev/hd0 image.hdd 102400
This command reads the first 102400 sectors from device /dev/hd0 and places
them in the image file, image.hdd.
Option:
P = Put the image file <ImageName> to physical device <DeviceName>.
Syntax:
{/P|-P} <DeviceName> <ImageName>
Example:
disktool –p /dev/hd0 image.hdd
This command reads image file image.hdd and writes data to physical device
/dev/hd0.
Option:
E = Erase (Write zeros to all blocks) physical device.
Syntax:
{/E|-E} <DeviceName>
Example:
disktool –e /dev/hd0
Option:
N = Create a new blank image file that represents a freshly formatted device.
Syntax:
{/N|-N} <ImageName> <ImageSize>
Example:
disktool –n image.hdd 102400
This command creates an image file named image.hdd that represents a physical
hard-disk drive containing 102400 sectors (each sector is 512 bytes).
DiskTool displays the names of these devices in the Physical Drives list box, using
names appropriate for the host operating system. When running under Windows, the
Physical Drives list box will show you the physical drives, and in parenthesis, the logical
drive letters that are associated with the partitions on that drive. Selecting any of these
physical devices causes DiskTool to display information about that device in the lower
Drive Information list box.
DiskTool also displays information about all identified devices in a shell window. The
DiskTool shell window is shown in Figure 13-1.
LINUX Note: The list box always shows /dev/fd0 and /dev/fd1. If you click on one of
these and the physical device does not actually exist, the GUI will hang for a short time,
and will then display information in the lower list box indicating that a 4Kb media is
installed in this device DiskTool only recognizes device names /dev/hda through
/dev/hdz. In addition, it looks for the file /proc/ide/hd?/media, and uses the information in
that file to determine whether the device is a hard drive or a DVD/CD drive. If the file
does not exist, or if its contents cannot be parsed, the device will not be listed.
The buttons on the right side of the DiskTool Window correspond to the four command
line options listed above. In addition, there are About and Exit buttons that perform the
obvious function.
When creating a new blank image, or when getting an image from a physical device to an
image file, an additional dialog is presented that allows you to select how large the new
image file should be. The options in this dialog mirrors the [Image Size] options for the
equivalent command line-commands.
After launching DiskTool, you are presented with the interface, shown in Figure 13-2.
When a drive is selected, you have the option to get an image from the drive, put an
image onto the drive, or erase the contents of the drive.
If you erase the contents of the drive, a dialog will ask for confirmation that you actually
wish to permanently destroy the contents of that hard disk.
In case DiskTool displays an “Operation failed!” message box, DiskTool was unable to
lock or unlock the drive. This can happen if, for example, any files or explorer windows
are open on any of the partitions on the selected drive.
For example, if the drive that DiskTool is trying to access has partitions for C: and D:,
and an explorer window is open on any path within D:, then DiskTool won‟t be able to
lock or unlock that drive, and DiskTool will display an “Operation failed!” message box.
If you put an image onto the drive, a dialog will again ask for confirmation that you
actually wish to permanently destroy the contents of that hard disk. Then a dialog
prompts for the location of the image file that should be placed on that hard disk. A
progress bar (Figure 13-4) will inform you of the progress being made.
If you get an image from a drive, a dialog window will prompt for the path of file that
will store the disk image. A progress bar will inform you of the progress being made.
To open the Memory Configurator dialog click on the main menu item View and then
choose Show Memory Configurator (View→Show Memory Configurator).
The Memory Configurator populates each DIMM device with two DIMMs of all
identical size and type. It accounts for DDR and DDR2 and registered or unregistered
memory types as required. The SPD files are loaded using the default path for SPD files
“./Images/<spdfile>”.
Please be advised that memory configurations that are too large will slow down the
simulation significantly and may also confuse some BIOS's.
If you want specific or non-symmetric DIMM configurations please follow these steps:
4. Select an SPD byte description from the large list box. The corresponding data
byte will be shown as two hex digits in the small edit box to the right of the list
box.
5. Type a new hex value in the edit box.
6. Optionally, the altered SPD data can be saved to a file by clicking the Export SPD
button.
7. Click OK to close the configuration property sheet and accept the changes.
If the contents of SPD byte 0 (Number of SPD Bytes Used) is set to zero, the DIMM will
not respond to any SMBUS accesses. This allows simulation of a DIMM module that
does not include an SPD ROM.
1. Open the Device Window from the Main Window Menu (“View→Show
Devices”). Double-click on the Northbridge device. This will bring up the device
Properties Window. Click on Logging Capabilities that will display the logging
options. Select Log PCI Configuration Cycle to and then click OK to accept the
configuration.
2. Select "View→Log Window" from the Main Window Menu. This will bring up a
Message Log dialog box similar to the one shown in Figure 14-3.
3. Log messages will only be captured from devices that have a check beside their
name. If the Northbridge device does not have a check, then check it by clicking
its check box.
4. Select whether to send log messages to the window, and/or to a file. If logging to
a file, enter a filename for the log file.
5. Execute the simulation, and the requested information will be logged.
When the image has been created, it can be loaded into the simulation as described in
Section 5.1.1, “Open a Simulation Definition”, on page 40.
Please note that this mode has interaction issues with the Exceed X-server on Windows if
you're running a Linux hosted version of the simulator and displaying it over a network
to a Windows PC desktop.
How do I Start, Stop, Reset, Press Soft Sleep, or Press Soft Power for simulations?
See Section 3.1, “Tool Bar Buttons”, on page 7.
How does the simulator access media? What are Hard Disk, DVD-/ CD-ROM Disk, or
Floppy Disk images?
See Section 4, “Disk Images”, on page 35.
The usage is relatively self-explanatory from its GUI, and it can also be run from the
command-line. Check out the command-line options via "DiskTool -h".
So, this file allows you to save a running simulation to a file. At any later time, you can
open this file in SimNow to restore the simulation to the same point where you left off.
Where can I find the POST codes/Diagnostic port values of the simulation?
See Section 3.4.1, “SimStats and Diagnostic Ports”, on page 28.
Why doesn’t the simulator work on Linux kernels prior to version 2.6.10?
See Section 2.1, “System Requirements”, on page 3.
Why doesn’t the simulated Operating System correctly recognize the DVD/CD after I
changed the DVD/CD image?
When changing DVD/CD images clear the old image, allow the simulation to run for a
couple of seconds, and then set the new image. This gives the Operating System a chance
to see that the DVD-/CD-ROM is "not ready", and it more correctly detects that the
DVD/CD image has changed. For example:
A Appendix
A.1 Format of Floppy and Hard-Drive Images
The floppy-disk format assumes a standard 1.44 Mbyte floppy disk, consisting of 80
cylinders, 2 heads, and eighteen 512-byte sectors per head (36 sectors per cylinder). The
image file consists simply of each sector, starting with the first sector of the first cylinder
on the first head, and proceeding sequentially through the last sector of the last cylinder
on the second head. The total size of the image file is identical to the total capacity of a
1.44 Mbyte floppy disk, or 1,474,560 bytes.
The hard-disk image is formatted in a similar fashion, with the exception that the total
number of cylinders, heads, and sectors per head varies. Because of this, the hard-disk
image file contains a 512-byte header before the raw data. This 512-byte header is
identical to the information provided by the drive in response to the ATA command
"IDENTIFY". Following the 512-byte header is the data for each sector from the device.
As with the floppy, the data starts with the first sector of the first cylinder on the first
head. Unlike floppies, however, the image file may end before the last sector of the last
cylinder on the last head. If an attempt is made by the simulator, to access data on the
drive image that is beyond the end of the available data (but still within the bounds
defined by the geometry of the device), the simulator will extend the image file
dynamically.
The BSD file contains the contents of all Viper Plus registers. It also saves the contents of
any buffers and the states of all internal devices (HDD controllers, PIT, PIC, etc.). When
the BSD file is read in, all buffers are filled with past data, and all states are restored to
their saved states.
The symbol files that the debugger uses are in a simple text format. Each line contains an
address, length, and symbol name. Any line that starts with a semicolon is considered a
comment. Following is a sample file:
The address value may be an absolute address or a module-relative address. For the latter
case, the load address may be specified when the symbols are loaded into the debugger
with the "load_symbols" command (see Section 10.2, “Debugger Command Reference”,
on page 155).
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A.4 CPUID
This section is an overview of the CPUID feature implementation in the AweSim CPU
processor model.
8th 8th
7th 8th Generation
Feature Generation Generation
Generation Rev. F
(Base) Pre.-Rev. F
Floating-Point Unit
Virtual Mode Extensions
Debugging Extensions1
Page-Size Extension
Time Stamp Counter
AMD Model-Specific Registers
Physical-Address Extensions
Machine Check Exception
CMPXCHG8B Instruction
APIC
SYSENTER and SYSEXIT
Memory Type Range Registers
Page Global Extension
Machine Check Architecture
Conditional Move Instruction
Page Attribute Table
Page Size Extensions (PSE-36)
CFLUSH Instruction
MMX™ Instructions
FXSAVE/FXRSTOR
SSE
SSE2
Hyper Threading
SSE3/PNI
Monitor/MWAIT
Table 15-6: CPUID Standard Feature implementation
1
Only read and write to debug registers is supported, side affects are not implemented.
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supported. A indicates that the returned feature bit is zero and this feature is not
implemented and not supported.
1
Only read and write to debug registers is supported, side effects are not implemented.
2
Controlled by FUSE state.
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However, the simulator does not simulate triple faults. In case a triple fault occurs, the
simulator stops the simulation. The simulation cannot be restarted until a reset is asserted
but the simulation state can be inspected with the simulator‟s debugger.
The simulator does support the RDPMC instruction but there is no logic behind the
simulated performance counter MSRs.
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The code we execute in step 6 will probably be the old code because our page-based
coherency mechanism depends on the software TLB to write protect pages which have
x86 code that has been translated. However, this mechanism protects physical pages
through the virtual mapping mechanism and this mechanism only knows about one
virtual address mapping, not all possible mappings of any code page.
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A.6.1 Notation
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rel8off – Relative address in the current code segment, in 8-bit offset range.
rel16off - Relative address in the current code segment, in 16-bit offset range.
rel32off - Relative address in the current code segment, in 32-bit offset range.
segReg or sReg – Word (16-bit) operand in a segment register.
ST(0) – x87 stack register 0.
ST(i) – x87 stack register i, where i is between 0 and 7.
xmm – Double quadword (128-bit) operand in an XMM register.
xmm1 – Double quadword (128-bit) operand in an XMM register, specified as the
left-most (first) operand in the instruction syntax..
xmm2 – Double quadword (128-bit) operand in an XMM register, specified as the
right-most (second) operand in the instruction syntax.
xmm/mem64 – Quadword (64-bit) operand in a 128-bit XMM register or memory.
xmm/mem128 – Double quadword (128-bit) operand in a 128-bit operand in an
XMM register or memory.
xmm1/mem128 – Double quadword (128-bit) operand in a 128-bit operand in an
XMM register or memory, specified as the left-most (first) operand in the
instruction syntax..
xmm2/mem128 – Double quadword (128-bit) operand in a 128-bit operand in an
XMM register or memory, specified as the right-most (second) operand in the
instruction syntax.
/digit – Indicates that the ModRM byte specifies only one register or memory
(r/m) operand. The digit is specified by the ModRM reg field and is used as an
instruction-opcode extension. Valid digit values range from 0 to 7.
/r – Indicates that the ModRM byte specifies both a register and operand and a
reg/mem (register or memory) operand.
cb, cw, cd ,cp – Specified a code-offset value and possibly a new code-segment
register value. The value following the opcode is either one byte (cb), two bytes
(cw), four bytes (cd), or six bytes (cp).
ib, iw, id – Specifies an immediate-operand value. The opcode determines
whether the value is signed or unsigned. The value following the opcode,
ModRM, or SIB byte is either one byte (ib), two bytes (iw), or four bytes (id).
Word and doubleword values start wit the low-order byte.
+rb, +rw, +rd, +rq – Specifies a register value that is added to the hexadecimal
byte on the left, forming a one-byte opcode. The result is an instruction that
operates on the register specified by the register code. Valid register-code values
are shown in “AMD x86-64 Architecture: Programmer‟s Manual, Volume 3”.
m64 – Specifies a quadword (64-bit) operand in memory.
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+i – Specifies an x87 floating-point stack operand, ST(i). The value is used only
with x87 floating-point instructions. It is added to the hexadecimal byte on the
left, forming a one-byte opcode. Valid values range from 0 to 7.
Instruction
Supported
Mnemonic Opcode Description
AAA 37 Create an unpacked BCD number.
AAD D5 Adjust two BCD digits in AL and AH.
Create a pair of unpacked BCD values
AAM D4
in AH and AL.
Create an unpacked BCD number from
AAS 3F
the contents of the AL register.
ADC AL,imm8 14 ib Add imm8 to AL + CF.
ADC AL,imm16 14 iw Add imm16 to AX + CF.
ADC EAX,imm32 15 id Add imm32 to EAX + CF.
ADC RAX,imm32 15 id Add sign-ext. imm32 to RAX + CF.
ADC reg/mem8,imm8 80 /2 ib Add imm8 to reg/mem8 + CF.
ADC reg/mem16,imm16 81 /2 iw Add imm16 to reg/mem16 + CF.
ADC reg/mem32,imm32 81 /2 id Add imm32 to reg/mem32 + CF.
Add sign-ext. imm32 to reg/mem64 +
ADC reg/mem64,imm32 81 /2 id
CF.
ADC reg/mem16,imm8 83 /2 ib Add sign-ext. imm8 to reg/mem16 + CF.
ADC reg/mem32,imm8 83 /2 ib Add sign-ext. imm8 to reg/mem32 + CF.
ADC reg/mem64,imm8 83 /2 ib Add sign-ext. imm8 to reg/mem64 + CF.
ADC reg/mem8,reg8 10 /r Add reg8 to reg/mem8 + CF.
ADC reg/mem16,reg16 11 /r Add reg16 to reg/mem16 + CF.
ADC reg/mem32,reg32 11 /r Add reg32 to reg/mem32 + CF.
ADC reg/mem64,reg64 11 /r Add reg64 to reg/mem64 + CF.
ADC reg8,reg/mem8 12 /r Add reg/mem8 to reg8 + CF.
ADC reg16,reg/mem16 13 /r Add reg/mem16 to reg16 + CF.
ADC reg32,reg/mem32 13 /r Add reg/mem32 to reg32 + CF.
ADC reg64,reg/mem64 13 /r Add reg/mem64 to reg64 + CF.
ADD AL,imm8 04 ib Add imm8 to AL.
ADD AX,imm16 05 iw Add imm16 to AX.
ADD EAX,imm32 05 id ADD imm32 to EAX.
ADD RAX,imm64 05 id ADD imm64 to RAX.
ADD reg/mem8,imm8 80 /0 ib Add imm8 to reg/mem8.
ADD reg/mem16,imm16 81 /0 iw Add imm16 to reg/mem16.
ADD reg/mem32,imm32 81 /0 id Add imm32 to reg/mem32.
ADD reg/mem64,imm32 81 /0 id Add sign-ext. imm32 to reg/mem64.
ADD reg/mem16,imm8 83 /0 ib Add sign-ext. imm8 to reg/mem16.
ADD reg/mem32,imm8 83 /0 ib Add sign-ext. imm8 to reg/mem32.
ADD reg/mem64,imm8 83 /0 ib Add sign-ext. imm8 to reg/mem64.
ADD reg/mem8,reg8 00 /r Add reg8 to reg/mem8.
ADD reg/mem16,reg16 01 /r Add reg16 to reg/mem16.
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Instruction
Supported
Mnemonic Opcode Description
ADD reg/mem32,reg32 01 /r Add reg32 to reg/mem32.
ADD reg/mem64,reg64 01 /r Add reg64 to reg/mem64.
ADD reg8,reg/mem8 02 /r Add reg/mem8 to reg8.
ADD reg16,reg/mem16 03 /r Add reg/mem16 to reg16.
ADD reg32,reg/mem32 03 /r Add reg/mem32 to reg32.
ADD reg64,reg/mem64 03 /r Add reg/mem64 to reg64.
AND the contents of AL with an
AND AL,imm8 24 ib immediate 8-bit value and store the
result in AL.
AND the contents of AX with an
AND AX,imm16 25 iw immediate 16-bit value and store the
result in AX.
AND the contents of EAX with an
AND EAX,imm32 25 id immediate 32-bit value and store the
result in EAX.
AND the contents of RAX with a sign-
AND RAX,imm32 25 id extended immediate 32-bit value and
store the result in RAX.
AND the contents of reg/mem8 with
AND reg/mem8,imm8 80 /4 ib
imm8.
AND the contents of reg/mem16 with
AND reg/mem16,imm16 81 /4 iw
imm16.
AND the contents of reg/mem32 with
AND reg/mem32,imm32 81 /4 id
imm32.
AND the contents of reg/mem64 with a
AND reg/mem64,imm32 81 /4 id
sign-extended imm32.
AND the contents of reg/mem16 with a
AND reg/mem16,imm8 83 /4 ib
sign-extended 8-bit value.
AND the contents of reg/mem32 with a
AND reg/mem32,imm8 83 /4 ib
sign-extended 8-bit value.
AND the contents of reg/mem64 with a
AND reg/mem64,imm8 83 /4 ib
sign-extended 8-bit value.
AND the contents of an 8-bit register
AND reg/mem8,reg8 20 /r or memory location with the contents
of an 8-bit register.
AND the contents of a 16-bit register
AND reg/mem16,reg16 21 /r or memory location with the contents
of a 16-bit register.
AND the contents of a 32-bit register
AND reg/mem32,reg32 21 /r or memory location with the contents
of a 32-bit register.
AND the contents of a 16-bit register
AND reg/mem64,reg64 21 /r or memory location with the contents
of a 16-bit register.
AND the contents of an 8-bit register
AND reg8,reg/mem8 22 /r with the contents of an 8-bit memory
location or register.
AND the contents of a 16-bit register
AND reg16,reg/mem16 23 /r with the contents of a 16-bit memory
location or register.
AND the contents of a 32-bit register
AND reg32,reg/mem32 23 /r with the contents of a 32-bit memory
location or register.
AND the contents of a 64-bit register
AND reg64,reg/mem64 23 /r with the contents of a 64-bit memory
location or register.
Test whether a 16-bit array index is
BOUND reg16,mem16&mem16 62 /r within the bounds specified by the
two 16-bit values in mem16&mem16.
Test whether a 32-bit array index is
BOUND reg32,mem32&mem32 62 /r within the bounds specified by the
two 32-bit values in mem32&mem32.
Bit scan forward on the contents of
BSF reg16,reg/mmem8 0F BC /r
reg/mem16.
Bit scan forward on the contents of
BSF reg32,reg/mmem32 0F BC /r
reg/mem32.
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Instruction
Supported
Mnemonic Opcode Description
Bit scan forward on the contents of
BSF reg64,reg/mmem64 0F BC /r
reg/mem64.
Bit scan reverse on the contents of
BSR reg16,reg/mmem8 0F BD /r
reg/mem16.
Bit scan reverse on the contents of
BSR reg32,reg/mmem32 0F BD /r
reg/mem32.
Bit scan reverse on the contents of
BSR reg64,reg/mmem64 0F BD /r
reg/mem64.
BSWAP reg32 0F C8 +rd Reverse the byte order of reg32.
BSWAP reg64 0F C8 +rd Reverse the byte order of reg64.
Copy the value of the selected bit to
BT reg/mem16,reg16 0F A3 /r
the carry flag.
Copy the value of the selected bit to
BT reg/mem32,reg32 0F A3 /r
the carry flag.
Copy the value of the selected bit to
BT reg/mem64,reg64 0F A3 /r
the carry flag.
Copy the value of the selected bit to
BT reg/mem16,imm8 0F BA /4 ib
the carry flag.
Copy the value of the selected bit to
BT reg/mem32,imm8 0F BA /4 ib
the carry flag.
Copy the value of the selected bit to
BT reg/mem64,imm8 0F BA /4 ib
the carry flag.
Copy the value of the selected bit to
BTC mem/mem16,reg16 0F BB /r the carry flag, and then complement
the selected bit.
Copy the value of the selected bit to
BTC mem/mem32,reg32 0F BB /r the carry flag, and then complement
the selected bit.
Copy the value of the selected bit to
BTC mem/mem64,reg64 0F BB /r the carry flag, and then complement
the selected bit.
Copy the value of the selected bit to
BTC reg/mem16,imm8 0F BA /7 ib the carry flag, and then complement
the selected bit.
Copy the value of the selected bit to
BTC reg/mem32,imm8 0F BA /7 ib the carry flag, and then complement
the selected bit.
Copy the value of the selected bit to
BTC reg/mem64,imm8 0F BA /7 ib the carry flag, and then complement
the selected bit.
Copy the value of the selected bit to
BTR reg/mem16,reg16 0F B3 /r the carry flag, and then clear the
selected bit.
Copy the value of the selected bit to
BTR reg/mem32,reg32 0F B3 /r the carry flag, and then clear the
selected bit.
Copy the value of the selected bit to
BTR reg/mem64,reg64 0F B3 /r the carry flag, and then clear the
selected bit.
Copy the value of the selected bit to
BTR reg/mem16,imm8 0F BA /6 ib the carry flag, and then clear the
selected bit.
Copy the value of the selected bit to
BTR reg/mem32,imm8 0F BA /6 ib the carry flag, and then clear the
selected bit.
Copy the value of the selected bit to
BTR reg/mem64,imm64 0F BA /6 ib the carry flag, and then clear the
selected bit.
Copy the value of the selected bit to
BTS reg/mem16,reg16 0F AB /r the carry flag, and then set the
selected bit.
Copy the value of the selected bit to
BTS reg/mem32,reg32 0F AB /r the carry flag, and then set the
selected bit.
Copy the value of the selected bit to
BTS reg/mem64,reg64 0F AB /r the carry flag, and then set the
selected bit.
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Instruction
Supported
Mnemonic Opcode Description
Copy the value of the selected bit to
BTS reg/mem16,imm8 0F BA /5 ib the carry flag, and then set the
selected bit.
Copy the value of the selected bit to
BTS reg/mem32,imm8 0F BA /5 ib the carry flag, and then set the
selected bit.
Copy the value of the selected bit to
BTS reg/mem64,imm8 0F BA /5 ib the carry flag, and then set the
selected bit.
Near call with the target specified
CALL rel16off E8 iw
by a 16-bit relative displacement.
Near call with the target specified
CALL rel32off E8 id
by a 32-bit relative displacement.
Near call with the target specified
CALL reg/mem16 FF /2
by reg/mem16.
Near call with the target specified
CALL reg/mem32 FF /2
by reg/mem32.
Near call with the target specified
CALL reg/mem64 FF /2
by reg/mem64.
Far call direct, with the target
CALL FAR pntr16:16 9A cd specified by a far pointer contained
in the instruction.
Far call direct, with the target
CALL FAR pntr16:32 9A cp specified by a far pointer contained
in the instruction.
Far call indirect, with the target
CALL FAR mem16:16 FF /3
specified by a far pointer in memory.
Far call indirect, with the target
CALL FAR mem16:32 FF /3
specified by a far pointer in memory.
CBW 98 Sign-extend AL into AX.
CWDE 98 Sign-extend AX into EAX.
CDQE 98 Sign-extend EAX into RAX.
CWD 99 Sign-extend AX into DX:AX.
CDQ 99 Sign-extend EAX into EDX:EAX.
CQO 99 Sign-extend RAX into RDX:RAX.
CLC F8 Clear the carry flag (CF) to zero.
Clear the direction flag (DF) to
CLD FC
zero.
CFLUSH mem8 0F AE /7 Flush cache line containing mem8.
CMC F5 Complement the carry flag (CF).
CMOVO reg16,reg/mem16 0F 40 /r Move if overflow (OF = 1).
CMOVO reg32,reg/mem32 0F 40 /r Move if overflow (OF = 1).
CMOVO reg64,reg/mem64 0F 40 /r Move if overflow (OF = 1).
CMOVNO reg16,reg/mem16 0F 41 /r Move if not overflow (OF = 0).
CMOVNO reg32,reg/mem32 0F 41 /r Move if not overflow (OF = 0).
CMOVNO reg64,reg/mem64 0F 41 /r Move if not overflow (OF = 0).
CMOVB reg16,reg/mem16 0F 42 /r Move if below (CF = 1).
CMOVB reg32,reg/mem32 0F 42 /r Move if below (CF = 1).
CMOVB reg64,reg/mem64 0F 42 /r Move if below (CF = 1).
CMOVC reg16,reg/mem16 0F 42 /r Move if carry (CF = 1).
CMOVC reg32,reg/mem32 0F 42 /r Move if carry (CF = 1).
CMOVC reg64,reg/mem64 0F 42 /r Move if carry (CF = 1).
CMOVNAE reg16,reg/mem16 0F 42 /r Move if not above or equal (CF = 1).
CMOVNAE reg32,reg/mem32 0F 42 /r Move if not above or equal (CF = 1).
CMOVNAE reg64,reg/mem64 0F 42 /r Move if not above or equal (CF = 1).
CMOVNB reg16,reg/mem16 0F 43 /r Move if not below (CF = 0).
CMOVNB reg32,reg/mem32 0F 43 /r Move if not below (CF = 0).
CMOVNB reg64,reg/mem64 0F 43 /r Move if not below (CF = 0).
CMOVNC reg16,reg/mem16 0F 43 /r Move if not carry (CF = 0).
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Instruction
Supported
Mnemonic Opcode Description
CMOVNC reg32,reg/mem32 0F 43 /r Move if not carry (CF = 0).
CMOVNC reg64,reg/mem64 0F 43 /r Move if not carry (CF = 0).
CMOVAE reg16,reg/mem16 0F 43 /r Move if above or equal (CF = 0).
CMOVAE reg32,reg/mem32 0F 43 /r Move if above or equal (CF = 0).
CMOVAE reg64,reg/mem64 0F 43 /r Move if above or equal (CF = 0).
CMOVZ reg16,reg/mem16 0F 44 /r Move if zero (ZF = 1).
CMOVZ reg32,reg/mem32 0F 44 /r Move if zero (ZF = 1).
CMOVZ reg64,reg/mem64 0F 44 /r Move if zero (ZF = 1).
CMOVE reg16,reg/mem16 0F 44 /r Move if equal (ZF = 1).
CMOVE reg32,reg/mem32 0F 44 /r Move if equal (ZF = 1).
CMOVE reg64,reg/mem64 0F 44 /r Move if equal (ZF = 1).
CMOVNZ reg16,reg/mem16 0F 45 /r Move if not zero (ZF = 0).
CMOVNZ reg32,reg/mem32 0F 45 /r Move if not zero (ZF = 0).
CMOVNZ reg64,reg/mem64 0F 45 /r Move if not zero (ZF = 0).
CMOVNE reg16,reg/mem16 0F 45 /r Move if not equal (ZF = 0).
CMOVNE reg32,reg/mem32 0F 45 /r Move if not equal (ZF = 0).
CMOVNE reg64,reg/mem64 0F 45 /r Move if not equal (ZF = 0).
Move if below or equal (CF = 1 or ZF
CMOVBE reg16,reg/mem16 0F 46 /r
= 1).
Move if below or equal (CF = 1 or ZF
CMOVBE reg32,reg/mem32 0F 46 /r
= 1).
Move if below or equal (CF = 1 or ZF
CMOVBE reg64,reg/mem64 0F 46 /r
= 1).
CMOVNA reg16,reg/mem16 0F 46 /r Move if not above (CF = 1 or ZF = 1).
CMOVNA reg32,reg/mem32 0F 46 /r Move if not above (CF = 1 or ZF = 1).
CMOVNA reg64,reg/mem64 0F 46 /r Move if not above (CF = 1 or ZF = 1).
Move if not below or equal (CF = 0 or
CMOVNBE reg16,reg/mem16 0F 47 /r
ZF = 0).
Move if not below or equal (CF = 0 or
CMOVNBE reg32,reg/mem32 0F 47 /r
ZF = 0).
Move if not below or equal (CF = 0 or
CMOVNBE reg64,reg/mem64 0F 47 /r
ZF = 0).
CMOVA reg16,reg/mem16 0F 47 /r Move if above (CF = 1 or ZF = 0).
CMOVA reg32,reg/mem32 0F 47 /r Move if above (CF = 1 or ZF = 0).
CMOVA reg64,reg/mem64 0F 47 /r Move if above (CF = 1 or ZF = 0).
CMOVS reg16,reg/mem16 0F 48 /r Move if sign (SF = 1).
CMOVS reg32,reg/mem32 0F 48 /r Move if sign (SF = 1).
CMOVS reg64,reg/mem64 0F 48 /r Move if sign (SF = 1).
CMOVNS reg16,reg/mem16 0F 49 /r Move if not sign (SF = 0).
CMOVNS reg32,reg/mem32 0F 49 /r Move if not sign (SF = 0).
CMOVNS reg64,reg/mem64 0F 49 /r Move if not sign (SF = 0).
CMOVP reg16,reg/mem16 0F 4A /r Move if parity (PF = 1).
CMOVP reg32,reg/mem32 0F 4A /r Move if parity (PF = 1).
CMOVP reg64,reg/mem64 0F 4A /r Move if parity (PF = 1).
CMOVPE reg16,reg/mem16 0F 4A /r Move if parity even (PF = 1).
CMOVPE reg32,reg/mem32 0F 4A /r Move if parity even (PF = 1).
CMOVPE reg64,reg/mem64 0F 4A /r Move if parity even (PF = 1).
CMOVNP reg16,reg/mem16 0F 4B /r Move if not parity (PF = 0).
CMOVNP reg32,reg/mem32 0F 4B /r Move if not parity (PF = 0).
CMOVNP reg64,reg/mem64 0F 4B /r Move if not parity (PF = 0).
CMOVPO reg16,reg/mem16 0F 4B /r Move if parity odd (PF = 0).
CMOVPO reg32,reg/mem32 0F 4B /r Move if parity odd (PF = 0).
CMOVPO reg64,reg/mem64 0F 4B /r Move if parity odd (PF = 0).
CMOVL reg16,reg/mem16 0F 4C /r Move if less (SF <> OF).
CMOVL reg32,reg/mem32 0F 4C /r Move if less (SF <> OF).
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Instruction
Supported
Mnemonic Opcode Description
CMOVL reg64,reg/mem64 0F 4C /r Move if less (SF <> OF).
Move if not greater or equal (SF <>
CMOVNGE reg16,reg/mem16 0F 4C /r
OF).
Move if not greater or equal (SF <>
CMOVNGE reg32,reg/mem32 0F 4C /r
OF).
Move if not greater or equal (SF <>
CMOVNGE reg64,reg/mem64 0F 4C /r
OF).
CMOVNL reg16,reg/mem16 0F 4D /r Move if not less (SF = OF).
CMOVNL reg32,reg/mem32 0F 4D /r Move if not less (SF = OF).
CMOVNL reg64,reg/mem64 0F 4D /r Move if not less (SF = OF).
CMOVGE reg16,reg/mem16 0F 4D /r Move if greater or equal (SF = OF).
CMOVGE reg32,reg/mem32 0F 4D /r Move if greater or equal (SF = OF).
CMOVGE reg64,reg/mem64 0F 4D /r Move if greater or equal (SF = OF).
Move if less or equal (ZF = 1 or SF
CMOVLE reg16,reg/mem16 0F 4E /r
<> OF).
Move if less or equal (ZF = 1 or SF
CMOVLE reg32,reg/mem32 0F 4E /r
<> OF).
Move if less or equal (ZF = 1 or SF
CMOVLE reg64,reg/mem64 0F 4E /r
<> OF).
Move if less not greater (ZF = 1 or
CMOVNG reg16,reg/mem16 0F 4E /r
SF <> OF).
Move if less not greater (ZF = 1 or
CMOVNG reg32,reg/mem32 0F 4E /r
SF <> OF).
Move if less not greater (ZF = 1 or
CMOVNG reg64,reg/mem64 0F 4E /r
SF <> OF).
Move if not less or equal (ZF = 0 or
CMOVNLE reg16,reg/mem16 0F 4F /r
SF = OF).
Move if not less or equal (ZF = 0 or
CMOVNLE reg32,reg/mem32 0F 4F /r
SF = OF).
Move if not less or equal (ZF = 0 or
CMOVNLE reg64,reg/mem64 0F 4F /r
SF = OF).
CMOVG reg16,reg/mem16 0F 4F /r Move if greater (ZF = 0 or SF = OF).
CMOVG reg32,reg/mem32 0F 4F /r Move if greater (ZF = 0 or SF = OF).
CMOVG reg64,reg/mem64 0F 4F /r Move if greater (ZF = 0 or SF = OF).
Compare an 8-bit immediate value with
CMP AL,imm8 3C ib
the contents of the AL register.
Compare a 16-bit immediate value with
CMP AX,imm16 3D iw
the contents of the AX register.
Compare a 32-bit immediate value with
CMP EAX,imm32 3D id
the contents of the EAX register.
Compare a 32-bit immediate value with
CMP RAX,imm32 3D id
the contents of the RAX register.
Compare an 8-bit value with the
CMP reg/mem8,imm8 80 /7 ib contents of an 8-bit register or
memory operand.
Compare a 16-bit value with the
CMP reg/mem16,imm16 81 /7 iw contents of a 16-bit register or
memory operand.
Compare a 32-bit value with the
CMP reg/mem32,imm32 81 /7 id contents of a 32-bit register or
memory operand.
Compare a 32-bit signed immediate
CMP reg/mem64,imm32 81 /7 id value with the contents of a 64-bit
register or memory operand.
Compare an 8-bit signed immediate
CMP reg/mem16,imm8 83 /7 ib value with the contents of a 16-bit
register or memory operand.
Compare an 8-bit signed immediate
CMP reg/mem32,imm8 83 /7 id value with the contents of a 32-bit
register or memory operand.
Compare an 8-bit signed immediate
CMP reg/mem64,imm8 83 /7 id value with the contents of a 64-bit
register or memory operand.
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Instruction
Supported
Mnemonic Opcode Description
Compare the contents of an 8-bit
CMP reg/mem8,reg8 38 /r register or memory operand with the
contents of an 8-bit register.
Compare the contents of a 16-bit
CMP reg/mem16,reg16 39 /r register or memory operand with the
contents of a 16-bit register.
Compare the contents of a 32-bit
CMP reg/mem32,reg32 39 /r register or memory operand with the
contents of a 32-bit register.
Compare the contents of a 64-bit
CMP reg/mem64,reg64 39 /r register or memory operand with the
contents of a 64-bit register.
Compare the contents of an 8-bit
CMP reg8,reg/mem8 3A /r register with the contents of an 8-
bit register or memory operand.
Compare the contents of a 16-bit
CMP reg16,reg/mem16 3B /r register with the contents of a 16-
bit register or memory operand.
Compare the contents of a 32-bit
CMP reg32,reg/mem32 3B /r register with the contents of a 32-
bit register or memory operand.
Compare the contents of a 64-bit
CMP reg64,reg/mem64 3B /r register with the contents of a 64-
bit register or memory operand.
Compare the byte at DS:rSI with the
CMPS mem8,mem8 A6 byte at ES:rDI and then increment or
decrement rSI and rDI.
Compare the word at DS:rSI with the
CMPS mem16,mem16 A7 word at ES:rDI and then increment or
decrement rSI and rDI.
Compare the doubleword at DS:rSI with
CMPS mem32,mem32 A7 the doubleword at ES:rDI and then
increment or decrement rSI and rDI.
Compare the quadword at DS:rSI with
CMPS mem64,mem64 A7 the quadword at ES:rDI and then
increment or decrement rSI and rDI.
Compare the byte at DS:rSI with the
CMPSB A6 byte at ES:rDI and then increment or
decrement rSI and rDI.
Compare the word at DS:rSI with the
CMPSW A7 word at ES:rDI and then increment or
decrement rSI and rDI.
Compare the doubleword at DS:rSI with
CMPSD A7 the doubleword at ES:rDI and then
increment or decrement rSI and rDI.
Compare the quadword at DS:rSI with
CMPSQ A7 the quadword at ES:rDI and then
increment or decrement rSI and rDI.
Compare AL register with an 8-bit
register or memory location. If
CMPXCHG reg/mem8,reg8 0F B0 /r equal, copy the second operand to the
first operand. Otherwise, copy the
first operand to AL.
Compare AX register with a 16-bit
register or memory location. If
CMPXCHG reg/mem16,reg16 0F B1 /r equal, copy the second operand to the
first operand. Otherwise, copy the
first operand to AX.
Compare EAX register with a 32-bit
register or memory location. If
CMPXCHG reg/mem32,reg32 0F B1 /r equal, copy the second operand to the
first operand. Otherwise, copy the
first operand to EAX.
Compare RAX register with a 64-bit
register or memory location. If
CMPXCHG reg/mem64,reg64 0F B1 /r equal, copy the second operand to the
first operand. Otherwise, copy the
first operand to RAX.
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Instruction
Supported
Mnemonic Opcode Description
Compare EDX:EAX register to 64-bit
memory location. If equal, set the
zero flag (ZF) to 1 and copy the
CMPXCHG8B 0F C7 /1 m64 ECX:EBX register to the memory
location. Otherwise, copy the memory
location to EDX:EAX and clear the
zero flag.
Executes the CPUID function whose
CPUID 0F A2
number is in the EAX register.
DAA 27 Decimal adjust AL.
DAS 2F Decimal adjusts AL after subtraction.
Decrement the contents of an 8-bit
DEC reg/mem8 FE /1
register or memory location by 1.
Decrement the contents of a 16-bit
DEC reg/mem16 FF /1
register or memory location by 1.
Decrement the contents of a 32-bit
DEC reg/mem32 FF /1
register or memory location by 1.
Decrement the contents of a 64-bit
DEC reg/mem64 FF /1
register or memory location by 1.
Decrement the contents of a 16-bit
DEC reg16 48 +rw
register by 1.
Decrement the contents of a 32-bit
DEC reg32 48 +rd
register by 1.
Perform unsigned division of AX by
the contents of an 8-bit register or
DIV reg/mem8 F6 /6 memory location and store the
quotient in AL and the remainder in
AH.
Perform unsigned division of DX:AX by
the contents of a 16-bit register or
DIV reg/mem16 F7 /6 memory location and store the
quotient in AX and the remainder in
DX.
Perform unsigned division of EDX:EAX
by the contents of a 32-bit register
DIV reg/mem32 F7 /6 or memory location and store the
quotient in EAX and the remainder in
EDX.
Perform unsigned division of RDX:RAX
by the contents of a 64-bit register
DIV reg/mem64 F7 /6 or memory location and store the
quotient in RAX and the remainder in
RDX.
ENTER imm16,0 CB iw 00 Create a procedure stack frame.
Create a nested stack frame for a
ENTER imm16,1 CB iw 01
procedure.
Create a nested stack frame for a
ENTER imm16,imm8 CB iw ib
procedure.
Perform signed division of AX by the
contents of an 8-bit register or
IDIV reg/mem8 F6 /7 memory location and store the
quotient in AL and the remainder in
AH.
Perform signed division of DX:AX by
the contents of a 16-bit register or
IDIV reg/mem16 F7 /7 memory location and store the
quotient in AX and the remainder in
DX.
Perform signed division of EDX:EAX by
the contents of a 32-bit register or
IDIV reg/mem32 F7 /7 memory location and store the
quotient in EAX and the remainder in
EDX.
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Instruction
Supported
Mnemonic Opcode Description
Perform signed division of RDX:RAX by
the contents of a 64-bit register or
IDIV reg/mem64 F7 /7 memory location and store the
quotient in RAX and the remainder in
RDX.
Multiply the contents of AL by the
contents of an 8-bit memory or
IMUL reg/mem8 F6 /5
register operand and put the signed
result in AX.
Multiply the contents of AX by the
contents of a 16-bit memory or
IMUL reg/mem16 F7 /5
register operand and put the signed
result in DX:AX.
Multiply the contents of EAX by the
contents of a 32-bit memory or
IMUL reg/mem32 F7 /5
register operand and put the signed
result in EDX:EAX.
Multiply the contents of RAX by the
contents of a 64-bit memory or
IMUL reg/mem64 F7 /5
register operand and put the signed
result in RDX:RAX.
Multiply the contents of a 16-bit
destination register by the contents
IMUL reg16,reg/mem16 OF AF /r of a 16-bit register or memory
operand and put the signed result the
16-bit destination register.
Multiply the contents of a 32-bit
destination register by the contents
IMUL reg32,reg/mem32 OF AF /r of a 32-bit register or memory
operand and put the signed result the
32-bit destination register.
Multiply the contents of a 64-bit
destination register by the contents
IMUL reg64,reg/mem64 OF AF /r of a 64-bit register or memory
operand and put the signed result the
64-bit destination register.
Multiply the contents of a 16-bit
register or memory operand by a sign-
IMUL reg16,reg/mem16,imm8 6B /r ib extended immediate byte and put the
signed result in the 16-bit
destination register.
Multiply the contents of a 32-bit
register or memory operand by a sign-
IMUL reg32,reg/mem32,imm8 6B /r ib extended immediate byte and put the
signed result in the 32-bit
destination register.
Multiply the contents of a 64-bit
register or memory operand by a sign-
IMUL reg64,reg/mem64,imm8 6B /r ib extended immediate byte and put the
signed result in the 64-bit
destination register.
Multiply the contents of a 16-bit
register or memory operand by a sign-
IMUL reg16,reg/mem16,imm16 69 /r iw extended immediate word and put the
signed result in the 16-bit
destination register.
Multiply the contents of a 32-bit
register or memory operand by a sign-
IMUL reg32,reg/mem32,imm32 69 /r id extended immediate double and put the
signed result in the 32-bit
destination register.
Multiply the contents of a 64-bit
register or memory operand by a sign-
IMUL reg64,reg/mem64,imm32 69 /r id extended immediate double and put the
signed result in the 64-bit
destination register.
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Instruction
Supported
Mnemonic Opcode Description
Input a byte from the port at the
IN AL,imm8 E4 ib address specified by imm8 and put it
into the AL register.
Input a word from the port at the
IN AX,imm8 E5 ib address specified by imm8 and put it
into the AX register.
Input a doubleword from the port at
IN EAX,imm8 E5 ib the address specified by imm8 and put
it into the EAX register.
Input a byte from the port at the
IN AL,DX EC address specified by the DX register
and put it into the AL register.
Input a word from the port at the
IN AX,DX ED address specified by the DX register
and put it into the AX register.
Input a doubleword from the port at
the address specified by the EDX
IN EAX,EDX ED
register and put it into the EAX
register.
Increment the contents of an 8-bit
INC reg/mem8 FE /0
register or memory location by 1.
Increment the contents of a 16-bit
INC reg/mem16 FF /0
register or memory location by 1.
Increment the contents of a 32-bit
INC reg/mem32 FF /0
register or memory location by 1.
Increment the contents of a 64-bit
INC reg/mem64 FF /0
register or memory location by 1.
Increment the contents of a 16-bit
INC reg16 40 +rw
register by 1.
Increment the contents of a 32-bit
INC reg32 40 +rd
register by 1.
Input a byte from the port specified
by DX, put it into the memory
INS mem8,DX 6C
location specified in ES:rDI, and
then increment or decrement rDI.
Input a word from the port specified
by DX, put it into the memory
INS mem16,DX 6D
location specified in ES:rDI, and
then increment or decrement rDI.
Input a doubleword from the port
specified by DX, put it into the
INS mem32,DX 6D
memory location specified in ES:rDI,
and then increment or decrement rDI.
Input a byte from the port specified
by DX, put it into the memory
INSB 6C
location specified in ES:rDI, and
then increment or decrement rDI.
Input a word from the port specified
by DX, put it into the memory
INSW 6D
location specified in ES:rDI, and
then increment or decrement rDI.
Input a doubleword from the port
specified by DX, put it into the
INSD 6D
memory location specified in ES:rDI,
and then increment or decrement rDI.
Calls interrupt service routine
INT imm8 CD ib
specified by interrupt vector imm8.
Calls overflow exception if the
INTO CE
overflow flag is set.
JO rel8off 80 cb Jump if overflow (OF = 1).
JO rel16off 0F 80 cw Jump if overflow (OF = 1).
JO rel32off 0F 80 cd Jump if overflow (OF = 1).
JNO rel8off 71 cb Jump if not overflow (OF = 0)
JNO rel16off 0F 81 cw Jump if not overflow (OF = 0)
JNO rel32off 0F 81 cd Jump if not overflow (OF = 0)
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Instruction
Supported
Mnemonic Opcode Description
JB rel8off 72 cb Jump if below (CF = 1).
JB rel16off 0F 82 cw Jump if below (CF = 1).
JB rel32off 0F 82 cd Jump if below (CF = 1).
JC rel8off 72 cb Jump if carry (CF =1).
JC rel16off 0F 82 cw Jump if carry (CF =1).
JC rel32off 0F 82 cd Jump if carry (CF =1).
JNAE rel8off 72 cb Jump if not above or equal (CF =1).
JNAE rel16off 0F 82 cw Jump if not above or equal (CF =1).
JNAE rel32off 0F 82 cd Jump if not above or equal (CF =1).
JNB rel8off 73 cb Jump if not below (CF = 0).
JNB rel16off 0F 83 cw Jump if not below (CF = 0).
JNB rel32off 0F 83 cd Jump if not below (CF = 0).
JNC rel8off 73 cb Jump if not carry (CF = 0).
JNC rel16off 0F 83 cw Jump if not carry (CF = 0).
JNC rel32off 0F 83 cd Jump if not carry (CF = 0).
JAE rel8off 73 cb Jump if above or equal (CF = 0).
JAE rel16off 0F 83 cw Jump if above or equal (CF = 0).
JAE rel32off 0F 83 cd Jump if above or equal (CF = 0).
JZ rel8off 74 cb Jump if zero (ZF =1).
JZ rel16off 0F 84 cw Jump if zero (ZF =1).
JZ rel32off 0F 84 cd Jump if zero (ZF =1).
JE rel8off 74 cb Jump if equal (ZF =1).
JE rel16off 0F 84 cw Jump if equal (ZF =1).
JE rel32off 0F 84 cd Jump if equal (ZF =1).
JNZ rel8off 75 cb Jump if not zero (ZF = 0).
JNZ rel16off 0F 85 cw Jump if not zero (ZF = 0).
JNZ rel32off 0F 85 cd Jump if not zero (ZF = 0).
JNE rel8off 75 cb Jump if not equal (ZF = 0).
JNE rel16off 0F 85 cw Jump if not equal (ZF = 0).
JNE rel32off 0F 85 cd Jump if not equal (ZF = 0).
Jump if below or equal (CF = 1 or ZF
JBE rel8off 76 cb
= 1).
Jump if below or equal (CF = 1 or ZF
JBE rel16off 0F 86 cw
= 1).
Jump if below or equal (CF = 1 or ZF
JBE rel32off 0F 86 cd
= 1).
JNA rel8off 76 cb Jump if not above (CF = 1 or ZF = 1).
JNA rel16off 0F 86 cw Jump if not above (CF = 1 or ZF = 1).
JNA rel32off 0F 86 cd Jump if not above (CF = 1 or ZF = 1).
Jump if not below or equal (CF = 0 or
JNBE rel8off 77 cb
ZF = 0).
Jump if not below or equal (CF = 0 or
JNBE rel16off 0F 87 cw
ZF = 0).
Jump if not below or equal (CF = 0 or
JNBE rel32off 0F 87 cd
ZF = 0).
JA rel8off 77 cb Jump if above (CF = 0 or ZF = 0).
JA rel16off 0F 87 cw Jump if above (CF = 0 or ZF = 0).
JA rel32off 0F 87 cd Jump if above (CF = 0 or ZF = 0).
JS rel8off 78 cb Jump if sign (SF = 1).
JS rel16off 0F 88 cw Jump if sign (SF = 1).
JS rel32off 0F 88 cd Jump if sign (SF = 1).
JNS rel8off 79 cb Jump if not sign (SF = 0).
JNS rel16off 0F 89 cw Jump if not sign (SF = 0).
JNS rel32off 0F 89 cd Jump if not sign (SF = 0).
JP rel8off 7A cb Jump if parity (PF = 1).
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Instruction
Supported
Mnemonic Opcode Description
JP rel16off 0F 8A cw Jump if parity (PF = 1).
JP rel32off 0F 8A cd Jump if parity (PF = 1).
JPE rel8off 7A cb Jump if parity even (PF = 1).
JPE rel16off 0F 8A cw Jump if parity even (PF = 1).
JPE rel32off 0F 8A cd Jump if parity even (PF = 1).
JNP rel8off 7B cb Jump if not parity (PF = 0).
JNP rel16off 0F 8B cw Jump if not parity (PF = 0).
JNP rel32off 0F 8B cd Jump if not parity (PF = 0).
JPO rel8off 7B cb Jump if parity odd (PF = 0).
JPO rel16off 0F 8B cw Jump if parity odd (PF = 0).
JPO rel32off 0F 8B cd Jump if parity odd (PF = 0).
JL rel8off 7C cb Jump if less (SF <> OF).
JL rel16off 0F 8C cw Jump if less (SF <> OF).
JL rel32off 0F 8C cd Jump if less (SF <> OF).
Jump if not greater or equal (SF <>
JNGE rel8off 7C cb
OF).
Jump if not greater or equal (SF <>
JNGE rel16off 0F 8C cw
OF).
Jump if not greater or equal (SF <>
JNGE rel32off 0F 8C cd
OF).
JNL rel8off 7D cb Jump if not less (SF = OF).
JNL rel16off 0F 8D cw Jump if not less (SF = OF).
JNL rel32off 0F 8D cd Jump if not less (SF = OF).
JGE rel8off 7D cb Jump if greater or equal (SF = OF).
JGE rel16off 0F 8D cw Jump if greater or equal (SF = OF).
JGE rel32off 0F 8D cd Jump if greater or equal (SF = OF).
Jump if less or equal (ZF = 1 or SF
JLE rel8off 7E cb
<> OF).
Jump if less or equal (ZF = 1 or SF
JLE rel16off 0F 8R cw
<> OF).
Jump if less or equal (ZF = 1 or SF
JLE rel32off 0F 8R cd
<> OF).
Jump if not greater (ZF = 1 or SF <>
JNG rel8off 7E cb
OF).
Jump if not greater (ZF = 1 or SF <>
JNG rel16off 0F 8E cw
OF).
Jump if not greater (ZF = 1 or SF <>
JNG rel32off 0F 8E cd
OF).
Jump if not less or equal (ZF = 0 or
JNLE rel8off 7F cb
SF = OF).
Jump if not less or equal (ZF = 0 or
JNLE rel16off 0F 8F cw
SF = OF).
Jump if not less or equal (ZF = 0 or
JNLE rel32off 0F 8F cd
SF = OF).
JG rel8off 7F cb Jump if greater (ZF = 0 or SF = OF).
JG rel16off 0F 8F cw Jump if greater (ZF = 0 or SF = OF).
JG rel32off 0F 8F cd Jump if greater (ZF = 0 or SF = OF).
Jump short if the 16-bit count
JCXZ rel8off E3 cb
register (CX) is zero.
Jump short if the 32-bit count
JCXZ rel16off E3 cb
register (ECX) is zero.
Jump short if the 32-bit count
JCXZ rel32off E3 cb
register (RCX) is zero.
Short jump with the target specified
JMP rel8off EB cb
by an 8-bit signed displacement.
Short jump with the target specified
JMP rel16off E9 cw
by a 16-bit signed displacement.
Short jump with the target specified
JMP rel32off E9 cd
by a 32-bit signed displacement.
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Instruction
Supported
Mnemonic Opcode Description
Near jump with the target specified
JMP reg/mem16 FF /4
reg/mem16.
Near jump with the target specified
JMP reg/mem32 FF /4
reg/mem32.
Near jump with the target specified
JMP reg/mem64 FF /4
reg/mem64.
Far jump direct, with the target
JMP FAR pntr16:16 EA cd specified by a far pointer contained
in the instruction.
Far jump direct, with the target
JMP FAR pntr16:32 EA cp specified by a far pointer contained
in the instruction.
Far jump indirect, with the target
JMP FAR mem16:16 FF /5
specified by a far pointer in memory.
Far jump indirect, with the target
JMP FAR mem16:32 FF /5
specified by a far pointer in memory.
Load the SF, ZF, AF, PF, and CF flags
LAHF 9F
into the AH register.
Load DS:reg16 with a far pointer from
LDS reg16,mem16:16 C5 /r
memory.
Load DS:reg32 with a far pointer from
LDS reg32,mem16:32 C5 /r
memory.
Load ES:reg16 with a far pointer from
LES reg16,mem16:16 C4 /r
memory.
Load ES:reg32 with a far pointer from
LES reg32,mem16:32 C4 /r
memory.
Load FS:reg16 with a far pointer from
LFS reg16,mem16:16 0F B4 /r
memory.
Load FS:reg32 with a far pointer from
LFS reg32,mem16:32 0F B4 /r
memory.
Load GS:reg16 with a far pointer from
LGS reg16,mem16:16 0F B5 /r
memory.
Load GS:reg32 with a far pointer from
LGS reg32,mem16:32 0F B5 /r
memory.
Load SS:reg16 with a far pointer from
LSS reg16,mem16:16 0F B2 /r
memory.
Load SS:reg32 with a far pointer from
LSS reg32,mem16:32 0F B2 /r
memory.
Store effective address in a 16-bit
LEA reg16,mem 8D /r
register.
Store effective address in a 32-bit
LEA reg32,mem 8D /r
register.
Store effective address in a 64-bit
LEA reg64,mem 8D /r
register.
Set the stack pointer SP to the value
LEAVE C9
in the BP register and pop BP.
Set the stack pointer ESP to the
LEAVE C9 value in the EBP register and pop
EBP.
Set the stack pointer RSP to the
LEAVE C9 value in the RBP register and pop
RBP.
Force strong ordering of (serialize)
LFENCE 0F AE E8
load operations.
Load byte at DS:rSI into AL and then
LODS mem8 AC
increment or decrement rSI.
Load word at DS:rSI into AX and then
LODS mem16 AD
increment or decrement rSI.
Load doubleword at DS:rSI into EAX
LODS mem32 AD
and then increment or decrement rSI.
Load quadword at DS:rSI into RAX and
LODS mem64 AD
then increment or decrement rSI.
Load byte at DS:rSI into AL and then
LODSB AC
increment or decrement rSI.
Load word at DS:rSI into AX and then
LODSW AD
increment or decrement rSI.
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Instruction
Supported
Mnemonic Opcode Description
Load doubleword at DS:rSI into EAX
LODSD AD
and then increment or decrement rSI.
Load quadword at DS:rSI into RAX and
LODSQ AD
then increment or decrement rSI.
Decrement rCX and then jump short if
LOOP rel8off E2 cb
rCX is not 0.
Decrement rCX and then jump short if
LOOPE rel8off E1 cb
rCX is not 0 and ZF is 1.
Decrement rCX and then jump short if
LOOPNE rel8off E0 cb
rCX is not 0 and ZF is 0.
Decrement rCX and then jump short if
LOOPNZ rel8off E0 cb
rCX is not 0 and ZF is 0.
Decrement rCX and then jump short if
LOOPZ rel8off E1 cb
rCX is not 0 and ZF is 1.
Force strong ordering of (serialized)
MFENCE 0F AE F0
load and store operations.
Move the contents of an 8-bit
MOV reg/mem8,reg8 88 /r register to an 8-bit destination
register or memory operand.
Move the contents of a 16-bit
MOV reg/mem16,reg16 89 /r register to a 16-bit destination
register or memory operand.
Move the contents of a 32-bit
MOV reg/mem32,reg32 89 /r register to a 32-bit destination
register or memory operand.
Move the contents of a 64-bit
MOV reg/mem64,reg64 89 /r register to a 64-bit destination
register or memory operand.
Move the contents of an 8-bit
MOV reg8,reg/mem8 8A /r register or memory operand to an 8-
bit destination register.
Move the contents of a 16-bit
MOV reg16,reg/mem16 8B /r register or memory operand to a 16-
bit destination register.
Move the contents of a 32-bit
MOV reg32,reg/mem32 8B /r register or memory operand to a 32-
bit destination register.
Move the contents of a 64-bit
MOV reg64,reg/mem64 8B /r register or memory operand to a 64-
bit destination register.
Move the contents of a segment
register to a 16-bit, 32-bit, or 64-
MOV reg16/32/64/mem16,segReg 8C /r
bit destination register or to a 16-
bit memory operand.
Move the contents of a 16-bit
MOV segReg,reg/mem16 8E /r register or memory operand to a
segment register.
Move 8-bit data at a specified memory
MOV AL,moffset8 A0
offset to the AL register.
Move 16-bit data at a specified
MOV AX,moffset16 A1
memory offset to the AX register.
Move 32-bit data at a specified
MOV EAX,moffset32 A1
memory offset to the EAX register.
Move 64-bit data at a specified
MOV RAX,moffset64 A1
memory offset to the RAX register.
Move the contents of the AL register
MOV moffset8,AL A2
to an 8-bit memory offset.
Move the contents of the AX register
MOV moffset16,AX A3
to a 16-bit memory offset.
Move the contents of the EAX register
MOV moffset32,EAX A3
to a 32-bit memory offset.
Move the contents of the RAX register
MOV moffset64,RAX A3
to a 64-bit memory offset.
Move an 8-bit immediate value into an
MOV reg8,imm8 B0 +rb
8-bit register.
Move a 16-bit immediate value into a
MOV reg16,imm16 B8 +rw
16-bit register.
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Instruction
Supported
Mnemonic Opcode Description
Move a 32-bit immediate value into a
MOV reg32,imm32 B8 +rd
32-bit register.
Move a 64-bit immediate value into a
MOV reg64,imm64 B8 +rq
64-bit register.
Move an 8-bit immediate value to an
MOV reg/mem8,imm8 C6 /0
8-bit register or memory operand.
Move a 16-bit immediate value to a
MOV reg/mem16,imm16 C7 /0
16-bit register or memory operand.
Move a 32-bit immediate value to a
MOV reg/mem32,imm32 C7 /0
32-bit register or memory operand.
Move a 64-bit immediate value to a
MOV reg/mem64,imm64 C7 /0
64-bit register or memory operand.
Move 32-bit value from a general-
MOVD xmm,reg/mem32 66 0F 6E /r purpose register or 32-bit memory
location to an XMM register.
Move 64-bit value from a general-
MOVD xmm,reg/mem64 66 0F 6E /r purpose register or 64-bit memory
location to an XMM register.
Move 32-bit value from an XMM
MOVD reg/mem32,xmm 66 0F 7E /r register to a 32-bit general-purpose
register or memory location.
Move 64-bit value from an XMM
MOVD reg/mem64,xmm 66 0F 7E /r register to a 64-bit general-purpose
register or memory location.
Move 32-bit value from a general-
MOVD mmx,reg/mem32 0F 6E /r purpose register or 32-bit memory
location to an MMX register.
Move 64-bit value from a general-
MOVD mmx,reg/mem64 0F 6E /r purpose register or 64-bit memory
location to an MMX register.
Move 32-bit value from an MMX
MOVD reg/mem32,mmx 0F 7E /r register to a 32-bit general-purpose
register or memory location.
Move 64-bit value from an MMX
MOVD reg/mem64,mmx 0F 7E /r register to a 64-bit general-purpose
register or memory location.
Move sign bits 127 and 63 in an XMM
MOVMSKPD reg32,xmm 66 0F 50 /r register t0 a 32-bit general purpose-
register.
Move sign bits 127, 95, 63, 31 in an
MOVMSKPS reg32,xmm 0F 50 /r XMM register to a 32-bit general-
purpose register.
Stores a 32-bit general-purpose
MOVNTI mem32,reg32 0F C3 /r register value into a 32-bit memory
location, minimizing cache pollution.
Stores a 64-bit general-purpose
MOVNTI mem64,reg64 0F C3 /r register value into a 64-bit memory
location, minimizing cache pollution.
Move byte at DS:rSI to ES:rDI, and
MOVS mem8,mem8 A4 then increment or decrement rSI and
rDI.
Move word at DS:rSI to ES:rDI, and
MOVS mem16,mem16 A5 then increment or decrement rSI and
rDI.
Move doubleword at DS:rSI to ES:rDI,
MOVS mem32,mem32 A5 and then increment or decrement rSI
and rDI.
Move quadword at DS:rSI to ES:rDI,
MOVS mem64,mem64 A5 and then increment or decrement rSI
and rDI.
Move byte at DS:rSI to ES:rDI, and
MOVSB A4 then increment or decrement rSI and
rDI.
Move word at DS:rSI to ES:rDI, and
MOVSW A5 then increment or decrement rSI and
rDI.
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Instruction
Supported
Mnemonic Opcode Description
Move doubleword at DS:rSI to ES:rDI,
MOVSD A5 and then increment or decrement rSI
and rDI.
Move quadword at DS:rSI to ES:rDI,
MOVSQ A5 and then increment or decrement rSI
and rDI.
Move the contents of an 8-bit
MOVSX reg16,reg/mem8 0F BE /r register or memory location to a 16-
bit register with sign extension.
Move the contents of an 8-bit
MOVSX reg32,reg/mem8 0F BE /r register or memory location to a 32-
bit register with sign extension.
Move the contents of an 8-bit
MOVSX reg64,reg/mem8 0F BE /r register or memory location to a 64-
bit register with sign extension.
Move the contents of a 16-bit
MOVSX reg32,reg/mem16 0F BF /r register or memory location to a 32-
bit register with sign extension.
Move the contents of a 16-bit
MOVSX reg64,reg/mem16 0F BF /r register or memory location to a 64-
bit register with sign extension.
Move the contents of a 32-bit
MOVSXD reg64,reg/mem32 63 /r register or memory operand to a 64-
bit register with sign extension.
Move the contents of an 8-bit
MOVZX reg16,reg/mem8 0F B6 /r register or memory operand to a 16-
bit register with zero-extension.
Move the contents of an 8-bit
MOVZX reg32,reg/mem8 0F B6 /r register or memory operand to a 32-
bit register with zero-extension.
Move the contents of an 8-bit
MOVZX reg64,reg/mem8 0F B6 /r register or memory operand to a 64-
bit register with zero-extension.
Move the contents of a 16-bit
MOVZX reg32,reg/mem16 0F B7 /r register or memory operand to a 32-
bit register with zero-extension.
Move the contents of a 16-bit
MOVZX reg64,reg/mem16 0F B7 /r register or memory operand to a 64-
bit register with zero-extension.
Multiplies an 8-bit register or
memory operand by the contents of the
MUL reg/mem8 F6 /4
AL register and stores the result in
the AX register.
Multiplies a 16-bit register or
memory operand by the contents of the
MUL reg/mem16 F7 /4
AX register and stores the result in
the DX:AX register.
Multiplies a 32-bit register or
memory operand by the contents of the
MUL reg/mem32 F7 /4
EAX register and stores the result in
the EDX:EAX register.
Multiplies a 64-bit register or
memory operand by the contents of the
MUL reg/mem64 F7 /4
RAX register and stores the result in
the RDX:RAX register.
Performs a tow’s complement negation
NEG reg/mem8 F6 /3 on an 8-bit register or memory
operand.
Performs a tow’s complement negation
NEG reg/mem16 F7 /3 on a 16-bit register or memory
operand.
Performs a tow’s complement negation
NEG reg/mem32 F7 /3 on a 32-bit register or memory
operand.
Performs a tow’s complement negation
NEG reg/mem64 F7 /3 on a 64-bit register or memory
operand.
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Instruction
Supported
Mnemonic Opcode Description
NOP 90 Performs no operation.
Complements the bits in an 8-bit
NOT reg/mem8 F6 /2
register or memory operand.
Complements the bits in a 16-bit
NOT reg/mem16 F7 /2
register or memory operand.
Complements the bits in a 32-bit
NOT reg/mem32 F7 /2
register or memory operand.
Complements the bits in a 64-bit
NOT reg/mem64 F7 /2
register or memory operand.
OR the contents of AL with an
OR AL,imm8 0C ib
immediate 8-bit value.
OR the contents of AX with an
OR AX,imm16 0D iw
immediate 16-bit value.
OR the contents of EAX with an
OR EAX,imm32 0D id
immediate 32-bit value.
OR the contents of RAX with an
OR RAX,imm64 0D id
immediate 64-bit value.
OR the contents of an 8-bit register
OR reg/mem8,imm8 80 /1 ib or memory operand and an immediate 8-
bit value.
OR the contents of a 16-bit register
OR reg/mem16,imm16 81 /1 iw or memory operand and an immediate
16-bit value.
OR the contents of a 32-bit register
OR reg/mem32,imm32 81 /1 id or memory operand and an immediate
32-bit value.
OR the contents of a 64-bit register
OR reg/mem64,imm32 81 /1 id or memory operand and a sign-extended
immediate 32-bit value.
OR the contents of a 16-bit register
OR reg/mem16,imm8 83 /1 ib or memory operand and a sign-extended
immediate 8-bit value.
OR the contents of a 32-bit register
OR reg/mem32,imm8 83 /1 ib or memory operand and a sign-extended
immediate 8-bit value.
OR the contents of a 64-bit register
OR reg/mem64,imm8 83 /1 ib or memory operand and a sign-extended
immediate 8-bit value.
OR the contents of an 8-bit register
OR reg/mem8,reg8 08 /r or memory operand with the contents
of an 8-bit register.
OR the contents of a 16-bit register
OR reg/mem16,reg16 09 /r or memory operand with the contents
of a 16-bit register.
OR the contents of a 32-bit register
OR reg/mem32,reg32 09 /r or memory operand with the contents
of a 32-bit register.
OR the contents of a 64-bit register
OR reg/mem64,reg64 09 /r or memory operand with the contents
of a 64-bit register.
OR the contents of an 8-bit register
OR reg8,reg/mem8 0A /r with the contents of an 8-bit
register or memory operand.
OR the contents of a 16-bit register
OR reg16,reg/mem16 0B /r with the contents of a 16-bit
register or memory operand.
OR the contents of a 32-bit register
OR reg32,reg/mem32 0B /r with the contents of a 32-bit
register or memory operand.
OR the contents of a 64-bit register
OR reg64,reg/mem64 0B /r with the contents of a 64-bit
register or memory operand.
Output the byte in the AL register to
OUT imm8,AL E6 ib the port specified by an 8-bit
immediate value.
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Instruction
Supported
Mnemonic Opcode Description
Output the word in the AX register to
OUT imm8,AX E7 ib the port specified by an 8-bit
immediate value.
Output the doubleword in the EAX
OUT imm8,EAX E7 ib register to the port specified by an
8-bit immediate value.
Output the byte in the AL register to
OUT DX,AL EE
the output port specified in DX.
Output the word in the AX register to
OUT DX,AX EE
the output port specified in DX.
Output the doubleword in the EAX
OUT DX,EAX EE register to the output port specified
in DX.
Output the byte in DS:rSI to the port
OUTS DX,mem8 6E specified in DX, and then increment
or decrement rSI.
Output the word in DS:rSI to the port
OUTS DX,mem16 6F specified in DX, and then increment
or decrement rSI.
Output the doubleword in DS:rSI to
OUTS DX,mem32 6F the port specified in DX, and then
increment or decrement rSI.
Output the byte in DS:rSI to the port
OUTSB 6E specified in DX, and then increment
or decrement rSI.
Output the word in DS:rSI to the port
OUTSW 6F specified in DX, and then increment
or decrement rSI.
Output the doubleword in DS:rSI to
OUTSD 6F the port specified in DX, and then
increment or decrement rSI.
Pop the top of the stack into a 16-
POP reg/mem16 8F /0
bit register or memory location.
Pop the top of the stack into a 32-
POP reg/mem32 8F /0
bit register or memory location.
Pop the top of the stack into a 64-
POP reg/mem64 8F /0
bit register or memory location.
Pop the top of the stack into a 16-
POP reg16 58 +rw
bit register.
Pop the top of the stack into a 32-
POP reg32 58 +rd
bit register.
Pop the top of the stack into a 64-
POP reg64 58 +rq
bit register.
Pop the top of the stack into the DS
POP DS 1F
register.
Pop the top of the stack into the ES
POP ES 07
register.
Pop the top of the stack into the SS
POP SS 17
register.
Pop the top of the stack into the FS
POP FS 0F A1
register.
Pop the top of the stack into the GS
POP GS 0F A9
register.
Pop the DI, SI, BP, SP, BX, DX, CX,
POPA 61
and AX registers.
Pop the EDI, ESI, EBP, ESP, EBX, EDX,
POPAD 61
ECX, and EAX registers.
Pop a word from the stack into the
POPF 9D
FLAGS register.
Pop a doubleword from the stack into
POPFD 9D
the EFLAGS register.
Pop a quadword from the stack into
POPFQ 9D
the RFLAGS register.
Prefetch processor cache line into L1
PREFETCH mem8 0F 0D /0
data cache.
Prefetch processor cache line into L1
PREFETCHW mem8 0F 0D /1
data cache and mark it modified.
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Instruction
Supported
Mnemonic Opcode Description
Move data closer to the processor
PREFETCHNTA mem8 0F 18 /0
using the NTA reference.
Move data closer to the processor
PREFETCHT0 mem8 0F 18 /1
using the T0 reference.
Move data closer to the processor
PREFETCHT1 mem8 0F 18 /2
using the T1 reference.
Move data closer to the processor
PREFETCHT2 mem8 0F 18 /3
using the T2 reference.
Push the contents of a 16-bit
PUSH reg/mem16 FF /6 register or memory operand onto the
stack.
Push the contents of a 32-bit
PUSH reg/mem32 FF /6 register or memory operand onto the
stack.
Push the contents of a 64-bit
PUSH reg/mem64 FF /6 register or memory operand onto the
stack.
Push the contents of a 16-bit
PUSH reg16 50 +rw
register onto the stack.
Push the contents of a 32-bit
PUSH reg32 50 +rd
register onto the stack.
Push the contents of a 64-bit
PUSH reg64 50 +rq
register onto the stack.
Push an 8-bit immediate value (sign-
PUSH imm8 6A extended to 16, 32, or 64 bits) onto
the stack.
Push a 16-=bit immediate value onto
PUSH imm16 68
the stack.
Push the contents of a 32-bit
PUSH imm32 68
register onto the stack.
Push the contents of a 64-bit
PUSH imm64 68
register onto the stack.
PUSH CS 0E Push the CS selector onto the stack.
PUSH SS 16 Push the SS selector onto the stack.
PUSH DS 1E Push the DS selector onto the stack.
PUSH ES 06 Push the ES selector onto the stack.
PUSH FS 0F A0 Push the FS selector onto the stack.
PUSH GS 0F A8 Push the GS selector onto the stack.
PUSHF 9C Push the FLAGS word onto the stack.
PUSHFD 9C Push the EFLAGS word onto the stack.
PUSHFQ 9C Push the RFLAGS word onto the stack.
Rotate the 9 bits consisting of the
RCL reg/mem8,1 D0 /2 carry flag and an 8-bit register or
memory location left 1 bit.
Rotate the 9 bits consisting of the
carry flag and an 8-bit register or
RCL reg/mem8,CL D2 /2
memory location left the number of
bits specified in the CL register.
Rotate the 9 bits consisting of the
carry flag and an 8-bit register or
RCL reg/mem8,imm8 C0 /2 ib memory location left the number of
bits specified by an 8-bit immediate
value.
Rotate the 17 bits consisting of the
RCL reg/mem16,1 D1 /2 carry flag and a 16-bit register or
memory location left 1 bit.
Rotate the 17 bits consisting of the
carry flag and a 16-bit register or
RCL reg/mem16,CL D3 /2
memory location left the number of
bits specified in the CL register.
Rotate the 17 bits consisting of the
carry flag and a 16-bit register or
RCL reg/mem16,imm8 C1 /2 ib memory location left the number of
bits specified by an 8-bit immediate
value.
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Instruction
Supported
Mnemonic Opcode Description
Rotate the 33 bits consisting of the
RCL reg/mem32,1 D1 /2 carry flag and a 32-bit register or
memory location left 1 bit.
Rotate the 33 bits consisting of the
carry flag and a 32-bit register or
RCL reg/mem32,CL D3 /2
memory location left the number of
bits specified in the CL register.
Rotate the 33 bits consisting of the
carry flag and a 32-bit register or
RCL reg/mem32,imm8 C1 /2 ib memory location left the number of
bits specified by an 8-bit immediate
value.
Rotate the 65 bits consisting of the
RCL reg/mem64,1 D1 /2 carry flag and a 64-bit register or
memory location left 1 bit.
Rotate the 65 bits consisting of the
carry flag and a 64-bit register or
RCL reg/mem64,CL D3 /2
memory location left the number of
bits specified in the CL register.
Rotate the 65 bits consisting of the
carry flag and a 64-bit register or
RCL reg/mem64,imm8 C1 /2 ib memory location left the number of
bits specified by an 8-bit immediate
value.
Rotate the 9 bits consisting of the
RCR reg/mem8,1 D0 /3 carry flag and an 8-bit register or
memory location right 1 bit.
Rotate the 9 bits consisting of the
carry flag and an 8-bit register or
RCR reg/mem8,CL D2 /3
memory location right the number of
bits specified in the CL register.
Rotate the 9 bits consisting of the
carry flag and an 8-bit register or
RCR reg/mem8,imm8 C0 /3 ib memory location right the number of
bits specified by an 8-bit immediate
value.
Rotate the 17 bits consisting of the
RCR reg/mem16,1 D1 /3 carry flag and a 16-bit register or
memory location right 1 bit.
Rotate the 17 bits consisting of the
carry flag and a 16-bit register or
RCR reg/mem16,CL D3 /3
memory location right the number of
bits specified in the CL register.
Rotate the 17 bits consisting of the
carry flag and a 16-bit register or
RCR reg/mem16,imm8 C1 /3 ib memory location right the number of
bits specified by an 8-bit immediate
value.
Rotate the 33 bits consisting of the
RCR reg/mem32,1 D1 /3 carry flag and a 32-bit register or
memory location right 1 bit.
Rotate the 33 bits consisting of the
carry flag and a 32-bit register or
RCR reg/mem32,CL D3 /3
memory location right the number of
bits specified in the CL register.
Rotate the 33 bits consisting of the
carry flag and a 32-bit register or
RCR reg/mem32,imm8 C1 /3 ib memory location right the number of
bits specified by an 8-bit immediate
value.
RCL reg/mem64,1
Rotate the 65 bits consisting of the
D1 /3 carry flag and a 64-bit register or
memory location right 1 bit.
RCR
Rotate the 65 bits consisting of the
carry flag and a 64-bit register or
RCR reg/mem64,CL D3 /3
memory location right the number of
bits specified in the CL register.
212 Appendix A
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Instruction
Supported
Mnemonic Opcode Description
Rotate the 65 bits consisting of the
carry flag and a 64-bit register or
RCR reg/mem64,imm8 C1 /3 ib memory location right the number of
bits specified by an 8-bit immediate
value.
RET C3 Near return to the calling procedure.
Near return to the calling procedure
RET imm16 C2 iw and then pop of the specified number
of bytes from the stack.
RETF CB Far return to the calling procedure.
Far return to the calling procedure
RETF imm16 CA iw and then pop of the specified number
of bytes from the stack.
Rotate an 8-bit register or memory
ROL reg/imm8,1 D0 /0
operand left 1 bit.
Rotate an 8-bit register or memory
ROL reg/mem8,CL D2 /0 operand left the number of bits
specified in the CL register.
Rotate an 8-bit register or memory
operand left the number of bits
ROL reg/mem8,imm8 C0 /0 ib
specified by an 8-bit immediate
value.
Rotate a 16-bit register or memory
ROL reg/imm16,1 D1 /0
operand left 1 bit.
Rotate a 16-bit register or memory
ROL reg/mem16,CL D3 /0 operand left the number of bits
specified in the CL register.
Rotate a 16-bit register or memory
operand left the number of bits
ROL reg/mem16,imm8 C1 /0 ib
specified by an 8-bit immediate
value.
Rotate a 32-bit register or memory
ROL reg/imm32,1 D1 /0
operand left 1 bit.
Rotate a 32-bit register or memory
ROL reg/mem32,CL D3 /0 operand left the number of bits
specified in the CL register.
Rotate a 32-bit register or memory
operand left the number of bits
ROL reg/mem32,imm8 C1 /0 ib
specified by an 8-bit immediate
value.
Rotate a 64-bit register or memory
ROL reg/imm64,1 D1 /0
operand left 1 bit.
Rotate a 64-bit register or memory
ROL reg/mem64,CL D3 /0 operand left the number of bits
specified in the CL register.
Rotate a 64-bit register or memory
operand left the number of bits
ROL reg/mem64,imm8 C1 /0 ib
specified by an 8-bit immediate
value.
Rotate an 8-bit register or memory
ROR reg/imm8,1 D0 /0
operand right 1 bit.
Rotate an 8-bit register or memory
ROR reg/mem8,CL D2 /0 operand right the number of bits
specified in the CL register.
Rotate an 8-bit register or memory
operand right the number of bits
ROR reg/mem8,imm8 C0 /0 ib
specified by an 8-bit immediate
value.
Rotate a 16-bit register or memory
ROR reg/imm16,1 D1 /0
operand left 1 bit.
Rotate a 16-bit register or memory
ROR reg/mem16,CL D3 /0 operand right the number of bits
specified in the CL register.
Rotate a 16-bit register or memory
operand right the number of bits
ROR reg/mem16,imm8 C1 /0 ib
specified by an 8-bit immediate
value.
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Instruction
Supported
Mnemonic Opcode Description
Rotate a 32-bit register or memory
ROR reg/imm32,1 D1 /0
operand left 1 bit.
Rotate a 32-bit register or memory
ROR reg/mem32,CL D3 /0 operand right the number of bits
specified in the CL register.
Rotate a 32-bit register or memory
operand right the number of bits
ROR reg/mem32,imm8 C1 /0 ib
specified by an 8-bit immediate
value.
Rotate a 64-bit register or memory
ROR reg/imm64,1 D1 /0
operand right 1 bit.
Rotate a 64-bit register or memory
ROR reg/mem64,CL D3 /0 operand right the number of bits
specified in the CL register.
Rotate a 64-bit register or memory
operand right the number of bits
ROR reg/mem64,imm8 C1 /0 ib
specified by an 8-bit immediate
value.
Loads the sign flag, the zero flag,
the auxiliary flag, the parity flag,
SAHF 9E and the carry flag from the AH
register into the lower 8 bits of the
EFLAGS register.
Shift an 8-bit register or memory
SAL reg/mem8,1 D0 /4
location left 1 bit.
Shift an 8-bit register or memory
SAL reg/mem8,CL D2 /4 location left the number of bits
specified in the CL register.
Shift an 8-bit register or memory
location left the number of bits
SAL reg/mem8,imm8 C0 /4 ib
specified by an 8-bit immediate
value.
Shift a 16-bit register or memory
SAL reg/mem16,1 D1 /4
location left 1 bit.
Shift a 16-bit register or memory
SAL reg/mem16,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 16-bit register or memory
location left the number of bits
SAL reg/mem16,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a 32-bit register or memory
SAL reg/mem32,1 D1 /4
location left 1 bit.
Shift a 32-bit register or memory
SAL reg/mem32,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 32-bit register or memory
location left the number of bits
SAL reg/mem32,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a 64-bit register or memory
SAL reg/mem64,1 D1 /4
location left 1 bit.
Shift a 64-bit register or memory
SAL reg/mem64,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 64-bit register or memory
location left the number of bits
SAL reg/mem64,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift an 8-bit register or memory
SHL reg/mem8,1 D0 /4
location left 1 bit.
Shift an 8-bit register or memory
SHL reg/mem8,CL D2 /4 location left the number of bits
specified in the CL register.
Shift an 8-bit register or memory
location left the number of bits
SHL reg/mem8,imm8 C0 /4 ib
specified by an 8-bit immediate
value.
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Instruction
Supported
Mnemonic Opcode Description
Shift a 16-bit register or memory
SHL reg/mem16,1 D1 /4
location left 1 bit.
Shift a 16-bit register or memory
SHL reg/mem16,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 16-bit register or memory
location left the number of bits
SHL reg/mem16,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a 32-bit register or memory
SHL reg/mem32,1 D1 /4
location left 1 bit.
Shift a 32-bit register or memory
SHL reg/mem32,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 32-bit register or memory
location left the number of bits
SHL reg/mem32,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a 64-bit register or memory
SHL reg/mem64,1 D1 /4
location left 1 bit.
Shift a 64-bit register or memory
SHL reg/mem64,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 64-bit register or memory
location left the number of bits
SHL reg/mem64,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a signed 8-bit register or
SAR reg/mem8,1 D0 /7
memory operand right 1 bit.
Shift a signed 8-bit register or
SAR reg/mem8,CL D2 /7 memory operand right the number of
bits specified in the CL register.
Shift a signed 8-bit register or
memory location right the number of
SAR reg/mem8,imm8 C0 /7 ib
bits specified by an 8-bit immediate
value.
Shift a signed 16-bit register or
SAR reg/mem16,1 D1 /7
memory operand right 1 bit.
Shift a signed 16-bit register or
SAR reg/mem16,CL D3 /7 memory operand right the number of
bits specified in the CL register.
Shift a signed 16-bit register or
memory location right the number of
SAR reg/mem16,imm8 C1 /7 ib
bits specified by an 8-bit immediate
value.
Shift a signed 32-bit register or
SAR reg/mem32,1 D1 /7
memory location right 1 bit.
Shift a signed 32-bit register or
SAR reg/mem32,CL D3 /7 memory operand right the number of
bits specified in the CL register.
Shift a signed 32-bit register or
memory operand right the number of
SAR reg/mem32,imm8 C1 /7 ib
bits specified by an 8-bit immediate
value.
Shift a signed 64-bit register or
SAR reg/mem64,1 D1 /7
memory operand left 1 bit.
Shift a signed 64-bit register or
SAR reg/mem64,CL D3 /7 memory operand right the number of
bits specified in the CL register.
Shift a signed 64-bit register or
memory operand right the number of
SAR reg/mem64,imm8 C1 /7 ib
bits specified by an 8-bit immediate
value.
Subtract an immediate 8-bit value
SBB AL,imm8 1C ib
from the AL register with borrow.
Subtract an immediate 16-bit value
SBB AX,imm16 1D iw
from the AX register with borrow.
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Instruction
Supported
Mnemonic Opcode Description
Subtract an immediate 32-bit value
SBB EAX,imm32 1D id
from the EAX register with borrow.
Subtract an immediate 32-bit value
SBB RAX,imm32 1D id
from the RAX register with borrow.
Subtract an immediate 8-bit value
SBB reg/mem8,imm8 80 /3 ib from an 8-bit register or memory
location with borrow.
Subtract an immediate 16-bit value
SBB reg/mem16,imm16 80 /3 iw from a 16-bit register or memory
location with borrow.
Subtract an immediate 32-bit value
SBB reg/mem32,imm32 81 /3 id from a 32-bit register or memory
location with borrow.
Subtract a sign-extended immediate
SBB reg/mem64,imm32 81 /3 id 32-bit value from a 64-bit register
or memory location with borrow.
Subtract a sign-extended 8-bit
immediate value from a 16-bit
SBB reg/mem16,imm8 83 /3 ib
register or memory location with
borrow.
Subtract a sign-extended 8-bit
immediate value from a 32-bit
SBB reg/mem32,imm8 83 /3 ib
register or memory location with
borrow.
Subtract a sign-extended 8-bit
immediate value from a 64-bit
SBB reg/mem64,imm8 83 /3 ib
register or memory location with
borrow.
Subtract the contents of an 8-bit
SBB reg/mem8,reg8 18 /r register from an 8-bit register or
memory location with borrow.
Subtract the contents of a 16-bit
SBB reg/mem16,reg16 19 /r register from a 16-bit register or
memory location with borrow.
Subtract the contents of a 32-bit
SBB reg/mem32,reg32 19 /r register from a 32-bit register or
memory location with borrow.
Subtract the contents of a 64-bit
SBB reg/mem64,reg64 19 /r register from a 64-bit register or
memory location with borrow.
Subtract the contents of an 8-bit
register or memory location from the
SBB reg8,reg/mem8 1A /r
contents of an 8-bit register with
borrow.
Subtract the contents of a 16-bit
register or memory location from the
SBB reg16,reg/mem16 1B /r
contents of a 16-bit register with
borrow.
Subtract the contents of a 32-bit
register or memory location from the
SBB reg32,reg/mem32 1B /r
contents of a 32-bit register with
borrow.
Subtract the contents of a 64-bit
register or memory location from the
SBB reg64,reg/mem64 1B /r
contents of a 64-bit register with
borrow.
Compare the contents of the AL
SCAS mem8 AE register with the byte at ES:rDI, and
then increment or decrement rDI.
Compare the contents of the AX
SCAS mem16 AF register with the word at ES:rDI, and
then increment or decrement rDI.
Compare the contents of the EAX
register with the doubleword at
SCAS mem32 AF
ES:rDI, and then increment or
decrement rDI.
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Instruction
Supported
Mnemonic Opcode Description
Compare the contents of the RAX
SCAS mem64 AF register with the quadword at ES:rDI,
and then increment or decrement rDI.
Compare the contents of the AL
SCASB AE register with the byte at ES:rDI, and
then increment or decrement rDI.
Compare the contents of the AX
SCASW AF register with the word at ES:rDI, and
then increment or decrement rDI.
Compare the contents of the EAX
register with the doubleword at
SCASD AF
ES:rDI, and then increment or
decrement rDI.
Compare the contents of the RAX
SCASQ AF register with the quadword at ES:rDI,
and then increment or decrement rDI.
SETO reg/mem8 0F 90 Set byte if overflow (OF = 1).
SETNO reg/mem8 0F 91 Set byte if not overflow (OF = 0).
SETB reg/mem8 0F 92 Set byte if below (CF = 1).
SETC reg/mem8 0F 92 Set byte if carry (CF = 1).
Set byte if not above or equal (CF =
SETNAE reg/mem8 0F 92
1).
SETNB reg/mem8 0F 93 Set byte if not below (CF = 0).
SETNC reg/mem8 0F 93 Set byte if not carry (CF = 0).
SETAE reg/mem8 0F 93 Set byte if above or equal (CF = 0).
SETZ reg/mem8 0F 94 Set byte if zero (ZF = 1).
SETE reg/mem8 0F 94 Set byte if equal (ZF = 1).
SETNZ reg/mem8 0F 95 Set byte if not zero (ZF = 0).
SETNE reg/mem8 0F 95 Set byte if not equal (ZF = 0).
Set byte if below or equal (CF = 1 or
SETBE reg/mem8 0F 96
ZF = 1).
Set byte if not above (CF = 1 or ZF =
SETNA reg/mem8 0F 96
1).
Set byte if not below or equal (CF =
SETNBE reg/mem8 0F 97
0 and ZF = 0).
Set byte if above (CF = 0 and ZF =
SETA reg/mem8 0F 97
0).
SETS reg/mem8 0F 98 Set byte if sign (SF = 1).
SETNS reg/mem8 0F 99 Set byte if not sign (SF = 0).
SETP reg/mem8 0F 9A Set byte if parity (PF = 1).
SETPE reg/mem8 0F 9A Set byte if parity even (PF = 1).
SETNP reg/mem8 0F 9B Set byte if not parity (PF = 0).
SETPO reg/mem8 0F 9B Set byte if parity odd (PF = 0).
SETL reg/mem8 0F 9C Set byte if less (SF <> OF).
Set byte if not greater or equal (SF
SETNGE reg/mem8 0F 9C
<> OF).
SETNL reg/mem8 0F 9D Set byte if not less (SF =OF).
Set byte if greater or equal (SF =
SETGE reg/mem8 0F 9D
OF).
Set byte if less or equal (ZF = 1 or
SETLE reg/mem8 0F 9E
SF <> OF).
Set byte if not greater (ZF = 1 or SF
SETNG reg/mem8 0F 9E
<> OF).
Set byte if not less or equal (ZF = 0
SETNLE reg/mem8 0F 9F
and SF = OF).
Set byte if greater (ZF = 0 and SF =
SETG reg/mem8 0F 9F
OF).
Force strong ordering of (serialized)
SFENCE 0F AE F8
store operations.
Shift an 8-bit register or memory
SHL reg/mem8,1 D0 /4
location left 1 bit.
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Instruction
Supported
Mnemonic Opcode Description
Shift an 8-bit register or memory
SHL reg/mem8,CL D2 /4 location left the number of bits
specified in the CL register.
Shift an 8-bit register or memory
location left the number of bits
SHL reg/mem8,imm8 C0 /4 ib
specified by an 8-bit immediate
value.
Shift a 16-bit register or memory
SHL reg/mem16,1 D1 /4
location left 1 bit.
Shift a 16-bit register or memory
SHL reg/mem16,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 16-bit register or memory
location left the number of bits
SHL reg/mem16,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a 32-bit register or memory
SHL reg/mem32,1 D1 /4
location left 1 bit.
Shift a 32-bit register or memory
SHL reg/mem32,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 32-bit register or memory
location left the number of bits
SHL reg/mem32,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift a 64-bit register or memory
SHL reg/mem64,1 D1 /4
location left 1 bit.
Shift a 64-bit register or memory
SHL reg/mem64,CL D3 /4 location left the number of bits
specified in the CL register.
Shift a 64-bit register or memory
location left the number of bits
SHL reg/mem64,imm8 C1 /4 ib
specified by an 8-bit immediate
value.
Shift bits of a 16-bit destination
register or memory operand to the
left the number of bits specified in
SHLD reg/mem16,reg16,imm8 0F A4 /r ib
an 8-bit immediate value, while
shifting in bits from the second
operand.
Shift bits of a 16-bit destination
register or memory operand to the
SHLD reg/mem16,reg16,CL 0F A5 /r left the number of bits specified in
the CL register, while shifting in
bits from the second operand.
Shift bits of a 32-bit destination
register or memory operand to the
left the number of bits specified in
SHLD reg/mem32,reg32,imm8 0F A4 /r ib
an 8-bit immediate value, while
shifting in bits from the second
operand.
Shift bits of a 32-bit destination
register or memory operand to the
SHLD reg/me326,reg32,CL 0F A5 /r left the number of bits specified in
the CL register, while shifting in
bits from the second operand.
Shift bits of a 64-bit destination
register or memory operand to the
left the number of bits specified in
SHLD reg/mem64,reg64,imm8 0F A4 /r ib
an 8-bit immediate value, while
shifting in bits from the second
operand.
Shift bits of a 64-bit destination
register or memory operand to the
SHLD reg/mem16,reg16,CL 0F A5 /r left the number of bits specified in
the CL register, while shifting in
bits from the second operand.
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Instruction
Supported
Mnemonic Opcode Description
Shift an 8-bit register or memory
SHR reg/mem8,1 D0 /5
operand right 1 bit.
Shift an 8-bit register or memory
SHR reg/mem8,CL D2 /5 operand right the number of bits
specified in the CL register.
Shift an 8-bit register or memory
operand right the number of bits
SHR reg/mem8,imm8 C0 /5 ib
specified by an 8-bit immediate
value.
Shift a 16-bit register or memory
SHR reg/mem16,1 D1 /5
operand right 1 bit.
Shift a 16-bit register or memory
SHR reg/mem16,CL D3 /5 operand right the number of bits
specified in the CL register.
Shift a 16-bit register or memory
operand right the number of bits
SHR reg/mem16,imm8 C1 /5 ib
specified by an 8-bit immediate
value.
Shift a 32-bit register or memory
SHR reg/mem32,1 D1 /5
operand right 1 bit.
Shift a 32-bit register or memory
SHR reg/mem32,CL D3 /5 operand right the number of bits
specified in the CL register.
Shift a 32-bit register or memory
operand right the number of bits
SHR reg/mem32,imm8 C1 /5 ib
specified by an 8-bit immediate
value.
Shift a 64-bit register or memory
SHR reg/mem64,1 D1 /5
operand left 1 bit.
Shift a 64-bit register or memory
SHR reg/mem64,CL D3 /5 operand right the number of bits
specified in the CL register.
Shift a 64-bit register or memory
operand right the number of bits
SHR reg/mem64,imm8 C1 /5 ib
specified by an 8-bit immediate
value.
Shift bits of a 16-bit destination
register or memory operand to the
right the number of bits specified in
SHRD reg/mem16,reg16,imm8 0F AC /r ib
an 8-bit immediate value, while
shifting in bits from the second
operand.
Shift bits of a 16-bit destination
register or memory operand to the
SHRD reg/mem16,reg16,CL 0F AD /r right the number of bits specified in
the CL register, while shifting in
bits from the second operand.
Shift bits of a 32-bit destination
register or memory operand to the
right the number of bits specified in
SHRD reg/mem32,reg32,imm8 0F AC /r ib
an 8-bit immediate value, while
shifting in bits from the second
operand.
Shift bits of a 32-bit destination
register or memory operand to the
SHRD reg/me326,reg32,CL 0F AD /r right the number of bits specified in
the CL register, while shifting in
bits from the second operand.
Shift bits of a 64-bit destination
register or memory operand to the
right the number of bits specified in
SHRD reg/mem64,reg64,imm8 0F AC /r ib
an 8-bit immediate value, while
shifting in bits from the second
operand.
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Instruction
Supported
Mnemonic Opcode Description
Shift bits of a 64-bit destination
register or memory operand to the
SHRD reg/mem16,reg16,CL 0F AD /r right the number of bits specified in
the CL register, while shifting in
bits from the second operand.
STC F9 Set the carry flag (CF) to 1.
STD FD Set the direction flag (DF) to 1.
Store the contents of the AL register
STOS reg8 AA to ES:rDI, and then increment or
decrement rDI.
Store the contents of the AX register
STOS reg16 AB to ES:rDI, and then increment or
decrement rDI.
Store the contents of the EAX
STOS reg32 AB register to ES:rDI, and then
increment or decrement rDI.
Store the contents of the RAX
STOS reg64 AB register to ES:rDI, and then
increment or decrement rDI.
Store the contents of the AL register
STOSB AA to ES:rDI, and then increment or
decrement rDI.
Store the contents of the AX register
STOSW AB to ES:rDI, and then increment or
decrement rDI.
Store the contents of the EAX
STOSD AB register to ES:rDI, and then
increment or decrement rDI.
Store the contents of the RAX
STOSQ AB register to ES:rDI, and then
increment or decrement rDI.
Subtract an immediate 8-bit value
SUB AL,imm8 2C ib from the AL register and store the
result in AL.
Subtract an immediate 16-bit value
SUB AX,imm16 2D iw from the AX register and store the
result in AX.
Subtract an immediate 32-bit value
SUB EAX,imm32 2D id from the EAX register and store the
result in EAX.
Subtract a sign-extended immediate
SUB RAX,imm32 2D id 32-bit value from the RAX register
and store the result in RAX.
Subtract an immediate 8-bit value
SUB reg/mem8,imm8 80 /5 ib from an 8-bit destination register or
memory location.
Subtract an immediate 16-bit value
SUB reg/mem16,imm16 81 /5 iw from a 16-bit destination register or
memory location.
Subtract an immediate 32-bit value
SUB reg/mem32,imm32 81 /5 id from a 32-bit destination register or
memory location.
Subtract a sign-extended immediate
32-bit value from a 64-bit
SUB reg/mem64,imm32 81 /5 id
destination register or memory
location.
Subtract a sign-extended immediate 8-
SUB reg/mem16,imm8 83 /5 ib bit value from a 16-bit register or
memory location.
Subtract a sign-extended immediate 8-
SUB reg/mem32,imm8 83 /5 ib bit value from a 32-bit register or
memory location.
Subtract a sign-extended immediate 8-
SUB reg/mem64,imm8 83 /5 ib bit value from a 64-bit register or
memory location.
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Instruction
Supported
Mnemonic Opcode Description
Subtract the contents of an 8-bit
SUB reg/mem8,reg8 28 /r register from an 8-bit destination
register or memory location.
Subtract the contents of a 16-bit
SUB reg/mem16,reg16 29 /r register from a 16-bit destination
register or memory location.
Subtract the contents of a 32-bit
SUB reg/mem32,reg32 29 /r register from a 32-bit destination
register or memory location.
Subtract the contents of a 64-bit
SUB reg/mem64,reg64 29 /r register from a 64-bit destination
register or memory location.
Subtract the contents of an 8-bit
SUB reg8,reg/mem8 2A /r register or memory operand from an 8-
bit destination register.
Subtract the contents of a 16-bit
SUB reg16,reg/mem16 2B /r register or memory operand from a 16-
bit destination register.
Subtract the contents of a 32-bit
SUB reg32,reg/mem32 2B /r register or memory operand from a 32-
bit destination register.
Subtract the contents of a 64-bit
SUB reg64,reg/mem64 2B /r register or memory operand from a 64-
bit destination register.
AND an immediate 8-bit value with the
TEST AL,imm8 AB ib contents of the AL register and set
rFLAGS to reflect the result.
AND an immediate 16-bit value with
TEST AX,imm16 A9 iw the contents of the AX register and
set rFLAGS to reflect the result.
AND an immediate 32-bit value with
TEST EAX,imm32 A9 id the contents of the EAX register and
set rFLAGS to reflect the result.
AND a sign-extened immediate 32-bit
value with the contents of the RAX
TEST RAX,imm32 A9 id
register and set rFLAGS to reflect
the result.
AND an immediate 8-bit value with the
contents of an 8-bit register or
TEST reg/mem8,imm8 F6 /0 ib
memory operand and set rFLAGS to
reflect the result.
AND an immediate 16-bit value with
the contents of a 16-bit register or
TEST reg/mem16,imm16 F7 /0 iw
memory operand and set rFLAGS to
reflect the result.
AND an immediate 32-bit value with
the contents of a 32-bit register or
TEST reg/mem32,imm32 F7 /0 id
memory operand and set rFLAGS to
reflect the result.
AND a sign-extened immediate 32-bit
value with the contents of a 64-bit
TEST reg/mem64,imm32 F7 /0 id
register or memory operand and set
rFLAGS to reflect the result.
AND the contents of an 8-bit register
with the contents of an 8-bit
TEST reg/mem8,reg8 84 /r
register or memory operand and set
rFLAGS to reflect the result.
AND the contents of a 16-bit register
with the contents of a 16-bit
TEST reg/mem16,reg16 85 /r
register or memory operand and set
rFLAGS to reflect the result.
AND the contents of a 32-bit register
with the contents of a 32-bit
TEST reg/mem32,reg32 85 /r
register or memory operand and set
rFLAGS to reflect the result.
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Instruction
Supported
Mnemonic Opcode Description
AND the contents of a 64-bit register
with the contents of a 64-bit
TEST reg/mem64,reg64 85 /r
register or memory operand and set
rFLAGS to reflect the result.
Exchange the contents of an 8-bit
register with the contents of 8-bit
XADD reg/mem8,reg8 0F C0 /r destination register or memory
operand and load their sum into the
destination.
Exchange the contents of a 16-bit
register with the contents of 16-bit
XADD reg/mem16,reg16 0F C1 /r destination register or memory
operand and load their sum into the
destination.
Exchange the contents of a 32-bit
register with the contents of 32-bit
XADD reg/mem32,reg32 0F C1 /r destination register or memory
operand and load their sum into the
destination.
Exchange the contents of a 64-bit
register with the contents of 64-bit
XADD reg/mem64,reg64 0F C1 /r destination register or memory
operand and load their sum into the
destination.
Exchange the contents of AX register
XCHG AX,reg16 90 +rw with the contents of a 16-bit
register.
Exchange the contents of a 16-bit
XCHG reg16,AX 90 +rw register with the contents of the AX
register.
Exchange the contents of EAX register
XCHG AX,reg32 90 +rd with the contents of a 32-bit
register.
Exchange the contents of a 32-bit
XCHG reg32,AX 90 +rd register with the contents of the EAX
register.
Exchange the contents of RAX register
XCHG RAX,reg64 90 +rq with the contents of a 64-bit
register.
Exchange the contents of a 64-bit
XCHG reg64,RAX 90 +rq register with the contents of the RAX
register.
Exchange the contents of an 8-bit
XCHG reg/mem8,reg8 86 /r register with the contents of an 8-
bit register or memory operand.
Exchange the contents of an 8-bit
XCHG reg8,reg/mem8 86 /r register or memory operand with the
contents of an 8-bit register.
Exchange the contents of a 16-bit
XCHG reg/mem16,reg16 87 /r register with the contents of a 16-
bit register or memory operand.
Exchange the contents of a 16-bit
XCHG reg16,reg/mem16 87 /r register or memory operand with the
contents of a 16-bit register.
Exchange the contents of a 32-bit
XCHG reg/mem32,reg32 87 /r register with the contents of a 32-
bit register or memory operand.
Exchange the contents of a 32-bit
XCHG reg32,reg/mem32 87 /r register or memory operand with the
contents of a 32-bit register.
Exchange the contents of a 64-bit
XCHG reg/mem64,reg64 87 /r register with the contents of a 64-
bit register or memory operand.
Exchange the contents of a 64-bit
XCHG reg64,reg/mem64 87 /r register or memory operand with the
contents of a 64-bit register.
Set AL to the contents of DS:[rBX +
XLAT mem8 D7
unsigned AL].
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Instruction
Supported
Mnemonic Opcode Description
Set AL to the contents of DS:[rBX +
XLATB D7
unsigned AL].
XOR the contents of AL with an
XOR AL,imm8 34 ib immediate 8-bit operand and store the
result in AL.
XOR the contents of AX with an
XOR AX,imm16 35 iw immediate 16-bit operand and store
the result in AX.
XOR the contents of EAX with an
XOR EAX,imm32 35 id immediate 32-bit operand and store
the result in EAX.
XOR the contents of RAX with a sign-
XOR RAX,imm32 35 id extended immediate 32-bit operand and
store the result in AX.
XOR the contents of an 8-bit
destination register or memory
XOR reg/mem8,imm8 80 /6 ib operand with an 8-bit immediate value
and store the result in the
destination.
XOR the contents of a 16-bit
destination register or memory
XOR reg/mem16,imm16 81 /6 iw operand with a 16-bit immediate value
and store the result in the
destination.
XOR the contents of a 32-bit
destination register or memory
XOR reg/mem32,imm32 81 /6 id operand with a 32-bit immediate value
and store the result in the
destination.
XOR the contents of a 64-bit
destination register or memory
XOR reg/mem64,imm32 81 /6 id operand with a sign-extended 32-bit
immediate value and store the result
in the destination.
XOR the contents of a 16-bit
destination register or memory
XOR reg/mem16,imm8 83 /6 ib operand with a sign-extended 8-bit
immediate value and store the result
in the destination.
XOR the contents of a 32-bit
destination register or memory
XOR reg/mem32,imm8 83 /6 ib operand with a sign-extended 8-bit
immediate value and store the result
in the destination.
XOR the contents of a 64-bit
destination register or memory
XOR reg/mem64,imm8 83 /6 ib operand with a sign-extended 8-bit
immediate value and store the result
in the destination.
XOR the contents of an 8-bit
destination register or memory
XOR reg/mem8,reg8 30 /r operand with the contents of an 8-bit
register and store the result in the
destination.
XOR the contents of a 16-bit
destination register or memory
XOR reg/mem16,reg16 31 /r operand with the contents of a 16-bit
register and store the result in the
destination.
XOR the contents of a 32-bit
destination register or memory
XOR reg/mem32,reg32 31 /r operand with the contents of a 32-bit
register and store the result in the
destination.
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Instruction
Supported
Mnemonic Opcode Description
XOR the contents of a 64-bit
destination register or memory
XOR reg/mem64,reg64 31 /r operand with the contents of a 64-bit
register and store the result in the
destination.
XOR the contents of an 8-bit
destination register with the
XOR reg8,reg/mem8 32 /r contents of an 8-bit register or
memory operand and store the result
in the destination.
XOR the contents of a 16-bit
destination register with the
XOR reg16,reg/mem16 33 /r contents of a 16-bit register or
memory operand and store the result
in the destination.
XOR the contents of a 32-bit
destination register with the
XOR reg32,reg/mem32 33 /r contents of a 32-bit register or
memory operand and store the result
in the destination.
XOR the contents of a 64-bit
destination register with the
XOR reg64,reg/mem64 33 /r contents of a 64-bit register or
memory operand and store the result
in the destination.
Instruction
Supported
Mnemonic Opcode Description
Adjust the RPL of a destination segment
selector to a level not less than the RPL of 1
ARPL reg/mem16,reg16 63 /r
the segment selector specifies in the 16-bit
source register.
CLI FA Clear the interrupt flag (IF) to zero.
Clear the task-switched (TS) flag in CR0 to
CLTS 0F 06
0.
HLT F4 Halt instruction execution.
INT 3 CC Trap to debugger at interrupt 3. 2
Flush internal caches and trigger external
INVD 0F 08
cache flushes.
Invalidate the TLB entry for the page
INVLPG mem8 0F 01 /7
containing a specified memory location.
IRET CF Return from interrupt (16-bit operand size). 1
1
In 64-bit mode, this opcode (0x63) is used for the MOVSXD instruction.
2
See Section A.6.3.1, “INT – Interrupt to Vector”, on page 225.
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Instruction
Supported
Mnemonic Opcode Description
IRETD CF Return from interrupt (32-bit operand size). 1
1
See Section A.6.3.2, “IRET – Return from Interrupt”, on page 225.
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Instruction
Supported
Mnemonic Opcode Description
Store global descriptor table register to
SGDT mem16:32 0F 01 /0
memory.
Store global descriptor table register to
SGDT mem16:64 0F 01 /0
memory.
Store interrupt descriptor table register to
SIDT mem16:32 0F 01 /1
memory.
Store interrupt descriptor table register to
SIDT mem16:64 0F 01 /1
memory.
Store the segment selector from the local
SLDT reg16 0F 00 /0 descriptor table register to a 16-bit
register.
Store the segment selector from the local
SLDT reg32 0F 00 /0 descriptor table register to a 32-bit
register.
Store the segment selector from the local
SLDT reg64 0F 00 /0 descriptor table register to a 64-bit
register.
Store the segment selector from the local
SLDT mem16 0F 00 /0 descriptor table register to a 16-bit memory
location.
Store the low 16 bits of CR0 to a 16-bit
SMSW reg16 0F 01 /4
register.
Store the low 32 bits of CR0 to a 32-bit
SMSW reg32 0F 01 /4
register.
Store the entire 64 bits of CR0 to a 64-bit
SMSW reg64 0F 01 /4
register.
SMSW mem16 0F 01 /4 Store the low 16 bits of CR0 to memory.
STI FB Set interrupt flag (IF) to 1.
Store the segment selector from the task
STR reg16 0F 00 /1 register to a 16-bit general-purpose
register.
Store the segment selector from the task
STR reg32 0F 00 /1 register to a 32-bit general-purpose
register.
Store the segment selector from the task
STR reg64 0F 00 /1 register to a 64-bit general-purpose
register.
Store the segment selector from the task
STR mem16 0F 00 /1
register to a 16-bit memory location.
SWAPGS 0F 01 F8 Exchange GS base with KernelGSBase MSR.
SYSCALL 0F 05 Call operating system.
SYSENTER 0F 34 Call operating system.
SYSEXIT 0F 35 Return from operating system.
SYSRET 0F 07 Return from operating system.
UD2 0F 08 Raise an invalid opcode exception.
Set the zero flag (ZF) to 1 if the segment
VERR reg/mem16 0F 00 /4
selected can be read.
Set the zero flag (ZF) to 1 if the segment
VERW 0F 00 /5
selected can be written.
Write modified cache lines to main memory,
WBINVD 0F 09 invalidate internal caches, and trigger
external cache flushes.
WRMSR 0F 30 Write EDX:EAX to the MSR specified by ECX.
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The simulator does not support nested task-switching using the rFLAGS nested-task bit
(NT) and the TSS back-link field. An interrupt return (IRET) to the previous task (nested-
task) will result in a „FeatureNotImplemented‟ exception and the simulation will be
stopped.
Instruction
Supported
Mnemonic Opcode Description
CLGI 0F 01 DD Clear Global Interrupt Flag.
Invalidates the TLB mapping for the
INVLPGA 0F 01 DF virtual page specified in rAX and the
ASID specified in ECX.
Alternate notation for move from CR8 to
MOV reg32,CR8 F0 20 /r
register.
Alternate notation for move register to
MOV reg64,CR8 F0 20 /r
CR8.
Alternate notation for move from CR8 to
MOV CR8,reg32 F0 22 /r
register.
Alternate notation for move register to
MOV CR8,reg64 F0 22 /r
CR8.
Secure initialization and jump, with
SKINIT 0F 01 DE
attestation.
STGI 0F 01 DC Set Global Interrupt Flag.
VMLOAD 0F 01 DA Load State from VMCB.
VMCALL 0F 01 D9 Call VMM.
VMRUN 0F 01 D8 Run Virtual Machine.
VMSAVE 0F 01 DB Save State to VMCB.
Instruction
Supported
Mnemonic Opcode Description
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Instruction
Supported
Mnemonic Opcode Description
Converts packed double-precision
floating-point values in an XMM
CVTPD2PI mmx,xmm2/m128 66 0F 2D /r register or 128-bit memory location to
packed doubleword integers values in
the destination MMX™ register.
Converts two packed doubleword integer
values in a MMX™ register or 64-bit
CVTPI2PD xmm,mmx/m64 66 0F 2A /r memory location to two packed double-
precision floating-point values in the
destination XMM register.
Converts packed doubleword integer
values in a MMX™ register or 64-bit
CVTPI2PS mmx,xmm2/m128 0F 2A /r memory location to single-precision
floating-point values in the
destination XMM register.
Instruction
Supported
Mnemonic Opcode Description
Fast Enter/Exit of the MMX or
FEMMS 0F 0E
floating-point state.
Average of unsigned packed 8-bit
PAVGUSB mmreg1,mmreg2/m64 0F 0F /BF
values.
Converts packed floating-point
PF2ID mmreg1,mmreg2/m64 0F 0F /1D
operand or packed 32-bit integer.
PFACC mmreg1,mmreg2/m64 0F 0F /AE Floating-point accumulate.
PFADD mmreg1,mmreg2/m64 0F 0F /9E Packed, floating-point addition.
Packed floating-point comparison,
PFCMPEQ mmreg1,mmreg2/m64 0F 0F /B0
equal to.
Packed floating-point comparison,
PFCMPPGE mmreg1,mmreg2/m64 0F 0F /90
greater than or equal to.
Packed floating-point comparison,
PFCMPGT mmreg1,mmreg2/m64 0F 0F /A0
greater than.
PFMAX mmreg1,mmreg2/m64 0F 0F /A4 Packed floating-point maximum.
PFMIN mmreg1,mmreg2/m64 0F 0F /94 Packed floating-point minimum.
Packed floating-point
PFMUL mmreg1,mmreg2/m64 0F 0F /B4
multiplication.
PFRCP mmreg1,mmreg2/m64 0F 0F /96 Packed floating-point approximation.
Packed floating-point reciprocal,
PFRCPIT1 mmreg1,mmreg2/m64 0F 0F /A6
first iteration step.
Packed floating-point reciprocal,
PFRCPIT2 mmreg1,mmreg2/m64 0F 0F /B6
second iteration step.
Packed floating-point reciprocal,
PFRSQIT1 mmreg1,mmreg2/m64 0F 0F /A7
square root, first iteration step.
Packed floating-point reciprocal,
PFRSQRT mmreg1,mmreg2/m64 0F 0F /97
square root approximation.
PFSUB mmreg1,mmreg2/m64 0F 0F /9A Packed, floating-point subtraction.
Packed, floating-point reverse
PFSUBR mmreg1,mmreg2/m64 0F 0F /AA
subtraction.
Packed 32-bit integer to floating-
PI2FD mmreg1,mmreg2/m64 0F 0F /0D
point conversion.
Multiply signed packed 16-bit values
PMULHRW mmreg1,mmreg2/m64 0F 0F /B7 with rounding and store the high 16
bits.
Prefetch processor cache line into
PREFETCH/PREFETCHW 0F 0D
L1 data cache (Dcache).
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Instruction
Supported
Mnemonic Opcode Description
Packed floating-point to integer
PF2IW mmreg1,mmreg2/m64 0F 0F /1C
word conversion with sign extend.
Packed floating-point negative
PFNACC mmreg1,mmreg2/m64 0F 0F /8A
accumulate.
Packed floating-point mixed
PFPNACC mmreg1,mmreg2/m64 0F 0F /8E
positive-negative accumulate.
Packed 16-bit integer to floating-
PI2FW mmreg1,mmreg2/m64 0F 0F /0C
point conversion.
PSWAPD mmreg1,mmreg2/m64 0F 0F /BB Packed swap double word.
Instruction
Supported
Mnemonic Opcode Description
Add/Subtract packed double-precision
ADDSUBPD xmm1,xmm2/m128 66 0F D0 /r floating-point number from XMM2/Mem
to XMM1.
Add/Subtract packed single-precision
ADDSUBPS xmm1,xmm2/m128 F2 0F D0 /r floating-point number from XMM2/Mem
to XMM1.
Store ST as a signed integer
FISTTP m16int DF /1
(truncate) in m16int and pop ST.
Store ST as a signed integer
FISTTP m32int DB /1
(truncate) in m32int and pop ST.
Store ST as a signed integer
FISTTP m64int DD /1
(truncate) in m16int and pop ST.
Add horizontally packed double-
HADDPD xmm1,xmm2/m128 66 0F 7C /r precision floating-point numbers
from XMM2/Mem to XMM1.
Add horizontally packed single-
HADDPS xmm1,xmm2/m128 F2 0F 7C /r precision floating-point numbers
from XMM2/Mem to XMM1.
Subtract horizontally packed double-
HSUBPD xmm1,xmm2/m128 66 0F 7D /r precision floating-point numbers
from XMM2/Mem to XMM1.
Subtract horizontally packed single-
HSUBPS xmm1,xmm2/m128 F2 0F 7D /r precision floating-point numbers
from XMM2/Mem to XMM1.
Load 128 bits from Memory to XMM
LDDQU xmm,m128 F2 0F F0 /r
register.
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Instruction
Supported
Mnemonic Opcode Description
Sets up a linear address range to be
monitored by hardware and activates
MONITOR EAX,ECX,EDX 0F 01 C8 the monitor. The address range 1
should be of a write-back memory
caching type.
Move 64 bits representing the lower
double-precision data element from
MOVDDUP xmm1,xmm2/m64 F2 0F 12 /r
XMM2/Mem to XMM1 register and
duplicate.
Move 128 bits representing packed
single-precision data elements from
MOVSHDUP xmm1,xmm2/m128 F3 0F 16 /r
XMM2/Mem to XMM1 register and
duplicate high.
Move 128 bits representing packed
single-precision data elements from
MOVSLDUP xmm1,xmm2/m128 F3 0F 12 /r
XMM2/Mem to XMM1 register and
duplicate low.
A hint that allows the processor to
stop instruction execution and enter
MWAIT EAX,ECX 0F 01 C9 an implementation–dependent 2
optimized state until occurrence of
a class events.
The simulator does not recognize this instruction. Therefore the simulator generates an
invalid-opcode exception.
The simulator does not recognize this instruction. Therefore the simulator generates an
invalid-opcode exception.
1
See Section A.6.8.1, “MONITOR – Setup Monitor Address”, on page 228.
2
See Section A.6.8.2, “MWAIT – Monitor Wait”, on page 229.
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Figure 15-1 shows the simulators Console Window. The Console Window is the user
interface to the simulators automation interface. All automation commands can be send
from the Console Window to the simulators automation interface, as explained in the
following sections.
1 simnow> shell.modules
If more than one device exists in the currently loaded BSD (for example, most BSDs
include two IDE controllers), you identify the specific device by following the device
name with a colon, and then the number of the device you are interested in. For example,
to send the DVDROMStatus command to the second IDE controller, you would use:
1 simnow> ide:1.DVDROMStatus 0
Omitting the colon and the device number causes the simulator to assume device 0. The
following two commands are equivalent:
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1 simnow> ide:0.DVDROMStatus 0
1 simnow> ide.DVDROMStatus 0
In addition to the commands supported by the various devices, detailed below, all devices
support the usage and ausage command. These commands return a brief description of
each of the commands supported by a specific device. For example, to get a non-
alphabetic ordered list of the commands supported by the shell, you could send the
command:
1 simnow> shell.usage
To get an alphabetic ordered list of the commands supported by the shell, please use the
ausage command as shown here:
1 simnow> shell.ausage
To get an overview of all automation commands which are not attached to any specific
device enter:
1 simnow> help
A.7.1 Shell
To list all registered shell commands enter
1 simnow> shell.usage
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A.7.2 IDE
1 simnow> ide.usage
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A.7.3 SATA
1 simnow> sata.usage
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A.7.4 USB
1 simnow> usb.usage
A.7.5 CMOS
1 simnow> cmos.usage
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A.7.6 ACPI
1 simnow> acpi.usage
A.7.7 Floppy
1 simnow> floppy.usage
A.7.8 Debug
1 simnow> debug.usage
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1 simnow> amd8151.usage
A.7.10 VGA
1 simnow> vga.usage
A.7.11 Serial
1 simnow> serial.usage
Previous versions of the simulator always used only the named-pipe format. Because of
this, the named-pipe was created as soon as the BSD was loaded. Because the new
version allows you to dynamically alter the communications method, the transport is not
created until you hit "go" for the first time (or after making any change to the transport
method). What this means is that if you are using a named-pipe, you will have to press
"go" before the named-pipe is actually created
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\\.\pipe\SimNow.COMn
This indicates that data is being transported through a
named-pipe with the given name. The "n" will be either 1
GetCommPort1 for the first serial port, or 2 for the second serial port.
\\.\COMn 57600
This indicates that data is being transported through the
given serial port on the host machine using a baud rate of
57600.
none
This indicates that data written to the simulated serial port
is discarded, and no data is ever received.
pipe
Tells the simulator to use a named-pipe as the method of
transport for serial data to/from the simulated machine.
The pipe name will be of the form
"\\.\pipe\SimNow.COMn", where "n" will be 1 for serial
port 1 and 2 for serial port 2. The name is not user
configurable.
COMn
Tells the simulator to use one of the host serial ports
SetCommPort1 <none | pipe (identified by "n") as the transport for data to and from the
| COMn BAUD> simulated machine. "n" can be any value between 1 and
255, and must be an actual COM port that is present on the
host system. Regardless of the configuration of the
simulated COM port, the host COM ports baud rate is
configured depending on the BAUD parameter, with 8 bit
data, no parity, 1 stop bit. “BAUD” can be one of the
following values (1200, 2400, 4800, 9600, 14400, 38400,
56000, 57600 or 115200). See also Section 11.1, "Kernel
Debugger", on page 161.
none
Tells the simulator to discard any written data, and always
return "receiver empty" on reads.
1
This only applies to the Windows® version of the simulator and not to the Linux version.
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1 simnow> sledgeldt.usage
1 simnow> sledgenb.usage
A.7.14 DBC
1 simnow> dbc.usage
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1 simnow> 8111.usage
A.7.16 EHC
1 simnow> ehc.usage
A.7.17 Journal
1 simnow> journal.usage
A.7.18 CPU
1 simnow> cpu.usage
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1 simnow> dumpprofile 3
34962861.000000 instructions executed since the last epoch
-------------------------------------------------------------------
Executed 3571672 times
CS.D=0 LongBit=0 physical_addr=00000000000e41de eip=00000000000041de
00000000000041de: cmp [04f0h],aah
00000000000041e3: jnz $-05h
0000000000000000: This block's execution was 20.431234 percent of
the total since the last epoch.
-------------------------------------------------------------------
Executed 229430 times
CS.D=0 LongBit=0 physical_addr=000000000002fd99 eip=000000000000fd99
000000000000fd99: lodsb ds:[esi]
000000000000fd9b: add ah,al
000000000000fd9d: loop $-04h
0000000000000020: This block's execution was 1.968632 percent of
the total since the last epoch.
-------------------------------------------------------------------
Executed 178599 times
CS.D=0 LongBit=0 physical_addr=00000000000274b2 eip=00000000000074b2
00000000000074b2: mov ax,[5724h]
00000000000074b5: cmp ax,[371ah]
00000000000074b9: jbe $+61h
0000000000000040: This block's execution was 1.532475 percent of
the total since the last epoch.
The simulator contains a code profiling facility that is accessed through the dumpprofile
automation command. There is no graphical user interface to the profiling facility at this
time. Profiling in the simulator has some limitations and features not present in most
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systems. The limitations are that no symbolic information is present in the output and that
only execution since the beginning of the last epoch (see the last paragraph for an
explanation of an epoch) is measured. The feature which is most unusual is that the user
can ask for a profile at any time, there is no profiling mechanism that needs to be enabled
before execution takes place. Another feature is that all code in the system is profiled,
even code executed with interrupts off, and code in all modes (16 bit mode, 32-bit legacy
mode, 32-bit compatibility mode, long mode, SMM mode, etc.) is measured equally.
This profiling mechanism is non-intrusive, no x86 interrupts are taken and profiling does
not affect the target machine's selection of code paths at all.
The dumpprofile command by itself causes all profile blocks to be displayed. This output
can be quite voluminous. The user can select just the most frequently executing blocks by
using an optional numeric argument. For example, "dumpprofile 10" will dump the ten
most frequently executing blocks. Blocks are ordered by their frequency of execution, not
weighted by the number of instructions in a block. Therefore, a short block executing 100
times will be displayed before a long block executing 99 times. In this example, the short
block represents fewer total instructions executed. The sense of time that the simulator
uses is quite simple, each instruction takes one "instruction count", with REP instructions
taking one extra count per iteration. Therefore, profiles from the simulator can differ
substantially from those obtained from other tools.
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1 simnow> emerald.usage
1 simnow> mgag400.usage
1 simnow> pcibus.usage
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A.7.22 SIO
1 simnow> sio.usage
1 simnow> memdevice.usage
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A.7.24 Raid
1 simnow> raid.usage
A.7.25 DIMM
1 simnow> dimm.usage
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1 simnow> keyboard.usage
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A.7.27 JumpDrive
1 simnow> jumpdrive.usage
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1 simnow>jumpdrive.initialize 64
The following example copies the file “C:\test.bin“ to the JumpDrive and places it in the
“\tmp“ directory. If the “\tmp“ directory does not exits on the JumpDrive, it is created
automatically.
This copies all files from “C:\tmp“ into the root of the JumpDrive. Any subdirectories are
also copied.
1 simnow>jumpdrive.importdir c:\tmp \
Importing c:\tmp\test.bin ---> \test1.bin
62.89 Mbytes Available
This example shows how to import all “*.exe” files from “C:\tmp” into the root of the
JumpDrive.
1 simnow>jumpdrive.importdir c:\tmp\*.exe \
Importing c:\tmp\app1.exe ---> \app1.exe
Importing c:\tmp\app2.exe ---> \app2.exe
62.60 Mbytes Available
This example shows how to export the “app1.exe” file from the root of the JumpDrive
into “C:\tmp” on the host.
To find out what is already stored in the root of the JumpDrive device, enter the
following:
1 simnow> jumpdrive.dir \
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Directory of: \
<DIR> tmp
103936 test.bin
103936 app1.exe
103936 app2.exe
To get information about how much space is left on the JumpDrive device, enter the
following:
1 simnow>jumpdrive.free
62.60 Mbytes Available
To save the contents of the JumpDrive to the image file “C:\test.img” on the host‟s hard-
disk, enter
1 simnow>jumpdrive.saveimage c:\test.img
This example shows how to load the saved JumpDrive image “C:\test.img” from the
host‟s hard-disk into the JumpDrive
1 simnow>jumpdrive.loadimage c:\test.img
A.7.28 E1000
The NIC device provides the following automation commands that can be used to
configure the device.
1 simnow> e1000.usage
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A.7.29 XTR
1 simnow> xtrnb.usage
1 simnow> xtrsvc.usage
1 simnow> sb600.usage
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1 simnow> rs780.usage
1 simnow> rv670.usage
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1 simnow> rs780.usage
1 simnow> rd790.usage
1 simnow> rd890.usage
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Index
View Memory ............................................153
*
Deprecated Devices ..........................................10
*.ROM ............................................................ 183 Device ID........................................................101
*.SPD.............................................................. 184 Device List........................................................10
Devices Window................................................ 9
A DHCP .............................................................130
A20 ................................................................... 82 Diagnostic Ports................................................29
ACPI ...................................................................8 DIMM ...............................................................59
Address-Translation Cache............................... 30 Disable USB Port..............................................94
AGP ............................................................ 65, 69 Disk Journaling ...........................................43, 96
AMD 3DNow!™ Technology ........................ 228 DiskTool .........................................................165
AMD 8th Generation Integrated Northbridge .. 90 Double Fault ...................................................188
AMD Virtualization™ (AMD-V™) Technology DVD-/CD-ROM ...............................................35
................................................................... 154
E
AMD-8111™ Device ....................................... 94
AMD-8132™ PCI-X® Controller ............ 14, 103 ECC ..................................................................64
AMD-8151™ Device ..................................... 106 EOT ................................................................116
AT24C Device .......................................... 14, 111 Error Log ........................................................147
EXDI ..............................................................112
B
F
Base Address .................................................. 171
Baud Rate ......................................................... 84 Fan ....................................................................82
BIOS ROM ..................................................... 171 FAQ ................................................................177
BSD file ...................................................... 40, 49 Flash-ROM .......................................................87
FLDENV ........................................................188
C Floppy-Disk ......................................................44
Checkpoint........................................................ 49 Frame-Buffer ....................................................66
Chip-Select ....................................................... 86 FRSTOR .........................................................188
Clearing CMOS .............................................. 173 FSAVE ...........................................................188
CMOS....................................................... 95, 173 FSTENV .........................................................188
Code Generator............................................... 246
G
Code Pages ..................................................... 188
COM1 ............................................................... 82 Gateways ........................................................130
COM2 ............................................................... 82 GDB................................................................160
Commit ....................................................... 43, 96 GPIO .................................................................82
Configuration File ..............................................5 Graphics ..................................................2, 65, 69
Console Window .............................................. 29
H
CPUID ............................................................ 186
CR4.PCE ........................................................ 188 Host Operating Systems .................................... 3
Create Device Connection ................................ 11 HyperTransport™ Technology
Creating Floppy-Disk Image .......................... 175 Coherent .......................................................90
Cycle-Accurate ...................................................1 Link ..............................................................92
Link-capable devices ...................................90
D
Messages ......................................................91
Debug Non-Coherent ..............................................90
Find Pattern................................................ 155 Tunnel ..................................................14, 103
Read/Write MSRs ...................................... 154 Upstream Link ...........................................104
Reading CPU MSRs .................................. 154
I
Reading PCI Configuration Registers ........ 154
Set Breakpoint ........................................... 151 Insert CD-ROM ................................................43
Single-Stepping ......................................... 152 INT/IOAPIC .....................................................94
Skip Instruction.......................................... 153 IR 82
Stepping Over ............................................ 152 IRQ-Routing Pin .............................................100
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X Recording ...................................................115
Stop Recording ..........................................115
XTR ................................................................ 114
XVGA ........................................................65, 69
Playback..................................................... 115
Index 263