Ade7854 7858 7868 7878 PDF

Polyphase Multifunction Energy Metering IC
with Harmonic and Fundamental Information

Data Sheet ADE7854/ADE7858/ADE7868/ADE7878
FEATURES harmonic) active, reactive (ADE7878, ADE7868, and
Highly accurate; supports EN 50470-1, EN 50470-3, ADE7858), and apparent energy measurement and rms calcu-
IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards lations, as well as fundamental-only active and reactive energy
Compatible with 3-phase, 3- or 4-wire (delta or wye), and measurement (ADE7878) and rms calculations. A fixed function
other 3-phase services digital signal processor (DSP) executes this signal processing.
Supplies total (fundamental and harmonic) active, reactive The DSP program is stored in the internal ROM memory.
(ADE7878, ADE7868, and ADE7858 only), and apparent The ADE7854/ADE7858/ADE7868/ADE7878 are suitable for
energy, and fundamental active/reactive energy (ADE7878 measuring active, reactive, and apparent energy in various 3-phase
only) on each phase and on the overall system configurations, such as wye or delta services, with both three
Less than 0.1% error in active and reactive energy over a and four wires. The ADE78xx devices provide system calibration
dynamic range of 1000 to 1 at TA = 25°C features for each phase, that is, rms offset correction, phase
Less than 0.2% error in active and reactive energy over a calibration, and gain calibration. The CF1, CF2, and CF3 logic
dynamic range of 3000 to 1 at TA = 25°C outputs provide a wide choice of power information: total active,
Supports current transformer and di/dt current sensors reactive, and apparent powers, or the sum of the current rms
Dedicated ADC channel for neutral current input (ADE7868 and values, and fundamental active and reactive powers.
ADE7878 only)
The ADE7854/ADE7858/ADE7868/ADE7878 contain wave-
Less than 0.1% error in voltage and current rms over a
form sample registers that allow access to all ADC outputs. The
dynamic range of 1000 to 1 at TA = 25°C
devices also incorporate power quality measurements, such as
Supplies sampled waveform data on all three phases and on
short duration low or high voltage detections, short duration
neutral current
high current variations, line voltage period measurement, and
Selectable no load threshold levels for total and
angles between phase voltages and currents. Two serial interfaces,
fundamental active and reactive powers, as well as for
SPI and I2C, can be used to communicate with the ADE78xx. A
apparent powers
dedicated high speed interface, the high speed data capture
Low power battery mode monitors phase currents for
(HSDC) port, can be used in conjunction with I2C to provide
antitampering detection (ADE7868 and ADE7878 only)
access to the ADC outputs and real-time power information.
Battery supply input for missing neutral operation
The ADE7854/ADE7858/ADE7868/ADE7878 also have two
Phase angle measurements in both current and voltage
channels with a typical 0.3° error
interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled
Wide-supply voltage operation: 2.4 V to 3.7 V interrupt event has occurred. For the ADE7868/ADE7878, three
Reference: 1.2 V (drift +5 ppm/°C typical) with external specially designed low power modes ensure the continuity of
overdrive capability energy accumulation when the ADE7868/ADE7878 is in a tam-
Single 3.3 V supply pering situation. See Table 1 for a quick reference chart listing
40-lead lead frame chip scale package (LFCSP), Pb-free each part and its functions. The ADE78xx are available in the
Operating temperature: −40°C to +85°C 40-lead LFCSP, Pb-free package.
Flexible I2C, SPI, and HSDC serial interfaces
Table 1. Part Comparison
APPLICATIONS IRMS, Tamper
VRMS, Fundamental Detect and
Energy metering systems and WATT and Low Power
Part No. WATT VAR VA di/dt VAR Modes
GENERAL DESCRIPTION ADE7878 Yes Yes Yes Yes Yes Yes
The ADE7854/ADE7858/ADE7868/ADE7878 are high accuracy, ADE7868 Yes Yes Yes Yes No Yes
3-phase electrical energy measurement ICs with serial interfaces ADE7858 Yes Yes Yes Yes No No
and three flexible pulse outputs. The ADE78xx devices incorporate ADE7854 Yes No Yes Yes No No
second-order sigma-delta (Σ-∆) analog-to-digital converters
(ADCs), a digital integrator, reference circuitry, and all of the
signal processing required to perform total (fundamental and
Rev. H Document Feedback

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ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Power Quality Measurements................................................... 34
Applications ....................................................................................... 1 Phase Compensation ................................................................. 39
General Description ......................................................................... 1 Reference Circuit ........................................................................ 41
Revision History ............................................................................... 3 Digital Signal Processor............................................................. 42
Functional Block Diagrams ............................................................. 5 Root Mean Square Measurement ............................................. 43
Specifications..................................................................................... 9 Active Power Calculation .......................................................... 47
Timing Characteristics .............................................................. 12 Reactive Power Calculation—ADE7858, ADE7868, ADE7878
Absolute Maximum Ratings.......................................................... 15 Only .............................................................................................. 52
Thermal Resistance .................................................................... 15 Apparent Power Calculation ..................................................... 57
ESD Caution ................................................................................ 15 Waveform Sampling Mode ....................................................... 60
Pin Configuration and Function Descriptions ........................... 16 Energy-to-Frequency Conversion............................................ 60
Typical Performance Characteristics ........................................... 18 No Load Condition .................................................................... 64
Test Circuit ...................................................................................... 21 Checksum Register..................................................................... 65
Terminology .................................................................................... 22 Interrupts ..................................................................................... 66
Power Management ........................................................................ 23 Serial Interfaces .......................................................................... 68
PSM0—Normal Power Mode (All Parts) ................................ 23 Quick Setup as Energy Meter ................................................... 75
PSM1—Reduced Power Mode (ADE7868, ADE7878 Only) 23 Layout Guidelines....................................................................... 75
PSM2—Low Power Mode (ADE7868, ADE7878 Only) ....... 23 Crystal Circuit ............................................................................ 76
PSM3—Sleep Mode (All Parts) ................................................ 24 ADE7878 Evaluation Board ...................................................... 76
Power-Up Procedure .................................................................. 26 Die Version .................................................................................. 76
Hardware Reset ........................................................................... 27 Silicon Anomaly ............................................................................. 77
Software Reset Functionality .................................................... 27 ADE7854/ADE7858/ADE7868/ADE7878 Functionality

Issues ............................................................................................ 77
Theory of Operation ...................................................................... 28
Functionality Issues.................................................................... 77
Analog Inputs .............................................................................. 28
Section 1. ADE7854/ADE7858/ADE7868/ADE7878
Analog-to-Digital Conversion .................................................. 28 Functionality Issues.................................................................... 79
Current Channel ADC............................................................... 29 Registers List ................................................................................... 80
di/dt Current Sensor and Digital Integrator .............................. 31 Outline Dimensions ....................................................................... 98
Voltage Channel ADC ............................................................... 32 Ordering Guide .......................................................................... 98
Changing Phase Voltage Datapath ........................................... 33
Rev. H | Page 2 of 100

REVISION HISTORY
4/14—Rev. G to Rev. H Changes to Equation 20 and to Equation 21 ............................... 45
Changes to Power-Up Procedure Section ....................................26 Changes to Active Energy Calculation Section........................... 46
Changes to Crystal Circuit Section ...............................................76 Changes to Figure 62 and to following text and to Equation 25 .... 47
Changes to Equation 32, Equation 34, and to Reactive
10/13—Rev. F to Rev. G Power Gain Calibration Section .................................................... 50
Changes to Product Title and Features Section ............................ 1 Changes to Reactive Energy Calculation Section ....................... 51
Changes to Table 2 ............................................................................ 9 Changes to Figure 66 ...................................................................... 52
Deleted Junction Temperature; Table 6 ........................................15 Changes to Energy Accumulation Modes Sections and to
Changes to NC and CLKIN Pin Descriptions .............................16 Caption for Figure 67...................................................................... 53
Replaced Typical Performance Characteristics Section .............18 Changes to Equation 40 ................................................................. 54
Added Text to Test Circuit Section ...............................................21 Changes to Apparent Power Calculation Using VNOM Section ... 55
Changes to Terminology Section ..................................................22 Changes to CF Outputs for Various Accumultation Modes
Changes to PSM2—Low Power Mode (ADE7868, ADE7878 Section .............................................................................................. 60
Only) Section and Added Figure 25 .............................................24 Changes to Sign of Sum-of-Phase Powers in the CFx
Changes to Changing Phase Voltage Datapath Section and Datapath Section and to Equation 47 ........................................... 61
Figure 42 ...........................................................................................33 Changes to Equation 48 ................................................................. 62
Changes to Reference Circuit Section; Added Figure 56, Changes to Checksum Register Section and to Table 23 ........... 63
Figure 57, and Figure 58; Renumbered Sequentially ..................41 Changes to Figure 81 ...................................................................... 66
Changes to Current RMS Compensation Section .........................44 Changes to Figure 82 ...................................................................... 67
Changes to Current Mean Absolute Value Calculation— Changes to SPI-Compatible Interface Section ............................ 68
ADE7868 and ADE7878 Only and Figure 60 ..............................45 Changes to HSDC Interface Section ............................................ 70
Changes to Voltage RMS Offset Compensation Section ...............47 Changes to Figure 88 ...................................................................... 71
Changes to Line Cycle Active Energy Accumulation Mode Changes to Figure 89, added Quick Setup as Energy Meter
Section ...............................................................................................51 Section, added Layout Guidelines, and added Figure 90;
Changes to Quick Setup as Energy Meter Section and Renumbered Sequentially .............................................................. 72
Figure 95 ...........................................................................................75 Added Figure 91 and Figure 92 ..................................................... 73
Changes to Figure 96 and Figure 97; Added Crystal Circuit Changes to Table 30 ........................................................................ 78
Section ..............................................................................................76 Changes to Table 33 ........................................................................ 79
Changes to Address 0xE520 Description; Table 33 ....................84 Changes to Table 46 ........................................................................ 90
Changes to Bit 11, Bit 12, Bit 13 Descriptions; Table 43 ............91 4/11—Rev. D to Rev. E
Updated Outline Dimensions ........................................................99
Changes to Input Clock FrequencyParameter, Table 2 .............. 10
10/12—Rev. E to Rev. F Changes to Current RMS Offset Compensation Section .......... 42
Changes to Figure 1........................................................................... 4 Changes to Voltage RMS Offset Compensation Section ........... 44
Changes to Figure 2........................................................................... 5 Changes to Note 2, Table 30........................................................... 77
Changes to Figure 3........................................................................... 6 Changes to Address 0xE707, Table 33 .......................................... 80
Changes to Figure 4........................................................................... 7 Changes to Table 45 ........................................................................ 87
Changes to Table 2 ............................................................................ 8 Changes to Table 46 ........................................................................ 88
Changes to Figure 5.........................................................................11 Changes to Bit Location 7:3, Default Value, Table 54 ................ 92
Added Text under Table 6 ..............................................................14 2/11—Rev. C to Rev. D
Changes to Figure 9 and to Table 8 ...............................................15
Changes to Power-Up Procedure Section ....................................24 Changes to Figure 1 .......................................................................... 4
Changes to Figure 31 and Figure 32 .............................................28 Changes to Figure 2 .......................................................................... 5
Changes to Figure 39 ......................................................................30 Changes to Figure 3 .......................................................................... 6
Changes to Voltage Waveform Gain Register Section................31 Changes to Figure 4 .......................................................................... 7
Changes to Figure 41 ......................................................................32 Changes to Table 2 ............................................................................ 8
Changes to Phase Compensation Section ....................................37 Changed SCLK Edge to HSCLK Edge, Table 5 ........................... 13
Changes to Digital Signal Processor Section ...............................39 Change to Current Channel HPF Section ................................... 28
Changes to Equation 12 ..................................................................40 Change to di/dt Current Sensor and Digital Integrator Section .... 30
Changes to Current RMS Offset Compensation Section ..........42 Changes to Digital Signal Processor Section ............................... 39
Changes to Voltage Channel RMS Calculation Section .............43 Changes to Figure 59 ...................................................................... 44
Changes to Voltage RMS Offset Compensation Section and Changes to Figure 62 ...................................................................... 47
to Figure 59 ......................................................................................44 Changes to Figure 65 ...................................................................... 49
Changes to Figure 66 ...................................................................... 52
Changes to Line Cycle Reactive Energy Accumulation Mode 3/10—Rev. 0 to Rev. A
Section and to Figure 67 ................................................................ 53 Added ADE7854, ADE7858, and ADE7878 ................... Universal
No Load Detection Based On Total Active, Reactive Powers Reorganized Layout............................................................ Universal
Section .............................................................................................. 61 Added Table 1, Renumbered Sequentially .....................................1
Change to Equation 50................................................................... 63 Added Figure 1, Renumbered Sequentially ...................................3
Changes to the HSDC Interface Section ..................................... 70 Added Figure 2...................................................................................4
Changes to Figure 87 and Figure 88 ............................................. 71 Added Figure 3...................................................................................5
Changes to Figure 89 ...................................................................... 72 Changes to Specifications Section ...................................................7
Changes to Table 30 ........................................................................ 77 Changes to Figure 9 and changes to Table 8 .............................. 14
Changes to Table 46 ........................................................................ 88 Changes to Typical Performance Characteristics Section ........ 16
11/10—Rev. B to Rev. C Changes to Figure 22...................................................................... 18
Change to Signal-to-Noise-and-Distortion Ratio, SINAD Changes to the Power Management Section .............................. 20
Parameter, Table 1............................................................................. 9 Changes to the Theory of Operation Section ............................. 25
Changes to Figure 18 ...................................................................... 18 Changes to Figure 31 and Figure 32............................................. 27
Changes to Figure 22 ...................................................................... 19 Change to Equation 28 .................................................................. 47
Changes to Silicon Anomaly Section ........................................... 72 Changes to Figure 83...................................................................... 66
Added Table 28 to Silicon Anomaly Section............................... 73 Changes to Figure 86...................................................................... 68
Changes to the Registers List Section .......................................... 72
8/10—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 91
Changes to Figure 1 .......................................................................... 4 2/10—Revision 0: Initial Version
Changes to Figure 2 .......................................................................... 5
Change to Table 8 ........................................................................... 16
Changes to Power-Up Procedure Section ................................... 23
Changes to Equation 6 and Equation 7 ....................................... 33
Changes to Equation 17 ................................................................. 43
Changes to Active Power Offset Calibration Section ................ 45
Changes to Reactive Power Offset Calibration Section............. 49
Added Silicon Anomaly Section, Renumbered Tables
Sequentially ..................................................................................... 71

Data Sheet
RESET REFIN/OUT VDD AGND AVDD DVDD DGND

4 17 26 25 24 5 6
AIRMSOS
ADE7854
AVAGAIN
2 PM0
CLKIN 27 X2 AIRMS
LPF
POR LDO LDO
CLKOUT 28 3 PM1
1.2V
REF
HPFDIS DIGITAL X2 AVRMS
[23:0] INTEGRATOR AIGAIN LPF
CF1DEN
AVRMSOS
FUNCTIONAL BLOCK DIAGRAMS
IAP 7
PGA1 ADC
HPF AWGAIN AWATTOS
IAN 8 DFC : 33 CF1
HPFDIS
APHCAL [23:0] AVGAIN
CF2DEN
LPF
PHASE A,
VAP 23 PHASE B,
PGA3 ADC AND 34 CF2
HPF DFC :
PHASE C
DATA
CF3DEN
IBP 9
PGA1 ADC TOTAL ACTIVE/APPARENT
IBN 12 ENERGIES AND VOLTAGE/
DFC : 35 CF3/HSCLK
CURRENT RMS CALCULATION FOR

PHASE B
VBP 22 (SEE PHASE A FOR DETAILED
PGA3 ADC DATA PATH)
29 IRQ0
Figure 1. ADE7854 Functional Block Diagram

ICP 13
TOTAL ACTIVE/APPARENT 32 IRQ1
PGA1 ADC
ENERGIES AND VOLTAGE/
ICN 14
CURRENT RMS CALCULATION FOR 36 SCLK/SCL
PHASE C
VCP 19 (SEE PHASE A FOR DETAILED
38 MOSI/SDA
PGA3 ADC DATA PATH) SPI
VN 18 OR
I2C/HSDC 37 MISO/HSD
DIGITAL SIGNAL
PROCESSOR 39 SS/HSA
08510-204
ADE7854/ADE7858/ADE7868/ADE7878
4 17 26 25 24 5 6
AIRMSOS
ADE7858
AVAGAIN
2 PM0
CLKIN 27 X2 AIRMS
LPF
POR LDO LDO
CLKOUT 28 3 PM1
1.2V
REF
CF1DEN
AVRMSOS
IAP 7
PGA1 ADC
HPF AWGAIN AWATTOS
IAN 8 DFC : 33 CF1
HPFDIS
CF2DEN
LPF
ADE7854/ADE7858/ADE7868/ADE7878
VAP 23 PHASE A,
PHASE B,
PGA3 ADC AND 34 CF2
HPF DFC :
PHASE C
AVARGAIN AVAROS DATA
COMPUTATIONAL CF3DEN
IBP 9
PGA1 ADC TOTAL ACTIVE/REACTIVE/ BLOCK FOR
IBN 12 APPARENT ENERGIES AND TOTAL
REACTIVE POWER DFC : 35 CF3/HSCLK
VOLTAGE/CURRENT

RMS CALCULATION FOR PHASE B
PGA3 ADC DATA PATH)
29 IRQ0

ICP 13
TOTAL ACTIVE/REACTIVE/ 32 IRQ1
PGA1 ADC
ICN 14 APPARENT ENERGIES AND
VOLTAGE/CURRENT 36 SCLK/SCL
RMS CALCULATION FOR PHASE C
SPI 38 MOSI/SDA
PGA3 ADC DATA PATH)
VN 18 OR
I2C/HSDC 37 MISO/HSD
DIGITAL SIGNAL
PROCESSOR 39 SS/HSA
08510-203
Data Sheet
Data Sheet

4 17 26 25 24 5 6
AIRMSOS
ADE7868
AVAGAIN
2 PM0
CLKIN 27 X2 AIRMS
LPF
POR LDO LDO
CLKOUT 28 3 PM1
1.2V
REF
CF1DEN
AVRMSOS
IAP 7
PGA1 ADC
HPF AWGAIN AWATTOS
IAN 8 DFC : 33 CF1
HPFDIS
CF2DEN
LPF
PHASE A,
VAP 23 PHASE B,
PGA3 ADC AND 34 CF2
HPF DFC :
PHASE C
AVARGAIN AVAROS DATA
IBP 9
PGA1 ADC TOTAL ACTIVE/REACTIVE/ BLOCK FOR
IBN 12 APPARENT ENERGIES AND TOTAL
VOLTAGE/CURRENT REACTIVE POWER DFC : 35 CF3/HSCLK

PGA3 ADC DATA PATH)
29 IRQ0

ICP 13
TOTAL ACTIVE/REACTIVE/ 32 IRQ1
PGA1 ADC
ICN 14 APPARENT ENERGIES AND
VOLTAGE/CURRENT 36 SCLK/SCL
38 MOSI/SDA
VN 18 OR
2
I C/HSDC 37 MISO/HSD
HPFDIS DIGITAL DIGITAL SIGNAL
[23:0] INTEGRATOR NIGAIN NIRMSOS PROCESSOR 39 SS/HSA
INP 15
PGA2 ADC X2 NIRMS
INN 16 HPF LPF
08510-202
ADE7854/ADE7858/ADE7868/ADE7878
4 17 26 25 24 5 6
AIRMSOS
ADE7878
AVAGAIN
2 PM0
CLKIN 27 X2 AIRMS
LPF
POR LDO LDO
CLKOUT 28 3 PM1
1.2V
REF
CF1DEN
AVRMSOS
IAP 7
PGA1 ADC
HPF AWGAIN AWATTOS
IAN 8 DFC : 33 CF1
HPFDIS
CF2DEN
LPF
ADE7854/ADE7858/ADE7868/ADE7878
PHASE A,
VAP 23 PHASE B,
PGA3 ADC 34 CF2
HPF AND DFC :
AVARGAIN AVAROS PHASE C
DATA
IBP 9
PGA1 ADC TOTAL/FUNDAMENTAL ACTIVE/ BLOCK FOR
IBN 12 REACTIVE ENERGIES, APPARENT TOTAL
REACTIVE POWER DFC : 35 CF3/HSCLK
ENERGY AND VOLTAGE/CURRENT

VBP 22 AFWGAIN AFWATTOS
(SEE PHASE A FOR DETAILED
PGA3 ADC DATA PATH)
29 IRQ0
COMPUTATIONAL

13 BLOCK FOR
ICP AFVARGAIN AFVAROS
TOTAL/FUNDAMENTAL ACTIVE/ FUNDAMENTAL 32 IRQ1
PGA1 ADC
REACTIVE ENERGIES, APPARENT ACTIVE AND
ICN 14
ENERGY AND VOLTAGE/CURRENT REACTIVE POWER 36 SCLK/SCL
VCP 19 (SEE PHASE A FOR DETAILED 38 MOSI/SDA
VN 18 OR
2
I C/HSDC 37 MISO/HSD
HPFDIS DIGITAL DIGITAL SIGNAL
[23:0] INTEGRATOR NIGAIN NIRMSOS 39 SS/HSA
PROCESSOR
INP 15
PGA2 ADC X2 NIRMS
INN 16 HPF LPF
08510-201
Data Sheet
SPECIFICATIONS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C, TTYP= 25°C.
Table 2.
Parameter 1, 2 Min Typ Max Unit Test Conditions/Comments
ACCURACY
Active Energy Measurement
Active Energy Measurement Error
(per Phase)
Total Active Energy 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;
integrator off
0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;
integrator off
0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;
integrator on
Fundamental Active Energy 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;
(ADE7878 Only) integrator off
integrator off
integrator on
AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz/100 Hz, IPx =
Output Frequency Variation 0.01 % VPx = ±100 mV rms
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc; IPx = VPx =
±100 mV rms
Output Frequency Variation 0.01 %
Total Active Energy Measurement 2 kHz
Bandwidth
REACTIVE ENERGY MEASUREMENT
(ADE7858, ADE7868, AND ADE7878)
Reactive Energy Measurement Error
(per Phase)
Total Reactive Energy 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;
integrator off
integrator off
integrator on
Fundamental Reactive Energy 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;
(ADE7878 Only) integrator off
integrator off
integrator on
AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz/100 Hz, IPx =
Output Frequency Variation 0.01 % VPx = ±100 mV rms
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc; IPx = VPx =
±100 mV rms
Output Frequency Variation 0.01 %
Total Reactive Energy Measurement 2 kHz
Bandwidth
RMS MEASUREMENTS
I rms and V rms Measurement 2 kHz
Bandwidth
I rms and V rms Measurement Error 0.1 % Over a dynamic range of 1000 to 1, PGA = 1
(PSM0 Mode)

MEAN ABSOLUTE VALUE (MAV)
MEASUREMENT (ADE7868 AND
ADE7878)
I mav Measurement Bandwidth (PSM1 260 Hz
Mode)
I mav Measurement Error (PSM1 Mode) 0.5 % Over a dynamic range of 100 to 1, PGA = 1, 2, 4, 8
ANALOG INPUTS
Maximum Signal Levels ±500 mV peak PGA = 1, differential inputs between the
following pins: IAP and IAN, IBP and IBN, ICP
and ICN; single-ended inputs between the
following pins: VAP and VN, VBP and VN, VCP,
and VN
Input Impedance (DC)
IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, 400 kΩ
and VCP Pins
VN Pin 130 kΩ
ADC Offset −24 mV PGA = 1, uncalibrated error, see the Terminology
section
Gain Error ±4 % External 1.2 V reference
WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS
Current and Voltage Channels See the Waveform Sampling Mode section
Signal-to-Noise Ratio, SNR 74 dB PGA = 1, fundamental frequency: 45 Hz to
65 Hz, see the Terminology section
Signal-to-Noise-and-Distortion Ratio, 74 dB PGA = 1; fundamental frequency: 45 Hz to
SINAD 65 Hz, see the Terminology section
Bandwidth (−3 dB) 2 kHz
TIME INTERVAL BETWEEN PHASES
Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on
CF1, CF2, CF3 PULSE OUTPUTS
Maximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139
Duty Cycle 50 % If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is even and > 1
(1 + 1/CFDEN) If CF1, CF2, or CF3 frequency > 6.25 Hz and
× 50% CFDEN is odd and > 1
Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz
Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz and
nominal phase currents are larger than 10% of
full scale
REFERENCE INPUT
REFIN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8%
Input Capacitance 10 pF
ON-CHIP REFERENCE Nominal 1.2 V at the REFIN/OUT pin at TA = 25°C
PSM0 and PSM1 Modes
Temperature Coefficient −50 ±5 +50 ppm/°C Drift across the entire temperature range of −40°C
to +85°C is calculated with reference to 25°C;
see the Reference Circuit section for more details
CLKIN All specifications CLKIN of 16.384 MHz. See the
Crystal Circuit section for more details.
Input Clock Frequency 16.22 16.384 16.55 MHz
LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS,
RESET, PM0, AND PM1
Input High Voltage, VINH 2.0 V VDD = 3.3 V ± 10%
Input Low Voltage, VINL 0.8 V VDD = 3.3 V ± 10%
Input Current, IIN −8.7 µA Input = 0 V, VDD = 3.3 V
3 μA Input = VDD = 3.3 V
Input Capacitance, CIN 10 pF
LOGIC OUTPUTS—IRQ0, IRQ1, MISO/HSD VDD = 3.3 V ± 10%
Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 10%
ISOURCE 800 µA
Output Low Voltage, VOL 0.4 V VDD = 3.3 V ± 10%
ISINK 2 mA
CF1, CF2, CF3/HSCLK
Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 10%
ISOURCE 500 µA
Output Low Voltage, VOL 0.4 V VDD = 3.3 V ± 10%
ISINK 2 mA
POWER SUPPLY For specified performance
PSM0 Mode
VDD Pin 2.97 3.63 V Minimum = 3.3 V − 10%; maximum = 3.3 V + 10%
IDD 24.4 27.2 mA
PSM1 and PSM2 Modes (ADE7868 and
ADE7878)
VDD Pin 2.4 3.7 V
IDD
PSM1 Mode 6.0 mA
PSM2 Mode 0.2 mA
PSM3 Mode
VDD Pin 2.4 3.7 V
IDD in PSM3 Mode 1.7 μA
1
See the Typical Performance Characteristics section.
2
See the Terminology section for a definition of the parameters.

TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams; see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions.
Table 3. I2C-Compatible Interface Timing Parameter

Standard Mode Fast Mode
Parameter Symbol Min Max Min Max Unit
SCL Clock Frequency fSCL 0 100 0 400 kHz
Hold Time (Repeated) Start Condition tHD;STA 4.0 0.6 μs
Low Period of SCL Clock tLOW 4.7 1.3 µs
High Period of SCL Clock tHIGH 4.0 0.6 µs
Set-Up Time for Repeated Start Condition tSU;STA 4.7 0.6 µs
Data Hold Time tHD;DAT 0 3.45 0 0.9 µs
Data Setup Time tSU;DAT 250 100 ns
Rise Time of Both SDA and SCL Signals tR 1000 20 300 ns
Fall Time of Both SDA and SCL Signals tF 300 20 300 ns
Setup Time for Stop Condition tSU;STO 4.0 0.6 µs
Bus Free Time Between a Stop and Start Condition tBUF 4.7 1.3 µs
Pulse Width of Suppressed Spikes tSP N/A 1 50 ns
1
N/A means not applicable.
SDA
tBUF
tF tSU;DAT tHD;STA tSP tR
tR
tLOW tF
SCLK
tHD;STA
tHD;DAT tSU;STA tSU;STO
tHIGH
08510-002
START REPEATED START STOP START
CONDITION CONDITION CONDITION CONDITION
Figure 5. I2C-Compatible Interface Timing

Table 4. SPI Interface Timing Parameters
Parameter Symbol Min Max Unit
SS to SCLK Edge tSS 50 ns
SCLK Period 0.4 4000 1 μs
SCLK Low Pulse Width tSL 175 ns
SCLK High Pulse Width tSH 175 ns
Data Output Valid After SCLK Edge tDAV 100 ns
Data Input Setup Time Before SCLK Edge tDSU 100 ns
Data Input Hold Time After SCLK Edge tDHD 5 ns
Data Output Fall Time tDF 20 ns
Data Output Rise Time tDR 20 ns
SCLK Rise Time tSR 20 ns
SCLK Fall Time tSF 20 ns
MISO Disable After SS Rising Edge tDIS 200 ns
SS High After SCLK Edge tSFS 0 ns
1
Guaranteed by design.
SS
tSS
tSFS
SCLK
tSL
tSH tSF tSR
tDAV
tDIS
MISO MSB INTERMEDIATE BITS LSB
tDF tDR
INTERMEDIATE BITS
MOSI MSB IN LSB IN
tDSU
08510-003
tDHD
Figure 6. SPI Interface Timing

Table 5. HSDC Interface Timing Parameter
Parameter Symbol Min Max Unit
HSA to HSCLK Edge tSS 0 ns
HSCLK Period 125 ns
HSCLK Low Pulse Width tSL 50 ns
HSCLK High Pulse Width tSH 50 ns
Data Output Valid After HSCLK Edge tDAV 40 ns
Data Output Fall Time tDF 20 ns
Data Output Rise Time tDR 20 ns
HSCLK Rise Time tSR 10 ns
HSCLK Fall Time tSF 10 ns
HSD Disable After HSA Rising Edge tDIS 5 ns
HSA High After HSCLK Edge tSFS 0 ns
HSA
tSS
tSFS
HSCLK
tSL
tSH tSF tSR

tDAV
tDIS
HSD MSB INTERMEDIATE BITS LSB
08510-004
tDF tDR
Figure 7. HSDC Interface Timing
2mA IOL
TO OUTPUT 1.6V
PIN
CL
50pF
800µA IOH
08510-005
Figure 8. Load Circuit for Timing Specifications

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 6. θJA is specified equal to 29.3°C/W; θJC is specified equal to
Parameter Rating 1.8°C/W.
VDD to AGND −0.3 V to +3.7 V Table 7. Thermal Resistance
VDD to DGND −0.3 V to +3.7 V Package Type θJA θJC Unit
Analog Input Voltage to AGND, IAP, −2 V to +2 V 40-Lead LFCSP 29.3 1.8 °C/W
IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP,
VN
Analog Input Voltage to INP and INN −2 V to +2 V
ESD CAUTION
Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Operating Temperature
Industrial Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Note that, regarding the temperature profile used in soldering
RoHS compliant parts, Analog Devices advises that reflow
profiles should conform to J-STD 20 from JEDEC. Refer to
www.jedec.org for the latest revision.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CF3/HSCLK
SCLK/SCL
MISO/HSD
MOSI/SDA
SS/HSA
IRQ1
CF2
CF1
NC
NC
32
31
40
39
38
37
36
35
34
33
NC 1 30 NC
PM0 2 29 IRQ0
PM1 3 28 CLKOUT
RESET 4 27 CLKIN
DVDD 5 ADE78xx 26 VDD
DGND 6 TOP VIEW 25 AGND
IAP 7 (Not to Scale) 24 AVDD
IAN 8 23 VAP
IBP 9 22 VBP
NC 10 21 NC
11
12
13
14
15
16
17
18
19
20
REFIN/OUT
IBN
ICP
INP
ICN
INN
VN
VCP
NC
NC
NOTES
1. NC = NO CONNECT.
2. CREATE A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD. SOLDER THE EXPOSED PAD TO
08510-106
THE PAD ON THE PCB TO CONFER MECHANICAL
STRENGTH TO THE PACKAGE. CONNECT THE
PADS TO AGND AND DGND.
Figure 9. Pin Configuration
Table 8. Pin Function Descriptions

Pin No. Mnemonic Description
1, 10, 11, 20, NC No Connect. These pins are not connected internally. It is recommended to ground these pins.
21, 30, 31, 40
2 PM0 Power Mode Pin 0. This pin, combined with PM1, defines the power mode of the
ADE7854/ADE7858/ADE7868/ADE7878, as described in Table 9.
3 PM1 Power Mode Pin 1. This pin defines the power mode of the ADE7854/ADE7858/ADE7868/ADE7878
when combined with PM0, as described in Table 9.
4 RESET Reset Input, Active Low. In PSM0 mode, this pin should stay low for at least 10 µs to trigger a
hardware reset.
5 DVDD 2.5 V output of the digital low dropout regulator (LDO). Decouple this pin with a 4.7 µF capacitor in
parallel with a ceramic 220 nF capacitor. Do not connect external active circuitry to this pin.
6 DGND Ground Reference. This pin provides the ground reference for the digital circuitry.
7, 8 IAP, IAN Analog Inputs for Current Channel A. This channel is used with the current transducers and is
referenced in this document as Current Channel A. These inputs are fully differential voltage inputs
with a maximum differential level of ±0.5 V. This channel also has an internal PGA equal to the ones
on Channel B and Channel C.
9, 12 IBP, IBN Analog Inputs for Current Channel B. This channel is used with the current transducers and is
referenced in this document as Current Channel B. These inputs are fully differential voltage inputs
on Channel C and Channel A.
13, 14 ICP, ICN Analog Inputs for Current Channel C. This channel is used with the current transducers and is
referenced in this document as Current Channel C. These inputs are fully differential voltage inputs
on Channel A and Channel B.
15, 16 INP, INN Analog Inputs for Neutral Current Channel N. This channel is used with the current transducers and
is referenced in this document as Current Channel N. These inputs are fully differential voltage
inputs with a maximum differential level of ±0.5 V. This channel also has an internal PGA, different
from the ones found on the A, B, and C channels. The neutral current channel is available in the
ADE7878 and ADE7868. In the ADE7858 and ADE7854, connect these pins to AGND.
17 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal
value of 1.2 V. An external reference source with 1.2 V ± 8% can also be connected at this pin. In
either case, decouple this pin to AGND with a 4.7 µF capacitor in parallel with a ceramic 100 nF
capacitor. After reset, the on-chip reference is enabled.

Pin No. Mnemonic Description
18, 19, 22, 23 VN, VCP, VBP, VAP Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is
referenced as the voltage channel in this document. These inputs are single-ended voltage inputs
with a maximum signal level of ±0.5 V with respect to VN for specified operation. This channel also
has an internal PGA.
24 AVDD 2.5 V output of the analog low dropout regulator (LDO). Decouple this pin with a 4.7 µF capacitor in
parallel with a ceramic 220 nF capacitor. Do not connect external active circuitry to this pin.
25 AGND Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the
analog ground plane or to the quietest ground reference in the system. Use this quiet ground
reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.
26 VDD Supply Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the
supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low
power mode), and PSM3 (sleep mode), when the ADE7868/ADE7878 is supplied from a battery,
maintain the supply voltage between 2.4 V and 3.7 V. Decouple this pin to AGND with a 10 µF
capacitor in parallel with a ceramic 100 nF capacitor. The only modes available on the ADE7858 and
ADE7854 are the PSM0 and PSM3 power modes.
27 CLKIN Master Clock. An external clock can be provided at this logic input. Alternatively, a crystal can be
connected across CLKIN and CLKOUT to provide a clock source for the ADE7854/ADE7858/
ADE7868/ADE7878. The clock frequency for specified operation is 16.384 MHz. See the Crystal
Circuit section for details on choosing a suitable crystal.
28 CLKOUT A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this
table) to provide a clock source for the ADE7854/ADE7858/ADE7868/ADE7878.
29, 32 IRQ0, IRQ1 Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a
detailed presentation of the events that can trigger interrupts.
33, 34, 35 CF1, CF2, Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the
CF3/HSCLK CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. These outputs are used for
operational and calibration purposes. The full-scale output frequency can be scaled by writing to the
CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion
section). CF3 is multiplexed with the serial clock output of the HSDC port.
36 SCLK/SCL Serial Clock Input for SPI Port/Serial Clock Input for I2C Port. All serial data transfers are synchronized
to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a
clock source that has a slow edge transition time, for example, opto-isolator outputs.
37 MISO/HSD Data Out for SPI Port/Data Out for HSDC Port.
38 MOSI/SDA Data In for SPI Port/Data Out for I2C Port.
39 SS/HSA Slave Select for SPI Port/HSDC Port Active.
EP Exposed Pad Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the
PCB to confer mechanical strength to the package. Connect the pads to AGND and DGND.

TYPICAL PERFORMANCE CHARACTERISTICS

1.5 1.5
+85°C VDD = 3.3V +85°C VDD = 3.3V
1.2 +25°C 1.2 +25°C
–40°C –40°C
0.9 0.9
0.6 0.6
0.3 0.3
ERROR (%)
ERROR (%)
0 0
–0.3 –0.3
–0.6 –0.6
–0.9 –0.9
–1.2 –1.2
–1.5 –1.5
08510-601
08510-604
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 10. Total Active Energy Error As Percentage of Reading (Gain = +1, Figure 13. Total Active Energy Error As Percentage of Reading (Gain = +16,
Power Factor = 1) over Temperature with Internal Reference and Integrator Off Power Factor = 1) over Temperature with Internal Reference and Integrator On
0.15 1.5
PF = +0.5 +85°C VDD = 3.3V
PF = –0.5 1.2 +25°C
PF = +1.0 –40°C
0.10
0.9
0.6
0.05
0.3
ERROR (%)
ERROR (%)
0 0
–0.3
–0.05
–0.6
–0.9
–0.10
–1.2
–0.15 –1.5
08510-605
08510-602
45 50 55 60 65 0.01 0.1 1 10 100

LINE FREQUENCY (Hz) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 11. Total Active Energy Error As Percentage of Reading (Gain = +1) Figure 14. Total Reactive Energy Error As Percentage of Reading (Gain = +1,
over Frequency with Internal Reference and Integrator Off Power Factor = 0) over Temperature with Internal Reference and Integrator Off
1.5 0.15
3.63V TA = 25°C PF = +0.866
1.2 3.30V PF = –0.866
2.97V PF = 0
0.10
0.9
0.6
0.05
0.3
ERROR (%)
ERROR (%)
0 0
–0.3
–0.05
–0.6
–0.9
–0.10
–1.2
–1.5 –0.15
08510-606
08510-603
0.01 0.1 1 10 100 45 50 55 60 65

PERCENTAGE OF FULL-SCALE CURRENT (%) LINE FREQUENCY (Hz)
Figure 12. Total Active Energy Error As Percentage of Reading (Gain = +1, Figure 15. Total Reactive Energy Error As Percentage of Reading (Gain = +1)
Power Factor = 1) over Power Supply with Internal Reference and Integrator Off over Frequency with Internal Reference and Integrator Off

1.5 1.5
3.63V TA = 25°C +85°C VDD = 3.3V
1.2 3.30V 1.2 +25°C
2.97V –40°C
0.9 0.9
0.6 0.6
0.3 0.3
ERROR (%)
ERROR (%)
0 0
–0.3 –0.3
–0.6 –0.6
–0.9 –0.9
–1.2 –1.2
–1.5 –1.5
08510-607
08510-610
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 16. Total Reactive Energy Error As Percentage of Reading (Gain = +1, Figure 19. Fundamental Active Energy Error As Percentage of Reading
Power Factor = 0) over Power Supply with Internal Reference and Integrator Off (Gain = +16) over Temperature with Internal Reference and Integrator On
1.5 0.15
+85°C VDD = 3.3V PF = +0.866
1.2 +25°C PF = –0.866
–40°C PF = 0
0.10
0.9
0.6
0.05
0.3
ERROR (%)
ERROR (%)
0 0
–0.3
–0.05
–0.6
–0.9
–0.10
–1.2
–1.5 –0.15
08510-608
08510-611
0.01 0.1 1 10 100 45 50 55 60 65
PERCENTAGE OF FULL-SCALE CURRENT (%) LINE FREQUENCY (Hz)
Figure 17. Total Reactive Energy Error As Percentage of Reading (Gain = +16, Figure 20. Fundamental Reactive Energy Error As Percentage of Reading
Power Factor = 0) over Temperature with Internal Reference and Integrator On (Gain = +1) over Frequency with Internal Reference and Integrator Off
0.15 1.5
PF = +0.5 +85°C VDD = 3.3V
PF = –0.5 1.2 +25°C
PF = +1.0 –40°C
0.10
0.9
0.6
0.05
0.3
ERROR (%)
ERROR (%)
0 0
–0.3
–0.05
–0.6
–0.9
–0.10
–1.2
–0.15 –1.5
08510-609
08510-612
45 50 55 60 65 0.01 0.1 1 10 100

LINE FREQUENCY (Hz) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 18. Fundamental Active Energy Error As Percentage of Reading Figure 21. Fundamental Reactive Energy Error As Percentage of Reading
(Gain = +1) over Frequency with Internal Reference and Integrator Off (Gain = +16) over Temperature with Internal Reference and Integrator On

1.5
+85°C VDD = 3.3V
1.2 +25°C
–40°C
0.9
0.6
0.3
ERROR (%)
–0.3
–0.6
–0.9
–1.2
–1.5
08510-613
0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 22. IRMS Error as Percentage of Reading (Gain = +1, Power Factor = 1)
over Temperature with Internal Reference and Integrator Off

TEST CIRCUIT
Note that in Figure 23, the PM1 and PM0 pins are pulled up internally to 3.3 V. Select the mode of operation by using a microcontroller to
programmatically change the pin values.
3.3V
+
10µF 0.1µF
+ +
4.7µF 0.22µF 4.7µF 0.22µF
24 26 5
VDD
AVDD
DVDD
3.3V 2 PM0
SS/HSA 39
3 PM1
10kΩ 1µF
MOSI/SDA 38
1kΩ 4 RESET
MISO/HSD 37
22nF 7 IAP
SCLK/SCL 36 3.3V
22nF 8 IAN
CF3/HSCLK 35
1kΩ 9 IBP 10kΩ
SAME AS
IAP, IAN CF2 34
12 IBN ADE78xx
SAME AS 1.5kΩ
CF1 33 CF2
13 ICP
SAME AS
IAP, IAN IRQ1 32
14 ICN
1kΩ 22nF IRQ0 29
18 VN
REFIN/OUT 17
19 VCP CL2 +
4.7µF 0.1µF
1kΩ 22nF SAME AS CLKOUT 28
22 VBP
VCP
5MΩ 16.384MHz
SAME AS
AGND
DGND
23 VAP
VCP
CLKIN 27
CL1
6 25
08510-099
Figure 23. Test Circuit

TERMINOLOGY
Measurement Error Gain Error
The error associated with the energy measurement made by the The gain error in the ADCs of the ADE7854/ADE7858/
ADE7854/ADE7858/ADE7868/ADE7878 is defined by ADE7868/ADE7878 is defined as the difference between the
Measurement Error = measured ADC output code (minus the offset) and the ideal
Energy Registered by ADE78 xx − True Energy output code (see the Current Channel ADC section and the
× 100% (1) Voltage Channel ADC section). The difference is expressed as a
True Energy
percentage of the ideal code.
Power Supply Rejection (PSR) CF Jitter
This quantifies the ADE7854/ADE7858/ADE7868/ADE7878
The period of pulses at one of the CF1, CF2, or CF3 pins is
measurement error as a percentage of reading when the power
continuously measured. The maximum, minimum, and average
supplies are varied. For the ac PSR measurement, a reading at
values of four consecutive pulses are computed as follows:
nominal supplies (3.3 V) is taken. A second reading is obtained
with the same input signal levels when an ac signal (120 mV rms Maximum = max(Period0, Period1, Period2, Period3)
at twice the fundamental frequency) is introduced onto the Minimum = min(Period0, Period1, Period2, Period3)
supplies. Any error introduced by this ac signal is expressed as a
percentage of reading—see the Measurement Error definition. Period 0 + Period1 + Period 2 + Period 3
Average =
4
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same The CF jitter is then computed as
input signal levels when the power supplies are varied ±10%. Maximum − Minimum
CFJITTER = × 100% (2)
Any error introduced is expressed as a percentage of the Average
reading.
Signal-to-Noise Ratio (SNR)
ADC Offset Error SNR is the ratio of the rms value of the actual input signal to
This refers to the dc offset associated with the analog inputs to the rms sum of all other spectral components below 2 kHz,
the ADCs. It means that with the analog inputs connected to excluding harmonics and dc. The input signal contains only
AGND, the ADCs still see a dc analog input signal. The magni- the fundamental component. The spectral components are
tude of the offset depends on the gain and input range selection calculated over a 2 sec window. The value for SNR is expressed
However, the HPF removes the offset from the current and voltage in decibels.
channels and the power calculation remains unaffected by this
offset. Signal-to-(Noise and Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below 2 kHz,
including harmonics but excluding dc. The input signal
contains only the fundamental component. The spectral
components are calculated over a 2 sec window. The value
for SINAD is expressed in decibels.

POWER MANAGEMENT
The ADE7868/ADE7878 have four modes of operation, deter- In summary, in this mode, it is not recommended to access any
mined by the state of the PM0 and PM1 pins (see Table 9). The register other than AIMAV, BIMAV, and CIMAV. The circuit
ADE7854/ADE7858 have two modes of operation. These pins that measures these estimates of rms values is also active during
provide complete control of the ADE7854/ADE7858/ADE7868/ PSM0; therefore, its calibration can be completed in either PSM0
ADE7878 operation and can easily be connected to an external mode or in PSM1 mode. Note that the ADE7868 and ADE7878
microprocessor I/O. The PM0 and PM1 pins have internal pull- do not provide any register to store or process the corrections
up resistors. See Table 11 and Table 12 for a list of actions that are resulting from the calibration process. The external microprocessor
recommended before and after setting a new power mode. stores the gain values in connection with these measurements
and uses them during PSM1 (see the Current Mean Absolute
Table 9. Power Supply Modes Value Calculation—ADE7868 and ADE7878 Only section for
Power Supply Modes PM1 PM0 more details on the xIMAV registers).
PSM0, Normal Power Mode 0 1
The 20-bit mean absolute value measurements done in PSM1,
PSM1, Reduced Power Mode1 0 0
although available also in PSM0, are different from the rms
PSM2, Low Power Mode1 1 0
measurements of phase currents and voltages executed only in
PSM3, Sleep Mode 1 1
PSM0 and stored in the xIRMS and xVRMS 24-bit registers.
1
Available in the ADE7868 and ADE7878.
See the Current Mean Absolute Value Calculation—ADE7868
PSM0—NORMAL POWER MODE (ALL PARTS) and ADE7878 Only section for details.
In PSM0 mode, the ADE7854/ADE7858/ADE7868/ADE7878 If the ADE7868/ADE7878 is set in PSM1 mode while still in the
are fully functional. The PM0 pin is set to high and the PM1 pin PSM0 mode, the ADE7868/ADE7878 immediately begin the
is set to low for the ADE78xx to enter this mode. If the ADE78xx mean absolute value calculations without any delay. The xIMAV
is in one of PSM1, PSM2, or PSM3 modes and is switched into registers are accessible at any time; however, if the ADE7878 or
PSM0 mode, then all control registers take the default values with ADE7868 is set in PSM1 mode while still in PSM2 or PSM3
the exception of the threshold register, LPOILVL, which is used modes, the ADE7868/ADE7878 signal the start of the mean
in PSM2 mode, and the CONFIG2 register, both of which absolute value computations by triggering the IRQ1 pin low.
maintain their values. The xIMAV registers can be accessed only after this moment.
The ADE7854/ADE7858/ADE7868/ADE7878 signal the end of PSM2—LOW POWER MODE (ADE7868, ADE7878
the transition period by triggering the IRQ1 interrupt pin low and ONLY)
setting Bit 15 (RSTDONE) in the STATUS1 register to 1. This bit is
The low power mode, PSM2, is available on the ADE7868 and
0 during the transition period and becomes 1 when the transition is
ADE7878 only. In this mode, the ADE7868/ADE7878 compare
finished. The status bit is cleared and the IRQ1 pin is set back to
all phase currents against a threshold for a period of 0.02 ×
high by writing to the STATUS1 register with the corresponding (LPLINE[4:0] + 1) seconds, independent of the line frequency.
bit set to 1. Bit 15 (RSTDONE) in the interrupt mask register LPLINE[4:0] are Bits[7:3] of the LPOILVL register (see Table 10).
does not have any functionality attached even if the IRQ1 pin goes
low when Bit 15 (RSTDONE) in the STATUS1 register is set to 1. Table 10. LPOILVL Register
This makes the RSTDONE interrupt unmaskable. Bit Mnemonic Default Description
[2:0] LPOIL[2:0] 111 Threshold is put at a value
PSM1—REDUCED POWER MODE (ADE7868,
corresponding to full scale
ADE7878 ONLY) multiplied by LPOIL/8.
The reduced power mode, PSM1, is available on the ADE7868 [7:3] LPLINE[4:0] 00000 The measurement period is
and ADE7878 only. In this mode, the ADE7868/ADE7878 (LPLINE[4:0] + 1)/50 sec.
measure the mean absolute values (mav) of the 3-phase currents
and store the results in the AIMAV, BIMAV, and CIMAV 20-bit
registers. This mode is useful in missing neutral cases in which
the voltage supply of the ADE7868 or ADE7878 is provided by an
external battery. The serial ports, I2C or SPI, are enabled in this
mode; the active port can be used to read the AIMAV, BIMAV,
and CIMAV registers. It is not recommended to read any of the
other registers because their values are not guaranteed in this
mode. Similarly, a write operation is not taken into account by
the ADE7868/ADE7878 in this mode.

The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the The PSM2 level threshold comparison works based on a peak
LPOILVL register as LPOIL[2:0]/8 of full scale. Every time detection methodology. The peak detect circuit makes the
one phase current becomes greater than the threshold, a comparison based on the positive terminal current channel
counter is incremented. If every phase counter remains below input, IAP, IBP, and ICP (see Figure 25). In case of differential
LPLINE[4:0] + 1 at the end of the measurement period, then inputs being applied to the current channels, Figure 25 shows
the IRQ0 pin is triggered low. If a single phase counter becomes the differential antiphase signals at each of the current input
greater or equal to LPLINE[4:0] + 1 at the end of the measure- terminals, IxP and IxN, and the net differential current, IxP – IxN.
ment period, the IRQ1 pin is triggered low. Figure 24 illustrates The I2C or SPI port is not functional during this mode. The PSM2
how the ADE7868/ADE7878 behave in PSM2 mode when mode reduces the power consumption required to monitor the
LPLINE[4:0] = 2 and LPOIL[2:0] = 3. The test period is three currents when there is no voltage input and the voltage supply
50 Hz cycles (60 ms), and the Phase A current rises above the of the ADE7868/ADE7878 is provided by an external battery. If
LPOIL[2:0] threshold three times. At the end of the test period, the IRQ0 pin is triggered low at the end of a measurement period,
the IRQ1 pin is triggered low. this signifies all phase currents stayed below threshold and,
LPLINE[4:0] = 2 therefore, there is no current flowing through the system.
At this point, the external microprocessor sets the ADE7868/
LPOIL[2:0] ADE7878 into Sleep Mode PSM3. If the IRQ1 pin is triggered
THRESHOLD
IA CURRENT
low at the end of the measurement period, this signifies that at
least one current input is above the defined threshold and
current is flowing through the system, although no voltage is
present at the ADE7868/ADE7878 pins. This situation is often
called missing neutral and is considered a tampering situation,
at which point the external microprocessor sets the ADE7868/
ADE7878into PSM1 mode, measures the mean absolute values
of phase currents, and integrates the energy based on their values
PHASE PHASE PHASE and the nominal voltage.
COUNTER = 1 COUNTER = 2 COUNTER = 3
It is recommended to use the ADE7868/ADE7878 in PSM2
08510-008
IRQ1 mode when Bits[2:0] (PGA1[2:0]) of the gain register are equal
Figure 24. PSM2 Mode Triggering IRQ1 Pin for LPLINE[4:0] = 2 to 1 or 2. These bits represent the gain in the current channel
(50 Hz Systems) datapath. It is not recommended to use the ADE7868/ADE7878
+V p-p/2 in PSM2 mode when the PGA1[2:0] bits are equal to 4, 8, or 16.
+V p-p
IxP
PSM3—SLEEP MODE (ALL PARTS)
IxP – IxN
The sleep mode is available on all parts (ADE7854, ADE7858,
–V p-p/2
ADE7868, and ADE7878). In this mode, the ADE78xx has most
+V p-p/2
of its internal circuits turned off and the current consumption is
IxN at its lowest level. The I2C, HSDC, and SPI ports are not func-
–V p-p tional during this mode, and the RESET, SCLK/SCL, MOSI/SDA,
–V p-p/2 and SS/HSA pins should be set high.
(a)
IxP
TAMPER
PEAK DETECT CIRCUIT INDICATION
VREF
08510-503
(b)
Figure 25. PSM2 Low Power Mode Peak Detection

Table 11. Power Modes and Related Characteristics
LPOILVL,
Power Mode All Registers1 CONFIG2 I2C/SPI Functionality
PSM0
State After Hardware Reset Set to default Set to default I2C enabled All circuits are active and DSP
is in idle mode.
State After Software Reset Set to default Unchanged Active serial port is unchanged if lock-in All circuits are active and DSP
procedure has been previously executed is in idle mode.
PSM1—ADE7878, ADE7868 Only Not available Values set Enabled Current mean absolute values
during PSM0 are computed and the results
unchanged are stored in the AIMAV,
BIMAV, and CIMAV registers.
The I2C or SPI serial port is
enabled with limited
functionality.
PSM2—ADE7878, ADE7868 Only Not available Values set Disabled Compares phase currents
during PSM0 against the threshold set in
unchanged LPOILVL. Triggers IRQ0or IRQ1
pins accordingly. The serial
ports are not available.
PSM3 Not available Values set Disabled Internal circuits shut down
during PSM0 and the serial ports are not
unchanged available.
1
Setting for all registers except the LPOILVL and CONFIG2 registers.
Table 12. Recommended Actions When Changing Power Modes

Recommended Actions Next Power Mode
Initial Power Before Setting Next
Mode Power Mode PSM0 PSM1 PSM2 PSM3
PSM0 Stop DSP by setting the run Current mean absolute Wait until the IRQ0 or No action
register = 0x0000. values (mav) computed IRQ1 pin is triggered necessary.
immediately. accordingly.
Disable HSDC by clearing Bit 6 xIMAV registers can be
(HSDEN) to 0 in the CONFIG accessed immediately.
register.
Mask interrupts by setting
MASK0 = 0x0 and
MASK1 = 0x0.
Erase interrupt status flags in
the STATUS0 and STATUS1
registers.
PSM1— No action necessary. Wait until the IRQ1 pin is Wait until the IRQ0 or No action
ADE7878, triggered low. IRQ1 pin is triggered necessary.
ADE7868 Only Poll the STATUS1 register accordingly.
until Bit 15 (RSTDONE) is
set to 1.
PSM2— No action necessary. Wait until the IRQ1 pin is Wait until the IRQ1 pin No action
ADE7878, triggered low. triggered low. necessary.
ADE7868 Only Poll the STATUS1 register Current mean absolute
until Bit 15 (RSTDONE) is values compute at this
set to 1. moment.
xIMAV registers may be
accessed from this
moment.
PSM3 No action necessary. Wait until the IRQ1 pin is Wait until the IRQ1 pin is Wait until the IRQ0 or
triggered low. triggered low. IRQ1 pin is triggered
Poll the STATUS1 register Current mav circuit begins accordingly.
until Bit 15 (RSTDONE) is computations at this time.
set to 1.
xIMAV registers can be
accessed from this
moment.

POWER-UP PROCEDURE
3.3V – 10%
VDD 2.0V ± 10% ADE78xx

PSM0 READY
0V
~26ms ~40ms
MICROPROCESSOR
MAKES THE
MICROPROCESSOR POR TIMER ADE78xx RSTDONE CHOICE BETWEEN
08510-009
SETS PM1 PIN TO 0; TURNED ON FULLY INTERRUPT I2C AND SPI
APPLY VDD TO CHIP POWERED UP TRIGGERED
Figure 26. Power-Up Procedure
The ADE7854/ADE7858/ADE7868/ADE7878 contain an on- Immediately after entering PSM0 mode, all registers in the
chip power supply monitor that supervises the power supply ADE7854/ADE7858/ADE7868/ADE7878 are set to their default
(VDD). At power-up, the device is inactive until VDD reaches values, including the CONFIG2 and LPOILVL registers.
2 V ± 10%. When VDD crosses this threshold, the power supply The ADE7854/ADE7858/ADE7868/ADE7878 signal the end of
monitor keeps the device in the inactive state for an additional the transition period by pulling the IRQ1 interrupt pin low and
26 ms to allow VDD to rise to 3.3 V − 10%, the minimum
setting Bit 15 (RSTDONE) in the STATUS1 register to 1. This
recommended supply voltage.
bit is cleared to 0 during the transition period and is set to 1
The PM0 and PM1 pins have internal pull-up resistors, but it is when the transition ends. Writing the STATUS1 register with
necessary to set the PM1 pin to Logic 0 either through a the RSTDONE bit set to 1 clears the status bit and returns the
microcontroller or by grounding the PM1 pin externally, before IRQ1 pin high. Because RSTDONE is an unmaskable interrupt,
powering up the chip. The PM0 pin can remain open as it is Bit 15 (RSTDONE) in the STATUS1 register must be cancelled
held high, due to the internal pull-up resistor. This ensures that for the IRQ1 pin to return high. Wait until the IRQ1 pin goes low
ADE7854/ADE7858/ADE7868/ADE7878 always power up in before accessing the STATUS1 register to test the state of the
PSM0 (normal) mode. The time taken from the chip being RSTDONE bit. At this point, as a good programming practice,
powered up completely to the state where all functionality is cancel all other status flags in the STATUS1 and STATUS0 registers
enabled, is about 40 ms (see Figure 26). It is necessary to ensure by writing the corresponding bits with 1.
that the RESET pin is held high during the entire power-up
Initially, the DSP is in idle mode and, therefore, does not
procedure.
execute any instructions. This is the moment to initialize all
If PSM0 mode is the only desired power mode, the PM1 pin can registers in the ADE7854, ADE7858, ADE7868, or ADE7878.
be tied to ground externally. When the ADE7854/ADE7858/ See the Digital Signal Processor section for the proper procedure
ADE7868/ADE7878 enter PSM0 mode, the I2C port is the active to initialize all registers and start the metering.
serial port. To use the SPI port, toggle the SS/HSA pin three times
If the supply voltage, VDD, falls lower than 2 V ± 10%, the
from high to low.
ADE7854/ADE7858/ADE7868/ADE7878 enter an inactive
To lock I2C as the active serial port, set Bit 1 (I2C_LOCK) of the state, which means that no measurements or computations
CONFIG2 register to 1. From this moment, the device ignores are executed.
spurious toggling of the SS/HSA pin, and a switch to the SPI
port is no longer possible.
If SPI is the active serial port, any write to the CONFIG2 register
locks the port, and a switch to the I2C port is no longer possible.
To use the I2C port, the ADE7854/ADE7858/ADE7868/ADE7878
must be powered down or the device must be reset by setting
the RESET pin low. After the serial port is locked, the serial port
selection is maintained when the device changes from one
PSMx power mode to another.

HARDWARE RESET SOFTWARE RESET FUNCTIONALITY
The ADE7854/ADE7858/ADE7868/ADE7878 each has a RESET Bit 7 (SWRST) in the CONFIG register manages the software
pin. If the ADE7854, ADE7858, ADE7868, or ADE7878 is in reset functionality in PSM0 mode. The default value of this bit is 0.
PSM0 mode and the RESET pin is set low, then the ADE78xx If this bit is set to 1, then the ADE7854/ADE7858/ADE7868/
enters the hardware reset state. The ADE78xx must be in PSM0 ADE7878 enter the software reset state. In this state, almost all
mode for a hardware reset to be considered. Setting the RESET internal registers are set to their default values. In addition, the
pin low while the ADE78xx is in PSM1, PSM2, and PSM3 choice of which serial port, I2C or SPI, is in use remains unchanged
modes does not have any effect. if the lock-in procedure has been executed previously (see the
Serial Interfaces for details). The registers that maintain their
If the ADE7854, ADE7858, ADE7868, or ADE7878 is in PSM0
values despite the SWRST bit being set to 1 are the CONFIG2
mode and the RESET pin is toggled from high to low and then and LPOILVL registers. When the software reset ends, Bit 7
back to high after at least 10 µs, all the registers are set to their (SWRST) in the CONFIG register is cleared to 0, the IRQ1
default values, including the CONFIG2 and LPOILVL registers.
interrupt pin is set low, and Bit 15 (RSTDONE) in the STATUS1
The ADE78xx signals the end of the transition period by triggering
register is set to 1. This bit is 0 during the transition period and
the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the becomes 1 when the transition ends. The status bit is cleared and
STATUS1 register to 1. This bit is 0 during the transition period the IRQ1 pin is set back high by writing to the STATUS1 register
and becomes 1 when the transition ends. The status bit is cleared
with the corresponding bit set to 1.
and the IRQ1 pin is returned high by writing to the STATUS1
register with the corresponding bit set to 1. After a software reset ends, the DSP is in idle mode, which
means it does not execute any instruction. It is recommended
After a hardware reset, the DSP is in idle mode, which means it to initialize all the ADE7854/ADE7858/ADE7868/ADE7878
does not execute any instruction. registers and then enable the data memory RAM protection and
Because the I2C port is the default serial port of the ADE7854/ write 0x0001 into the run register to start the DSP (see the
ADE7858/ADE7868/ADE7878, it becomes active after a reset Digital Signal Processor section for details on data memory
state. If SPI is the port used by the external microprocessor, the RAM protection and the run register).
procedure to enable it must be repeated immediately after the Software reset functionality is not available in PSM1, PSM2, or
RESET pin is toggled back to high (see the Serial Interfaces PSM3 mode.
section for details).
At this point, it is recommended to initialize all of the ADE78xx
registers, enable data memory RAM protection, and then write
0x0001 into the run register to start the DSP. See the Digital
Signal Processor section for details on data memory RAM
protection and the run register.

THEORY OF OPERATION
ANALOG INPUTS Figure 29 shows how the gain selection from the gain register
works in both current and voltage channels.
The ADE7868/ADE7878 have seven analog inputs forming GAIN
current and voltage channels. The ADE7854/ADE7858 have six SELECTION
analog inputs, not offering the neutral current. The current IxP, VyP
channels consist of four pairs of fully differential voltage inputs: VIN K × VIN
IAP and IAN, IBP and IBN, ICP and ICN, and INP and INN.
IxN, VN
These vol-tage input pairs have a maximum differential signal of
08510-011
±0.5 V. In addition, the maximum signal level on analog inputs NOTES
1. x = A, B, C, N
for the IxP/IxN pair is ±0.5 V with respect to AGND. The y = A, B, C.
maximum common-mode signal allowed on the inputs is ±25 mV. Figure 29. PGA in Current and Voltage Channels
Figure 27 presents a schematic of the input for the current
channels and their relation to the maximum common-mode ANALOG-TO-DIGITAL CONVERSION
voltage. The ADE7868/ADE7878 have seven sigma-delta (Σ-Δ) analog-
DIFFERENTIAL INPUT to-digital converters (ADCs), and the ADE7854/ADE7858 have
V1 + V2 = 500mV MAX PEAK
COMMON MODE
six Σ-Δ ADCs. In PSM0 mode, all ADCs are active. In PSM1
V1 + V2
VCM = ±25mV MAX mode, only the ADCs that measure the Phase A, Phase B, and
+500mV IAP, IBP,
Phase C currents are active. The ADCs that measure the neutral
V1 ICP, OR INP current and the A, B, and C phase voltages are turned off. In
VCM PSM2 and PSM3 modes, the ADCs are powered down to
VCM V2 IAN, IBN, minimize power consumption.
08510-010
–500mV ICN, OR INN

For simplicity, the block diagram in Figure 30 shows a first-
Figure 27. Maximum Input Level, Current Channels, Gain = 1 order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
All inputs have a programmable gain amplifier (PGA) with a
CLKIN/16
possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and ANALOG
DIGITAL
LOW-PASS FILTER
IC inputs is set in Bits[2:0] (PGA1[2:0]) of the gain register. For INTEGRATOR
LATCHED
LOW-PASS
R FILTER
the ADE7868 and ADE7878 only, the gain of the IN input is set +
–
+ COMPARATOR
in Bits[5:3] (PGA2[2:0]) of the gain register; thus, a different gain C

VREF
– 24
from the IA, IB, or IC inputs is possible. See Table 44 for details
on the gain register.
08510-013
.....10100101.....
The voltage channel has three single-ended voltage inputs: VAP, 1-BIT DAC
VBP, and VCP. These single-ended voltage inputs have a maximum

Figure 30. First-Order Σ-∆ ADC
input voltage of ±0.5 V with respect to VN. In addition, the max-
imum signal level on analog inputs for VxP and VN is ±0.5 V A Σ-Δ modulator converts the input signal into a continuous
with respect to AGND. The maximum common-mode signal serial stream of 1s and 0s at a rate determined by the sampling
allowed on the inputs is ±25 mV. Figure 28 presents a schematic clock. In the ADE7854/ADE7858/ADE7868/ADE7878, the
of the voltage channels inputs and their relation to the maximum sampling clock is equal to 1.024 MHz (CLKIN/16). The 1-bit
common-mode voltage. DAC in the feedback loop is driven by the serial data stream.
DIFFERENTIAL INPUT The DAC output is subtracted from the input signal. If the loop
V1 + V2 = 500mV MAX PEAK gain is high enough, the average value of the DAC output (and,
COMMON MODE
V1
VCM = ±25mV MAX therefore, the bit stream) can approach that of the input signal
level. For any given input value in a single sampling interval, the
+500mV VAP, VBP,
V1 OR VCP data from the 1-bit ADC is virtually meaningless. Only when a
VCM large number of samples are averaged is a meaningful result
VN
obtained. This averaging is carried out in the second part of the
08510-012
VCM
–500mV ADC, the digital low-pass filter. By averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
Figure 28. Maximum Input Level, Voltage Channels, Gain = 1 data-words that are proportional to the input signal level.
All inputs have a programmable gain with a possible gain The Σ-Δ converter uses two techniques to achieve high resolu-
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6] tion from what is essentially a 1-bit conversion technique. The
(PGA3[2:0]) in the gain register (see Table 44). first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than
the bandwidth of interest. For example, the sampling rate in and prevent the distortion of the band of interest, a low-pass
the ADE7854/ADE7858/ADE7868/ADE7878 is 1.024 MHz, filer (LPF) must be introduced. For conventional current
and the bandwidth of interest is 40 Hz to 2 kHz. Oversampling sensors, it is recommended to use one RC filter with a corner
has the effect of spreading the quantization noise (noise due to frequency of 5 kHz for the attenuation to be sufficiently high at
sampling) over a wider bandwidth. With the noise spread more the sampling frequency of 1.024 MHz. The 20 dB per decade
thinly over a wider bandwidth, the quantization noise in the band attenuation of this filter is usually sufficient to eliminate the
of interest is lowered, as shown in Figure 31. However, oversam- effects of aliasing for conventional current sensors. However, for a
pling alone is not efficient enough to improve the signal-to-noise di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per
ratio (SNR) in the band of interest. For example, an oversampling decade gain. This neutralizes the 20 dB per decade attenuation
factor of 4 is required just to increase the SNR by a mere 6 dB produced by the LPF. Therefore, when using a di/dt sensor, take
(1 bit). To keep the oversampling ratio at a reasonable level, it is care to offset the 20 dB per decade gain. One simple approach is
possible to shape the quantization noise so that the majority of to cascade one additional RC filter, thereby producing a −40 dB
the noise lies at the higher frequencies. In the Σ-Δ modulator, per decade attenuation.
the noise is shaped by the integrator, which has a high-pass-type ALIASING EFFECTS
SAMPLING
response for the quantization noise. This is the second technique FREQUENCY
used to achieve high resolution. The result is that most of the

noise is at the higher frequencies where it can be removed by
the digital low-pass filter. This noise shaping is shown in Figure 31.
ANTIALIAS FILTER
(RC) 0 2 4 512 1024
DIGITAL FILTER
SIGNAL FREQUENCY (kHz)
08510-015
SHAPED NOISE
IMAGE
SAMPLING
FREQUENCIES
FREQUENCY
Figure 32. Aliasing Effects
NOISE
ADC Transfer Function
0 2 4 512 1024 All ADCs in the ADE7854/ADE7858/ADE7868/ADE7878 are
FREQUENCY (kHz)
designed to produce the same 24-bit signed output code for the
HIGH RESOLUTION same input signal level. With a full-scale input signal of 0.5 V
OUTPUT FROM
SIGNAL
DIGITAL LPF and an internal reference of 1.2 V, the ADC output code is nomi-
nally 5,928,256 (0x5A7540). The code from the ADC can vary
between 0x800000 (−8,388,608) and 0x7FFFFF (+8,388,607);
NOISE this is equivalent to an input signal level of ±0.707 V. However,
for specified performance, do not exceed the nominal range of
08510-014
0 2 4 512 1024 ±0.5 V; ADC performance is guaranteed only for input signals
FREQUENCY (kHz)
lower than ±0.5 V.
Figure 31. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator CURRENT CHANNEL ADC
Antialiasing Filter Figure 33 shows the ADC and signal processing path for
Figure 30 also shows an analog low-pass filter (RC) on the input Input IA of the current channels (it is the same for IB and IC).
to the ADC. This filter is placed outside the ADE7854/ADE7858/ The ADC outputs are signed twos complement 24-bit data-
ADE7868/ADE7878, and its role is to prevent aliasing. Aliasing words and are available at a rate of 8 kSPS (thousand samples
is an artifact of all sampled systems as shown in Figure 32. Aliasing per second). With the specified full-scale analog input signal
means that frequency components in the input signal to the of ±0.5 V, the ADC produces its maximum output code value.
ADC, which are higher than half the sampling rate of the ADC, Figure 33 shows a full-scale voltage signal applied to the differ-
appear in the sampled signal at a frequency below half the ential inputs (IAP and IAN). The ADC output swings between
sampling rate. Frequency components above half the sampling −5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540). The
frequency (also known as the Nyquist frequency, that is, 512 kHz) input, IN, corresponds to the neutral current of a 3-phase
are imaged or folded back down below 512 kHz. This happens system (available in the ADE7868 and ADE7878 only). If no
with all ADCs regardless of the architecture. In the example shown, neutral line is present, connect this input to AGND. The
only frequencies near the sampling frequency, that is, 1.024 MHz, datapath of the neutral current is similar to the path of the
move into the band of interest for metering, that is, 40 Hz to phase currents as shown in Figure 34.
2 kHz. To attenuate the high frequency (near 1.024 MHz) noise

ZX SIGNAL
ZX DETECTION DATA RANGE
LPF1
0x5A7540 =
CURRENT PEAK, +5,928,256
OVERCURRENT
DETECT
0V
DSP INTEN BIT CURRENT RMS (IRMS)
CONFIG[0] CALCULATION
PGA1 BITS
REFERENCE HPFDIS
GAIN[2:0] [23:0] IAWV WAVEFORM
DIGITAL AIGAIN[23:0] 0xA58AC0 =
×1, ×2, ×4, ×8, ×16 SAMPLE REGISTER
IAP INTEGRATOR –5,928,256
TOTAL/FUNDAMENTAL
VIN PGA1 ADC ACTIVE AND REACTIVE
HPF POWER CALCULATION
IAN
CURRENT CHANNE L
VIN CURRENT CHANNE L DATA RANGE AFTER
DATA RANGE INTEGRATION
+0.5V/GAIN 0x5A7540 = 0x5A7540 =
+5,928,256 +5,928,256
0V 0V 0V
08510-019
–0.5V/GAIN 0xA58AC0 = 0xA58AC0 =
–5,928,256 –5,928,256
ANALOG INPUT RANGE ADC OUTPUT RANGE
Figure 33. Current Channel Signal Path
DSP INTEN BIT

CONFIG[0]
PGA2 BITS HPFDIS
GAIN[5:3] REFERENCE [23:0]
NIGAIN[23:0] CURRENT RMS (IRMS)
×1, ×2, ×4, ×8, ×16 DIGITAL
INP CALCULATION
INTEGRATOR
INWV WAVEFORM
08510-120
VIN PGA2 ADC
HPF SAMPLE REGISTER
INN
Figure 34. Neutral Current Signal Path (ADE7868, ADE7878 Only)
Current Waveform Gain Registers most significant bits (MSBs) padded with 0s and sign extended
to 28 bits. See Figure 35 for details.
There is a multiplier in the signal path of each phase and
31 28 27 24 23 0
neutral current. The current waveform can be changed by
0000 24-BIT NUMBER
±100% by writing a corresponding twos complement number
to the 24-bit signed current waveform gain registers (AIGAIN,
08510-016
BITS[27:24] ARE BIT 23 IS A SIGN BIT
BIGAIN, CIGAIN, and NIGAIN). For example, if 0x400000 is EQUAL TO BIT 23
written to those registers, the ADC output is scaled up by 50%. Figure 35. 24-Bit xIGAIN Transmitted as 32-Bit Words
To scale the input by −50%, write 0xC00000 to the registers.
Equation 3 describes mathematically the function of the current Current Channel HPF
waveform gain registers. The ADC outputs can contain a dc offset. This offset can create
Current Waveform = errors in power and rms calculations. High-pass filters (HPFs)
are placed in the signal path of the phase and neutral currents
 Content of Current Gain Register 
ADC Output  1   (3) and of the phase voltages. If enabled, the HPF eliminates any dc
 223  offset on the current channel. All filters are implemented in the
Changing the content of the AIGAIN, BIGAIN, CIGAIN, or DSP and, by default, they are all enabled: the 24-bit HPFDIS
INGAIN registers affects all calculations based on its current; register is cleared to 0x00000000. All filters are disabled by
that is, it affects the corresponding phase active/reactive/ setting HPFDIS to any nonzero value.
apparent energy and current rms calculation. In addition, As stated in the Current Waveform Gain Registers section, the
waveform samples scale accordingly. serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
Note that the serial ports of the ADE7854, ADE7858, ADE7868, The HPFDIS register is accessed as a 32-bit register with eight
and/or ADE7878 work on 32-, 16-, or 8-bit words, and the DSP MSBs padded with 0s. See Figure 36 for details.
works on 28 bits. The 24-bit AIGAIN, BIGAIN, CIGAIN, and 31 24 23 0
08510-017
NIGAIN registers are accessed as 32-bit registers with the four 0000 0000 24-BIT NUMBER
Figure 36. 24-Bit HPFDIS Register Transmitted as 32-Bit Word

Current Channel Sampling loop generate an electromotive force (EMF) between the two
The waveform samples of the current channel are taken at the ends of the loop. The EMF is a voltage signal that is propor-
output of HPF and stored in the 24-bit signed registers, IAWV, tional to the di/dt of the current. The voltage output from the
IBWV, ICWV, and INWV (ADE7868 and ADE7878 only) at a di/dt current sensor is determined by the mutual inductance
rate of 8 kSPS. All power and rms calculations remain uninter- between the current carrying conductor and the di/dt sensor.
rupted during this process. Bit 17 (DREADY) in the STATUS0 Due to the di/dt sensor, the current signal needs to be filtered
register is set when the IAWV, IBWV, ICWV, and INWV registers before it can be used for power measurement. On each phase and
are available to be read using the I2C or SPI serial port. Setting neutral current datapath, there is a built-in digital integrator to
Bit 17 (DREADY) in the MASK0 register enables an interrupt recover the current signal from the di/dt sensor. The digital inte-
to be set when the DREADY flag is set. See the Digital Signal grator is disabled by default when the ADE78xx is powered up
Processor section for more details on Bit DREADY. and after a reset. Setting Bit 0 (INTEN) of the CONFIG register
As stated in the Current Waveform Gain Registers section, the turns on the integrator. Figure 39 and Figure 40 show the
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words. magnitude and phase response of the digital integrator.
When the IAWV, IBWV, ICWV, and INWV 24-bit signed Note that the integrator has a −20 dB/dec attenuation and
registers are read from the ADE78xx (INWV is available on approximately −90° phase shift. When combined with a di/dt
ADE7868/ADE7878 only), they are transmitted sign extended sensor, the resulting magnitude and phase response should be a
to 32 bits. See Figure 37 for details. flat gain over the frequency band of interest. However, the di/dt
31 24 23 22 0 sensor has a 20 dB/dec gain associated with it and generates sig-
24-BIT SIGNED NUMBER nificant high frequency noise. An antialiasing filter of at least
the second order is needed to avoid noise aliasing back in the
08510-018
BITS[31:24] ARE BIT 23 IS A SIGN BIT band of interest when the ADC is sampling (see the Antialiasing
EQUAL TO BIT 23
Filter section).
Figure 37. 24-Bit IxWV Register Transmitted as 32-Bit Signed Word 50
MAGNITUDE (dB)
The ADE7854/ADE7858/ADE7868/ADE7878 devices each

contain a high speed data capture (HSDC) port that is specially 0
designed to provide fast access to the waveform sample registers.

See the HSDC Interface section for more details. –50
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR 0.01 0.1 1 10 100 1000
FREQUENCY (Hz)
The di/dt sensor detects changes in the magnetic field caused by 0
the ac current. Figure 38 shows the principle of a di/dt current
PHASE (Degrees)
sensor.
–50
MAGNETIC FIELD CREATED BY CURRENT

(DIRECTLY PROPORTIONAL TO CURRENT) –100
08510-116
0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
Figure 39. Combined Gain and Phase Response of the

+ EMF (ELECTROMOTIVE FORCE)
Digital Integrator
– INDUCED BY CHANGES IN
The DICOEFF 24-bit signed register is used in the digital
08510-020
MAGNETIC FLUX DENSITY (di/dt)

integrator algorithm. At power-up or after a reset, its value is
Figure 38. Principle of a di/dt Current Sensor 0x000000. Before turning on the integrator, this register must be
The flux density of a magnetic field induced by a current is initialized with 0xFFF8000. DICOEFF is not used when the
directly proportional to the magnitude of the current. The integrator is turned off and can remain at 0x000000 in that case.
changes in the magnetic flux density passing through a conductor

–15
32-bit register with four MSBs padded with 0s and sign
MAGNITUDE (dB)
–20
extended to 28 bits, which practically means it is transmitted
equal to 0xFFF8000.
–25
When the digital integrator is switched off, the ADE7854/
–30 ADE7858/ ADE7868/ADE7878 can be used directly with a
30 35 40 45 50 55 60 65 70
conventional current sensor, such as a current transformer (CT).
FREQUENCY (Hz)
–89.96
VOLTAGE CHANNEL ADC
PHASE (Degrees)
–89.97 Figure 41 shows the ADC and signal processing chain for
Input VA in the voltage channel. The VB and VC channels
–89.98 have similar processing chains. The ADC outputs are signed
twos complement 24-bit words and are available at a rate of
–89.99
8 kSPS. With the specified full-scale analog input signal of
08510-101
30 35 40 45 50 55 60 65 70
FREQUENCY (Hz)
±0.5 V, the ADC produces its maximum output code value.
Figure 40. Combined Gain and Phase Response of the
Digital Integrator (40 Hz to 70 Hz)
Figure 41 shows a full-scale voltage signal being applied to the
differential inputs (VA and VN). The ADC output swings
As stated in the Current Waveform Gain Registers section, the between −5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540).
serial ports of the ADE7854/ADE7858/ADE7868/ADE7878 work
on 32-, 16-, or 8-bit words. Similar to the registers shown in
Figure 35, the DICOEFF 24-bit signed register is accessed as a
VOLTAGE PEAK,
OVERVOLTAGE,
SAG DETECT
DSP CURRENT RMS (VRMS)

CALCULATION
PGA3 BITS
REFERENCE HPFDIS
GAIN[8:6] [23:0] VAWV WAVEFORM
×1, ×2, ×4, ×8, ×16 AVGAIN[23:0]
SAMPLE REGISTER
VAP
TOTAL/FUNDAMENTAL
VIN PGA3 ADC
HPF ACTIVE AND REACTIVE
POWER CALCULATION
VN
VIN VOLTAGE CHANNEL ZX DETECTION

DATA RANGE LPF1
+0.5V/GAIN 0x5A7540 =
+5,928,256
ZX SIGNAL
DATA RANGE
0V 0V
0x5A7540 =
+5,928,256
–0.5V/GAIN 0xA58AC0 =
–5,928,256 0V
ANALOG INPUT RANGE ANALOG OUTPUT RANGE
08510-025
0xA58AC0 =
–5,928,256
Figure 41. Voltage Channel Datapath

Voltage Waveform Gain Registers CHANGING PHASE VOLTAGE DATAPATH
There is a multiplier in the signal path of each phase voltage. The ADE7854/ADE7858/ADE7868/ADE7878 can direct one
The voltage waveform can be changed by ±100% by writing phase voltage input to the computational datapath of another
a corresponding twos complement number to the 24-bit signed phase. For example, Phase A voltage can be introduced in the
voltage waveform gain registers (AVGAIN, BVGAIN, and Phase B computational datapath, which means all powers
CVGAIN). For example, if 0x400000 is written to those registers, computed by the ADE78xx in Phase B are based on Phase A
the ADC output is scaled up by 50%. To scale the input by −50%, voltage and Phase B current.
write 0xC00000 to the registers. Equation 4 describes mathe-
Bits[9:8] (VTOIA[1:0]) of the CONFIG register manage what
matically the function of the current waveform gain registers.
phase voltage is directed to Phase A computational data path. If
Voltage Waveform = VTOIA[1:0] = 00 (default value), the Phase A voltage is directed
 Content of Voltage Gain Register  to the Phase A computational data path. If VTOIA[1:0] = 01,
ADC Output × 1 +  (4)
 2 23  the Phase B voltage is directed to the Phase A computational
data path. If VTOIA[1:0] = 10, the Phase C voltage is directed
Changing the content of the AVGAIN, BVGAIN, and CVGAIN to the Phase A computational data path. If VTOIA[1:0] = 11,
registers affects all calculations based on its voltage; that is, it the ADE7854/ADE7858/ADE7868/ADE7878 behaves as if
affects the corresponding phase active/reactive/apparent energy VTOIA[1:0] = 00.
and voltage rms calculation. In addition, waveform samples are
scaled accordingly. Bits[11:10] (VTOIB[1:0]) of the CONFIG register manage
what phase voltage is directed to the Phase B computational
As stated in the Current Waveform Gain Registers section, the data path. If VTOIB[1:0] = 00 (default value), the Phase B
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words, voltage is directed to the Phase B computational data path.
and the DSP works on 28 bits. As presented in Figure 35, the If VTOIB[1:0] = 01, the Phase C voltage is directed to the
AVGAIN, BVGAIN, and CVGAIN registers are accessed as Phase B computational data path. If VTOIB[1:0] = 10, the Phase A
32-bit registers with four MSBs padded with 0s and sign voltage is directed to the Phase B computational data path. If
extended to 28 bits. VTOIB[1:0] = 11, the ADE7854/ADE7858/ADE7868/ADE7878
Voltage Channel HPF behaves as if VTOIB[1:0] = 00.
As explained in the Current Channel HPF section, the ADC Bits[13:12] (VTOIC[1:0]) of the CONFIG register manage what
outputs can contain a dc offset that can create errors in power phase voltage is directed to the Phase C computational data
and rms calculations. HPFs are placed in the signal path of the path. If VTOIC[1:0] = 00 (default value), the Phase C voltage is
phase voltages, similar to the ones in the current channels. The directed to Phase C computational data path, if VTOIC[1:0] =
HPFDIS register can enable or disable the filters. See the 01, the Phase A voltage is directed to the Phase C computational
Current Channel HPF section for more details. data path. If VTOIC[1:0] = 10, the Phase B voltage is directed to
Voltage Channel Sampling the Phase C computational data path. If VTOIC[1:0] = 11, the
ADE7854/ADE7858/ADE7868/ADE7878 behaves as if
The waveform samples of the voltage channel are taken at the
VTOIC[1:0] = 00.
output of HPF and stored into VAWV, VBWV, and VCWV
24-bit signed registers at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the VAWV,
VBWV, and VCWV registers are available to be read using the
I2C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
register enables an interrupt to be set when the DREADY flag is
set. See the Digital Signal Processor section for more details on
Bit DREADY.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
Similar to registers presented in Figure 37, the VAWV, VBWV,
and VCWV 24-bit signed registers are transmitted sign
extended to 32 bits.
The ADE7854/ADE7858/ADE7868/ADE7878 each contain an
HSDC port especially designed to provide fast access to the
waveform sample registers. See the HSDC Interface section for
more details.

IA DSP
IA, IB, IC, REFERENCE HPFDIS xIGAIN[23:0] OR
PHASE A
OR [23:0] xVGAIN[23:0]
COMPUTATIONAL
APHCAL VA, VB, VC
DATAPATH ZX
VTOIB[1:0] = 10, DETECTION
VA PHASE A VOLTAGE PGA ADC
HPF LPF1
DIRECTED
IB TO PHASE B
39.6° OR 2.2ms @ 50Hz
PHASE B 1
COMPUTATIONAL 0.855
BPHCAL DATAPATH
VTOIC[1:0] = 10, ZX
VB 0V
PHASE B VOLTAGE ZX ZX ZX
DIRECTED
08510-027
IC TO PHASE C IA, IB, IC,
LPF1 OUTPUT
OR VA, VB, VC
PHASE C
COMPUTATIONAL Figure 43. Zero-Crossing Detection on Voltage and Current Channels
CPHCAL DATAPATH
VC
VTOIA[1:0] = 10, To provide further protection from noise, input signals to the
PHASE C VOLTAGE
08510-026
DIRECTED voltage channel with amplitude lower than 10% of full scale do
TO PHASE A
not generate zero-crossing events at all. The Current Channel ZX
Figure 42. Phase Voltages Used in Different Datapaths detection circuit is active for all input signals independent of their
Figure 42 presents the case in which Phase A voltage is used in amplitudes.
the Phase B datapath, Phase B voltage is used in the Phase C The ADE7854/ADE7858/ADE7868/ADE7878 contain six zero-
datapath, and Phase C voltage is used in the Phase A datapath. crossing detection circuits, one for each phase voltage and
POWER QUALITY MEASUREMENTS current channel. Each circuit drives one flag in the STATUS1
register. If a circuit placed in the Phase A voltage channel
Zero-Crossing Detection
detects one zero-crossing event, Bit 9 (ZXVA) in the STATUS1
The ADE7854/ADE7858/ADE7868/ADE7878 have a zero- register is set to 1.
crossing (ZX) detection circuit on the phase current and voltage
channels. The neutral current datapath does not contain a zero- Similarly, the Phase B voltage circuit drives Bit 10 (ZXVB), the
crossing detection circuit. Zero-crossing events are used as a Phase C voltage circuit drives Bit 11 (ZXVC), and circuits placed
time base for various power quality measurements and in the in the current channel drive Bit 12 (ZXIA), Bit 13 (ZXIB), and
calibration process. Bit 14 (ZXIC) in the STATUS1 register. If a ZX detection bit is
set in the MASK1 register, the IRQ1 interrupt pin is driven low
The output of LPF1 is used to generate zero crossing events.
and the corresponding status flag is set to 1. The status bit is
The low-pass filter is intended to eliminate all harmonics of
cleared and the IRQ1 pin is set to high by writing to the STATUS1
50 Hz and 60 Hz systems, and to help identify the zero-crossing
register with the status bit set to 1.
events on the fundamental components of both current and
voltage channels. Zero-Crossing Timeout
The digital filter has a pole at 80 Hz and is clocked at 256 kHz. Every zero-crossing detection circuit has an associated timeout
As a result, there is a phase lag between the analog input signal register. This register is loaded with the value written into the
(one of IA, IB, IC, VA, VB, and VC) and the output of LPF1. 16-bit ZXTOUT register and is decremented (1 LSB) every
The error in ZX detection is 0.0703° for 50 Hz systems (0.0843° 62.5 μs (16 kHz clock). The register is reset to the ZXTOUT
for 60 Hz systems). The phase lag response of LPF1 results in a value every time a zero crossing is detected. The default value of
time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between this register is 0xFFFF. If the timeout register decrements to 0
its input and output. The overall delay between the zero crossing before a zero crossing is detected, one of Bits[8:3] of the
on the analog inputs and ZX detection obtained after LPF1 is STATUS1 register is set to 1. Bit 3 (ZXTOVA), Bit 4 (ZXTOVB),
about 39.6° or 2.2 ms (at 50 Hz). The ADC and HPF introduce and Bit 5 (ZXTOVC) in the STATUS1 register refer to Phase A,
the additional delay. The LPF1 cannot be disabled to assure a Phase B, and Phase C of the voltage channel; Bit 6 (ZXTOIA),
good resolution of the ZX detection. Figure 43 shows how the Bit 7 (ZXTOIB), and Bit 8 (ZXTOIC) in the STATUS1 register
zero-crossing signal is detected. refer to Phase A, Phase B, and Phase C of the current channel.
If a ZXTOIx or ZXTOVx bit is set in the MASK1 register, the
IRQ1 interrupt pin is driven low when the corresponding status bit
is set to 1. The status bit is cleared and the IRQ1 pin is returned to
high by writing to the STATUS1 register with the status bit set to 1.
The resolution of the ZXOUT register is 62.5 μs (16 kHz clock)
per LSB. Thus, the maximum timeout period for an interrupt is
4.096 sec: 216/16 kHz.

Figure 44 shows the mechanism of the zero-crossing timeout PHASE A PHASE C PHASE B
detection when the voltage or the current signal stays at a fixed
dc level for more than 62.5 µs × ZXTOUT µs.
A, B, C PHASE
VOLTAGES AFTER
16-BIT INTERNAL LPF1
REGISTER VALUE
ZXTOUT
ZX A ZX C ZX B
BIT 19 (SEQERR) IN
STATUS1 REGISTER
VOLTAGE
OR
0V
CURRENT IRQ1
SIGNAL
STATUS1[19] SET TO 1 STATUS1[19] CANCELLED

BY A WRITE TO THE
08510-029
STATUS1 REGISTER WITH
ZXZOxy FLAG IN SEQERR BIT SET
STATUS1[31:0], x = V, A
y = A, B, C Figure 45. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by
08510-028
Phase C Voltage
IRQ1 INTERRUPT PIN Once a phase sequence error has been detected, the time
Figure 44. Zero-Crossing Timeout Detection
measurement between various phase voltages (see the Time
Interval Between Phases section) can help to identify which
phase voltage should be considered with another phase current
Phase Sequence Detection in the computational datapath. Bits[9:8] (VTOIA[1:0]), Bits[11:10]
The ADE7854/ADE7858/ADE7868/ADE7878 have on-chip (VTOIB[1:0]), and Bits[13:12] (VTOIC[1:0]) in the CONFIG
phase sequence error detection circuits. This detection works register can be used to direct one phase voltage to the datapath
on phase voltages and considers only the zero crossings of another phase. See the Changing Phase Voltage Datapath
determined by their negative-to-positive transitions. The regular section for details.
succession of these zero-crossing events is Phase A followed by Time Interval Between Phases
Phase B followed by Phase C (see Figure 46). If the sequence of The ADE7854/ADE7858/ADE7868/ADE7878 have the capa-
zero-crossing events is, instead, Phase A followed by Phase C bility to measure the time delay between phase voltages, between
followed by Phase B, then Bit 19 (SEQERR) in the STATUS1 phase currents, or between voltages and currents of the same
register is set. phase. The negative-to-positive transitions identified by the zero-
If Bit 19 (SEQERR) in the MASK1 register is set to 1 and a crossing detection circuit are used as start and stop measuring
phase sequence error event is triggered, the IRQ1 interrupt pin points. Only one set of such measurements is available at one time,
is driven low. The status bit is cleared and the IRQ1 pin is set based on Bits[10:9] (ANGLESEL[1:0]) in the COMPMODE
high by writing to the STATUS1 register with the Status Bit 19 register.
(SEQERR) set to 1.
PHASE A PHASE B PHASE C
The phase sequence error detection circuit is functional only
when the ADE78xx is connected in a 3-phase, 4-wire, three voltage
sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE
register, set to 00). In all other configurations, only two voltage
sensors are used; therefore, it is not recommended to use the
08510-030
detection circuit. In these cases, use the time intervals between ZX A ZX B ZX C
phase voltages to analyze the phase sequence (see the Time Figure 46. Regular Succession of Phase A, Phase B, and Phase C
Interval Between Phases section for details).
When the ANGLESEL[1:0] bits are set to 00, the default value,
Figure 45 presents the case in which Phase A voltage is not the delays between voltages and currents on the same phase are
followed by Phase B voltage but by Phase C voltage. Every time measured. The delay between Phase A voltage and Phase A
a negative-to-positive zero crossing occurs, Bit 19 (SEQERR) in current is stored in the 16-bit unsigned ANGLE0 register (see
the STATUS1 register is set to 1 because such zero crossings on Figure 47 for details). In a similar way, the delays between voltages
Phase C, Phase B, or Phase A cannot come after zero crossings and currents on Phase B and Phase C are stored in the ANGLE1
from Phase A, Phase C, or respectively, Phase B zero crossings. and ANGLE2 registers, respectively.

PHASE A LPF1 filter (see Figure 43), a settling time of 30 ms to 40 ms is
VOLTAGE
PHASE A
CURRENT
associated with this filter before the measurement is stable.
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period register
08510-031
ANGLE0
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
Figure 47. Delay Between Phase A Voltage and Phase A Current Is for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
Stored in the ANGLE0 Register length of the register enables the measurement of line frequencies
When the ANGLESEL[1:0] bits are set to 01, the delays between as low as 3.9 Hz (256 kHz/216). The period register is stable at
phase voltages are measured. The delay between Phase A voltage ±1 LSB when the line is established and the measurement does
and Phase C voltage is stored into the ANGLE0 register. The not change.
delay between Phase B voltage and Phase C voltage is stored in The following expressions can be used to compute the line
the ANGLE1 register, and the delay between Phase A voltage period and frequency using the period register:
and Phase B voltage is stored in the ANGLE2 register (see PERIOD[15:0] + 1
Figure 48 for details). TL = [sec] (6)
256E3
When the ANGLESEL[1:0] bits are set to 10, the delays between
256E3
phase currents are measured. Similar to delays between phase fL = [Hz] (7)
PERIOD[15:0] + 1
voltages, the delay between Phase A and Phase C currents is stored
into the ANGLE0 register, the delay between Phase B and Phase C Phase Voltage Sag Detection
currents is stored in the ANGLE1 register, and the delay between The ADE7854/ADE7858/ADE7868/ADE7878 can be pro-
Phase A and Phase B currents is stored into the ANGLE2 grammed to detect when the absolute value of any phase voltage
register (see Figure 48 for details). drops below a certain peak value for a number of half-line cycles.
The phase where this event takes place is identified in Bits[14:12]
PHASE A PHASE B PHASE C
(VSPHASE[x]) of the PHSTATUS register. This condition is
illustrated in Figure 49.
PHASE B VOLTAGE
FULL SCALE
SAGLVL[23:0]
ANGLE2 ANGLE1
08510-032
ANGLE0
Figure 48. Delays Between Phase Voltages (Currents) SAGCYC[7:0] = 0x4
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit PHASE A VOLTAGE
unsigned registers with 1 LSB corresponding to 3.90625 μs FULL SCALE
(256 kHz clock), which means a resolution of 0.0703° (360° × SAGLVL[23:0]
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/

256 kHz) for 60 Hz systems. The delays between phase voltages STATUS1[16] AND
PHSTATUS[12]
or phase currents are used to characterize how balanced the CANCELLED BY A
WRITE TO
load is. The delays between phase voltages and currents are SAGCYC[7:0] = 0x4
STATUS1[31:0]
WITH SAG BIT SET
used to compute the power factor on each phase as shown in
the following Equation 5: BIT 16 (SAG) IN
STATUS1[31:0]
 360  × f LINE 
cosφx = cos  ANGLEx ×  (5)
 256 kHz  IRQ1 PIN
where fLINE = 50 Hz or 60 Hz. STATUS[16] AND

PHSTATUS[13]
Period Measurement VSPHASE[0] =
SET TO 1
PHSTATUS[12]
The ADE7854/ADE7858/ADE7868/ADE7878 provide the
period measurement of the line in the voltage channel. Bits[1:0]
(PERSEL[1:0]) in the MMODE register select the phase voltage
08510-033
VSPHASE[1] =
used for this measurement. The period register is a 16-bit PHSTATUS[13]
unsigned register and updates every line period. Because of the Figure 49. SAG Detection

Figure 49 shows Phase A voltage falling below a threshold that the SAG event is triggered continuously. Writing 0x00 or 0x01
is set in the SAG level register (SAGLVL) for four half-line cycles puts the SAG detection level at 0, therefore, the SAG event is
(SAGCYC = 4). When Bit 16 (SAG) in the STATUS1 register is set never triggered.
to 1 to indicate the condition, Bit VSPHASE[0] in the PHSTATUS As stated in the Current Waveform Gain Registers section, the
register is also set to 1 because the event happened on Phase A serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
Bit 16 (SAG) in the STATUS1 register. All Bits[14:12] (VSPHASE[2], Similar to the register presented in Figure 36, the SAGLVL
VSPHASE[1], and VSPHASE[0]) of the PHSTATUS register (not register is accessed as a 32-bit register with eight MSBs padded
just the VSPHASE[0] bit) are erased by writing the STATUS1 with 0s.
register with the SAG bit set to 1.
Peak Detection
The SAGCYC register represents the number of half-line cycles
The ADE7854/ADE7858/ADE7868/ADE7878 record the
the phase voltage must remain below the level indicated in the
maximum absolute values reached by the voltage and current
SAGLVL register to trigger a SAG condition; 0 is not a valid
channels over a certain number of half-line cycles and stores
number for SAGCYC. For example, when the SAG cycle
them into the less significant 24 bits of the VPEAK and IPEAK
(SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1
32-bit registers.
register is set at the end of the seventh half line cycle for which
the line voltage falls below the threshold. If Bit 16 (SAG) in The PEAKCYC register contains the number of half-line cycles
MASK1 is set, the IRQ1 interrupt pin is driven low in case of used as a time base for the measurement. The circuit uses the
a SAG event in the same moment the Status Bit 16 (SAG) in zero-crossing points identified by the zero-crossing detection
STATUS1 register is set to 1. The SAG status bit in the STATUS1 circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select
register and all Bits[14:12] (VSPHASE[2], VSPHASE[1], and the phases upon which the peak measurement is performed. Bit 2
VSPHASE[0]]) of the PHSTATUS register are cleared, and the selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C.
IRQ1 pin is returned to high by writing to the STATUS1 Selecting more than one phase to monitor the peak values
register with the status bit set to 1. decreases proportionally the measurement period indicated in
the PEAKCYC register because zero crossings from more
When the Phase B voltage falls below the indicated threshold
phases are involved in the process. When a new peak value is
into the SAGLVL register for two line cycles, Bit VSPHASE[1]
determined, one of Bits[26:24] (IPPHASE[2:0] or VPPHASE[2:0])
in the PHSTATUS register is set to 1, and Bit VSPHASE[0] is
in the IPEAK and VPEAK registers is set to 1, identifying the
cleared to 0. Simultaneously, Bit 16 (SAG) in the STATUS1 register
phase that triggered the peak detection event. For example, if a
is set to 1 to indicate the condition.
peak value has been identified on Phase A current, Bit 24
Note that the internal zero-crossing counter is always active. By (IPPHASE[0]) in the IPEAK register is set to 1. If next time a
setting the SAGLVL register, the first SAG detection result is, new peak value is measured on Phase B, Bit 24 (IPPHASE[0])
therefore, not executed across a full SAGCYC period. Writing to of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])
the SAGCYC register when the SAGLVL register is already initia- of the IPEAK register is set to 1. Figure 50 shows the composition
lized resets the zero-crossing counter, thus ensuring that the first of the IPEAK and VPEAK registers.
SAG detection result is obtained across a full SAGCYC period. IPPHASE/VPPHASE BITS
The recommended procedure to manage SAG events is the 31 27 26 25 24 23 0
following: 00000 24 BIT UNSIGNED NUMBER
1. Enable SAG interrupts in the MASK1 register by setting PEAK DETECTED

ON PHASE C
PEAK DETECTED
ON PHASE A
Bit 16 (SAG) to 1.
08510-034
PEAK DETECTED
2. When a SAG event happens, the IRQ1 interrupt pin goes ON PHASE B
low and Bit 16 (SAG) in the STATUS1 is set to 1. Figure 50. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
3. The STATUS1 register is read with Bit 16 (SAG) set to 1.
4. The PHSTATUS register is read, identifying on which
phase or phases a SAG event happened.
5. The STATUS1 register is written with Bit 16 (SAG) set to 1.
Immediately, the SAG bit and all Bits[14:12] (VSPHASE[2],
VSPHASE[1], and VSPHASE[0]) of the PHSTATUS register
are erased.
SAG Level Set
The content of the SAGLVL[23:0] SAG level register is compared
to the absolute value of the output from HPF. Writing 5,928,256
(0x5A7540) to the SAGLVL register, puts the SAG detection
level at full scale (see the Voltage Channel ADC section), thus;
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST thereby ensuring that the first peak detection result is obtained
PEAKCYC PERIOD
END OF FIRST
across a full PEAKCYC period.
PEAKCYC = 16 PERIOD
Overvoltage and Overcurrent Detection
END OF SECOND
PEAKCYC = 16 PERIOD
The ADE7854/ADE7858/ADE7868/ADE7878 detect when the
instantaneous absolute value measured on the voltage and
PHASE A
CURRENT
current channels becomes greater than the thresholds set in the
OVLVL and OILVL 24-bit unsigned registers. If Bit 18 (OV) in
the MASK1 register is set, the IRQ1 interrupt pin is driven low
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
in case of an overvoltage event. There are two status flags set
BIT 24
OF IPEAK
PEAKCYC PERIOD
when the IRQ1 interrupt pin is driven low: Bit 18 (OV) in the
STATUS1 register and one of Bits[11:9] (OVPHASE[2:0]) in the
PHASE B
PHSTATUS register to identify the phase that generated the
CURRENT
overvoltage. The Status Bit 18 (OV) in the STATUS1 register
and all Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS register
BIT 25 OF IPEAK are cleared, and the IRQ1 pin is set to high by writing to the
PEAK VALUE WRITTEN INTO SET TO 1 AT THE
IPEAK AT THE END OF SECOND END OF SECOND STATUS1 register with the status bit set to 1. Figure 52 presents
08510-035
PEAKCYC PERIOD PEAKCYC PERIOD

BIT 25
OF IPEAK overvoltage detection in Phase A voltage.
Figure 51. Peak Level Detection PHASE A OVERVOLTAGE
VOLTAGE CHANNEL DETECTED
Figure 51 shows how the ADE78xx records the peak value on the
current channel when measurements on Phase A and Phase B are
OVLVL[23:0]
enabled (Bit PEAKSEL[2:0] in the MMODE register are 011).
PEAKCYC is set to 16, meaning that the peak measurement
cycle is four line periods. The maximum absolute value of Phase A
is the greatest during the first four line periods (PEAKCYC = 16),
so the maximum absolute value is written into the less signifi-
cant 24 bits of the IPEAK register, and Bit 24 (IPPHASE[0]) of
the IPEAK register is set to 1 at the end of the period. This bit
remains at 1 for the duration of the second PEAKCYC period of
four line cycles. The maximum absolute value of Phase B is the BIT 18 (OV) OF
STATUS1
greatest during the second PEAKCYC period; therefore, the
maximum absolute value is written into the less significant STATUS1[18] AND
PHSTATUS[9]
24 bits of the IPEAK register, and Bit 25 (IPPHASE[1]) in the CANCELLED BY A
IPEAK register is set to 1 at the end of the period. WRITE OF STATUS1
WITH OV BIT SET.
At the end of the peak detection period in the current channel, BIT 9 (OVPHASE)
OF PHSTATUS
08510-036
Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)
in the MASK1 register is set, the IRQ1 interrupt pin is driven low Figure 52. Overvoltage Detection
at the end of PEAKCYC period and Status Bit 23 (PKI) in the
STATUS1 register is set to 1. In a similar way, at the end of the Whenever the absolute instantaneous value of the voltage goes
peak detection period in the voltage channel, Bit 24 (PKV) in the above the threshold from the OVLVL register, Bit 18 (OV) in
STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1 the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
register are set to 1. Bit 18 (OV) of the STATUS1 register and
register is set, the IRQ1 interrupt pin is driven low at the end of
Bit 9 (OVPHASE[0]) in the PHSTATUS register are cancelled
PEAKCYC period and Status Bit 24 (PKV) in the STATUS1
when the STATUS1 register is written with Bit 18 (OV) set to 1.
register is set to 1. To find the phase that triggered the interrupt,
one of either the IPEAK or VPEAK registers is read immediately The recommended procedure to manage overvoltage events is
after reading the STATUS1 register. Next, the status bits are the following:
cleared, and the IRQ1 pin is set to high by writing to the 1. Enable OV interrupts in the MASK1 register by setting
STATUS1 register with the status bit set to 1. Bit 18 (OV) to 1.
Note that the internal zero-crossing counter is always active. By 2. When an overvoltage event happens, the IRQ1 interrupt
setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the pin goes low.
first peak detection result is, therefore, not executed across a full 3. The STATUS1 register is read with Bit 18 (OV) set to 1.
PEAKCYC period. Writing to the PEAKCYC register when the 4. The PHSTATUS register is read, identifying on which
PEAKSEL[2:0] bits are set resets the zero-crossing counter, phase or phases an overvoltage event happened.

5. The STATUS1 register is written with Bit 18 (OV) set to 1. ADCMAX = 5,928,256, the ADC output when the input is at full
In this moment, Bit OV is erased and also all Bits[11:9] scale.
(OVPHASE[2:0]) of the PHSTATUS register. IFS is the full-scale ADC phase current.
In case of an overcurrent event, if Bit 17 (OI) in the MASK1 The ADE7868/ADE7878 compute the difference between the
register is set, the IRQ1 interrupt pin is driven low. Immediately, absolute values of ISUM and the neutral current from the
Bit 17 (OI) in the STATUS1 register and one of Bits[5:3] INWV register, take its absolute value and compare it against
(OIPHASE[2:0]) in the PHSTATUS register, which identify the ISUMLVL threshold. If ISUM − INWV ≤ ISUMLVL ,
the phase that generated the interrupt, are set. To find the then it is assumed that the neutral current is equal to the sum
phase that triggered the interrupt, the PHSTATUS register of the phase currents, and the system functions correctly. If
is read immediately after reading the STATUS1 register. Next, ISUM − INWV > ISUMLVL , then a tamper situation may
Status Bit 17 (OI) in the STATUS1 register and Bits[5:3]
have occurred, and Bit 20 (MISMTCH) in the STATUS1 register
(OIPHASE[2:0]) in the PHSTATUS register are cleared and the
is set to 1. An interrupt attached to the flag can be enabled by
IRQ1 pin is set to high by writing to the STATUS1 register with
setting Bit 20 (MISMTCH) in the MASK1 register. If enabled,
the status bit set to 1. The process is similar with overvoltage
the IRQ1 pin is set low when Status Bit MISMTCH is set to 1.
detection.
The status bit is cleared and the IRQ1 pin is set back to high by
Overvoltage and Overcurrent Level Set writing to the STATUS1 register with Bit 20 (MISMTCH) set to 1.
The content of the overvoltage (OVLVL), and overcurrent,
If ISUM − INWV ≤ ISUMLVL , then MISMTCH = 0
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of If ISUM − INWV > ISUMLVL , then MISMTCH = 1
these registers is the maximum value of the HPF outputs:
+5,928,256 (0x5A7540). When the OVLVL or OILVL register is ISUMLVL, the positive threshold used in the process, is a 24-bit
equal to this value, the overvoltage or overcurrent conditions signed register. Because it is used in a comparison with an
are never detected. Writing 0x0 to these registers signifies the absolute value, always set ISUMLVL as a positive number,
overvoltage or overcurrent conditions are continuously detected, somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses
and the corresponding interrupts are permanently triggered. the same scale of the current ADCs outputs, so writing
+5,928,256 (0x5A7540) to the ISUMLVL register puts the
mismatch detection level at full scale; see the Current Channel
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
ADC section for details. Writing 0x000000, the default value, or
Similar to the register presented in Figure 36, OILVL and
a negative value, signifies the MISMTCH event is always triggered.
OVLVL registers are accessed as 32-bit registers with the eight
The right value for the application should be written into the
MSBs padded with 0s.
ISUMLVL register after power-up or after a hardware/software
Neutral Current Mismatch—ADE7868, ADE7878 reset to avoid continuously triggering MISMTCH events.
Neutral current mismatch is available in the ADE7868 and As stated in the Current Waveform Gain Registers section, the
ADE7878 only. In 3-phase systems, the neutral current is equal serial ports of the ADE7868/ADE7878 work on 32-, 16-, or 8-bit
to the algebraic sum of the phase currents words and the DSP works on 28 bits. As presented in Figure 53,
IN(t) = IA(t) + IB(t) + IC(t) ISUM, the 28-bit signed register, is accessed as a 32-bit register
with the four most significant bits padded with 0s.
If there is a mismatch between these two quantities, then a
31 28 27 0
08510-250
tamper situation may have occurred in the system. 0000 28-BIT SIGNED NUMBER
The ADE7868/ADE7878 compute the sum of the phase

currents adding the content of the IAWV, IBWV, and ICWV BIT 27 IS A SIGN BIT
registers, and storing the result into the ISUM 28-bit signed Figure 53. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
register: ISUM(t) = IA(t) + IB(t) + IC(t). ISUM is computed every
Similar to the registers presented in Figure 35, the ISUMLVL
125 µs (8 kHz frequency), the rate at which the current samples
register is accessed as a 32-bit register with four most significant
are available, and Bit 17 (DREADY) in the STATUS0 register is
bits padded with 0s and sign extended to 28 bits.
used to signal when the ISUM register can be read. See the
Digital Signal Processor section for more details on Bit DREADY. PHASE COMPENSATION
To recover ISUM(t) value from the ISUM register, use the As described in the Current Channel ADC and Voltage Channel
following expression: ADC sections, the datapath for both current and voltages is the
same. The phase error between current and voltage signals
ISUM[27:0]
I SUM (t ) = × I FS introduced by the ADE7854/ADE7858/ADE7868/ADE7878
ADC MAX
is negligible. However, the ADE7854/ADE7858/ADE7868/
where: ADE7878 must work with transducers that may have inherent
phase errors. For example, a current transformer (CT) with a acceptable; numbers outside this range are not accepted. If the
phase error of 0.1° to 3° is not uncommon. These phase errors current leads the voltage, the result is negative and the absolute
can vary from part to part, and they must be corrected to value is written into the PHCAL registers. If the current lags
perform accurate power calculations. the voltage, the result is positive and 512 is added to the result
The errors associated with phase mismatch are particularly before writing it into xPHCAL.
noticeable at low power factors. The ADE78xx provides a means APHCAL,  x  (8)
of digitally calibrating these small phase errors. The ADE78xx BPHCAL, or  ,x ≤ 0 
 phase _ resolution 
allows a small time delay or time advance to be introduced into CPHCAL =  
 x
the signal processing chain to compensate for the small phase + 512, x > 0
 phase _ resolution 
errors.  
The phase calibration registers (APHCAL, BPHCAL, and Figure 55 illustrates how the phase compensation is used to remove
CPHCAL) are 10-bit registers that can vary the time advance x = −1° phase lead in IA of the current channel from the external
in the voltage channel signal path from −374.0 µs to +61.5 μs. current transducer (equivalent of 55.5 µs for 50 Hz systems). To
Negative values written to the PHCAL registers represent a time cancel the lead (1°) in the current channel of Phase A, a phase
advance whereas positive values represent a time delay. One LSB lead must be introduced into the corresponding voltage channel.
is equivalent to 0.976 µs of time delay or time advance (clock Using Equation 8, APHCAL is 57 least significant bits, rounded
rate of 1.024 MHz). With a line frequency of 60 Hz, this gives up from 56.8. The phase lead is achieved by introducing a time
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the delay of 55.73 µs into the Phase A current.
fundamental. This corresponds to a total correction range of
−8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is As stated in the Current Waveform Gain Registers section, the
−6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/ serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
1.024 MHz). As shown in Figure 54, APHCAL, BPHCAL, and CPHCAL
10-bit registers are accessed as 16-bit registers with the six MSBs
Given a phase error of x degrees, measured using the phase padded with 0s.
voltage as the reference, the corresponding LSBs are computed
08510-038
15 10 9 0
dividing x by the phase resolution (0.0211°/LSB for 60 Hz and 0000 00 xPHCAL
0.0176°/LSB for 50 Hz). Results between −383 and +63 only are
Figure 54. xPHCAL Registers Communicated As 16-Bit Registers
IAP
IA PGA1 ADC
IAN
PHASE
CALIBRATION
APHCAL = 57
VAP
VA PGA3 ADC
VN
1°
IA IA
PHASE COMPENSATION
ACHIEVED DELAYING
VA IA BY 56µs
VA
08510-039
50Hz
Figure 55. Phase Calibration on Voltage Channels

REFERENCE CIRCUIT The drift curve on any particular IC can be matched with either
The nominal reference voltage at the REFIN/OUT pin is 1.2 V. This of these sample curves. The general relationship between the
is the reference voltage for the ADCs in the ADE7854/ absolute value of the voltage reference at a particular endpoint
ADE7858/ADE7868/ADE7878. Use a typical external reference temperature and the temperature coefficient for that region of
voltage of 1.2 V to overdrive the REFIN/OUT pin. The temperature the curve is explained by the following two equations:
coefficient of the internal voltage reference is calculated based  α (− 40°C − 25°C ) 
VREF (−40°C) = VREF (+25°C) × 1 + c 
on the endpoint method. To calculate the drift over  10 6 
temperature, the values of the voltage reference at endpoints
(−40°C and +85°C) are measured and compared to the  α (85°C − 25°C ) 
VREF (85°C) = VREF (25°C) × 1 + h 
reference value at 25°C, which in turn provides the slope of the  10 6 
temperature coefficient curve. Figure 56 is a typical where αc and αh are cold and hot temperature coefficients,
representation of the drift over temperature. It contains two respectively, calculated by
curves: Curve X and Curve Y, which are typical representations
of two possible curvatures that are observed over the entire VREF ( −40°C) − VREF ( +25°C)
specified temperature range. VREF ( +25°C)
αc = × 106 ppm/°C
–40°C +85°C
(−40°C − 25°C )
VREF (85°C) − VREF (25°C)
REFERENCE VOLTAGE
A' C'
CURVE Y
VREF (25°C)
+25°C
αh = × 106 ppm/°C
B (85°C − 25°C )
CURVE X
A C As the sign of cold and hot temperature coefficients can vary

–40°C +85°C from one IC to another, the typical drift is specified for the
whole range with a plus-minus sign(±). To find the typical,
08510-555
TEMPERATURE (°C) minimum and maximum temperature coefficients, as listed in

Figure 56. Internal Voltage Reference Temperature Drift the Specifications section, data based on the end-point method
Figure 56 shows that independent consideration of two regions is collected on ICs spread out over different lots. The minimum
is necessary for accurate analysis of the drift over temperature, and maximum temperature coefficents denote that the drift of
as follows: any particular IC will be within those limits, over the specified
temperature range, with reference to 25°C. See Figure 57 and
• Considering the region between Point A and Point B in Figure 58 for the device-to-device variation of the drift.
Curve X, the reference value increases with an increase in
temperature; thus, the curve has a positive slope from A to
B. This results in a positive temperature coefficient in this
region.
• Considering the region between Point B and Point C in
NUMBER OF PARTS
Curve X, the slope of the curve is negative because the

voltage reference decreases with an increase in
temperature; thus, this region of the curve has a negative
temperature coefficient.
• Based on similar logic, Curve Y has a negative temperature
coefficient between Point A’ and PointB and a positive
temperature coefficient between Point B and PointC’.
08510-256
–50 –45 –40 –35 –30 –5 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50
COLD TEMPERATURE COEFFICIENT (ppm/°C)
Figure 57. Histogram of the Reference Drift from −40°C to +25°C

memory RAM are initialized at 0, their default values, and they
can be read/written without any restriction. The run register,
used to start and stop the DSP, is cleared to 0x0000. The run
register needs to be written with 0x0001 for the DSP to start
NUMBER OF PARTS
code execution.
To protect the integrity of the data stored in the data memory
RAM of the DSP (addresses between 0x4380 and 0x43BE),
a write protection mechanism is available. By default, the
protection is disabled and registers placed between 0x4380 and
0x43BE can be written without restriction. When the protection
is enabled, no writes to these registers is allowed. Registers can
be always read, without restriction, independent of the write
08510-257
–50 –45 –40 –35 –30 –5 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50
protection state.
HOT TEMPERATURE COEFFICIENT (ppm/°C)
Figure 58. Histogram of the Reference Drift from 25°C to 85°C To enable the protection, write 0xAD to an internal 8-bit
Because the reference is used for all ADCs, any x% drift in the register located at Address 0xE7FE, followed by a write of 0x80
reference results in a 2x% deviation of the meter accuracy. The to an internal 8-bit register located at Address 0xE7E3.
reference drift resulting from temperature changes is usually very It is recommended to enable the write protection after the
small and, typically, much smaller than the drift of other registers have been initialized. If any data memory RAM based
components on a meter. register needs to be changed, simply disable the protection,
The ADE7854/ADE7858/ADE7868/ADE7878 use the internal change the value and then re-enable the protection. There is
voltage reference when Bit 0 (EXTREFEN) in the CONFIG2 no need to stop the DSP to change these registers.
register is cleared to 0 (the default value); the external voltage To disable the protection, write 0xAD to an internal 8-bit
reference is used when the bit is set to 1. Set the CONFIG2 register register located at Address 0xE7FE, followed by a write of 0x00
during the PSM0 mode; its value is maintained during the PSM1, to an internal 8-bit register located at Address 0xE7E3.
PSM2, and PSM3 power modes. The recommended procedure to initialize the ADE7854/
DIGITAL SIGNAL PROCESSOR ADE7858/ADE7868/ADE7878 registers at power up is as
The ADE7854/ADE7858/ADE7868/ADE7878 contain a fixed follows:
function digital signal processor (DSP) that computes all powers  Initialize the AIGAIN, BIGAIN, CIGAIN, and NIGAIN
and rms values. It contains program memory ROM and data registers.
memory RAM.
 Start the DSP by setting run = 1.
The program used for the power and rms computations is
 Initialize all the other data memory RAM registers. Write
stored in the program memory ROM and the processor executes
the last register in the queue three times to ensure its
it every 8 kHz. The end of the computations is signaled by
value was written into the RAM. Initialize all of the other
setting Bit 17 (DREADY) to 1 in the STATUS0 register. An
ADE7854/ADE7858/ADE7868/ADE7878 registers with the
interrupt attached to this flag can be enabled by setting Bit 17
exception of the CFMODE register.
(DREADY) in the MASK0 register. If enabled, the IRQ0 pin is
set low and Status Bit DREADY is set to 1 at the end of the  Read the energy registers xWATTHR, xFWATTHR,
computations. The status bit is cleared and the IRQ0 pin is set xVARHR, xFVARHR, and xVAHR to erase their content
to high by writing to the STATUS0 register with Bit 17 (DREADY) and start energy accumulation from a known state.
set to 1.  Clear Bit 9 (CF1DIS), Bit 10 (CF2DIS), and Bit 11
The registers used by the DSP are located in the data memory (CF3DIS) in the CFMODE register to enable pulses at
RAM, at addresses between 0x4380 and 0x43BE. The width of the CF1, CF2, and CF3 pins. Do this initialization last,
this memory is 28 bits. Within the DSP core, the DSP contains a so no spurious pulses are generated while the ADE7854/
two stage pipeline. This means that when a single register needs ADE7858/ADE7868/ADE7878 are initialized.
to be initialized, two more writes are required to ensure the  Enable the write protection by writing 0xAD to an internal
value has been written into RAM, and if two or more registers 8-bit register located at Address 0xE7FE, followed by a write of
need to be initialized, the last register must be written two more 0x80 to an internal 8-bit register located at Address 0xE7E3.
times to ensure the value has been written into RAM.
 Read back all data memory RAM registers to ensure they
As explained in the Power-Up Procedure section, at power-up were initialized with the desired values.
or after a hardware or software reset, the DSP is in idle mode.
No instruction is executed. All the registers located in the data  In the remote case that one or more registers are not initia-
lized correctly, disable the protection by writing 0xAD to
an internal 8-bit register located at Address 0xE7FE, followed ∞
f (t ) = ∑ Fk 2 sin(kωt + γ k ) (11)
by a write of 0x00 to an internal 8-bit register located at k =1
Address 0xE7E3. Reinitialize the registers. Write the last
Then
register in the queue three times. Enable the write protec-
∞ ∞
tion by writing 0xAD to an internal 8-bit register located f 2 (t ) = ∑ Fk2 − ∑ Fk2 cos(2kωt + 2 γ k ) +
at Address 0xE7FE, followed by a write of 0x80 to an internal k =1 k =1
8-bit register located at Address 0xE7E3. ∞ (12)
+2 ∑ 2 × Fk × Fm sin(kωt + γ k ) × sin(mωt + γ m )
There is no obvious reason to stop the DSP if the ADE78xx is k ,m=1
k ≠m
maintained in PSM0 normal mode. All ADE78xx registers,
including ones located in the data memory RAM, can be After the LPF and the execution of the square root, the rms
modified without stopping the DSP. However, to stop the DSP, value of f(t) is obtained by
0x0000 has to be written into run register. To restart the DSP, ∞
one of the following procedures must be followed: F= ∑ Fk2 (13)
k =1
• If the ADE7854/ADE7858/ADE7868/ADE7878 registers
The rms calculation based on this method is simultaneously
located in the data memory RAM have not been modified,
processed on all seven analog input channels. Each result is
write 0x0001 into the run register to start the DSP.
available in the 24-bit registers: AIRMS, BIRMS, CIRMS,
• If the ADE7854/ADE7858/ADE7868/ADE7878 registers
AVRMS, BVRMS, CVRMS, and NIRMS (NIRMS is available
located in the data memory RAM have to be modified, first
on the ADE7868 and ADE7878 only).
execute a software or a hardware reset, and then follow the
recommended procedure to initialize the registers at power The second method computes the absolute value of the input
up. signal and then filters it to extract its dc component. It computes
the absolute mean value of the input. If the input signal in
As mentioned in the Power Management section, when the Equation 12 has a fundamental component only, its average
ADE7854/ADE7858/ADE7868/ADE7878 switch out of PSM0 value is
power mode, it is recommended to stop the DSP by writing
0x0000 into the run register (see Figure 11 and Table 12 for T T

1 2 
the recommended actions when changing power modes). FDC =  ∫ 2 × F1 × sin(ωt )dt − ∫ 2 × F1 × sin(ωt )dt 
T 0 T
ROOT MEAN SQUARE MEASUREMENT  2

Root mean square (rms) is a measurement of the magnitude of 2

FDC = × 2 × F1
an ac signal. Its definition can be both practical and mathematical. π
Defined practically, the rms value assigned to an ac signal is the The calculation based on this method is simultaneously processed
amount of dc required to produce an equivalent amount of only on the three phase currents. Each result is available in the
power in the load. Mathematically, the rms value of a conti- 20-bit registers, which are available on the ADE7868 and
nuous signal f(t) is defined as ADE7878 only: AIMAV, BMAV, and CMAV. Note that the
1 t 2 proportionality between mav and rms values is maintained for
F rms = ∫ f (t )dt
t 0
(9) the fundamental components only. If harmonics are present in the
current channel, the mean absolute value is no longer
For time sampling signals, rms calculation involves squaring the proportional to rms.
signal, taking the average, and obtaining the square root.
Current RMS Calculation
1 N
F rms =
N
∑ f [n]
2
(10) This section presents the first approach to compute the rms
N =1 values of all phase and neutral currents.
Equation 10 implies that for signals containing harmonics, the Figure 59 shows the detail of the signal processing chain for the
rms calculation contains the contribution of all harmonics, not rms calculation on one of the phases of the current channel.
only the fundamental. The ADE78xx uses two different methods The current channel rms value is processed from the samples
to calculate rms values. The first one is very accurate and is active used in the current channel. The current rms values are signed
only in PSM0 mode. The second one is less accurate, uses the 24-bit values and they are stored into the AIRMS, BIRMS, CIRMS,
estimation of the mean absolute value (mav) measurement, is and NIRMS (ADE7868/ADE7878 only) registers. The update
active in PSM0 and PSM1 modes, and is available for the rate of the current rms measurement is 8 kHz.
ADE7868 and ADE7878 only.
With the specified full-scale analog input signal of 0.5 V, the
The first method is to low-pass filter the square of the input ADC produces an output code that is approximately ±5,928,256.
signal (LPF) and take the square root of the result (see Figure 59). The equivalent rms value of a full-scale sinusoidal signal is
4,191,910 (0x3FF6A6), independent of the line frequency. If
the integrator is enabled, that is, when Bit 0 (INTEN) in the power-up and DSP reset cases, it would typically take about
CONFIG register is set to 1, the equivalent rms value of a full- 1.2 seconds for a FS/1000 signal to be settled.
scale sinusoidal signal at 50 Hz is 4,191,910 (0x3FF6A6) and at
Table 13. Settling Time for I rms Measurement
60 Hz is 3,493,258 (0x354D8A).
Integrator Status 50 Hz Input signals 60 Hz Input signals
The accuracy of the current rms is typically 0.1% error from Integrator Off 440 ms 440 ms
the full-scale input down to 1/1000 of the full-scale input when Integrator On 550 ms 500 ms
PGA = 1. Additionally, this measurement has a bandwidth of
2 kHz. It is recommended to read the rms registers synchronous As stated in the Current Waveform Gain Registers section, the
to the voltage zero crossings to ensure stability. The IRQ1 inter- serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
rupt can be used to indicate when a zero crossing has occurred Similar to the register presented in Figure 36, the AIRMS,
(see the Interrupts section). Table 13 shows the settling time for BIRMS, CIRMS, and NIRMS (ADE7868 and ADE7878 only)
the I rms measurement, which is the time it takes for the rms 24-bit signed registers are accessed as 32-bit registers with the
register to reflect the value at the input to the current channel eight MSBs padded with 0s.
when starting from 0 to full scale. However, during the chip
xIRMSOS[23:0]
27
CURRENT SIGNAL FROM

HPF OR INTEGRATOR x2 √ xIRMS[23:0]
(IF ENABLED) LPF
0x5A7540 =
5,928,256
0V
08510-040
0xA58AC0 =
–5,928,256
Figure 59. Current RMS Signal Processing

212000
Current RMS Offset Compensation
211500
The ADE7854/ADE7858/ADE7868/ADE7878 incorporate a
211000
current rms offset compensation register for each phase:
AIRMSOS, BIRMSOS, CIRMSOS registers, and the NIRMSOS 210500
register for ADE7868 and ADE7878 only. These are 24-bit 210000
signed registers that are used to remove offsets in the current
LSB
209500
rms calculations. An offset can exist in the rms calculation due
209000
to input noises that are integrated in the dc component of I2(t).
208500
The current rms offset register is multiplied by 128 and added
208000
to the squared current rms before the square root is executed.
Assuming that the maximum value from the current rms 207500
calculation is 4,191,910 with full-scale ac inputs (50 Hz), one LSB of
08510-252
207000
45 50 55 60 65
the current rms offset represents 0.00037% (( 41912  128 /4191 FREQUENCY (Hz)
− 1) × 100) of the rms measurement at 60 dB down from full Figure 61. xIMAV Register Values at Full Scale, 45 Hz to 65 Hz Line
scale. Conduct offset calibration at low current; avoid using Frequencies
currents equal to zero for this purpose. The mav values of full-scale sinusoidal signals of 50 Hz and
60 Hz are 209,686 and 210,921, respectively. As seen in Figure 61,
I rms  I rms02  128  IRMSOS (14)
there is a 1.25% variation between the mav estimate at 45 Hz
where I rms0 is the rms measurement without offset correction. and the one at 65 Hz for full-scale sinusoidal inputs. The accuracy
of the current mav is typically 0.5% error from the full-scale
input down to 1/100 of the full-scale input. Additionally, this
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words
measurement has a bandwidth of 2 kHz. The settling time for
and the DSP works on 28 bits. Similar to the register presented
the current mav measurement, that is the time it takes for the
in Figure 35, the AIRMSOS, BIRMSOS, CIRMSOS, and
mav register to reflect the value at the input to the current
NIRMSOS (ADE7868/ADE7878 only) 24-bit signed registers
channel within 0.5% error, is 500 ms. However, during the first
are accessed as 32-bit registers with four MSBs padded with 0s
measurement after entering this mode, it takes a longer time to
and sign extended to 28 bits.
settle to the correct value.
Current Mean Absolute Value Calculation—ADE7868
and ADE7878 Only As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7868/ADE7878 work on 32-, 16-, or
This section presents the second approach to estimate the rms 8-bit words. As presented in Figure 62, the AIMAV, BIMAV, and
values of all phase currents using the mean absolute value (mav) CIMAV 20-bit unsigned registers are accessed as 32-bit registers
method. This approach is used in PSM1 mode, which is available with the 12 MSBs padded with 0s.
to the ADE7868 and ADE7878 only, to allow energy accumu- 31 20 19 0
08510-253
lation based on current rms values when the missing neutral 0000 0000 0000 20-BIT UNSIGNED NUMBER
case demonstrates to be a tamper attack. This datapath is active Figure 62. xIMAV Registers Transmitted as 32-Bit Registers
also in PSM0 mode to allow for its gain calibration. The gain is
used in the external microprocessor during PSM1 mode. The Current MAV Gain and Offset Compensation
mav value of the neutral current is not computed using this The current rms values stored in the AIMAV, BIMAV, and
method. Figure 60 shows the details of the signal processing CIMAV registers can be calibrated using gain and offset
chain for the mav calculation on one of the phases of the current coefficients corresponding to each phase. It is recommended to
channel. calculate the gains in PSM0 mode by supplying the ADE7868/
ADE7878 with nominal currents. The offsets can be estimated
08510-251
CURRENT SIGNAL |X| xIMAV[23:0]

COMING FROM ADC
HPF LPF by supplying the ADE7868/ADE7878 with low currents, usually
Figure 60. Current MAV Signal Processing for PSM1 Mode equal to the minimum value at which the accuracy is required.
Every time the external microcontroller reads the AIMAV,
The current channel mav value is processed from the samples
used in the current channel waveform sampling mode. The BIMAV, and CIMAV registers, it uses these coefficients stored
samples are passed through a high-pass filter to eliminate the in its memory to correct them.
eventual dc offsets introduced by the ADCs and the absolute Voltage Channel RMS Calculation
values are computed. The outputs of this block are then filtered Figure 63 shows the detail of the signal processing chain for the
to obtain the average. The current mav values are unsigned 20-bit rms calculation on one of the phases of the voltage channel. The
values and they are stored in the AIMAV, BIMAV, and CIMAV voltage channel rms value is processed from the samples used in
registers. The update rate of this mav measurement is 8 kHz. the voltage channel. The voltage rms values are signed 24-bit

values and they are stored into the Registers AVRMS, BVRMS, and to ensure stability. The IRQ1 interrupt can be used to indicate
CVRMS. The update rate of the current rms measurement is 8 kHz. when a zero crossing has occurred (see the Interrupts section).
With the specified full-scale analog input signal of 0.5 V, the The settling time for the V rms measurement is 440 ms for both
ADC produces an output code that is approximately ±5,928,256. 50 Hz and 60 Hz input signals. The V rms measurement settling
The equivalent rms value of a full-scale sinusoidal signal is time is the time it takes for the rms register to reflect the value
4,191,910 (0x3FF6A6), independent of the line frequency. at the input to the voltage channel when starting from 0.
The accuracy of the voltage rms is typically 0.1% error from the As stated in the Current Waveform Gain Registers section, the
full-scale input down to 1/1000 of the full-scale input. Additionally, serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
this measurement has a bandwidth of 2 kHz. It is recommended Similar to the register presented in Figure 36, the AVRMS,
to read the rms registers synchronous to the voltage zero crossings BVRMS, and CVRMS 24-bit signed registers are accessed as
32-bit registers with the eight MSBs padded with 0s.
xVRMSOS[23:0]
27
VOLTAGE SIGNAL
FROM HPF
x2 √ xVRMS[23:0]
LPF
0x5A7540 =
5,928,256
0V
08510-041
0xA58AC0 =
–5,928,256
Figure 63. Voltage RMS Signal Processing

Voltage RMS Offset Compensation ac system is supplied by a voltage, v(t), and consumes the current,
The ADE78xx incorporates voltage rms offset compensation i(t), and each of them contains harmonics, then
registers for each phase: AVRMSOS, BVRMSOS, and CVRMSOS. 
v(t )  Vk 2 sin (kωt + φk) (16)
These are 24-bit signed registers used to remove offsets in the k 1
voltage rms calculations. An offset can exist in the rms calculation 
due to input noises that are integrated in the dc component of i(t )   I k 2 sinkωt  γ k 
V2(t). The voltage rms offset register is multiplied by 128 and k 1
added to the squared current rms before the square root is where:
executed. Assuming that the maximum value from the voltage Vk, Ik are rms voltage and current, respectively, of each
rms calculation is 4,191,910 with full-scale ac inputs (50 Hz), one harmonic.
LSB of the voltage rms offset represents 0.00037% φk, γk are the phase delays of each harmonic.
(( 41912  128 /4191 − 1) × 100) of the rms measurement at The instantaneous power in an ac system is
60 dB down from full scale. Conduct offset calibration at low  
current; avoid using voltages equal to zero for this purpose. p(t) = v(t) × i(t) = Vk I k cos(φk – γk) − Vk I k cos(2kωt + φk + γk) +
k 1 k 1

V rms  V rms02  128  VRMSOS (15) Vk I m {cos[(k − m)ωt + φk – γm] – cos[(k + m)ωt + φk + γm]}
k , m 1
where V rms0 is the rms measurement without offset correction. k m
As stated in the Current Waveform Gain Registers section, the (17)

serial ports of the ADE78xx work on 32-, 16-, or 8-bit words The average power over an integral number of line cycles (n) is
and the DSP works on 28 bits. Similar to registers presented in given by the expression in Equation 18.
Figure 35, the AVRMSOS, BVRMSOS, and CVRMSOS 24-bit 
1 nT
registers are accessed as 32-bit registers with the four most P=  pt dt  Vk I k cos(φk – γk) (18)
nT 0 k 1
significant bits padded with 0s and sign extended to 28 bits.
where:
ACTIVE POWER CALCULATION
T is the line cycle period.
The ADE7854/ADE7858/ADE7868/ADE7878 compute the P is referred to as the total active or total real power.
total active power on every phase. Total active power considers
Note that the total active power is equal to the dc component of
in its calculation all fundamental and harmonic components of
the instantaneous power signal p(t) in Equation 17, that is,
the voltages and currents. In addition, the ADE7878 computes 
the fundamental active power, the power determined only by Vk I k cos(φk – γk)
the fundamental components of the voltages and currents. k 1
Total Active Power Calculation This is the expression used to calculate the total active power in
the ADE78xx for each phase. The expression of fundamental active
Electrical power is defined as the rate of energy flow from source
power is obtained from Equation 18 with k = 1, as follows:
to load, and it is given by the product of the voltage and current
FP = V1I1 cos(φ1 – γ1) (19)
waveforms. The resulting waveform is called the instantaneous
power signal, and it is equal to the rate of energy flow at every Figure 64 shows how the ADE78xx computes the total active
instant of time. The unit of power is the watt or joules/sec. If an power on each phase. First, it multiplies the current and voltage
signals in each phase. Next, it extracts the dc component of the
instantaneous power signal in each phase (A, B, and C) using
LPF2, the low-pass filter.
HPFDIS DIGITAL
[23:0] INTEGRATOR AIGAIN
IA AWGAIN AWATTOS
HPF
HPFDIS
INSTANTANEOUS
APHCAL [23:0] AVGAIN PHASE A ACTIVE
LPF POWER
VA
AWATT
HPF
08510-145
24
DIGITAL SIGNAL PROCESSOR
Figure 64. Total Active Power Datapath

If the phase currents and voltages contain only the fundamental PMAX = 33,516,139; it is the instantaneous power computed
component, are in phase (that is φ1 = γ1 = 0), and they correspond when the ADC inputs are at full scale and in phase.
to full-scale ADC inputs, then multiplying them results in an The xWATT[23:0] waveform registers can be accessed using
instantaneous power signal that has a dc component, V1 × I1, various serial ports. Refer to the Waveform Sampling Mode
and a sinusoidal component, V1 × I1 cos(2ωt); Figure 65 shows section for more details.
the corresponding waveforms.
INSTANTANEOUS
Fundamental Active Power Calculation—ADE7878 Only
p(t)= V rms × I rms – V rms × I rms × cos(2ωt)
POWER SIGNAL
0x3FED4D6 The ADE7878 computes the fundamental active power using
67,032,278
INSTANTANEOUS a proprietary algorithm that requires some initializations function
ACTIVE POWER
SIGNAL: V rms × I rms of the frequency of the network and its nominal voltage measured
in the voltage channel. Bit 14 (SELFREQ) in the COMPMODE
V rms × I rms
0x1FF6A6B =
register must be set according to the frequency of the network in
33,516,139
which the ADE7878 is connected. If the network frequency is
50 Hz, clear this bit to 0 (the default value). If the network fre-
quency is 60 Hz, set this bit to 1. In addition, initialize the VLEVEL
0x000 0000 24-bit signed register with a positive value based on the
following expression:
i(t) = √2 × I rms × sin(ωt)
v(t) = √2 × V rms × sin(ωt) VFS
VLEVEL = × 491,520 (21)
08510-043
Vn
Figure 65. Active Power Calculation where:
VFS is the rms value of the phase voltages when the ADC inputs
Because LPF2 does not have an ideal brick wall frequency
are at full scale.
response (see Figure 66), the active power signal has some
Vn is the rms nominal value of the phase voltage.
ripple due to the instantaneous power signal. This ripple is
sinusoidal and has a frequency equal to twice the line frequency. As stated in the Current Waveform Gain Registers section, the
Because the ripple is sinusoidal in nature, it is removed when serial ports of the ADE7878 work on 32-, 16-, or 8-bit words
the active power signal is integrated over time to calculate the and the DSP works on 28 bits. Similar to the registers presented
energy. in Figure 35, the VLEVEL 24-bit signed register is accessed as a
0 32-bit register with four most significant bits padded with 0s
and sign extended to 28 bits.
–5 Table 14 presents the settling time for the fundamental active
power measurement.
MAGNITUDE (dB)
–10 Table 14. Settling Time for Fundamental Active Power

Input Signals
–15 63% Full Scale 100% Full Scale
375 ms 875 ms
–20 Active Power Gain Calibration
Note that the average active power result from the LPF2 output
–25 in each phase can be scaled by ±100% by writing to the phase’s
08510-103
0.1 1 3 10
FREQUENCY (Hz) watt gain 24-bit register (AWGAIN, BWGAIN, CWGAIN,
AFWGAIN, BFWGAIN, or CFWGAIN). The xWGAIN
Figure 66. Frequency Response of the LPF Used
to Filter Instantaneous Power in Each Phase registers are placed in each phase of the total active power
datapath, and the xFWGAIN (available for the ADE7878 only)
The ADE7854/ADE7858/ADE7868/ADE7878 store the
registers are placed in each phase of the fundamental active
instantaneous total phase active powers into the AWATT,
power datapath. The watt gain registers are twos complement,
BWATT, and CWATT registers. Their expression is
signed registers and have a resolution of 2−23/LSB. Equation 22
∞ Vk I 1 describes mathematically the function of the watt gain registers.
xWATT = ∑ × k × cos(φk – γk) × PMAX × 4 (20)
V
k =1 FS I FS 2 Average Power Data =
where:  Watt Gain Register  (22)
VFS, IFS are the rms values of the phase voltage and current when LPF 2 Output × 1 + 
 223 
the ADC inputs are at full scale.

The output is scaled by −50% by writing 0xC00000 to the watt Calculation section, the active energy accumulation is performed
gain registers, and it is increased by +50% by writing 0x400000 in two stages. Every time a sign change is detected in the energy
to them. These registers are used to calibrate the active power accumulation at the end of the first stage, that is, after the energy
(or energy) calculation in the ADE7854/ADE7858/ADE7868/ accumulated into the internal accumulator reaches the WTHR
ADE7878for each phase. register threshold, a dedicated interrupt is triggered. The sign of
As stated in the Current Waveform Gain Registers section, the each phase active power can be read in the PHSIGN register.
serial ports of the ADE7854/ADE7858/ADE7868/ADE7878 Bit 6 (REVAPSEL) in the ACCMODE register sets the type
work on 32-, 16-, or 8-bit words, and the DSP works on 28 bits. of active power being monitored. When REVAPSEL is 0,
Similar to registers presented in Figure 35, AWGAIN, BWGAIN, the default value, the total active power is monitored. When
CWGAIN, AFWGAIN, BFWGAIN, and CFWGAIN 24-bit REVAPSEL is 1, the fundamental active power is monitored.
signed registers are accessed as 32-bit registers with the four Bits[8:6] (REVAPC, REVAPB, and REVAPA, respectively) in the
MSBs padded with 0s and sign extended to 28 bits. STATUS0 register are set when a sign change occurs in the
Active Power Offset Calibration power selected by Bit 6 (REVAPSEL) in the ACCMODE
The ADE7854/ADE7858/ADE7868/ADE7878 incorporate a register.
watt offset 24-bit register on each phase and on each active Bits[2:0] (CWSIGN, BWSIGN, and AWSIGN, respectively) in
power. The AWATTOS, BWATTOS, and CWATTOS registers the PHSIGN register are set simultaneously with the REVAPC,
compensate the offsets in the total active power calculations, REVAPB, and REVAPA bits. They indicate the sign of the power.
and the AFWATTOS, BFWATTOS, and CFWATTOS registers When they are 0, the corresponding power is positive. When
compensate offsets in the fundamental active power calculations. they are 1, the corresponding power is negative.
These are signed twos complement, 24-bit registers that are
Bit REVAPx of STATUS0 and Bit xWSIGN in the PHSIGN
used to remove offsets in the active power calculations. An
register refer to the total active power of Phase x, the power type
offset can exist in the power calculation due to crosstalk between being selected by Bit 6 (REVAPSEL) in the ACCMODE register.
channels on the PCB or in the chip itself. One LSB in the active
power offset register is equivalent to 1 LSB in the active power Interrupts attached to Bits[8:6] (REVAPC, REVAPB, and REVAPA,
multiplier output. With full-scale current and voltage inputs, respectively) in the STATUS0 register can be enabled by setting
the LPF2 output is PMAX = 33,516,139. At −80 dB down from Bits[8:6] in the MASK0 register. If enabled, the IRQ0 pin is set
the full scale (active power scaled down 104 times), one LSB of low, and the status bit is set to 1 whenever a change of sign occurs.
the active power offset register represents 0.0298% of PMAX. To find the phase that triggered the interrupt, the PHSIGN register
is read immediately after reading the STATUS0 register. Next, the
status bit is cleared and the IRQ0 pin is returned to high by writing
serial ports of the ADE7854/ADE7858/ADE7868/ADE7878
to the STATUS0 register with the corresponding bit set to 1.
work on 32-, 16-, or 8-bit words and the DSP works on 28 bits.
Similar to registers presented in Figure 35, the AWATTOS, Active Energy Calculation
BWATTOS, CWATTOS, AFWATTOS, BFWATTOS, and As previously stated, power is defined as the rate of energy flow.
CFWATTOS 24-bit signed registers are accessed as 32-bit This relationship can be expressed mathematically as
registers with the four MSBs padded with 0s and sign extended
dEnergy
to 28 bits. Power = (23)
dt
Sign of Active Power Calculation
Conversely, energy is given as the integral of power, as follows:
The average active power is a signed calculation. If the phase
difference between the current and voltage waveform is more Energy = ∫ p (t )dt (24)
than 90°, the average power becomes negative. Negative power Total and fundamental active energy accumulations are always
indicates that energy is being injected back on the grid. The signed operations. Negative energy is subtracted from the active
ADE78xx has sign detection circuitry for active power energy contents.
calculations. It can monitor the total active powers or the
fundamental active powers. As described in the Active Energy

HPFDIS DIGITAL
REVAPA BIT IN
IA STATUS0[31:0]
HPF AWGAIN AWATTOS
AWATTHR[31:0]
HPFDIS
ACCUMULATOR
LPF2 32-BIT
VA REGISTER
HPF WTHR[47:0]
AWATT
08510-044
DIGITAL SIGNAL PROCESSOR 24
Figure 67. Total Active Energy Accumulation
The ADE7854/ADE7858/ADE7868/ADE7878 achieve the where:

integration of the active power signal in two stages (see Figure 67). PMAX = 33,516,139 = 0x1FF6A6B as the instantaneous power
The process is identical for both total and fundamental active computed when the ADC inputs are at full scale.
powers. The first stage is accomplished inside the DSP: every fS = 8 kHz, the frequency with which the DSP computes the
125 µs (8 kHz frequency) the instantaneous phase total or funda- instantaneous power.
mental active power is accumulated into an internal register. VFS, IFS are the rms values of phase voltages and currents when
When a threshold is reached, a pulse is generated at the processor the ADC inputs are at full scale.
port, and the threshold is subtracted from the internal register. The maximum value that can be written on WTHR is 247 − 1.
The sign of the energy in this moment is considered the sign of The minimum value is 0x0, but it is recommended to write a
the active power (see Sign of Active Power Calculation section number equal to or greater than PMAX. Never use negative
for details). The second stage is done outside the DSP and consists numbers.
of accumulating the pulses generated by the processor into internal
32-bit accumulation registers. The content of these registers is WTHR is a 48-bit register. As stated in the Current Waveform
transferred to watt-hour registers, xWATTHR and xFWATTHR, Gain Registers section, the serial ports of the ADE7854/ADE7858/
when these registers are accessed. ADE7868/ADE7878work on 32-, 16-, or 8-bit words. As shown
WTHR[47:0]
in Figure 69, the WTHR register is accessed as two 32-bit
registers (WTHR1 and WTHR0), each having eight MSBs
padded with 0s.
ACTIVE POWER WTHR[47:0]
ACCUMULATION
IN DSP
47 24 23 0
31 24 23 0 31 24 23 0
0000 0000 24 BIT SIGNED NUMBER 0000 0000 24 BIT SIGNED NUMBER
08510-046
DSP
08510-045
GENERATED
PULSES WTHR1[31:0] WTHR0[31:0]
1 DSP PULSE = 1LSB OF WATTHR[31:0]
Figure 69. WTHR[47:0] Communicated As Two 32-Bit Registers
Figure 68. Active Power Accumulation Inside the DSP
This discrete time accumulation or summation is equivalent to
Figure 68 explains this process. The WTHR 48-bit signed register
integration in continuous time following the description in
contains the threshold. It is introduced by the user and is common
Equation 26.
for all phase total and fundamental active powers. Its value
depends on how much energy is assigned to one LSB of watt- ∞ 
Energy = ∫ p (t )dt = Lim  ∑ p (nT ) × T  (26)
hour registers. When a derivative of active energy (wh) of [10n T→0 n =0 
wh], where n is an integer, is desired as one LSB of the
where:
xWATTHR register, then, the xWATTHR register can be
n is the discrete time sample number.
computed using the following equation:
T is the sample period.
PMAX × f S × 3600 × 10 n In the ADE7854/ADE7858/ADE7868/ADE7878, the total phase
WTHR = (25)
VFS × I FS active powers are accumulated in the AWATTHR, BWATTHR, and
CWATTHR 32-bit signed registers, and the fundamental phase
active powers are accumulated in AFWATTHR, BFWATTHR, and

CFWATTHR 32-bit signed registers. The active energy register Table 15. Inputs to Watt-Hour Accumulation Registers
content can roll over to full-scale negative (0x80000000) and CONSEL AWATTHR BWATTHR CWATTHR
continue increasing in value when the active power is positive. 00 VA × IA VB × IB VC × IC
Conversely, if the active power is negative, the energy register 01 VA × IA 0 VC × IC
underflows to full-scale positive (0x7FFFFFFF) and continues 10 VA × IA VB × IB VC × IC
decreasing in value. VB = −VA − VC
Bit 0 (AEHF) in the STATUS0 register is set when Bit 30 of 11 VA × IA VB × IB VC × IC
one of the xWATTHR registers changes, signifying one of these VB = −VA
registers is half full. If the active power is positive, the watt-hour Depending on the polyphase meter service, choose the appro-
register becomes half full when it increments from 0x3FFF FFFF to priate formula to calculate the active energy. The American
0x4000 0000. If the active power is negative, the watt-hour ANSI C12.10 standard defines the different configurations of
register becomes half full when it decrements from 0xC000 the meter. Table 16 describes which mode to choose in these
0000 to 0xBFFF FFFF. Similarly, Bit 1 (FAEHF) in STATUS0 various configurations.
register, is set when Bit 30 of one of the xFWATTHR registers
changes, signifying one of these registers is half full. Table 16. Meter Form Configuration
ANSI Meter Form Configuration CONSEL
Setting Bits[1:0] in the MASK0 register enable the FAEHF and
5S/13S 3-wire delta 01
AEHF interrupts, respectively. If enabled, the IRQ0 pin is set
6S/14S 4-wire wye 10
low and the status bit is set to 1 whenever one of the energy
8S/15S 4-wire delta 11
registers, xWATTHR (for the AEHF interrupt) or xFWATTHR
9S/16S 4-wire wye 00
(for the FAEHF interrupt), become half full. The status bit is
cleared and the IRQ0 pin is set to logic high by writing to the Bits[1:0] (WATTACC[1:0]) in the ACCMODE register determine
STATUS0 register with the corresponding bit set to 1. how the CF frequency output can be generated as a function of
the total and fundamental active powers. Whereas the watt-hour
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
accumulation registers accumulate the active power in a signed
read-with-reset for all watt-hour accumulation registers, that is,
format, the frequency output can be generated in signed mode
the registers are reset to 0 after a read operation.
or in absolute mode as a function of the WATTACC[1:0] bits.
Integration Time Under Steady Load See the Energy-to-Frequency Conversion section for details.
The discrete time sample period (T) for the accumulation register Line Cycle Active Energy Accumulation Mode
is 125 µs (8 kHz frequency). With full-scale sinusoidal signals
In line cycle energy accumulation mode, the energy accumula-
on the analog inputs and the watt gain registers set to 0x00000, the
tion is synchronized to the voltage channel zero crossings such
average word value from each LPF2 is PMAX = 33,516,139 =
that active energy is accumulated over an integral number of
0x1FF6A6B. If the WTHR register threshold is set at the PMAX
half line cycles. The advantage of summing the active energy
level, this means the DSP generates a pulse that is added at watt-
over an integer number of line cycles is that the sinusoidal compo-
hour registers every 125 µs.
nent in the active energy is reduced to 0. This eliminates any
The maximum value that can be stored in the watt-hour ripple in the energy calculation and allows the energy to be
accumulation register before it overflows is 231 − 1 or accumulated accurately over a shorter time. By using the line
0x7FFFFFFF. The integration time is calculated as cycle energy accumulation mode, the energy calibration can be
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec (27) greatly simplified, and the time required to calibrate the meter
can be significantly reduced. In line cycle energy accumulation
Energy Accumulation Modes
mode, the ADE7854/ADE7858/ADE7868/ADE7878 transfer the
The active power accumulated in each watt-hour accumulation active energy accumulated in the 32-bit internal accumulation
32-bit register (AWATTHR, BWATTHR, CWATTHR, registers into the xWATTHR or xFWATTHR registers after an
AFWATTHR, BFWATTHR, and CFWATTHR) depends on the integral number of line cycles, as shown in Figure 70. The
configuration of Bit 5 and Bit 4 (CONSEL bits) in the ACCMODE number of half line cycles is specified in the LINECYC register.
register. The various configurations are described in Table 15.

Because the active power is integrated on an integer number of
ZXSEL[0] IN
LCYCMODE[7:0]
half-line cycles in this mode, the sinusoidal components are

ZERO-
CROSSING reduced to 0, eliminating any ripple in the energy calculation.
DETECTION
(PHASE A) Therefore, total energy accumulated using the line cycle
ZXSEL[1] IN accumulation mode is
LCYCMODE[7:0] LINECYC[15:0]
t +nT ∞
ZERO-
CROSSING CALIBRATION
e= ∫ p (t )dt = nT ∑ Vk I k cos(φk – γk) (28)
t k =1
DETECTION CONTROL
(PHASE B)
where nT is the accumulation time.
ZXSEL[2] IN
LCYCMODE[7:0] Note that line cycle active energy accumulation uses the same
ZERO-
signal path as the active energy accumulation. The LSB size of
CROSSING
DETECTION
these two methods is equivalent.
(PHASE C)
REACTIVE POWER CALCULATION—ADE7858,
AWATTOS
ADE7868, ADE7878 ONLY
AWGAIN AWATTHR[31:0]
The ADE7858/ADE7868/ADE7878 can compute the total
OUTPUT reactive power on every phase. Total reactive power integrates
FROM LPF2
ACCUMULATOR
32-BIT
all fundamental and harmonic components of the voltages and
REGISTER
currents. The ADE7878 also computes the fundamental reactive
08510-147
WTHR[47:0]
power, the power determined only by the fundamental

Figure 70. Line Cycle Active Energy Accumulation Mode components of the voltages and currents.
The line cycle energy accumulation mode is activated by setting A load that contains a reactive element (inductor or capacitor)
Bit 0 (LWATT) in the LCYCMODE register. The energy accu- produces a phase difference between the applied ac voltage and
mulation over an integer number of half line cycles is written the resulting current. The power associated with reactive elements
to the watt-hour accumulation registers after LINECYC number is called reactive power, and its unit is VAR. Reactive power is
of half line cycles is detected. When using the line cycle defined as the product of the voltage and current waveforms when
accumulation mode, the Bit 6 (RSTREAD) of the LCYCMODE all harmonic components of one of these signals are phase
register should be set to Logic 0 because the read with reset of shifted by 90°.
watt-hour registers is not available in this mode. Equation 31 gives an expression for the instantaneous reactive
Phase A, Phase B, and Phase C zero crossings are, respectively, power signal in an ac system when the phase of the current
included when counting the number of half line cycles by setting channel is shifted by +90°.
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi- ∞
nation of the zero crossings from all three phases can be used v(t ) = ∑ Vk 2 sin(kωt + φk) (29)
k =1
for counting the zero crossing. Select only one phase at a time
∞
for inclusion in the zero crossings count during calibration. i(t ) = ∑ I k 2 sin(kωt + γk ) (30)
k =1
The number of zero crossings is specified by the LINECYC 16-bit
∞ π
unsigned register. The ADE78xx can accumulate active power i ' (t ) = ∑ I k 2 sin kωt + γ k + 
for up to 65,535 combined zero crossings. Note that the internal k =1  2
zero-crossing counter is always active. By setting Bit 0 (LWATT) where iʹ(t) is the current waveform with all harmonic
in the LCYCMODE register, the first energy accumulation components phase shifted by 90°.
result is, therefore, incorrect. Writing to the LINECYC register
when the LWATT bit is set resets the zero-crossing counter, thus Next, the instantaneous reactive power, q(t), can be expressed as
ensuring that the first energy accumulation result is accurate. q(t) = v(t) × iʹ(t) (31)
At the end of an energy calibration cycle, Bit 5 (LENERGY) in ∞ π
q(t ) = ∑ Vk I k × 2 sin(kωt + φk) × sin(kωt + γk + )+
the STATUS0 register is set. If the corresponding mask bit in k =1 2
the MASK0 interrupt mask register is enabled, the IRQ0 pin ∞ π
also goes active low. The status bit is cleared and the IRQ0 pin is ∑ Vk I m × 2sin(kωt + φk) × sin(mωt + γm + )
k ,m =1 2
k ≠m
set to high again by writing to the STATUS0 register with the
corresponding bit set to 1.

Note that q(t) can be rewritten as Table 17 presents the settling time for the fundamental reactive
∞ power measurement, which is the time it takes the power to
{
q(t ) = ∑ Vk I k cos(φk − γk −
π
2
) − cos(2 kωt + φ + γ + π )} +
k k
2
reflect the value at the input of the ADE7878.
k =1
Table 17. Settling Time for Fundamental Reactive Power

∞
∑ V kI m
k ,m =1
{cos[(k – m)ωt + φ − γ − π2 ]−
k k
Input Signals
k ≠m 63% Full Scale 100% Full Scale
375 ms 875 ms
cos[(k + m)ωt + φk + γk +
π
]} (32) Reactive Power Gain Calibration
2
The average total reactive power over an integral number of line The average reactive power in each phase can be scaled by
cycles (n) is given by the expression in Equation 33. ±100% by writing to one of the phase’s VAR gain 24-bit registers
(AVARGAIN, BVARGAIN, CVARGAIN, AFVARGAIN,
1 nT ∞ π BFVARGAIN, or CFVARGAIN). The xVARGAIN registers are
Q= ∫ q(t )dt = ∑ Vk I k cos(φk – γk − ) (33)
nT 0 k =1 2 placed in each phase of the total reactive power datapath. The
∞ xFVARGAIN registers are placed in each phase of the fundamental
Q = ∑ Vk I k sin(φk – γk) reactive power datapath. The xVARGAIN registers are twos com-
k =1
plement signed registers and have a resolution of 2−23/LSB. The
where: function of the xVARGAIN registers is expressed by
T is the period of the line cycle.
Average Reactive Power =
Q is referred to as the total reactive power. Note that the total
reactive power is equal to the dc component of the instantaneous  xVARGAIN Register  (35)
LPF 2 Output × 1 + 
reactive power signal q(t) in Equation 32, that is,  223 
∞
The output is scaled by –50% by writing 0xC00000 to the
∑ Vk I k sin(φk – γk)
k =1 xVARGAIN registers and increased by +50% by writing
This is the relationship used to calculate the total reactive power 0x400000 to them. These registers can be used to calibrate the
in the ADE7858/ADE7868/ADE7878 for each phase. The reactive power (or energy) gain in the ADE78xx for each phase.
instantaneous reactive power signal, q(t), is generated by multi- As stated in the Current Waveform Gain Registers section, the
plying each harmonic of the voltage signals by the 90° phase- serial ports of the ADE7858/ADE7868/ADE7878 work on 32-,
shifted corresponding harmonic of the current in each phase. 16-, or 8-bit words and the DSP works on 28 bits. Similar to
The ADE7858/ADE7868/ADE7878 store the instantaneous registers presented in Figure 35, the AVARGAIN, BVARGAIN,
total phase reactive powers into the AVAR, BVAR, and CVAR CVARGAIN, AFVARGAIN, BFVARGAIN, and CFVARGAIN
registers. Their expression is 24-bit signed registers are accessed as 32-bit registers with the
four MSBs padded with 0s and sign extended to 28 bits.
∞ Vk I 1
xVAR = ∑ × k × sin(φk – γk) × PMAX × 4 (34) Reactive Power Offset Calibration
k =1 VFS I FS 2
The ADE7858/ADE7868/ADE7878 provide a reactive power
where: offset register on each phase and on each reactive power. AVAROS,
VFS, IFS are the rms values of the phase voltage and current when BVAROS, and CVAROS registers compensate the offsets in the
the ADC inputs are at full scale. total reactive power calculations, whereas AFVAROS, BFVAROS,
PMAX = 33,516,139, the instantaneous power computed when and CFVAROS registers compensate offsets in the fundamental
the ADC inputs are at full scale and in phase. reactive power calculations. These are signed twos complement,
The xVAR waveform registers can be accessed using various 24-bit registers that are used to remove offsets in the reactive
serial ports. Refer to the Waveform Sampling Mode section for power calculations. An offset can exist in the power calculation
more details. due to crosstalk between channels on the PCB or in the chip
The expression of fundamental reactive power is obtained from itself. The offset resolution of the registers is the same as for the
Equation 33 with k = 1, as follows: active power offset registers (see the Active Power Offset
Calibration section).
FQ = V1I1 sin(φ1 – γ1)
The ADE7878 computes the fundamental reactive power using serial ports of the ADE7858/ADE7868/ADE7878 work on 32-,
a proprietary algorithm that requires some initialization function 16-, or 8-bit words and the DSP works on 28 bits. Similar to the
of the frequency of the network and its nominal voltage measured registers presented in Figure 35, the AVAROS, BVAROS, and
in the voltage channel. These initializations are introduced in CVAROS 24-bit signed registers are accessed as 32-bit registers
the Active Power Calculation section and are common for both with the four MSBs padded with 0s and sign extended to 28 bits.
fundamental active and reactive powers.
Sign of Reactive Power Calculation Both total and fundamental reactive energy accumulations are
Note that the reactive power is a signed calculation. Table 18 always a signed operation. Negative energy is subtracted from
summarizes the relationship between the phase difference between the reactive energy contents.
the voltage and the current and the sign of the resulting reactive Similar to active power, the ADE7858/ADE7868/ADE7878
power calculation. achieve the integration of the reactive power signal in two
The ADE7858/ADE7868/ADE7878 have sign detection circuitry stages (see Figure 71). The process is identical for both total and
for reactive power calculations that can monitor the total reactive fundamental reactive powers.
powers or the fundamental reactive powers. As described in the • The first stage is conducted inside the DSP: every 125 µs
Reactive Energy Calculation section, the reactive energy accu- (8 kHz frequency), the instantaneous phase total reactive
mulation is executed in two stages. Every time a sign change is or fundamental power is accumulated into an internal
detected in the energy accumulation at the end of the first stage, register. When a threshold is reached, a pulse is generated
that is, after the energy accumulated into the internal accumulator at the processor port and the threshold is subtracted from
reaches the VARTHR register threshold, a dedicated interrupt is the internal register. The sign of the energy in this moment
triggered. The sign of each phase reactive power can be read in is considered the sign of the reactive power (see the Sign of
the PHSIGN register. Bit 7 (REVRPSEL) in the ACCMODE Reactive Power Calculation section for details).
register sets the type of reactive power being monitored. When • The second stage is performed outside the DSP and consists
REVRPSEL is 0, the default value, the total reactive power is in accumulating the pulses generated by the processor into
monitored. When REVRPSEL is 1, then the fundamental internal 32-bit accumulation registers. The content of these
reactive power is monitored. registers is transferred to the var-hour registers (xVARHR and
Bits[12:10] (REVRPC, REVRPB, and REVRPA, respectively) xFVARHR) when these registers are accessed. AVARHR,
in the STATUS0 register are set when a sign change occurs in BVARHR, CVARHR, AFWATTHR, BFWATTHR, and
the power selected by Bit 7 (REVRPSEL) in the ACCMODE CFWATTHR represent phase fundamental reactive powers.
register. Figure 68 from the Active Energy Calculation section explains
Bits[6:4] (CVARSIGN, BVARSIGN, and AVARSIGN, respectively) this process. The VARTHR 48-bit signed register contains the
in the PHSIGN register are set simultaneously with the REVRPC, threshold and it is introduced by the user. It is common for both
REVRPB, and REVRPA bits. They indicate the sign of the reactive total and fundamental phase reactive powers. Its value depends
power. When they are 0, the reactive power is positive. When on how much energy is assigned to one LSB of var-hour
they are 1, the reactive power is negative. registers. When a derivative of reactive energy (varh) of [10n
Bit REVRPx of the STATUS0 register and Bit xVARSIGN in the varh], where n is an integer, is desired as one LSB of the
PHSIGN register refer to the reactive power of Phase x, the xVARHR register; then, the xVARTHR register can be computed
power type being selected by Bit REVRPSEL in ACCMODE using the following equation:
register. PMAX × f s × 3600 × 10 n
VARTHR =
Setting Bits[12:10] in the MASK0 register enables the REVRPC, VFS × I FS
REVRPB, and REVRPA interrupts, respectively. If enabled, the
where:
IRQ0 pin is set low and the status bit is set to 1 whenever a change
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
of sign occurs. To find the phase that triggered the interrupt,
computed when the ADC inputs are at full scale.
the PHSIGN register is read immediately after reading the
fS = 8 kHz, the frequency with which the DSP computes the
STATUS0 register. Next, the status bit is cleared and the IRQ0 instantaneous power.
pin is set to high by writing to the STATUS0 register with the VFS, IFS are the rms values of phase voltages and currents when
corresponding bit set to 1. the ADC inputs are at full scale.
Table 18. Sign of Reactive Power Calculation The maximum value that may be written on the VARTHR
Φ1 Integrator Sign of Reactive Power register is 247 − 1. The minimum value is 0x0, but it is
Between 0 to +180 Off Positive recommended to write a number equal to or greater than
Between −180 to 0 Off Negative PMAX. Never use negative numbers.
Between 0 to +180 On Positive VARTHR is a 48-bit register. As previously stated in the Voltage
Between −180 to 0 On Negative Waveform Gain Registers section, the serial ports of the ADE7858/
1
Φ is defined as the phase angle of the voltage signal minus the current ADE7868/ADE7878 work on 32-, 16-, or 8-bit words. Similar to
signal; that is, Φ is positive if the load is inductive and negative if the load is
capacitive. the WTHR register shown in Figure 69, VARTHR is accessed as
two 32-bit registers (VARTHR1 and VARTHR0), each having eight
Reactive Energy Calculation
MSBs padded with 0s.
Reactive energy is defined as the integral of reactive power.
Reactive Energy = ∫q(t)dt (36)
This discrete time accumulation or summation is equivalent to Bit 2 (REHF) in the STATUS0 register is set when Bit 30 of
integration in continuous time following the expression in one of the xVARHR registers changes, signifying one of these
Equation 37: registers is half full. If the reactive power is positive, the var-hour
register becomes half full when it increments from 0x3FFF FFFF
∞ 
ReactiveEnergy = ∫ q (t )dt = Lim  ∑ q (nT ) × T  (37) to 0x4000 0000. If the reactive power is negative, the var-hour
T→0 n=0  register becomes half full when it decrements from 0xC000 0000
where: to 0xBFFF FFFF. Analogously, Bit 3 (FREHF) in the STATUS0
n is the discrete time sample number. register is set when Bit 30 of one of the xFVARHR registers
T is the sample period. changes, signifying one of these registers is half full.
On the ADE7858/ADE7868/ADE7878, the total phase reactive Setting Bits[3:2] in the MASK0 register enable the FREHF and
powers are accumulated in the AVARHR, BVARHR, and REHF interrupts, respectively. If enabled, the IRQ0 pin is set
CVARHR 32-bit signed registers. The fundamental phase reactive low and the status bit is set to 1 whenever one of the energy
powers are accumulated in the AFVARHR, BFVARHR, and registers, xVARHR (for REHF interrupt) or xFVARHR (for
CFVARHR 32-bit signed registers. The reactive energy register FREHF interrupt), becomes half full. The status bit is cleared
content can roll over to full-scale negative (0x80000000) and and the IRQ0 pin is set to high by writing to the STATUS0
continue increasing in value when the reactive power is positive. register with the corresponding bit set to 1.
Conversely, if the reactive power is negative, the energy register
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
underflows to full-scale positive (0x7FFFFFFF) and continues
read-with-reset for all var-hour accumulation registers, that is,
to decrease in value.
the registers are reset to 0 after a read operation.
HPFDIS DIGITAL
AVARGAIN REVRPA BIT IN
IA STATUS0[31:0]
AVAROS
HPF
AVARHR[31:0]
HPFDIS TOTAL
APHCAL [23:0] AVGAIN REACTIVE
POWER ACCUMULATOR
ALGORITHM 32-BIT
VA VARTHR[47:0] REGISTER
HPF
AVAR
08510-245
DIGITAL SIGNAL PROCESSOR 24
Figure 71. Total Reactive Energy Accumulation

Integration Time Under A Steady Load In this mode, the ADE7858/ADE7868/ADE7878 transfer the
The discrete time sample period (T) for the accumulation register reactive energy accumulated in the 32-bit internal accumulation
is 125 µs (8 kHz frequency). With full-scale pure sinusoidal signals registers into the xVARHR or xFVARHR registers after an
on the analog inputs and a 90° phase difference between the vol- integral number of line cycles, as shown in Figure 72. The
tage and the current signal (the largest possible reactive power), number of half line cycles is specified in the LINECYC register.
the average word value representing the reactive power is PMAX = The line cycle reactive energy accumulation mode is activated by
33,516,139 = 0x1FF6A6B. If the VARTHR threshold is set at the setting Bit 1 (LVAR) in the LCYCMODE register. The total reactive
PMAX level, this means the DSP generates a pulse that is added energy accumulated over an integer number of half line cycles
at the var-hour registers every 125 µs. or zero crossings is available in the var-hour accumulation registers
The maximum value that can be stored in the var-hour after the number of zero crossings specified in the LINECYC reg-
accumulation register before it overflows is 231 − 1 or ister is detected. When using the line cycle accumulation mode,
0x7FFFFFFF. The integration time is calculated as Bit 6 (RSTREAD) of the LCYCMODE register should be set to
Logic 0 because a read with the reset of var-hour registers is not
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec (38)
available in this mode.
Energy Accumulation Modes ZXSEL[0] IN
LCYCMODE[7:0]
The reactive power accumulated in each var-hour accumulation
32-bit register (AVARHR, BVARHR, CVARHR, AFVARHR, ZERO-
CROSSING
BFVARHR, and CFVARHR) depends on the configuration of DETECTION

(PHASE A)
Bits[5:4] (CONSEL[1:0]) in the ACCMODE register, in correlation ZXSEL[1] IN

LINECYC[15:0]
with the watt-hour registers. The different configurations are LCYCMODE[7:0]
described in Table 19. Note that IA’/IB’/IC’ are the phase-shifted ZERO-
current waveforms. DETECTION CONTROL
(PHASE B)
Table 19. Inputs to Var-Hour Accumulation Registers ZXSEL[2] IN

LCYCMODE[7:0]
AVARHR, BVARHR, CVARHR,
CONSEL[1:0] AFVARHR BFVARHR CFVARHR ZERO-
00 VA × IA’ VB × IB’ VC × IC’ CROSSING

DETECTION
01 VA × IA’ 0 VC × IC’ (PHASE C)
10 VA × IA’ VB × IB’ VC × IC’

AVAROS
VB = −VA − VC
11 VA × IA’ VB × IB’ VC × IC’ AVARGAIN AVARHR[31:0]
OUTPUT
VB = −VA FROM
TOTAL ACCUMULATOR
32-BIT
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine REACTIVE
REGISTER
08510-146
POWER VARTHR[47:0]
how CF frequency output can be a generated function of the total ALGORITHM
and fundamental reactive powers. While the var-hour accumu- Figure 72. Line Cycle Total Reactive Energy Accumulation Mode
lation registers accumulate the reactive power in a signed
format, the frequency output can be generated in either the signed Phase A, Phase B, and Phase C zero crossings are, respectively,
mode or the sign adjusted mode function of VARACC[1:0]. See included when counting the number of half line cycles by setting
the Energy-to-Frequency Conversion section for details. Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
nation of the zero crossings from all three phases can be used
Line Cycle Reactive Energy Accumulation Mode for counting the zero crossing. Select only one phase at a time
As mentioned in the Line Cycle Active Energy Accumulation for inclusion in the zero-crossings count during calibration.
Mode section, in line cycle energy accumulation mode, the
For details on setting the LINECYC register and the Bit 5
energy accumulation can be synchronized to the voltage
(LENERGY) in the MASK0 interrupt mask register associated
channel zero crossings so that reactive energy can be accu-
with the line cycle accumulation mode, see the Line Cycle
mulated over an integral number of half line cycles.
Active Energy Accumulation Mode section.

APPARENT POWER CALCULATION The ADE7854/ADE7858/ADE7868/ADE7878 store the instan-
Apparent power is defined as the maximum power that can be taneous phase apparent powers into the AVA, BVA, and CVA
delivered to a load. One way to obtain the apparent power is by registers. Their expression is
multiplying the voltage rms value by the current rms value (also V I 1
xVA = × × PMAX × 4 (40)
called the arithmetic apparent power) VFS I FS 2
S = V rms × I rms (39) where:
where: V, I are the rms values of the phase voltage and current.
S is the apparent power. VFS, IFS are the rms values of the phase voltage and current when
V rms and I rms are the rms voltage and current, respectively. the ADC inputs are at full scale.
PMAX = 33,516,139, the instantaneous power computed when
The ADE7854/ADE7858/ADE7868/ADE7878 compute the
the ADC inputs are at full scale and in phase.
arithmetic apparent power on each phase. Figure 73 illustrates
the signal processing in each phase for the calculation of the The xVA[23:0] waveform registers may be accessed using
apparent power in the ADE78xx. Because V rms and I rms con- various serial ports. Refer to the Waveform Sampling Mode
tain all harmonic information, the apparent power computed by section for more details.
the ADE78xx is total apparent power. The ADE7878 does not The ADE7854/ADE7858/ADE7868/ADE7878 can compute the
compute fundamental apparent power because it does not measure apparent power in an alternative way by multiplying the phase
the rms values of the fundamental voltages and currents. rms current by an rms voltage introduced externally. See the
Apparent Power Calculation Using VNOM section for details.
AIRMS AVAGAIN
AVAHR[31:0]
ACCUMULATOR
32-BIT REGISTER
AVA VATHR[47:0]
08510-048
AVRMS
24 DIGITAL SIGNAL PROCESSOR
Figure 73. Apparent Power Data Flow and Apparent Energy Accumulation

Apparent Power Gain Calibration As stated in the Current Waveform Gain Registers, the serial
The average apparent power result in each phase can be scaled ports of the ADE78xx work on 32-, 16-, or 8-bit words. Similar
by ±100% by writing to one of the phase’s VAGAIN 24-bit registers to the register presented in Figure 36, the VNOM 24-bit signed
(AVAGAIN, BVAGAIN, or CVAG AIN). The VAGAIN registers register is accessed as a 32-bit register with the eight MSBs
are twos complement, signed registers and have a resolution of padded with 0s.
2−23/LSB. The function of the xVAGAIN registers is expressed Apparent Energy Calculation
mathematically as Apparent energy is defined as the integral of apparent power.
Average Apparent Power = Apparent Energy = ∫s(t)dt (43)
 VAGAIN Register  (41)
V rms × I rms × 1 +  Similar to active and reactive powers, the ADE7854/ADE7858/
 2 23  ADE7868/ADE7878 achieve the integration of the apparent power
The output is scaled by –50% by writing 0xC00000 to the signal in two stages (see Figure 73). The first stage is conducted
xVAGAIN registers, and it is increased by +50% by writing inside the DSP: every 125 µs (8 kHz frequency), the instanta-
0x400000 to them. These registers calibrate the apparent power neous phase apparent power is accumulated into an internal
(or energy) calculation in the ADE7854/ADE7858/ADE7868/ register. When a threshold is reached, a pulse is generated at the
ADE7878 for each phase. processor port and the threshold is subtracted from the internal
register. The second stage is conducted outside the DSP and
As previously stated in the Current Waveform Gain Registers
consists of accumulating the pulses generated by the processor
section, the serial ports of the ADE78xx work on 32-, 16-, or 8-bit
into internal 32-bit accumulation registers. The content of these
words and the DSP works on 28 bits. Similar to registers presented
registers is transferred to the VA-hour registers, xVAHR, when
in Figure 35, the AVAGAIN, BVAGAIN, and CVAGAIN 24-bit
these registers are accessed. Figure 68 from the Active Energy
registers are accessed as 32-bit registers with the four MSBs
Calculation section illustrates this process. The VATHR 48-bit
padded with 0s and sign extended to 28 bits.
register contains the threshold. Its value depends on how much
Apparent Power Offset Calibration energy is assigned to one LSB of the VA-hour registers. When a
Each rms measurement includes an offset compensation register derivative of apparent energy (VAh) of [10n VAh], where n is an
to calibrate and eliminate the dc component in the rms value integer, is desired as one LSB of the xVAHR register; then, the
(see the Root Mean Square Measurement section). The voltage xVATHR register can be computed using the following equation:
and current rms values are multiplied together in the apparent PMAX × f s × 3600 × 10 n
power signal processing. As no additional offsets are created in VATHR =
VFS × I FS
the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The offset where:
compensation of the apparent power measurement in each phase is PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
accomplished by calibrating each individual rms measurement. computed when the ADC inputs are at full scale.
Apparent Power Calculation Using VNOM fS = 8 kHz, the frequency with which the DSP computes the
instantaneous power.
The ADE7854/ADE7858/ADE7868/ADE7878 can compute the
VFS, IFS are the rms values of phase voltages and currents when
apparent power by multiplying the phase rms current by an rms
voltage introduced externally in the VNOM 24-bit signed register.
VATHR is a 48-bit register. As previously stated in the Current
When one of Bits[13:11] (VNOMCEN, VNOMBEN, or
Waveform Gain Registers section, the serial ports of the ADE7854/
VNOMAEN) in the COMPMODE register is set to 1, the
ADE7858/ADE7868/ADE7878 work on 32-, 16-, or 8-bit words.
apparent power in the corresponding phase (Phase x for
Similar to the WTHR register presented in Figure 69, the VATHR
VNOMxEN) is computed in this way. When the VNOMxEN
register is accessed as two 32-bit registers (VATHR1 and VATHR0),
bits are cleared to 0, the default value, then the arithmetic
each having eight MSBs padded with 0s.
apparent power is computed.
This discrete time accumulation or summation is equivalent to
The VNOM register contains a number determined by V, the
integration in continuous time following the description in
desired rms voltage, and VFS, the rms value of the phase voltage
Equation 44.
when the ADC inputs are at full scale:
∞ 
V ApparentEnergy = ∫ s (t )dt = Lim  ∑ s (nT ) × T  (44)
VNOM = × 4,191,910 (42) T→0 n =0 
VFS
where:
where V is the desired nominal phase rms voltage.
n is the discrete time sample number.
T is the sample period.

In the ADE7854/ADE7858/ADE7868/ADE7878, the phase The maximum value that can be stored in the xVAHR
apparent powers are accumulated in the AVAHR, BVAHR, and accumulation register before it overflows is 231 − 1 or
CVAHR 32-bit signed registers. The apparent energy register 0x7FFFFFFF. The integration time is calculated as
content can roll over to full-scale negative (0x80000000) and Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec (45)
continue increasing in value when the apparent power is
positive. Energy Accumulation Mode
The apparent power accumulated in each accumulation register
Bit 4 (VAEHF) in the STATUS0 register is set when Bit 30 of one of
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
the xVAHR registers changes, signifying one of these registers is
ACCMODE register. The various configurations are described
half full. As the apparent power is always positive and the xVAHR
in Table 20.
registers are signed, the VA-hour registers become half full when
they increment from 0x3FFFFFFF to 0x4000 0000. Interrupts Table 20. Inputs to VA-Hour Accumulation Registers
attached to Bit VAEHF in the STATUS0 register can be enabled by CONSEL[1:0] AVAHR BVAHR CVAHR
setting Bit 4 in the MASK0 register. If enabled, the IRQ0 pin is set 00 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
low and the status bit is set to 1 whenever one of the Energy 01 AVRMS × AIRMS 0 CVRMS × CIRMS
Registers xVAHR becomes half full. The status bit is cleared and 10 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
VB = −VA − VC
the IRQ0 pin is set to high by writing to the STATUS0 register
11 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
with the corresponding bit set to 1.
VB = −VA
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables Line Cycle Apparent Energy Accumulation Mode
a read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation. As described in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
Integration Time Under Steady Load energy accumulation can be synchronized to the voltage channel
The discrete time sample period for the accumulation register is zero crossings allowing apparent energy to be accumulated over an
125 μs (8 kHz frequency). With full-scale pure sinusoidal signals integral number of half line cycles. In this mode, the ADE7854/
on the analog inputs, the average word value representing the ADE7858/ADE7868/ADE7878transfer the apparent energy
apparent power is PMAX. If the VATHR threshold register is set accumulated in the 32-bit internal accumulation registers into
at the PMAX level, this means the DSP generates a pulse that the xVAHR registers after an integral number of line cycles, as
is added at the xVAHR registers every 125 μs. shown in Figure 74. The number of half line cycles is specified
in the LINECYC register.
ZXSEL[0] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN LINECYC[15:0]
LCYCMODE[7:0]
ZERO-
DETECTION CONTROL
(PHASE B)
ZXSEL[2] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE C)
AIRMS AVAGAIN
AVAHR[31:0]
ACCUMULATOR
32-BIT
REGISTER
08510-049
VAHR[47:0]
AVRMS
Figure 74. Line Cycle Apparent Energy Accumulation Mode

The line cycle apparent energy accumulation mode is activated The ADE7854/ADE7858/ADE7868/ADE7878 contain a high
by setting Bit 2 (LVA) in the LCYCMODE register. The apparent speed data capture (HSDC) port that is specially designed to
energy accumulated over an integer number of zero crossings is provide fast access to the waveform sample registers. Read the
written to the xVAHR accumulation registers after the number HSDC Interface section for more details.
of zero crossings specified in LINECYC register is detected. When As stated in the Current Waveform Gain Registers section, the
using the line cycle accumulation mode, set Bit 6 (RSTREAD) of serial ports of the ADE7854/ADE7858/ADE7868/ADE7878
the LCYCMODE register to Logic 0 because a read with the reset work on 32-, 16-, or 8-bit words. All registers listed in Table 21
of xVAHR registers is not available in this mode. are transmitted signed extended from 24 bits to 32 bits (see
Phase A, Phase B, and Phase C zero crossings are, respectively, Figure 37).
included when counting the number of half line cycles by setting
ENERGY-TO-FREQUENCY CONVERSION
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
nation of the zero crossings from all three phases can be used The ADE7854/ADE7858/ADE7868/ADE7878 provide three
for counting the zero crossing. Select only one phase at a time frequency output pins: CF1, CF2, and CF3. The CF3 pin is
for inclusion in the zero-crossings count during calibration. multiplexed with the HSCLK pin of the HSDC interface. When
HSDC is enabled, the CF3 functionality is disabled at the pin.
For details on setting the LINECYC register and Bit 5 (LENERGY) CF1 and CF2 pins are always available. After initial calibration
in the MASK0 interrupt mask register associated with the line at manufacturing, the manufacturer or end customer verifies
cycle accumulation mode, see the Line Cycle Active Energy the energy meter calibration. One convenient way to verify the
Accumulation Mode section. meter calibration is to provide an output frequency propor-
WAVEFORM SAMPLING MODE tional to the active, reactive, or apparent powers under steady
The waveform samples of the current and voltage waveform, load conditions. This output frequency can provide a simple,
the active, reactive, and apparent power outputs are stored single-wire, optically isolated interface to external calibration
every 125 µs (8 kHz rate) into 24-bit signed registers that can be equipment. Figure 75 illustrates the energy-to-frequency
accessed through various serial ports of the ADE7854/ADE7858/ conversion in the ADE7854/ADE7858/ADE7868/ADE7878.
ADE7868/ADE7878. Table 21 provides a list of registers and their The DSP computes the instantaneous values of all phase powers:
descriptions. total active, fundamental active, total reactive, fundamental
reactive, and apparent. The process in which the energy is sign
Table 21. Waveform Registers List accumulated in various xWATTHR, xVARHR, and xVAHR
Register Description registers has already been described in the energy calculation
IAWV Phase A current sections: Active Energy Calculation, Reactive Energy Calculation,
VAWV Phase A voltage and Apparent Energy Calculation. In the energy-to-frequency
IBWV Phase B current conversion process, the instantaneous powers generate signals
VBWV Phase B voltage at the frequency output pins (CF1, CF2, and CF3). One digital-
ICWV Phase C current to-frequency converter is used for every CFx pin. Every converter
VCWV Phase C voltage sums certain phase powers and generates a signal proportional
INWV Neutral current, available in the ADE7868 to the sum. Two sets of bits decide what powers are converted.
and ADE7878 only
AVA Phase A apparent power First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
BVA Phase B apparent power and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
CVA Phase C apparent power decide which phases, or which combination of phases, are added.
AWATT Phase A active power The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits
BWATT Phase B active power refer to the CF2 pin, and the TERMSEL3 bits refer to the CF3
CWATT Phase C active power pin. The TERMSELx[0] bits manage Phase A. When set to 1,
AVAR Phase A reactive power Phase A power is included in the sum of powers at the CFx
BVAR Phase B reactive power converter. When cleared to 0, Phase A power is not included.
CVAR Phase C reactive power The TERMSELx[1] bits manage Phase B, and the TERMSELx[2]
Bit 17 (DREADY) in the STATUS0 register can be used to bits manage Phase C. Setting all TERMSELx bits to 1 means all
signal when the registers listed in Table 21 can be read using 3-phase powers are added at the CFx converter. Clearing all
I2C or SPI serial ports. An interrupt attached to the flag can be TERMSELx bits to 0 means no phase power is added and no
enabled by setting Bit 17 (DREADY) in the MASK0 register. CF pulse is generated.
See the Digital Signal Processor section for more details on
Bit DREADY.

Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and Table 22. CFxSEL Bits Description
Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what Registers
type of power is used at the inputs of the CF1, CF2, and CF3 Latched When
converters, respectively. Table 22 shows the values that CFxSEL CFxSEL Description CFxLATCH = 1
can have: total active, total reactive (available in the ADE7858, 000 CFx signal proportional to the AWATTHR,
ADE7868, and ADE7878 only), apparent, fundamental active sum of total phase active BWATTHR,
powers CWATTHR
(available in the ADE7878 only), or fundamental reactive
001 CFx signal proportional to the AVARHR, BVARHR,
(available in the ADE7878 only) powers. sum of total phase reactive CVARHR
powers (ADE7858/ADE7868/
ADE7878)
010 CFx signal proportional to the AVAHR, BVAHR,
sum of phase apparent powers CVAHR
011 CFx signal proportional to the AFWATTHR,
sum of fundamental phase BFWATTHR,
active powers (ADE7878 only) CFWATTHR
100 CFx signal proportional to the AFVARHR,
sum of fundamental phase BFVARHR,
reactive powers (ADE7878 only) CFVARHR
101 to Reserved
111
CFxSEL BITS
IN CFMODE
INSTANTANEOUS
PHASE A ACTIVE
POWER TERMSELx BITS IN 27
COMPMODE VA
REVPSUMx BIT OF
INSTANTANEOUS WATT STATUS0[31:0]
PHASE B ACTIVE ACCUMULATOR
POWER VAR FREQUENCY CFx PULSE
DIVIDER OUTPUT
INSTANTANEOUS FWATT1
WTHR[47:0]
PHASE C ACTIVE
POWER FVAR1
CFxDEN
DIGITAL SIGNAL 27
PROCESSOR
08510-050
1FWATT AND FVAR FOR ADE7878 ONLY.
Figure 75. Energy-to-Frequency Conversion

By default, the TERMSELx bits are all 1 and the CF1SEL bits are The pulse output is active low and preferably connected to an
000, the CF2SEL bits are 001, and the CF3SEL bits are 010. This LED, as shown in Figure 76.
means that by default, the CF1 digital-to-frequency converter VDD
produces signals proportional to the sum of all 3-phase total

active powers, CF2 produces signals proportional to total CFx PIN
reactive powers, and CF3 produces signals proportional to
apparent powers.
08510-051
Similar to the energy accumulation process, the energy-to-
frequency conversion is accomplished in two stages. In the first Figure 76. CFx Pin Recommended Connection
stage, the instantaneous phase powers obtained from the DSP at
the 8 kHz rate are shifted left by seven bits and then accumulate Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE
into an internal register at a 1 MHz rate. When a threshold is register decide if the frequency converter output is generated
reached, a pulse is generated and the threshold is subtracted at the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the
from the internal register. The sign of the energy in this moment default value), the CFx pin is disabled and the pin stays high.
is considered the sign of the sum of phase powers (see the Sign When Bit CFxDIS is cleared to 0, the corresponding CFx pin
of Sum-of-Phase Powers in the CFx Datapath section for details). output generates an active low signal.
The threshold is the same threshold used in various active, Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask Register MASK0
reactive, and apparent energy accumulators in the DSP, such manage the CF3, CF2, and CF1 related interrupts. When the
as the WTHR, VARTHR, or VATHR registers, except for being CFx bits are set, whenever a high-to-low transition at the corres-
shifted left by seven bits. The advantage of accumulating the ponding frequency converter output occurs, an interrupt IRQ0
instantaneous powers at the 1 MHz rate is that the ripple at the is triggered and a status bit in the STATUS0 register is set to 1.
CFx pins is greatly diminished. The interrupt is available even if the CFx output is not enabled
The second stage consists of the frequency divider by the by the CFxDIS bits in the CFMODE register.
CFxDEN 16-bit unsigned registers. The values of CFxDEN Synchronizing Energy Registers with CFx Outputs
depend on the meter constant (MC), measured in impulses/kWh The ADE7854/ADE7858/ADE7868/ADE7878 contain a feature
and how much energy is assigned to one LSB of various energy that allows synchronizing the content of phase energy accu-
registers: xWATTHR, xVARHR, and so forth. Supposing a deri- mulation registers with the generation of a CFx pulse. When
vative of wh [10n wh], n a positive or negative integer, is desired a high-to-low transition at one frequency converter output
as one LSB of xWATTHR register. Then, CFxDEN is as follows: occurs, the content of all internal phase energy registers that
103 relate to the power being output at CFx pin is latched into hour
CFxDEN = (46) registers and then resets to 0. See Table 22 for the list of registers
MC[imp/kwh] × 10n
that are latched based on the CFxSEL[2:0] bits in the CFMODE
The derivative of wh must be chosen in such a way to obtain a register. All 3-phase registers are latched independent of the
CFxDEN register content greater than 1. If CFxDEN = 1, then TERMSELx bits of the COMPMODE register. The process is
the CFx pin stays active low for only 1 µs, therefore, avoid this shown in Figure 77 for CF1SEL[2:0] = 010 (apparent powers
number. The frequency converter cannot accommodate fractional contribute at the CF1 pin) and CFCYC = 2.
results; the result of the division must be rounded to the nearest
The CFCYC 8-bit unsigned register contains the number of high to
integer. If CFxDEN is set equal to 0, then the ADE78xx considers it
low transitions at the frequency converter output between two
to be equal to 1.
consecutive latches. Avoid writing a new value into the CFCYC
The pulse output for all digital-to-frequency converters stays register during a high-to-low transition at any CFx pin.
low for 80 ms if the pulse period is larger than 160 ms (6.25 Hz). If CF1 PULSE
the pulse period is smaller than 160 ms and CFxDEN is an even BASED ON
PHASE A AND
number, the duty cycle of the pulse output is exactly 50%. If the PHASE B
APPARENT CFCYC = 2
pulse period is smaller than 160 ms and CFxDEN is an odd POWERS
AVAHR, BVAHR, AVAHR, BVAHR,
number, the duty cycle of the pulse output is CVAHR LATCHED CVAHR LATCHED
08510-052
ENERGY REGISTERS ENERGY REGISTERS

(1+1/CFxDEN) × 50% RESET RESET
Figure 77. Synchronizing AVAHR and BVAHR with CF1
Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the

CFMODE register enable this process when set to 1. When
cleared to 0, the default state, no latch occurs. The process is
available even if the CFx output is not enabled by the CFxDIS
bits in the CFMODE register.
CF Outputs for Various Accumulation Modes
Bits[1:0] (WATTACC[1:0]) in the ACCMODE register deter-
mine the accumulation modes of the total active and fundamental
powers when signals proportional to the active powers are chosen
at the CFx pins (the CFxSEL[2:0] bits in the CFMODE register
equal 000 or 011). When WATTACC[1:0] = 00 (the default value), ACTIVE ENERGY
the active powers are sign accumulated before entering the energy-
to-frequency converter. Figure 78 shows how signed active power
accumulation works. In this mode, the CFx pulses synchronize NO-LOAD
THRESHOLD
perfectly with the active energy accumulated in xWATTHR regis-
ters because the powers are sign accumulated in both data paths. ACTIVE POWER
NO-LOAD
THRESHOLD
REVAPx BIT
ACTIVE ENERGY IN STATUS0
xWSIGN BIT
IN PHSIGN
08510-054
NO-LOAD APNOLOAD POS NEG POS NEG
THRESHOLD SIGN = POSITIVE
Figure 79. Active Power Absolute Accumulation Mode

ACTIVE POWER
NO-LOAD
THRESHOLD
REVAPx BIT REACTIVE

IN STATUS0 ENERGY
xWSIGN BIT
IN PHSIGN
NO-LOAD
08510-053
APNOLOAD POS NEG POS NEG THRESHOLD

SIGN = POSITIVE
Figure 78. Active Power Signed Accumulation Mode REACTIVE

POWER
When WATTACC[1:0] = 11, the active powers are accumulated NO-LOAD
THRESHOLD
in absolute mode. When the powers are negative, they change
sign and accumulate together with the positive power. Figure 79 REVRPx BIT
IN STATUS0
shows how absolute active power accumulation works. Note
xVARSIGN BIT
that in this mode, the xWATTHR registers continue to accumulate IN PHSIGN
active powers in signed mode, even if the CFx pulses are gener-
08510-153
POS NEG POS NEG
ated based on the absolute accumulation mode. VARNOLOAD
SIGN = POSITIVE
WATTACC[1:0] settings of 01 and 10 are reserved. The Figure 80. Reactive Power Signed Accumulation Mode
ADE7854/ADE7858/ADE7868/ADE7878 behave identically to
When VARACC[1:0] = 10, the reactive powers are accumulated
the case when WATTACC[1:0] = 00.
depending on the sign of the corresponding active power. If the
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine the active power is positive, the reactive power is accumulated as is.
accumulation modes of the total and fundamental reactive powers If the active power is negative, the sign of the reactive power is
when signals proportional to the reactive powers are chosen at the changed for accumulation. Figure 81 shows how the sign adjusted
CFx pins (the CFxSEL[2:0] bits in the CFMODE register equal reactive power accumulation mode works. In this mode, the
001 or 100). When VARACC[1:0] = 00, the default value, the xVARHR registers continue to accumulate reactive powers in
reactive powers are sign accumulated before entering the signed mode, even if the CFx pulses are generated based on the
energy-to-frequency converter. Figure 80 shows how signed sign adjusted accumulation mode.
reactive power accumulation works. In this mode, the CFx
VARACC[1:0] settings of 01 and 11 are reserved. The
pulses synchronize perfectly with the reactive energy accumu-
ADE7854/ADE7858/ADE7868/ADE7878 behave identically to
lated in the xVARHR registers because the powers are sign
the case when VARACC[1:0] = 00.
accumulated in both datapaths.

NO LOAD CONDITION
The no load condition is defined in metering equipment standards
REACTIVE
ENERGY as occurring when the voltage is applied to the meter and no cur-
rent flows in the current circuit. To eliminate any creep effects in
NO-LOAD
THRESHOLD the meter, the ADE7854/ADE7858/ADE7868/ADE7878contain
REACTIVE
POWER
three separate no load detection circuits: one related to the total
NO-LOAD active and reactive powers (ADE7858/ADE7868/ADE7878
THRESHOLD
only), one related to the fundamental active and reactive powers
NO-LOAD (ADE7878 only), and one related to the apparent powers.
THRESHOLD
ACTIVE No Load Detection Based On Total Active, Reactive
POWER
Powers
REVRPx BIT This no load condition is triggered when the absolute values of
IN STATUS0
both phase total active and reactive powers are less than or equal
xVARSIGN BIT
IN PHSIGN 08510-155 to positive thresholds indicated in the respective APNOLOAD
VARNOLOAD POS NEG POS and VARNOLOAD signed 24-bit registers. In this case, the total
SIGN = POSITIVE
active and reactive energies of that phase are not accumulated
Figure 81. Reactive Power Accumulation in Sign Adjusted Mode and no CFx pulses are generated based on these energies. The
Sign of Sum-of-Phase Powers in the CFx Datapath APNOLOAD register represents the positive no load level of
The ADE7854/ADE7858/ADE7868/ADE7878 have sign active power relative to PMAX, the maximum active power
detection circuitry for the sum of phase powers that are used in obtained when full-scale voltages and currents are provided at
the CFx datapath. As seen in the beginning of the Energy-to- ADC inputs. The VARNOLOAD register represents the positive
Frequency Conversion section, the energy accumulation in the no load level of reactive power relative to PMAX. The expres-
CFx datapath is executed in two stages. Every time a sign change is sion used to compute APNOLOAD signed 24-bit value is
detected in the energy accumulation at the end of the first stage, Vn I NOLOAD
APNOLOAD = × × PMAX (47)
that is, after the energy accumulated into the accumulator VFS I FS
reaches one of the WTHR, VARTHR, or VATHR thresholds, a
dedicated interrupt can be triggered synchronously with the where:
corresponding CFx pulse. The sign of each sum can be read in PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
the PHSIGN register. computed when the ADC inputs are at full scale.
Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and the ADC inputs are at full scale.
REVPSUM1, respectively) of the STATUS0 register are set Vn is the nominal rms value of phase voltage.
to 1 when a sign change of the sum of powers in CF3, CF2, INOLOAD is the minimum rms value of phase current the meter
or CF1 datapaths occurs. To correlate these events with the starts measuring.
pulses generated at the CFx pins, after a sign change occurs,
Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 are set The VARNOLOAD register usually contains the same value as
in the same moment in which a high-to-low transition at the the APNOLOAD register. When APNOLOAD and VARNOLOAD
CF3, CF2, and CF1 pin, respectively, occurs. are set to negative values, the no load detection circuit is disabled.
Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and SUM1SIGN, Note that the ADE7854 measures only the total active powers.
respectively) of the PHSIGN register are set in the same moment To ensure good functionality of the ADE7854 no-load circuit,
with Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 and set the VARNOLOAD register at 0x800000.
indicate the sign of the sum of phase powers. When cleared to As previously stated in the Current Waveform Gain Registers
0, the sum is positive. When set to 1, the sum is negative. section, the serial ports of the ADE78xx work on 32-, 16-, or
Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3, 8-bit words and the DSP works on 28 bits. APNOLOAD and
REVPSUM2, and REVPSUM1, respectively) in the STATUS0 VARNOLOAD 24-bit signed registers are accessed as 32-bit
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the registers with the four MSBs padded with 0s and sign extended
to 28 bits. See Figure 35 for details.
MASK0 register. If enabled, the IRQ0 pin is set low, and the
status bit is set to 1 whenever a change of sign occurs. To find Bit 0 (NLOAD) in the STATUS1 register is set when this no
the phase that triggered the interrupt, the PHSIGN register is load condition in one of the three phases is triggered. Bits[2:0]
read immediately after reading the STATUS0 register. Next, the (NLPHASE[2:0]) in the PHNOLOAD register indicate the state
status bit is cleared, and the IRQ0 pin is set high again by writing of all phases relative to a no load condition and are set simulta-
to the STATUS0 register with the corresponding bit set to 1. neously with Bit NLOAD in the STATUS1 register. NLPHASE[0]
indicates the state of Phase A, NLPHASE[1] indicates the state

of Phase B, and NLPHASE[2] indicates the state of Phase C. power obtained when full-scale voltages and currents are
When Bit NLPHASE[x] is cleared to 0, it means the phase is out provided at the ADC inputs. The expression used to compute
of a no load condition. When set to 1, it means the phase is in a the VANOLOAD signed 24-bit value is
no load condition. Vn I NOLOAD
VANOLOAD = × × PMAX (48)
An interrupt attached to Bit 0 (NLOAD) in the STATUS1 VFS I FS
register can be enabled by setting Bit 0 in the MASK1 register.
where:
If enabled, the IRQ1 pin is set to low, and the status bit is set
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous apparent
to 1 whenever one of three phases enters or exits this no load
power computed when the ADC inputs are at full scale.
condition. To find the phase that triggered the interrupt, the
PHNOLOAD register is read immediately after reading the
STATUS1 register. Next, the status bit is cleared, and the IRQ1
Vn is the nominal rms value of phase voltage.
pin is set to high by writing to the STATUS1 register with the
INOLOAD is the minimum rms value of phase current the meter
corresponding bit set to 1.
starts measuring.
No Load Detection Based on Fundamental Active and
When the VANOLOAD register is set to negative values, the no
Reactive Powers—ADE7878 Only
load detection circuit is disabled.
This no load condition (available on the ADE7878 only) is
triggered when the absolute values of both phase fundamental
serial ports of the ADE7854/ADE7858/ADE7868/ADE7878
active and reactive powers are less than or equal to the respective
work on 32-, 16-, or 8-bit words and the DSP works on 28 bits.
APNOLOAD and VARNOLOAD positive thresholds. In this
Similar to the registers presented in Figure 35, the VANOLOAD
case, the fundamental active and reactive energies of that phase
24-bit signed register is accessed as a 32-bit register with the
are not accumulated, and no CFx pulses are generated based on
four MSBs padded with 0s and sign extended to 28 bits.
these energies. APNOLOAD and VARNOLOAD are the same
no load thresholds set for the total active and reactive powers. Bit 2 (VANLOAD) in the STATUS1 register is set when this no
When APNOLOAD and VARNOLOAD are set to negative load condition in one of the three phases is triggered. Bits[8:6]
values, this no load detection circuit is disabled. (VANLPHASE[2:0]) in the PHNOLOAD register indicate the
state of all phases relative to a no load condition and they are set
Bit 1 (FNLOAD) in the STATUS1 register is set when this no
simultaneously with Bit VANLOAD in the STATUS1 register:
load condition in one of the three phases is triggered. Bits[5:3]
(FNLPHASE[2:0]) in the PHNOLOAD register indicate the • Bit VANLPHASE[0] indicates the state of Phase A.
state of all phases relative to a no load condition and are set • Bit VANLPHASE[1] indicates the state of Phase B.
simultaneously with Bit FNLOAD in the STATUS1 register. • Bit VANLPHASE[2] indicates the state of Phase C.
FNLPHASE[0] indicates the state of Phase A, FNLPHASE[1]
indicates the state of Phase B, and FNLPHASE[2] indicates the When Bit VANLPHASE[x] is cleared to 0, it means the phase is
state of Phase C. When Bit FNLPHASE[x] is cleared to 0, it out of no load condition. When set to 1, it means the phase is in
means the phase is out of the no load condition. When set to 1, no load condition.
it means the phase is in a no load condition. An interrupt attached to Bit 2 (VANLOAD) in the STATUS1
An interrupt attached to the Bit 1 (FNLOAD) in the STATUS1 register is enabled by setting Bit 2 in the MASK1 register. If
register can be enabled by setting Bit 1 in the MASK1 register. If enabled, the IRQ1 pin is set low and the status bit is set to 1
enabled, the IRQ1 pin is set low and the status bit is set to 1 whenever one of three phases enters or exits this no load
whenever one of three phases enters or exits this no load condition. To find the phase that triggered the interrupt, the
condition. To find the phase that triggered the interrupt, the PHNOLOAD register is read immediately after reading the
PHNOLOAD register is read immediately after reading the STATUS1 register. Next, the status bit is cleared, and the IRQ1
STATUS1 register. Then the status bit is cleared and the IRQ1 pin is set to high by writing to the STATUS1 register with the
pin is set back high by writing to the STATUS1 register with the corresponding bit set to 1.
corresponding bit set to 1. CHECKSUM REGISTER
No Load Detection Based on Apparent Power The ADE7854/ADE7858/ADE7868/ADE7878 have a checksum
This no load condition is triggered when the absolute value 32-bit register, CHECKSUM, that ensures certain very important
of phase apparent power is less than or equal to the threshold configuration registers maintain their desired value during
indicated in the VANOLOAD 24-bit signed register. In this Normal Power Mode PSM0.
case, the apparent energy of that phase is not accumulated The registers covered by this register are MASK0, MASK1,
and no CFx pulses are generated based on this energy. The COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
VANOLOAD register represents the positive no load level CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
of apparent power relative to PMAX, the maximum apparent and another six 8-bit reserved internal registers that always have
default values. The ADE78xx computes the cyclic redundancy gi, i = 0, 1, 2, …, 31 are the coefficients of the generating
check (CRC) based on the IEEE802.3 standard. The registers polynomial defined by the IEEE802.3 standard as follows:
are introduced one-by-one into a linear feedback shift register G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 +
(LFSR) based generator starting with the least significant bit (as x5 + x4 + x2 + x + 1 (49)
shown in Figure 82). The 32-bit result is written in the
CHECKSUM register. After power-up or a hardware/software g0 = g1 = g2 = g4 = g5 = g7 = 1
reset, the CRC is computed on the default values of the registers g8 = g10 = g11 = g12 = g16 = g22 =g23= g26 = 1 (50)
giving the results presented in the Table 23. All of the other gi coefficients are equal to 0.
Table 23. Default Values of CHECKSUM and of Internal FB(j) = aj – 1 XOR b31(j – 1) (51)
Registers CRC b0(j) = FB(j) AND g0 (52)
Default Value of CRC of Internal
bi(j) = FB(j) AND gi XOR bi − 1(j – 1), i = 1, 2, 3, ..., 31 (53)
Part No. CHECKSUM Registers
ADE7854 0x44C48F8 0x391FBDDD Equation 51, Equation 52, and Equation 53 must be repeated for
ADE7858 0xD6744F93 0x3E7D0FC1 j = 1, 2, …, 256. The value written into the CHECKSUM register
ADE7868 0x93D774E6 0x23F7C7B1 contains the Bit bi(256), i = 0, 1, …, 31. The value of the CRC,
ADE7878 0x33666787 0x2D32A389 after the bits from the reserved internal register have passed
through LFSR, is obtained at Step j = 48 and is presented in the
Figure 83 shows how the LFSR works. The MASK0, MASK1,
Table 23.
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG Two different approaches can be followed in using the CHECK-
registers, and the six 8-bit reserved internal registers form the SUM register. One is to compute the CRC based on the relations
bits [a255, a254,…, a0] used by LFSR. Bit a0 is the least significant (47) to (53) and then compare the value against the CHECKSUM
bit of the first internal register to enter LFSR; Bit a255 is the most register. Another is to periodically read the CHECKSUM register.
significant bit of the MASK0 register, the last register to enter If two consecutive readings differ, it can be assumed that one of
LFSR. The formulas that govern LFSR are as follows: the registers has changed value and therefore, the ADE7854,
ADE7858, ADE7868, or ADE7878 has changed configuration.
bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form
The recommended response is to initiate a hardware/software
the CRC. Bit b0 is the least significant bit, and Bit b31 is the most
reset that sets the values of all registers to the default, including
significant.
the reserved ones, and then reinitialize the configuration registers.
7 0 7 0 7 0 7 0 7 0 7 0
31 0 31 0 15 0 15 0 15 0
INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL INTERNAL
MASK0 MASK1 COMPMODE GAIN CFMODE
REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER
255 248 240 232 224 216
40 32 24 16 8 7 0
08510-055
LFSR
GENERATOR
Figure 82. CHECKSUM Register Calculation
g0 g1 g2 g3 g31
FB
b0 b1 b2 b31
LFSR
08510-056
a255, a254,....,a2, a1, a0
Figure 83. LFSR Generator Used in CHECKSUM Register Calculation
INTERRUPTS 1. To disable it, the bit must be cleared to 0. Two 32-bit status
The ADE7854/ADE7858/ADE7868/ADE7878 have two interrupt registers, STATUS0 and STATUS1, are associated with the inter-
rupts. When an interrupt event occurs in the ADE78xx, the
pins, IRQ0 and IRQ1. Each of the pins is managed by a 32-bit
corresponding flag in the interrupt status register is set to a Logic 1
interrupt mask register, MASK0 and MASK1, respectively. To
(see Table 37 and Table 38). If the mask bit for this interrupt in
enable an interrupt, a bit in the MASKx register must be set to
the interrupt mask register is Logic 1, then the IRQx logic output
goes active low. The flag bits in the interrupt status register are set When the STATUSx register is read and one of these bits is set
irrespective of the state of the mask bits. To determine the source to 1, the status register associated with the bit is immediately
of the interrupt, the MCU should perform a read of the corres- read to identify the phase that triggered the interrupt and only
ponding STATUSx register and identify which bit is set to 1. To at that time can the STATUSx register be written back with the bit
erase the flag in the status register, write back to the STATUSx set to 1.
register with the flag set to 1. After an interrupt pin goes low, the Using the Interrupts with an MCU
status register is read and the source of the interrupt is identified.
Figure 84 shows a timing diagram that illustrates a suggested
Then, the status register is written back without any change to
implementation of the ADE7854/ADE7858/ADE7868/ADE7878
clear the status flag to 0. The IRQx pin remains low until the
interrupt management using an MCU. At Time t1, the IRQx pin
status flag is cancelled.
goes active low indicating that one or more interrupt events
By default, all interrupts are disabled. However, the RSTDONE have occurred in the ADE78xx, at which point the following
interrupt is an exception. This interrupt can never be masked steps should be taken:
(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1
1. Tie the IRQx pin to a negative-edge-triggered external
register does not have any functionality. The IRQ1 pin always
interrupt on the MCU.
goes low, and Bit 15 (RSTDONE) in the STATUS1 register is set
2. On detection of the negative edge, configure the MCU to
to 1 whenever a power-up or a hardware/software reset process
start executing its interrupt service routine (ISR).
ends. To cancel the status flag, the STATUS1 register has to be
3. On entering the ISR, disable all interrupts using the global
written with Bit 15 (RSTDONE) set to 1.
interrupt mask bit. At this point, the MCU external interrupt
Certain interrupts are used in conjunction with other status flag can be cleared to capture interrupt events that occur
registers. The following bits in the MASK1 register work in during the current ISR.
conjunction with the status bits in the PHNOLOAD register: 4. When the MCU interrupt flag is cleared, a read from
• Bit 0 (NLOAD) STATUSx, the interrupt status register, is carried out. The
• Bit1 (FNLOAD), available in the ADE7878 only interrupt status register content is used to determine the
• Bit 2 (VANLOAD) source of the interrupt(s) and, hence, the appropriate
action to be taken.
The following bits in the MASK1 register work with the status bits 5. The same STATUSx content is written back into the
in the PHSTATUS register: ADE78xx to clear the status flag(s) and reset the IRQx line
• Bit 16, (SAG) to logic high (t2).
• Bit 17 (OI) If a subsequent interrupt event occurs during the ISR (t3), that
• Bit 18 (OV) event is recorded by the MCU external interrupt flag being set
The following bits in the MASK1 register work with the status bits again.
in the IPEAK and VPEAK registers, respectively: On returning from the ISR, the global interrupt mask bit is
• Bit 23 (PKI) cleared (same instruction cycle) and the external interrupt flag
• Bit 24 (PKV) uses the MCU to jump to its ISR once again. This ensures that
the MCU does not miss any external interrupts.
The following bits in the MASK0 register work with the status bits Figure 85 shows a recommended timing diagram when the
in the PHSIGN register: status bits in the STATUSx registers work in conjunction with
• Bits[6:8] (REVAPx) bits in other registers. When the IRQx pin goes active low, the
• Bits[10:12] (REVRPx), available in the ADE7858, STATUSx register is read, and if one of these bits is 1, a second
ADE7868, and ADE7878 only
• Bit 9, Bit 13, and Bit 18 (REVPSUMx)

MCU
INTERRUPT
t1 t2 t3 FLAG SET
IRQx
GLOBAL WRITE ISR RETURN
08510-057
PROGRAM JUMP CLEAR MCU READ ISR ACTION JUMP
TO ISR INTERRUPT INTERRUPT STATUSx BACK GLOBAL INTERRUPT
SEQUENCE STATUSx (BASED ON STATUSx CONTENTS) TO ISR
MASK FLAG MASK RESET
Figure 84. Interrupt Management
MCU
INTERRUPT
t1 t2 t3 FLAG SET
IRQx
08510-058
PROGRAM JUMP GLOBAL CLEAR MCU READ WRITE ISR RETURN
READ BACK ISR ACTION JUMP
TO ISR INTERRUPT INTERRUPT STATUSx PHx (BASED ON STATUSx CONTENTS) GLOBAL INTERRUPT TO ISR
SEQUENCE MASK STATUSx MASK RESET
FLAG
Figure 85. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved
status register is read immediately to identify the phase that After the serial port choice is completed, it needs to be locked.
triggered the interrupt. The name, PHx, in Figure 85 denotes Consequently, the active port remains in use until a hardware
one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers. reset is executed in PSM0 normal mode or until a power-down.
Then, STATUSx is written back to clear the status flag(s). If I2C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2
register must be set to 1 to lock it in. From this moment, the
SERIAL INTERFACES
ADE7854/ADE7858/ADE7868/ADE7878 ignore spurious
The ADE7854/ADE7858/ADE7868/ADE7878 have three serial toggling of the SS pin and an eventual switch into using the SPI
port interfaces: one fully licensed I2C interface, one serial port is no longer possible. If the SPI is the active serial port, any
peripheral interface (SPI), and one high speed data capture port write to the CONFIG2 register locks the port. From this moment,
(HSDC). As the SPI pins are multiplexed with some of the pins a switch into using the I2C port is no longer possible. Once locked,
of the I2C and HSDC ports, the ADE78xx accepts two confi- the serial port choice is maintained when the ADE78xx changes
gurations: one using the SPI port only and one using the I2C PSMx power modes.
port in conjunction with the HSDC port.
The functionality of the ADE78xx is accessible via several on-
Serial Interface Choice chip registers. The contents of these registers can be updated or
After reset, the HSDC port is always disabled. Choose between read using either the I2C or SPI interfaces. The HSDC port provides
the I2C and SPI ports by manipulating the SS/HSA pin after the state of up to 16 registers representing instantaneous values of
power-up or after a hardware reset. If the SS/HSA pin is kept phase voltages and neutral currents, and active, reactive, and
high, then the ADE7854/ADE7858/ADE7868/ADE7878 use the apparent powers.
I2C port until a new hardware reset is executed. If the SS/HSA I2C-Compatible Interface
pin is toggled high to low three times after power-up or after a
The ADE7854/ADE7858/ADE7868/ADE7878 supports a fully
hardware reset, the ADE7854/ADE7858/ADE7868/ADE7878
licensed I2C interface. The I2C interface is implemented as a full
use the SPI port until a new hardware reset is executed. This
hardware slave. SDA is the data I/O pin, and SCL is the serial
manipulation of the SS/HSA pin can be accomplished in two
clock. These two pins are shared with the MOSI and SCLK pins
ways. First, use the SS/HSA pin of the master device (that is, the of the on-chip SPI interface. The maximum serial clock frequency
microcontroller) as a regular I/O pin and toggle it three times. supported by this interface is 400 kHz.
Second, execute three SPI write operations to a location in the
address space that is not allocated to a specific ADE78xx register The two pins used for data transfer, SDA and SCL, are confi-
(for example 0xEBFF, where eight bit writes can be executed). gured in a wire-AND’ed format that allows arbitration in a
multimaster system.
These writes allow the SS/HSA pin to toggle three times. See the
SPI Write Operation section for details on the write protocol The transfer sequence of an I2C system consists of a master device
involved. initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This con-
tinues until the master issues a stop condition, and the bus
becomes idle.

I2C Write Operation read/write bit. Because this is a write operation, it has to be
The write operation using the I2C interface of the ADE7854/ cleared to 0; therefore, the first byte of the write operation is
ADE7858/ADE7868/ADE7878 initiate when the master generates 0x70. After every byte is received, the ADE7854/ADE7858/
a start condition and consists in one byte representing the ADE7868/ADE7878 generate an acknowledge. As registers can
address of the ADE78xx followed by the 16-bit address of the have 8, 16, or 32 bits, after the last bit of the register is transmitted
target register and by the value of the register. and the ADE78xx acknowledges the transfer, the master gene-
rates a stop condition. The addresses and the register content
The most significant seven bits of the address byte constitute are sent with the most significant bit first. See Figure 86 for
the address of the ADE7854/ADE7858/ADE7868/ADE7878 details of the I2C write operation.
and they are equal to 0111000b. Bit 0 of the address byte is a
START
STOP
15 8 7 0 31 24 23 16 15 8 7 0
S 0 1 1 1 0 0 0 0 S
A MSB 8 BITS OF A LSB 8 BITS OF A BYTE 3 (MSB) A A A BYTE 0 (LSB) OF A

SLAVE ADDRESS C REGISTER ADDRESS C REGISTER ADDRESS C OF REGISTER C BYTE 2 OF REGISTER C BYTE 1 OF REGISTER C REGISTER C
K K K K K K K
08510-059
ACKNOWLEDGE
GENERATED BY
ADE78xx
Figure 86. I2C Write Operation of a 32-Bit Register

I2C Read Operation ADE7854/ADE7858/ADE7868/ADE7878, the second stage
The read operation using the I2C interface of the ADE7854/ begins with the master generating a new start condition followed
ADE7858/ADE7868/ADE7878 is accomplished in two stages. by an address byte. The most significant seven bits of this address
The first stage sets the pointer to the address of the register. The byte constitute the address of the ADE78xx, and they are equal to
second stage reads the content of the register. 0111000b. Bit 0 of the address byte is a read/write bit. Because this
is a read operation, it must be set to 1; thus, the first byte of the
As seen in Figure 87, the first stage initiates when the master read operation is 0x71. After this byte is received, the ADE78xx
generates a start condition and consists in one byte representing generates an acknowledge. Then, the ADE78xx sends the value
the address of the ADE7854/ADE7858/ADE7868/ADE7878 of the register, and after every eight bits are received, the master
followed by the 16-bit address of the target register. The ADE78xx generates an acknowledge. All the bytes are sent with the most
acknowledges every byte received. The address byte is similar to significant bit first. Because registers can have 8, 16, or 32 bits,
the address byte of a write operation and is equal to 0x70 (see after the last bit of the register is received, the master does not
the I2C Write Operation section for details). After the last byte acknowledge the transfer but generates a stop condition.
of the register address has been sent and acknowledged by the
START
15 8 7 0
S 0 1 1 1 0 0 0 0
A MSB 8 BITS OF A LSB 8 BITS OF A

SLAVE ADDRESS C REGISTER ADDRESS C REGISTER ADDRESS C
K K K
ACKNOWLEDGE
GENERATED BY
ADE78xx
ACKNOWLEDGE
GENERATED BY
MASTER N
O
START
STOP
A A A C
31 24 C 23 16 C 15 8 C 7 0 K
K K K
S 0 1 1 1 0 0 0 1 S
A
C BYTE 3 (MSB) BYTE 2 OF BYTE 1 OF BYTE 0 (LSB)
SLAVE ADDRESS K OF REGISTER REGISTER REGISTER OF REGISTER
08510-060
ACKNOWLEDGE
GENERATED BY
ADE78xx
Figure 87. I2C Read Operation of a 32-Bit Register

SPI-Compatible Interface
ADE78xx SPI DEVICE
The SPI of the ADE7854/ADE7858/ADE7868/ADE7878 is
MOSI/SDA MOSI
always a slave of the communication and consists of four pins MISO/HSD MISO
(with dual functions): SCLK/SCL, MOSI/SDA, MISO/HSD, and SCLK/SCL SCK
08510-061
SS/HSA SS
SS/HSA. The functions used in the SPI-compatible interface are
SCLK, MOSI, MISO, and SS. The serial clock for a data transfer Figure 88. Connecting ADE78xx SPI with an SPI Device
is applied at the SCLK logic input. All data transfer operations
synchronize to the serial clock. Data shifts into the ADE78xx at SPI Read Operation
the MOSI logic input on the falling edge of SCLK and the The read operation using the SPI interface of the ADE7854/
ADE78xx samples it on the rising edge of SCLK. Data shifts out ADE7858/ADE7868/ADE7878 initiate when the master sets the
of the ADE7854/ADE7858/ADE7868/ADE7878 at the MISO SS/HSA pin low and begins sending one byte, representing the
logic output on a falling edge of SCLK and can be sampled by address of the ADE7854/ADE7858/ADE7868/ADE7878, on the
the master device on the raising edge of SCLK. The most MOSI line. The master sets data on the MOSI line starting with
significant bit of the word is shifted in and out first. The the first high-to-low transition of SCLK. The SPI of the ADE78xx
maximum serial clock frequency supported by this interface is samples data on the low-to-high transitions of SCLK. The most
2.5 MHz. MISO stays in high impedance when no data is significant seven bits of the address byte can have any value, but
transmitted from the ADE7854/ADE7858/ADE7868/ADE7878. as a good programming practice, they should be different from
See Figure 88 for details of the connection between the 0111000b, the seven bits used in the I2C protocol. Bit 0 (read/write)
ADE78xx SPI and a master device containing an SPI interface. of the address byte must be 1 for a read operation. Next, the
The SS logic input is the chip select input. This input is used master sends the 16-bit address of the register that is read. After
when multiple devices share the serial bus. Drive the SS input the ADE78xx receives the last bit of address of the register on a
low for the entire data transfer operation. Bringing SS high low-to-high transition of SCLK, it begins to transmit its contents
on the MISO line when the next SCLK high-to-low transition
during a data transfer operation aborts the transfer and places
occurs; thus, the master can sample the data on a low-to-high
the serial bus in a high impedance state. A new transfer can
SCLK transition. After the master receives the last bit, it sets the
then be initiated by returning the SS logic input to low. However,
SS and SCLK lines high and the communication ends. The data
because aborting a data transfer before completion leaves the
lines, MOSI and MISO, go into a high impedance state. See
accessed register in a state that cannot be guaranteed, every
Figure 89 for details of the SPI read operation.
time a register is written, its value should be verified by reading
it back. The protocol is similar to the protocol used in I2C
interface.
SS
SCLK
15 14 1 0
MOSI REGISTER ADDRESS

0 0 0 0 0 0 0 1
31 30 1 0
08510-062
MISO REGISTER VALUE
Figure 89. SPI Read Operation of a 32-Bit Register

SPI Write Operation seven bits used in the I2C protocol. Bit 0 (read/write) of the
The write operation using the SPI interface of the ADE78xx address byte must be 0 for a write operation. Next, the master
initiates when the master sets the SS/HSA pin low and begins sends both the 16-bit address of the register that is written and
sending one byte representing the address of the ADE7854/ the 32-, 16-, or 8-bit value of that register without losing any
ADE7858/ADE7868/ADE7878 on the MOSI line. The master SCLK cycle. After the last bit is transmitted, the master sets the
sets data on the MOSI line starting with the first high-to-low SS and SCLK lines high at the end of the SCLK cycle and the
transition of SCLK. The SPI of the ADE78xx samples data on communication ends. The data lines, MOSI and MISO, go into
the low-to-high transitions of SCLK. The most significant seven a high impedance state. See Figure 90 for details of the SPI write
bits of the address byte can have any value, but as a good pro- operation.
gramming practice, they should be different from 0111000b, the
SS
SCLK
15 14 1 0 31 30 1 0
08510-063
MOSI REGISTER ADDRESS REGISTER VALUE
0 0 0 0 0 0 0 0
Figure 90. SPI Write Operation of a 32-Bit Register

HSDC Interface Bit 0 (HCLK) in the HSDC_CFG register determines the serial
The high speed data capture (HSDC) interface is disabled after clock frequency of the HSDC communication. When HCLK is
default. It can be used only if the ADE7854/ADE7858/ADE7868/ 0 (the default value), the clock frequency is 8 MHz. When HCLK
ADE7878 is configured with an I2C interface. The SPI interface is 1, the clock frequency is 4 MHz. A bit of data is transmitted
of the ADE7854/ADE7858/ADE7868/ADE7878 cannot be used for every HSCLK high-to-low transition. The slave device that
simultaneously with HSDC. receives data from HSDC samples the HSD line on the low-to-
high transition of HSCLK.
Bit 6 (HSDCEN) in the CONFIG register activates HSDC when
set to 1. If Bit HSDCEN is cleared to 0, the default value, the The words can be transmitted as 32-bit packages or as 8-bit
HSDC interface is disabled. Setting Bit HSDCEN to 1 when SPI packages. When Bit 1 (HSIZE) in the HSDC_CFG register is 0 (the
is in use does not have any effect. HSDC is an interface for default value), the words are transmitted as 32-bit packages. When
sending to an external device (usually a microprocessor or a Bit HSIZE is 1, the registers are transmitted as 8-bit packages. The
DSP) up to sixteen 32-bit words. The words represent the HSDC interface transmits the words MSB first.
instantaneous values of the phase currents and voltages, neutral Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between
current, and active, reactive, and apparent powers. The registers packages when Bit 2 (HGAP) is set to 1. When Bit HGAP is cleared
being transmitted include IAWV, VAWV, IBWV, VBWV, ICWV, to 0 (the default value), no gap is introduced between packages
VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, and the communication time is shortest. In this case, HSIZE
AVAR, BVAR, and CVAR. All are 24-bit registers that are sign does not have any influence on the communication and a data
extended to 32-bits (see Figure 37 for details). In the case of bit is placed on the HSD line with every HSCLK high-to-low
ADE7854 and ADE7858, the INWV register is not available. In transition.
its place, the HSDC transmits one 32-bit word always equal Bits[4:3] (HXFER[1:0]) decide how many words are transmitted.
to 0. In addition, the AVAR, BVAR, and CVAR registers are not When HXFER[1:0] is 00, the default value, then all 16 words are
available in the ADE7854. In their place, the HSDC transmits transmitted. When HXFER[1:0] is 01, only the words representing
three 32-bit words that are always equal to 0.
the instantaneous values of phase and neutral currents and phase
HSDC can be interfaced with SPI or similar interfaces. HSDC is voltages are transmitted in the following order: IAWV, VAWV,
always a master of the communication and consists of three IBWV, VBWV, ICWV, VCWV, and one 32-bit word that is always
pins: HSA, HSD, and HSCLK. HSA represents the select signal. equal to INWV. When HXFER[1:0] is 10, only the instantaneous
It stays active low or high when a word is transmitted and it is values of phase powers are transmitted in the following order:
usually connected to the select pin of the slave. HSD sends data AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and
to the slave and it is usually connected to the data input pin of CVAR. The value, 11, for HXFER[1:0] is reserved and writing it is
the slave. HSCLK is the serial clock line that is generated by the equivalent to writing 00, the default value.
ADE7854/ADE7858/ADE7868/ADE7878 and it is usually con- Bit 5 (HSAPOL) determines the polarity of HSA function of the
nected to the serial clock input of the slave. Figure 91 shows the SS/HSA pin during communication. When HSAPOL is 0 (the
connections between the ADE78xx HSDC and slave devices
default value), HSA is active low during the communication.
containing an SPI interface.
This means that HSA stays high when no communication is in
progress. When a communication is executed, HSA is low when
ADE78xx SPI DEVICE
the 32-bit or 8-bit packages are transferred, and is high during
MISO/HSD MISO
CF3/HSCLK SCK the gaps. When HSAPOL is 1, the HSA function of the SS/HSA
08510-064
SS/HSA SS pin is active high during the communication. This means that
HSA stays low when no communication is in progress. When a
Figure 91. Connecting the ADE78xx HSDC with an SPI
communication is executed, HSA is high when the 32-bit or
The HSDC communication is managed by the HSDC_CFG 8-bit packages are transferred, and is low during the gaps.
register (see Table 53). It is recommended to set the HSDC_CFG Bits[7:6] of the HSDC_CFG register are reserved. Any value
register to the desired value before enabling the port using Bit 6 written into these bits does not have any consequence on HSDC
(HSDCEN) in the CONFIG register. In this way, the state of behavior.
various pins belonging to the HSDC port do not take levels incon-
sistent with the desired HSDC behavior. After a hardware reset Figure 92 shows the HSDC transfer protocol for HGAP = 0,
HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC
or after power-up, the MISO/HSD and SS/HSA pins are set high.
interface sets a data bit on the HSD line every HSCLK high-
to-low transition and the value of Bit HSIZE is irrelevant.

Figure 93 shows the HSDC transfer protocol for HSIZE = 0, Table 24 lists the time it takes to execute an HSDC data transfer
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the for all HSDC_CFG register settings. For some settings, the
HSDC interface introduces a seven-HSCLK cycles gap between transfer time is less than 125 μs (8 kHz), the waveform sample
every 32-bit word. registers update rate. This means the HSDC port transmits data
Figure 94 shows the HSDC transfer protocol for HSIZE = 1, every sampling cycle. For settings in which the transfer time is
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the greater than 125 μs, the HSDC port transmits data only in the
HSDC interface introduces a seven-HSCLK cycles gap between first of two consecutive 8 kHz sampling cycles. This means it
every 8-bit word. transmits registers at an effective rate of 4 kHz.
See Table 53 for the HSDC_CFG register and descriptions for

the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 24. Communication Times for Various HSDC Settings
HXFER[1:0] HGAP HSIZE1 HCLK Communication Time (μs)
00 0 N/A 0 64
00 0 N/A 1 128
00 1 0 0 77.125
00 1 0 1 154.25
00 1 1 0 119.25
00 1 1 1 238.25
01 0 N/A 0 28
01 0 N/A 1 56
01 1 0 0 33.25
01 1 0 1 66.5
01 1 1 0 51.625
01 1 1 1 103.25
10 0 N/A 0 36
10 0 N/A 1 72
10 1 0 0 43
10 1 0 1 86
10 1 1 0 66.625
10 1 1 1 133.25
1
HSCLK
31 0 31 0 31 0 31 0
HSD IAVW (32 BITS) VAWV (32 BITS) IBWV (32 BITS) CVAR (32 BITS)
08510-066
HSA
Figure 92. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
HSCLK
31 0 31 0 31 0 31 0
HSD IAVW (32-BIT) VAWV (32-BIT) IBWV (32-BIT) CVAR (32-BIT)
7 HCLK CYCLES 7 HCLK CYCLES

08510-067
HSA
Figure 93. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0

HSCLK
31 24 23 16 15 8 7 0
HSD IAVW (BYTE 3) IAWV (BYTE 2) IAWV (BYTE 1) CVAR (BYTE 0)
7 HCLK CYCLES 7 HCLK CYCLES
08510-068
HSA
Figure 94. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
QUICK SETUP AS ENERGY METER ADE7858 and ADE7868 have an identical approach to the
decoupling capacitors, the crystal and its load capacitors.
An energy meter is usually characterized by the nominal
current In, nominal voltage Vn, nominal frequency fn, and the
meter constant MC.
C3 C4
To quickly setup the ADE7878, execute the following steps: 4.7µF 0.22µF
C1 C2 C5 C6
1. Select the PGA gains in the phase currents, voltages, and 4.7µF 0.22µF 0.1µF 10µF
neutral current channels: Bits [2:0] (PGA1), Bits [5:3] 24 5 26 U1
(PGA2) and Bits [8:6] (PGA3) in the Gain register.
VDD
AVDD
DVDD
2 C7 C10
2. If Rogowski coils are used, enable the digital integrators in 3
PM0 0.1µF 4.7µF
PM1 17
REFIN/OUT
the phase and neutral currents: Bit 0 (INTEN) set to 1 in 4 RESET 28
7 IAP CLKOUT
CONFIG register. C8 Y1
16.384MHz
8 IAN
9 29 20pF R1
2
IBP IRQ0
3. If fn=60 Hz, set Bit 14 (SELFREQ) in COMPMODE 12 IBN 32 5MΩ
13 IRQ1 C9 1
register (ADE7878 only). ICP 20pF
14 ICN 33
15 CF1
4. Initialize WTHR1 and WTHR0 registers based on 16
INP
CF2
34
INN 35
Equation 25. Make VARTHR1 (ADE7858, ADE7868, and 18 VN CF3/HSCLK
23 VAP
ADE7878 only) and VATHR1 equal to WTHR1 and 22
VBP MISQ/HSD 37
19 39
VCP SS/HSA
VARTHR0 (ADE7858, ADE7868, and ADE7878 only) and 27
CLKIN
36 SCLK/SCL
VATHR0 equal to WTHR0. 38 MOSI/SDA 25 AGND
6 DGND
PAD PAD
5. Initialize CF1DEN, CF2DEN, and CF3DEN based on NC

Equation 26.
1
10
11
21
30
31
40
20
6. Initialize VLEVEL (ADE7878 only) and VNOM registers
08510-086
based on Equation 21 and Equation 42.
7. Enable the data memory RAM protection by writing 0xAD ADE7878ACPZ
to an internal 8-bit register located at Address 0xE7FE Figure 95. ADE7878 Crystal and Capacitors Connections
followed by a write of 0x80 to an internal 8-bit register Figure 96 and Figure 97 present a proposed layout of a printed
located at Address 0xE7E3. circuit board (PCB) with two layers that have the components
8. Start the DSP by setting Run=1. placed only on the top of the board. Following these layout
9. Read the energy registers xWATTHR, xVARHR guidelines will help in creating a low noise design with higher
(ADE7858, ADE7868, and ADE7878 only), xVAHR, immunity to EMC influences.
xFWATTHR, and xFVARHR (ADE7878 only) to erase
The VDD, AVDD, DVDD and REFin/out pins have each two
their content and start energy accumulation from a known
decoupling capacitors, one of uF order and a ceramic one of
state.
220nF or 100nF. These ceramic capacitors need to be placed the
10. Enable the CF1, CF2 and CF3 frequency converter outputs
closest the the ADE7878 as they decouple high frequency
by clearing bits 9, 10 and 11 (CF1DIS, CF2DIS, and
noises, while the uF ones need to be placed in close proximity.
CF3DIS) to 0 in CFMODE register.
The crystal load capacitors need to be placed closest to the
LAYOUT GUIDELINES ADE7878, while the crystal can be placed in close proximity.
Figure 95 presents a basic schematic of the ADE7878 together
with its surrounding circuitry: decoupling capacitors at pins
VDD, AVDD, DVDD and REFin/out, the 16.384 MHz crystal and
its load capacitors. The rest of the pins are dependent on the
particular application and are not shown here. The ADE7854,
shown in Figure 98. CL1 and CL2 denote the capacitances of the
ceramic capacitors attached to the crystal pins, whereas CP1 and
CP2 denote the parasitic capacitances on those pins.
The recommended typical value of total capacitance at each
clock pin, CLKIN and CLKOUT, is 24 pF, which means that
Total Capacitance = CP1 + CL1 = CP2 + CL2 = 24 pF
Crystal manufacturer data sheets specify the load capacitance
value. A total capacitance of 24 pF, per clock pin, is recommended;
therefore, select a crystal with a 12 pF load capacitance. In
addition, when selecting the ceramic capacitors, CL1 and CL2,
the parasitic capacitances, CP1 and CP2, on the crystal pins of
the IC must be taken into account. Thus, the values of CL1 and
CL2 must be based on the following expression:
CL1 = CL2 = 2 × Crystal Load Capacitance − CP1
where CP1 = CP2.
08510-087
For example, if a 12 pF crystal is chosen and the parasitic

Figure 96. ADE7878 Top Layer Printed Circuit Board
capacitances on the clock pins are CP1 = CP2 = 2 pF, the ceramic
The exposed pad of the ADE7878 is soldered to an equivalent capacitors that must be used in the crystal circuit are CL1 = CL2
pad on the PCB. The AGND and DGND traces of the ADE7878 = 22 pF.
are then routed directly into the PCB pad. The Evaluation Board EVAL-ADE7878EBZ uses the crystal
The bottom layer is composed mainly of a ground plane VM6-1D11C12-TR-16.384MHZ (maximum drive level 1 mW;
surrounding as much as possible the crystal traces. maximum ESR 20 Ω; load capacitance 12 pF). It is recommended
that the same crystal, or a crystal with similar specifications, be
selected. Lower values of ESR and load capacitance and higher
values of drive level capability of the crystal are preferable.
It is also recommended that a 5 MΩ resistor be attached in
parallel to the crystal, as shown in Figure 98.
CL2
CLKIN GND
CP2
ADE78xx IC 5MΩ 16.384MHz CRYSTAL
CP1
CLKOUT
08510-123
GND
CL1
Figure 98. Crystal Circuit
ADE7878 EVALUATION BOARD

An evaluation board built upon the ADE7878 configuration
08510-088
supports all ADE7854, ADE7858, ADE7868, and ADE7878

components. Visit www.analog.com/ADE7878 for details.
Figure 97. ADE7878 Bottom Layer Printed Circuit Board
DIE VERSION
The register named version identifies the version of the die. It is
CRYSTAL CIRCUIT an 8-bit, read-only version register located at Address 0xE707.
A digital clock signal of 16.384 MHz can be provided to the
CLKIN pin of the ADE7854/ADE7858/ADE7868/ADE7878.
Alternatively, attach a crystal of the specified frequency, as

SILICON ANOMALY
This anomaly list describes the known issues with the ADE7854, ADE7858, ADE7868, and ADE7878 silicon identified by the version
register (Address 0xE707) being equal to 2, to 4, and to 5.
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
ADE7854/ADE7858/ADE7868/ADE7878 FUNCTIONALITY ISSUES
Silicon Revision
Identifier Chip Marking Silicon Status Anomaly Sheet No. of Reported Issues
Version = 2 ADE7854ACPZ Released Rev. A 4 (er001, er002, er003, er004)
ADE7858ACPZ
ADE7868ACPZ
ADE7878ACPZ
Version = 4 ADE7854ACPZ Released Rev. B 1 (er005)
ADE7858ACPZ
ADE7868ACPZ
ADE7878ACPZ
Version = 5 ADE7854ACPZ Released Rev. C 1 (er005)
ADE7858ACPZ
ADE7868ACPZ
ADE7878ACPZ
FUNCTIONALITY ISSUES
Table 25. Offset RMS Registers Cannot be Set to Negative Values [er001, Version = 2 Silicon]
Background When the AIRMSOS, AVRMSOS, BIRMSOS, BVRMSOS, CIRMSOS, CVRMSOS, and NIRMSOS registers are set to a negative
value, for sufficiently small inputs, the argument of the square root used in the rms data path may become negative. In
this case, the corresponding AIRMS, AVRMS, BIRMS, BVRMS, CIRMS, or CVRMS rms register is automatically set to 0.
Issue Negative values for the AIRMSOS, AVRMSOS, BIRMSOS, BVRMSOS, CIRMSOS, CVRMSOS, and NIRMSOS registers are not
supported in the silicon version identified by the version register being equal to 2.
Workaround Do not use negative values for the AIRMSOS, AVRMSOS, BIRMSOS, BVRMSOS, CIRMSOS, CVRMSOS, and NIRMSOS
registers.
If further details on this issue are required, please use the following website to submit your query:
www.analog.com/en/content/technical_support_page/fca.html.
Related Issues None.

Table 26. Values Written to the CF1DEN, CF2DEN, CF3DEN, SAGLVL, and ZXTOUT Registers May Not Be Immediately Used By
ADE7854, ADE7858, ADE7868, ADE7878 [er002, Version = 2 Silicon]
Background Usually, the CF1DEN, CF2DEN, CF3DEN, SAGLVL, and ZXTOUT registers initialize immediately after power-up or after a
hardware/software reset. After the RUN register is set to 1, the energy-to-frequency converter (for CF1DEN, CF2DEN, and CF3DEN), the
phase voltage sag detector (for SAGLVL), and the zero-crossing timeout circuit (for ZXTOUT) use these values immediately.
Issue After the CF1DEN register is initialized with a new value after power-up or a hardware/software reset, the new value may be
delayed and, therefore, not immediately available for use by the energy-to-frequency converter. It is, however, used by the
converter after the first high-to-low transition is triggered at t the CF1 pin using the CF1DEN default value (0x0).
CF2DEN and CF3DEN registers present similar behavior at the CF2 and CF3 pins, respectively. CF1DEN, CF2DEN and CF3DEN
above behavior has been corrected in Version = 4 silicon.
After the SAGLVL register is initialized with a new value after power-up or a hardware or software reset, the new value may be
delayed and not available for immediate use by the phase voltage sag detector. However, it is used by the detector after at least
one phase voltage rises above 10% of the full-scale input at the phase voltage ADCs.
After the ZXTOUT register is initialized with a new value after power-up or a hardware or software reset, the new value may be
delayed and not available for immediate use by the zero-crossing timeout circuit. However, the circuit does use the new value
after at least one phase voltage rises above 10% of the full-scale input at the phase voltage ADCs.
Workaround If the behavior outlined in the Issue row does not conflict with the meter specification, then the new values of the CF1DEN,
CF2DEN, CF3DEN, SAGLVL, and ZXTOUT registers may be written one time only.
If the behavior is not acceptable, write the new value into the CF1DEN, CF2DEN, and CF3DEN registers eight consecutive times.
This ensures the probability of the new value not being considered immediately by the energy-to-frequency converter becomes
lower than 0.2 ppm.
Usually, at least one of the phase voltages is greater than 10% of full scale after power-up or after a hardware/software reset. If
this cannot be guaranteed, then the SAGLVL and ZXTOUT registers should also be written eight consecutive times to reduce the
probability of not being considered immediately by the phase voltage sag detector and zero-crossing timeout circuit.
Table 27. The Read-Only RMS Registers May Show the Wrong Value [er003, Version = 2 Silicon]
Background The read-only rms registers (AVRMS, BVRMS, CVRMS, AIRMS, BIRMS, CIRMS, and NIRMS) can be read without restrictions at
any time.
Issue The fixed function DSP of ADE7854, ADE7858, ADE7868, and ADE7878 computes all the powers and rms values in a loop
with a period of 125 µs (8 kHz frequency). If two rms registers are accessed (read) consecutively, the value of the second
register may be corrupted. Consequently, the apparent power computed during that 125 µs cycle is also corrupted. The
rms calculation recovers in the next 125 µs cycle, and all the rms and apparent power values compute correctly.
The issue appears independent of the communication type, SPI or I2C, when the time between the start of two
consecutive rms readings is lower than 265 µs. The issue affects only the rms registers; all of the other registers of
ADE7854, ADE7858, ADE7868, and ADE7878 can be accessed without any restrictions.
Workaround The rms registers can be read one at a time with at least 265 µs between the start of the readings. DREADY interrupt at the
IRQ0 pin can be used to time one rms register reading every three consecutive DREADY interrupts. This ensures 375 µs
between the start of the rms readings.
Alternatively, the rms registers can be read interleaved with readings of other registers that are not affected by this
restriction as long as the time between the start of two consecutive rms register readings is 265 μs.
Table 28. To Obtain Best Accuracy Performance, Internal Setting Must Be Changed [er004, Version = 2 Silicon]
Background Internal default settings provide best accuracy performance for ADE7854, ADE7858, ADE7868, and ADE7878.
Issue It was found that if a different setting is used, the accuracy performance can be improved.
Workaround To enable a new setting for this internal register, execute two consecutive 8-bit register write operations:
The first write operation: 0xAD is written to Address 0xE7FE.
The second write operation: 0x01 is written to Address 0xE7E2.
The write operations must be executed consecutively without any other read/write operation in between. As a
verification that the value was captured correctly, a simple 8-bit read of Address 0xE7E2 should show the 0x01 value.

Table 29. Values Written to the SAGLVL and ZXTOUT Registers May Not Be Immediately Used by ADE7854, ADE7858,
ADE7868, and ADE7878 [er005, Version = 4 and Version = 5 Silicons]
Background Usually, the SAGLVL and ZXTOUT registers initialize immediately after power-up or after a hardware/software reset. After
the run register is set to 1, the phase voltage sag detector (for SAGLVL), and the zero-crossing timeout circuit (for ZXTOUT)
use these values immediately.
Issue After the SAGLVL register is initialized with a new value after power-up or a hardware or software reset, the new value
may be delayed and not available for immediate use by the phase voltage sag detector. However, it is used by the
detector after at least one phase voltage rises above 10% of the full-scale input at the phase voltage ADCs.
After the ZXTOUT register is initialized with a new value after power-up or a hardware or software reset, the new value
may be delayed and not available for immediate use by the zero-crossing timeout circuit. However, the circuit does use
the new value after at least one phase voltage rises above 10% of the full-scale input at the phase voltage ADCs.
Workaround Usually, at least one of the phase voltages is greater than 10% of full scale after power-up or after a hardware/software
reset. If this cannot be guaranteed, then the SAGLVL and ZXTOUT registers should be written eight consecutive times to
reduce the probability of not being considered immediately by the phase voltage sag detector and zero-crossing timeout
circuit below 0.2 ppm.
SECTION 1. ADE7854/ADE7858/ADE7868/ADE7878 FUNCTIONALITY ISSUES

Reference
Number Description Status
er001 Offset rms registers cannot be set to negative values. Identified
er002 Values written to the CF1DEN, CF2DEN, CF2DEN, SAGLVL, and ZXTOUT registers may not be immediately Identified
used by ADE7854, ADE7858, ADE7868, and ADE7878.
er003 The read-only rms registers may show the wrong value. Identified
er004 To obtain best accuracy performance, internal setting must be changed. Identified
er005 Values written to the SAGLVL and ZXTOUT registers may not be immediately used by ADE7854, ADE7858, Identified
ADE7868, and ADE7878.
This completes the Silicon Anomaly section.

REGISTERS LIST
Table 30. Registers List Located in DSP Data Memory RAM
Register Bit Bit Length During Default
Address Name R/W 1 Length Communication 2 Type 3 Value Description
0x4380 AIGAIN R/W 24 32 ZPSE S 0x000000 Phase A current gain adjust.
0x4381 AVGAIN R/W 24 32 ZPSE S 0x000000 Phase A voltage gain adjust.
0x4382 BIGAIN R/W 24 32 ZPSE S 0x000000 Phase B current gain adjust.
0x4383 BVGAIN R/W 24 32 ZPSE S 0x000000 Phase B voltage gain adjust.
0x4384 CIGAIN R/W 24 32 ZPSE S 0x000000 Phase C current gain adjust.
0x4385 CVGAIN R/W 24 32 ZPSE S 0x000000 Phase C voltage gain adjust.
0x4386 NIGAIN R/W 24 32 ZPSE S 0x000000 Neutral current gain adjust (ADE7868 and
ADE7878 only).
0x4387 AIRMSOS R/W 24 32 ZPSE S 0x000000 Phase A current rms offset.
0x4388 AVRMSOS R/W 24 32 ZPSE S 0x000000 Phase A voltage rms offset.
0x4389 BIRMSOS R/W 24 32 ZPSE S 0x000000 Phase B current rms offset.
0x438A BVRMSOS R/W 24 32 ZPSE S 0x000000 Phase B voltage rms offset.
0x438B CIRMSOS R/W 24 32 ZPSE S 0x000000 Phase C current rms offset.
0x438C CVRMSOS R/W 24 32 ZPSE S 0x000000 Phase C voltage rms offset.
0x438D NIRMSOS R/W 24 32 ZPSE S 0x000000 Neutral current rms offset (ADE7868 and
ADE7878 only).
0x438E AVAGAIN R/W 24 32 ZPSE S 0x000000 Phase A apparent power gain adjust.
0x438F BVAGAIN R/W 24 32 ZPSE S 0x000000 Phase B apparent power gain adjust.
0x4390 CVAGAIN R/W 24 32 ZPSE S 0x000000 Phase C apparent power gain adjust.
0x4391 AWGAIN R/W 24 32 ZPSE S 0x000000 Phase A total active power gain adjust.
0x4392 AWATTOS R/W 24 32 ZPSE S 0x000000 Phase A total active power offset adjust.
0x4393 BWGAIN R/W 24 32 ZPSE S 0x000000 Phase B total active power gain adjust.
0x4394 BWATTOS R/W 24 32 ZPSE S 0x000000 Phase B total active power offset adjust.
0x4395 CWGAIN R/W 24 32 ZPSE S 0x000000 Phase C total active power gain adjust.
0x4396 CWATTOS R/W 24 32 ZPSE S 0x000000 Phase C total active power offset adjust.
0x4397 AVARGAIN R/W 24 32 ZPSE S 0x000000 Phase A total reactive power gain adjust
(ADE7858, ADE7868, and ADE7878).
0x4398 AVAROS R/W 24 32 ZPSE S 0x000000 Phase A total reactive power offset adjust
(ADE7858, ADE7868, and ADE7878).
0x4399 BVARGAIN R/W 24 32 ZPSE S 0x000000 Phase B total reactive power gain adjust
(ADE7858, ADE7868, and ADE7878).
0x439A BVAROS R/W 24 32 ZPSE S 0x000000 Phase B total reactive power offset adjust
(ADE7858, ADE7868, and ADE7878).
0x439B CVARGAIN R/W 24 32 ZPSE S 0x000000 Phase C total reactive power gain adjust
(ADE7858, ADE7868, and ADE7878).
0x439C CVAROS R/W 24 32 ZPSE S 0x000000 Phase C total reactive power offset adjust
(ADE7858, ADE7868, and ADE7878).
0x439D AFWGAIN R/W 24 32 ZPSE S 0x000000 Phase A fundamental active power gain
adjust. Location reserved for ADE7854,
0x439E AFWATTOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental active power offset
adjust. Location reserved for ADE7854,
0x439F BFWGAIN R/W 24 32 ZPSE S 0x000000 Phase B fundamental active power gain
adjust (ADE7878 only).
0x43A0 BFWATTOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental active power offset
0x43A1 CFWGAIN R/W 24 32 ZPSE S 0x000000 Phase C fundamental active power gain
adjust.
0x43A2 CFWATTOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental active power offset

0x43A3 AFVARGAIN R/W 24 32 ZPSE S 0x000000 Phase A fundamental reactive power gain
0x43A4 AFVAROS R/W 24 32 ZPSE S 0x000000 Phase A fundamental reactive power
offset adjust (ADE7878 only).
0x43A5 BFVARGAIN R/W 24 32 ZPSE S 0x000000 Phase B fundamental reactive power gain
0x43A6 BFVAROS R/W 24 32 ZPSE S 0x000000 Phase B fundamental reactive power
0x43A7 CFVARGAIN R/W 24 32 ZPSE S 0x000000 Phase C fundamental reactive power gain
0x43A8 CFVAROS R/W 24 32 ZPSE S 0x000000 Phase C fundamental reactive power
0x43A9 VATHR1 R/W 24 32 ZP U 0x000000 Most significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
0x43AA VATHR0 R/W 24 32 ZP U 0x000000 Less significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
0x43AB WTHR1 R/W 24 32 ZP U 0x000000 Most significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
0x43AC WTHR0 R/W 24 32 ZP U 0x000000 Less significant 24 bits of WTHR[47:0]
0x43AD VARTHR1 R/W 24 32 ZP U 0x000000 Most significant 24 bits of VARTHR[47:0]
reactive power datapath (ADE7858,
ADE7868, and ADE7878).
0x43AE VARTHR0 R/W 24 32 ZP U 0x000000 Less significant 24 bits of VARTHR[47:0]
reactive power datapath (ADE7858,
ADE7868, and ADE7878).
0x43AF Reserved N/A 4 N/A4 N/A4 N/A4 0x000000 This memory location should be kept at
0x000000 for proper operation.
0x43B0 VANOLOAD R/W 24 32 ZPSE S 0x0000000 No load threshold in the apparent power
datapath.
0x43B1 APNOLOAD R/W 24 32 ZPSE S 0x0000000 No load threshold in the total/fundamental
0x43B2 VARNOLOAD R/W 24 32 ZPSE S 0x0000000 No load threshold in the total/fundamental
reactive power datapath. Location
reserved for ADE7854.
0x43B3 VLEVEL R/W 24 32 ZPSE S 0x000000 Register used in the algorithm that
computes the fundamental active and
reactive powers (ADE7878 only).
0x43B4 Reserved N/A4 N/A4 N/A4 N/A4 0x000000 This location should not be written for
proper operation.
0x43B5 DICOEFF R/W 24 32 ZPSE S 0x0000000 Register used in the digital integrator
algorithm. If the integrator is turned on, it
must be set at 0xFF8000. In practice, it is
transmitted as 0xFFF8000.
0x43B6 HPFDIS R/W 24 32 ZP U 0x000000 Disables/enables the HPF in the current
datapath (see Table 34).
0x43B7 Reserved N/A4 N/A4 N/A4 N/A4 0x000000 This memory location should be kept at
0x000000 for proper operation.
0x43B8 ISUMLVL R/W 24 32 ZPSE S 0x000000 Threshold used in comparison between
the sum of phase currents and the neutral
current (ADE7868 and ADE7878 only).

0x43B9 to Reserved N/A4 N/A4 N/A4 N/A4 0x000000 These memory locations should be kept
0x43BE at 0x000000 for proper operation.
0x43BF ISUM R 28 32 ZP S N/A4 Sum of IAWV, IBWV, and ICWV registers
(ADE7868 and ADE7878 only).
0x43C0 AIRMS R 24 32 ZP S N/A4 Phase A current rms value.
0x43C1 AVRMS R 24 32 ZP S N/A4 Phase A voltage rms value.
0x43C2 BIRMS R 24 32 ZP S N/A4 Phase B current rms value.
0x43C3 BVRMS R 24 32 ZP S N/A4 Phase B voltage rms value.
0x43C4 CIRMS R 24 32 ZP S N/A4 Phase C current rms value.
0x43C5 CVRMS R 24 32 ZP S N/A4 Phase C voltage rms value.
0x43C6 NIRMS R 24 32 ZP S N/A4 Neutral current rms value (ADE7868 and
ADE7878 only).
0x43C7 to Reserved N/A4 N/A4 N/A4 N/A4 N/A4 These memory locations should not be
0x43FF written for proper operation.
1
R is read, and W is write.
2
32 ZPSE = 24-bit signed register that is transmitted as a 32-bit word with four MSBs padded with 0s and sign extended to 28 bits. Whereas 32 ZP = 28- or 24-bit signed
or unsigned register that is transmitted as a 32-bit word with four MSBs or eight MSBs, respectively, padded with 0s.
3
U is unsigned register, and S is signed register in twos complement format.
4
Table 31. Internal DSP Memory RAM Registers

Bit Length
Register Bit During Default
Address Name R/W 1 Length Communication Type 2 Value Description
0xE203 Reserved R/W 16 16 U 0x0000 This memory location should not be written for
proper operation.
0xE228 Run R/W 16 16 U 0x0000 Run register starts and stops the DSP. See the
Digital Signal Processor section for more details.
1
2
Table 32. Billable Registers

Bit Length
Address Name R/W 1, 2 Length2 Communication2 Type2, 3 Value Description
0xE400 AWATTHR R 32 32 S 0x00000000 Phase A total active energy accumulation.
0xE401 BWATTHR R 32 32 S 0x00000000 Phase B total active energy accumulation.
0xE402 CWATTHR R 32 32 S 0x00000000 Phase C total active energy accumulation.
0xE403 AFWATTHR R 32 32 S 0x00000000 Phase A fundamental active energy
accumulation (ADE7878 only).
0xE404 BFWATTHR R 32 32 S 0x00000000 Phase B fundamental active energy
0xE405 CFWATTHR R 32 32 S 0x00000000 Phase C fundamental active energy
0xE406 AVARHR R 32 32 S 0x00000000 Phase A total reactive energy accumulation
(ADE7858, ADE7868, and ADE7878 only).
0xE407 BVARHR R 32 32 S 0x00000000 Phase B total reactive energy accumulation
0xE408 CVARHR R 32 32 S 0x00000000 Phase C total reactive energy accumulation
0xE409 AFVARHR R 32 32 S 0x00000000 Phase A fundamental reactive energy
0xE40A BFVARHR R 32 32 S 0x00000000 Phase B fundamental reactive energy
0xE40B CFVARHR R 32 32 S 0x00000000 Phase C fundamental reactive energy

Bit Length
Address Name R/W 1, 2 Length2 Communication2 Type2, 3 Value Description
0xE40C AVAHR R 32 32 S 0x00000000 Phase A apparent energy accumulation.
0xE40D BVAHR R 32 32 S 0x00000000 Phase B apparent energy accumulation.
0xE40E CVAHR R 32 32 S 0x00000000 Phase C apparent energy accumulation.
1
2
N/A is not applicable.
3
Table 33. Configuration and Power Quality Registers

Bit Length
Address Name R/W 1 Length Communication 2 Type 3 Value 4 Description
0xE500 IPEAK R 32 32 U N/A Current peak register. See Figure 50
and Table 35 for details about its
composition.
0xE501 VPEAK R 32 32 U N/A Voltage peak register. See Figure 50
and Table 36 for details about its
composition.
0xE502 STATUS0 R/W 32 32 U N/A Interrupt Status Register 0. See Table 37.
0xE503 STATUS1 R/W 32 32 U N/A Interrupt Status Register 1. See Table 38.
0xE504 AIMAV R 20 32 ZP U N/A Phase A current mean absolute value
computed during PSM0 and PSM1
modes (ADE7868 and ADE7878 only).
0xE505 BIMAV R 20 32 ZP U N/A Phase B current mean absolute value
0xE506 CIMAV R 20 32 ZP U N/A Phase C current mean absolute value
0xE507 OILVL R/W 24 32 ZP U 0xFFFFFF Overcurrent threshold.
0xE508 OVLVL R/W 24 32 ZP U 0xFFFFFF Overvoltage threshold.
0xE509 SAGLVL R/W 24 32 ZP U 0x000000 Voltage SAG level threshold.
0xE50A MASK0 R/W 32 32 U 0x00000000 Interrupt Enable Register 0. See Table 39.
0xE50B MASK1 R/W 32 32 U 0x00000000 Interrupt Enable Register 1. See Table 40.
0xE50C IAWV R 24 32 SE S N/A Instantaneous value of Phase A current.
0xE50D IBWV R 24 32 SE S N/A Instantaneous value of Phase B current.
0xE50E ICWV R 24 32 SE S N/A Instantaneous value of Phase C current.
0xE50F INWV R 24 32 SE S N/A Instantaneous value of neutral current
(ADE7868 and ADE7878 only).
0xE510 VAWV R 24 32 SE S N/A Instantaneous value of Phase A voltage.
0xE511 VBWV R 24 32 SE S N/A Instantaneous value of Phase B voltage.
0xE512 VCWV R 24 32 SE S N/A Instantaneous value of Phase C voltage.
0xE513 AWATT R 24 32 SE S N/A Instantaneous value of Phase A total
active power.
0xE514 BWATT R 24 32 SE S N/A Instantaneous value of Phase B total
active power.
0xE515 CWATT R 24 32 SE S N/A Instantaneous value of Phase C total
active power.
0xE516 AVAR R 24 32 SE S N/A Instantaneous value of Phase A total
reactive power (ADE7858, ADE7868,
and ADE7878 only).
0xE517 BVAR R 24 32 SE S N/A Instantaneous value of Phase B total
and ADE7878 only).
0xE518 CVAR R 24 32 SE S N/A Instantaneous value of Phase C total
and ADE7878 only).
Bit Length
0xE519 AVA R 24 32 SE S N/A Instantaneous value of Phase A
apparent power.
0xE51A BVA R 24 32 SE S N/A Instantaneous value of Phase B
apparent power.
0xE51B CVA R 24 32 SE S N/A Instantaneous value of Phase C
apparent power.
0xE51F CHECKSUM R 32 32 U 0x33666787 Checksum verification. See the
Checksum Register section for details.
0xE520 VNOM R/W 24 32 ZP S 0x000000 Nominal phase voltage rms used in the
alternative computation of the
apparent power. When the VNOMxEN
bit is set, the applied voltage input in
the corresponding phase is ignored
and all corresponding rms voltage
instances are replaced by the value in
the VNOM register.
0xE521 to Reserved These addresses should not be written
0xE52E for proper operation.
0xE600 PHSTATUS R 16 16 U N/A Phase peak register. See Table 41.
0xE601 ANGLE0 R 16 16 U N/A Time Delay 0. See the Time Interval
Between Phases section for details.
0xE606 for proper operation.
0xE607 PERIOD R 16 16 U N/A Network line period.
0xE608 PHNOLOAD R 16 16 U N/A Phase no load register. See Table 42.
0xE60B for proper operation.
0xE60C LINECYC R/W 16 16 U 0xFFFF Line cycle accumulation mode count.
0xE60D ZXTOUT R/W 16 16 U 0xFFFF Zero-crossing timeout count.
0xE60E COMPMODE R/W 16 16 U 0x01FF Computation-mode register. See
Table 43.
0xE60F Gain R/W 16 16 U 0x0000 PGA gains at ADC inputs. See Table 44.
0xE610 CFMODE R/W 16 16 U 0x0E88 CFx configuration register. See Table 45.
0xE611 CF1DEN R/W 16 16 U 0x0000 CF1 denominator.
0xE614 APHCAL R/W 10 16 ZP S 0x0000 Phase calibration of Phase A. See
Table 46.
0xE615 BPHCAL R/W 10 16 ZP S 0x0000 Phase calibration of Phase B. See Table 46.
0xE616 CPHCAL R/W 10 16 ZP S 0x0000 Phase calibration of Phase C. See Table 46.
0xE617 PHSIGN R 16 16 U N/A Power sign register. See Table 47.
0xE618 CONFIG R/W 16 16 U 0x0000 ADE7878 configuration register. See
Table 48.
0xE700 MMODE R/W 8 8 U 0x1C Measurement mode register.
See Table 49.
0xE701 ACCMODE R/W 8 8 U 0x00 Accumulation mode register.
See Table 50.
0xE702 LCYCMODE R/W 8 8 U 0x78 Line accumulation mode behavior. See
Table 52.
0xE703 PEAKCYC R/W 8 8 U 0x00 Peak detection half line cycles.
0xE704 SAGCYC R/W 8 8 U 0x00 SAG detection half line cycles.

Bit Length
0xE705 CFCYC R/W 8 8 U 0x01 Number of CF pulses between two
consecutive energy latches. See the
Synchronizing Energy Registers with
CFx Outputs section.
0xE706 HSDC_CFG R/W 8 8 U 0x00 HSDC configuration register. See Table 53.
0xE707 Version R 8 8 U Version of die.
0xEBFF Reserved 8 8 This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port. See the Serial Interfaces
section for details.
0xEC00 LPOILVL R/W 8 8 U 0x07 Overcurrent threshold used during
PSM2 mode (ADE7868 and ADE7878
only). See Table 54 in which the register
is detailed.
0xEC01 CONFIG2 R/W 8 8 U 0x00 Configuration register used during
PSM1 mode. See Table 55.
1
2
32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3
4
N/A is not applicable.
Table 34. HPFDIS Register (Address 0x43B6)

Bit Default
Location Value Description
23:0 00000000 When HPFDIS = 0x00000000, then all high-pass filters in voltage and current channels are enabled. When the
register is set to any nonzero value, all high-pass filters are disabled.
Table 35. IPEAK Register (Address 0xE500)

Bit Location Bit Mnemonic Default Value Description
23:0 IPEAKVAL[23:0] 0 These bits contain the peak value determined in the current channel.
24 IPPHASE[0] 0 When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.
25 IPPHASE[1] 0 When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.
26 IPPHASE[2] 0 When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.
31:27 00000 These bits are always 0.
Table 36. VPEAK Register (Address 0xE501)

23:0 VPEAKVAL[23:0] 0 These bits contain the peak value determined in the voltage channel.
24 VPPHASE[0] 0 When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.
25 VPPHASE[1] 0 When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.
26 VPPHASE[2] 0 When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.
31:27 00000 These bits are always 0.
Table 37. STATUS0 Register (Address 0xE502)

Bit
Location Bit Mnemonic Default Value Description
0 AEHF 0 When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, or CWATTHR) has changed.
1 FAEHF 0 When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active
energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed. This bit is always 0
for ADE7854, ADE7858, and ADE7868.
2 REHF 0 When this bit is set to 1, it indicates that Bit 30 of any one of the total reactive energy
registers (AVARHR, BVARHR, or CVARHR) has changed. This bit is always 0 for ADE7854.

Bit
3 FREHF 0 When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental reactive
energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed. This bit is always 0 for
ADE7854, ADE7858, and ADE7868.
4 VAEHF 0 When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
5 LENERGY 0 When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
6 REVAPA 0 When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 47).
7 REVAPB 0 When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6
itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 47).
8 REVAPC 0 When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6
itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 47).
9 REVPSUM1 0 When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath
has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register
(see Table 47).
10 REVRPA 0 When this bit is set to 1, it indicates that the Phase A reactive power identified by Bit 7
(REVRPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 4 (AVARSIGN) of the PHSIGN register (see Table 47). This bit is
always 0 for ADE7854.
11 REVRPB 0 When this bit is set to 1, it indicates that the Phase B reactive power identified by Bit 7
itself is indicated in Bit 5 (BVARSIGN) of the PHSIGN register (see Table 47). This bit is
12 REVRPC 0 When this bit is set to 1, it indicates that the Phase C reactive power identified by Bit 7
itself is indicated in Bit 6 (CVARSIGN) of the PHSIGN register (see Table 47). This bit is
(see Table 47).
14 CF1 When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin; that
is, an active low pulse has been generated. The bit is set even if the CF1 output is disabled
by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at the CF1
pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 45).
15 CF2 When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2 pin;
that is, an active low pulse has been generated. The bit is set even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
16 CF3 When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin; that
is, an active low pulse has been generated. The bit is set even if the CF3 output is disabled
by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at the CF3
pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17 DREADY 0 When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP computations
have finished.
(see Table 47).
31:19 Reserved 0 0000 0000 0000 Reserved. These bits are always 0.
Rev. H| Page 86 of 100

Table 38. STATUS1 Register (Address 0xE503)

Bit
0 NLOAD 0 When this bit is set to 1, it indicates that at least one phase entered no load condition based
on total active and reactive powers. The phase is indicated in Bits[2:0] (NLPHASE[x]) in the
PHNOLOAD register (see Table 42).
1 FNLOAD 0 When this bit is set to 1, it indicates that at least one phase entered no load condition based
on fundamental active and reactive powers. The phase is indicated in Bits[5:3] (FNLPHASE[x])
in PHNOLOAD register (see Table 42 in which this register is described). This bit is always 0
for ADE7854, ADE7858, and ADE7868.
2 VANLOAD 0 When this bit is set to 1, it indicates that at least one phase entered no load condition based
on apparent power. The phase is indicated in Bits[8:6] (VANLPHASE[x]) in the PHNOLOAD
register (see Table 42).
3 ZXTOVA 0 When this bit is set to 1, it indicates a zero crossing on Phase A voltage is missing.
4 ZXTOVB 0 When this bit is set to 1, it indicates a zero crossing on Phase B voltage is missing.
5 ZXTOVC 0 When this bit is set to 1, it indicates a zero crossing on Phase C voltage is missing.
6 ZXTOIA 0 When this bit is set to 1, it indicates a zero crossing on Phase A current is missing.
7 ZXTOIB 0 When this bit is set to 1, it indicates a zero crossing on Phase B current is missing.
8 ZXTOIC 0 When this bit is set to 1, it indicates a zero crossing on Phase C current is missing.
9 ZXVA 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase A voltage.
10 ZXVB 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase B voltage.
11 ZXVC 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase C voltage.
12 ZXIA 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase A current.
13 ZXIB 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase B current.
14 ZXIC 0 When this bit is set to 1, it indicates a zero crossing has been detected on Phase C current.
15 RSTDONE 1 In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG register, or a
transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the
end of the transition process and after all registers changed value to default. The IRQ1 pin
goes low to signal this moment because this interrupt cannot be disabled.
16 SAG 0 When this bit is set to 1, it indicates a SAG event has occurred on one of the phases indicated
by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 41).
17 OI 0 When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases
indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 41).
18 OV 0 When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases
indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 41).
19 SEQERR 0 When this bit is set to 1, it indicates a negative-to-positive zero crossing on Phase A voltage
was not followed by a negative-to-positive zero crossing on Phase B voltage but by a
negative-to-positive zero crossing on Phase C voltage.
20 MISMTCH 0 When this bit is set to 1, it indicates ISUM − INWV > ISUMLVL , where ISUMLVL is
indicated in the ISUMLVL register. This bit is always 0 for ADE7854 and ADE7858.
21 Reserved 1 Reserved. This bit is always set to 1.
22 Reserved 0 Reserved. This bit is always set to 0.
23 PKI 0 When this bit is set to 1, it indicates that the period used to detect the peak value in the
current channel has ended. The IPEAK register contains the peak value and the phase where
the peak has been detected (see Table 35).
24 PKV 0 When this bit is set to 1, it indicates that the period used to detect the peak value in the
voltage channel has ended. VPEAK register contains the peak value and the phase where the
peak has been detected (see Table 36).
31:25 Reserved 000 0000 Reserved. These bits are always 0.

Table 39. MASK0 Register (Address 0xE50A)

Bit
0 AEHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active
energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.
1 FAEHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes. Setting this bit to1
does not have any consequence for ADE7854, ADE7858, and ADE7868.
2 REHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total reactive
energy registers (AVARHR, BVARHR, CVARHR) changes. Setting this bit to1 does not have any
consequence for ADE7854.
3 FREHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes. Setting this bit to1
does not have any consequence for ADE7854, ADE7858, and ADE7868.
4 VAEHF 0 When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent
energy registers (AVAHR, BVAHR, or CVAHR) changes.
5 LENERGY 0 When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end
of an integration over an integer number of half line cycles set in the LINECYC register.
6 REVAPA 0 When this bit is set to 1, it enables an interrupt when the Phase A active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
7 REVAPB 0 When this bit is set to 1, it enables an interrupt when the Phase B active power identified by
8 REVAPC 0 When this bit is set to 1, it enables an interrupt when the Phase C active power identified by
9 REVPSUM1 0 When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
10 REVRPA 0 When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
this bit to1 does not have any consequence for ADE7854.
11 REVRPB 0 When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified
12 REVRPC 0 When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified
14 CF1 When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the
CF1 pin, that is, an active low pulse is generated. The interrupt can be enabled even if the
CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of
power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
(see Table 45).
15 CF2 When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF2
output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power
used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
16 CF3 When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF3
output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power
used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17 DREADY 0 When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate) DSP
computations finish.
31:19 Reserved 00 0000 0000 Reserved. These bits do not manage any functionality.
0000

Table 40. MASK1 Register (Address 0xE50B)
Bit
0 NLOAD 0 When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on total active and reactive powers.
1 FNLOAD 0 When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on fundamental active and reactive powers. Setting this bit to 1 does not
have any consequence for ADE7854, ADE7858, and ADE7868.
2 VANLOAD 0 When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on apparent power.
3 ZXTOVA 0 When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A voltage is
missing.
4 ZXTOVB 0 When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B voltage is
missing.
5 ZXTOVC 0 When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C voltage is
missing.
6 ZXTOIA 0 When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A current is
missing.
7 ZXTOIB 0 When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B current is
missing.
8 ZXTOIC 0 When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C current is
missing.
9 ZXVA 0 When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
voltage.
10 ZXVB 0 When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
voltage.
11 ZXVC 0 When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
voltage.
12 ZXIA 0 When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
current.
13 ZXIB 0 When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
current.
14 ZXIC 0 When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
current.
15 RSTDONE 0 Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
16 SAG 0 When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the
phases indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 41).
17 OI 0 When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of
the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 41).
18 OV 0 When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of
the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 41).
19 SEQERR 0 When this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on
Phase A voltage is not followed by a negative-to-positive zero crossing on Phase B voltage,
but by a negative-to-positive zero crossing on Phase C voltage.
20 MISMTCH 0 When this bit is set to 1, it enables an interrupt when ISUM − INWV > ISUMLVL is
greater than the value indicated in ISUMLVL register. Setting this bit to1 does not have any
consequence for ADE7854 and ADE7858.
22:21 Reserved 00 Reserved. These bits do not manage any functionality.
23 PKI 0 When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
24 PKV 0 When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
31:25 Reserved 000 0000 Reserved. These bits do not manage any functionality.

Table 41. PHSTATUS Register (Address 0xE600)

Bit
2:0 Reserved 000 Reserved. These bits are always 0.
3 OIPHASE[0] 0 When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
4 OIPHASE[1] 0 When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
5 OIPHASE[2] 0 When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
8:6 Reserved 000 Reserved. These bits are always 0.
9 OVPHASE[0] 0 When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
10 OVPHASE[1] 0 When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
11 OVPHASE[2] 0 When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
12 VSPHASE[0] 0 When this bit is set to 1, Phase A voltage generates Bit 16 (SAG) in the STATUS1 register.
13 VSPHASE[1] 0 When this bit is set to 1, Phase B voltage generates Bit 16 (SAG) in the STATUS1 register.
14 VSPHASE[2] 0 When this bit is set to 1, Phase C voltage generates Bit16 (SAG) in the STATUS1 register.
15 Reserved 0 Reserved. This bit is always 0.
Table 42. PHNOLOAD Register (Address 0xE608)

Bit
0 NLPHASE[0] 0 0: Phase A is out of no load condition based on total active/reactive powers.
1: Phase A is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
1 NLPHASE[1] 0 0: Phase B is out of no load condition based on total active/reactive powers.
1: Phase B is in no load condition based on total active/reactive powers. Bit set together with
2 NLPHASE[2] 0 0: Phase C is out of no load condition based on total active/reactive powers.
1: Phase C is in no load condition based on total active/reactive powers. Bit set together with
3 FNLPHASE[0] 0 0: Phase A is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
4 FNLPHASE[1] 0 0: Phase B is out of no load condition based on fundamental active/reactive powers. This bit
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
5 FNLPHASE[2] 0 0: Phase C is out of no load condition based on fundamental active/reactive powers. This bit
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
6 VANLPHASE[0] 0 0: Phase A is out of no load condition based on apparent power.
1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
7 VANLPHASE[1] 0 0: Phase B is out of no load condition based on apparent power.
1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2
8 VANLPHASE[2] 0 0: Phase C is out of no load condition based on apparent power.
1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2

Table 43. COMPMODE Register (Address 0xE60E)
Bit
0 TERMSEL1[0] 1 Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1
output. Phase A is included in the CF1 outputs calculations.
1 TERMSEL1[1] 1 Phase B is included in the CF1 outputs calculations.
2 TERMSEL1[2] 1 Phase C is included in the CF1 outputs calculations.
10:9 ANGLESEL[1:0] 00 00: the angles between phase voltages and phase currents are measured.
01: the angles between phase voltages are measured.
10: the angles between phase currents are measured.
11: no angles are measured.
11 VNOMAEN 0 When this bit is 0, the apparent power on Phase A is computed regularly.
When this bit is 1, the apparent power on Phase A is computed using VNOM register instead
of regular measured rms phase voltage. The applied Phase A voltage input is ignored, and all
Phase A rms voltage instances are replaced by the value in the VNOM register.
12 VNOMBEN 0 When this bit is 0, the apparent power on Phase B is computed regularly.
When this bit is 1, the apparent power on Phase B is computed using VNOM register instead
of regular measured rms phase voltage. The applied Phase B voltage input is ignored, and all
Phase B rms voltage instances are replaced by the value in the VNOM register.
13 VNOMCEN 0 When this bit is 0, the apparent power on Phase C is computed regularly.
When this bit is 1, the apparent power on Phase C is computed using VNOM register instead
of regular measured rms phase voltage. The applied Phase C voltage input is ignored, and all
Phase C rms voltage instances are replaced by the value in the VNOM register.
14 SELFREQ 0 When the ADE7878 is connected to 50 Hz networks, this bit should be cleared to 0 (default
value). When the ADE7878 is connected to 60 Hz networks, this bit should be set to 1. This
bit does not have any consequence for ADE7854, ADE7858, and ADE7868.
15 Reserved 0 This bit is 0 by default and it does not manage any functionality.
Table 44. Gain Register (Address 0xE60F)

Bit
2:0 PGA1[2:0] 000 Phase currents gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave
like PGA1[2:0] = 000.
5:3 PGA2[2:0] 000 Neutral current gain selection.
000: gain = 1. These bits are always 000 for ADE7854 and ADE7858.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7868/ADE7878 behave like PGA2[2:0] =
000.

8:6 PGA3[2:0] 000 Phase voltages gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave
like PGA3[2:0] = 000.
15:9 Reserved 000 0000 Reserved. These bits do not manage any functionality.
Table 45. CFMODE Register (Address 0xE610)

Bit
2:0 CF1SEL[2:0] 000 000: the CF1 frequency is proportional to the sum of total active powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
001: the CF1 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854.
010: the CF1 frequency is proportional to the sum of apparent powers on each phase
011: the CF1 frequency is proportional to the sum of fundamental active powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854, ADE7858, and ADE7868.
100: the CF1 frequency is proportional to the sum of fundamental reactive powers on each
101, 110, 111: reserved. When set, the CF1 signal is not generated.
011: the CF2 frequency is proportional to the sum of fundamental active powers on each
100: the CF2 frequency is proportional to the sum of fundamental reactive powers on each
101,110,111: reserved. When set, the CF2 signal is not generated.
011: CF3 frequency is proportional to the sum of fundamental active powers on each phase
have any consequence for the ADE7854, ADE7858, and ADE7868.
100: CF3 frequency is proportional to the sum of fundamental reactive powers on each
101,110,111: reserved. When set, the CF3 signal is not generated.
9 CF1DIS 1 When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency
converter remains enabled even if CF1DIS = 1.
When this bit is set to 0, the CF1 output is enabled.

Bit
12 CF1LATCH 0 When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF1 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
15 Reserved 0 Reserved. This bit does not manage any functionality.
Table 46. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
9:0 PHCALVAL 0000000000 If the current leads the voltage, these bits can vary only between 0 and 383.
If the current lags the voltage, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
Table 47. PHSIGN Register (Address 0xE617)

Bit
0 AWSIGN 0 0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
1 BWSIGN 0 0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
2 CWSIGN 0 0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
3 SUM1SIGN 0 0: if the sum of all phase powers in the CF1 datapath is positive.
1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
4 AVARSIGN 0 0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
5 BVARSIGN 0 0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive. This bit is always 0 for ADE7854.
fundamental) on Phase B is negative.
6 CVARSIGN 0 0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive. This bit is always 0 for ADE7854.
fundamental) on Phase C is negative.
Bit
Table 48. CONFIG Register (Address 0xE618)

Bit
0 INTEN 0 Integrator enable. When this bit is set to 1, the internal digital integrator is enabled for use in
meters utilizing Rogowski coils on all 3-phase and neutral current inputs.
When this bit is cleared to 0, the internal digital integrator is disabled.
3 SWAP 0 When this bit is set to 1, the voltage channel outputs are swapped with the current channel
outputs. Thus, the current channel information is present in the voltage channel registers
and vice versa.
4 MOD1SHORT 0 When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put
to ground.
5 MOD2SHORT 0 When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put
to ground.
6 HSDCEN 0 When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at
CF3/HSCLK pin.
When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.
7 SWRST 0 When this bit is set to 1, a software reset is initiated.
9:8 VTOIA[1:0] 00 These bits decide what phase voltage is considered together with Phase A current in the
power path.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave like VTOIA[1:0] =
00.
11:10 VTOIB[1:0] 00 These bits decide what phase voltage is considered together with Phase B current in the
power path.
11 = reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave like VTOIB[1:0] =
00.
13:12 VTOIC[1:0] 00 These bits decide what phase voltage is considered together with Phase C current in the
power path.
11 = reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave like VTOIC[1:0] =
00.

Table 49. MMODE Register (Address 0xE700)

Bit
1:0 PERSEL[1:0] 00 00: Phase A selected as the source of the voltage line period measurement.
01: Phase B selected as the source of the voltage line period measurement.
10: Phase C selected as the source of the voltage line period measurement.
11: reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave like PERSEL[1:0] = 00.
2 PEAKSEL[0] 1 PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three
phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak
measurement period indicated in the PEAKCYC register decreases accordingly because zero
crossings are detected on more than one phase.
When this bit is set to 1, Phase A is selected for the voltage and current peak registers.
3 PEAKSEL[1] 1 When this bit is set to 1, Phase B is selected for the voltage and current peak registers.
4 PEAKSEL[2] 1 When this bit is set to 1, Phase C is selected for the voltage and current peak registers.
Table 50. ACCMODE Register (Address 0xE701)

Bit
1:0 WATTACC[1:0] 00 00: signed accumulation mode of the total and fundamental active powers. Fundamental
active powers are available in the ADE7878.
01: reserved. When set, the device behaves like WATTACC[1:0] = 00.
10: reserved. When set, the device behaves like WATTACC[1:0] = 00.
11: absolute accumulation mode of the total and fundamental active powers.
3:2 VARACC[1:0] 00 00: signed accumulation of the total and fundamental reactive powers. Total reactive powers
are available in the ADE7858, ADE7868, and ADE7878. Fundamental reactive powers are
available in the ADE7878. These bits are always 00 for the ADE7854.
01: reserved. When set, the device behaves like VARACC[1:0] = 00.
10: the total and fundamental reactive powers are accumulated, depending on the sign of
the total and fundamental active power: if the active power is positive, the reactive power is
accumulated as is, whereas if the active power is negative, the reactive power is accumulated
with reversed sign.
11: reserved. When set, the device behave like VARACC[1:0] = 00.
5:4 CONSEL[1:0] 00 These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB, and
IC shifted respectively by −90°. See Table 51.
00: 3-phase four wires with three voltage sensors.
01: 3-phase three wires delta connection.
10: 3-phase four wires with two voltage sensors.
11: 3-phase four wires delta connection.
6 REVAPSEL 0 0: The total active power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB), and on
Phase C triggers Bit 8 (REVAPC). This bit is always 0 for the ADE7854, ADE7858, and ADE7868.
1: The fundamental active power on each phase is used to trigger a bit in the STATUS0
register as follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB),
and on Phase C triggers Bit 8 (REVAPC).
7 REVRPSEL 0 0: The total reactive power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A triggers Bit 10 (REVRPA), on Phase B triggers Bit 11 (REVRPB), and on
Phase C triggers Bit 12 (REVRPC). This bit is always 0 for the ADE7854, ADE7858, and
ADE7868.
1: The fundamental reactive power on each phase is used to trigger a bit in the STATUS0
register as follows: on Phase A triggers Bit 10 (REVRPA), on Phase B triggers Bit 11 (REVRPB),
and on Phase C triggers Bit 12 (REVRPC).

Table 51. CONSEL[1:0] Bits in Energy Registers

Energy Registers CONSEL[1:0] = 00 CONSEL[1:0] = 01 CONSEL[1:0] = 10 CONSEL[1:0] = 11
AWATTHR, AFWATTHR VA × IA VA × IA VA × IA VA × IA
BWATTHR, BFWATTHR VB × IB 0 VB = −VA − VC VB = −VA
VB × IB VB × IB
CWATTHR, CFWATTHR VC × IC VC × IC VC × IC VC × IC
AVARHR, AFVARHR VA × IA’ VA × IA’ VA × IA’ VA × IA’
BVARHR, BFVARHR VB × IB’ 0 VB = −VA − VC VB = −VA
VB × IB’ VB × IB’
CVARHR, CFVARHR VC × IC’ VC × IC’ VC × IC’ VC × IC’
AVAHR VA rms × IA rms VA rms × IA rms VA rms × IA rms VA rms × IA rms
BVAHR VB rms × IB rms 0 VB rms × IB rms VB rms × IB rms
CVAHR VC rms × IC rms VC rms × IC rms VC rms × IC rms VC rms × IC rms
Table 52. LCYCMODE Register (Address 0xE702)

Bit
0 LWATT 0 0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.
1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.
1 LVAR 0 0: the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) are placed in regular
accumulation mode. This bit is always 0 for the ADE7854.
1: the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) are placed into line-
cycle accumulation mode.
2 LVA 0 0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular
accumulation mode.
1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle
accumulation mode.
3 ZXSEL[0] 1 0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
4 ZXSEL[1] 1 0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.
5 ZXSEL[2] 1 0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.
6 RSTREAD 1 0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,
LVAR, and LVA) are set to 1.
1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. This means a read of those registers resets them to 0.
7 Reserved 0 Reserved. This bit does not manage any functionality.
Table 53. HSDC_CFG Register (Address 0xE706)

Bit
0 HCLK 0 0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
1 HSIZE 0 0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
2 HGAP 0 0: no gap is introduced between packages.
1: a gap of seven HCLK cycles is introduced between packages.

Bit
4:3 HXFER[1:0] 00 00 = for ADE7854, HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV,
IBWV, VBWV, ICWV, and VCWV, one 32-bit word equal to 0, AVA, BVA, CVA, AWATT, BWATT,
and CWATT, three 32-bit words equal to 0. For ADE7858, HSDC transmits sixteen 32-bit
words in the following order: IAWV, VAWV, IBWV, VBWV, ICWV, and VCWV, one 32-bit word
equal to 0, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR. For the ADE7868
and ADE7878, HSDC transmits sixteen 32-bit words in the following order: IAWV, VAWV, IBWV,
VBWV, ICWV, VCWV, INWV, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.
01 = for the ADE7854 and ADE7858, HSDC transmits six instantaneous values of currents
and voltages: IAWV, VAWV, IBWV, VBWV, ICWV, and VCWV, and one 32-bit word equal to 0.
For the ADE7868 and ADE7878, HSDC transmits seven instantaneous values of currents and
voltages: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV, and INWV.
10 = for the ADE7854, HSDC transmits six instantaneous values of phase powers: AVA, BVA,
CVA, AWATT, BWATT, and CWATT and three 32-bit words equal to 0. For the ADE7858,
ADE7868, and ADE7878, HSDC transmits nine instantaneous values of phase powers: AVA,
BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and CVAR.
11 = reserved. If set, the ADE7854/ADE7858/ADE7868/ADE7878 behave as if HXFER[1:0] = 00.
5 HSAPOL 0 0: SS/HSA output pin is active low.
1: SS/HSA output pin is active high.
Table 54. LPOILVL Register (Address 0xEC00)1

2:0 LPOIL[2:0] 111 Threshold is put at a value corresponding to full scale multiplied by LPOIL/8.
7:3 LPLINE[4:0] 00000 The measurement period is (LPLINE + 1)/50 seconds.
1
The LPOILVL register is available only for the ADE7868 and ADE7878; it is reserved for ADE7854 and ADE7858.
Table 55. CONFIG2 Register (Address 0xEC01)

Bit
0 EXTREFEN 0 When this bit is 0, it signifies that the internal voltage reference is used in the ADCs.
When this bit is 1, an external reference is connected to the Pin 17 REFIN/OUT.
1 I2C_LOCK 0 When this bit is 0, the SS/HSA pin can be toggled three times to activate the SPI port. If I2C is
the active serial port, this bit must be set to 1 to lock it in. From this moment on, spurious
toggling of the SS/HSA pin and an eventual switch into using the SPI port is no longer possible. If
SPI is the active serial port, any write to CONFIG2 register locks the port. From this moment
on, a switch into using I2C port is no longer possible. Once locked, the serial port choice is
maintained when the ADE7854/ADE7858/ADE7868/ADE7878 change PSMx power modes.

OUTLINE DIMENSIONS
6.10 0.30
6.00 SQ 0.23
PIN 1 5.90 0.18
INDICATOR PIN 1
31 40
INDICATOR
30 1
0.50
BSC 4.45
EXPOSED
PAD 4.30 SQ
4.25
21 10
20 11
0.45 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE
05-06-2011-A
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 99. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm x 6 mm Body, Very Very Thin Quad
(CP-40-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADE7854ACPZ −40°C to +85°C 40-Lead LFCSP_WQ CP-40-10
ADE7854ACPZ-RL −40°C to +85°C 40-Lead LFCSP_WQ, 13” Tape and Reel CP-40-10
1
Z = RoHS Compliant Part.

NOTES

NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
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Polyphase Multifunction Energy Metering IC

with Harmonic and Fundamental Information

Rev. H Document Feedback

Thermal Resistance .................................................................... 15 Apparent Power Calculation ..................................................... 57

ESD Caution ................................................................................ 15 Waveform Sampling Mode ....................................................... 60

Pin Configuration and Function Descriptions ........................... 16 Energy-to-Frequency Conversion............................................ 60

Typical Performance Characteristics ........................................... 18 No Load Condition .................................................................... 64

Test Circuit ...................................................................................... 21 Checksum Register..................................................................... 65

Terminology .................................................................................... 22 Interrupts ..................................................................................... 66

Power Management ........................................................................ 23 Serial Interfaces .......................................................................... 68

PSM1—Reduced Power Mode (ADE7868, ADE7878 Only) 23 Layout Guidelines....................................................................... 75

PSM3—Sleep Mode (All Parts) ................................................ 24 ADE7878 Evaluation Board ...................................................... 76

Power-Up Procedure .................................................................. 26 Die Version .................................................................................. 76

Hardware Reset ........................................................................... 27 Silicon Anomaly ............................................................................. 77

Software Reset Functionality .................................................... 27 ADE7854/ADE7858/ADE7868/ADE7878 Functionality

Rev. H | Page 2 of 100

Rev. H | Page 4 of 100

RESET REFIN/OUT VDD AGND AVDD DVDD DGND

Rev. H | Page 5 of 100

Figure 1. ADE7854 Functional Block Diagram

Rev. H | Page 6 of 100

Figure 2. ADE7858 Functional Block Diagram

RESET REFIN/OUT VDD AGND AVDD DVDD DGND

Rev. H | Page 7 of 100

Figure 3. ADE7868 Functional Block Diagram

Rev. H | Page 8 of 100

Figure 4. ADE7878 Functional Block Diagram

Rev. H | Page 9 of 100

Rev. H | Page 11 of 100

Table 3. I2C-Compatible Interface Timing Parameter

Figure 5. I2C-Compatible Interface Timing

Rev. H | Page 12 of 100

MISO MSB INTERMEDIATE BITS LSB

MOSI MSB IN LSB IN

Figure 6. SPI Interface Timing

Rev. H | Page 13 of 100

tSH tSF tSR

HSD MSB INTERMEDIATE BITS LSB

Figure 7. HSDC Interface Timing

Figure 8. Load Circuit for Timing Specifications

Rev. H | Page 14 of 100

ABSOLUTE MAXIMUM RATINGS

Rev. H | Page 15 of 100

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 9. Pin Configuration

Table 8. Pin Function Descriptions

Rev. H | Page 16 of 100

Rev. H | Page 17 of 100

TYPICAL PERFORMANCE CHARACTERISTICS

45 50 55 60 65 0.01 0.1 1 10 100

0.01 0.1 1 10 100 45 50 55 60 65

Rev. H | Page 18 of 100

45 50 55 60 65 0.01 0.1 1 10 100

Rev. H | Page 19 of 100

Rev. H | Page 20 of 100

Rev. H | Page 21 of 100

Rev. H | Page 22 of 100

Rev. H | Page 23 of 100

Figure 25. PSM2 Low Power Mode Peak Detection

Rev. H | Page 24 of 100

Table 12. Recommended Actions When Changing Power Modes

Rev. H | Page 25 of 100

VDD 2.0V ± 10% ADE78xx