Falcon Xbox PDF

CR-1 : @FALCON_LIB.
FALCON(SCH_1):PAGE1
SCHEMATIC REV PCBA NUMBER REV BOM RELEASE DATE

1.0 X8XXXXX-001 D XX/XX/06
PAGE CONTENTS PAGE CONTENTS
[1] COVER PAGE [33] SB, PCIEX + SMM GPIO + JTAG
[2] CLOCK DIAGRAM [34] SB, SMC
[3] RESET/ENABLE DIAGRAM [35] SB, FLASH + USB + SPI
[4] CPU, CLOCKS + EEPROM + STRAPPING [36] SB, ETHERNET + AUDIO + SATA
[5] CPU, FSB [37] SB, STANDBY POWER + DECOUPLE
[6] CPU, FSB POWER + PLL POWER [38] SB, MAIN POWER + DECOUPLE
[7]
[8]
[9]
[10]
CPU, CORE POWER
CPU, POWER
CPU, DECOUPLING
CPU, DECOUPLING
[39]
[40]
[41]
[42]
SB OUT, ETHERNET
SB OUT, AUDIO
SB OUT, FLASH
SB OUT, FAN + INFRARED + BUTTONS
FALCON
[11]
[12]
CPU, DECOUPLING
GPU, FSB
[43]
[44]
CONN, AVIP
CONN, RJ45 + USB COMBO
RETAIL
[13]
[14]
GPU, VIDEO + PCIEX + EEPROM
GPU, MEMORY CONTROLLER A + B
[45]
[46]
CONN, GAME PORTS + MEMORY PORTS
MISC, V_5P0 DUAL, DEBUG MAPPING REV 1.0
[15]
[16]
GPU, MEMORY CONTROLLER C + D
GPU, PLL POWER + FSB POWER
[47]
[48]
CONN, ODD AND HDD
CONN, ARGON + POWER FAB D
[17] GPU, CORE POWER + MEM POWER [49] VREGS, INPUT + OUTPUT FILTERS
[18] GPU, DECOUPLING [50] VREGS, CPU CONTROLLER
[19] MEMORY, A (TOP) [51] VREGS, GPU OUTPUT PHASE 1,2,3
[20] MEMORY, A MIRRORED (BOTTOM) [52] VREGS, GPU CONTROLLER
[21] MEMORY, B (TOP) [53] VREGS, GPU OUTPUT PHASE 1,2
[22] MEMORY, B MIRRORED (BOTTOM) [54] VREGS, SWITCHED 1.8, 5.0V
[23] MEMORY, C (TOP) [55] VREGS, LINEAR REGULATORS
[24] MEMORY, C MIRRORED (BOTTOM) [56] XDK, DEBUG CONN
[25] MEMORY, D (TOP) [57] DEBUG BOARD, CPU + GPU BREAKOUT
[26] MEMORY, D MIRRORED (BOTTOM) [58] DEBUG BOARD, CPU CONN
[27] HANA, CLOCKS + STRAPPING [59] DEBUG BOARD, CPU CONN + TERM
[28] HANA, VIDEO + FAN + JTAG [60] DEBUG BOARD, CPU TERM
[29] CONN, HDMI [61] DEBUG BOARD, TITAN + YETI CONN
[30] HANA, POWER + DECOUPLING [62] DEBUG BOARD, GPU CONN + TERM
[31] HANA, POWER + DECOUPLING [63] XDK, LEDS, BDCM PHY
[32] POWER TRACE EMI CAPS [64] LABELS AND MOUNTING, PCI SWIZ
[65-6] MEM QUAL BOARDS
RULES:
1.)
2.)
3.)
(APPLIED WHEN POSSIBLE)
MSB TO LSB IS TOP TO BOTTOM
WHEN POSSIBLE: INPUTS ON LEFT,
ORDER OF PAGES=CHIP INTERFACES,
OUTPUTS ON RIGHT
TERMINATION, POWER, DECOUPLING PLEASE
FALCON
REFER TO THE XENON DESIGN SPEC
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS BOM RELEASE DATE XX/XX/06 PB NUMBER X80XXXX-00X
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE SIGNATURE DATE
10.)
12.)
13.)
SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
SUFFIX _P FOR P JUNCTION
SUFFIX _EN FOR ENABLE
DRN BY MICROSOFT XBOX
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS CHK BY TITLE
15.) PWRGD FOR POWER GOOD SCH, PBA, FALCON
ENGR
APVD
DRAWING
FALCON_FABD APVD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=COVER PAGE] Tue May 08 18:21:43 2007 APVD
CONFIDENTIAL
FALCON_RETAIL 1/82 1.0
CR-2 : @FALCON_LIB.FALCON(SCH_1):PAGE2
RJ45/USB AVIP
CONN CONN
FAN
CONN
* THIS IS OUT OF DATE * POWER
CONN
ENET
ENET_CLK(25MHZ) CLOCK DIAGRAM
PHY
I2S_MCLK(12.288MHZ) AUDIO ANA_XTAL_IN(27MHZ)

I2S_BCLK(3.072MHZ) DAC
GPU VR
DEBUG
CONN ANA
ANA
BCKUP
STBY_CLK(48MHZ) GPU VR
CNTL
SB SATA_CLK_REF(25MHZ)
SATA_CLK_DP/DN(100MHZ)
DVD PCIEX_CLK_DP/DN(100MHZ)
SATA AUD_CLK(24.576MHZ)
CONN CPU_CLK_DP/DN(100MHZ) RISCWATCH
PIX_CLK_OUT_DP/DN(100MHZ) CONN
GPU_CLK_DP/DN (100MHZ)
DVD
PWR
CONN MC_CLK1_DP/DN(800MHZ)
MC_CLK0_DP/DN(800MHZ)
ANA
BCKUP MEM
CLAM C+D
MD_CLK1_DP/DN(800MHZ)
MD_CLK0_DP/DN(800MHZ)
GPU CPU CPU
VR
MA_CLK1_DP/DN(800MHZ)
MA_CLK0_DP/DN(800MHZ)
MB_CLK1_DP/DN(800MHZ)
MB_CLK0_DP/DN(800MHZ)
1P8 VR
FLSH
HDD
CONN
TITAN JTAG
3P3 VR CONN
VMEM VR MEM EFUSE VR

CLAM A+B CPU VR
5P0 VR CNTL
MPORT VR
GAME
CONN
IR EJECT MEM MEM BIND ARGON

SW CONN CONN SW CONN
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
<PAGE_TITLE=CLOCK DIAGRAM> Tue May 08 11:47:32 2007
CONFIDENTIAL
RJ45/USB AVIP
CONN CONN POWER
FAN CONN
CONN
RESET/ENABLE DIAGRAM
EXT_PWR_ON_N
ENET AUD_CLAMP
PHY ENET_RST_N AUDIO PSU_V12P0_EN
AUD_RST_N DAC
GPU VR
HANA_CLK_OE
HANA_RST_N
HANA VREG_GPU_EN_N
GPU VR
CNTL
SMC_RST_N
SB_RST_N
DVD
SATA
SB VREG_GPU_PWRGD
EXT_PWR_ON_N
CONN CPU_CHECKSTOP_N
CPU_RST_N
CPU_PWRGD
GPU_RST_N RISCWATCH
DVD GPU_RST_DONE CONN
PWR
SMC_DBG_EN
CONN
VREG_CPU_PWRGD
CPU
VREG_3P3_EN
MEM_RST VR
MEM_SCAN_EN
MEM
CLAM C+D
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN
GPU CPU
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN
MEM_SCAN_EN
HDD 3P3 MEM_RST
CONN VR
CPU_PWRGD
TITAN JTAG
MEM CONN
DEBUG CLAM A+B
CONN VREG_1P8_EN_N VMEM VR EFUSE VR
VREG_5P0_EN_N CPU VR
5P0 VR CNTL
VREG_EFUSE_EN
VREG_CPU_EN
GAME
CONN
IR EJECT MEM MEM BIND ARGON

SW CONN CONN SW CONN
DRAWING
[PAGE_TITLE=RESET/ENABLE DIAGRAM] Tue May 08 11:47:32 2007
CONFIDENTIAL
58 OUT CPU_RST_V1P1_N
34 CPU_RST_N 1 R7R4 2
CPU, CLOCKS + EEPROM + STRAPPING
IN
3.92K 1% R6D4
402 CH 1 27 IN CPU_CLK_DP 1 2
1 1 R7R16 2 C7R112
FT2P11 FTP 360PF 0 5% CPU_CLK_DP_C
6.19K 1% 10% 402 CH
1 50V
FT2P12 FTP 402 CH 2 EMPTY
603
CPU_PWRGD 1 R7R10 2 R6D5
34 IN CPU_PWRGD_V1P1_N
27 IN CPU_CLK_DN1 2
3.92K 1%
402 CH 0 5%
V_GPUCORE 1 R7R11 2 1 402 CH
C7R113
360PF U7D1 1 OF 10 IC
6.19K 1% 10%
V_GPUCORE 402 CH 50V CPU_CLK_DN_C TP7R1
2 R6R4 1
2 EMPTY LOKI
PROBE
603 AG23 AH15 CPU_CORE_IF_BGR_PLL 1
CORE_CLK_DP CORE_IF_BGR_PLL
1K 5% TP6D1 AF23 CORE_CLK_DN 2
1 1 402 CH PROBE
R6R6 1 AF1 C7 VREG_EFUSE_EN SMT
R6R9 2 HARD_RESET_B EFU_POWERON OUT 56
10K 2 R6R5 1 AD14 POWER_GOOD
10K 5%
5% 1K 5% SMT
EMPTY 402 CH FSB_CLK_DP AH21 AF20 CPU_FSB_HF_CLKOUT_DP
CH 402 FSB_CLK_DP FSB_HF_CLKOUT_DP OUT
402 2 FSB_CLK_DN AH20 FSB_CLK_DN FSB_HF_CLKOUT_DN AG20 CPU_FSB_HF_CLKOUT_DN OUT
2
CPU_FSB_CLK_SEL AE16 FSB_CLK_SEL FSB_IMPED_CAL_DP AH23 CPU_FSB_IMPED_CAL_DP OUT
FSB_IMPED_CAL_DN AH22 CPU_FSB_IMPED_CAL_DN OUT
1
CPU_EXT_CLK_EN AD16 EXT_CLK_EN
TP7R3
R6R8 CPU_PLL_BYPASS AF14 PROBE
1 PLL_BYPASS AH12 CPU_RES0_DP 1
10K RESISTOR0_DP
5% R6R7 1 CPU_PULSE_LIMIT_BYPASS AG14 RESISTOR0_DN AH13 CPU_RES0_DN 2
PULSE_LIMIT_BYPASS
EMPTY 10K R7R17 TP7R4
402 5% 10K 1 SMT PROBE
2 1 DB7R2
1
AF11 CPU_VDDS0_DP 1
CH 5% R7D1 VDDS0_DP
402 CH 10K R7D2 VDDS0_DN AH10 CPU_VDDS0_DN 2 TP7R2
2 402 5% 10K
5% V_GPUCORE PROBE
2 CH CPU_SYS_CONFIG0 AH3 SYS_CONFIG0 VDDS1_DP AG2 CPU_VDDS1_DP SMT 1
402 EMPTY CPU_SYS_CONFIG1 AE2 AH1 CPU_VDDS1_DN 2
402 SYS_CONFIG1 VDDS1_DN
2 2
CPU_POST_IN<0..4> SMT DB7R1
0 AF8 POST_IN0
V_GPUCORE 1 1 AG8 POST_IN1
TP
1 AH7 PSRO0_OUT AE14 CPU_PSRO0_OUT 1
R7R15 2 POST_IN2
100 R7R8 V_CPUCORE 3 AH8 POST_IN3
100 AH9
1
5% 4 POST_IN4
5% R7R9
EMPTY
402 EMPTY 10K
2 402 1 CPU_SPI_SI C4 B4 CPU_SPI_CLK 5%
2 4 IN SPI_SI SPI_CLK OUT 4
CH
R7T18 SPI_EN A3 CPU_SPI_EN OUT 4 402
LAYOUT: MUST BE ACCESSIBLE 10K SPI_SO A4 CPU_SPI_SO 4 2 2
5% OUT
CH AH18 CPU_TEMP_P R6E1
402 TEMP_DP IN 28 10K
2 OUT CPU_ANL_1 AE22 ANL_1 TEMP_DN AH19 CPU_TEMP_N OUT 28 5%
OUT CPU_ANL_2 AD22 ANL_2 CH
VID0 C5 CPU_VREG_APS0 OUT 50 402
57 CPU_SRVID A2 SRVID VID1 B6 CPU_VREG_APS1 50
1
OUT CPU_VGATE AH14 A5 CPU_VREG_APS2 OUT
VGATE VID2 OUT 50
VID3 B5 CPU_VREG_APS3 OUT 50
V_1P8 CPU_TEST_EN AF2 TE VID4 A6 CPU_VREG_APS4 OUT 50
V_GPUCORE VID5 C6 CPU_VREG_APS5 50
OUT
1 R7R1 2 1 1 1 FTP FT7T5
R7R14 X806937-001 1 FTP FT7T2 1 FTP FT7T4
1.40K 1% FTP FT7T1 1
402 CH 10K 1 FTP FT7T3
5% FTP FT7T7
1 1 1 1 1 CH CPU R7R1 R7R2
1 R7R2 2 402
R7R21 R7R12 R7R13 R7R22 R7R23 2 LOKI 1.40K 1K V_MEM V_MEM
10K 10K 10K 10K 10K 1K 1% ASPEN EMPTY 10K
5% 5% 5% 5% 5% 402 CH
CH CH CH CH CH
402 402 402 402 402
2 2 2 2 2 1 1
V_MEM C6F1
.1UF R7F3
0 1 2 3 4 10% 10K
U7E1 EMPTY 6.3V
2 X5R 5%
1 1 1 1 1 AT25020A 402 EMPTY
4 CPU_SPI_CLK R6E2 CPU_SPI_CLK_R 6 SCK VCC 8 402
R7R20 R7R5 R7R3 R7R19 R7R18 IN 5 2
1K 5% CPU_SPI_SO_R SDI
10K 10K 10K 10K 10K 402 CH SDO 2 CPU_SPI_SI_R 2 R7F7 1 CPU_SPI_SI 4
5% 5% 5% 5% 5% 7
OUT
HOLD_N* 1K 5%
EMPTY EMPTY EMPTY EMPTY EMPTY
4 CPU_SPI_SO R7E7 CPU_SPI_EN_R 1 CS_N* 402 CH
402 402 402 402 402 IN 3 4
1
2 2 2 2 2 1K 5% WP_N* GND
1 4 V_MEM 402 CH V_MEM R7F4
FT7R4 FTP 100
FT7R6 FTP
1 3
1 X800552-001 5%
2
FT7R2 FTP 2 R7E8 1 CH
FT7R1 FTP
1 1 1 402
FT7R5 FTP
1 0 R7U3 10K 5% 2
10K 402 CH
5%
CH 2 R7F1 1
402
2 R7F2 10K 5%
4 IN CPU_SPI_EN 402 EMPTY CPU_SPI_WP_N IN
1K 5%
402 CH
DRAWING
[PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] Tue May 08 18:24:08 2007
CONFIDENTIAL
CPU, FSB
U7D1 2 OF 10 IC
LOKI
12 IN FSB_GP_CP0_CLK_DP V28 GP_CP0_CLK_DP CP_GP0_CLK_DP AE27 FSB_CP_GP0_CLK_DP OUT 12

12 IN FSB_GP_CP0_CLK_DN V27 GP_CP0_CLK_DN CP_GP0_CLK_DN AE28 FSB_CP_GP0_CLK_DN OUT 12
12 IN FSB_GP_CP0_FLAG_DP AB27 GP_CP0_FLAG_DP CP_GP0_FLAG_DP AH25 FSB_CP_GP0_FLAG_DP OUT 12

12 IN FSB_GP_CP0_FLAG_DN AB28 GP_CP0_FLAG_DN CP_GP0_FLAG_DN AH26 FSB_CP_GP0_FLAG_DN OUT 12
12 IN FSB_GP_CP0_DATA0_DP T26 GP_CP0_DATA0_DP CP_GP0_DATA0_DP AB26 FSB_CP_GP0_DATA0_DP OUT 12

12 IN FSB_GP_CP0_DATA0_DN T25 GP_CP0_DATA0_DN CP_GP0_DATA0_DN AB25 FSB_CP_GP0_DATA0_DN OUT 12
12 IN FSB_GP_CP0_DATA1_DP T28 GP_CP0_DATA1_DP CP_GP0_DATA1_DP AC27 FSB_CP_GP0_DATA1_DP OUT 12
12 IN FSB_GP_CP0_DATA1_DN T27 GP_CP0_DATA1_DN CP_GP0_DATA1_DN AC28 FSB_CP_GP0_DATA1_DN OUT 12
12 IN FSB_GP_CP0_DATA2_DP U27 GP_CP0_DATA2_DP CP_GP0_DATA2_DP AD28 FSB_CP_GP0_DATA2_DP OUT 12
12 IN FSB_GP_CP0_DATA2_DN U28 GP_CP0_DATA2_DN CP_GP0_DATA2_DN AD27 FSB_CP_GP0_DATA2_DN OUT 12
12 IN FSB_GP_CP0_DATA3_DP V26 GP_CP0_DATA3_DP CP_GP0_DATA3_DP AD25 FSB_CP_GP0_DATA3_DP OUT 12
12 IN FSB_GP_CP0_DATA3_DN V25 GP_CP0_DATA3_DN CP_GP0_DATA3_DN AD26 FSB_CP_GP0_DATA3_DN OUT 12
12 IN FSB_GP_CP0_DATA4_DP W27 GP_CP0_DATA4_DP CP_GP0_DATA4_DP AF28 FSB_CP_GP0_DATA4_DP OUT 12
12 IN FSB_GP_CP0_DATA4_DN W28 GP_CP0_DATA4_DN CP_GP0_DATA4_DN AF27 FSB_CP_GP0_DATA4_DN OUT 12
12 IN FSB_GP_CP0_DATA5_DP Y26 GP_CP0_DATA5_DP CP_GP0_DATA5_DP AF25 FSB_CP_GP0_DATA5_DP OUT 12
12 IN FSB_GP_CP0_DATA5_DN Y25 GP_CP0_DATA5_DN CP_GP0_DATA5_DN AF26 FSB_CP_GP0_DATA5_DN OUT 12
12 IN FSB_GP_CP0_DATA6_DP Y28 GP_CP0_DATA6_DP CP_GP0_DATA6_DP AG27 FSB_CP_GP0_DATA6_DP OUT 12
12 IN FSB_GP_CP0_DATA6_DN Y27 GP_CP0_DATA6_DN CP_GP0_DATA6_DN AG28 FSB_CP_GP0_DATA6_DN OUT 12
12 IN FSB_GP_CP0_DATA7_DP AA27 GP_CP0_DATA7_DP CP_GP0_DATA7_DP AH28 FSB_CP_GP0_DATA7_DP OUT 12
12 IN FSB_GP_CP0_DATA7_DN AA28 GP_CP0_DATA7_DN CP_GP0_DATA7_DN AH27 FSB_CP_GP0_DATA7_DN OUT 12
12 IN FSB_GP_CP1_CLK_DP E28 GP_CP1_CLK_DP CP_GP1_CLK_DP M28 FSB_CP_GP1_CLK_DP OUT 12

12 IN FSB_GP_CP1_CLK_DN E27 GP_CP1_CLK_DN CP_GP1_CLK_DN M27 FSB_CP_GP1_CLK_DN OUT 12
12 IN FSB_GP_CP1_FLAG_DP J26 GP_CP1_FLAG_DP CP_GP1_FLAG_DP R28 FSB_CP_GP1_FLAG_DP OUT 12

12 IN FSB_GP_CP1_FLAG_DN J25 GP_CP1_FLAG_DN CP_GP1_FLAG_DN R27 FSB_CP_GP1_FLAG_DN OUT 12
12 IN FSB_GP_CP1_DATA0_DP C26 GP_CP1_DATA0_DP CP_GP1_DATA0_DP J28 FSB_CP_GP1_DATA0_DP OUT 12

12 IN FSB_GP_CP1_DATA0_DN C25 GP_CP1_DATA0_DN CP_GP1_DATA0_DN J27 FSB_CP_GP1_DATA0_DN OUT 12
12 IN FSB_GP_CP1_DATA1_DP C28 GP_CP1_DATA1_DP CP_GP1_DATA1_DP K28 FSB_CP_GP1_DATA1_DP OUT 12
12 IN FSB_GP_CP1_DATA1_DN C27 GP_CP1_DATA1_DN CP_GP1_DATA1_DN K27 FSB_CP_GP1_DATA1_DN OUT 12
12 IN FSB_GP_CP1_DATA2_DP D27 GP_CP1_DATA2_DP CP_GP1_DATA2_DP L25 FSB_CP_GP1_DATA2_DP OUT 12
12 IN FSB_GP_CP1_DATA2_DN D28 GP_CP1_DATA2_DN CP_GP1_DATA2_DN L26 FSB_CP_GP1_DATA2_DN OUT 12
12 IN FSB_GP_CP1_DATA3_DP E26 GP_CP1_DATA3_DP CP_GP1_DATA3_DP L28 FSB_CP_GP1_DATA3_DP OUT 12
12 IN FSB_GP_CP1_DATA3_DN E25 GP_CP1_DATA3_DN CP_GP1_DATA3_DN L27 FSB_CP_GP1_DATA3_DN OUT 12
12 IN FSB_GP_CP1_DATA4_DP F27 GP_CP1_DATA4_DP CP_GP1_DATA4_DP N25 FSB_CP_GP1_DATA4_DP OUT 12
12 IN FSB_GP_CP1_DATA4_DN F28 GP_CP1_DATA4_DN CP_GP1_DATA4_DN N26 FSB_CP_GP1_DATA4_DN OUT 12
12 IN FSB_GP_CP1_DATA5_DP G26 GP_CP1_DATA5_DP CP_GP1_DATA5_DP N28 FSB_CP_GP1_DATA5_DP OUT 12
12 IN FSB_GP_CP1_DATA5_DN G25 GP_CP1_DATA5_DN CP_GP1_DATA5_DN N27 FSB_CP_GP1_DATA5_DN OUT 12
12 IN FSB_GP_CP1_DATA6_DP G28 GP_CP1_DATA6_DP CP_GP1_DATA6_DP P28 FSB_CP_GP1_DATA6_DP OUT 12
12 IN FSB_GP_CP1_DATA6_DN G27 GP_CP1_DATA6_DN CP_GP1_DATA6_DN P27 FSB_CP_GP1_DATA6_DN OUT 12
12 IN FSB_GP_CP1_DATA7_DP H27 GP_CP1_DATA7_DP CP_GP1_DATA7_DP R25 FSB_CP_GP1_DATA7_DP OUT 12
12 IN FSB_GP_CP1_DATA7_DN H28 GP_CP1_DATA7_DN CP_GP1_DATA7_DN R26 FSB_CP_GP1_DATA7_DN OUT 12
X806937-001
V_GPUCORE
1 1 1 1 1 1 1 1 1 1 1
C6R15 C6R18 C6R14 C6R25 C6R37 C6T19 C6T7 C6T27 C6T33 C6T32 C6R6
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402
DRAWING
[PAGE_TITLE=CPU, FSB] Tue May 08 18:24:09 2007
CONFIDENTIAL
CPU, FSB POWER + PLL POWER
V_1P8
V_CPUPLL V_GPUCORE
U7D1 4 of 10 IC
FB7R1 1 1 1 LOKI
1 2 C7R115 C7R116 C7R114 AA25
.1UF .1UF .1UF VDD_FSB0
1K FB 10% 10% 10% VDD_FSB1 AB24
0.2A 603 6.3V 6.3V 6.3V AC25
2 X5R 2 X5R 2 X5R VDD_FSB2
1 0.7DCR 1 402 402 402 VDD_FSB3 AD24
C7R1 C7R7 AE25
.1UF 2.2UF VDD_FSB4
10% 10% VDD_FSB5 AF24
6.3V 6.3V AG25
2 X5R 2 X5R VDD_FSB6
402 ST7R1 603 VDD_FSB7 AH24
1 2 VDD_FSB8 B11
V_EFUSE VDD_FSB9 B15
SHORT VDD_FSB10 B19
2 R7T2 1 VDD_FSB11 B23
CPU_VDDE
VDD_FSB12 B27
FB6D1 10K 5% VDD_FSB13 C24
1 2 402 CH AH4 D8
VDD_IO VDD_FSB14
1K FB VDD_FSB15 D12
0.2A 603 A7 VDDE VDD_FSB16 D16
1 0.7DCR 1 B7 VDDE_SEC VDD_FSB17 D20
C6D1 C6D4 D25
.1UF 2.2UF VDD_FSB18
10% 10% V_CPU_CORE_HF_VDDA_PLL AG17 CORE_HF_VDDA_PLL VDD_FSB19 E24
6.3V 6.3V AF17 F25
2 X5R 2 X5R V_CPU_CORE_HF_GNDA_PLL CORE_HF_GNDA_PLL VDD_FSB20
402 603 VDD_FSB21 G24
ST6D1 V_CPU_CORE_IF_VDDA_PLL AH17 CORE_IF_VDDA_PLL VDD_FSB22 H25
1 2 V_CPU_CORE_IF_GNDA_PLL AH16 CORE_IF_GNDA_PLL VDD_FSB23 J24
VDD_FSB24 K25
SHORT V_CPU_FSB_HF_VDDA_PLL AD20 FSB_HF_VDDA_PLL VDD_FSB25 L24
V_CPU_FSB_HF_GNDA_PLL AE20 FSB_HF_GNDA_PLL VDD_FSB26 M25
VDD_FSB27 N24
FB6R1 V_CPU_FSB_IF_VDDA_PLL AD18 FSB_IF_VDDA_PLL VDD_FSB28 P25
1 2 V_CPU_FSB_IF_GNDA_PLL AE18 FSB_IF_GNDA_PLL VDD_FSB29 R24
1K FB VDD_FSB30 T24
0.2A 603 V_CPU_VDDA_RNG AH11 VDDA_RNG VDD_FSB31 U25
1 0.7DCR 1 V_CPU_GNDA_RNG AG11 GNDA_RNG VDD_FSB32 V24
C6R2 C6R4 W25
.1UF 2.2UF VDD_FSB33
10% 10% VDD_FSB34 Y24
6.3V 6.3V
2 X5R 2 X5R
402 ST6R1 603
1 2
SHORT
FB6R2
1 2
1K FB
0.2A 603
1 0.7DCR 1
C6R3 C6R5
.1UF 2.2UF
10% 10% X806937-001
6.3V 6.3V
2 X5R 2 X5R
402 603
ST6R2
1 2
SHORT
FB7D1
1 2
1K FB
0.2A 603
0.7DCR 1
C7D1 C7D2
1UF 2.2UF
10% 10%
16V 6.3V
EMPTY 2 X5R
603 603
ST7D1
1 2
SHORT
DRAWING
[PAGE_TITLE=CPU, FSB POWER + PLL POWER] Tue May 08 18:24:09 2007
CONFIDENTIAL
CPU, CORE POWER
V_CPUCORE U7D1 IC V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE U7D1 IC V_CPUVCS

U7D1 IC
5 of 10 6 of 10 7 of 10
LOKI LOKI LOKI
AA2 VDD0 VDD48 AE6 K5 VDD96 VDD143 P7 V9 VDD190 VCS0 B1
AA4 VDD1 VDD49 AE8 K7 VDD97 VDD144 P9 V11 VDD191 VCS1 B3
AA6 VDD2 VDD50 AE10 K9 VDD98 VDD145 P11 V13 VDD192 VCS2 C1
AA8 VDD3 VDD51 AE12 K11 VDD99 VDD146 P13 V15 VDD193 VCS3 C2
AA10 VDD4 VDD52 AF4 K13 VDD100 VDD147 P15 V17 VDD194 VCS4 C3
AA12 VDD5 VDD53 AF7 K15 VDD101 VDD148 P17 V19 VDD195 VCS5 D1
AA18 VDD8 VDD56 AG3 K21 VDD104 VDD151 P23 W2 VDD198 VCS8 D5
AA20 VDD9 VDD57 AG6 K23 VDD105 VDD152 R2 W4 VDD199 VCS9 E2
AA22 VDD10 VDD58 AG9 L2 VDD106 VDD153 R4 W6 VDD200 VCS10 E4
AB1 VDD11 VDD59 AG12 L4 VDD107 VDD154 R6 W8 VDD201 VCS11 E6
AB3 VDD12 VDD60 G2 L6 VDD108 VDD155 R8 W10 VDD202 VCS12 F1
AB11 VDD16 VDD64 G10 L14 VDD112 VDD159 R16 W18 VDD206
AB17 VDD19 VDD67 G16 L20 VDD115 VDD162 R22 Y1 VDD209
AB19 VDD20 VDD68 G18 L22 VDD116 VDD163 T1 Y3 VDD210
AB21 VDD21 VDD69 G20 M1 VDD117 VDD164 T3 Y5 VDD211
AB23 VDD22 VDD70 G22 M3 VDD118 VDD165 T5 Y7 VDD212
AC2 VDD23 VDD71 H1 M5 VDD119 VDD166 T7 Y9 VDD213
AC18 VDD31 VDD79 H17 M21 VDD127 VDD174 T23
AC20 VDD32 VDD80 H19 M23 VDD128 VDD175 U2
AC22 VDD33 VDD81 H21 N2 VDD129 VDD176 U4
AD1 VDD34 VDD82 H23 N4 VDD130 VDD177 U6
AD3 VDD35 VDD83 J2 N6 VDD131 VDD178 U8
AD19 VDD43 VDD91 J18 N22 VDD139 VDD186 V1
AD21 VDD44 VDD92 J20 P1 VDD140 VDD187 V3
AD23 VDD45 VDD93 J22 P3 VDD141 VDD188 V5
AE1 VDD46 VDD94 K1 P5 VDD142 VDD189 V7
AE4 VDD47 VDD95 K3
X806937-001 X806937-001
X806937-001
DRAWING
[PAGE_TITLE=CPU, CORE POWER] Tue May 08 18:24:10 2007
CONFIDENTIAL
CPU, POWER
U7D1 IC U7D1 IC
U7D1 IC
9 of 10 10 of 10
8 of 10
LOKI LOKI
LOKI
F22 VSS117 VSS175 L11 T4 VSS233 VSS291 Y20
AA1 VSS0 VSS58 AF3
F24 VSS118 VSS176 L13 T6 VSS234 VSS292 Y22
AA3 VSS1 VSS59 AF6
F26 VSS119 VSS177 L15 T8 VSS235
AA5 VSS2 VSS60 AF9
G1 VSS120 VSS178 L17 T10 VSS236
AA7 VSS3 VSS61 AF12
G3 VSS121 VSS179 L19 T12 VSS237
AA9 VSS4 VSS62 AF15
G5 VSS122 VSS180 L21 T14 VSS238
AA11 VSS5 VSS63 AF16
G7 VSS123 VSS181 L23 T16 VSS239
G9 VSS124 VSS182 M2 T18 VSS240
G11 VSS125 VSS183 M4 T20 VSS241
G13 VSS126 VSS184 M6 T22 VSS242
G15 VSS127 VSS185 M8 U1 VSS243
AA21 VSS10 VSS68 AG4
G17 VSS128 VSS186 M10 U3 VSS244
G19 VSS129 VSS187 M12 U5 VSS245
G21 VSS130 VSS188 M14 U7 VSS246
G23 VSS131 VSS189 M16 U9 VSS247
AB2 VSS14 VSS72 AG15
H2 VSS132 VSS190 M18 U11 VSS248
H4 VSS133 VSS191 M20 U13 VSS249
H6 VSS134 VSS192 M22 U15 VSS250
H8 VSS135 VSS193 M24 U17 VSS251
H10 VSS136 VSS194 M26 U19 VSS252
H12 VSS137 VSS195 N1 U21 VSS253
H14 VSS138 VSS196 N3 U23 VSS254
H16 VSS139 VSS197 N5 U24 VSS255
AB18 VSS22 VSS80 B2
H18 VSS140 VSS198 N7 U26 VSS256
AB20 VSS23 VSS81 B9
H20 VSS141 VSS199 N9 V2 VSS257
AB22 VSS24 VSS82 B13
H22 VSS142 VSS200 N11 V4 VSS258
AC1 VSS25 VSS83 B17
H24 VSS143 VSS201 N13 V6 VSS259
AC3 VSS26 VSS84 B21
H26 VSS144 VSS202 N15 V8 VSS260
AC5 VSS27 VSS85 B25
J1 VSS145 VSS203 N17 V10 VSS261
AC7 VSS28 VSS86 B28
J3 VSS146 VSS204 N19 V12 VSS262
AC9 VSS29 VSS87 D2
J5 VSS147 VSS205 N21 V14 VSS263
AC11 VSS30 VSS88 D6
J7 VSS148 VSS206 N23 V16 VSS264
AC13 VSS31 VSS89 D10
J9 VSS149 VSS207 P2 V18 VSS265
J11 VSS150 VSS208 P4 V20 VSS266
J13 VSS151 VSS209 P6 V22 VSS267
J15 VSS152 VSS210 P8 W1 VSS268
J17 VSS153 VSS211 P10 W3 VSS269
J19 VSS154 VSS212 P12 W5 VSS270
AC24 VSS37 VSS95 E1
J21 VSS155 VSS213 P14 W7 VSS271
AC26 VSS38 VSS96 E3
J23 VSS156 VSS214 P16 W9 VSS272
AD2 VSS39 VSS97 E5
K2 VSS157 VSS215 P18 W11 VSS273
AD4 VSS40 VSS98 E7
K4 VSS158 VSS216 P20 W13 VSS274
AD6 VSS41 VSS99 E9
K6 VSS159 VSS217 P22 W15 VSS275
AD8 VSS42 VSS100 E11
K8 VSS160 VSS218 P24 W17 VSS276
K10 VSS161 VSS219 P26 W19 VSS277
K12 VSS162 VSS220 R1 W21 VSS278
AE3 VSS45 VSS103 E17
K14 VSS163 VSS221 R3 W23 VSS279
K16 VSS164 VSS222 R5 W24 VSS280
K18 VSS165 VSS223 R7 W26 VSS281
K20 VSS166 VSS224 R9 Y2 VSS282
AE11 VSS49 VSS107 F2
K22 VSS167 VSS225 R11 Y4 VSS283
K24 VSS168 VSS226 R13 Y6 VSS284
K26 VSS169 VSS227 R15 Y8 VSS285
L1 VSS170 VSS228 R17 Y10 VSS286
L3 VSS171 VSS229 R19 Y12 VSS287
L5 VSS172 VSS230 R21 Y14 VSS288
L7 VSS173 VSS231 R23 Y16 VSS289
L9 VSS174 VSS232 T2 Y18 VSS290
VSS116 F20
X806937-001 X806937-001
X806937-001
DRAWING
[PAGE_TITLE=CPU, POWER] Tue May 08 18:24:10 2007
CONFIDENTIAL
V_CPUCORE CPU, DECOUPLING
C7T94 C7E6 C7R3 C7R27 C6R7

1 2 1 2 1 2 1 2 1 2
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
EMPTY X5R X5R X5R X5R
805 805 805 805 805
C7T93 C7D12 C7E1 C7D8 C6R10

1 2 1 2 1 2 1 2 1 2
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
EMPTY X5R X5R X5R X5R
805 805 805 805 805
C7R119
C7T33 C7D19 1 2 C7D4 C7R28
1 2 1 2 1 2 1 2
4.7UF 10%
4.7UF 10% 4.7UF 10% 6.3V 4.7UF 10% 4.7UF 10%
6.3V 6.3V EMPTY 6.3V 6.3V
X5R EMPTY 805 X5R X5R
805 805 805 805
C7D18
C7R2 C7D3 C7R90 1 2 C7R29
1 2 1 2 1 2 1 2
4.7UF 10%
4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 4.7UF 10%
6.3V 6.3V 6.3V EMPTY 6.3V
X5R X5R X5R 805 X5R
805 805 805 805
C7E2
C7R120 1 2 C7D7 C7T4
C7E10 1 2 1 2 1 2
1 2
4.7UF 10%
4.7UF 10% 6.3V 4.7UF 10% 4.7UF 10%
4.7UF 10% 6.3V X5R 6.3V 6.3V
6.3V EMPTY 805 X5R X5R
EMPTY 805 805 805
805
C7T32 C7E5 C7T83 C7R91

1 2 1 2 1 2 1 2
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R
805 805 805 805
C7R26 C7D5 C7D11 C7T5

1 2 1 2 1 2 1 2
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

6.3V 6.3V 6.3V 6.3V
X5R EMPTY X5R X5R
805 805 805 805
C7E9 C7R121 C7T84 C7R5

1 2 1 2 1 2 1 2
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

6.3V 6.3V 6.3V 6.3V
EMPTY EMPTY X5R X5R
805 805 805 805
C7T1 C7R23 C6T1 C7R4

1 2 1 2 1 2 1 2
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R
805 805 805 805
C7R30 C7R25
C7T6 C7R24 1 2 1 2
1 2 1 2
4.7UF 10% 4.7UF 10%
4.7UF 10% 4.7UF 10% 6.3V 6.3V
6.3V 6.3V X5R X5R
X5R X5R 805 805
805 805
DRAWING
[PAGE_TITLE=CPU, DECOUPLING] Tue May 08 18:24:11 2007
CONFIDENTIAL
V_CPUCORE
CPU, DECOUPLING
C7R49 C7T9 C6R44 C7R52 C6T10 C7T21

1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402
C7R44 C7R22 C6R32 C7R51 C7T22 C6T2

1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402
C6R29 C7R35 C7R102 C7R50 C7T27 C7T10

1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402
C6R28 C7R34 C7R81 C6T6 C7R48 C7R111

1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402
C6R17 C7R19 C7R68 C6R36 C7T51

1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
C7R76 C7R43 C7R69 C6R23 C7T37

1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
C6R39 C6R16 C7R57 C7R58 C7R89

1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
C6R42 C6R19 C6R20 C7R59 C6T25

1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
C7R67 C7R61 C6R21 C7R60 C7R99

1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
C7T3 C6R35 C6T26 C7T2 C7R100

1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
DRAWING
CONFIDENTIAL
CPU, DECOUPLING
V_CPUCORE V_CPUVCS
N:EMPTIES
C7R31 C7T25 C7T38 C7T58 C6T17 C7R66 C7T7 C7T29

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R
402 402 402 402 402 402 402 402
C7T54 C6T24 C7R110 C6R24 C7R95 C6T4 C7T14 C7T30

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402
C6T16 C6T13 C6T14 C7T56 C6T18 C7T15 C7T12 C7T31

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402
C7R56 C7R20 C7T28 C7T50 C7R101 C7T24 C7T13

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
C6R26 C7R42 C7R14 C7R106 C7T57 C6T11 C7T8

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402
C6T9 C7R41 C7T49 C7T11 C7T55 C7R74 C7T16

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402
C6T3 C7R40 C6T22 C7T40 C7R83 C6R30 C7T17

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402
C7R21 C7R39 C7T41 C7R75 C7T39 C7R82 C7T18

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402
C6R41 C6T21 C7R33 C7T47 C7T26 C7T23 C7T19

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402
C6R13 C6R12 C7R32 C7T46 C7T48 C7R65 C7T20

1 2 1 2 1 2 1 2 1 2 1 2 1 2
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402
DRAWING
CONFIDENTIAL
V_MEM
V_GPUCORE GPU, FSB

MEM SCAN BUFFERS
STUFFED EMPTY
2 R5C12 1 V_MEM R2R5: 10K 0OHM
1 R2E5 2
1K 5% 1
1 402 CH 0 5%
C2E4 402 CH R2R5
R5R1 U4D1 1 OF 12 IC 1 2 0
1K 2 R5C11 1 5%
5% GPU Y2 VERSION 1 .1UF 10% CH
1K 5% 6.3V U2E2 EMPTY 402
EMPTY 402 CH X5R
402 FSB_BYPCLK_DP B29 FSB_BYPCLK_DP SN74LVC1G125
2
2 402
FSB_BYPCLK_DN A29 FSB_BYPCLK_DN 5
FSB_BYPCLK_SEL D25 VCC 25 26
FSB_BYPCLK_SEL MEM_SCAN_EN_BUFF 2 4 MEM_SCAN_EN
13 IN IN OUT OUT 19 20 21
1 FSB_CP_GP0_CLK_DP J34 P33 FSB_GP_CP0_CLK_DP 3 GND OE_N 1 22 23 24
5 IN CP_GP0_CLK_DP GP_CP0_CLK_DP OUT 5
R5R2 5 IN FSB_CP_GP0_CLK_DN J33 CP_GP0_CLK_DN GP_CP0_CLK_DN P34 FSB_GP_CP0_CLK_DN OUT 5 1 1
1K 5 FSB_CP_GP0_FLAG_DP J30 CP_GP0_FLAG_DP GP_CP0_FLAG_DP L34 FSB_GP_CP0_FLAG_DP 5 X801565-001
5% IN FSB_CP_GP0_FLAG_DN J29 L33 FSB_GP_CP0_FLAG_DN OUT R4F8 R2D11
5 IN CP_GP0_FLAG_DN GP_CP0_FLAG_DN OUT 5
CH 1K 1K
402 5% 5%
2 5 IN FSB_CP_GP0_DATA0_DP M29 CP_GP0_DATA0_DP GP_CP0_DATA0_DP T29 FSB_GP_CP0_DATA0_DP OUT 5
FSB_CP_GP0_DATA0_DN M30 T30 FSB_GP_CP0_DATA0_DN CH CH
5 IN CP_GP0_DATA0_DN GP_CP0_DATA0_DN OUT 5 402 402
5 IN FSB_CP_GP0_DATA1_DP L32 CP_GP0_DATA1_DP GP_CP0_DATA1_DP T31 FSB_GP_CP0_DATA1_DP OUT 5 2 2
5 IN FSB_CP_GP0_DATA1_DN L31 CP_GP0_DATA1_DN GP_CP0_DATA1_DN T32 FSB_GP_CP0_DATA1_DN OUT 5
5 IN FSB_CP_GP0_DATA2_DP K33 CP_GP0_DATA2_DP GP_CP0_DATA2_DP R34 FSB_GP_CP0_DATA2_DP OUT 5
5 IN FSB_CP_GP0_DATA2_DN K34 CP_GP0_DATA2_DN GP_CP0_DATA2_DN R33 FSB_GP_CP0_DATA2_DN OUT 5
5 IN FSB_CP_GP0_DATA3_DP L30 CP_GP0_DATA3_DP GP_CP0_DATA3_DP R29 FSB_GP_CP0_DATA3_DP OUT 5
5 IN FSB_CP_GP0_DATA3_DN L29 CP_GP0_DATA3_DN GP_CP0_DATA3_DN R30 FSB_GP_CP0_DATA3_DN OUT 5
5 IN FSB_CP_GP0_DATA4_DP J31 CP_GP0_DATA4_DP GP_CP0_DATA4_DP N34 FSB_GP_CP0_DATA4_DP OUT 5
5 IN FSB_CP_GP0_DATA4_DN J32 CP_GP0_DATA4_DN GP_CP0_DATA4_DN N33 FSB_GP_CP0_DATA4_DN OUT 5
5 IN FSB_CP_GP0_DATA5_DP K30 CP_GP0_DATA5_DP GP_CP0_DATA5_DP P29 FSB_GP_CP0_DATA5_DP OUT 5
5 IN FSB_CP_GP0_DATA5_DN K29 CP_GP0_DATA5_DN GP_CP0_DATA5_DN P30 FSB_GP_CP0_DATA5_DN OUT 5
5 IN FSB_CP_GP0_DATA6_DP H34 CP_GP0_DATA6_DP GP_CP0_DATA6_DP N31 FSB_GP_CP0_DATA6_DP OUT 5
5 FSB_CP_GP0_DATA6_DN H33 CP_GP0_DATA6_DN GP_CP0_DATA6_DN N32 FSB_GP_CP0_DATA6_DN 5 V_MEM
IN FSB_CP_GP0_DATA7_DP H31 M34 FSB_GP_CP0_DATA7_DP OUT 1 R2D12 2
5 IN CP_GP0_DATA7_DP GP_CP0_DATA7_DP OUT 5
5 IN FSB_CP_GP0_DATA7_DN H32 CP_GP0_DATA7_DN GP_CP0_DATA7_DN M33 FSB_GP_CP0_DATA7_DN OUT 5 0 5%
C2R12 402 CH
5 IN FSB_CP_GP1_CLK_DP V33 CP_GP1_CLK_DP GP_CP1_CLK_DP AC33 FSB_GP_CP1_CLK_DP OUT 5 1 2
5 IN FSB_CP_GP1_CLK_DN V34 CP_GP1_CLK_DN GP_CP1_CLK_DN AC34 FSB_GP_CP1_CLK_DN OUT 5
FSB_CP_GP1_FLAG_DP T33 Y29 FSB_GP_CP1_FLAG_DP .1UF 10%
5 IN CP_GP1_FLAG_DP GP_CP1_FLAG_DP OUT 5 6.3V U2D1 EMPTY
5 IN FSB_CP_GP1_FLAG_DN T34 CP_GP1_FLAG_DN GP_CP1_FLAG_DN Y30 FSB_GP_CP1_FLAG_DN OUT 5 X5R
402 SN74LVC1G125
5 IN FSB_CP_GP1_DATA0_DP AA31 CP_GP1_DATA0_DP GP_CP1_DATA0_DP AC28 FSB_GP_CP1_DATA0_DP OUT 5 5 VCC
5 IN FSB_CP_GP1_DATA0_DN AA32 CP_GP1_DATA0_DN GP_CP1_DATA0_DN AC29 FSB_GP_CP1_DATA0_DN OUT 5 13 IN MEM_SCAN_TOP_EN_BUFF 2 IN OUT 4 MEM_SCAN_TOP_EN OUT 19 21 23
5 IN FSB_CP_GP1_DATA1_DP Y33 CP_GP1_DATA1_DP GP_CP1_DATA1_DP AD29 FSB_GP_CP1_DATA1_DP OUT 5 3 GND OE_N 1 25
5 IN FSB_CP_GP1_DATA1_DN Y34 CP_GP1_DATA1_DN GP_CP1_DATA1_DN AD30 FSB_GP_CP1_DATA1_DN OUT 5 1 1
5 IN FSB_CP_GP1_DATA2_DP W30 CP_GP1_DATA2_DP GP_CP1_DATA2_DP AD34 FSB_GP_CP1_DATA2_DP OUT 5 R4F7 R2T2
FSB_CP_GP1_DATA2_DN W29 AD33 FSB_GP_CP1_DATA2_DN X801565-001
5 IN CP_GP1_DATA2_DN GP_CP1_DATA2_DN OUT 5 1K 1K
5 IN FSB_CP_GP1_DATA3_DP W33 CP_GP1_DATA3_DP GP_CP1_DATA3_DP AB29 FSB_GP_CP1_DATA3_DP OUT 5 5% 5%
5 IN FSB_CP_GP1_DATA3_DN W34 CP_GP1_DATA3_DN GP_CP1_DATA3_DN AB30 FSB_GP_CP1_DATA3_DN OUT 5 CH CH
5 IN FSB_CP_GP1_DATA4_DP V29 CP_GP1_DATA4_DP GP_CP1_DATA4_DP AC32 FSB_GP_CP1_DATA4_DP OUT 5 402 402
5 FSB_CP_GP1_DATA4_DN V28 CP_GP1_DATA4_DN GP_CP1_DATA4_DN AC31 FSB_GP_CP1_DATA4_DN 5
2 2
IN FSB_CP_GP1_DATA5_DP V31 AA29 FSB_GP_CP1_DATA5_DP OUT
5 IN CP_GP1_DATA5_DP GP_CP1_DATA5_DP OUT 5
5 IN FSB_CP_GP1_DATA5_DN V32 CP_GP1_DATA5_DN GP_CP1_DATA5_DN AA30 FSB_GP_CP1_DATA5_DN OUT 5
5 IN FSB_CP_GP1_DATA6_DP U33 CP_GP1_DATA6_DP GP_CP1_DATA6_DP AB33 FSB_GP_CP1_DATA6_DP OUT 5
5 IN FSB_CP_GP1_DATA6_DN U34 CP_GP1_DATA6_DN GP_CP1_DATA6_DN AB34 FSB_GP_CP1_DATA6_DN OUT 5
V_GPUCORE 5 FSB_CP_GP1_DATA7_DP U30 CP_GP1_DATA7_DP GP_CP1_DATA7_DP AA34 FSB_GP_CP1_DATA7_DP 5
IN FSB_CP_GP1_DATA7_DN U29 AA33 FSB_GP_CP1_DATA7_DN OUT
5 IN CP_GP1_DATA7_DN GP_CP1_DATA7_DN OUT 5
1 R4R9 2 FSB_IMPED_CAL T28 FSB_IMPED_PCAL
49.9 1% FSB_IMPED_NCAL AA28 FSB_IMPED_NCAL
1
402 EMPTY
R5R3 1 V_MEM
4.87K C4R70
1% 1000PF X02125-001 V_MEM
GPU R5R3 R4R9 10% 1 R2R6 2
CH 50V
B13L STUFF EMPTY 402 2 X7R
2 402 0 5% 1 1
GUNGA EMPTY STUFF C2D5 402 CH
1 2 R4U6 R2T1
1K 1K
.1UF 10% 5% 5%
6.3V U2R1 EMPTY
X5R CH CH
402 SN74LVC1G125 402 402
2 2
5 VCC
V_GPUCORE 13 MEM_SCAN_BOT_EN_BUFF 2 IN OUT 4 20 22 24
FSB DECOUPLING IN MEM_SCAN_BOT_EN OUT 26
3 GND OE_N 1
X801565-001
C4R27 C4R33 C4R45 C4T22 C5R18 C4R65 C4R60 C4T13

.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 13 IN GPU_SCAN_BUFF_EN_N
X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402
DRAWING
[PAGE_TITLE=GPU, FSB] Tue May 08 18:24:13 2007
CONFIDENTIAL
GPU, VIDEO + PCIEX + EEPROM + JTAG

U4D1 2 OF 12 IC
GPU Y2 VERSION 1 C4D1
1 GPU_CLK_DP A25 1
1 2 PEX_GPU_SB_L1_DP OUT 33 58
FT2P14 FTP 27 IN NB_CLK_DP FTP FT2P13
27 IN GPU_CLK_DN A24 NB_CLK_DN .1UF 10%
6.3V
GPU_RST_N E11 D14 GPU_RST_DONE X5R
34 IN RST_IN_N* RST_DONE OUT 34 402
33 IN PEX_SB_GPU_L1_DP B27 PEX_RX1_DP PEX_TX1_DP B26 PEX_GPU_SB_L1_DP_C C4D2

33 IN PEX_SB_GPU_L1_DN A27 PEX_RX1_DN PEX_TX1_DN A26 PEX_GPU_SB_L1_DN_C 1 2 PEX_GPU_SB_L1_DN OUT 33 58
33 IN PEX_SB_GPU_L0_DP B23 PEX_RX0_DP PEX_TX0_DP B22 PEX_GPU_SB_L0_DP_C
PEX_SB_GPU_L0_DN A23 A22 PEX_GPU_SB_L0_DN_C
.1UF 10%
33 IN PEX_RX0_DN PEX_TX0_DN 6.3V
X5R
1 R5D1 2 PEX_PCAL A28 PEX_PCAL 402
562 1% 1 R5D2 2 B28 PEX_NCAL C4D3
PEX_NCAL
402 CH V_GPUPCIE B21 PEX_ICAL 1 2 PEX_GPU_SB_L0_DP 33 58
2K 1% B14 GPU_PIX_CLK_1X OUT
402 CH PIX_CLK_OUT OUT 28
D10 .1UF 10%
PIX_CLK_IN_DP PIX_DATA<14..0> 6.3V
C10 B17 OUT 28
1 R4R3 2 PEX_ICAL PIX_CLK_IN_DN PIX_DATA14 14 X5R
PIX_DATA13 A17 13 402
1.47K 1% V_MEM
PIX_DATA12 D16 12 C4D7
402 CH ANA_PIX_CLK_2X_DP B16 1 2 PEX_GPU_SB_L0_DN
27 IN PIX_DATA11 11 OUT 33 58
27 IN ANA_PIX_CLK_2X_DN PIX_DATA10 A16 10 1
GPU_TEMP_P C22 D15 9 .1UF 10%
28 IN NB_THERMD_P PIX_DATA9 R4D1 6.3V
28 OUT GPU_TEMP_N C23 NB_THERMD_N PIX_DATA8 B15 8 1K X5R
28 EDRAM_TEMP_P G14 ED_THERMD_P PIX_DATA7 A15 7 5% 402
IN EDRAM_TEMP_N G15 A14
28 ED_THERMD_N PIX_DATA6 6 EMPTY
OUT D13 402
PIX_DATA5 5
GPU R5D2 R5D1 R4R3 R4T1 R4R8 PIX_DATA4 B13 4 2
1 DB4D1
PIX_DATA3 A13 3 TP
B13L 2K, 1% 562, 1% 1.47K, 1% 40.2, 1% 40.2, 1% B12 2 1
PIX_DATA2
GUNGA 49.9, 1% EMPTY EMPTY 240, 1% 240, 1% A12 1
PIX_DATA1 R4D2
PIX_DATA0 D11 0 1K
5%
1 R3C28 2 GPU_TCLK_R VSYNC_OUT A11 GPU_VSYNC_OUT OUT 28 CH
IN 34 B11 GPU_HSYNC_OUT 402
HSYNC_OUT OUT 28
1.27K 1% 2
402 CH GPU_SPI_SI G16 G17 GPU_SROM_EN_PSRO_OUT
13 IN SROM_SO SROM_EN_PSRO_OUT
SROM_SI E16 GPU_SPI_SO OUT 13
1 R4T1 2 SROM_SCLK E15 GPU_SPI_CLK OUT 13
MEM_CALA
SROM_CS E14 GPU_SPI_CS_N OUT 13
40.2 1%
402 CH 1 R4R8 2 MEM_CALB
40.2 1% AG16 MEM_CALA MEM_RST AG11 MEM_RST OUT 19 20 21 22 23 24 25 26
402 CH V8 MEM_CALB MEM_SCAN_EN AN13 MEM_SCAN_EN_BUFF OUT 12
MEM_SCAN_OEN_A G9 MEM_SCAN_TOP_EN_BUFF OUT 12
GPU_TCLK E13 TCLK MEM_SCAN_OEN_B G10 MEM_SCAN_BOT_EN_BUFF OUT 12
GPU_TDO D12 TDO 2 2
GPU_TDI E12 TDI
GPU_TMS G12 TMS R2E1 R4F6
GPU_TRST G11 TRST 1K 1K
V_MEM V_MEM GPU_TRST_ED G13 5% 5%
TRST_ED
CH CH
402 402
X02125-001
1 1
1 1
R2E2 R2E4
1.5K 1.5K
1% 1%
CH
J2D2 CH J5C2
402 402 V_1P8 2X3HDR
2 2X4HDR 2
1 2
1 2 GPU_SPI_SI OUT 13
3 4 GPU_SPI_WP_N 13 V_1P8
3 4 OUT
5 6
5 6
7 8
1
1 R4C7 HDR
1 1 10K
R2D10 HDR 5%
1.5K R2D9 R2E3 1
1% 1.5K 1.5K CH C5C3 V_MEM
1% 1% 402 V_1P8 .1UF
CH 2 10%
402 CH CH 6.3V
2 402 402 U4C1 EMPTY 2 X5R VIDEO DECOUPLING
2 2 402
AT25020A
13 GPU_SPI_CLK R5C5 GPU_SPI_CLK_R 6 SCK VCC 8
IN 5
1K 5% GPU_SPI_SO_R SDI
402 CH SDO 2 GPU_SPI_SI OUT 13 C3C2 C3R9 C4R26 C3R8
7 HOLD_N* 4.7UF .1UF .1UF .1UF
R5C8 10% 10% 10% 10%
13 IN GPU_SPI_SO GPU_SPI_CS_N_R 1 CS_N* 6.3V 6.3V 6.3V 6.3V
1K 5% 3 WP_N* GND 4 2 X5R X5R X5R X5R
805 402 402 402
402 CH V_1P8 R4C6
R4C3 X800552-001 10K
13 IN GPU_SPI_CS_N 5%
2 R4C4 1 CH
1K 5%
1 1 402 CH 10K 5% 402
402 CH 1
GPU_SCAN_BUFF_EN_N R5C10 R5P3
OUT 12 10K 10K
5% 5% 2 R4C5 1 GPU_SPI_WP_N 13
CH CH IN
402 402 10K 5%
2 2 402 EMPTY
DRAWING
[PAGE_TITLE=GPU, VIDEO + PCIEX + EEPROM + JTAG] Tue May 08 18:24:13 2007
CONFIDENTIAL
GPU, MEMORY CONTROLLER 0 PARTITION A & B

U4D1 3 OF 12 IC U4D1 4 OF 12 IC
GPU Y2 VERSION 1 GPU Y2 VERSION 1
20 19 BI MA_DQ31 AP19 MA_DQ31 22 21 BI MB_DQ31 AN27 MB_DQ31
20 19 BI MA_DQ30 AN19 MA_DQ30 22 21 BI MB_DQ30 AP28 MB_DQ30
20 19 BI MA_DQ29 AL18 MA_DQ29 22 21 BI MB_DQ29 AP27 MB_DQ29
20 19 BI MA_DQ28 AN20 MA_DQ28 22 21 BI MB_DQ28 AP29 MB_DQ28
20 19 BI MA_DQ27 AN18 MA_DQ27 22 21 BI MB_DQ27 AL25 MB_DQ27
20 19 BI MA_DQ26 AM20 MA_DQ26 22 21 BI MB_DQ26 AP31 MB_DQ26
20 19 BI MA_DQ25 AN17 MA_DQ25 22 21 BI MB_DQ25 AM25 MB_DQ25
20 19 BI MA_DQ24 AL20 MA_DQ24 22 21 BI MB_DQ24 AP32 MB_DQ24
20 19 OUT MA_WDQS3 AP20 MA_WDQS3 22 21 OUT MB_WDQS3 AP30 MB_WDQS3
20 19 IN MA_RDQS3 AM18 MA_RDQS3 22 21 IN MB_RDQS3 AN26 MB_RDQS3
20 19 OUT MA_DM3 AP18 MA_DM3 22 21 OUT MB_DM3 AP26 MB_DM3
20 19 BI MA_DQ23 AP15 MA_DQ23 MA_CLK1_DP AH10 MA_CLK1_DP OUT 20 22 21 BI MB_DQ23 AM23 MB_DQ23 MB_CLK1_DP AM33 MB_CLK1_DP OUT 22
20 19 BI MA_DQ22 AN15 MA_DQ22 MA_CLK1_DN AK10 MA_CLK1_DN OUT 20 22 21 BI MB_DQ22 AP23 MB_DQ22 MB_CLK1_DN AM34 MB_CLK1_DN OUT 22
20 19 BI MA_DQ21 AM15 MA_DQ21 MA_CLK0_DP AN12 MA_CLK0_DP OUT 19 22 21 BI MB_DQ21 AL23 MB_DQ21 MB_CLK0_DP AL33 MB_CLK0_DP OUT 21
20 19 BI MA_DQ20 AN14 MA_DQ20 MA_CLK0_DN AP12 MA_CLK0_DN OUT 19 22 21 BI MB_DQ20 AN23 MB_DQ20 MB_CLK0_DN AL34 MB_CLK0_DN OUT 21
20 19 BI MA_DQ19 AN16 MA_DQ19 MA_A<12..0> 22 21 BI MB_DQ19 AN25 MB_DQ19 MB_A<12..0>
MA_DQ18 AL13 AN4 12 OUT 19 20 MB_DQ18 AP22 AK32 12 OUT 21 22
20 19 BI MA_DQ18 MA_A12 22 21 BI MB_DQ18 MB_A12
20 19 BI MA_DQ17 AP17 MA_DQ17 MA_A11 AP7 11 22 21 BI MB_DQ17 AP25 MB_DQ17 MB_A11 AE29 11
20 19 BI MA_DQ16 AM13 MA_DQ16 MA_A10 AP4 10 22 21 BI MB_DQ16 AN21 MB_DQ16 MB_A10 AE34 10
20 19 OUT MA_WDQS2 AP14 MA_WDQS2 MA_A9 AP8 9 22 21 OUT MB_WDQS2 AN22 MB_WDQS2 MB_A9 AJ30 9
20 19 IN MA_RDQS2 AL15 MA_RDQS2 MA_A8 AN11 8 22 21 IN MB_RDQS2 AP24 MB_RDQS2 MB_A8 AK33 8
20 19 OUT MA_DM2 AP16 MA_DM2 MA_A7 AP9 7 22 21 OUT MB_DM2 AN24 MB_DM2 MB_A7 AJ33 7
MA_A6 AN10 6 MB_A6 AK34 6
20 19 BI MA_DQ15 AH16 MA_DQ15 MA_A5 AP11 5 22 21 BI MB_DQ15 AH26 MB_DQ15 MB_A5 AM32 5
20 19 BI MA_DQ14 AK20 MA_DQ14 MA_A4 AN9 4 22 21 BI MB_DQ14 AN32 MB_DQ14 MB_A4 AJ34 4
20 19 BI MA_DQ13 AK16 MA_DQ13 MA_A3 AN8 3 22 21 BI MB_DQ13 AK26 MB_DQ13 MB_A3 AE30 3
20 19 BI MA_DQ12 AH20 MA_DQ12 MA_A2 AN7 2 22 21 BI MB_DQ12 AN31 MB_DQ12 MB_A2 AF28 2
20 19 BI MA_DQ11 AH17 MA_DQ11 MA_A1 AN5 1 22 21 BI MB_DQ11 AN29 MB_DQ11 MB_A1 AE33 1
20 19 BI MA_DQ10 AJ19 MA_DQ10 MA_A0 AP6 0 22 21 BI MB_DQ10 AN30 MB_DQ10 MB_A0 AF29 0
20 19 BI MA_DQ9 AJ18 MA_DQ9 MA_BA<2..0> 22 21 BI MB_DQ9 AK28 MB_DQ9 MB_BA<2..0>
MA_DQ8 AH18 AP10 2 OUT 19 20 MB_DQ8 AK29 AH30 2 OUT 21 22
20 19 BI MA_DQ8 MA_BA2 22 21 BI MB_DQ8 MB_BA2
20 19 OUT MA_WDQS1 AK19 MA_WDQS1 MA_BA1 AM10 1 22 21 OUT MB_WDQS1 AK30 MB_WDQS1 MB_BA1 AH33 1
20 19 IN MA_RDQS1 AK17 MA_RDQS1 MA_BA0 AP5 0 22 21 IN MB_RDQS1 AN28 MB_RDQS1 MB_BA0 AG30 0
20 19 OUT MA_DM1 AM17 MA_DM1 22 21 OUT MB_DM1 AK27 MB_DM1
MA_CKE AN6 MA_CKE OUT 19 20 MB_CKE AG34 MB_CKE OUT 21 22
20 19 BI MA_DQ7 AK15 MA_DQ7 MA_WE_N* AJ9 MA_WE_N OUT 19 20 22 21 BI MB_DQ7 AK25 MB_DQ7 MB_WE_N* AF33 MB_WE_N OUT 21 22
20 19 BI MA_DQ6 AH11 MA_DQ6 MA_CAS_N* AK8 MA_CAS_N OUT 19 20 22 21 BI MB_DQ6 AH21 MB_DQ6 MB_CAS_N* AF32 MB_CAS_N OUT 21 22
20 19 BI MA_DQ5 AH15 MA_DQ5 MA_RAS_N* AK7 MA_RAS_N OUT 19 20 22 21 BI MB_DQ5 AH25 MB_DQ5 MB_RAS_N* AF31 MB_RAS_N OUT 21 22
20 19 BI MA_DQ4 AK11 MA_DQ4 MA_CS1_N* AK9 MA_CS1_N OUT 19 20 22 21 BI MB_DQ4 AK21 MB_DQ4 MB_CS1_N* AH34 MB_CS1_N OUT 21 22
20 19 BI MA_DQ3 AH13 MA_DQ3 MA_CS0_N* AL10 MA_CS0_N OUT 19 22 21 BI MB_DQ3 AH23 MB_DQ3 MB_CS0_N* AF34 MB_CS0_N OUT 21
20 19 BI MA_DQ2 AK12 MA_DQ2 22 21 BI MB_DQ2 AK22 MB_DQ2
20 19 BI MA_DQ1 AJ13 MA_DQ1 22 21 BI MB_DQ1 AJ23 MB_DQ1
20 19 BI MA_DQ0 AH12 MA_DQ0 22 21 BI MB_DQ0 AH22 MB_DQ0
20 19 OUT MA_WDQS0 AM12 MA_WDQS0 22 21 OUT MB_WDQS0 AM22 MB_WDQS0
20 19 IN MA_RDQS0 AJ14 MA_RDQS0 22 21 IN MB_RDQS0 AJ24 MB_RDQS0
20 19 OUT MA_DM0 AK14 MA_DM0 22 21 OUT MB_DM0 AK24 MB_DM0
AK6 MA_VREF1 AG33 MB_VREF1

V_MEM AP13 MA_VREF0 AP21 MB_VREF0
V_MEM
1
X02125-001 1 X02125-001
R4T4
549 R5E2
1% 549 V_MEM
CH V_MEM 1% V_MEM
402 CH MEMORY CONTROLLER B, DECOUPLING
2 MA_VREF1 402
1 2 1
MB_VREF1
1 R4T7 R4T8
1 549 C4T47 C4T31 C4T34 C5T2 C4T39
C4T40 R4T3 1% 549
1 1% 4.7UF .22UF .22UF .22UF .22UF
.1UF 1.27K CH 10% 10% 10% 10% 10%
10% 1% V_MEM 1 CH 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V 402 C5E1 R5E1 402 X5R X5R X5R X5R X5R
2 X5R CH 2 MEMORY CONTROLLER A, DECOUPLING .1UF 1.27K 805 402 402 402 402
402 402 10% 1% 2
2 MA_VREF0 2 6.3V
CH
MB_VREF0
X5R
402 402
1 2 1
1 C4R3 C4T29 C4T32 C4T42 C4T44 1
R4T6 C4T45 4.7UF .22UF .22UF .22UF .22UF R4T5 C4T46
1.27K .1UF 10% 10% 10% 10% 10% 1.27K .1UF
1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 1% 10%
6.3V X5R X5R X5R X5R X5R 6.3V C4T33 C5T3 C5T4 C5T1
CH 2 X5R 805 402 402 402 402 CH 2 X5R .22UF .22UF .22UF .22UF
402 402 402 402 10% 10% 10% 10%
2 2 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R
402 402 402 402
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE C4T35 C4T27 C4T41 C4T43
R4T3, R4T6, R5E1, R4T5, R4R5, R4R2, R4T2, R4R7 .22UF .22UF .22UF .22UF
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
MEM VREF RESISTOR VALUE X5R X5R X5R X5R
THESE ARE THE GPU VREFS NEEDED 402 402 402 402
70% 1.27KOHM
FOR VARIOUS MEMORIES. CONSULT
72% 1.40KOHM
WITH MEM TEAM FOR USAGE.
73% 1.47KOHM
74% 1.54KOHM DRAWING
[PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] Tue May 08 18:24:14 2007
CONFIDENTIAL
GPU, MEMORY CONTROLLER 1 PARTITION C & D

U4D1 5 OF 12 IC U4D1 6 OF 12 IC
GPU Y2 VERSION 1 GPU Y2 VERSION 1
24 23 BI MC_DQ31 R1 MC_DQ31 26 25 BI MD_DQ31 AC3 MD_DQ31
24 23 BI MC_DQ28 R4 MC_DQ28 26 25 BI MD_DQ28 AD1 MD_DQ28
24 23 BI MC_DQ27 N4 MC_DQ27 26 25 BI MD_DQ27 AB1 MD_DQ27
24 23 BI MC_DQ26 T2 MC_DQ26 26 25 BI MD_DQ26 AE2 MD_DQ26
24 23 BI MC_DQ25 N3 MC_DQ25 26 25 BI MD_DQ25 AA2 MD_DQ25
24 23 BI MC_DQ24 U1 MC_DQ24 26 25 BI MD_DQ24 AE1 MD_DQ24
24 23 OUT MC_WDQS3 T1 MC_WDQS3 26 25 OUT MD_WDQS3 AD2 MD_WDQS3
24 23 IN MC_RDQS3 P2 MC_RDQS3 26 25 IN MD_RDQS3 AC2 MD_RDQS3
24 23 OUT MC_DM3 P1 MC_DM3 26 25 OUT MD_DM3 AB2 MD_DM3
24 23 BI MC_DQ23 L1 MC_DQ23 MC_CLK1_DP J1 MC_CLK1_DP OUT 24 26 25 BI MD_DQ23 W2 MD_DQ23 MD_CLK1_DP AD6 MD_CLK1_DP OUT 26
24 23 BI MC_DQ22 K4 MC_DQ22 MC_CLK1_DN H1 MC_CLK1_DN OUT 24 26 25 BI MD_DQ22 W1 MD_DQ22 MD_CLK1_DN AD5 MD_CLK1_DN OUT 26
24 23 BI MC_DQ21 L2 MC_DQ21 MC_CLK0_DP F1 MC_CLK0_DP OUT 23 26 25 BI MD_DQ21 Y2 MD_DQ21 MD_CLK0_DP AE4 MD_CLK0_DP OUT 25
24 23 BI MC_DQ20 K3 MC_DQ20 MC_CLK0_DN E1 MC_CLK0_DN OUT 23 26 25 BI MD_DQ20 V4 MD_DQ20 MD_CLK0_DN AE3 MD_CLK0_DN OUT 25
24 23 BI MC_DQ19 N2 MC_DQ19 MC_A<12..0> 26 25 BI MD_DQ19 Y4 MD_DQ19 MD_A<12..0>
MC_DQ18 K2 A10 12 OUT 23 24 MD_DQ18 V1 AK5 12 OUT 25 26
24 23 BI MC_DQ18 MC_A12 26 25 BI MD_DQ18 MD_A12
24 23 BI MC_DQ17 N1 MC_DQ17 MC_A11 A7 11 26 25 BI MD_DQ17 AA1 MD_DQ17 MD_A11 AL2 11
24 23 BI MC_DQ16 J2 MC_DQ16 MC_A10 B10 10 26 25 BI MD_DQ16 V2 MD_DQ16 MD_A10 AM2 10
24 23 OUT MC_WDQS2 K1 MC_WDQS2 MC_A9 B6 9 26 25 OUT MD_WDQS2 V3 MD_WDQS2 MD_A9 AF5 9
24 23 IN MC_RDQS2 M1 MC_RDQS2 MC_A8 D1 8 26 25 IN MD_RDQS2 Y1 MD_RDQS2 MD_A8 AE5 8
24 23 OUT MC_DM2 M2 MC_DM2 MC_A7 A5 7 26 25 OUT MD_DM2 Y3 MD_DM2 MD_A7 AF2 7
MC_A6 A4 6 MD_A6 AF7 6
24 23 BI MC_DQ15 J6 MC_DQ15 MC_A5 C1 5 26 25 BI MD_DQ15 W6 MD_DQ15 MD_A5 AE7 5
24 23 BI MC_DQ14 N6 MC_DQ14 MC_A4 B5 4 26 25 BI MD_DQ14 AC7 MD_DQ14 MD_A4 AG2 4
24 23 BI MC_DQ13 J5 MC_DQ13 MC_A3 A6 3 26 25 BI MD_DQ13 W5 MD_DQ13 MD_A3 AM1 3
24 23 BI MC_DQ12 N7 MC_DQ12 MC_A2 B7 2 26 25 BI MD_DQ12 AC6 MD_DQ12 MD_A2 AJ2 2
24 23 BI MC_DQ11 L5 MC_DQ11 MC_A1 A9 1 26 25 BI MD_DQ11 AA5 MD_DQ11 MD_A1 AM3 1
24 23 BI MC_DQ10 M5 MC_DQ10 MC_A0 B8 0 26 25 BI MD_DQ10 AB5 MD_DQ10 MD_A0 AK2 0
24 23 BI MC_DQ9 L7 MC_DQ9 MC_BA<2..0> 26 25 BI MD_DQ9 AA7 MD_DQ9 MD_BA<2..0>
MC_DQ8 M3 B4 2 OUT 23 24 MD_DQ8 AB3 AG5 2 OUT 25 26
24 23 BI MC_DQ8 MC_BA2 26 25 BI MD_DQ8 MD_BA2
24 23 OUT MC_WDQS1 M7 MC_WDQS1 MC_BA1 A3 1 26 25 OUT MD_WDQS1 AB7 MD_WDQS1 MD_BA1 AH2 1
24 23 IN MC_RDQS1 K5 MC_RDQS1 MC_BA0 B9 0 26 25 IN MD_RDQS1 Y5 MD_RDQS1 MD_BA0 AJ5 0
24 23 OUT MC_DM1 K7 MC_DM1 26 25 OUT MD_DM1 Y7 MD_DM1
MC_CKE A8 MC_CKE OUT 23 24 MD_CKE AK1 MD_CKE OUT 25 26
24 23 BI MC_DQ7 H2 MC_DQ7 MC_WE_N* E7 MC_WE_N OUT 23 24 26 25 BI MD_DQ7 V7 MD_DQ7 MD_WE_N* AH1 MD_WE_N OUT 25 26
24 23 BI MC_DQ6 B2 MC_DQ6 MC_CAS_N* E8 MC_CAS_N OUT 23 24 26 25 BI MD_DQ6 P6 MD_DQ6 MD_CAS_N* AJ1 MD_CAS_N OUT 25 26
24 23 BI MC_DQ5 H5 MC_DQ5 MC_RAS_N* E9 MC_RAS_N OUT 23 24 26 25 BI MD_DQ5 V6 MD_DQ5 MD_RAS_N* AL1 MD_RAS_N OUT 25 26
24 23 BI MC_DQ4 C2 MC_DQ4 MC_CS1_N* E6 MC_CS1_N OUT 23 24 26 25 BI MD_DQ4 P5 MD_DQ4 MD_CS1_N* AH5 MD_CS1_N OUT 25 26
24 23 BI MC_DQ3 F2 MC_DQ3 MC_CS0_N* B3 MC_CS0_N OUT 23 26 25 BI MD_DQ3 U3 MD_DQ3 MD_CS0_N* AG1 MD_CS0_N OUT 25
24 23 BI MC_DQ2 E5 MC_DQ2 26 25 BI MD_DQ2 R5 MD_DQ2
24 23 BI MC_DQ1 F5 MC_DQ1 26 25 BI MD_DQ1 T5 MD_DQ1
24 23 BI MC_DQ0 E2 MC_DQ0 26 25 BI MD_DQ0 T7 MD_DQ0
24 23 OUT MC_WDQS0 D2 MC_WDQS0 26 25 OUT MD_WDQS0 R7 MD_WDQS0
24 23 IN MC_RDQS0 G5 MC_RDQS0 26 25 IN MD_RDQS0 U5 MD_RDQS0
24 23 OUT MC_DM0 G2 MC_DM0 26 25 OUT MD_DM0 U7 MD_DM0
G1 MC_VREF1 AF1 MD_VREF1

E10 MC_VREF0 V_MEM U2 MD_VREF0
V_MEM
2 1
X02125-001 X02125-001
R4R4 R3T2
549
1% V_MEM
549 V_MEM
1% V_MEM
CH
402 CH
1 402 MEMORY CONTROLLER D, DECOUPLING
2
2 1
MC_VREF1 MD_VREF1
R4R1 1
R4R6 1 1 1 1 1
1 549 549 C4T28 C4R15 C4R61 C4T38 C4R50
1% V_MEM 1 1% 4.7UF .22UF .22UF .22UF .22UF
1 R4R5 C4T36 R4T2 10% 10% 10% 10% 10%
C4R25 CH .1UF 1.27K CH 6.3V 6.3V 6.3V 6.3V 6.3V
.1UF 1.27K 402 MEMORY CONTROLLER C, DECOUPLING 10% 1% 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
10% 1% 1 6.3V 2 805 402 402 402 402
2 6.3V
CH
2 X5R CH
X5R MC_VREF0 402 402
402 402 2 MD_VREF0
2 1 1 1 1 1 1
1 C3R5 C4R38 C4R51 C4T14 C4R48
R4R2 C4R10 4.7UF .22UF .22UF .22UF .22UF 1
1.27K .1UF 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V R4R7 1
1% 10% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R C4R64 1 1 1 1
6.3V 1.27K .1UF C4T7 C4R31 C4R12 C4R19
CH 2 X5R 805 402 402 402 402
1% 10%
402 402 6.3V .22UF .22UF .22UF .22UF
2 CH 2 X5R 10% 10% 10% 10%
402 6.3V 6.3V 6.3V 6.3V
2
402 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
1 1 1 1
C4R23 C4R66 C4T12 C4R32
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE .22UF .22UF .22UF .22UF
10% 10% 10% 10%
R4T3, R4T6, R5E1, R4T5, R4R5, R4R2, R4T2, R4R7 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
GPU MEM VREF RESISTOR VALUE
THESE ARE THE GPU VREFS NEEDED
70% 1.27KOHM
72% 1.40KOHM
73% 1.47KOHM
74% 1.54KOHM DRAWING
PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] Tue May 08 18:24:14 2007
CONFIDENTIAL
GPU, PLL POWER + FSB POWER
V_GPUCORE
FB4D1
1 2
120 FB
0.2A 603
0.5 DCR 1 1 1
C4D6 C4D5 C4D4
2.2UF .1UF 0.01UF
10% 10% 10%
6.3V 6.3V 16V
2 X5R 2 X5R 2 X7R
603 402 402
V_GPUCORE
V_GPUPCIE U4D1 8 OF 12 IC
GPU Y2 VERSION 1
FB4T1 VDD_FSB24 AA27
1 2 VDD_FSB23 AB28
120 FB V_PVDDA A20 PVDDA VDD_FSB22 AB32
0.2A 603
1 1 1 1 A21 PVSSA VDD_FSB21 AC27
0.5 DCR C4T48 C4T30 C4T37 C5R7 C4R8 AD28
.1UF .1UF VDD_FSB20
2.2UF .1UF 0.01UF 10% 10% C27 VDD_BSB1 VDD_FSB19 AD31
10% 10% 10% 6.3V 6.3V
6.3V 6.3V 16V 2 X5R 2 X5R C26 VSS_BSB1 VDD_FSB18 K28
2 X5R 2 X5R X7R 402 402 VDD_FSB17 K31
603 402 402 C25 L27
VDD_BSB0 VDD_FSB16
C24 VSS_BSB0 VDD_FSB15 M28
VDD_FSB14 M32
V_PVDDA_MEM AG10 PVDDA_MEM VDD_FSB13 N27
AG9 PVSSA_MEM VDD_FSB12 P28
FB4R1 VDD_FSB11 P31
1 2 V_PVDDA_ED A18 PVDDA_ED VDD_FSB10 R28
120 FB A19 PVSSA_ED VDD_FSB9 R32
0.2A 603 VDD_FSB8 T27
0.5 DCR 1 1
C4R68 C4R4 C4R6 B25 PVDDA_PEX VDD_FSB7 U28
2.2UF .1UF 0.01UF B24 PVSSA_PEX VDD_FSB6 U31
10% 10% 10%
6.3V 6.3V 16V VDD_FSB5 V27
2 X5R 2 X5R X7R V_PVDDA_FSB G34 PVDDA_FSB VDD_FSB4 V30
603 402 402 F34 W28
PVSSA_FSB VDD_FSB3
VDD_FSB2 W32
V_GPUPCIE VDD_FSB1 Y28
VDD_FSB0 Y31
X02125-001
1
C4R5 C4R7
.1UF 0.01UF
10% 10%
6.3V 16V
2 X5R X7R
402 402
FB5R1
1 2
120 FB
0.2A 603
0.5 DCR 1 1
C5R19 C5R13 C5R15
2.2UF .1UF 0.01UF
10% 10% 10%
6.3V 6.3V 16V
2 X5R 2 X5R X7R
603 402 402
DRAWING
[PAGE_TITLE=GPU, PLL POWER + FSB POWER] Tue May 08 18:24:14 2007
CONFIDENTIAL
GPU, CORE POWER + MEM POWER
V_GPUCORE V_GPUCORE
U4D1 IC
U4D1 IC 12 OF 12
U4D1 9 OF 12 IC
11 OF 12
GPU Y2 VERSION 1
GPU Y2 VERSION 1
E28 H14 GPU Y2 VERSION 1 F21 P18
VDD_CORE157 VDD_CORE78 V_MEM V_MEM VSS130 VSS65
D27 VDD_CORE156 VDD_CORE77 H16 A1 VSS260 VSS195 AJ15 F24 VSS129 VSS64 P22
E27 VDD_CORE155 VDD_CORE76 H18 AA3 VSS259 VSS194 AJ17 F26 VSS128 VSS63 P23
D26 H20 U4D1 10 OF 12 IC AA8 AJ20 F28 P24
VDD_CORE154 VDD_CORE75 VSS258 VSS193 VSS127 VSS62
E26 VDD_CORE153 VDD_CORE74 H22 GPU Y2 VERSION 1 AA11 VSS257 VSS192 AJ25 F31 VSS126 VSS61 P27
G26 VDD_CORE152 VDD_CORE73 H24 AA4 VDD_MEM111 VDD_MEM55 AL28 AA12 VSS256 VSS191 AJ27 G4 VSS125 VSS60 P32
G25 VDD_CORE151 VDD_CORE72 H26 AA6 VDD_MEM110 VDD_MEM54 AL30 AA13 VSS255 VSS190 AJ29 G7 VSS124 VSS59 R6
D24 VDD_CORE150 VDD_CORE71 H27 AB6 VDD_MEM109 VDD_MEM53 AL32 AA17 VSS254 VSS189 AJ31 G18 VSS123 VSS58 R11
E24 VDD_CORE149 VDD_CORE70 J27 AC5 VDD_MEM108 VDD_MEM52 AM5 AA18 VSS253 VSS188 AK4 G20 VSS122 VSS57 R12
E23 VDD_CORE148 VDD_CORE69 L11 AC8 VDD_MEM107 VDD_MEM51 AM7 AA22 VSS252 VSS187 AK18 G27 VSS121 VSS56 R13
G24 VDD_CORE147 VDD_CORE68 L12 AD4 VDD_MEM106 VDD_MEM50 AM9 AA23 VSS251 VSS186 AL3 G29 VSS120 VSS55 R17
D23 VDD_CORE146 VDD_CORE67 L13 AD7 VDD_MEM105 VDD_MEM49 AM16 AA24 VSS250 VSS185 AL5 G33 VSS119 VSS54 R18
G23 VDD_CORE145 VDD_CORE66 L17 AE8 VDD_MEM104 VDD_MEM48 AM19 AB4 VSS249 VSS184 AL7 H3 VSS118 VSS53 R22
F22 VDD_CORE144 VDD_CORE65 L18 AE28 VDD_MEM103 VDD_MEM47 AM26 AB8 VSS248 VSS183 AL9 H6 VSS117 VSS52 R23
G22 VDD_CORE143 VDD_CORE64 L22 AE31 VDD_MEM102 VDD_MEM46 AM27 AB14 VSS247 VSS182 AL12 H8 VSS116 VSS51 R24
G21 VDD_CORE142 VDD_CORE63 L23 AF3 VDD_MEM101 VDD_MEM45 AM29 AB15 VSS246 VSS181 AL16 H9 VSS115 VSS50 R27
D29 VDD_CORE141 VDD_CORE62 L24 AF6 VDD_MEM100 VDD_MEM44 AM31 AB16 VSS245 VSS180 AL19 H11 VSS114 VSS49 R31
E25 VDD_CORE140 VDD_CORE61 M11 AF27 VDD_MEM99 VDD_MEM43 AN2 AB19 VSS244 VSS179 AL22 H13 VSS113 VSS48 T4
AA14 VDD_CORE139 VDD_CORE60 M12 AF30 VDD_MEM98 VDD_MEM42 AP3 AB20 VSS243 VSS178 AL26 H15 VSS112 VSS47 T8
AA15 VDD_CORE138 VDD_CORE59 M13 AG4 VDD_MEM97 VDD_MEM41 C3 AB21 VSS242 VSS177 AL27 H17 VSS111 VSS46 T11
AA20 VDD_CORE135 VDD_CORE56 M22 AG15 VDD_MEM94 VDD_MEM38 C9 AC14 VSS239 VSS174 AM4 H23 VSS108 VSS43 T17
AA21 VDD_CORE134 VDD_CORE55 M23 AG17 VDD_MEM93 VDD_MEM37 C12 AC15 VSS238 VSS173 AM6 H25 VSS107 VSS42 T18
AB11 VDD_CORE133 VDD_CORE54 M24 AG20 VDD_MEM92 VDD_MEM36 C14 AC16 VSS237 VSS172 AM8 H28 VSS106 VSS41 T22
AB12 VDD_CORE132 VDD_CORE53 N11 AG23 VDD_MEM91 VDD_MEM35 C16 AC19 VSS236 VSS171 AM11 J4 VSS105 VSS40 T23
AB13 VDD_CORE131 VDD_CORE52 N12 AG25 VDD_MEM90 VDD_MEM34 C18 AC20 VSS235 VSS170 AM14 J8 VSS104 VSS39 T24
AB17 VDD_CORE130 VDD_CORE51 N13 AG28 VDD_MEM89 VDD_MEM33 D4 AC21 VSS234 VSS169 AM21 J28 VSS103 VSS38 U6
AB18 VDD_CORE129 VDD_CORE50 N17 AG32 VDD_MEM88 VDD_MEM32 D6 AC30 VSS233 VSS168 AM24 K6 VSS102 VSS37 U14
AB22 VDD_CORE128 VDD_CORE49 N18 AH3 VDD_MEM87 VDD_MEM31 D8 AD3 VSS232 VSS167 AM28 K27 VSS101 VSS36 U15
AB23 VDD_CORE127 VDD_CORE48 N22 AH6 VDD_MEM86 VDD_MEM30 E3 AD8 VSS231 VSS166 AM30 K32 VSS100 VSS35 U16
AB24 VDD_CORE126 VDD_CORE47 N23 AH8 VDD_MEM85 VDD_MEM29 F4 AD14 VSS230 VSS165 AN3 L3 VSS99 VSS34 U19
AC11 VDD_CORE125 VDD_CORE46 N24 AH9 VDD_MEM84 VDD_MEM28 F7 AD15 VSS229 VSS164 AN33 L8 VSS98 VSS33 U20
AC12 VDD_CORE124 VDD_CORE45 P14 AH14 VDD_MEM83 VDD_MEM27 F9 AD16 VSS228 VSS163 B19 L14 VSS97 VSS32 U21
AC13 VDD_CORE123 VDD_CORE44 P15 AH19 VDD_MEM82 VDD_MEM26 F11 AD19 VSS227 VSS162 B33 L15 VSS96 VSS31 U27
AC17 VDD_CORE122 VDD_CORE43 P16 AH24 VDD_MEM81 VDD_MEM25 F13 AD20 VSS226 VSS161 C4 L16 VSS95 VSS30 U32
AC18 VDD_CORE121 VDD_CORE42 P19 AH27 VDD_MEM80 VDD_MEM24 F15 AD21 VSS225 VSS160 C6 L19 VSS94 VSS29 V5
AC22 VDD_CORE120 VDD_CORE41 P20 AH29 VDD_MEM79 VDD_MEM23 G3 AD27 VSS224 VSS159 C8 L20 VSS93 VSS28 V14
AC23 VDD_CORE119 VDD_CORE40 P21 AH31 VDD_MEM78 VDD_MEM22 G6 AD32 VSS223 VSS158 C11 L21 VSS92 VSS27 V15
AC24 VDD_CORE118 VDD_CORE39 R14 AJ4 VDD_MEM77 VDD_MEM21 G8 AE6 VSS222 VSS157 C13 L28 VSS91 VSS26 V16
AD11 VDD_CORE117 VDD_CORE38 R15 AJ7 VDD_MEM76 VDD_MEM20 H4 AE27 VSS221 VSS156 C15 M4 VSS90 VSS25 V19
AD12 VDD_CORE116 VDD_CORE37 R16 AJ11 VDD_MEM75 VDD_MEM19 H7 AE32 VSS220 VSS155 C17 M8 VSS89 VSS24 V20
AD13 VDD_CORE115 VDD_CORE36 R19 AJ12 VDD_MEM74 VDD_MEM18 H10 AF4 VSS219 VSS154 C20 M14 VSS88 VSS23 V21
AD17 VDD_CORE114 VDD_CORE35 R20 AJ16 VDD_MEM73 VDD_MEM17 J3 AF8 VSS218 VSS153 C28 M15 VSS87 VSS22 W4
AD18 VDD_CORE113 VDD_CORE34 R21 AJ21 VDD_MEM72 VDD_MEM16 J7 AG3 VSS217 VSS152 C32 M16 VSS86 VSS20 W11
AD22 VDD_CORE112 VDD_CORE33 T14 AJ22 VDD_MEM71 VDD_MEM15 K8 AG6 VSS216 VSS151 D3 M19 VSS85 VSS21 W8
AD23 VDD_CORE111 VDD_CORE32 T15 AJ26 VDD_MEM70 VDD_MEM14 L4 AG8 VSS215 VSS150 D5 M20 VSS84 VSS19 W12
AD24 VDD_CORE110 VDD_CORE31 T16 AJ28 VDD_MEM69 VDD_MEM13 L6 AG12 VSS214 VSS149 D7 M21 VSS83 VSS18 W13
B18 VDD_CORE109 VDD_CORE30 T19 AJ32 VDD_MEM68 VDD_MEM12 M6 AG14 VSS213 VSS148 D9 M27 VSS82 VSS17 W17
B20 VDD_CORE108 VDD_CORE29 T20 AK3 VDD_MEM67 VDD_MEM11 N5 AG18 VSS212 VSS147 D19 M31 VSS81 VSS16 W18
C19 VDD_CORE107 VDD_CORE28 T21 AK13 VDD_MEM66 VDD_MEM10 N8 AG19 VSS211 VSS146 D21 N14 VSS80 VSS15 W22
C21 VDD_CORE106 VDD_CORE27 U11 AK23 VDD_MEM65 VDD_MEM9 P4 AG21 VSS210 VSS145 D31 N15 VSS79 VSS14 W23
C29 VDD_CORE105 VDD_CORE26 U12 AK31 VDD_MEM64 VDD_MEM8 P7 AG22 VSS209 VSS144 E4 N16 VSS78 VSS13 W24
C31 VDD_CORE104 VDD_CORE25 U13 AL4 VDD_MEM63 VDD_MEM7 R8 AG24 VSS208 VSS143 E18 N19 VSS77 VSS12 W27
C33 VDD_CORE103 VDD_CORE24 U17 AL6 VDD_MEM62 VDD_MEM6 T3 AG26 VSS207 VSS142 E20 N20 VSS76 VSS11 W31
C34 VDD_CORE102 VDD_CORE23 U18 AL8 VDD_MEM61 VDD_MEM5 T6 AG27 VSS206 VSS141 E22 N21 VSS75 VSS10 Y6
D17 VDD_CORE101 VDD_CORE22 U22 AL11 VDD_MEM60 VDD_MEM4 U4 AG29 VSS205 VSS140 E30 N28 VSS74 VSS9 Y11
D18 VDD_CORE100 VDD_CORE21 U23 AL14 VDD_MEM59 VDD_MEM3 U8 AG31 VSS204 VSS139 E32 N29 VSS73 VSS8 Y12
D20 VDD_CORE99 VDD_CORE20 U24 AL17 VDD_MEM58 VDD_MEM2 W3 AH4 VSS203 VSS138 F3 N30 VSS72 VSS7 Y13
D22 VDD_CORE98 VDD_CORE19 V11 AL21 VDD_MEM57 VDD_MEM1 W7 AH7 VSS202 VSS137 F6 P3 VSS71 VSS6 Y17
D30 VDD_CORE97 VDD_CORE18 V12 AL24 VDD_MEM56 VDD_MEM0 Y8 AH28 VSS201 VSS136 F8 P8 VSS70 VSS5 Y18
D32 VDD_CORE96 VDD_CORE17 V13 AH32 VSS200 VSS135 F10 P11 VSS69 VSS4 Y22
D34 VDD_CORE95 VDD_CORE16 V17 AJ3 VSS199 VSS134 F12 P12 VSS68 VSS3 Y23
E17 V18 X02125-001 AJ6 F14 P13 Y24
VDD_CORE94 VDD_CORE15 VSS198 VSS133 VSS67 VSS2
E19 VDD_CORE93 VDD_CORE14 V22 AJ8 VSS197 VSS132 F16 P17 VSS66 VSS1 Y27
E21 VDD_CORE92 VDD_CORE13 V23 AJ10 VSS196 VSS131 F19 VSS0 Y32
E31 VDD_CORE91 VDD_CORE12 V24
F17 VDD_CORE90 VDD_CORE11 W14
F18 W15 X02125-001 X02125-001
VDD_CORE89 VDD_CORE10
F29 VDD_CORE84 VDD_CORE5 Y14
F30 VDD_CORE83 VDD_CORE4 Y15
G19 VDD_CORE82 VDD_CORE3 Y16
H12 VDD_CORE79 VDD_CORE0 Y21
X02125-001 DRAWING
XENON_FABK MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, CORE POWER + MEM POWER] Tue May 08 18:24:14 2007
CONFIDENTIAL
GPU, DECOUPLING
V_GPUCORE V_GPUCORE V_GPUCORE
N:EMPTIES
C4R20 C4R11 C4R16 C4R28 C4R13 C4R54 C5D2 C6R47 C4R29
1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 10UF 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R X5R
402 402 402 402 402 402 805 805 805
C4R37 C4R17 C4R21 C4R22 C5R16 C4T5 C6E2 C6E1 C4T17

1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 10UF 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R X5R
402 402 402 402 402 402 805 805 805
C4R30
C4T15 C4R55 C4T26 C4T23 C5R10 C4R59 C5R5 C5D3 2 1
1 2 1 2 1 2 1 2 2 1 1 2 2 1 2 1
10UF 20%
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
X5R X5R X5R X5R X5R EMPTY X5R X5R 805
402 402 402 402 402 402 805 805
C4R69
C4R14 C4R47 C4T21 C4R44 C5R12 C4T6 C5R4 C5D4 2 1
1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1
10UF 20%
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
X5R X5R X5R X5R X5R EMPTY X5R X5R 805
402 402 402 402 402 402 805 805
C4R39 C5D6
1 2 C4T20 C4R46 C4T24 C4R24 C4R57 C5R20 2 1
1 2 1 2 1 2 1 2 1 2 2 1
.1UF 10% 4.7UF 10%
6.3V .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 6.3V
X5R 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
402 X5R X5R X5R X5R EMPTY X5R 805
402 402 402 402 402 805
C4T25 C4R36 C4R41 C4T19 C4R40 C4R56 C5R2 C5D5

1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 805 805
C4T11 C4R34 C4R35 C4T18 C5R8 C4T4 C5R1

1 2 1 2 1 2 1 2 1 2 1 2 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 805
C4T3 C4R42 C4R67 C4R62 C4R9 C4R58 C5R3

1 2 1 2 2 1 1 2 1 2 1 2 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
EMPTY X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 805
C5R11
C4R49 C4T16 C4R63 C4R43 C5R14 C4T8 2 1
1 2 1 2 1 2 1 2 1 2 1 2
4.7UF 10%
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
X5R X5R X5R X5R X5R EMPTY 805
402 402 402 402 402 402
C4R18 C4T1 C4T2 C5R17 C5R9 C5R6

1 2 1 2 1 2 1 2 1 2 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 805
DRAWING
[PAGE_TITLE=GPU, DECOUPLING] Tue May 08 18:24:14 2007
CONFIDENTIAL
MEMORY PARTITION A, TOP

V_MEM CHIP SELECT = 0, MIRROR FUNCTION = 0
1 1
R4F3 R4F4
60.4 60.4 V_MEM
1% 1%
CH CH
402 402 U4F1 IC
U4F1 IC
2 2
GDDR136
GDDR136 V1
MA_CLK0_DP T3 MA_DQ31 VDDQ<21> MF=0
14 IN MF=0 DQ31 BI 14 20 R12
T2 MA_DQ30 VDDQ<20>
DQ30 BI 14 20 R9 T12
R3 MA_DQ29 VDDQ<19> VSSQ<19>
DQ29 BI 14 20 R4 T9
R2 MA_DQ28 VDDQ<18> VSSQ<18>
DQ28 BI 14 20 R1 T4
M3 MA_DQ27 VDDQ<17> VSSQ<17>
DQ27 BI 14 20 N12 T1
N2 MA_DQ26 VDDQ<16> VSSQ<16>
DQ26 BI 14 20 N9 P12
L3 MA_DQ25 VDDQ<15> VSSQ<15>
DQ25 BI 14 20 V12 P9
DQ24 BI 14 20 N4 P4
J11 P2 MA_WDQS3 VDDQ<13> VSSQ<13>
CLK_DP WDQS3 IN 14 N1 P1
MA_CLK0_DN J10 P3 MA_RDQS3 VDDQ<12> VSSQ<12>
14 IN CLK_DN RDQS3 OUT 20 14 J9 L11
N3 MA_DM3 VDDQ<11> VSSQ<11>
DM3 IN 14 J4 L2
MEM_RST V9 VDDQ<10> VSSQ<10>
13 IN RESET E12 G11
T10 MA_DQ23 VDDQ<9> VSSQ<9>
MA_A<11..0> DQ23 BI 14 20 E9 G2
14 IN 11 L4 T11 MA_DQ22 VDDQ<8> VSSQ<8>
A11/A7 DQ22 BI 14 20 E4 D12
10 K2 R10 MA_DQ21 VDDQ<7> VSSQ<7>
A10/A8 DQ21 BI 14 20 E1 D9
9 M9 R11 MA_DQ20 VDDQ<6> VSSQ<6>
A9/A3 DQ20 BI 14 20 C12 D4
8 K11 M10 MA_DQ19 VDDQ<5> VSSQ<5>
A8/A10 DQ19 BI 14 20 C9 D1
7 L9 N11 MA_DQ18 VDDQ<4> VSSQ<4>
A7/A11 DQ18 BI 14 20 C4 B12
6 K10 L10 MA_DQ17 VDDQ<3> VSSQ<3>
A6/A2 DQ17 BI 14 20 C1 B9
5 H11 M11 MA_DQ16 VDDQ<2> VSSQ<2>
A5/A1 DQ16 BI 14 20 A12 B4
4 K9 P11 MA_WDQS2 VDDQ<1> VSSQ<1>
A4/A0 WDQS2 IN 14 A1 B1
3 M4 P10 MA_RDQS2 VDDQ<0> VSSQ<0>
A3/A9 RDQS2 OUT 20 14
2 K3 A2/A6 DM2 N10 MA_DM2 IN 14 V2 V3
1 H2 VDD<7> VSS<7>
A1/A5 M12 L12
0 K4 G10 MA_DQ15 VDD<6> VSS<6>
A0/A4 DQ15 BI 14 20 M1 L1
F11 MA_DQ14 VDD<5> VSS<5>
MA_BA<2..0> DQ14 BI 14 20 V11 G12
14 IN 2 H10 F10 MA_DQ13 VDD<4> VSS<4>
BA2/RAS_N DQ13 BI 14 20 F12 G1
1 G9 E11 MA_DQ12 VDD<3> VSS<3>
BA1/BA0 DQ12 BI 14 20 F1 A10
0 G4 C10 MA_DQ11 VDD<2> VSS<2>
BA0/BA1 DQ11 BI 14 20 A11 V10
C11 MA_DQ10 VDD<1> VSS<1>
DQ10 BI 14 20 A2 A3
MA_CKE H4 B10 MA_DQ9 VDD<0> VSS<0>
14 IN CKE/WE_N DQ9 BI 14 20
14 IN MA_WE_N H9 WE_N/CKE DQ8 B11 MA_DQ8 BI 14 20 K12 J3
MA_CAS_N F4 D11 MA_WDQS1 VDDA<1> NC<1>
14 IN CAS_N/CS_N WDQS1 IN 14 K1 J2
MA_RAS_N H3 D10 MA_RDQS1 VDDA<0> NC<0>
14 IN RAS_N/BA2 RDQS1 OUT 20 14
14 IN MA_CS0_N F9 CS_N/CAS_N DM1 E10 MA_DM1 IN 14 J12 VSSA<1>
MEM_SCAN_TOP_EN A9 G3 MA_DQ7 J1 VSSA<0>
12 IN MF DQ7 BI 14 20
DQ6 F2 MA_DQ6 BI 14 20
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MA_DQ5 BI 14 20
E2 MA_DQ4 X801995-011
DQ4 BI 14 20
19 IN MEM_A_VREF1 H1 VREF1 DQ3 C3 MA_DQ3 BI 14 20
20 IN MEM_A_VREF0 H12 VREF0 DQ2 C2 MA_DQ2 BI 14 20 MA_CS1_N
B3 MA_DQ1 IN 14
DQ1 BI 14 20
DQ0 B2 MA_DQ0 BI 14 20
WDQS0 D2 MA_WDQS0 IN 14
D3 MA_RDQS0 MX_CS1_N CONNECTED
RDQS0 OUT 20 14
E3 MA_DM0 TO J3 O SUPPORT 1G
DM0 IN 14
V_MEM RAM CONFIGS.
ZQ A4 MA_ZQ_TOP
1
1 X801995-011 R3F1
243
R4U4 1%
549 CH
1% 402
2 V_MEM
CH
402 PARTITION A DECOUPLING
2 V_MEM MEMORY A, TOP, DECOUPLING
MEM_A_VREF1 OUT 19 20
1 1 C3F3 C4F9 C4F11 C4F7 C3F1 C4F1 C4F6 C4F3

C4F12 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
R4U5 C4U9 4.7UF 10% 10% 10% 10% 10% 10% 10% 10%
1.27K .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 6.3V X5R X5R X5R X5R X5R X5R X5R X5R
1%
6.3V TO CHANGE MEM VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE
2 X5R 402 402 402 402 402 402 402 402
CH X5R 805
402 402 R4U5, R4F2, R5U3, R5F2, R2R2, R3D2, R2T3, R3E2
2
MEM VREF RESISTOR VALUE
70% 1.27KOHM
72% 1.40KOHM
THESE ARE THE MEM VREFS NEEDED

DRAWING
[PAGE_TITLE=DUAL ETHERNET PHY] Tue May 08 18:24:15 2007
CONFIDENTIAL
V_MEM
MEMORY PARTITION A, BOTTOM
CHIP SELECT = 1, MIRROR FUNCTION = 1
1 1
R4U2 R4U3
60.4 60.4
1% 1%
CH CH
402 402
2 2 U4U1 IC
V_MEM
GDDR136
14 IN MA_CLK1_DP MF=1 DQ31 T3 MA_DQ23 BI 14 19 U4U1 IC
DQ30 T2 MA_DQ22 BI 14 19
R3 MA_DQ21 GDDR136
DQ29 BI 14 19 V1
R2 MA_DQ20 VDDQ<21> MF=1
DQ28 BI 14 19 R12
M3 MA_DQ19 VDDQ<20>
DQ27 BI 14 19 R9 T12
N2 MA_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 14 19 R4 T9
L3 MA_DQ17 VDDQ<18> VSSQ<18>
DQ25 BI 14 19 R1 T4
DQ24 BI 14 19 N12 T1
J11 P2 MA_WDQS2 VDDQ<16> VSSQ<16>
MA_CLK1_DN J10 P3 MA_RDQS2 VDDQ<15> VSSQ<15>
14 IN CLK_DN RDQS3 OUT 19 14 V12 P9
N3 MA_DM2 VDDQ<14> VSSQ<14>
DM3 IN 14 N4 P4
13 IN RESET N1 P1
T10 MA_DQ31 VDDQ<12> VSSQ<12>
MA_A<11..0> DQ23 BI 14 19 J9 L11
14 IN 11 L9 T11 MA_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 14 19 J4 L2
10 K11 R10 MA_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 14 19 E12 G11
9 M4 R11 MA_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 14 19 E9 G2
8 K2 M10 MA_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 14 19 E4 D12
7 L4 N11 MA_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 14 19 E1 D9
6 K3 L10 MA_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 14 19 C12 D4
5 H2 M11 MA_DQ24 VDDQ<5> VSSQ<5>
A1/A5 DQ16 BI 14 19 C9 D1
4 K4 P11 MA_WDQS3 VDDQ<4> VSSQ<4>
A0/A4 WDQS2 IN 14 C4 B12
3 M9 P10 MA_RDQS3 VDDQ<3> VSSQ<3>
A9/A3 RDQS2 OUT 19 14 C1 B9
2 K10 N10 MA_DM3 VDDQ<2> VSSQ<2>
A6/A2 DM2 IN 14 A12 B4
1 H11 VDDQ<1> VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MA_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 14 19
MA_BA<2..0> DQ14 F11 MA_DQ6 BI 14 19 V2 V3
14 IN 2 H3 F10 MA_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 14 19 M12 L12
1 G4 E11 MA_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 14 19 M1 L1
0 G9 C10 MA_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 14 19 V11 G12
C11 MA_DQ2 VDD<4> VSS<4>
DQ10 BI 14 19 F12 G1
MA_CKE H9 B10 MA_DQ1 VDD<3> VSS<3>
14 IN WE_N/CKE DQ9 BI 14 19 F1 A10
MA_WE_N H4 B11 MA_DQ0 VDD<2> VSS<2>
14 IN CKE/WE_N DQ8 BI 14 19 A11 V10
MA_CAS_N F9 D11 MA_WDQS0 VDD<1> VSS<1>
14 IN CS_N/CAS_N WDQS1 IN 14 A2 A3
MA_RAS_N H10 D10 MA_RDQS0 VDD<0> VSS<0>
14 IN BA2/RAS_N RDQS1 OUT 19 14
14 IN MA_CS1_N F4 CAS_N/CS_N DM1 E10 MA_DM0 IN 14 K12 J3
VDDA<1> NC<1>
K1 VDDA<0> NC<0> J2
12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MA_DQ15 BI 14 19
DQ6 F2 MA_DQ14 BI 14 19 J12
MEM_SCAN_EN V4 F3 MA_DQ13 VSSA<1>
12 IN SCAN_EN DQ5 BI 14 19 J1
E2 MA_DQ12 VSSA<0>
DQ4 BI 14 19
B3 MA_DQ9 X801995-011
DQ1 BI 14 19
DQ0 B2 MA_DQ8 BI 14 19
WDQS0 D2 MA_WDQS1 IN 14
RDQS0 D3 MA_RDQS1 OUT 19 14
DM0 E3 MA_DM1 IN 14
ZQ A4 MA_ZQ_BOT
V_MEM
1
X801995-011 R3U1
243
1 1%
R4F1 CH
549 402
1% 2
V_MEM
CH
402
2 MEMORY A, BOTTOM, DECOUPLING
MEM_A_VREF0 OUT 19 20
1 C3U2 C4U8 C4U11 C4U6 C3U1 C4U1 C4U5 C4U2

R4F2 C4F2 10% 10% 10% 10% 10% 10% 10% 10%
1.27K .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1% 10% X5R X5R X5R X5R X5R X5R X5R X5R
6.3V 402 402 402 402 402 402 402 402
CH X5R
402 402
2
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARTITION A, TOP] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
CONFIDENTIAL
MEMORY PARTITION B, TOP

1 1
R5F3 R5F4
60.4 60.4 V_MEM
1% 1%
CH CH
402 402 U5F1 IC
2 2
GDDR136
U5F1 IC V1 VDDQ<21> MF=1
R12 VDDQ<20>
GDDR136 R9 T12
MB_CLK0_DP T3 MB_DQ31 VDDQ<19> VSSQ<19>
14 IN MF=0 DQ31 BI 14 22 R4 T9
T2 MB_DQ30 VDDQ<18> VSSQ<18>
DQ30 BI 14 22 R1 T4
R3 MB_DQ29 VDDQ<17> VSSQ<17>
DQ29 BI 14 22 N12 T1
R2 MB_DQ28 VDDQ<16> VSSQ<16>
DQ28 BI 14 22 N9 P12
M3 MB_DQ27 VDDQ<15> VSSQ<15>
DQ27 BI 14 22 V12 P9
N2 MB_DQ26 VDDQ<14> VSSQ<14>
DQ26 BI 14 22 N4 P4
L3 MB_DQ25 VDDQ<13> VSSQ<13>
DQ25 BI 14 22 N1 P1
DQ24 BI 14 22 J9 L11
J11 P2 MB_WDQS3 VDDQ<11> VSSQ<11>
CLK_DP WDQS3 IN 14 J4 L2
MB_CLK0_DN J10 P3 MB_RDQS3 VDDQ<10> VSSQ<10>
14 IN CLK_DN RDQS3 OUT 22 14 E12 G11
N3 MB_DM3 VDDQ<9> VSSQ<9>
DM3 IN 14 E9 G2
13 IN RESET E4 D12
MB_A<11..0> DQ23 BI 14 22 E1 D9
14 IN 11 L4 T11 MB_DQ22 VDDQ<6> VSSQ<6>
A11/A7 DQ22 BI 14 22 C12 D4
10 K2 R10 MB_DQ21 VDDQ<5> VSSQ<5>
A10/A8 DQ21 BI 14 22 C9 D1
9 M9 R11 MB_DQ20 VDDQ<4> VSSQ<4>
A9/A3 DQ20 BI 14 22 C4 B12
8 K11 M10 MB_DQ19 VDDQ<3> VSSQ<3>
A8/A10 DQ19 BI 14 22 C1 B9
7 L9 N11 MB_DQ18 VDDQ<2> VSSQ<2>
A7/A11 DQ18 BI 14 22 A12 B4
6 K10 L10 MB_DQ17 VDDQ<1> VSSQ<1>
A6/A2 DQ17 BI 14 22 A1 B1
5 H11 M11 MB_DQ16 VDDQ<0> VSSQ<0>
A5/A1 DQ16 BI 14 22
4 K9 A4/A0 WDQS2 P11 MB_WDQS2 IN 14 V2 V3
3 M4 P10 MB_RDQS2 VDD<7> VSS<7>
A3/A9 RDQS2 OUT 22 14 M12 L12
2 K3 N10 MB_DM2 VDD<6> VSS<6>
A2/A6 DM2 IN 14 M1 L1
1 H2 VDD<5> VSS<5>
A1/A5 V11 G12
0 K4 G10 MB_DQ15 VDD<4> VSS<4>
A0/A4 DQ15 BI 14 22 F12 G1
F11 MB_DQ14 VDD<3> VSS<3>
MB_BA<2..0> DQ14 BI 14 22 F1 A10
14 IN 2 H10 F10 MB_DQ13 VDD<2> VSS<2>
BA2/RAS_N DQ13 BI 14 22 A11 V10
1 G9 E11 MB_DQ12 VDD<1> VSS<1>
BA1/BA0 DQ12 BI 14 22 A2 A3
0 G4 C10 MB_DQ11 VDD<0> VSS<0>
BA0/BA1 DQ11 BI 14 22
DQ10 C11 MB_DQ10 BI 14 22 K12 J3
MB_CKE H4 B10 MB_DQ9 VDDA<1> NC<1>
14 IN CKE/WE_N DQ9 BI 14 22 K1 J2
MB_WE_N H9 B11 MB_DQ8 VDDA<0> NC<0>
14 IN WE_N/CKE DQ8 BI 14 22
14 IN MB_CAS_N F4 CAS_N/CS_N WDQS1 D11 MB_WDQS1 IN 14
MB_RAS_N H3 D10 MB_RDQS1 J12 VSSA<1>
14 IN RAS_N/BA2 RDQS1 OUT 22 14 J1
MB_CS0_N F9 E10 MB_DM1 VSSA<0>
14 IN CS_N/CAS_N DM1 IN 14
12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MB_DQ7 BI 14 22

F2 MB_DQ6 X801995-011
DQ6 BI 14 22
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MB_DQ5 BI 14 22
DQ4 E2 MB_DQ4 BI 14 22
21 MEM_B_VREF1 H1 VREF1 DQ3 C3 MB_DQ3 14 22
MB_CS1_N 14
IN MEM_B_VREF0 H12 C2 MB_DQ2 BI IN
22 IN VREF0 DQ2 BI 14 22
DQ1 B3 MB_DQ1 BI 14 22
WDQS0 D2 MB_WDQS0 IN 14
RDQS0 D3 MB_RDQS0 OUT 22 14
DM0 E3 MB_DM0 IN 14
V_MEM
ZQ A4 MB_ZQ_TOP
1
1 R4F5
X801995-011
R5U4 243
549 1% V_MEM
1% CH
CH 402 MEMORY B, TOP, DECOUPLING
402 2 PARTITION B DECOUPLING
2 V_MEM
MEM_B_VREF1 OUT 21 22
C4F10 C5F5 C4F8 C4F5 C4F4 C5F2 C5F3 C5F4
10% 10% 10% 10% 10% 10% 10% 10%
1 1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C5F6 1 C5F8 X5R X5R X5R X5R X5R X5R X5R X5R
R5U3 4.7UF 220UF 402 402 402 402 402 402 402 402
C5U5 10% 20%
1.27K .1UF 6.3V 10V
1% 10% 2 X5R ELEC
6.3V 805
2 RDL
CH X5R
402 402
2
DRAWING
[PAGE_TITLE=MEMORY PARITION A, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
CONFIDENTIAL
MEMORY PARTITION B, BOTTOM

V_MEM
1 1
R5U2 R5U1
60.4 60.4
1% 1%
CH CH
402 402 U5U1 IC
2 2 V_MEM
GDDR136
14 IN MB_CLK1_DP MF=1 DQ31 T3 MB_DQ23 BI 14 21 U5U1 IC
DQ30 T2 MB_DQ22 BI 14 21
R3 MB_DQ21 GDDR136
DQ29 BI 14 21 V1
R2 MB_DQ20 VDDQ<21> MF=1
DQ28 BI 14 21 R12
M3 MB_DQ19 VDDQ<20>
DQ27 BI 14 21 R9 T12
N2 MB_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 14 21 R4 T9
L3 MB_DQ17 VDDQ<18> VSSQ<18>
DQ25 BI 14 21 R1 T4
DQ24 BI 14 21 N12 T1
J11 P2 MB_WDQS2 VDDQ<16> VSSQ<16>
MB_CLK1_DN J10 P3 MB_RDQS2 VDDQ<15> VSSQ<15>
N3 MB_DM2 VDDQ<14> VSSQ<14>
DM3 IN 14 N4 P4
13 IN RESET N1 P1
MB_A<11..0> DQ23 BI 14 21 J9 L11
14 IN 11 L9 T11 MB_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 14 21 J4 L2
10 K11 R10 MB_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 14 21 E12 G11
9 M4 R11 MB_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 14 21 E9 G2
8 K2 M10 MB_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 14 21 E4 D12
7 L4 N11 MB_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 14 21 E1 D9
6 K3 L10 MB_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 14 21 C12 D4
5 H2 M11 MB_DQ24 VDDQ<5> VSSQ<5>
A1/A5 DQ16 BI 14 21 C9 D1
4 K4 P11 MB_WDQS3 VDDQ<4> VSSQ<4>
3 M9 P10 MB_RDQS3 VDDQ<3> VSSQ<3>
2 K10 N10 MB_DM3 VDDQ<2> VSSQ<2>
A6/A2 DM2 IN 14 A12 B4
A5/A1 A1 B1
0 K9 G10 MB_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 14 21
MB_BA<2..0> DQ14 F11 MB_DQ6 BI 14 21 V2 V3
14 IN 2 H3 F10 MB_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 14 21 M12 L12
1 G4 E11 MB_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 14 21 M1 L1
0 G9 C10 MB_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 14 21 V11 G12
C11 MB_DQ2 VDD<4> VSS<4>
DQ10 BI 14 21 F12 G1
MB_CKE H9 B10 MB_DQ1 VDD<3> VSS<3>
MB_WE_N H4 B11 MB_DQ0 VDD<2> VSS<2>
MB_CAS_N F9 D11 MB_WDQS0 VDD<1> VSS<1>
MB_RAS_N H10 D10 MB_RDQS0 VDD<0> VSS<0>
14 IN MB_CS1_N F4 CAS_N/CS_N DM1 E10 MB_DM0 IN 14 K12 J3
VDDA<1> NC<1>
MEM_SCAN_BOT_EN A9 G3 MB_DQ15 K1 VDDA<0> NC<0> J2
12 IN MF DQ7 BI 14 21
DQ6 F2 MB_DQ14 BI 14 21 J12
MEM_SCAN_EN V4 F3 MB_DQ13 VSSA<1>
E2 MB_DQ12 VSSA<0>
DQ4 BI 14 21
22 IN MEM_B_VREF0 H1 VREF1 DQ3 C3 MB_DQ11 BI 14 21
21 IN MEM_B_VREF1 H12 VREF0 DQ2 C2 MB_DQ10 BI 14 21
B3 MB_DQ9 X801995-011
DQ1 BI 14 21
WDQS0 D2 MB_WDQS1 IN 14
RDQS0 D3 MB_RDQS1 OUT 21 14
V_MEM DM0 E3 MB_DM1 IN 14
ZQ A4 MB_ZQ_BOT
1
1 R4U1
X801995-011
R5F1 243
549 1%
1% CH
CH 402 V_MEM
402 2
2
MEM_B_VREF0 21 22
MEMORY B, BOTTOM, DECOUPLING
OUT
1
C4U10 C5U4 C4U7 C4U4 C4U3 C5U1 C5U2 C5U3
R5F2 C5F1 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
1.27K .1UF 10% 10% 10% 10% 10% 10% 10% 10%
1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V X5R X5R X5R X5R X5R X5R X5R X5R
CH X5R 402 402 402 402 402 402 402 402
402 402
2
DRAWING
[PAGE_TITLE=MEMORY PARITION B, TOP] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
CONFIDENTIAL
MEMORY PARTITION C, TOP

V_MEM
1 1
R3D5 R3D4
60.4 60.4 V_MEM
1% 1%
CH CH U3D1 IC
402 402 U3D1 IC
2 2 GDDR136
GDDR136 V1 VDDQ<21> MF=0
15 IN MC_CLK0_DP MF=0 DQ31 T3 MC_DQ31 BI 15 24 R12 VDDQ<20>
DQ30 T2 MC_DQ30 BI 15 24 R9 VDDQ<19> VSSQ<19> T12
DQ29 R3 MC_DQ29 BI 15 24 R4 VDDQ<18> VSSQ<18> T9
DQ28 R2 MC_DQ28 BI 15 24 R1 VDDQ<17> VSSQ<17> T4
DQ27 M3 MC_DQ27 BI 15 24 N12 VDDQ<16> VSSQ<16> T1
DQ26 N2 MC_DQ26 BI 15 24 N9 VDDQ<15> VSSQ<15> P12
DQ25 L3 MC_DQ25 BI 15 24 V12 VDDQ<14> VSSQ<14> P9
DQ24 M2 MC_DQ24 BI 15 24 N4 VDDQ<13> VSSQ<13> P4
J11 CLK_DP WDQS3 P2 MC_WDQS3 IN 15 N1 VDDQ<12> VSSQ<12> P1
15 IN MC_CLK0_DN J10 CLK_DN RDQS3 P3 MC_RDQS3 OUT 24 15 J9 VDDQ<11> VSSQ<11> L11
DM3 N3 MC_DM3 IN 15 J4 VDDQ<10> VSSQ<10> L2
13 IN MEM_RST V9 RESET E12 VDDQ<9> VSSQ<9> G11
MC_A<11..0> DQ23 T10 MC_DQ23 BI 15 24 E9 VDDQ<8> VSSQ<8> G2
15 IN 11 L4 T11 MC_DQ22 E4 D12
A11/A7 DQ22 BI 15 24 VDDQ<7> VSSQ<7>
10 K2 A10/A8 DQ21 R10 MC_DQ21 BI 15 24 E1 VDDQ<6> VSSQ<6> D9
9 M9 A9/A3 DQ20 R11 MC_DQ20 BI 15 24 C12 VDDQ<5> VSSQ<5> D4
8 K11 A8/A10 DQ19 M10 MC_DQ19 BI 15 24 C9 VDDQ<4> VSSQ<4> D1
7 L9 A7/A11 DQ18 N11 MC_DQ18 BI 15 24 C4 VDDQ<3> VSSQ<3> B12
6 K10 A6/A2 DQ17 L10 MC_DQ17 BI 15 24 C1 VDDQ<2> VSSQ<2> B9
5 H11 A5/A1 DQ16 M11 MC_DQ16 BI 15 24 A12 VDDQ<1> VSSQ<1> B4
4 K9 A4/A0 WDQS2 P11 MC_WDQS2 IN 15 A1 VDDQ<0> VSSQ<0> B1
3 M4 A3/A9 RDQS2 P10 MC_RDQS2 OUT 24 15
2 K3 A2/A6 DM2 N10 MC_DM2 IN 15 V2 VDD<7> VSS<7> V3
1 H2 A1/A5 M12 VDD<6> VSS<6> L12
0 K4 A0/A4 DQ15 G10 MC_DQ15 BI 15 24 M1 VDD<5> VSS<5> L1
MC_BA<2..0> DQ14 F11 MC_DQ14 BI 15 24 V11 VDD<4> VSS<4> G12
15 IN 2 H10 F10 MC_DQ13 F12 G1
BA2/RAS_N DQ13 BI 15 24 VDD<3> VSS<3>
1 G9 BA1/BA0 DQ12 E11 MC_DQ12 BI 15 24 F1 VDD<2> VSS<2> A10
0 G4 BA0/BA1 DQ11 C10 MC_DQ11 BI 15 24 A11 VDD<1> VSS<1> V10
DQ10 C11 MC_DQ10 BI 15 24 A2 VDD<0> VSS<0> A3
15 IN MC_CKE H4 CKE/WE_N DQ9 B10 MC_DQ9 BI 15 24
15 IN MC_WE_N H9 WE_N/CKE DQ8 B11 MC_DQ8 BI 15 24 K12 VDDA<1> NC<1> J3
15 IN MC_CAS_N F4 CAS_N/CS_N WDQS1 D11 MC_WDQS1 IN 15 K1 VDDA<0> NC<0> J2
15 IN MC_RAS_N H3 RAS_N/BA2 RDQS1 D10 MC_RDQS1 OUT 24 15
15 IN MC_CS0_N F9 CS_N/CAS_N DM1 E10 MC_DM1 IN 15 J12 VSSA<1>
J1 VSSA<0>
12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MC_DQ7 BI 15 24
DQ6 F2 MC_DQ6 BI 15 24
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ5 BI 15 24 X801995-011
DQ4 E2 MC_DQ4 BI 15 24
23 IN MEM_C_VREF1 H1 VREF1 DQ3 C3 MC_DQ3 BI 15 24
DQ1 B3 MC_DQ1 BI 15 24
DQ0 B2 MC_DQ0 15 24
MC_CS1_N 15
D2 MC_WDQS0 BI IN
WDQS0 IN 15
RDQS0 D3 MC_RDQS0 OUT 24 15
DM0 E3 MC_DM0 IN 15
ZQ A4 MC_ZQ_TOP
V_MEM 1
X801995-011 R3D1
243
1 1% V_MEM
CH
R2R1 402 MEMORY C, TOP, DECOUPLING
549 2
1% PARTITION C DECOUPLING
CH V_MEM
402
2 C2E1 C3E2 C3E1 C3E3 C3E5 C3E7 C3E6 C2E3
MEM_C_VREF1 23 24 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
OUT 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1 1 1 402 402 402 402 402 402 402 402
1 C2D3 C3C5 C2E8
4.7UF 4.7UF 4.7UF
10% 10% 10%
R2R2 C2R9 6.3V 6.3V 6.3V
1.27K .1UF 2 X5R 2 X5R 2 X5R
1% 10% 805 805 805
6.3V
CH X5R
402 402
2
DRAWING
[PAGE_TITLE=MEMORY PARTITION B, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
CONFIDENTIAL
MEMORY PARTITION C, BOTTOM

V_MEM
1 1
R2R4 R2R3
60.4 60.4
1% 1%
CH CH V_MEM
402 402 U3R1 IC
2 2 V_MEM
GDDR136
MC_CLK1_DP T3 MC_DQ23 U3R1 IC
15 IN MF=1 DQ31 BI 15 23
DQ30 T2 MC_DQ22 BI 15 23 1 GDDR136
DQ29 R3 MC_DQ21 BI 15 23 C3T4 V1 VDDQ<21> MF=1
DQ28 R2 MC_DQ20 15 23 .1UF R12 VDDQ<20>
M3 MC_DQ19 BI 10%
R9 T12
DQ27 BI 15 23 6.3V VDDQ<19> VSSQ<19>
DQ26 N2 MC_DQ18 15 23
2 X5R R4 VDDQ<18> VSSQ<18> T9
L3 MC_DQ17 BI 402 R1 T4
DQ25 BI 15 23 VDDQ<17> VSSQ<17>
DQ24 M2 MC_DQ16 BI 15 23 N12 VDDQ<16> VSSQ<16> T1
J11 CLK_DP WDQS3 P2 MC_WDQS2 IN 15 N9 VDDQ<15> VSSQ<15> P12
15 IN MC_CLK1_DN J10 CLK_DN RDQS3 P3 MC_RDQS2 OUT 23 15 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MC_DM2 IN 15 N4 VDDQ<13> VSSQ<13> P4
13 IN MEM_RST V9 RESET N1 VDDQ<12> VSSQ<12> P1
MC_A<11..0> DQ23 T10 MC_DQ31 BI 15 23 J9 VDDQ<11> VSSQ<11> L11
15 IN 11 L9 T11 MC_DQ30 J4 L2
A7/A11 DQ22 BI 15 23 VDDQ<10> VSSQ<10>
10 K11 A8/A10 DQ21 R10 MC_DQ29 BI 15 23 E12 VDDQ<9> VSSQ<9> G11
9 M4 A3/A9 DQ20 R11 MC_DQ28 BI 15 23 E9 VDDQ<8> VSSQ<8> G2
8 K2 A10/A8 DQ19 M10 MC_DQ27 BI 15 23 E4 VDDQ<7> VSSQ<7> D12
7 L4 A11/A7 DQ18 N11 MC_DQ26 BI 15 23 E1 VDDQ<6> VSSQ<6> D9
6 K3 A2/A6 DQ17 L10 MC_DQ25 BI 15 23 C12 VDDQ<5> VSSQ<5> D4
5 H2 A1/A5 DQ16 M11 MC_DQ24 BI 15 23 C9 VDDQ<4> VSSQ<4> D1
4 K4 A0/A4 WDQS2 P11 MC_WDQS3 IN 15 C4 VDDQ<3> VSSQ<3> B12
3 M9 A9/A3 RDQS2 P10 MC_RDQS3 OUT 23 15 C1 VDDQ<2> VSSQ<2> B9
2 K10 A6/A2 DM2 N10 MC_DM3 IN 15 A12 VDDQ<1> VSSQ<1> B4
1 H11 A5/A1 A1 VDDQ<0> VSSQ<0> B1
0 K9 A4/A0 DQ15 G10 MC_DQ7 BI 15 23
MC_BA<2..0> DQ14 F11 MC_DQ6 BI 15 23 V2 VDD<7> VSS<7> V3
15 IN 2 H3 F10 MC_DQ5 M12 L12
RAS_N/BA2 DQ13 BI 15 23 VDD<6> VSS<6>
1 G4 BA0/BA1 DQ12 E11 MC_DQ4 BI 15 23 M1 VDD<5> VSS<5> L1
0 G9 BA1/BA0 DQ11 C10 MC_DQ3 BI 15 23 V11 VDD<4> VSS<4> G12
DQ10 C11 MC_DQ2 BI 15 23 F12 VDD<3> VSS<3> G1
15 IN MC_CKE H9 WE_N/CKE DQ9 B10 MC_DQ1 BI 15 23 F1 VDD<2> VSS<2> A10
15 IN MC_WE_N H4 CKE/WE_N DQ8 B11 MC_DQ0 BI 15 23 A11 VDD<1> VSS<1> V10
15 IN MC_CAS_N F9 CS_N/CAS_N WDQS1 D11 MC_WDQS0 IN 15 A2 VDD<0> VSS<0> A3
15 IN MC_RAS_N H10 BA2/RAS_N RDQS1 D10 MC_RDQS0 OUT 23 15
15 IN MC_CS1_N F4 CAS_N/CS_N DM1 E10 MC_DM0 IN 15 K12 VDDA<1> NC<1> J3
K1 VDDA<0> NC<0> J2
12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MC_DQ15 BI 15 23
DQ6 F2 MC_DQ14 BI 15 23 J12 VSSA<1>
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ13 BI 15 23 J1 VSSA<0>
DQ4 E2 MC_DQ12 BI 15 23
23 IN MEM_C_VREF1 H12 VREF0 DQ2 C2 MC_DQ10 BI 15 23 X801995-011
WDQS0 D2 MC_WDQS1 IN 15
RDQS0 D3 MC_RDQS1 OUT 23 15
DM0 E3 MC_DM1 IN 15
V_MEM
ZQ A4 MC_ZQ_BOT
1
1 X801995-011 R3R1
243
R3D3 1%
549 CH
1% V_MEM
402
CH 2 MEMORY C, BOTTOM, DECOUPLING
402
2
MEM_C_VREF0 OUT 23 24
C2T1 C3T1 C3T2 C3T3 C3T5 C3T7 C3T6 C2T3

1 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
R3D2 C3D3 X5R X5R X5R X5R X5R X5R X5R X5R
1.27K .1UF 402 402 402 402 402 402 402 402
1% 10%
6.3V
CH X5R
402 402
2
DRAWING
[PAGE_TITLE=MEMORY PARITION C, TOP] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT PROJECT NAME
FALCON_RETAIL
PAGE
24/82
REV
1.0
CONFIDENTIAL
V_MEM MEMORY PARTITION D, TOP

1 1
R3E5 R3E4 MD_CLK0
60.4 60.4 V_MEM
1% 1% STITCHING CAP
CH CH U3E1 IC
402 402 V_MEM
2 2 U3E1 IC GDDR136
V1 VDDQ<21> MF=0
GDDR136 R12
MD_CLK0_DP T3 MD_DQ31 VDDQ<20>
15 IN MF=0 DQ31 BI 15 26 1 R9 T12
T2 MD_DQ30 C3R3 VDDQ<19> VSSQ<19>
DQ30 BI 15 26 R4 T9
R3 MD_DQ29 .1UF VDDQ<18> VSSQ<18>
DQ29 BI 15 26 10% R1 T4
R2 MD_DQ28 VDDQ<17> VSSQ<17>
DQ28 BI 15 26 6.3V N12 T1
DQ27 M3 MD_DQ27 15 26
2 X5R VDDQ<16> VSSQ<16>
MD_DQ26 BI 402 N9 VDDQ<15> VSSQ<15> P12
DQ26 N2 15 26
L3 MD_DQ25 BI V12 VDDQ<14> VSSQ<14> P9
DQ25 BI 15 26 N4 P4
M2 MD_DQ24 VDDQ<13> VSSQ<13>
DQ24 BI 15 26 N1 P1
J11 P2 MD_WDQS3 VDDQ<12> VSSQ<12>
CLK_DP WDQS3 IN 15 J9 L11
MD_CLK0_DN J10 P3 MD_RDQS3 VDDQ<11> VSSQ<11>
15 IN CLK_DN RDQS3 OUT 26 15 J4 L2
N3 MD_DM3 VDDQ<10> VSSQ<10>
DM3 IN 15 E12 G11
13 IN RESET E9 G2
T10 MD_DQ23 VDDQ<8> VSSQ<8>
MD_A<11..0> DQ23 BI 15 26 E4 D12
15 IN 11 L4 T11 MD_DQ22 VDDQ<7> VSSQ<7>
A11/A7 DQ22 BI 15 26 E1 D9
10 K2 R10 MD_DQ21 VDDQ<6> VSSQ<6>
A10/A8 DQ21 BI 15 26 C12 D4
9 M9 R11 MD_DQ20 VDDQ<5> VSSQ<5>
A9/A3 DQ20 BI 15 26 C9 D1
8 K11 M10 MD_DQ19 VDDQ<4> VSSQ<4>
A8/A10 DQ19 BI 15 26 C4 B12
7 L9 N11 MD_DQ18 VDDQ<3> VSSQ<3>
A7/A11 DQ18 BI 15 26 C1 B9
6 K10 L10 MD_DQ17 VDDQ<2> VSSQ<2>
A6/A2 DQ17 BI 15 26 A12 B4
5 H11 M11 MD_DQ16 VDDQ<1> VSSQ<1>
A5/A1 DQ16 BI 15 26 A1 B1
4 K9 P11 MD_WDQS2 VDDQ<0> VSSQ<0>
A4/A0 WDQS2 IN 15
3 M4 A3/A9 RDQS2 P10 MD_RDQS2 OUT 26 15 V2 V3
2 K3 N10 MD_DM2 VDD<7> VSS<7>
A2/A6 DM2 IN 15 M12 L12
1 H2 VDD<6> VSS<6>
A1/A5 M1 L1
0 K4 G10 MD_DQ15 VDD<5> VSS<5>
A0/A4 DQ15 BI 15 26 V11 G12
F11 MD_DQ14 VDD<4> VSS<4>
MD_BA<2..0> DQ14 BI 15 26 F12 G1
15 IN 2 H10 F10 MD_DQ13 VDD<3> VSS<3>
BA2/RAS_N DQ13 BI 15 26 F1 A10
1 G9 E11 MD_DQ12 VDD<2> VSS<2>
BA1/BA0 DQ12 BI 15 26 A11 V10
0 G4 C10 MD_DQ11 VDD<1> VSS<1>
BA0/BA1 DQ11 BI 15 26 A2 A3
C11 MD_DQ10 VDD<0> VSS<0>
DQ10 BI 15 26
15 IN MD_CKE H4 CKE/WE_N DQ9 B10 MD_DQ9 BI 15 26 K12 J3
MD_WE_N H9 B11 MD_DQ8 VDDA<1> NC<1>
15 IN WE_N/CKE DQ8 BI 15 26 K1 J2
MD_CAS_N F4 D11 MD_WDQS1 VDDA<0> NC<0>
15 IN CAS_N/CS_N WDQS1 IN 15
15 IN MD_RAS_N H3 RAS_N/BA2 RDQS1 D10 MD_RDQS1 OUT 26 15 J12
MD_CS0_N F9 E10 MD_DM1 VSSA<1>
15 IN CS_N/CAS_N DM1 IN 15 J1 VSSA<0>
12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MD_DQ7 BI 15 26
DQ6 F2 MD_DQ6 BI 15 26
MEM_SCAN_EN V4 F3 MD_DQ5 X801995-011
12 IN SCAN_EN DQ5 BI 15 26
DQ4 E2 MD_DQ4 BI 15 26
25 IN MEM_D_VREF1 H1 VREF1 DQ3 C3 MD_DQ3 BI 15 26
26 IN MEM_D_VREF0 H12 VREF0 DQ2 C2 MD_DQ2 BI 15 26
DQ1 B3 MD_DQ1 15 26
MD_CS1_N 15
B2 MD_DQ0 BI IN
DQ0 BI 15 26
WDQS0 D2 MD_WDQS0 IN 15
RDQS0 D3 MD_RDQS0 OUT 26 15
DM0 E3 MD_DM0 IN 15
ZQ A4 MD_ZQ_TOP
V_MEM 1
X801995-011 R3E1
243
1% V_MEM
1
CH
R2T4 402 MEMORY D, TOP, DECOUPLING
549 2 PARTITION D DECOUPLING
1% V_MEM
CH
402
2 C2D2 C2D1 C3D1 C3D2 C3D4 C3D6 C3D5 C2D4
MEM_D_VREF1 OUT 25 26 10% 10% 10% 10% 10% 10% 10% 10%
1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C2E2 X5R X5R X5R X5R X5R X5R X5R X5R
4.7UF 402 402 402 402 402 402 402 402
10%
1 6.3V
2 X5R
R2T3 C2T2 805
1.27K .1UF
1% 10%
6.3V
CH X5R
402 402
2
DRAWING
[PAGE_TITLE=MEMORY PARTITION C, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
CONFIDENTIAL
MEMORY PARTITION D, BOTTOM

1 1
R2T5 R2T6
60.4 60.4
1% 1%
CH CH
402 402
2 2
U3T1 IC
GDDR136 V_MEM
15 IN MD_CLK1_DP MF=1 DQ31 T3 MD_DQ23 BI 15 25 U3T1 IC
DQ30 T2 MD_DQ22 BI 15 25
R3 MD_DQ21 GDDR136
DQ29 BI 15 25 V1
R2 MD_DQ20 VDDQ<21> MF=1
DQ28 BI 15 25 R12
M3 MD_DQ19 VDDQ<20>
DQ27 BI 15 25 R9 T12
N2 MD_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 15 25 R4 T9
L3 MD_DQ17 VDDQ<18> VSSQ<18>
DQ25 BI 15 25 R1 T4
M2 MD_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 15 25 N12 T1
J11 P2 MD_WDQS2 VDDQ<16> VSSQ<16>
MD_CLK1_DN J10 P3 MD_RDQS2 VDDQ<15> VSSQ<15>
N3 MD_DM2 VDDQ<14> VSSQ<14>
DM3 IN 15 N4 P4
13 IN RESET N1 P1
T10 MD_DQ31 VDDQ<12> VSSQ<12>
MD_A<11..0> DQ23 BI 15 25 J9 L11
15 IN 11 L9 T11 MD_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 15 25 J4 L2
10 K11 R10 MD_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 15 25 E12 G11
9 M4 R11 MD_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 15 25 E9 G2
8 K2 M10 MD_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 15 25 E4 D12
7 L4 N11 MD_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 15 25 E1 D9
6 K3 L10 MD_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 15 25 C12 D4
5 H2 M11 MD_DQ24 VDDQ<5> VSSQ<5>
A1/A5 DQ16 BI 15 25 C9 D1
4 K4 P11 MD_WDQS3 VDDQ<4> VSSQ<4>
3 M9 P10 MD_RDQS3 VDDQ<3> VSSQ<3>
2 K10 N10 MD_DM3 VDDQ<2> VSSQ<2>
A6/A2 DM2 IN 15 A12 B4
A5/A1 A1 B1
0 K9 G10 MD_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 15 25
MD_BA<2..0> DQ14 F11 MD_DQ6 BI 15 25 V2 V3
15 IN 2 H3 F10 MD_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 15 25 M12 L12
1 G4 E11 MD_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 15 25 M1 L1
0 G9 C10 MD_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 15 25 V11 G12
C11 MD_DQ2 VDD<4> VSS<4>
DQ10 BI 15 25 F12 G1
MD_CKE H9 B10 MD_DQ1 VDD<3> VSS<3>
MD_WE_N H4 B11 MD_DQ0 VDD<2> VSS<2>
MD_CAS_N F9 D11 MD_WDQS0 VDD<1> VSS<1>
MD_RAS_N H10 D10 MD_RDQS0 VDD<0> VSS<0>
15 IN MD_CS1_N F4 CAS_N/CS_N DM1 E10 MD_DM0 IN 15 K12 VDDA<1> NC<1> J3
V_MEM K1 VDDA<0> NC<0> J2
12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MD_DQ15 BI 15 25
DQ6 F2 MD_DQ14 BI 15 25
MEM_SCAN_EN V4 F3 MD_DQ13 J12 VSSA<1>
E2 MD_DQ12 VSSA<0>
DQ4 BI 15 25
26 IN MEM_D_VREF0 H1 VREF1 DQ3 C3 MD_DQ11 BI 15 25 1
MEM_D_VREF1 H12 C2 MD_DQ10 C2T7
25 IN VREF0 DQ2 BI 15 25 4.7UF
B3 MD_DQ9 10% X801995-011
DQ1 BI 15 25
B2 MD_DQ8 6.3V
DQ0 BI 15 25 2 X5R
WDQS0 D2 MD_WDQS1 IN 15 805
RDQS0 D3 MD_RDQS1 OUT 25 15
DM0 E3 MD_DM1 IN 15
V_MEM
ZQ A4 MD_ZQ_BOT
1
1 X801995-011 R3T1
243
R3E3 1% V_MEM
549 CH
1% 402 MEMORY D, BOTTOM, DECOUPLING
CH 2
402
2
MEM_D_VREF0 OUT 25 26
V_MEM C2R7 C3R1 C3R2 C3R4 C3R7 C3R6 C2R10 C2R8
10% 10% 10% 10% 10% 10% 10% 10%
MEMORY D, BOTTOM, DECOUPLING 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1 X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402
R3E2 C3E4
1.27K .1UF
1% 10%
6.3V C2R13 C2T6 C3E8 C3F5 C3U4 C4F14 C4F15 C4U12
CH X5R .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
402 402 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402 402 402 402 402 402 402 402
DRAWING
[PAGE_TITLE=MEMORY PARTITION D, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
CONFIDENTIAL
V_12P0
HANA, CLOCKS + STRAPPING R4C11 1 R4C9 2
33 5% 49.9 1%
402 CH 402 CH
HANA_V_12P0_DET_R
CPU_CLK_DP OUT 4
1 R4B9 2 1 R4B8 2 1 R4B2 2 1 FTP FT4P4
CPU_CLK_DN OUT 4
1 R3B2 2 ANA_VRST_OK 34 R4C12 1 R4C10 2
1% 1K 1% 75 1% 68.1 OUT
1M 5% CH 402 1 CH 402 CH 402 ANA_V12P0_PWRGD OUT 34 49
1 C4B13 SMC_RST_N 33 5% 49.9 1%
402 CH FT2P7 FTP 470PF OUT 34 47 58
5% 402 CH 402 CH
50V 1
Y3B1
1 R4B1 2
2 EMPTY 1
27MHZ 402 U4C2 1 OF 4 IC R2P3 FTP FT2N3
1 2 1K 1 R3C8 1 R3C16 2
5% 10K HANA 5% FTP FT3P4
CH 402
SM CH 33 5% 49.9 1%
XTAL HANA_V_12P0_DET B6 V_12P0_DET V_RST_OK E11 402 402 CH 402 CH
34 ANA_RST_N M2 CORE_RST_N* V_12P0_OK D10 2
2 2 IN 1 2 R2P1 1 GPU_CLK_DP OUT 13
C3B7 C3B6 FT4P1 FTP
HANA_POR_BYPASS E12 POR_BYPASS SMC_RST_N* M3 SMC_RST_N_R
GPU_CLK_DN
22PF 22PF OUT 13
5% 5% 10K 5%
1 50V
1 50V 402 CH R3C7 1 R3C15 2
NPO NPO
402 402 33 5% 49.9 1%
402 CH 402 CH
HANA_XTAL_IN P2 XTAL_IN CPU_CLK_DP R14 CPU_CLK_DP_R
HANA_XTAL_OUT R2 XTAL_OUT CPU_CLK_DN P14 CPU_CLK_DN_R
V_3P3STBY R4C8 1 R3C9 2

HANA_XTAL_VSS_CAP P3 XTAL_VSS_CAP NB_CLK_DP R13 GPU_CLK_DP_R
NB_CLK_DN P13 GPU_CLK_DN_R 33 5% 49.9 1%
2 R4N5 1 HANA_XTAL_BYPASS M4 XTAL_BYPASS 402 CH 402 CH
1K 5% PCIEX_CLK_DP R10 PCIEX_CLK_DP_R
1 P10
PCIEX_CLK_DP OUT 33
FT2P4 FTP 402 EMPTY PCIEX_CLK_DN PCIEX_CLK_DN_R
PCIEX_CLK_DN OUT 33
2 R4B17 1 SATA_CLK_DP R9 SATA_CLK_DP_R 1 R4B27 2 1 R3B5 2
34 IN ANA_CLK_OE ANA_CLK_OE_R N3 ANA_CLK_OE P9
1 FTP FT3P2
SATA_CLK_DN SATA_CLK_DN_R
1K 5% 33 5% 49.9 1% 1 FTP FT3P1
2 402 CH R6 402 CH 402 CH
2 R4P1 1 HANA_CLK_DRV_RSET2 K13 SATA_CLK_REF SATA_CLK_REF_R
R3B1 CLK_DRV_RSET2
10K 475 1% HANA_CLK_DRV_RSET1 R11 CLK_DRV_RSET1
PIX_CLK_OUT_DP M15 ANA_PIX_CLK_2X_DP_R
5% 402 CH M14
EMPTY
PIX_CLK_OUT_DN ANA_PIX_CLK_2X_DN_R 1 R4B26 2 1 R3B4 2
402 2 R4N6 1
1 ENET_CLK P6 ENET_CLK_R 33 5% 49.9 1%
475 1% 402 CH 402 CH
402 CH R8 STBY_CLK_R SATA_CLK_DP
STBY_CLK OUT 33
SATA_CLK_DN OUT 33
AUD_CLK R4 AUD_CLK_R
58 34 SMB_DATA N1 SMB_DATA
1 R4B25 2 1 R3B6 2
BI SMB_CLK 1
58 34 P1 SMB_CLK 33 5% 49.9 1% FTP FT1P2
IN 1 FTP FT1P1
402 CH 402 CH
AV_CLK N2 HANA_AV_CLK 1 FTP FT4N5 1 R4B6 2 SATA_CLK_REF 33
OUT
33 5%
HANA_TCLK G12 TCK <DN> 402 CH 1 1
FTP FT2N4
HANA_TDO F11 TDO 1 C3B1
HANA_TDI J12 TDI <UP> 10PF
F12
R4N4 5%
HANA_TMS TMS <UP> 10K 50V
HANA_TRST H12 TRST 5% 1 R4C15 2 1 R4C13 2 2 EMPTY
402
CH 33 5% 49.9 1%
402 402 CH 402 CH
X802478-003 2
ANA_PIX_CLK_2X_DP OUT 13
ANA_PIX_CLK_2X_DN OUT 13
1 R4C16 2 1 R4C14 2
1 FTP FT4P2
33 5% 49.9 1% 1
402 CH 402 CH FTP FT4P3
J5C1
2X3HDR
1 2
3 4 1 R4B5 2 ENET_CLK 39 40
5 6
OUT
33 5%
402 CH 1
C3B4
HDR 10PF
5%
50V
2 EMPTY
402
SMB_CLK STITCH STBY_CLK STITCH SATA_CLK STITCH 1 R4B24 2 STBY_CLK OUT 34

ENET_CLK STITCH 33 5%
402 CH 1 1
SATA_CLK_REF STITCH C3B2 FTP FT2R2
V_1P8STBY V_1P8STBY V_3P3 10PF
V_3P3 5%
V_3P3 50V
2 EMPTY 1
402 FTP FT2P2
1 R4B4 2 AUD_CLK
1 1 1 OUT 36
C2P7 C3N6 C1P9 1 1 33 5%
.1UF .1UF .1UF C1B4 C2B14 1 402 CH 1
10% V_3P3STBY 10% 10% .1UF .1UF C2B17 C3B12
6.3V 6.3V 6.3V 10% 10% .1UF 10PF
2 X5R 2 X5R 2 X5R 6.3V 6.3V 10% 5%
402 402 402 2 X5R 2 X5R 2 6.3V
2 50V
402 402 X5R EMPTY
402 402
DRAWING
[PAGE_TITLE=HANA, CLOCKS + STRAPING] Tue May 08 18:24:16 2007
CONFIDENTIAL
HANA, VIDEO + FAN + JTAG

U4C2 2 OF 4 IC
HANA
13 IN GPU_PIX_CLK_1X G14 PIX_CLK_IN VID_INT L3 ANA_VID_INT OUT 33
STBY_CLK STITCH 13 IN PIX_DATA<14..0> VID_DACD_DP
14 C14 PIX_DATA14 DAC_D_OUT_DP A7 44
C15 B7
OUT 1 R4B10 2
13 PIX_DATA13 DAC_D_OUT_DN VID_DACD_DN
V_1P8STBY V_3P3STBY V_1P8STBY V_3P3STBY 12 D14 PIX_DATA12 37.4 1%
11 D15 PIX_DATA11 DAC_C_OUT_DP A8 VID_DACC_DP OUT 44 402 CH
10 E14 B8 VID_DACC_DN
1 R4B11 2
PIX_DATA10 DAC_C_OUT_DN
9 E15 PIX_DATA9 37.4 1%
1 VID_DACB_DP
1 1 C2R1 1 1 8 F14 PIX_DATA8 DAC_B_OUT_DP A9
OUT 44 402 CH
C3P4 C2R2 .1UF C3N10 C2P50 7 F15 B9 VID_DACB_DN
1 R4B13 2
10% PIX_DATA7 DAC_B_OUT_DN
.1UF .1UF 6.3V .1UF .1UF 6 G15 PIX_DATA6
10% 10% 2 10% 10% 37.4 1%
6.3V 6.3V X5R 6.3V 6.3V 5 H14 PIX_DATA5 DAC_A_OUT_DP A10 VID_DACA_DP OUT 44 402 CH
2 X5R 2 X5R 402 2 X5R 2 X5R 4 H15 PIX_DATA4 DAC_A_OUT_DN B10 VID_DACA_DN 1 R4B14 2
402 402 402 402 J14
V_1P8STBY 3 PIX_DATA3 37.4 1%
2 J15 PIX_DATA2 HSYNC_OUT B5 VID_HSYNC_OUT_R OUT 44 402 CH
V_3P3STBY 1 K14 PIX_DATA1 VSYNC_OUT A5 VID_VSYNC_OUT_R 44 V_3P3STBY
K15
OUT
0 PIX_DATA0
1 R4B23 2
13 IN GPU_HSYNC_OUT L14 HSYNC_IN TMDS_EXT_SWING A2 HDMI_EXT_SWING 422 1%
13 IN GPU_VSYNC_OUT L15 VSYNC_IN 402 CH
TMDS_TXC_DP B1 HDMI_TXC_DP OUT 29
2 R4B12 1 HANA_DAC_RSET C8 DAC_RSET TMDS_TXC_DN B2
C4B12 2 R4B22 1
787 1% 2 1 HDMI_TXC_DP_R
402 CH A4 HDMI_HPD TMDS_TX2_DP H1
1 R4B18 2 I2S_SD3 TMDS_TX2_DN H2 .1UF 10% 301 1%
6.3V 603 CH
10K 5% X5R
402 CH TMDS_TX1_DP F1 402
29 IN HDMI_HPD TMDS_TX1_DN F2
HDMI_TXC_DN OUT 29
1 R4N3 2 I2S_SD2 D1
TMDS_TX0_DP
10K 5% TMDS_TX0_DN D2
HDMI_TX2_DP OUT 29
402 CH
36 IN SB_SPDIF_OUT M1 SPDIF_IN SPDIF_OUT B4 HANA_SPDIF_OUT OUT 44 C4B4
2 1 HDMI_TX2_DP_R 2 R4B19 1
1 R4N2 2 I2S_BCLK K1 DDC_SCK B3 HDMI_DDC_CLK OUT 34 44 29
I2S_SD1 36 I2S_SCK 301 1%
IN I2S_WS K2 DDC_SDA A3 HDMI_DDC_DATA OUT 34 44 29 .1UF 10%
10K 5% 36 IN I2S_WS 6.3V 603 CH
402 CH L2 I2S_SD3 X5R
K4 I2S_SD2 402
K3 I2S_SD1 HDMI_TX2_DN OUT 29
36 IN I2S_SD L1 I2S_SD0
2 R4B15 1 HANA_OP2_DP C11 FAN_OP2_DP FAN_OUT2 B11 HDMI_TX1_DP 29
HANA_OP2_DN A11
OUT
10K 5% 28 IN FAN_OP2_DN
402 CH C4B10 2 R4B20 1
2 1 HDMI_TX1_DP_R
C12 FAN_OP1_DP FAN_OUT1 A12 FAN1_OUT OUT 43
43 FAN1_FDBK B12 FAN_OP1_DN .1UF 10% 301 1%
IN 6.3V 603 CH
A15 C13 X5R
TEMP_N TEMP3_P 402
TEMP2_P B15
A6 B13
HDMI_TX1_DN OUT 29
34 SMC_PWM0 2 R4C1 1 FAN_OP1_DP
BND_GAP_CAP BND_GAP_CAP TEMP1_P
IN TEMP0_P A13
205K 1% TEMP_RSET A14 TEMP_RSET TEMPCAL_P B14
402 CH 1 HDMI_TX0_DP OUT 29
C4P2
.22UF
10% X802478-003 C4B11 2 R4B21 1
6.3V 1 2 1 HDMI_TX0_DP_R
2 X5R DB4P5
402 .1UF 10% 301 1%
1 SATA_CLK_REF STITCH 6.3V 603 CH
X5R
R4C2 402
ST4C1 11K V_3P3 HDMI_TX0_DN 29
CPU_TEMP_N 2 1 1% OUT
4 IN CH
402
SHORT 2 1 R4B3 2
ST4C2 1 HANA_OP2_OUT HANA_OP2_DN OUT 28
C1P13 V_1P8 0 5%
13 IN GPU_TEMP_N 2 1 .1UF
10% 402 CH
SHORT 6.3V
1 2 X5R
FT4N4 FTP 402
ST4C5
13 IN EDRAM_TEMP_N 2 1 2 1
C4B3 1
DB4P1 CUSTOM THERMAL
SHORT 0.01UF DB4P2 CALIBRATION PADS
10%
16V 1 LOCATION MUST
ST4C4 1 X7R Q1G3 DB4P3
1 REMAIN LOCKED
28 IN BRD_TEMP_N 2 1 402 MMBT3906 DB4P4
1 2 XSTR
FT4N1 FTP
SHORT 1
ST4C3 CAL_TEMP_P CAL_TEMP_N OUT 28
CAL_TEMP_N 2 1 3 CPU_TEMP_P
28 IN OUT 4
GPU_TEMP_P OUT 13
SHORT EDRAM_TEMP_P OUT 13
BRD_TEMP_P OUT 28
28 IN BRD_TEMP_P
28 OUT BRD_TEMP_N
DRAWING
[PAGE_TITLE=HANA, VIDEO + FAN + JTAG] Tue May 08 18:24:16 2007
CONFIDENTIAL
R2A11
0 5%
603 CH
44 IN V_AVIP
NA 1
SM FTP FT2M2
1
CM2A1 EMPTY 1
FTP FT2M3 C2A9
.1UF
CMCHOKE 1 10%
28 IN HDMI_TX2_DP 1 2 FTP FT2M4 6.3V
1 2 X5R
FTP FT2M5 402
1
FTP FT3M1
28 IN HDMI_TX2_DN 4 3
1
ESDB-MLP7 ESDB-MLP7 FTP FT3M2
1
402 402 1
X801560-001 FTP FT3M3 J2A1 HDR
EG2A2 EG2A1
1 HDMI
R2A12 FTP FT3M4
DIO DIO HDMI_TX2_DP_CM 1 TMDS_DATA2_DP
0 5% 2 TMDS_DATA2_SHD
603 CH HDMI_TX2_DN_CM 3 TMDS_DATA2_DN
2
HDMI_TX1_DP_CM 4 TMDS_DATA1_DP
5 TMDS_DATA1_SHD
HDMI_TX1_DN_CM 6 TMDS_DATA1_DN
HDMI_TX0_DP_CM 7 TMDS_DATA0_DP
R2A13 8 TMDS_DATA0_SHD
HDMI_TX0_DN_CM 9 TMDS_DATA0_DN
0 5% HDMI_TXC_DP_CM 10 TMDS_CLK_DP
603 CH 11 TMDS_CLK_SHD
NA HDMI_TXC_DN_CM 12 TMDS_CLK_DN
SM 1 HDMI_CEC 13 CEC
DB3A1
CM2A2 EMPTY V_5P0STBY 14 RESERVED
15 SCL
HDMI_TX1_DP 1 CMCHOKE 2 16
28 IN SDA
17 DDC_CEC_GND
18 5VCC
HDMI_TX1_DN 4 3
1 1 19 HOT_PLUG_DET
28 IN ESDB-MLP7 ESDB-MLP7 R3M5 R3M6 23 ME4
1
1
402 402 2K 2K 22
X801560-001 ME3
EG2A4 EG2A3 1% 1% 1 21 ME2
HDMI_HPD_PIN
CH CH FTP FT4N2
R2A14 20 ME1
DIO DIO 402 402
2 2
0 5% X806395-002
603 CH HDMI_DDC_CLK
34 28 IN
2
2
28 44 IN HDMI_DDC_DATA 1
FTP FT2N6
34
44 1 R3M7 2 HDMI_HPD 28
OUT
R3A10 CR3M1 CR3M1 10K 5%
402 CH
0 5% 2 5
603 CH
NA 6 3 PGB0010603
1
1
SM 603
CM3A1 EMPTY 1 4 R3M1 EG3M1
ESDB-MLP7 47K
ESDB-MLP7
1
HDMI_TX0_DP CMCHOKE 402 5%
1
28 1 2 BAV99 BAV99 402 DIO
IN DIO EG3M2 DIO CH
EG3M3 402
EMPTY
2
2
HDMI_TX0_DN 4 3 EMPTY
28 IN ESDB-MLP7 ESDB-MLP7
1
402 402
2
X801560-001
2
EG3A2 EG3A1
R3A11 DIO DIO
0 5%
603 CH
2
R3A12
0 5%
603 CH
NA
SM
CM3A2 EMPTY
HDMI_TXC_DP 1 CMCHOKE 2
28 IN
28 IN HDMI_TXC_DN 4 3
ESDB-MLP7 ESDB-MLP7
1
402 402
X801560-001
EG3A4 EG3A3
R3A13 DIO DIO
0 5%
603 CH
2
DRAWING
[PAGE_TITLE=CONN, HDMI] Tue May 08 18:24:16 2007
CONFIDENTIAL
HANA, POWER + DECOUPLING

V_3P3STBY
FB4N5
1 2 V_HANA_VAA_RTS33S
120 FB
0.2A 603
1
C4N360.5 DCR C4N37 C4N35
4.7UF 4.7UF .1UF
10% 10% 10%
6.3V 6.3V 6.3V
X5R 2 X5R X5R
805 805 402 V_1P8STBY
U4C2 3 OF 4 IC
HANA
V_3P3 D12 VAA_RTS33S VAA_VID_PLL M12
D11 AVSS_RTS33S AVSS_VID_PLL M13
FB4N8
1 2 V_HANA_VAA_DAC33M E9 VAA_DAC33M3 VAA_GP_PLL R7
60 FB D9 VAA_DAC33M2 AVSS_GP_PLL P7
0.5A 603 C9 VAA_DAC33M1
0.1DCR 1 1
C4N15 C4N24 C4N23 C4N29 D8 AVSS_DAC33M1 VAA_100M_PLL_A N15
4.7UF 4.7UF .1UF .1UF AVSS_100M_PLL_A1 P15
10% 10% 10% 10% V_3P3STBY
6.3V 6.3V 6.3V 6.3V C7 VAA_DAC33M0 AVSS_100M_PLL_A0 R15
X5R 2 X5R X5R 2 X5R D7 AVSS_DAC33M0
805 805 402 402 R12
VAA_100M_PLL_D
C6 VAA_POR33S AVSS_100M_PLL_D P12
C10 VAA_FAN33S VDDC_STBY_PLL N7

V_3P3STBY VSSC_STBY_PLL M7
R3 VAA_XTAL33S V_1P8STBY
VDDC_25M_PLL N5
1 R4N1 2 N8 VDDIO33S_STBY_PLL VSSC_25M_PLL M5
V_HANA_VAA_XTAL_33S
P8 VSSIO33S_STBY_PLL
100 5% VDDC_AUD_PLL N4
402 CH M6 P4
1 VDDIO33S_25M_PLL VSSC_AUD_PLL
C4N16 N6 VSSIO33S_25M_PLL
.1UF VDD_DAC18S E7
10% 1 1 1
6.3V P5 VDDIO33S_AUD_PLL VAA_POR18S D6 C3C6 C4P13 C3N3
2 X5R R5 VSSIO33S_AUD_PLL 4.7UF 4.7UF 4.7UF
402 10% 10% 10%
VDDIO18S_100M_PLL5 N14 6.3V 6.3V 6.3V
VDDIO18S_100M_PLL4 N13 2 X5R 2 X5R 2 X5R
P11 805 805 805
VDDIO18S_100M_PLL3
VDDIO18S_100M_PLL2 M10
VSSIO18S_100M_PLL2 N12
V_3P3STBY VDDIO18S_100M_PLL1 N9
VDDIO18S_100M_PLL0 M9
VDDIO18S_PIX_PLL L13
VSSIO18S_PIX_PLL L12
1 1
C4N25 C4N8
4.7UF 4.7UF
10% 10%
6.3V 6.3V X802478-003
2 X5R 2 X5R
805 805
V_1P8STBY
V_3P3STBY
1 1 1 1 1 1 1 1 1 1
C4N31 C4N17 C4P5 C4N34 C4P6 C4N27 C4P11 C4P1 C4P9 C4N26
1 1 1 1 1 1 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
C4N18 C4N19 C4N20 C4N28 C4P8 C4N42 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
.1UF .1UF .1UF .1UF .1UF .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10% 10% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 402 402 402 402 402 402 402 402 402 402
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402
DRAWING
[PAGE_TITLE=HANA, POWER + DECOUPLING] Tue May 08 18:24:16 2007
CONFIDENTIAL
HANA, POWER + DECOUPLING
V_3P3STBY
U4C2 4 of 4 IC V_1P8STBY
HANA FB4P1
E13 VDD33S3 VDD18S21 L11 V_HANA_VDD18S 1 2
J4 VDD33S2 VDD18S20 K11 120 FB
J3 VDD33S1 VDD18S19 G11 0.5A 603
1 1 0.2DCR 1
C3 VDD33S0 VDD18S18 J10 C4P4 C4P3 C3P1
VDD18S17 H10 .1UF 4.7UF 4.7UF
V_3P3STBY 10% 10% 10%
F4 VSSIO_33S_AVSS8 VDD18S16 J9 6.3V 6.3V 6.3V
E4 VSSIO_33S_AVSS7 VDD18S15 H9 2 X5R 2 X5R 2 X5R
FB4N6 F3 M8 402 805 805
V_HANA_VDDIO_33S_AVCC
VSSIO_33S_AVSS6 VDD18S14
1 2 G4 VDDIO_33S_AVCC5 VDD18S13 L8
120 FB G3 VDDIO_33S_AVCC4 VDD18S12 K8
0.5A 603 C2 VDDIO_33S_AVCC3 VDD18S11 G8
0.2DCR 1 1 1 1
C4N3 C4N6 C4N9 C4N10 C4N14 C4N13 G1 VDDIO_33S_AVCC2 VDD18S10 F8
4.7UF 4.7UF .1UF .1UF .1UF .1UF C1 VDDIO_33S_AVCC1 VDD18S9 L7
10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V G2 VDDIO_33S_AVCC0 VDD18S8 K7
X5R 2 X5R X5R 2 X5R 2 X5R 2 X5R VDD18S7 G7
805 805 402 402 402 402 A1 F7
VSSIO_33S_AVSS5 VDD18S6
E1 VSSIO_33S_AVSS4 VDD18S5 J6
J1 VSSIO_33S_AVSS3 VDD18S4 H6
1 1 1 1 1 1 1
E2 VSSIO_33S_AVSS2 VDD18S3 J5 C4N32 C4N30 C4N41 C4N33 C4N22 C4P7 C4N21
V_3P3STBY E3 VSSIO_33S_AVSS1 VDD18S2 H5 .1UF .1UF .1UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10% 10%
J2 VSSIO_33S_AVSS0 VDD18S1 E5 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VDD18S0 D5 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
H3 402 402 402 402 402 402 402
VDDIO_33S_PVDD1
VSS35 J13
D3 VDDIO_33S_PVCC0 VSS34 H13
1
C4N5 C4N12 VSS33 G13
.1UF .1UF VSS32 F13
10% 10%
6.3V 6.3V H4 VSSIO_33S_PVSS1 VSS31 D13
2 X5R X5R D4 VSSIO_33S_PVSS0 VSS30 K12
402 402 M11
VSS29
VSS28 J11
VSS27 H11
VSS26 L10
V_3P3STBY VSS25 K10
VSS24 G10
FB4N7 VSS23 F10
1 2 V_HANA_VDDIO_33S_PVCC0 VSS22 E10
VSS21 L9
120 FB K9
0.2A 603 VSS20
0.5 DCR 1 VSS19 G9
C4N4 C4N7 C4N11 F9
4.7UF 4.7UF .1UF VSS18
10% 10% 10% VSS17 J8
6.3V 6.3V 6.3V H8
X5R 2 X5R X5R VSS16
805 805 402 VSS15 E8
VSS14 J7
VSS13 H7
VSS12 L6
VSS11 K6
VSS10 G6
VSS9 F6
VSS8 E6
VSS7 L5
VSS6 K5
VSS5 G5
VSS4 F5
VSS3 C5
VSS2 L4
VSS1 C4
VSS0 R1
X802478-003
DRAWING
[PAGE_TITLE=HANA, POWER + DECOUPLING] Tue May 08 18:24:16 2007
CONFIDENTIAL
POWER TRACE DECOUPLING

V_12P0 V_12P0 V_5P0STBY V_3P3STBY V_5P0DUAL 55 V_VREG_V1P8V5P0
IN
C7G2 C3N2 C7B1 C2F2 C1C8 C4F13

1 2 1 2 1 2 1 2 1 2 1 2
0.01UF 10% 0.01UF 10% .1UF 10% .1UF 10% .1UF 10% 0.01UF 10%
16V 16V 6.3V 6.3V 6.3V 16V
402 402 402 402 402 402
C4N40 C1N12 C6B1 C2G1 C5G1

1 2 1 2 1 2 1 2 C8G2 1 2
1 2
0.01UF 10% 0.01UF 10% .1UF 10% .1UF 10% 0.01UF 10%
16V 16V 6.3V 6.3V .1UF 10% 16V
X7R X7R X5R X5R 6.3V X7R
402 402 402 402 X5R 402
402
C9F2 C1C7 C4A1 C3G3

1 2 1 2 1 2 1 2 C1F1
1 2
0.01UF 10% 0.01UF 10% .1UF 10% .1UF 10%
16V 16V 6.3V 6.3V .1UF 10%
X7R X7R X5R X5R 6.3V
402 402 402 402 X5R
402
V_5P0
C9E2 C1D8 C5G3
1 2 1 2 1 2 C5G5
1 2
0.01UF 10% .1UF 10% .1UF 10%
16V 6.3V 6.3V .1UF 10%
X7R X5R X5R 6.3V
402 402 402 X5R
C5V1 402
1 2
V_1P8
C9C7 .1UF 10% C1B2 C1C12
1 2 6.3V 1 2 1 2
X5R
0.01UF 10% 402 .1UF 10% .1UF 10%
16V 6.3V 6.3V
X7R X5R X5R
402 402 402
C3U3 C9N1
1 2 1 2
C1C15 .1UF 10% C1C1 C1N13 .1UF 10%

1 2 6.3V 1 2 1 2 6.3V
X5R X5R
0.01UF 10% 402 .1UF 10% .1UF 10% 402
16V 6.3V 6.3V
X7R X5R X5R
402 402 402
C2T4
1 2 C5N2
1 2
C7N1 .1UF 10% C1D10 C1G1
1 2 6.3V 1 2 1 2 .1UF 10%
X5R 6.3V
402 X5R
0.01UF 10% .1UF 10% .1UF 10% 402
16V 6.3V 6.3V
X7R X5R X5R
402 402 402
C3N1
1 2
C6N1 C1B3 C1F2 .1UF 10%
1 2 1 2 1 2
6.3V
X5R
0.01UF 10% .1UF 10% .1UF 10% 402
16V 6.3V 6.3V
X7R X5R X5R
402 402 402
C7N2
1 2
C5N1 .1UF 10%

1 2 6.3V
X5R
0.01UF 10% 402
16V
X7R
402
C4N1
1 2
0.01UF 10%
16V
X7R
402
DRAWING
[PAGE_TITLE=POWER TRACE EMI CAPS] Tue May 08 18:24:16 2007
CONFIDENTIAL
ADB:ADD CONFIG TABLE SB, PCIEX + SMM GPIO + JTAG]

U2C1 1 of 6 IC
SB VERSION 106 C2C2
2 R2P9 1 SATA_CLK_DP
1 2 PEX_SB_GPU_L1_DP OUT 13 58
27 IN K1 SATA_CLK_DP
1K 5% 27 IN SATA_CLK_DN J1 SATA_CLK_DN .1UF 10%
V_3P3 402 CH 6.3V
SATA_CLK_REF H3 X5R
27 IN SATA_CLK_REF 402
SATA_CLK_SEL H4 SATA_CLK_SEL<UP>
C2C1
DB1N5
1 ECB_CLK_BYP A6
1 2 PEX_SB_GPU_L1_DN OUT 13 58
TP ECB_CLK_BYP<DN>
V_1P8 2 R2P5 1 ECB_CLK_SEL B6 ECB_CLK_SEL<DN> .1UF 10%
1K 5% DB2P15 6.3V
1 HBEDB_CLK_BYP U20 X5R
402 EMPTY TP HBEDB_CLK_BYP<DN> 402
2 R2P16 1 HBEDB_CLK_SEL V20 HBEDB_CLK_SEL<DN>
1K 5% DB2N8
402 EMPTY 1 XUSB_CLK_BYP B15 XUSB_CLK_BYP<DN> C2C4
2 R2P2 1 TP
XUSB_CLK_SEL C15
1 2 PEX_SB_GPU_L0_DP OUT 13 58
XUSB_CLK_SEL<DN>
1K 5% .1UF 10%
402 EMPTY 6.3V
27 IN PCIEX_CLK_DN L22 PEX_CLK_DP X5R
27 PCIEX_CLK_DP L21 PEX_CLK_DN 402
IN
13 PEX_GPU_SB_L1_DP P22 PEX_RX1_DP PEX_TX1_DP N20 PEX_SB_GPU_L1_DP_C C2C3
IN PEX_GPU_SB_L1_DN N22 M20
1 2 PEX_SB_GPU_L0_DN OUT 13 58
13 PEX_RX1_DN PEX_TX1_DN PEX_SB_GPU_L1_DN_C
IN
.1UF 10%
13 IN PEX_GPU_SB_L0_DP T21 PEX_RX0_DP PEX_TX0_DP R19 PEX_SB_GPU_L0_DP_C 6.3V
PEX_GPU_SB_L0_DN R21 P19 X5R
13 PEX_RX0_DN PEX_TX0_DN PEX_SB_GPU_L0_DN_C 402
IN
PEX_RBIAS1 K20 PEX_RBIAS1
PEX_RBIAS0 K19 PEX_RBIAS0
2 R2N8 1 KER_DBG_TXD 58
OUT
1 47 5%
1 58 IN KER_DBG_RXD D15 UART0_RXD<UP> UART0_TXD D14 KER_DBG_TXD_R 402 CH
R2P11 1
C2P25 1
.1UF 124 C2P18 R2P8
10% 1% .1UF 499 GPIO31 D10 SB_GPIO_RESERVED31 1
6.3V DB2P1
2 X5R CH 10% 1% GPIO30 D11 SB_GPIO_RESERVED30 1 DB2P2
402 6.3V D12 SB_GPIO_RESERVED29 1
402
2
2 X5R CH GPIO29 DB2P3
402 402 GPIO28 D13 SB_GPIO_RESERVED28 1
2 DB2P4
GPIO27 C8 SB_GPIO_RESERVED27 1 DB2P5
V_3P3 GPIO26 D9 SB_GPIO_RESERVED26 1 DB2P6
GPIO25 C9 SB_GPIO_RESERVED25 1
DB2P7
GPIO24 B9 SB_GPIO_RESERVED24 1 DB2N6
GPIO23 A9 SB_GPIO_RESERVED23 1 DB2N5
GPIO22 C10 SB_GPIO_RESERVED22 1
DB2N4
1 1 1 1 1 1 1 1 GPIO21 B10 SB_GPIO_RESERVED21 1 DB2N3
R1P6 R1P2 R1P3 R1P5 R1P1 R2N6 R2N4 R2N5 GPIO19 C11 SB_GPIO_RESERVED19 1 DB2N12
10K 10K 10K 10K 10K 10K 10K 10K GPIO18 B11 SB_GPIO_RESERVED18 1
5% 5% 5% 5% 5% 5% 5% 5% DB2N10
EMPTY EMPTY CH CH EMPTY EMPTY EMPTY EMPTY C12 SB_GPIO_RESERVED16 1
402 402 402 402 402 402 402 402 GPIO16 DB2N7 SB_GPIO<0..15>
B12 15 BI 33
2 2 2 2 2 2 2 2 GPIO15
GPIO14 A12 14
0 1 2 3 5 11 14 15
SB_GPIO<0..15> GPIO13 C13 SCART_RGB OUT 44
BI 33 B13 AUD_RST_N
GPIO12 OUT 41
1 1 1 1 1 1 1 1 GPIO11 A13 11
GPIO10 C14 ANA_VID_INT IN 28
R1C7 R1C4 R1C5 R1C6 R1C2 R2B10 R2B8 R2B9 GPIO9 B14 WSS_CNTL0 OUT 44 DB1P1
1K 1K 1K 1K 1K 1K 1K 1K GPIO8 A14 WSS_CNTL1 44
5% 5% 5% 5% 5% 5% 5% 5% E3 PCIEX_INT OUT 1
TP DB1P2
GPIO7 TP
CH CH EMPTY EMPTY CH CH CH CH F1 SB_GPIO_RESERVED6 1
402 402 402 402 402 402 402 402 GPIO6
2 2 2 2 2 2 2 2 GPIO5 F2 5
GPIO4 F3 ENET_RST_N OUT 39 40
GPIO3 G1 3
GPIO2 G2 2
GPIO1 G3 1
GPIO0 G4 0
SB_TCLK W20 TCK<DN> 1 FTP FT1N1

SB_TDO V22 TDO
SB_TDI V21 TDI<UP> SATA_CLK V_3P3 STITCH
SB_TMS W22 TMS<UP>
GPIO<1> = 0 ENABLE DEBUG OUTPUT SB_TRST W21 TRST<DN> V_3P3
1 DISABLE DEBUG OUTPUT
J2D1
GPIO<0,2,3> = 111 XENON 2X3HDR X02047-012
110 ZEPHYR A 1 2 2 2
101 ZEPHYR B 3 4 C1C2 C2B16
100 ZEPHYR C .1UF .1UF
5 6 10% 10%
011 FALCON 6.3V 6.3V
010 JASPER
1 X5R 1 X5R
HDR 402 402
DRAWING
[PAGE_TITLE=SB, PCIEX + SMM GPIO + JTAG] Tue May 08 18:24:16 2007
CONFIDENTIAL
SB, SMC
V_3P3STBY V_12P0
27 IN STBY_CLK
27 IN SMC_RST_N
2
R8N17
C2P51 4.7K
1UF 5%
48 TRAY_OPEN 2 R2N15 1 10% CH
OUT 16V
33 5% X7R 402
402 CH 603 1
VREG_GPU_PWRGD IN 53
58 44 EXT_PWR_ON_N 2 R2N21 1
IN U2C1 2 of 6 IC 1 R8N18 2
10K 5%
402 CH SB VERSION 106 SMC_DBG_TXD OUT 58 1.82K 1%
HDMI_DDC_DATA 402 CH
29 44 28 BI Y12 STBY_CLK
1
FT2N5 FTP
FT2P10 FTP
1 C17 SMC_RST_N*
58 BI SMC_CPU_CHKSTOP_DETECT SB_RST_N G20 N: TIED TO V_MEMPORT

34 IN SB_RST_N* V_5P0
FOR BETTER ROUTING
34 IN SB_MAIN_PWRGD G19 MAIN_PWR_OK
V_3P3STBY 1 R7V4 2
D16 SMC_UART1_RXD<UP> SMC_UART1_TXD B16 SMC_DBG_TXD_R 1 R2N9 2
10K 5%
47 5% 402 CH
58 IN SMC_DBG_EN C16 SMC_DBG<DN> 402 CH
1 1 VREG_CPU_PWRGD IN 51
R2P6 R2P4
2.2K 2.2K TRAY_OPEN_R A18 SMC_P4_GPIO7 SMC_P2_GPIO7 E22 PWRSW_N 49
5% 5% TRAY_STATUS VREG_3P3_EN OUT
48 B18 SMC_P4_GPIO6 SMC_P2_GPIO6 E21 56
CH CH IN C18 E20 ANA_V12P0_PWRGD OUT
EXT_PWR_ON_R SMC_P4_GPIO5 SMC_P2_GPIO5 27
FT2P24 FTP
1 402 402
AUD_CLAMP D18 E19
IN
1 2 2 41 OUT SMC_P4_GPIO4 SMC_P2_GPIO4
FT2P15 FTP A19 SMC_P4_GPIO3 SMC_P2_GPIO3 F22 ANA_RST_N OUT 27 2 R3P7 1 GPU_RST_DONE
B19 F21 VREG_GPU_EN_N IN 13
SMC_P4_GPIO2 SMC_P2_GPIO2 OUT 53
58 27 SMB_DATA C19 SMC_P4_GPIO1 SMC_P2_GPIO1 F20 PSU_V12P0_EN 49 1K 5%
BI SMB_CLK A20 F19 ANA_CLK_OE OUT 402 CH 2
27 58 BI SMC_P4_GPIO0 SMC_P2_GPIO0 OUT 27
R3P6
AV_MODE2_R B20 SMC_P3_GPIO7 SMC_P1_GPIO7 Y21 VREG_CPU_EN 51 10K
OUT 5%
AV_MODE2 2 R2M3 1 AV_MODE1_R B21 SMC_P3_GPIO6 SMC_P1_GPIO6 Y22
44 IN AV_MODE0_R C20 AA20 VREG_V5P0_EN CH
SMC_P3_GPIO5 SMC_P1_GPIO5 OUT 55 402
10K 5% C22 SMC_P3_GPIO4 SMC_P1_GPIO4 AA21 VREG_V5P0_SEL 47 1
402 CH C21 AB20 VREG_V1P8_EN OUT
SMC_P3_GPIO3 SMC_P1_GPIO3 OUT 55
D22 SMC_P3_GPIO2 SMC_P1_GPIO2 Y20 BINDSW_N IN 43
44 AV_MODE1 2 R2M5 1 D21 SMC_P3_GPIO1 SMC_P1_GPIO1 AA19 TILTSW_N 43
IN D20 AB19 EJECTSW_N IN
10K 5% SMC_P3_GPIO0 SMC_P1_GPIO0 IN 43
402 CH 1
SMC_P0_GPIO7 J20 GPU_RST_DONE_R FTP FT2P5
AV_MODE0 2 R2A2 1 H21 CPU_RST_N
44 IN SMC_P0_GPIO6 OUT 4
SMC_P0_GPIO5 H19 SB_MAIN_PWRGD_R 2 R2P15 1 SB_MAIN_PWRGD 34
10K 5% OUT
402 CH SMC_P0_GPIO4 H20 SB_RST_N OUT 34 1K 5%
SMC_P0_GPIO3 J19 402 CH
SMC_P0_GPIO2 J22 2
SMC_P0_GPIO1 J21 GPU_RST_N OUT 13 R2P10
29 44 28 OUT HDMI_DDC_CLK SMC_P0_GPIO0 H22 CPU_PWRGD OUT 4 60 10K
5%
43 IN IR_DATA A16 SMC_IR_IN SMC_PWM1 A17 SMC_PWM1 1 DB2B1 CH
SMC_PWM0 B17 SMC_PWM0 OUT 28 402
1
TP
DB2P8 1 EN_TEST1_N G22 ENTEST1_N*<UP>
13 BI GPU_TCLK_R TP 1 EN_TEST0_N G21 ENTEST0_N*<UP>
27 BI ANA_VRST_OK DB2P9
55 BI VREG_V5P0_VMEM_PWRGD
X02047-012 V_1P8STBY
FT3P3 FTP
1
FT2P25 FTP
1
FT1U2 FTP
1 1 1
1 R2P12 R2P13
DB1F1 10K 10K
34 BI DBG_LED0 5% 5%
V_5P0DUAL CH CH
V_5P0DUAL U1U1 IC 402 402
1 2 2 2
SN74LVC1G14
R2B16 R2B19 5 VCC D1F1 ARGON_DATA
2K 2K DBG_LED0 2 4 1 R1U3 2 2 1 BI 49
1% 1% 34 IN IN OUT DBG_LED0_LED_R DBG_LED0_LED
ARGON_CLK
3 1 BI 49
GND N/C 249 1% YELLOW
CH EMPTY 402 CH
V_3P3STBY 402 402 LED SM
2 1 X801189-001
N: DBG_LED0 PULLDOWN = SMC PRODUCTION MODE

DBG_LED0 PULLUP = SMC DEVELOPMENT MODE
DRAWING
[PAGE_TITLE=SB, SMC] Tue May 08 18:24:17 2007
CONFIDENTIAL
SB, FLASH + USB + SPI
U2C1 3 of 6 IC
SB VERSION 106
58 SPI_CLK U3 SPI_CLK SPI_MISO AB5 SPI_MISO_R
2 R1R1 1 SPI_MISO 58
IN SPI_MOSI Y5
OUT
58 IN SPI_MOSI 33 5%
58 IN SPI_SS_N AA5 SPI_SS_N*<UP> 402 CH
42 BI FLSH_DATA<7..0> Y2 W1 FLSH_CLE
7 FLSH_DATA7 FLSH_CLE 42
AA2
OUT
6 FLSH_DATA6
42 OUT FLSH_WP_N 5 Y3 FLSH_DATA5 FLSH_CE_N* V3 FLSH_CE_N OUT 42
4 AA3 FLSH_DATA4
V_3P3STBY 3 AB3 FLSH_DATA3 FLSH_RE_N* V2 FLSH_RE_N OUT 42
2 Y4 FLSH_DATA2
1 AA4 FLSH_DATA1 FLSH_WE_N* W3 FLSH_WE_N OUT 42
2 R1P7 1 0 AB4 FLSH_DATA0
2.2K 5% FLSH_ALE W2 FLSH_ALE OUT 42
402 CH Y1 FLSH_WP_N*<DN>
42 IN FLSH_READY V1 FLSH_READY
FT2P22 FTP
1 USBPORTA3_DP W18 USBA_D3_DP USBB_D4_DP Y10 ARGONPORT_DP BI 49
FT2P23 FTP
1 USBPORTA3_DN Y18 USBA_D3_DN USBB_D4_DN W10 ARGONPORT_DN BI 49
1 USBPORTA2_DP AA17 USBA_D2_DP USBB_D3_DP Y8 MEMPORT1_DP BI 46

FT2P20 FTP
FT2P21 FTP
1 USBPORTA2_DN AB17 USBA_D2_DN USBB_D3_DN W8 MEMPORT1_DN BI 46
46 BI GAMEPORT2_DP W16 USBA_D1_DP USBB_D2_DP AB7 EXPPORT_DP BI 45

46 BI GAMEPORT2_DN Y16 USBA_D1_DN USBB_D2_DN AA7 EXPPORT_DN BI 45
46 BI GAMEPORT1_DP AA15 USBA_D0_DP USBB_D1_DP AB9 MEMPORT2_DP BI 46

46 BI GAMEPORT1_DN AB15 USBA_D0_DN USBB_D1_DN AA9 MEMPORT2_DN BI 46
USBB_D0_DP AB11 MEMPORT3_DP BI 60

W12 USB_RBIAS USBB_D0_DN AA11 MEMPORT3_DN BI 60
X02047-012
SB_USB_RBIAS
1
1 R2P14
C2P40
.1UF 113
10% 1%
6.3V
2 EMPTY CH
402 402
2
DRAWING
[PAGE_TITLE=SB, FLASH + USB + SPI] Tue May 08 18:24:17 2007
CONFIDENTIAL
SB, ETHERNET + AUDIO + SATA
40 39 MII_TX_CLK R1B9 MII_TX_CLK_R

IN
33 5%
402 CH
MII_MDC_CLK_OUT_R
R1C3 MII_MDC_CLK_OUT OUT 39 40
U2C1 4 of 6 IC
R1B10 33 5%
40 39 IN MII_RX_CLK MII_RX_CLK_R SB VERSION 106 402 CH
33 5% B3 MII_TX_CLK MII_MDC_CLK_OUT E2
402 CH C3 MII_RX_CLK
MII_RXD3 D1 MII_TXD3 C5 MII_TXD3 OUT 39 40

40 39 IN MII_RXD3 A4 MII_TXD2
MII_RXD2 D2 MII_TXD2 OUT 39 40
40 39 IN MII_RXD2 B4 MII_TXD1
MII_RXD1 D3 MII_TXD1 OUT 39 40
40 39 IN MII_RXD1 C4 MII_TXD0
MII_RXD0 C1 MII_TXD0 OUT 39 40
40 39 IN MII_RXD0
MII_RXDV C2 MII_TXEN A3 MII_TXEN OUT 39 40

40 39 IN MII_RXDV
40 39 IN MII_RXER B2 MII_RXER
40 39 IN MII_COL B5 MII_COL
40 39 MII_CRS A5 MII_CRS
R2B11 I2S_MCLK 41
IN MII_MDIO OUT
40 39 E1 MII_MDIO 47 5%
BI
R2B14 402 CH I2S_BCLK 28 41
OUT
47 5%
27 IN AUD_CLK A8 AUD_CLK I2S_MCLK_OUT C7 I2S_MCLK_R 402 CH R2B13 I2S_SD
B8 I2S_BCLK_R OUT 28 41
I2S_BCLK_OUT
I2S_SD A7 I2S_SD_R 47 5%
B7 I2S_WS_R
R2B12 402 CH I2S_WS
I2S_WS OUT 28 41
SPDIF C6 SPDIF_R 47 5%
402 CH 1 R2B15 2 SB_SPDIF_OUT 28
OUT
47 5%
402 CH
48 IN HDD_RX_DP N4 SATA1_RX_DP SATA1_TX_DP R2 HDD_TX_DP OUT 48
48 IN HDD_RX_DN P4 SATA1_RX_DN SATA1_TX_DN P2 HDD_TX_DN OUT 48
1 R2N12 2
48 IN ODD_RX_DP L3 SATA0_RX_DP SATA0_TX_DP N1 ODD_TX_DP OUT 48 10K 5%
48 IN ODD_RX_DN M3 SATA0_RX_DN SATA0_TX_DN M1 ODD_TX_DN OUT 48 402 CH
SATA_RBIAS U2 1 R2N11 2
SATA_RBIAS
10K 5%
402 CH
1 1 R2N10 2
1 X02047-012
C1C9 R1C8 10K 5%
.1UF 374 402 CH
10% 1%
6.3V
2 X5R CH 1 R1B3 2
402 402
2 10K 5%
402 CH
DRAWING
[PAGE_TITLE=SB, ETHERNET + AUDIO + SATA] Tue May 08 18:24:17 2007
CONFIDENTIAL
SB, STANDBY POWER + DECOUPLING
U2C1 5 of 6 IC V_1P8STBY
SB VERSION 106
VDD18_AUX<9> J18
VDD18_AUX<8> H18
VDD18_AUX<7> G18
V_1P8STBY VDD18_AUX<6> J15
VDD18_AUX<5> H15
VDD18_AUX<4> R14
VDD18_AUX<3> H14 SB BALLS V18 AND V19 ARE IN THE
VDD18_AUX<2> R12 LOWER RIGHT HAND OF THE CHIP
VDD18_AUX<1> P12 THEY HAVE BEEN ISOLATED
VDD18_AUX<0> R9 FOR BETTER POWER ROUTING
VDD33_AUX<14> V19 V_CMPAVDD33_USB IN 37
FB2P4 VDD33_AUX<13> D19
1 2 V_AVDD_USB AB13 AVDD_USB VDD33_AUX<12> V18
120 FB V_AVSS_USB AA13 AVSS_USB VDD33_AUX<11> F18 V_3P3STBY
0.2A 603 VDD33_AUX<10> E18
0.5 DCR 1 1
C2R5 C2P47 C2P43 V_CMPAVDD18_USB Y13 CMPAVDD18_USB VDD33_AUX<9> E17
4.7UF 2.2UF .1UF V_CMPAVSS18_USB W13 CMPAVSS18_USB VDD33_AUX<8> D17
10% 10% 10%
6.3V 6.3V 6.3V VDD33_AUX<7> E16
X5R 2 X5R 2 X5R V_VDD18_USB V13 E15
805 603 402 VDD18_USB<9> VDD33_AUX<6>
ST2P3 V12 W5
1 2 VDD18_USB<8> VDD33_AUX<5>
V11 VDD18_USB<7> VDD33_AUX<4> V5
V10 VDD18_USB<6> VDD33_AUX<3> U5
SHORT
V9 VDD18_USB<5> VDD33_AUX<2> W4
V8 VDD18_USB<4> VDD33_AUX<1> V4
FB2P3 V7 VDD18_USB<3> VDD33_AUX<0> U4
1 2 Y6 VDD18_USB<2>
W6 VDD18_USB<1> VSS_USB<25> Y19
120 FB V6 W19
0.2A 603 VDD18_USB<0> VSS_USB<24>
0.5 DCR 1 1 VSS_USB<23> AB18
C2P46 C2P42 Y14 AA18
2.2UF .1UF CMPAVDD33_USB VSS_USB<22>
10% 10% V_CMPAVSS33_USB W14 CMPAVSS33_USB VSS_USB<21> Y17
6.3V 6.3V W17
2 X5R 2 X5R VSS_USB<20>
ST2P2 603 402 V_VDD33_USB V17 VDD33_USB<3> VSS_USB<19> AB16
1 2 V16 VDD33_USB<2> VSS_USB<18> AA16
V15 VDD33_USB<1> VSS_USB<17> Y15
SHORT V14 VDD33_USB<0> VSS_USB<16> W15
VSS_USB<15> AB14 V_1P8STBY
FB2R1 VSS_USB<14> AA14
1 2 VSS_USB<13> AB12
120 FB VSS_USB<12> AA12
0.5A 603 VSS_USB<11> Y11
1 0.2DCR 1 1 1 1
C2R3 C2P45 C2P41 C2P2 C2P3 VSS_USB<10> W11
1
4.7UF 10UF .1UF .1UF .1UF VSS_USB<9> AB10 C2P38 C2P37 C2P23 C2P24
10% 20% 10% 10% 10% .1UF .1UF .1UF .1UF
6.3V 6.3V 6.3V 6.3V 6.3V VSS_USB<8> AA10
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 10% 10% 10% 10%
VSS_USB<7> Y9 6.3V 6.3V 6.3V 6.3V
805 805 402 402 402
VSS_USB<6> W9 2 X5R X5R X5R X5R
AB8 402 402 402 402
VSS_USB<5>
VSS_USB<4> AA8
VSS_USB<3> Y7
VSS_USB<2> W7
VSS_USB<1> AB6
VSS_USB<0> AA6
V_3P3STBY X02047-012
37 V_CMPAVDD33_USB V_3P3STBY
FB2P5 OUT
1 2
120 FB
0.2A 603
0.5 DCR 1 1 1
C2R6 C2P48 C2P44 C2P6 C2N1 C2P5
4.7UF 2.2UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 X5R 2 X5R 2 X5R X5R X5R
805 ST2P4 603 402 402 402 402
1 2
SHORT
FB2P1
1 2
120 FB
0.2A 603
0.5 DCR 1 1
C2P8 C2P34 C2P35
4.7UF 2.2UF .1UF
10% 10% 10%
6.3V 6.3V 6.3V
X5R 2 X5R 2 X5R
805 603 402
DRAWING
[PAGE_TITLE=SB, STANDBY POWER + DECOUPLING] Tue May 08 18:24:17 2007
CONFIDENTIAL
V_SBPCIE V_1P8
V_1P8
1 R2C1 2 U2C1 6 of 6 IC
0 5% SB VERSION 106
603 CH U19 V_1P8
VDD18<17>
STUFF THIS WHEN NOT USING V_SBPCIE REGULATOR VDD18<16> U18
VDD18<15> R15
VDD18<14> P15
VDD18<13> M15
V_SBPCIE VDD18<12> M14 1 1 1 1 1 1 1 1 1
J12
C2P22 C2P21 C2P16 C2P28 C2P30 C2P17 C2P15 C2P33 C2P29
VDD18<11> .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
FB2P2 VDD18<10> H12 10% 10% 10% 10% 10% 10% 10% 10% 10%
1 2 L19 R11 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
V_AVDD_PEX AVDD_PEX VDD18<9> 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
120 FB V_AVSS_PEX L20 AVSS_PEX VDD18<8> J11 402 402 402 402 402 402 402 402 402
0.2A 603 VDD18<7> H11
1 0.5 DCR 1 1
C3P3 C2P27 C2P26 V_VDD_PEX_FB T18 VDD_PEX<4> VDD18<6> M9
4.7UF 2.2UF 0.01UF R18 VDD_PEX<3> VDD18<5> H9
10% 10% 10%
6.3V 6.3V 16V P18 VDD_PEX<2> VDD18<4> R8
2 X5R 2 X5R 2 X7R N18 VDD_PEX<1> VDD18<3> P8
805 ST2P1 603 402 M18 M8
1 2 VDD_PEX<0> VDD18<2> V_3P3
VDD18<1> J8
U22 VSS_PEX<15> VDD18<0> H8 V_1P8
SHORT
T22 VSS_PEX<14>
R22 VSS_PEX<13> VDD33<13> E14
R2P17 M22 VSS_PEX<12> VDD33<12> E13
0 5% K22 VSS_PEX<11> VDD33<11> E12
603 CH U21 VSS_PEX<10> VDD33<10> E11
1 1 1 1
C2P10 C2P32 C2P31 P21 VSS_PEX<9> VDD33<9> E10 C2P39 C2P20 C1D2
4.7UF .1UF 0.01UF N21 VSS_PEX<8> VDD33<8> E9 1UF 1UF 4.7UF
10% 10% 10% 10% 10% 10%
6.3V 6.3V 16V M21 VSS_PEX<7> VDD33<7> D8 16V 16V 6.3V
2 X5R 2 X5R 2 X7R K21 VSS_PEX<6> VDD33<6> D7 X7R X7R 2 X5R
805 402 402 T20 D6 603 603 805
VSS_PEX<5> VDD33<5>
R20 VSS_PEX<4> VDD33<4> G5
P20 VSS_PEX<3> VDD33<3> D5
T19 VSS_PEX<2> VDD33<2> F4
V_1P8 N19 VSS_PEX<1> VDD33<1> E4
M19 VSS_PEX<0> VDD33<0> D4
FB1P2
1 2 V_AVDD1_SATA J3 AVDD1_SATA VSS<41> N15
120 FB V_AVSS1_SATA J2 AVSS1_SATA VSS<40> L15
0.2A 603 VSS<39> K15 V_3P3
1 1 0.5 DCR 1 1
C1P2 C1P7 C1P5 C1P6 V_AVDD0_SATA H1 AVDD0_SATA VSS<38> P14
4.7UF 4.7UF 2.2UF .1UF V_AVSS0_SATA H2 AVSS0_SATA VSS<37> N14
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V VSS<36> L14
2 X5R 2 X5R 2 X5R 2 X5R V_CMPAVDD_SATA U1 CMPAVDD_SATA VSS<35> K14
805 805 ST1P2 603 402 T1 J14 1 1 1 1 1
V_CMPAVSS_SATA CMPAVSS_SATA VSS<34>
1 2 R13 C2P13 C2P12 C2P14 C2P11 C2P9
VSS<33> .1UF .1UF .1UF .1UF .1UF
V_VDD_SATA T5 VDD_SATA<5> VSS<32> P13 10% 10% 10% 10% 10%
SHORT 6.3V 6.3V 6.3V 6.3V 6.3V
R5 VDD_SATA<4> VSS<31> N13 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
P5 VDD_SATA<3> VSS<30> M13 402 402 402 402 402
FB1P1 N5 VDD_SATA<2> VSS<29> L13
1 2 M5 VDD_SATA<1> VSS<28> K13
L5 VDD_SATA<0> VSS<27> J13
120 FB H13
0.2A 603 VSS<26>
0.5 DCR 1 1 T4 VSS_SATA<18> VSS<25> N12
C1P3 C1P4 R4 M12
2.2UF .1UF VSS_SATA<17> VSS<24>
10% 10% M4 VSS_SATA<16> VSS<23> L12
6.3V 6.3V L4 K12
2 X5R 2 X5R VSS_SATA<15> VSS<22>
ST1P1 603 402 K4 VSS_SATA<14> VSS<21> P11
1 2 J4 VSS_SATA<13> VSS<20> N11 V_3P3
T3 VSS_SATA<12> VSS<19> M11
SHORT R3 VSS_SATA<11> VSS<18> L11
P3 VSS_SATA<10> VSS<17> K11
FB1P4 N3 VSS_SATA<9> VSS<16> R10
1 2 K3 VSS_SATA<8> VSS<15> P10
1
120 FB T2 VSS_SATA<7> VSS<14> N10 C2P4 C2P1
0.2A 603 N2 VSS_SATA<6> VSS<13> M10 1UF 4.7UF
0.5 DCR 1 1 10% 10%
C1P10 C1P11 M2 VSS_SATA<5> VSS<12> L10 16V 6.3V
2.2UF .1UF L2 VSS_SATA<4> VSS<11> K10 X7R 2 X5R
10% 10% 603 805
6.3V 6.3V K2 VSS_SATA<3> VSS<10> J10
2 X5R 2 X5R R1 VSS_SATA<2> VSS<9> H10
ST1P3 603 402 P1 P9
1 2 VSS_SATA<1> VSS<8>
L1 VSS_SATA<0> VSS<7> N9
VSS<6> L9
SHORT
VSS<5> K9
VSS<4> J9
FB1P3 VSS<3> N8
1 2 VSS<2> L8
VSS<1> K8
120 FB A15
0.5A 603 VSS<0>
0.2DCR 1 1 1
C1P8 C2P52 C1P1
10UF .1UF .1UF
20% 10% 10%
6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R X02047-012
805 402 402
DRAWING
[PAGE_TITLE=SB, MAIN POWER + DECOUPLING] Tue May 08 18:24:17 2007
CONFIDENTIAL
N: 123.8 OHM TERMINATION REQUIRED FOR ICS

N: 100 OHM TERMINATION REQUIRED FOR BROADCOM
ENET_RX_DP BI 40 45
1
R1A4
39 IN V_ENET 61.9
1%
1 CH
402
R1B7 2
1K
5% ENET_RX_DP_R
CH 1
402
ENET_CLK 2 R1M1
27 IN ENET_POAC_R 0
OUT 45
U1B2 IC
STUFF FOR BROADCOM 5%
1 EMPTY FOR ICS CH
1
ICS1893BF 603
R1B6 R1B13 2
10K 332
47 REF_IN VDD<7> 48 5% 1% ENET_RX_DN_R
1 ENET_REF_CLK_OUT 46 REF_OUT VDD<6> 45 CH
DB1N4 EMPTY
VDD<5> 33 402
ENET_RST_N 23 14 2 402 1
RESET_N* VDD<4>
2
33 IN
VDD<3> 7 R1A3
36 40 MII_RX_CLK 34 RXCLK VDD<2> 24 61.9
2 OUT MII_RXDV 32 22
ENET_ACT_N OUT 40 45 1%
36 40 OUT RXDV VDD<1>
R1C1 MII_RXER 35 18 CH
36 40 OUT RXER VDD<0> 402
10K 2
5% MII_RXD3 28 12
36 40 OUT RXD<3> TP_AP
CH MII_RXD2 29 13 ENET_RX_DN
402 36 40 OUT RXD<2> TP_AN BI 40 45
1 36 40 OUT MII_RXD1 30 RXD<1>
36 40 OUT MII_RXD0 31 RXD<0> TP_BP 16 ENET_TX_DP BI 40 45
TP_BN 15
36 40 OUT MII_TX_CLK 37 TXCLK
36 IN MII_TXEN 38 TXEN P4RD 8
1
P3TD 6
36 IN MII_MDC_CLK_OUT MII_TXD3 42 4 R1A1
36 IN TXD<3> P2LI
36 MII_TXD2 41 TXD<2> P1CL 3 61.9
IN MII_TXD1 40 1 ENET_P2LI_R 1%
39 V_ENET 2 R1B11 1 36 IN TXD<1> P0AC OUT 45
CH
IN 36 IN MII_TXD0 39 TXD<0> 402
1.5K 1% 10/100 9 1 2
402 CH
ENET_P4RD
ENET_P3TD
ENET_P1CL
27 MDC
MII_MDIO 26 36
R1B4
40 36 BI MDIO VSS<6> 10K ENET_TX_DP_R
VSS<5> 25 5%
36 40 OUT MII_COL 43 COL VSS<4> 21 CH 1
36 40 OUT MII_CRS 44 CRS VSS<3> 17 1 402
VSS<2> 11 2 R1M2
10 5
R1N6 0
ENET_AMDIX_EN AMDIX_EN VSS<1> 10K
2
ENET_LINK_N OUT 40 45 5%
2 R1N4 1 VSS<0> 5%
CH
20 100TCSR 1 CH 1 1 603
100 5% 19 10TCSR 402 2
402 EMPTY R1N7 2 R1N5 R1B5
10K 10K 1K ENET_TX_DN_R
5% 5% 5%
39 V_ENET 2 R1N1 1 ENET_100BIAS X800188-002 CH CH CH 1
IN 402 402 402
9.53K 1% ENET_10BIAS
2 2 2 R1A2
402 CH 61.9
1 ENET_10_100_OUT
EMPTY FOR BROADCOM 1%
2 2 DB1N3 STUFF FOR ICS CH
R1N2 R1N3 AMDIX_EN HAS INTERNAL PULLUP 402
1.58K 2K AUTO MDIX IS ON BY DEFAULT 2
1% 1%
CH CH
402 402 10/100 PIN IS FOR OUTPUT
1 1 INDICATION OF CONNECTION SPEED ENET_TX_DN BI 40 45
ETHERNET ADDRESS="00001"
V_3P3
FB1B1
1 2 V_ENET 39 40 45
OUT
60 0.1DCR
0.5A 603
2
1 C1A5 C1B1 C1N1 C1N4 C1N5 C1N3 C1N9 C1N11 C1N2 C1N10
100UF 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
16V 1 X5R X5R X5R X5R X5R X5R X5R X5R X5R
2 ELEC 805 402 402 402 402 402 402 402 402
RDL
DRAWING
[PAGE_TITLE=SB OUT, ETHERNET] Tue May 08 18:24:17 2007
CONFIDENTIAL
BDCM PHY
V_1P8
FB1N1
2 1 ENET_AVDD OUT 40
60 EMPTY
0.5A 603
0.1DCR 1 1
C1N7 C1N14
1 10UF .1UF
C1N8 20% 10%
4.7UF 6.3V 6.3V
10% 2 EMPTY 2 EMPTY
6.3V 805 402
2 EMPTY
805
ENET_CLK U1B1 EMPTY

27 IN
BCM5241
1 XTALI2
DB1N1
1 ENET_REF_CLK2_OUT 2 XTALO2
39 IN V_ENET ENET_RST_N 10
33 IN RESET_N
1 36 39 OUT MII_RX_CLK 20 RXC

R1B12 36 39 OUT MII_RXDV 19 RX_DV/TEST0
4.7K 36 39 OUT MII_RXER 21 RX_ER/TEST1 OVDD2 22 V_ENET IN 39
5% OVDD1 9
EMPTY 36 39 OUT MII_RXD3 15 RXD3/ISOLATE
402 36 39 OUT MII_RXD2 16 RXD2/F100 AVDD 7 ENET_AVDD IN 40
2 36 39 MII_RXD1 17 RXD1/ANEN
MII_RXD0
OUT 18 12 ENET_LINK_N
36 39 OUT RXD0/PHYAD0 LINK# OUT 39 45
ACT# 11 ENET_ACT_N OUT 39 45
36 39 OUT MII_TX_CLK 23 TXC
36 IN MII_TXEN 24 TX_EN TDP 3 ENET_RX_DP OUT 39 45
TDN 4 ENET_RX_DN OUT 39 45
36 IN MII_TXD3 28 TXD3
36 IN MII_TXD2 27 TXD2 RDP 6 ENET_TX_DP OUT 39 45
36 IN MII_TXD1 26 TXD1 RDN 5 ENET_TX_DN OUT 39 45
36 IN MII_TXD0 25 TXD0
RDAC 8
36 IN MII_MDC_CLK_OUT 14 MDC_CLK_OUT
ENET_RDAC
39 36 BI MII_MDIO 13 MDIO GND 33
36 39 OUT MII_COL 29 COL/ENERGYDET

36 39 OUT MII_CRS 30 CRS/LOWPWR0
31 REGVDDIN 1
40 IN ENET_AVDD 32 REGVDDOUT R1N8
1.27K
1 1%
C1N6
.1UF X801554-002 LCC32 EMPTY
10% 402
2 6.3V 2
EMPTY
402
DRAWING PROJECT NAME PAGE REV

MICROSOFT
[PAGE_TITLE=XDK, DEBUG LEDS, BDCM PHY] FALCON_FABD
Tue May 08 18:24:20 2007 CONFIDENTIAL
V_12P0
FB2B2
2 R2B3 1 AUD_CLAMP_R 1 2
1 C2B10
FTP FT2M1 10UF 1K 5% 1K 0.7DCR
V_3P3 1 2 AUD_AC_R 402 CH 0.2A 603
1 R2B1 2 20% 16V

AUD_VAA TANT
0 5% 1206
1 FTP FT2N1 603 CH
2 2
C2A7 C2B7
1 R2B6 2 AUD_VDD 4.7UF 0.1UF R2B5
10% 10% 10K
0 5% 16V 25V
603 CH X5R 1 X7R 5%
1 1206 603 CH
C2B11 C2B5 402
2
4.7UF .1UF PGB0010603 1 C2B3
1
10% 10% 603 470PF
6.3V 6.3V 5%
2 X5R X5R EG2B2
50V
805 402 X801161-001 1 X7R
U2B1 IC EMPTY 402
XDAC
2
14 DVDD
36 IN I2S_MCLK 13 MCLK AVDD 9 AUD_R_OUT OUT 44

36 IN I2S_BCLK 4 BCLK
36 IN I2S_SD 3 SD VOUTR 6 AUD_VOUTR
FT2N2 FTP
1 36 IN I2S_WS 2 WS VOUTL 10 AUD_VOUTL AUD_L_OUT OUT 44
5 NC AVREF 8 AUD_ACAP
33 IN AUD_RST_N 12 PDN
AUD_DCAP 11 DVREF AGND 7
1 C2B4 C2B8 PGB0010603
.1UF 10UF
1
1 DGND 603
R2N3 C2B1 C2B6 10% 20%
2
10UF .1UF 6.3V 6.3V EG2B1
1K 20% 10% X5R X5R X801161-001
5% 6.3V 6.3V 402 805 R2B4
X5R X5R X02238-003 EMPTY 10K
CH 805 402 5%
402
2 CH 2
C2B2
2
402 470PF
1 5%
50V
1 X7R
402
C2B9
10UF
1 2 AUD_AC_L
FB2B1
20% 16V 2 R2B2 1 1 2
TANT AUD_CLAMP_L
1206 1K 5% 1K 0.7DCR
402 CH 0.2A 603
FT2P1 FTP
1
CR2M2
MBT3904 3 6
34 AUD_CLAMP 2 3 AUD_CLAMP_C 2 R2N2 1 AUD_CLAMP_B2

5 2 AUD_CLAMP_B3 2 R2N1 1
IN
Q2N1 1K 5% 1K 5%
MMBT3906 402 CH 402 CH
XSTR 4 1 XSTR
1
V_3P3STBY
1 R2N23 2 AUD_CLAMP_B1
4.7K 5%
402 CH 1
R2N22
1K
5%
CH
402
2
DRAWING
[PAGE_TITLE=SB OUT, AUDIO] Tue May 08 18:24:17 2007
CONFIDENTIAL
FLSH_DATA0 N: RETAIL=16MB
N: XDK=64MB
0 1
FLSH_DATA1
0 8MB 16MB
1 32MB 64MB
V_3P3STBY
N: STUFFED AT CONFIG LEVEL

1 1 1
1 1 1 N: UPDATE TO RECENT PART NO#
R2D7 R2D6 R1E2 C2E6 C2E5 C2R11
10K 10K 10K 4.7UF .1UF .1UF
FT1R3 FTP
1 5% 5% 5% 10% 10% 10%
1 6.3V 6.3V 6.3V
FT1R4 FTP CH CH CH 2 X5R 2 X5R 2 X5R
FT1R5 FTP
1 402 402 402 805 402 402 U2E1 IC
1 2 2 2
FT2R3 FTP NAND FLASH
FT2R4 FTP
1 7 FLSH_READY
1 RDY OUT 35
FT2R5 FTP
FT2R6 FTP
1 38 2 R2D2 1
NC<27> FLSH_NC38
FT2R7 FTP
1 37 48
VCC1 NC<26> 0 5%
1 FTP FT1T1
12 VCC0 NC<25> 47 402 EMPTY
NC<24> 46
35 IN FLSH_DATA<7..0> 44 45
7 DATA<7> NC<23>
6 43 DATA<6> NC<22> 40
5 42 DATA<5> NC<21> 39
4 41 DATA<4> NC<20> 35
3 32 DATA<3> NC<19> 34
2 31 DATA<2> NC<18> 33
1 30 DATA<1> NC<17> 28
0 29 DATA<0> NC<16> 27
NC<15> 26
35 IN FLSH_CE_N 9 CE_N* NC<14> 25
35 IN FLSH_RE_N 8 RE_N* NC<13> 24
1 1 1 1 1 1 1 1 35 IN FLSH_WE_N 18 WE_N* NC<12> 23
R2D8 R2D5 R2D4 R2D3 R2D1 R1D4 R1D3 R1D2 35 IN FLSH_WP_N 19 WP_N* NC<11> 22
10K 10K 10K 10K 10K 10K 10K 10K 35 IN FLSH_ALE 17 ALE NC<10> 21
5% 5% 5% 5% 5% 5% 5% 5% 35 IN FLSH_CLE 16 CLE NC<9> 20
EMPTY EMPTY CH CH CH CH CH CH NC<8> 15
402 402 402 402 402 402 402 402 6 VSS/NC NC<7> 14
2 2 2 2 2 2 2 2 36 VSS1 NC<6> 11
13 VSS0 NC<5> 10
NC<4> 5
NC<3> 4
NC<2> 3
NC<1> 2
NC<0> 1
X802184-001 TSOP
DRAWING
[PAGE_TITLE=SB OUT, FLASH] Tue May 08 18:24:17 2007
CONFIDENTIAL
V_3P3STBY
BINDING BUTTON
FAN CONTROL
1 V_12P0
R5V3
SWITCH 10K
TH 5%
2 R3M9 1
CH
SW5G1 402 5.11K 1%
THR
2 402 CH
2
4 1 BINDSW_N_R
2 R5V2 1 BINDSW_N 34 FAN1_Q1_C 1 Q3M1
3 2
OUT MJD210
10K 5% 3 XSTR
402 CH 3
X02246-002 28 FAN1_OUT 1 Q3M2 3
IN MMBT2222
XSTR D3A1
2 1N4148
V_3P3STBY SOT23
1 DIO
FAN1_Q1_E
2
C4P14
ODD EJECT BUTTON 1 2700PF
10%
R1G4 50V J3A2
SWITCH 1 X7R 1X3HDR
10K 402 2
TH 5% V_FAN1 1
CH R3M8 2
SW1G1 402 100 3
2 5% C3A9
THR 1UF
CH 10% CONN
2 R1G3 1 402 16V
FAN1_FDBK_R
4 1 EJECTSW_N_R EJECTSW_N OUT 34 48 1 1 X7R
3 2 10K 5% R3A7 603
402 CH 30.1K
X02246-002 1%
CH
402
2 R4P2 1 2
5.11K 1% FAN1_FDBK OUT 28

402 CH
1
V_3P3STBY
R3A2
11K
1%
1 CH
402
TILT SWITCH, ALPS R2G2 2
10K
EMPTY 5%
SW2G1 CH
SM 402
2
4 1
3 2 TILTSW_N_R
2 R2G3 1 TILTSW_N 34
OUT
10K 5%
X800550-003 402 CH
IR MODULE
V_3P3STBY
TILT SWITCH, SOLICO N: X800550-003 HOLDS ALL THREE TILT SWITCHES
TMEC ONLY HAS 3 PINS WHICH REQUIRES A DIFFERENT
SM UNIQUE PART NUMBER TO HOLD THE SYMBOL NAME 1 R2V1 2
SW2G2 N: BOM MUST CALL OUT X800550-003 WITH QTY 1 AND V_IR
SM LIST ALL THREE REF DES. FACTORY CHOOSES FROM THERE 49.9 1%
402 CH 2
4 1 1
3 2 C2V1 C2V2 R2N7
.1UF
4.7UF 10% 10K
10% 6.3V 5%
X800550-003 6.3V 2 X5R CH
U1G1 IC X5R 402
805 402
1
IR
VCC 3
DATA 1 IR_DATA OUT 34
GND 2
TILT SWITCH, TMEC ME2 5
ME1 4
EMPTY
SW2G3
TH X803473-002
1
3 2
X813350-001
DRAWING
[PAGE_TITLE=CONN, FAN + INFRARED + SWITCHES] Tue May 08 18:24:18 2007
CONFIDENTIAL
L3A3 OUT 29
1 2 V_5P0
28 IN VID_DACA_DP VID_DACA_OUT OUT 44 DAC STANDARD ADVANCED SDTV HDTV SCART VGA
.27UH IND RT2M1
DIO
BAV99
SOT363
1 0.45A 1210 1 2 V_AVIP
NA
6
R3A4 A N/A Y(LUMA) Y Y G G

1 1 1.1A THRMSTR
75 C3A6 C3A3 0.21DCR 1206 1
CR3A2
1% 62PF 75PF
5% 5% C2M5 C2A1
V_3P3 CH
50V 50V 28 HANA_SPDIF_OUT 4.7UF 470PF B N/A C(CHROMA) PR PR R R
402 2 NPO 2 NPO IN 10% 5%
2 402 402 2 6.3V 50V
X5R X7R
2
1 805 402
C2A6 C N/A N/A PB PB B B
SOT23S
BAV99
22PF
3
5%
DIO
50V
2 NPO D CVBS(COMP) CVBS(COMP) CVBS N/A CVBS CVBS
402
D2A1
L3A2
28 VID_DACB_DP 1 2 VID_DACB_OUT 44
IN OUT
.27UH IND
1
J3A1 CONN
DIO
BAV99
SOT363
1 0.45A 1210 V_3P3

NA XENON AVIP CONNECTOR
3
R3A3 1 1 29 V_AVIP
75 C3A5 C3A2 27 V_AVIP_RET
CR3A2
1% 62PF 75PF
V_3P3 CH 5% 5%
402 50V 50V 44 IN VID_DACA_OUT 4 VID_DACA_OUT
2
2 NPO 2 NPO 2 VID_DACA_RET
402 402
5
V_12P0 44 IN VID_DACB_OUT 3 VID_DACB_OUT

1 VID_DACB_RET
EXT_PWR_ON 30 EXT_PWR_ON_N OUT 58 34 44
44 IN VID_DACC_OUT 8 VID_DACC_OUT
6 VID_DACC_RET DDC_CLK 21 HDMI_DDC_CLK BI 28 34 29
L3A1 DDC_DATA 23 HDMI_DDC_DATA 28 34 29
VID_DACC_DP 1 2 VID_DACC_OUT VID_DACD_OUT 7 BI
1
28 IN OUT 44 44 IN VID_DACD_OUT
CH
1%
5 VID_DACD_RET AV_MODE2 28 AV_MODE2 OUT 34 44
.27UH IND
R2A8
BAV99
DIO
24 AV_MODE1
SOT363
0.45A 1210 AV_MODE1 OUT 34 44

1 NA 44 IN VID_HSYNC_OUT 11 VID_HSYNC_OUT AV_MODE0 20 AV_MODE0 OUT 34 44
6
9 VID_HSYNC_RET
1.82K
R3A6
402
75 1 1 GND<2> 26
C3A4 C3A1
CR3A1
2
1% 62PF 75PF 44 IN VID_VSYNC_OUT 12 VID_VSYNC_OUT GND<1> 22
V_3P3 CH 5% 5%
WSS_CNTL1 1 R2A6 2 10 VID_VSYNC_RET GND<0> 18
50V 50V 33 WSS_CNTL_B
402 2 NPO 2 NPO IN
2 5.36K 1% CR2A1 25 34
2
402 402
1
402 CH SPDIF SHIELD<3>

MBT3904 3 6 SHIELD<2> 33
41 IN AUD_R_OUT 15 AUD_R_OUT SHIELD<1> 32
5 2 13 AUD_R_RET SHIELD<0> 31
WSS_CNTL0 1 R2A7 2
33 IN AUD_L_OUT 16
41 IN AUD_L_OUT MTGB<8-1>
4.75K 1% XSTR 14 AUD_L_RET MTGA<8-1>
402 CH 4 1
WSS_CNTL_OUT_R 2 R2A5 1 WSS_CNTL_OUT 17 WSS_CNTL
WSS_CNTL_E
1K 5% 19 SCART_RGB
402 CH
R2A9 2
R2A4 2
CH
CH
1%
5%
2
C2A8 X806743-001 TH
75PF
L3A4 5%
50V
VID_DACD_DP 1 2 VID_DACD_OUT 1 NPO
10K
402
402
28 44
301
IN OUT 402
1
1
.27UH IND
DIO
BAV99
1
SOT363
0.45A 1210
R3A9 NA
3
SCART_RGB_OUT
75 C3A7 2
1% 62PF C3A8 V_3P3STBY
CR3A1
CH 5% 75PF
V_3P3 50V 5%
402 1 NPO 50V
2 402 1 NPO
402 1 1 1 1
5
R2A1 R2M6 R2M4 R2N20

V_3P3 10K 10K 10K 10K
5% 5% 5% 5%
CH CH CH CH
402 402 402 402
2 2 2 2
2 58 44 IN EXT_PWR_ON_N
1 R3M3 2 33 SCART_RGB 2 R2N19 1 SCART_RGB_R 1 Q2N3 44 AV_MODE2
28 IN VID_VSYNC_OUT_R VID_VSYNC_OUT OUT 44 IN MMBT3906 IN AV_MODE1
10K 5% XSTR 44 IN
49.9 1% 402 CH 3 44 AV_MODE0
402 CH IN
1 R2M9 2 1 1 1 1
3
SCART_RGB_OUT_R C2A3 C2M3 C2M2 C2N3

470PF 470PF 470PF 470PF
33 5% 5% 5% 5% 5%
V_3P3STBY
CR3M2
2 R2M10 1
VID_HSYNC_OUT_R 1 R3M2 2 VID_HSYNC_OUT 402 CH

2 50V
2 50V
2 50V
2 50V
5%
CH
28 44
BAV99
DIO
IN OUT 1 X7R X7R X7R X7R

SOT363
49.9 1% C2M4 402 402 402 402

402 CH 0.01UF
10%
5
16V
2
DIO
BAV99
X7R
10K
402
6
402
LAYOUT:PLACE CLOSE TO CONNECTOR
V_3P3STBY
CR3M2
EMI CAPS
2
DRAWING PROJECT NAME PAGE REV

MICROSOFT
[PAGE_TITLE=[CONN, AVIP] FALCON_FABD
Tue May 08 18:24:18 2007 CONFIDENTIAL
V_5P0DUAL
RT1B1
V_EXPPORT
2 1 V_EXPPORT OUT 45
45 IN
1.1A THRMSTR
0.21DCR 1206 1 C2A4 2 2 1
D1A2 C1A3 C1M2 FTP FT1N2
220UF 470PF 4.7UF
R1B2 2 20% 5% 10%
10V 50V 6.3V
2 ELEC 1 X7R 1 X5R
0 5% 3 RDL 402 805
603 CH
1
NA
SM BAV99
L1B1 EMPTY SOT23S
CMCHOKE DIO
35 BI EXPPORT_DN 1 2 EXPPORT_DN_CM
35 BI EXPPORT_DP 4 3 EXPPORT_DP_CM
D1A1
X801560-001
2 PGB0010603 PGB0010603
1
603 603
3 EG1A2 EG1A1
R1B1 1 EMPTY EMPTY
0 5%
603 CH BAV99
2
SOT23S J1A1 CONN
DIO
XENON RJ45/USB COMBO
12 VBUS
13 D-
IN ARGON_NTX 14 D+
D1B1 15 GND
2
V_EXPPORT 2
C1A4
45 IN 470PF 16
5% OMNI
3 50V
1 X7R 39 ENET_P2LI_R 1 LED_LEFT_A
402 IN
1 40 39 IN ENET_LINK_N 2 LED_LEFT_C
39 IN ENET_POAC_R 3 LED_RIGHT_A
BAV99 ENET_ACT_N 4
SOT23S 40 39 IN LED_RIGHT_C
DIO
40 39 IN ENET_TX_DP 11 XFMER2_P
V_ENET 1 R1M3 2 ENET_TX_CT 10
39 IN XFMER2_C
0 5% 40 39 IN ENET_TX_DN 7 XFMER2_N
402 EMPTY
40 39 IN ENET_RX_DP 9 XFMER1_P
1 R1A5 2 ENET_RX_CT 6 XFMER1_C
0 5% 40 39 IN ENET_RX_DN 5 XFMER1_N
402 EMPTY
8 CAP
C1M1 C1A2
.1UF .1UF 20 EMI4
10% 10%
6.3V 6.3V 19 EMI3
X5R X5R 18 EMI2
402 402 21 EMI1
17 ME1
X806148-001
DRAWING
[PAGE_TITLE=CONN, RJ45 + USB COMBO] Tue May 08 18:24:18 2007
CONFIDENTIAL
V_MEMPORT1 OUT 60
V_MPORT
V_5P0DUAL
RT2G1 FB5G1
RT8G1 2 1 2 1 V_MEMPORT2
2 1 V_GAMEPORT2 120 FB
1.1A THRMSTR 0.5A 603
1.1A THRMSTR 0.21DCR 1206 0.2DCR 1 C5G4 1 2
0.21DCR 1206 2 2 C4V6 C5G6
1 C9G2 220UF 470PF 4.7UF
C9G5 C9G1 20% 5% 10%
4.7UF 220UF 470PF 10V
10% 20% 5% 50V 6.3V
6.3V 10V 50V 2 ELEC 2 X7R 1 X5R
1 ELEC 1 RDL 402 805
X5R 2 X7R
805 RDL 402 PGB0010603
1
603 R4G5
EG9G2
0 5%
603 CH
EMPTY
V_5P0DUAL NA
SM
L4G1 EMPTY
2
D9G2
2 MEMPORT2_DN 1 CMCHOKE 2 MEMPORT2_DN_CM
35 BI
1 R9G2 2
0 5% 3
603 CH MEMPORT2_DP 4 3 MEMPORT2_DP_CM
1 35 BI
NA PGB0010603 PGB0010603
SM X801560-001
1
BAV99 603 603
L9G1 EMPTY SOT23S PGB0010603 EG4G2 EG4G1 J4G2 CONN
DIO
1
GAMEPORT2_DN 4 CMCHOKE 3 603
35 BI XENON MU
EG9G1 DIO DIO
1 GND
EMPTY
R4G4 2 VBUS
GAMEPORT2_DP 1 2 3
2
35 BI 0 5% D-
TH 603 CH 4 D+
5
2
X801560-001 D9G1 J9G1 CONN GND
2 XENON GAME 6 GND
CONN 7
3 VBUS
1 VBUS 8 D-
1 R9G1 2 1
GAMEPORT2_DN_CM 2 D- 2 2 9 D+
GAMEPORT2_DP_CM 3 D+ 1 C2G2 C3V5 C2G3 10 GND
0 5% 4 220UF 470PF 4.7UF
603 CH GND 20% 5% 10%
BAV99 10V 14
50V 6.3V EMI4
SOT23S
5 2 ELEC 1 X7R 1 X5R 13
DIO VBUS RDL 402 805 EMI3
GAMEPORT1_DN_CM 6 D- R3G4 12 EMI2
GAMEPORT1_DP_CM 7 D+ 11 EMI1
V_5P0DUAL 8 GND 0 5%
603 CH 15
RT8G2 NA ME4
9 EMI1 16 ME3
2 1 V_GAMEPORT1 10 EMI2
SM 17
L2G1 EMPTY
ME2
18 ME1
1.1A THRMSTR 11
0.21DCR 1206 2 ME1 MEMPORT1_DN 1 CMCHOKE 2 MEMPORT1_DN_CM
2 1 C9G3 C9G4 12 ME2
35 BI MTGA<8-1>
C9G6 220UF 470PF
4.7UF 20% 5% MTGB<8-1>
10% 10V 50V MTGC<8-1>
1 6.3V
2 ELEC 1 X7R X800245-003 35 MEMPORT1_DP 4 3 MEMPORT1_DP_CM
X5R RDL 402 BI
805
X800059-001 TH
X801560-001
PGB0010603 PGB0010603
1
603 603
V_5P0DUAL EG3G1 EG2G1
D9V2 R2G5 DIO DIO
2 PGB0010603 0 5%
R9V2 603 CH
1
603
2
0 5% 3 EG9V2
603 CH
1 EMPTY
NA
SM BAV99
L9V1 EMPTY V_5P0 V_MPORT
2
SOT23S
DIO U1F2 IC
GAMEPORT1_DN 4 CMCHOKE 3
35 BI PGB0010603
NCP1117
1
603 3 2 1
IN OUT FTP FT1V1
EG9V1
35 BI GAMEPORT1_DP 1 2 1 ADJUST/GND
EMPTY 1
D9V1 1 C1F6 1 C1F4
X801560-001 C1U2 0.1UF 100UF
2 1.0UF X800499-001 10% 20%
2
10% 25V 16V

2 16V 2 X7R 2 ELEC
3 X7R 603 RDL
805
1
R9V1
0 5% BAV99
603 CH SOT23S
DIO
DRAWING
[PAGE_TITLE=CONN, MEMORY PORTS + GAME PORTS] Tue May 08 18:24:18 2007
CONFIDENTIAL
XDK BOARD MAPPING
DEBUG BOARD MAPPING
CPU_DBGSEL_XDK<0..69> 1 FTP FT6U11 CPU_DBGSEL_DEBUG<0..69> CPU_DBG_TERM<0..69>

59 IN 1 IN 0 0 OUT
FTP FT6U9
1 FTP FT6U10
1 1
N:CONNECT TO CPU N:CONNECT TO CPU 2 2
DEBUG OUT DEBUG OUT 3 3
4 4
5 5
6 6
52 DBG_CPU_LINKTRAINED 1
DB6E1 7 7
53 DBG_CPU_SECURE_SYS 1
DB6E2
DBG_CPU_PLL_LOCK 8 8
54 1
DB6E3 9 9
55 DBG_CPU_TST_CLK 1
DB6E4 10 10
11 11
12 12
13 13
56 DBG_CPU_POST_OUT0 1 14 14
FTP FT6U8
57 DBG_CPU_POST_OUT1 1 FTP FT6U2
15 15
16 16
FTP FT6U4
18 18
19 19
FTP FT6U7
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
V_5P0STBY 32 32
33 33
V_5P0STBY V_12P0 34 34
35 35
36 36
1 C1D11 37 37
1 1 220UF
20% 38 38
R1R2 R1R3 10V 39 39
10K 10K ELEC
5% 5% 2 RDL 40 40
U1R1 IC 41 41
CH CH 42 42
402 402 SI4501DY V_5P0DUAL
2 2 43 43
3 S2
2 R1R5 1 VREG_V5P0_SEL_PGATE 4 44 44
G2 45 45
10K 5% VREG_V5P0_SEL_NGATE
D<3> 5 1 46 46
402 CH FTP FT1R2
VREG_V5P0_SEL_C
2 V_5P0 D<2> 8 47 47
CR1D1 C1R3 D<1> 7 1 1 1 48 48
MBT3904 .22UF D<0> 6 49 49
10% R1G2 R1G1 R1V2
6.3V 1K 20 20 50 50
1 X5R 2 G1
34 VREG_V5P0_SEL 1 R1D6 2 VREG_V5P0_SEL_B1 VREG_V5P0_SEL_B2 402 1 S1
5% 1% 1% 51 51
IN CH CH CH 52 52
4.7K 5% 402 1206 1206 53 53
FT1R1 FTP
1 402 CH 2 2 2 2
XSTR X801132-002 54 54
R1D5 55 55
4.7K 56 56
5%
BLEEDER_C1
BLEEDER_C2
57 57
CH 58 58
402
1 59 59
60 60
61 61
3 62 62
1 Q1G2 63 63
MMBT2222
VREG_5P0_SEL XSTR 64 64
VREG_5P0_SEL NGATE/PGATE V_5P0DUAL 3 2 65 65
27 SMC_RST_N 2 R1V1 1 BLEEDER_B 1 Q1V1 66 66
IN MMBT2222 67 67
HIGH LOW V_5P0STBY 10K 5% XSTR 68 68
402 CH 2 69 69
LOW HIGH V_5P0
DRAWING
[PAGE_TITLE=[MISC, V_5P0 DUAL, DEBUG MAPPING] Tue May 08 18:24:20 2007
CONFIDENTIAL
V_5P0
D1E4
2
3
C1E4
36 IN HDD_TX_DP 1 2
1
0.01UF 10%
16V BAV99
X7R
402 SOT23S
DIO
HDD_TX_DP_C HDD SATA AND POWER
HDD_TX_DN_C
D1E3
C1E3 J1E1 CONN
36 IN HDD_TX_DN 1 2 2
XENON HDD
0.01UF 10% 3 1 CONN
16V GND
X7R 2 D+
402 1 3 D-
4 GND
BAV99 5 D-
SOT23S 6 D+
DIO 7 GND
V_5P0 8 GND
9 GND
D1E2 10 GND
2 PGB0010603 PGB0010603 PGB0010603 PGB0010603 11 V_HDD
12
1
603 603 603 603 V_HDD
EG1E4 EG1E3 EG1E2 EG1E1 13 V_HDD
3
C1E2 14 V_XPOD
36 OUT HDD_RX_DN 1 2
1 EMPTY EMPTY EMPTY EMPTY
15 EMI1
0.01UF 10% 16
16V EMI2
BAV99
2
X7R
402 SOT23S
DIO 17 ME1
HDD_RX_DN_C 18 ME2
HDD_RX_DP_C
MTGA<8-1>
V_5P0 MTGB<8-1>
D1E1 RT1U1
C1E1
36 OUT HDD_RX_DP 1 2 2 2 1 V_HDD X800351-002 TH
0.01UF 10% 3 1.5A THRMSTR
16V 0.11DCR 1812 1 C1E5 C1T5 C1T4 C1T3
X7R 100UF 1UF 1UF 470PF
402 1 20% 10% 10% 5%
16V 16V 16V 50V
2 ELEC X7R X7R X7R
BAV99 RDL 603 603 402
SOT23S
DIO
V_5P0DUAL
RT1R1
ODD SATA 2 1 V_XPOD
V_3P3 V_3P3
ODD_TX_DP 1
C1C6
2 ODD_TX_DP_C
ODD POWER DECOUPLING 1.1A
0.21DCR
THRMSTR
1206 C1T1 C1T2
36 IN 1UF 470PF
0.01UF 10%
10%
16V
5%
50V
ODD POWER AND CONTROL
16V V_12P0 V_3P3 X7R X7R
X7R 603 402
402 CR1D2
CR1D3
2
C1C5 J1C1 2
36 IN ODD_TX_DN 1 2 ODD_TX_DN_C SATA 1 C1C10 1 C1C11
C1C14 C1C13 C1D6 C1R1 3
3
9 100UF 1UF 0.1UF 100UF 1UF .1UF
0.01UF 10% 20% 10% 10% 20% 10% 10%
16V 16V 16V 25V 16V 16V 6.3V 1
X7R 1 ELEC X7R X7R ELEC X7R X5R 1
402 2 2 RDL 603 603 2 RDL 603 402
BAV99
3
TRAY_STATUS 1 R1R4 2 TRAY_STATUS_R SOT23S BAV99
4 34 OUT SOT23S
C1C4 EMPTY
36 ODD_RX_DN 1 2 ODD_RX_DN_C 5 100 5% EMPTY
OUT 6 402 CH
0.01UF 10% V_5P0 V_3P3
16V 7 J1D1
X7R 8 V_5P0 1 EJECTSW_N
402 IN 43
4 3 TRAY_OPEN IN 34
C1C3 CONN 1 C1D9 V_12P0 6 5
ODD_RX_DP 1 2 C1D4 C1D1 C1D3 8 7
36 OUT ODD_RX_DP_C 100UF 1UF 1UF .1UF
20% 10% 10% 10% 10 9 1
0.01UF 10% 16V 16V 16V 6.3V 12 11 C1R4
16V 2 ELEC X7R X7R X5R 75PF
X7R RDL 603 603 402 5%
402 50V
CONN 2 NPO
402
DRAWING
[PAGE_TITLE=CONN, ODD + HDD] Tue May 08 18:24:20 2007
CONFIDENTIAL
V_3P3STBY V_12P0 1
DB8M1
1
1 FTP FT9N1 1
DB8M2
DB8M3
1 C6G5 2
C6G2
100UF 470PF 1 1 1 1
20% 5% 1 C9B1 C9A1 C9A5 C9A6 C9A2
16V 50V 1500UF 0.1UF 0.1UF 0.1UF 0.1UF
2 ELEC 1 X7R 20% 10% 10% 10% 10%
RDL 402 16V J9A1 CONN
25V 25V 25V 25V
2 ALUM 2 X7R 2 X7R 2 X7R 2 X7R XENON PWR
RDL 603 603 603 603
1 GND
2 GND
3 GND
4 V12P0
5 V12P0
6 V12P0
1 R6G7 2 34 PSU_V12P0_EN 2 R8A2 1 PSU_V12P0_EN_R 7 PSU_EN
IN
0 5% 1 100 5%
603 CH 402 CH 1 1 8 VSB5P0
R8A1 C8A1 C8A2
NA .1UF 470PF
SM 10K 10% 5% 9 EMI1
5% 6.3V 50V 10
L6G1 EMPTY CH
2 X5R 2 EMPTY EMI2
402 402 402 13 EMI3
ARGONPORT_DN 4 CMCHOKE 3 2 14 EMI4
35 BI
11 ME1
TH 12 ME2
ARGONPORT_DP 1 2 J6G1 CONN
35 BI
MTGA<8-1>
XENON RF
X801560-001 1 1 1 MTGB<8-1>
C6G3 C6G4 1 CONN V_5P0STBY DB8N1
VCC
470PF 470PF ARGON_DN_CM 2 D- 1
5% 5% FTP FT8N1 X811487-001 TH
50V 50V ARGON_DP_CM 3 D+
2 EMPTY 2 EMPTY 4 GND
1 R6G8 2 402 402
0 5% 5 SPARE 1 C5B7 1 C8B1 1
6
C9A4
603 CH C_DATA 100UF 100UF 470PF
7 C_CLK 20% 20% 5%
16V 16V 50V
8 GND ELEC ELEC 2 X7R
USE LC NETWORK FOR USB 1.1 9 NTX
2 RDL 2 RDL 402
V_3P3STBY
USE USB CHOKE FOR USB 2.0
10 EMI1
11 EMI2
1
R3N7 12 ME1
10K 13 ME2
5% 34 BI ARGON_DATA
CH 34 BI ARGON_CLK V_5P0STBY V_12P0
402
2 X800095-001
2 2
PWRSW_N 2 R3N6 1 PWRSW_N_R
C6V11 C6V10 1 1
34 IN 470PF 470PF
10K 5% 5% 5% V_12P0
2 50V 50V R8B5 R7B2
402 CH
C6V15 1 X7R 1 X7R 2.2K 2.2K
470PF 402 402 5% 5%
5% CH CH
50V 402 402
1 X7R 2 2 3
402
R6G37 2 2 R8N1 1 1 Q8N1
1 BLEEDER_V12P0_B2
BCP51
549 1% XSTR
0 5%
BLEEDER_V12P0_C1
BLEEDER_V12P0_C2
402 CH 2 4
603 EMPTY
NA BLEEDER_V12P0_LOAD
SM
L6G2 EMPTY 1 1 1 1
MEMPORT3_DP_ARGON 4 CMCHOKE 3 R7N3 R7N1 R7N4 R7N2
60 MEMPORT3_DP_ARGON_CM 10 10 10 10
BI
1% 1% 1% 1%
3
CH CH CH CH
1 Q8B4 805 805 805 805
60 BI MEMPORT3_DN_ARGON 1 2 MEMPORT3_DN_ARGON_CM MMBT2222 2 2 2 2
3 XSTR
2
X801560-001 2 R8A4 1 BLEEDER_V12P0_B1 1 Q8B5
MMBT2222
2.2K 5% XSTR
402 CH 2
1 R6G38 2
56 5% 27 ANA_V12P0_PWRGD 2 R8A3 1
603 EMPTY IN
2.2K 5%
402 CH
DRAWING
[PAGE_TITLE=CONN, ARGON + POWER SUPPLY] Tue May 08 18:24:18 2007
CONFIDENTIAL
4 CPU_VREG_APS5 R7E3 5
IN
0 5% V_GPUCORE
4 CPU_VREG_APS4 402 CH R7E1 4
IN
0 5%
4 CPU_VREG_APS3 R7E5 402 CH
3
IN N: WATERNOSE=011100=1.1625V
0 5% 1 1 1 1 1 1 N: DD1.0 REQUIRES VID0 RC
4 CPU_VREG_APS2 402 CH R7E4 2 N: DD2.0 NO STUFF RC
IN R7T6 R7T4 R7T8 R7T7 R7T5 R7T9
0 5% 10K 10K 10K 10K 10K 10K N: LOKI=100001=1.05V
4 CPU_VREG_APS1 R7E2 402 CH
1
5% 5% 5% 5% 5% 5%
IN CH EMPTY EMPTY EMPTY EMPTY CH
0 5% 402 402 402 402 402 402
CPU_VREG_APS0 402 CH R7E6 0 2 2 2 2 2 2
4 IN
1K 5%
402 CH 5 4 3 2 1 0
VREG_CPU_VID<5..0> OUT 51
1 1 1 1 1 1
R7T13 R7T11 R7T15 R7T14 R7T12 R7T16
10K 10K 10K 10K 10K 10K
5% 5% 5% 5% 5% 5%
EMPTY CH CH CH CH EMPTY
402 402 402 402 402 402
2 2 2 2 2 2
V_12P0 N:GPU INPUT FILTER
V_12P0 N:CPU INPUT FILTER L8B1

1 2 V_VREG_GPU 53 54
OUT
L9B1 1.6UH IND
1 2 V_VREG_CPU 51 52 10A TH
1 C6B3 1 C7B3 1 1 1 1 1
OUT 1 NA C8B4 C6B5 C6N2 C7B4 C7N3
1.6UH IND
C8B2 1500UF 1500UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF
4.7UF 20% 20% 10% 10% 10% 10% 10%
1 10A TH 1 1 10% 16V 16V 16V 16V 16V 16V 16V
C9B2 NA C9C4 C9C1 C9E3 C9D2 C9B4 C9C3 16V ALUM ALUM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
4.7UF 1500UF 1500UF 1500UF 1500UF 4.7UF 4.7UF 2 X5R 2 RDL 2 RDL 1206 1206 1206 1206 1206
10% 20% 20% 20% 20% 10% 10% 1206
16V 16V 16V 16V 16V 16V 16V
2 X5R ALUM ALUM ALUM ALUM 2 EMPTY 2 EMPTY
1206 RDL RDL RDL RDL 1206 1206
1 DB8P1
1 DB8P2 V_GPUCORE
V_CPUCORE
1 FTP FT7T9
1 FTP FT5R2
N:CPU OUTPUT FILTER N:GPU OUTPUT FILTER
1 C8C2 1 C8E3 1 C8E1 1 C8F1 1 C8E2 1 C8D1 1 C8C1 1 C8D4 1 C7C2 1 C7C1 1 C6C3 1 C7C3 1 C6C2 1 C6C1 1 C5C8 1 C5C9
820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2.5V 2.5V
2 EMPTY 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 EMPTY 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 EMPTY 2 EMPTY
RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL 8X8 8X8
1
FTP FT7U4
DRAWING
[PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] Tue May 08 18:24:18 2007
CONFIDENTIAL
3188 3190A
R8G1 STUFF EMPTY

R8V10 EMPTY STUFF
V_5P0 C8U4 EMPTY STUFF
50 IN V_VREG_CPU
1 R8G1 2 1
10 1% R8U5
603 CH 1K
1%
CH
402
50 V_VREG_CPU 2 R8V10 1 VREG_CPU_VCC 2
IN
10 1%
VREG_CPU_EN 805 EMPTY VREG_CPU_RAMPADJ_R
34 IN
C8V15 1 C8G5
1 1UF 100UF
10% 20% 1
1 R8F7 16V 16V
1
FT2P17 FTP ELEC
10K X7R 2 RDL
R8U3 C8U4
603 294K .1UF
5% 10% 1
1% FTP FT2P16
CH 6.3V
402 CH 2 X5R
2 402 402
2 VREG_CPU_PWRGD 34
OUT
U8U1 IC
52 VREG_CPU_PHASE3 R8V6 ADP3190A
IN 28
0 5% VCC
603 EMPTY PWRGD 10
VREG_CPU_RAMPADJ 14 RAMPADJ
VREG_CPU_PHASE2 R8V7 6
VREG_CPU_VID<5..0> IN 50
52 VID5 5
IN 11 1
0 5% EN VID4 4
603 CH VID3 2 3
DB8U4 1 VREG_CPU_SW4 20 SW4 VID2 3 2
52 VREG_CPU_PHASE1 R8V9 TP VREG_CPU_PHASE3_R 21 SW3 VID1 4 1 1 R8F8 2
IN
0 5% VREG_CPU_PHASE2_R 22 SW2 VID0 5 0
603 CH VREG_CPU_PHASE1_R 23 SW1 0 5%
24 402 CH
PWM4
RT8F1 VREG_CPU_CSCOMP 18 CSCOMP PWM3 25 VREG_CPU_PWM3 OUT 52
1 2 PWM2 26 VREG_CPU_PWM2 52
OUT
VREG_CPU_CSCOMP_R
17 CSSUM PWM1 27 VREG_CPU_PWM1 OUT 52

NA THRMSTR 1
100K 603 FT8U1 FTP
16 CSREF ILIMIT 15 VREG_CPU_DRV_EN OUT 52
TEMP SENSOR
8 FB DELAY 12 VREG_CPU_DELAY
2 2 2
R8V1 R8V2 R8V4 1 R8V3 2 9 COMP RT 13 VREG_CPU_RT 2 2
47.5K 47.5K 47.5K R8U4
1 R8U1 2
1% 1% 1% 35.7K 1% 7 19 C8U1 240K C8U2
603 CH FBRTN GND 2 .047UF 324K 1000PF
EMPTY CH CH 10% 1% 5% 10%
603 603 603 2 R8U2 16V 50V
1 1 1 1 1 X806818-001
2 X7R CH CH 1 EMPTY
R8V5 C8V1 C8U3 422K 603 603 402
76.8K 360PF 8200PF 1% 1 1 402
1% 10% 10% CH
50V 16V ST7T1
CH 2 2 402
603
NPO CH VREG_CPU_FBRTN 2 1 1
603 603
1
SHORT
VREG_CPU_CSSUM 2
C8U10
1000PF N: TARGET FSW=233KHZ
10%
V_CPUCORE 50V
1 X7R
LAYOUT:ATTACH TO 1 402
CLOSEST INDUCTOR FT8U2 FTP
ST8F1
1 2 VREG_CPU_CSREF 1 R8G3 2 VREG_CPU_CSREF_R
10 1%
SHORT 402 CH 2
C8G1
1000PF
10%
50V
1 X7R
VREG_V_CPUCORE_S
402
ST7T2
R8U13
1 2 C8U7
1 2 1 VREG_CPU_FB
2 5% 0
SHORT EMPTY 402 10% 0.1UF
2 C8U8
25V 22PF
EMPTY 5%
603 50V
1 NPO
402
1 R8U10 2 C8U6 1 R8U11 2
1 2 VREG_CPU_COMP_R VREG_CPU_COMP
1% 1.33K 330PF 5% 24.3K 1%
CH 603 50V 402 CH
X7R
402
DRAWING
[PAGE_TITLE=VREGS, CPU CONTROLLER] Tue May 08 18:24:18 2007
CONFIDENTIAL
50 IN V_VREG_CPU
D9C1 3
1N4148
C9P3 3
50 V_VREG_CPU 1 R9P2 2 VREG_CPU3_VCC 1 3
VREG_CPU_BST3 1 2
D
Q9D2 D Q9D1
IN 1 1
2.2 1% NTD60N02R C9D3 C9D1
805 EMPTY SOT23 0.01UF 10% DPAK NTD60N02R 4.7UF 4.7UF
EMPTY 50V DPAK 10% 10%
1 EMPTY 1 16V 16V
C9P4 805 1 2 X5R 2 EMPTY
1.0UF G S EMPTY 1206 1206
10% C9P2 G S
16V
1 R9P1 2 VREG_CPU_BST3_R 1 2 EMPTY 2 VREG_CPU_PHASE3 51
2 EMPTY
2 OUT
805 2.2 1% 0.015UF 5%
U9P1 EMPTY 805 EMPTY 16V V_CPUCORE
EMPTY
MOS DRIVER 805
4 VCC BST 1 L8D1
51 VREG_CPU_PWM3 2 IN DRVH 8 VREG_CPU_DRVH3 2 1
VREG_CPU_DRV_EN IN 3 7
51 IN OD_N* SW EMPTY 0.6UH
6 PGND DRVL 5 TH 30A
1
NA
VREG_CPU_BG3
3 3 R9C1
X801233-001 2.2
D Q9C1 D Q8C1 1%
EMPTY
NTD85N02R NTD85N02R 805
2
DPAK DPAK
1 1
G S EMPTY G S EMPTY VREG_CPU_SW3_R
2 2
1
C9C5
4700PF
10%
50V
D9E1 2 EMPTY
1N4148 603
1 R9T2 2 VREG_CPU_BST2 C9T2
VREG_CPU2_VCC 1 3 1 2 3 3
2.2 1% D Q9E1 D Q9D4 1 1
805 CH SOT23 0.01UF 10% C9D4 C9E1
DIO 50V 4.7UF 4.7UF
1 X7R NTD60N02R NTD60N02R
C9T3 805 10% 10%
1.0UF DPAK DPAK 16V 16V
10% 1 R9T1 2 C9T1 1 1 2 EMPTY 2 X5R
16V VREG_CPU_BST2_R 1 2 1206 1206
2 G S G S EMPTY VREG_CPU_PHASE2
X7R FET OUT 51
805 2.2 1% 0.015UF 5% 2 2
U9T1 IC 805 CH 16V
X7R
MOS DRIVER 805
4 VCC BST 1 L8E1
IN
3 OD_N* SW 7
IND 0.6UH
6 PGND DRVL 5 1 TH 30A
R9E1 NA
VREG_CPU_BG2
X801233-001 3 3 2.2
1%
D Q9E3 D Q9D3 EMPTY
805
DPAK DPAK
1 1
G S G S
FET FET VREG_CPU_SW2_R
2 2
1
C9E4
4700PF
10%
D9F1 50V
1N4148 2 EMPTY
1 R9U2 2 VREG_CPU_BST1 C9U2 603
VREG_CPU1_VCC 1 3 1 2
3 3
2.2 1% 0.01UF 10% D Q9F1 D Q9F4
805 CH 1 SOT23 50V
1 1
C9U3 DIO X7R
C9F4 C9F1
4.7UF 4.7UF
1.0UF 805 NTD60N02R NTD60N02R 10% 10%
10% 1 R9U1 2 C9U1 16V 16V
16V VREG_CPU_BST1_R 1 2 DPAK DPAK 2 2
2 1 1 X5R EMPTY
X7R 2.2 1% G S G S 1206 1206 VREG_CPU_PHASE1 OUT 51
805
805 CH 0.015UF 5% FET EMPTY
U9U1 IC 16V 2 2
X7R
MOS DRIVER 805
4 VCC BST 1 L8F1
IN 3 7
OD_N* SW IND 0.6UH
6 PGND DRVL 5 TH 30A
1
NA
VREG_CPU_BG1
3 3 R9F1
X801233-001 2.2
D Q9F2 D Q8F1 1%
EMPTY
2
DPAK DPAK
1 1 VREG_CPU_SW1_R
G S G S
FET FET
2 2
1
C9F3
4700PF
10%
50V
2 EMPTY
603
DRAWING
[PAGE_TITLE=VREGS, CPU OUTPUT PHASE 1,2,3] Tue May 08 18:24:18 2007
CONFIDENTIAL
GPU MEM VID VOLTAGE

50 IN V_VREG_GPU 50 IN V_VREG_GPU
<4.5 ANY VID 0=10000 1.150V
4.5-6.0 SEC VID-1=10001 1.125V
V_GPUCORE 1 OUT 62
4.5-6.0 IFX VID 0=10000 1.150V
YR1
ST5R2 R8N7 4.5-6.0 HYNIX VID 0=10000 1.150V VREG_GPU_VID4 1 R8B1 2
1 2 2.2 6.0-7.0 ANY VID-1=10001 1.125V D8B3
1% 7.0-8.0 ANY VID ?=01110 1.XXXV 0 5% VREG_GPU_PHASE1_C
62 402 EMPTY 1 1
SHORT
1 FT8P2 FTP
1 CH OUT
805 D8B2 C8B3
R8C9 1 2 YR2 B13 ANY VID 0=10000 1.150V VREG_GPU_VID3
1 R8B7 2 1N4148 3 2 1 VREG_GPU_PHASE1 54 53
0 FT8P1 FTP SOT23 OUT
5% YR3 GUNGA ANY VID 0=10000 1.150V 0 5% DIO
402 CH 3 2 0.1UF 10%
62 OUT OUT 62 25V
EMPTY BAV99 X7R
402 1 R8B8 2 603
2 VREG_GPU_VID2 SOT23S
1 1 0 5% DIO
C8N3 C8B9
RT7C1 1.0UF 1.0UF OUT 62 402 CH
2 1 2 R8P9 1 10% 10% U8N1 IC
VREG_GPU_VFB_R
2 16V
2 16V VREG_GPU_VID1 1 R8B9 2 VREG_GPU_NPNC
1.21K 1% X7R X7R NCP5331
NA THRMSTR 2 R8P4 1 805 805 16 0 5% 1 2
402 CH VCCL2
10K 603 25 15 OUT 62 402 CH R8N2 C9B3
5.11K 1% VCCL1 VID4 0.1UF
402 CH VID3 14 1 R8B10 2 62 10%
26 13
VREG_GPU_VID0 5% 25V
2 R8P7 1
VREG_GPU_VCCL VCCL VID2
CH
1 X7R
C8P2 VID1 12 0 5% 603
2 1 402 CH 805
1.1K 1% 53 IN VREG_GPU_5VREF 30 5VSB VID0 11 2
402 CH 1000PF 10%
50V VREG_GPU_VFFB 7 VFFB VCCH 20 VREG_GPU_VCCH
EMPTY
402
VREG_GPU_VFB 1 VFB ILIM 31 VREG_GPU_ILIM 1 1
C8N1 D8B1
C8P1 2 R8P3 1 0.1UF MMSZ18
1 2 VREG_GPU_COMP_R VREG_GPU_VDRP 2 VDRP 5VREF 8 VREG_GPU_5VREF OUT 53 10% SOD123
25V
6800PF 10% 4.02K 1% 2 X7R 2 DIO
50V 402 CH VREG_GPU_COMP 32 COMP CBOUT 21 603
X7R
603 VREG_GPU_SEN 10 NSEN PGD 29
VREG_GPU_COMP_C 1 R8P1 2 VREG_GPU_CS2 6 19

CS2 GH2
7.5K 1% VREG_GPU_CS1 4 CS1 GL2 17
2 603 CH
C9P1 C8N5 VREG_GPU_CSREF 5 22 1 R8B4 2
2 1 CSREF GH1
.047UF GL1 24
10% 7.5K 1%
16V 6800PF 10% VREG_GPU_ROSC 9 ROSC 603 CH
1 X7R 50V 3
2 3
603 X7R LGND 2 Q8B3
603 2 VREG_GPU_CPGD 28 CPGD C9C2 R8C1 FET
GND2 18 0.1UF 6.19K 1 2N7002
ST5R1 R8C7 10% 1% V_5P0STBY
1 2 35.7K 27 COVC GND1 23 25V 2 SOT23
1% 1 X7R CH
VREG_GPU_EN_N_R
603 402
SHORT CH 1 1
603 C8N4 X800631-001 1
1 0.01UF
10%
16V R5N1
2 R8P5 1
2 X7R 10K
54 IN VREG_GPU_PHASE2 402 5%
7.5K 1% CH
603 CH 402
V_GPUCORE 1 2
C8P3
0.1UF
10% 1 R9B1 2
25V 34 IN VREG_GPU_EN_N
2 X7R
603 1 10K 5%
FT2P6 FTP 402 CH
54 53 VREG_GPU_PHASE1 2 R8P6 1
IN
7.5K 1%
603 CH
V_GPUCORE 1 VREG_GPU_PWRGD OUT 34
C8P4
0.1UF 1
10% FTP FT2P3
25V
2 X7R
603 VREG_GPU_GH2_R
1 R8N5 2 VREG_GPU_GH2 OUT 54
0 1A
805 CH
VREG_GPU_GL2_R
1 R8N6 2 VREG_GPU_GL2 OUT 54
ST8C1 0 1A
1 2 VREG_GPU_CSREF_R 2 R8B2 1 805 CH
2K 1% VREG_GPU_GH1_R 1 R8N3 2 VREG_GPU_GH1 54
SHORT 402 CH 2
OUT
0 1A
2 R8B3 805 CH
C8B8 VREG_GPU_GL1_R 1 R8N4 2 VREG_GPU_GL1
0.1UF 750K OUT 54
10% C8B7 1% 0 1A
25V 1 2
1 X7R CH 805 CH
603 603
470PF 5% 1
50V
X7R
402
DRAWING
[PAGE_TITLE=VREGS, GPU CONTROLLER] Tue May 08 18:24:19 2007
CONFIDENTIAL
50 IN V_VREG_GPU
3 C6B2
D Q6B1 4.7UF
10%
16V
X5R
NTD60N02R 1206
1
DPAK V_GPUCORE
53 IN VREG_GPU_GH2
G S
FET VREG_GPU_PHASE2 OUT 53
2
L6C1
2 1
IND 0.6UH
1 TH 30A
3 3 NA
D Q6B2 D Q6C1 R6C2
2.2
1%
NTD85N02R NTD85N02R CH
DPAK DPAK 805
53 VREG_GPU_GL2 1 1 2
IN G S G S
FET FET
2 2
VREG_GPU_PH2_R
2
C5C6
3 C7B2 4700PF
4.7UF 10%
D Q7B1 10% 1 50V
16V X7R
X5R 603
NTD60N02R 1206
DPAK
53 VREG_GPU_GH1 1
IN G S
FET
2
L7C1
2 1
IND 0.6UH
1 TH 30A
3 3 NA
D Q7B2 D Q7C1 R7B6
2.2 VREG_GPU_PHASE1 OUT 53
1%
NTD85N02R NTD85N02R CH
DPAK DPAK 805
53 VREG_GPU_GL1 1 1 2
IN G S G S
FET FET
2 2
VREG_GPU_PH1_R
2
C8B6
4700PF
10%
50V
1 X7R
603
V_5P0
V_1P8
U2T1 IC
NCP1117
1 R2E7 2 V_V3P3TOV1P8 3 IN OUT 2 1 FTP FT2R8
10 5% V_1P8 V_MEM
1210 CH 1 ADJUST/GND
1 1 1 C2D6
C2T5 C2R4
1 R2E6 2 0.1UF X800500-001 0.1UF 100UF
1 R2T8 2
10% 10% 20%
10 5% 25V DPAK 25V 16V
1210 CH
2 X7R 2 X7R 2 ELEC 0 1A
603 1.8V 603 RDL 805 EMPTY
1 R1E3 2 R2T7
1 2
10 5%
1210 CH 0 1A
805 EMPTY
1 R1E1 2
10 5%
1210 CH
DRAWING
[PAGE_TITLE=VREGS, GPU OUTPUT PHASE 1,2] Tue May 08 18:24:19 2007
CONFIDENTIAL
V_12P0
L7F1
1 2 V_VREG_V1P8V5P0 32
OUT
1.6UH NA
10A TH
1 C6F3 C6U2 D3V1

1500UF 1UF 1 C7F1
20% 10% 1 C3V6
16V 1 1500UF 1UF
16V C4V7 20% 10%
2 ALUM
RDL
X7R
603 3 ADI_VREG 55 0.1UF 16V 16V
OUT 10% 2 ALUM
RDL
X7R
603
25V
V_5P0 2 2 X7R
603
BAT54A
SOT23S
DIO
V_MEM
1 3
3 C4V15 C4V8 1
1 470NF 1UF C3V7 D Q3F1
DB6G1 D Q6F1 10% 10% 470NF
10V 16V 10% 1
FET 2
17
28
1 X7R X7R 10V DB3F1
FTP FT6V1 NTD60N02R 603 603 U4V1 IC 2 NTD60N02R
X7R DPAK
DPAK 603 1 1
FT2U1 FTP
PV
IN
1 29 VREG LDOSD 27 G S
ST6F1
S G FET
2 VREG_V5P0_BST2 11 BST2 BST1 23 VREG_V1P8_BST1 2
1 2 ST2F1
ADP1823
VREG_V5P0_DH2 12 DH2 DH1 22 VREG_V1P8_DH1 2 1
SHORT ST6F2 ST2F2
1 2 VREG_V5P0_SW2 13 SW2 SW1 21 VREG_V1P8_SW1 1 2 VREG_V1P8_SW1_S
1 VREG_V5P0_SW2_S SHORT
1 R4V7 2 VREG_V5P0_CSL2 14 20 VREG_V1P8_CSL1
1 R3V1 2 1
R4V11 SHORT CSL2 CSL1 SHORT
0 7.5K 1% VREG_V5P0_DL2 16 DL2 DL1 18 VREG_V1P8_DL1 7.5K 1% R4G9
5% 402 CH 402 CH 0
ST5V1 15 19 5%
EMPTY 1 2 PGND2 PGND1 VREG_V1P8_CSL1_R
402 L6F1 ST3G1 EMPTY
2 7 COMP2 COMP1 32
1 2 VREG_V5P0_CSL2_R 1 2 402
SHORT 2
9 SS2 SS1 30 L3F1
1.7UH 4 SHORT
13.8A TH 1 2
5 UV2
1.7UH 4
VREG_V1P8_COMP1
6 FB2 FB1 1
13.8A TH
VREG_V5P0_COMP2
C6U1 1 C7F3 3 VREG_V_MEM_S_0

1UF 820UF 3
VREG_V5P0_FB2_R
20% D Q6F2 8 TRK2 TRK1 31

10% 1 C2F1 1 C2F3 1 C3F6
16V 6.3V FET 26 EN2 EN1 25 D Q2F3 C3U5
820UF 820UF 820UF
GNDSLUG
X7R 2 ALUM NTD60N02R 10 24 1UF
603 RDL POK2 POK1 20% 20% 20% 10%
DPAK 3 FREQ NTD60N02R 4V 4V 4V 16V
1 2 EMPTY POLY POLY X7R
SYNC 2 2 2
GND
DPAK RDL RDL RDL 603
1 S G 1
S 1
VREG_V5P0_SS2
2 G FET
VREG_V1P8_SS1
R4V9 LCC32 X807026-001 2 R4G1
VREG_V1P8_FB1_C
357
464
4
33
1%
ADI_FREQ
1%
CH
VREG_V5P0_FB2_C
402
1 CH
2 402
1
R4G6 2
1 R4V3 2 ADI_VREG 1.91K
C4V12 1 R4V4 2 55 1 R4V1 2 C4V11 1%
R4V6 1 2 VREG_V5P0_COMP2_R IN VREG_V1P8_COMP1_R 1 2
1.82K 10K 5% CH
1% 820PF 10% 7.5K 1% 402 CH 18.2K 1% 330PF 5% 402 1
1 50V 402 CH 402 CH 50V 2 C4G1
C4V1 CH X7R 1 R4V2 2 X7R 2700PF
3300PF 402 10%
10% 2 402 C4V13 C4V10 402 50V
50V 1 2 10K 5% 1 2 2
2 X7R 1 402 EMPTY 1 X7R
402 C4V14 C4V9 402
220PF 5% .1UF 82PF 5%
50V .1UF FREQ PIN 3: 10% 50V
NPO 10% 6.3V NPO
VREG_V5P0_FB2 402 2 6.3V 0 300KHZ 2 X5R 402 VREG_V1P8_FB1
X5R 1 600KHZ 402
402 OUT 62
1 VREG_V5P0_VMEM_PWRGD 1
34 OUT
R4V5 R4G7
243
1% 75
VREG_V1P8_EN 1%
CH ADI_VREG 1 R4V10 2 IN 34
402 55 IN CH
2 10K 5% 1 FTP FT2P19
402
402 CH 2
1 V_MEM R4G6 R4G7 R4G8
VREG_V1P8_FB1_R
R3V3 1.9V 1.91K 75 806
1K 1.95V 1.91K 43.2 806
5% 1
2.0V 1.91K 267 549
CH R4G8
34 VREG_V5P0_EN 1 R3V5 2 VREG_V5P0_EN_R 402 2.1V 1.91K 301 464
IN 2 806
1 47K 5% 1%
FT2P18 FTP 1 402 CH CH
THESE ARE THE VOLTAGES NEEDED 402
R3V4 1 FOR VARIOUS MEMORIES. CONSULT 2
1K C3V8 WITH MEM TEAM FOR USAGE.
5% .22UF
CH 10%
402 6.3V
2
2 X5R
402
DRAWING
[PAGE_TITLE=VREGS, V1P8 AND V5P0] Tue May 08 18:24:19 2007
CONFIDENTIAL
V_3P3 U6T2 EMPTY

V_5P0 V_5P0 LP2980
V_5P0 1 VIN VOUT 5
1 FTP FT1U1
U1F1 IC 3 ENABLE GND 2
1 1 C1F3 1 1
NCP5662 1 C1F5 4
VREG_3P3_EN 2 6 0.1UF 100UF R7T10 R6T3 NC
34 IN IN TAB R1U1 10% 20%
25V 16V 10K 10K
1.27K 2 5% 5% C7T100
1% X7R 2 ELEC
1 3 4 603 RDL 1UF X803461-001 2.9V
C1U1 GND OUT CH CH 10%
EMPTY 402 402
1.0UF 402 16V
1 10% 2 2 2 X7R
16V 1 EN ADJ 5 603 V_EFUSE
2
VREG_EFUSE_EN_C1
VREG_V3P3_ADJ
R1F7 X7R
1 U6T1 IC
1K 805
5% R1U2 NCP502D
X807964-001
CH 475 1 5 1
402 1% VIN VOUT FTP FT7T6
2 EMPTY VREG_EFUSE_EN_C2 3 ENABLE GND 2
1 R1F8 2 402
VREG_3P3_EN_R 2 C7T98 C7T99
1K 5% NC 4 1UF 1UF
402 CH CR6T1 10% 10%
16V 16V
TYPE PART # R1U1 R1U2 MBT3904 3 6 X810988-001 2.9V X7R EMPTY
V_5P0STBY V_3P3STBY FIXED X807964-001 EMPTY EMPTY 603 603
SC70
U5B1 IC ADJ X807089-001 1.27K 475 5 2
NCP1117
3 IN OUT 2 1 FTP FT5N1 VREG_EFUSE_EN 2 R6T4 1 THIS IS ACTUALLY A 3.3V PART
4 IN VREG_EFUSE_EN_R
4 1 XSTR
NCP612 FAMILY. NEED TO MAKE NEW SYMBOL
1 ADJUST/GND 1K 5%
1 1 402 CH
1 C5B1 1 C5B2 FT7T8 FTP
C5B3 0.1UF 100UF 2 V_3P3
1.0UF X800499-001 10% 20%
10% DPAK 25V 16V R6T1
2 16V 2 X7R 2 ELEC 10K R4C31 1 R4P14 2
X7R 3.3V 603 RDL 5% 1 2
805 0 5%
CH 0 5% 603 EMPTY V_GPUPCIE
402 603 CH
1
V_GPUCORE U5C1 IC
V_5P0 V_5P0STBY 1 R4P13 2
NCP1117 N: TARGET IS 1.25V
VREG_GPUPCIE_IN 3 IN OUT 2 1 FTP FT5R1
0 5%
603 EMPTY 1 ADJUST/GND OUT/TAB 4 1 1
2 2 IF USING U5B2 AS A FIXED - SET TO 1.8V 1 R5P2 R5C9
C4C6 1K 1
D5N1 D5B1 R5B1 = EMPTY 1.0UF X800501-001
DIO DIO 10% 1% 1%
R5B2 = 0 OHM SOT223
SOD123 SMA 16V CH CH
1 MBR130L 1 S1A 2 X7R 1.2V 402 0402
VREG_1P8STBY_D1 VREG_1P8STBY_D2
805 2 2
2 IF USING U5B2 AS AN ADJUSTABLE - SET TO 1.816V
2 R5B1 = 549 OHM
D5N2 VREG_PCIEX_ADJUST
VREG_PCIEX_R
DIO
R5B3 R5B2 = 221 OHM
1 1
SOD123 5%
MBR130L GPU R4P13 R4C31 R4P14 U5C1
1 1 R5P1
CH C5P1
1206 B13L EMPTY STUFF EMPTY STUFF 0
1 V_1P8STBY .1UF 5%
GUNGA STUFF EMPTY STUFF EMPTY 10%
U5B2 IC 6.3V CH
PLACEHOLDERS
2 X5R 402
NCP1117 402 2 1
VREG_1P8STBY_IN 3 IN OUT 2 1 FTP FT5N2 C5C5
4.7UF
10%
1 ADJUST/GND 6.3V
1 1 1 2 X5R
C5N3 C5B6 1 C5B4 V_3P3 805
1.0UF R5B1 100UF 1 R6C1 2
10% X800500-001 0.1UF
16V 549 10% 20%
2 X7R DPAK 1%
2 25V 16V 1 R5C6 2 0 1A
805 1.8V EMPTY X7R
603
2 ELEC
RDL 805 CH
402 0 1A V_CPUPLL
2 805 EMPTY
V_1P8 U6R1 EMPTY
VREG_1P8STBY_ADJ 1 R5B2 2 NCP1117
N: TARGET IS 2.20V
1 R5C4 2 VREG_CPUPLL_IN
3 IN OUT 2 1
0 5% FTP FT7R3
V_3P3 402 CH V_SBPCIE 0 1A
805 CH 1 ADJUST/GND OUT/TAB 4 1 1
U3P1 EMPTY
1 R6R3 R6R1
NCP1117 C6P1 499 1
3 2 1 1.0UF X800501-001 1% 1%
IN OUT FTP FT2P26 10% SOT223
16V EMPTY CH
1 4 1 1 2 X7R 1.8V 402 0402
ADJUST/GND OUT/TAB 805 2 2
1 R3C22 R3C21
C2C5
VREG_CPUPLL_R
X800501-001 549 1 VREG_CPUPLL_ADJUST
1.0UF 1% 1%
10% SOT223
16V EMPTY EMPTY
2 X7R 1.2V 402 0402
805 2 2 1
1
VREG_VDD_PEX_R
VREG_VDD_PEX_ADJ C6R1 R6R2

.1UF 374
1 10% 1%
6.3V 1
1 R2C3 2 EMPTY EMPTY C7P1
V_SBPCIE R3C22 C2C6 243 402 402 4.7UF
.1UF 1% 2 10%
1.87V 499 10% 6.3V
1.80V 549 2 6.3V EMPTY 2 X5R
EMPTY 402 805
402 2 1
C3C1
4.7UF
10%
6.3V
2 EMPTY DRAWING
805
[PAGE_TITLE=[VREGS, LINEAR VREGS] Tue May 08 18:24:19 2007
CONFIDENTIAL
VCS REGULATOR V_5P0
R7G23
0
805
2 1A 1
CH
L7G1
DB8U1 1 V_12P0
V_VREG_VCS 1 2
TP
CPU_SRVID 1.6UH EMPTY
4 IN 2 2 2 2 2 TH
C8G4 C7G3 C7G4 1 C7G7 C7V2 C7G5 10A 1
1 4.7UF 4.7UF 4.7UF 1500UF 0.1UF 0.1UF NA
C7F5
V_CPUCORE 10% 10% 10% 20% 10% 10% 4.7UF
16V 16V 16V 16V 25V 25V 10%
R7T19 C7U9 C8F2 1 1 1 1 1 16V
0
DB8U2 1 VREG_VCS_VREF
1UF 1UF X5R
1206
X5R
1206
X5R
1206
2 EMPTY
RDL
X7R
603
X7R
603
2 X5R
TP 10% 10%
5% 1206
16V 16V
EMPTY 1 2 X7R X7R
402 1 603 603
2 R8U8 R8U9
0 0 R8U7
5% 5% 0
V_12P0 5%
EMPTY CH V_CPUVCS
402 402 EMPTY
IRF8915PBF
10
2 1 402
4
U7F1
2 U7U2 IC FET
3
VC
VCC
2
R7F9 NC0
VREG_VCS_VP 4 GATE0 1
10K 2 VP VREG_VCS_HDRV DRN0 5 L8F2 FTP FT7U3
HDRV 9
5% DB7U2 VREG_VCS_SS_SD_N 3 SRC0 DRN0 6 VREG_VCS_VOUT_L 2 1
1 13 SS IR3638
EMPTY TP 6 VREG_VCS_LDRV
11 LDRV IND 1.7UH
402 3 1 2 VREG_VCS_RT NC2
Q7F1 C7U5 C7U6 DB8F4 1 2 GATE1 DRN1 7 TH 13.8A
V_CPUCORE 12 COMP PGND 8 4
1
VREG_VCS_LTO EMPTY 4.7NF .1UF TP 8
GND
1 10% 10% 1 DRN1
2 2
NC1
2N7002 1 C7F4
NC
SRC1
16V 6.3V 1 FB C7T103 C7T102
2 SOT23 2 X7R 1 X5R 1 SSOP 820UF 4.7UF 4.7UF
2
603 402 C8U9 R7U6 X811812-001 SO-8
20% 10% 10%
.1UF 0 X807111-001 6.3V 6.3V 6.3V
3 ALUM 1 1
5
7
X5R X5R
14
10% 402 2 RDL
1 R7U4 2 1 Q7U1 2 6.3V 805 805
1
MMBT2222 X5R EMPTY
1K 5% VREG_VCS_CPUCORE_R EMPTY 402 5% VREG_VCS_NC CR7V2
402 EMPTY 2 MBR0520L
1 SOD123
2
EMPTY
1
DB7U1
R7U6 SWITCH FREQ VREG_VCS_NC1
STUFF 400KHZ 1
DB8U3
EMPTY 200KHZ
R8U14 ST7D2
1 R7U5 2 C7U8 VREG_VCS_FB 1 R7U7 2 VREG_VCS_FB_R 1 2 2 1
VREG_VCS_COMP_C 1 2 VREG_VCS_COMP
10K 1% 0 5%
15K 1% 3300PF 10% 402 CH 402 EMPTY SHORT
402 EMPTY 50V
EMPTY
402
1 R8U6 2 C8U5
VREG_VCS_FB_COMP 1 2
C7U7 C7U11
1 2 1 2 2.67K 1% 2700PF 10%
402 EMPTY 50V
47PF 5% 220PF 5% EMPTY
50V 50V 402
EMPTY NPO
402 402
1 1
R7U8 R8U12
4.02K GAIN=20% WITH R7U7=10K, R8U12=49.9K
1% 33.2K
1% OUTPUT = CPU_SRVID(1+GAIN)
CH
402 CH
2 402
2
VREG_VCS_COMP_R
1
C7U10
0.01UF
10%
16V
2 X7R
402
DRAWING
Tue May 08 18:24:20 2007 FALCON_RETAIL 57/82 1.0
CONFIDENTIAL
XDK, DEBUG CONNECTORS

J1D2
2X5HDR_10
V_5P0STBY
35 OUT SPI_SS_N 2 1 SPI_MOSI OUT 35 KER_DBG_RXD
SPI_MISO 4 3 SPI_CLK OUT 33
35 IN OUT 35
6 5
8 7 SMC_DBG_RXD_R
9 OUT 60
HDR C1D7
.1UF
10% 1 R2P18 2
6.3V SMC_RST_N IN 27
X5R 100 5%
402
402 CH
V_3P3STBY V_5P0STBY
J9A2
1X2HDR
1
SMC_RST_XDK_N
2
C2B12 C2B15
.1UF 1UF SM
10% 10% HDR C9A3
6.3V 16V .1UF
X5R X7R 10%
402 603 6.3V
J2B1 X5R
V_3P3 402
2X7HDR_14
33 IN KER_DBG_TXD 2 1
34 IN SMC_DBG_TXD 4 3
34 OUT SMC_DBG_EN 6 5
8 7
SMB_CLK_R 10 9 SMB_DATA_R 1 R2N14 2 SMB_DATA 27 34
12 11
BI
100 5%
1 13 402 CH
C1R2
.1UF
10% HDR 1 R3B3 2
6.3V EXT_PWR_ON_DBG EXT_PWR_ON_N OUT 44 58 34
2 X5R 27 34 SMB_CLK 1 R2N13 2
402 BI 1K 5%
100 5% 402 CH
402 CH V_5P0STBY V_12P0
1
1 D8B4
C3B8 C3B9 GREEN
.1UF 1UF SM
10% 10%
6.3V 16V 2 LED
2 X5R X7R
402 603 1 CPU_CHECKSTOP_N_LED
R8B6
2K
1%
CH
402
2
CPU_CHECKSTOP_N_LED_B
CPU_CHECKSTOP_N_LED_C
3
1 R8A5 2 1 Q8B6
MMBT2222
1K 5% XSTR V_3P3STBY
402 CH 2
PCIEX DEBUG CONNECTOR
N: DEBUG BOARDS ONLY
I225 2
SM V_1P8 R2P19
J3C1 EMPTY V_1P8 10K
5%
PCIEX
CH
MIDBUS 402
2 1 PEX_GPU_SB_L0_DP
IN 13 2 2 2 2 1
PEX_SB_GPU_L0_DP PEX_GPU_SB_L0_DN
2
33 4 3 13
IN IN R8C3 R8C4 R8C5 R8C6 1 R8P8 SMC_CPU_CHKSTOP_DETECT
33 IN PEX_SB_GPU_L0_DN 6 5 10K 10K 10K 10K C8P5 BI 34
8 7 PEX_GPU_SB_L1_DP 13 5% 5% 5% 5% .1UF 10K
PEX_SB_GPU_L1_DP PEX_GPU_SB_L1_DN
IN 10% 5% SMC_CPU_CHKSTOP_DETECT_B
33 10 9 13 EMPTY EMPTY EMPTY EMPTY 6.3V 3
IN PEX_SB_GPU_L1_DN
IN 402 402 402 402 2 X5R EMPTY
33 IN 12 11
1 1 1 1 402 402 1 R3N8 2 1 Q2P1
14 13 1 MMBT2222
16 15 1K 5% EMPTY
402 EMPTY 2
18 17 J8C1
20 19 2X5HDR
22 21
CPU_RST_V1P1_N 2 R8C2 1 CPU_RST_N_2_R 2 1 CPU_CHECKSTOP_N_R
1 R8C8 2 CPU_CHECKSTOP_N
24 23 4 IN IN 59
1K 5% 4 3 0 5%
402 CH 6 5 402 CH
X801071-001 59 OUT CPU_TMS 8 7 CPU_TCLK OUT 59
59 OUT CPU_TRST_N 10 9 EXT_PWR_ON_N OUT 44 58 34
59 IN CPU_TDO
59 OUT CPU_TDI HDR
N: FOOTPRINT PADS 13-24 REMOVED.
N: REMOVED PADS FREE UP NEEDED 1 1
FT7R7 FTP C7D23
BOARD SPACE FOR ROUTING. .1UF
10%
6.3V
2 X5R
402
DRAWING
[PAGE_TITLE=XDK. DEBUG CONN] Tue May 08 18:24:19 2007
CONFIDENTIAL
V_GPUCORE DEBUG BOARD, CPU + GPU DEBUG BREAKOUT]

U4D1 7 OF 12 IC U7D1 3 OF 10 IC
GPU Y2 VERSION 1 LOKI
58 IN CPU_TCLK AF5 TCLK TDO AG5 CPU_TDO OUT 58
58 IN CPU_TDI AH6 TDI CHECKSTOP_B AG1 CPU_CHECKSTOP_N OUT 58
TBCLK1 G30 58 IN CPU_TMS AH2 TMS
TBCLK0 F32 58 IN CPU_TRST_N AH5 TRST_B DEBUG_CLKOUT_DP D23 CPU_DBG_CLK_DP OUT
DEBUG_CLKOUT_DN C23 CPU_DBG_CLK_DN OUT
CPU_DBGSEL_XDK<0..69> OUT 47
DEBUG_OUT0 F9 0
DEBUG_OUT1 C8 1
DEBUG_OUT2 E8 2 N:CPU_DBGSEL_DEBUG<0..69>
DEBUG_OUT3 D7 3 N:CPU_DBGSEL_XDK<0..69>
V_GPUCORE DEBUG_OUT4 B8 4
DEBUG_OUT5 A8 5
DEBUG_OUT6 F11 6
DEBUG_OUT7 D9 7
DEBUG_OUT8 C9 8
DEBUG_OUT9 F13 9
DEBUG_OUT10 A9 10
1 1 1 1
C6T35 C7T90 C6T36 C7T91 DEBUG_OUT11 E10 11
.1UF .1UF .1UF .1UF DEBUG_OUT12 C10 12
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V DEBUG_OUT13 B10 13
2 X5R 2 X5R 2 X5R 2 X5R DEBUG_OUT14 E12 14
D28 402 402 402 402 D11
TB15 DEBUG_OUT15 15
TB14 H29 DEBUG_OUT16 A10 16
TB13 E29 DEBUG_OUT17 C11 17
TB12 H30 DEBUG_OUT18 A11 18
TB11 C30 DEBUG_OUT19 C12 19
TB10 B30 DEBUG_OUT20 F15 20
TB9 A30 V_GPUCORE DEBUG_OUT21 B12 21
TB8 G31 DEBUG_OUT22 E14 22
TB7 B31 DEBUG_OUT23 D13 23
TB6 A31 DEBUG_OUT24 C13 24
TB5 B32 DEBUG_OUT25 A12 25
TB4 A32 DEBUG_OUT26 C14 26
TB3 F33 1 1 1 1 DEBUG_OUT27 D15 27
E33 C6T12 C6T34 C7T92 C6T31 C15 28
TB2 .1UF .1UF .1UF .1UF DEBUG_OUT28
TB1 D33 10% 10% 10% 10% DEBUG_OUT29 B14 29
E34 6.3V 6.3V 6.3V 6.3V E16
TB0 2 X5R 2 X5R 2 X5R 2 X5R DEBUG_OUT30 30
402 402 402 402 DEBUG_OUT31 A13 31
DEBUG_OUT32 A14 32
X02125-001 DEBUG_OUT33 C16 33
DEBUG_OUT34 B16 34
DEBUG_OUT35 A15 35
DEBUG_OUT36 A16 36
DEBUG_OUT37 A17 37
DEBUG_OUT38 D17 38
DEBUG_OUT39 C17 39
DEBUG_OUT40 F17 40
DEBUG_OUT41 A18 41
DEBUG_OUT42 B18 42
DEBUG_OUT43 A19 43
DEBUG_OUT44 C18 44
DEBUG_OUT45 C19 45
DEBUG_OUT46 D19 46
DEBUG_OUT47 E18 47
DEBUG_OUT48 C20 48
DEBUG_OUT49 C21 49
DEBUG_OUT50 E20 50
DEBUG_OUT51 F19 51
DEBUG_OUT52 A20 52
DEBUG_OUT53 B26 53
DEBUG_OUT54 B20 54
DEBUG_OUT55 A21 55
DEBUG_OUT56 A22 56
DEBUG_OUT57 A26 57
DEBUG_OUT58 B22 58
DEBUG_OUT59 A24 59
DEBUG_OUT60 A27 60
DEBUG_OUT61 A23 61
DEBUG_OUT62 A28 62
DEBUG_OUT63 A25 63
DEBUG_OUT64 F21 64
DEBUG_OUT65 D21 65
DEBUG_OUT66 B24 66
DEBUG_OUT67 C22 67
DEBUG_OUT68 E22 68
DEBUG_OUT69 F23 69
X806937-001
DRAWING
[PAGE_TITLE=DEBUG BOARD, CPU + GPU DEBUG BREAKOUT] Tue May 08 18:24:19 2007
CONFIDENTIAL
XDK DEBUG, LEDS
2 R6G36 1 V_MEM
5% 0
60 BI MEMPORT3_DN_ARGONYETI EMPTY 402 MEMPORT3_DN_ARGON BI 49
60 BI MEMPORT3_DP_ARGONYETI MEMPORT3_DP_ARGON BI 49 2
2 R6G35 1 R7F6
0
5% 0 5%
EMPTY 402 CH
603
J7G3 1
2X6HDR
2 R6V2 1 1 2 V_YETI
5% 0 3 4 N: CONNECTED TO V_MEMPORT
EMPTY 402 MEMPORT3_DN_YETI 5 6 FOR BETTER ROUTING
MEMPORT3_DP_YETI 7 8
9 10
2 R6V1 1 11 12 V_MEMPORT1 46
IN
5% 0
EMPTY 402 HDR 1 2
C7G9 C7G8
.1UF 4.7UF
10% 10%
6.3V 6.3V
1 R7V8 2
2 EMPTY 1 EMPTY
34 IN CPU_PWRGD CPU_PWRGD_R 402 805
5% 1K
CH 402
2 R2D14 1
5% 0
35 BI MEMPORT3_DN EMPTY 402 MEMPORT3_DN_ARGONYETI V_5P0 V_1P8
BI 60 V_3P3
35 BI MEMPORT3_DP MEMPORT3_DP_ARGONYETI BI 60
2 R2D13 1
C2T9
1 2
5% 0
EMPTY 402
1 2 .1UF 10%
J1E2 C2T10 C1T6 6.3V
.1UF 4.7UF EMPTY
1X5HDR 10% 10% 402
2 R2R8 1 6.3V 6.3V
1 2 EMPTY 1 EMPTY C2T8
5% 0 2 402 805 1 2
EMPTY 402 MEMPORT3_DN_FLASH 3
MEMPORT3_DP_FLASH 4 .1UF 10%
6.3V
2 R2R7 1 5 EMPTY
402
5% 0 EMPTY
EMPTY 402
TH
DRAWING
[PAGE_TITLE=XDK, DEBUG LEDS, BDCM PHY] Tue May 08 18:24:20 2007
CONFIDENTIAL
INTELLIGENT SERIAL NUMBER TARGET.

LB7G1
LABEL
1
1375X250_TARGET
X801181-001
MIDDLE PCB MOUNTING HOLES EAST PCB MOUNTING HOLES

EDGE CTR EDGE
MTG1B1 MTG5G1 MTG9G1
MTG_HOLE MTG_HOLE MTG_HOLE
NC9 9 NC9 9 NC9 9
EMPTY EMPTY EMPTY

GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
EDGE CTR EDGE
MTG1G1 MTG5B1 MTG9B1
MTG_HOLE MTG_HOLE MTG_HOLE
NC9 9 NC9 9 NC9 9
EMPTY EMPTY EMPTY

GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
HEAT SINK MOUNTING HOLES

STD STD
MTG8C1 MTG6E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG3C1 MTG3E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG6C1 MTG8E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG5C1 MTG5E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
DRAWING
[PAGE_TITLE=LABELS AND MOUNTING, PCI SWIZ] Tue May 08 18:24:20 2007
CONFIDENTIAL
GPU VID BOARD

60 OHM COUPONS (TOP & BOTTOM)
TP7M2 EMPTY
TDRX2
TDR_SINGLE_XDK2 1 SIG
2 GND
THESE CONNECTORS ARE EMPTY BY DEFAULT
THEY ARE ONLY STUFFED WHEN VIPER IS REQUIRED
90 OHM COUPONS (TOP) TP5A1 EMPTY
TDRX4
TDR_DIFF_XDK3_DP 1 DP
2 GND
TDR_DIFF_XDK3_DN 3 DN TP7M1 EMPTY
4 GND TDRX2
1 SIG
2 GND
J8B1
1X8HDR
TP5A2 EMPTY
TDRX4 53 IN VREG_GPU_VID4 1
53 VREG_GPU_VID3 2 TP8A2 EMPTY
1
IN VREG_GPU_VID2 3 TDRX2
DP 53 IN
2 GND 53 IN VREG_GPU_VID1 4
TDR_SINGLE_XDK1 1 SIG
3 DN 53 IN VREG_GPU_VID0 5
2
4 6 GND
GND
53 IN VREG_GPU_VFFB 7
8
EMPTY
TH
TP8A1 EMPTY
TDRX2
THIS IS ON THE MOTHERBOARD
THE REST IS ON A SEPARATE BOARD ON THE FAN CUTOUT 1 SIG
2 GND
100 OHM COUPONS (TOP & BOTTOM) TP7A1 EMPTY

TDRX4
V_MEM
2 GND J4G1
TDR_DIIFF_XDK2_DN 3 J4F1 1X2HDR
DN VREG_V1P8_FB1 1
4 1X3HDR 55 OUT
GND 1 2 50 OHM COUPONS (TOP)
2 TP6A2 EMPTY
3 TH TDRX2
EMPTY
EMPTY TDR_SINGLE_XDK3 1 SIG
TP7A2 EMPTY 2 GND
TDRX4 THESE ARE ON THE MOTHERBOARD
1 DP
2 GND
3 DN
4 GND
TP6A1 EMPTY
TP8M1 EMPTY TDRX2
TDRX4 1 SIG
2 GND
2 GND
TDR_DIFF_XDK1_DN 3 DN
4 GND
TP8M2 EMPTY
TDRX4
1 DP
2 GND
3 DN
4 GND
MICROSOFT PROJECT NAME PAGE REV

CONFIDENTIAL
Title: Basenet Report BLEEDER_B 47A4 CPU_SPI_WP_N 4A2 ENET_P4RD 39B3
Design: falcon BLEEDER_C1 47A4 CPU_SRVID 4B6 57D7 ENET_POAC_R 39C3 45B4
Date: May 8 12:04:43 2007 BLEEDER_C2 47A3 CPU_SYS_CONFIG0 4C6 ENET_RDAC 40B3
BLEEDER_V12P0_B1 49A3 CPU_SYS_CONFIG1 4C6 ENET_REF_CLK2_OUT 40C5
Base nets and synonyms for BLEEDER_V12P0_B2 49B2 CPU_TCLK 58A1 59D5 ENET_REF_CLK_OUT 39C6
falcon_lib.FALCON(@falcon_lib.falcon(sch_ BLEEDER_V12P0_C1 49A3 CPU_TDI 58A5 59D5 ENET_RST_N 33A2 39C8 40C6
1)) BLEEDER_V12P0_C2 49A2 CPU_TDO 59D1 58A5 ENET_RX_CT 45B4
Base Signal BLEEDER_V12P0_LOAD 49A2 CPU_TEMP_N 4B2 28A8 ENET_RX_DN 39C1 40B3 45B4
Location([Zone][dir]) BND_GAP_CAP 28B6 CPU_TEMP_P 28A1 4B2 ENET_RX_DN_R 39C2
BRD_TEMP_N 28A5 28A8 CPU_TEST_EN 4B5 ENET_RX_DP 39D1 40B3 45B4
ADI_FREQ 55B5 BRD_TEMP_P 28A1 28A5 CPU_TMS 58A5 59D5 ENET_RX_DP_R 39D2
ADI_VREG 55D4 55A7 55B4 CAL_TEMP_N 28A1 28A8 CPU_TRST_N 58A5 59D5 ENET_TX_CT 45B4
ANA_CLK_OE 34B3 27C8 CAL_TEMP_P 28A3 CPU_VDDE 6C5 ENET_TX_DN 39A1 40B3 45B4
ANA_CLK_OE_R 27C7 CPU_ANL_1 4B6 CPU_VDDS0_DN 4C3 ENET_TX_DN_R 39B2
ANA_PIX_CLK_2X_DN 27B1 13C8 CPU_ANL_2 4B6 CPU_VDDS0_DP 4C3 ENET_TX_DP 39C1 40B3 45B4
ANA_PIX_CLK_2X_DN_R 27C4 CPU_CHECKSTOP_N 59D1 58A1 CPU_VDDS1_DN 4C3 ENET_TX_DP_R 39B2
ANA_PIX_CLK_2X_DP 27B1 13C8 CPU_CHECKSTOP_N_LED 58B2 CPU_VDDS1_DP 4C3 EN_TEST0_N 34A6
ANA_PIX_CLK_2X_DP_R 27C4 CPU_CHECKSTOP_N_LED_B 58B3 CPU_VGATE 4B5 EN_TEST1_N 34A6
ANA_RST_N 34C3 27D7 CPU_CHECKSTOP_N_LED_C 58B2 CPU_VREG_APS0 4B2 50C7 EXPPORT_DN 35B3 45C8
ANA_V12P0_PWRGD 27D3 34C3 49A5 CPU_CHECKSTOP_N_R 58A3 CPU_VREG_APS1 4B2 50D7 EXPPORT_DN_CM 45C5
ANA_VID_INT 28D3 33B2 CPU_CLK_DN 27D1 4D6 CPU_VREG_APS2 4B2 50D7 EXPPORT_DP 35B3 45C8
ANA_VRST_OK 27D3 34A8 CPU_CLK_DN_C 4D5 CPU_VREG_APS3 4B2 50D7 EXPPORT_DP_CM 45C5
ARGONPORT_DN 35C3 49C8 CPU_CLK_DN_R 27C4 CPU_VREG_APS4 4B2 50D7 EXT_PWR_ON_DBG 58C5
ARGONPORT_DP 35C3 49C8 CPU_CLK_DP 27D1 4D6 CPU_VREG_APS5 4B2 50D7 EXT_PWR_ON_N 44C1 58A1 58C3 34D8
ARGON_CLK 34A1 49B7 CPU_CLK_DP_C 4D5 DBG_CPU_LINKTRAINED 47C5 44A3
ARGON_DATA 34A1 49B7 CPU_CLK_DP_R 27C4 DBG_CPU_PLL_LOCK 47C5 EXT_PWR_ON_R 34C6
ARGON_DN_CM 49C6 CPU_CORE_IF_BGR_PLL 4D3 DBG_CPU_POST_OUT0 47C5 FAN1_FDBK 43C2 28B6
ARGON_DP_CM 49C6 CPU_DBGSEL_DEBUG<0..69> 47D3 DBG_CPU_POST_OUT1 47C5 FAN1_FDBK_R 43C4
ARGON_NTX 45B6 CPU_DBGSEL_XDK<0..69> 59D1 47D7 DBG_CPU_POST_OUT2 47C5 FAN1_OUT 28B3 43D5
AUD_ACAP 41C5 CPU_DBG_CLK_DN 59D1 DBG_CPU_POST_OUT3 47C5 FAN1_Q1_C 43D4
AUD_AC_L 41B5 CPU_DBG_CLK_DP 59D1 DBG_CPU_POST_OUT4 47C5 FAN1_Q1_E 43C4
AUD_AC_R 41D5 CPU_EXT_CLK_EN 4C6 DBG_CPU_POST_OUT5 47C5 FAN_OP1_DP 28B7
AUD_CLAMP 34C6 41A6 CPU_FSB_CLK_SEL 4C6 DBG_CPU_POST_OUT6 47C5 FLSH_ALE 35C3 42B5
AUD_CLAMP_B1 41A6 CPU_FSB_HF_CLKOUT_DN 4C2 DBG_CPU_POST_OUT7 47C5 FLSH_CE_N 35C3 42B5
AUD_CLAMP_B2 41A4 CPU_FSB_HF_CLKOUT_DP 4C2 DBG_CPU_SECURE_SYS 47C5 FLSH_CLE 35C3 42B5
AUD_CLAMP_B3 41A2 CPU_FSB_IMPED_CAL_DN 4C2 DBG_CPU_TST_CLK 47C5 FLSH_DATA<7..0> 35C6 42C8
AUD_CLAMP_C 41A5 CPU_FSB_IMPED_CAL_DP 4C2 DBG_LED0 34A8 34A6 FLSH_NC38 42C2
AUD_CLAMP_L 41B3 CPU_PLL_BYPASS 4C6 DBG_LED0_LED 34A4 FLSH_READY 42C1 35C7
AUD_CLAMP_R 41D3 CPU_POST_IN<0..4> 4C6 DBG_LED0_LED_R 34A5 FLSH_RE_N 35C3 42B5
AUD_CLK 27A1 36C7 CPU_PSRO0_OUT 4C3 ECB_CLK_BYP 33D6 FLSH_WE_N 35C3 42B5
AUD_CLK_R 27B4 CPU_PULSE_LIMIT_BYPASS 4C6 ECB_CLK_SEL 33D6 FLSH_WP_N 35C6 42B5
AUD_DCAP 41C7 CPU_PWRGD 34B3 4D8 60C5 EDRAM_TEMP_N 13C8 28A8 FSB_BYPCLK_DN 12D7
AUD_L_OUT 41C1 44B4 CPU_PWRGD_R 60C4 EDRAM_TEMP_P 28A1 13C8 FSB_BYPCLK_DP 12D7
AUD_RST_N 33B2 41C8 CPU_PWRGD_V1P1_N 4D7 EJECTSW_N 43C6 34B3 48A1 FSB_BYPCLK_SEL 12D7
AUD_R_OUT 41C1 44B4 CPU_RES0_DN 4C3 EJECTSW_N_R 43C7 FSB_CLK_DN 4C6
AUD_VAA 41D6 CPU_RES0_DP 4C3 ENET_10BIAS 39B6 FSB_CLK_DP 4C6
AUD_VDD 41D7 CPU_RST_N 34B3 4D8 ENET_10_100_OUT 39B5 FSB_CP_GP0_CLK_DN 5D3 12D8
AUD_VOUTL 41C6 CPU_RST_N_2_R 58A4 ENET_100BIAS 39B6 FSB_CP_GP0_CLK_DP 5D3 12D8
AUD_VOUTR 41C6 CPU_RST_V1P1_N 4D8 58A6 ENET_ACT_N 39C3 40B3 45B4 FSB_CP_GP0_DATA0_DN 5C3 12C8
AV_MODE0 44C1 34B8 44A3 CPU_SPI_CLK 4B1 4A5 ENET_AMDIX_EN 39B6 FSB_CP_GP0_DATA0_DP 5C3 12C8
AV_MODE0_R 34B6 CPU_SPI_CLK_R 4A4 ENET_AVDD 40C4 40B3 40B6 FSB_CP_GP0_DATA1_DN 5C3 12C8
AV_MODE1 44C1 34B8 44A3 CPU_SPI_EN 4B2 4A6 ENET_CLK 27A1 39C7 40C6 FSB_CP_GP0_DATA1_DP 5C3 12C8
AV_MODE1_R 34B6 CPU_SPI_EN_R 4A4 ENET_CLK_R 27C4 FSB_CP_GP0_DATA2_DN 5C3 12C8
AV_MODE2 44C1 34B8 44A3 CPU_SPI_SI 4A1 4B6 ENET_LINK_N 39B2 40B3 45B4 FSB_CP_GP0_DATA2_DP 5C3 12C8
AV_MODE2_R 34B6 CPU_SPI_SI_R 4A2 ENET_P1CL 39B4 FSB_CP_GP0_DATA3_DN 5C3 12C8
BINDSW_N 43D6 34B3 CPU_SPI_SO 4B2 4A5 ENET_P2LI_R 39B2 45B4 FSB_CP_GP0_DATA3_DP 5C3 12C8
BINDSW_N_R 43D7 CPU_SPI_SO_R 4A4 ENET_P3TD 39B4 FSB_CP_GP0_DATA4_DN 5C3 12C8
CONFIDENTIAL
FSB_CP_GP0_DATA4_DP 5C3 12C8 FSB_GP_CP1_DATA3_DN 12B4 5B7 HANA_OP2_OUT 28A3 I2S_SD3 28C7
FSB_CP_GP0_DATA5_DN 5C3 12C8 FSB_GP_CP1_DATA3_DP 12B4 5B7 HANA_POR_BYPASS 27D6 I2S_SD_R 36C4
FSB_CP_GP0_DATA5_DP 5C3 12C8 FSB_GP_CP1_DATA4_DN 12B4 5B7 HANA_SPDIF_OUT 28C3 44D6 I2S_WS 36C1 28C6 41C7
FSB_CP_GP0_DATA6_DN 5C3 12C8 FSB_GP_CP1_DATA4_DP 12B4 5B7 HANA_TCLK 27B6 I2S_WS_R 36C4
FSB_CP_GP0_DATA6_DP 5C3 12C8 FSB_GP_CP1_DATA5_DN 12B4 5B7 HANA_TDI 27B6 IR_DATA 43A1 34B6
FSB_CP_GP0_DATA7_DN 5C3 12C8 FSB_GP_CP1_DATA5_DP 12B4 5B7 HANA_TDO 27B6 KER_DBG_RXD 58D4 33C6
FSB_CP_GP0_DATA7_DP 5C3 12C8 FSB_GP_CP1_DATA6_DN 12B4 5B7 HANA_TMS 27B6 KER_DBG_TXD 33C1 58C6
FSB_CP_GP0_FLAG_DN 5C3 12C8 FSB_GP_CP1_DATA6_DP 12B4 5B7 HANA_TRST 27B6 KER_DBG_TXD_R 33C3
FSB_CP_GP0_FLAG_DP 5C3 12C8 FSB_GP_CP1_DATA7_DN 12B4 5B7 HANA_V_12P0_DET 27D6 LVLCNT 44B5
FSB_CP_GP1_CLK_DN 5C3 12C8 FSB_GP_CP1_DATA7_DP 12B4 5B7 HANA_V_12P0_DET_R 27D6 MA_A<11..0> 19C8 20C8 14C5
FSB_CP_GP1_CLK_DP 5C3 12C8 FSB_GP_CP1_FLAG_DN 12B4 5B7 HANA_XTAL_BYPASS 27C6 MA_A<12..0> 14C5
FSB_CP_GP1_DATA0_DN 5B3 12B8 FSB_GP_CP1_FLAG_DP 12C4 5B7 HANA_XTAL_IN 27C6 MA_BA<2..0> 14C5 19B8 20C8
FSB_CP_GP1_DATA0_DP 5B3 12B8 FSB_IMPED_CAL 12B7 HANA_XTAL_OUT 27C6 MA_CAS_N 14B5 19B8 20B8
FSB_CP_GP1_DATA1_DN 5B3 12B8 FSB_IMPED_NCAL 12B7 HANA_XTAL_VSS_CAP 27C6 MA_CKE 14B5 19B8 20B8
FSB_CP_GP1_DATA1_DP 5B3 12B8 GAMEPORT1_DN 35B6 46A8 HBEDB_CLK_BYP 33D6 MA_CLK0_DN 14C5 19C8
FSB_CP_GP1_DATA2_DN 5B3 12B8 GAMEPORT1_DN_CM 46B6 HBEDB_CLK_SEL 33C6 MA_CLK0_DP 14C5 19D8
FSB_CP_GP1_DATA2_DP 5B3 12B8 GAMEPORT1_DP 35B6 46A8 HDD_RX_DN 48C8 36B7 MA_CLK1_DN 14C5 20C8
FSB_CP_GP1_DATA3_DN 5B3 12B8 GAMEPORT1_DP_CM 46B6 HDD_RX_DN_C 48C6 MA_CLK1_DP 14C5 20D8
FSB_CP_GP1_DATA3_DP 5B3 12B8 GAMEPORT2_DN 35B6 46C8 HDD_RX_DP 48B8 36B7 MA_CS0_N 14B5 19B8
FSB_CP_GP1_DATA4_DN 5B3 12B8 GAMEPORT2_DN_CM 46B6 HDD_RX_DP_C 48B6 MA_CS1_N 14B5 19B1 20B8
FSB_CP_GP1_DATA4_DP 5B3 12B8 GAMEPORT2_DP 35B6 46C8 HDD_TX_DN 36B3 48D8 MA_DM0 14B8 19B4 20B5
FSB_CP_GP1_DATA5_DN 5B3 12B8 GAMEPORT2_DP_CM 46B6 HDD_TX_DN_C 48D6 MA_DM1 14C8 19B4 20B5
FSB_CP_GP1_DATA5_DP 5B3 12B8 GPU_CLK_DN 27D1 13D7 HDD_TX_DP 36B3 48D8 MA_DM2 14C8 19C4 20C5
FSB_CP_GP1_DATA6_DN 5B3 12B8 GPU_CLK_DN_R 27C4 HDD_TX_DP_C 48D6 MA_DM3 14D8 19C4 20C5
FSB_CP_GP1_DATA6_DP 5B3 12B8 GPU_CLK_DP 27D1 13D7 HDMI_CEC 29C3 MA_DQ0 14B8 19B4 20B5
FSB_CP_GP1_DATA7_DN 5B3 12B8 GPU_CLK_DP_R 27C4 HDMI_DDC_CLK 28C3 34B8 44C1 29B5 MA_DQ1 14B8 19B4 20B5
FSB_CP_GP1_DATA7_DP 5B3 12B8 GPU_HSYNC_OUT 13C4 28C6 HDMI_DDC_DATA 28C3 34C8 44C1 29B5 MA_DQ2 14B8 19B4 20B5
FSB_CP_GP1_FLAG_DN 5B3 12B8 GPU_PIX_CLK_1X 13C3 28D6 HDMI_EXT_SWING 28C4 MA_DQ3 14B8 19B4 20B5
FSB_CP_GP1_FLAG_DP 5B3 12C8 GPU_RST_DONE 13D3 34C1 HDMI_HPD 29B1 28C6 MA_DQ4 14B8 19B4 20B5
FSB_GP_CP0_CLK_DN 12D4 5D7 GPU_RST_DONE_R 34B4 HDMI_HPD_PIN 29B2 MA_DQ5 14B8 19B4 20B5
FSB_GP_CP0_CLK_DP 12D4 5D7 GPU_RST_N 34B3 13D8 HDMI_TX0_DN 28B1 29B8 MA_DQ6 14B8 19B4 20C5
FSB_GP_CP0_DATA0_DN 12C4 5C7 GPU_SCAN_BUFF_EN_N 13A7 12A3 HDMI_TX0_DN_CM 29C3 MA_DQ7 14B8 19B4 20C5
FSB_GP_CP0_DATA0_DP 12C4 5C7 GPU_SPI_CLK 13B3 13A7 HDMI_TX0_DP 28B1 29B8 MA_DQ8 14C8 19B4 20B5
FSB_GP_CP0_DATA1_DN 12C4 5C7 GPU_SPI_CLK_R 13A5 HDMI_TX0_DP_CM 29C3 MA_DQ9 14C8 19B4 20B5
FSB_GP_CP0_DATA1_DP 12C4 5C7 GPU_SPI_CS_N 13B3 13A7 HDMI_TX0_DP_R 28B2 MA_DQ10 14C8 19B4 20B5
FSB_GP_CP0_DATA2_DN 12C4 5C7 GPU_SPI_CS_N_R 13A5 HDMI_TX1_DN 28B1 29C8 MA_DQ11 14C8 19B4 20B5
FSB_GP_CP0_DATA2_DP 12C4 5C7 GPU_SPI_SI 13A2 13B4 13C7 HDMI_TX1_DN_CM 29C3 MA_DQ12 14C8 19B4 20B5
FSB_GP_CP0_DATA3_DN 12C4 5C7 GPU_SPI_SO 13C3 13A7 HDMI_TX1_DP 28B1 29C8 MA_DQ13 14C8 19B4 20B5
FSB_GP_CP0_DATA3_DP 12C4 5C7 GPU_SPI_SO_R 13A5 HDMI_TX1_DP_CM 29C3 MA_DQ14 14C8 19C4 20B5
FSB_GP_CP0_DATA4_DN 12C4 5C7 GPU_SPI_WP_N 13B4 13A4 HDMI_TX1_DP_R 28B2 MA_DQ15 14C8 19C4 20B5
FSB_GP_CP0_DATA4_DP 12C4 5C7 GPU_SROM_EN_PSRO_OUT 13C5 HDMI_TX2_DN 28B1 29D8 MA_DQ16 14C8 19C4 20C5
FSB_GP_CP0_DATA5_DN 12C4 5C7 GPU_TCLK 13B7 HDMI_TX2_DN_CM 29C3 MA_DQ17 14C8 19C4 20C5
FSB_GP_CP0_DATA5_DP 12C4 5C7 GPU_TCLK_R 34A8 13C7 HDMI_TX2_DP 28C1 29D8 MA_DQ18 14C8 19C4 20C5
FSB_GP_CP0_DATA6_DN 12C4 5C7 GPU_TDI 13B7 HDMI_TX2_DP_CM 29C3 MA_DQ19 14C8 19C4 20C5
FSB_GP_CP0_DATA6_DP 12C4 5C7 GPU_TDO 13B7 HDMI_TX2_DP_R 28C2 MA_DQ20 14C8 19C4 20C5
FSB_GP_CP0_DATA7_DN 12C4 5C7 GPU_TEMP_N 13C8 28A8 HDMI_TXC_DN 28C1 29A8 MA_DQ21 14C8 19C4 20D5
FSB_GP_CP0_DATA7_DP 12C4 5C7 GPU_TEMP_P 28A1 13C8 HDMI_TXC_DN_CM 29C3 MA_DQ22 14C8 19C4 20D5
FSB_GP_CP0_FLAG_DN 12C4 5C7 GPU_TMS 13B7 HDMI_TXC_DP 28C1 29A8 MA_DQ23 14C8 19C4 20D5
FSB_GP_CP0_FLAG_DP 12C4 5C7 GPU_TRST 13B7 HDMI_TXC_DP_CM 29C3 MA_DQ24 14D8 19C4 20C5
FSB_GP_CP1_CLK_DN 12C4 5C7 GPU_TRST_ED 13B7 HDMI_TXC_DP_R 28C2 MA_DQ25 14D8 19C4 20C5
FSB_GP_CP1_CLK_DP 12C4 5C7 GPU_VSYNC_OUT 13C4 28C6 I2S_BCLK 36C1 28C6 41C7 MA_DQ26 14D8 19C4 20C5
FSB_GP_CP1_DATA0_DN 12B4 5B7 HANA_AV_CLK 27B4 I2S_BCLK_R 36C4 MA_DQ27 14D8 19C4 20C5
FSB_GP_CP1_DATA0_DP 12B4 5B7 HANA_CLK_DRV_RSET1 27C6 I2S_MCLK 36C1 41C7 MA_DQ28 14D8 19C4 20C5
FSB_GP_CP1_DATA1_DN 12B4 5B7 HANA_CLK_DRV_RSET2 27C6 I2S_MCLK_R 36C4 MA_DQ29 14D8 19D4 20C5
FSB_GP_CP1_DATA1_DP 12B4 5B7 HANA_DAC_RSET 28C6 I2S_SD 36C1 28B6 41C7 MA_DQ30 14D8 19D4 20C5
FSB_GP_CP1_DATA2_DN 12B4 5B7 HANA_OP2_DN 28A1 28B6 I2S_SD1 28C7 MA_DQ31 14D8 19D4 20C5
FSB_GP_CP1_DATA2_DP 12B4 5B7 HANA_OP2_DP 28B6 I2S_SD2 28C7 MA_RAS_N 14B5 19B8 20B8
CONFIDENTIAL
MA_RDQS0 19B4 20B5 14B8 MB_DQ29 14D4 21C5 22C5 MC_DQ25 15D8 23C4 24C4 MD_DQ21 15C4 25C4 26D5
MA_RDQS1 19B4 20B5 14C8 MB_DQ30 14D4 21C5 22C5 MC_DQ26 15D8 23C4 24C4 MD_DQ22 15C4 25C4 26D5
MA_RDQS2 19C4 20C5 14C8 MB_DQ31 14D4 21D5 22C5 MC_DQ27 15D8 23C4 24C4 MD_DQ23 15D4 25C4 26D5
MA_RDQS3 19C4 20C5 14D8 MB_RAS_N 14B1 21B8 22B8 MC_DQ28 15D8 23C4 24C4 MD_DQ24 15D4 25C4 26C5
MA_VREF0 14A7 MB_RDQS0 21B4 22B4 14B4 MC_DQ29 15D8 23D4 24C4 MD_DQ25 15D4 25C4 26C5
MA_VREF1 14A8 MB_RDQS1 21B4 22B4 14C4 MC_DQ30 15D8 23D4 24C4 MD_DQ26 15D4 25C4 26C5
MA_WDQS0 14B8 19B4 20B5 MB_RDQS2 21C4 22C4 14C4 MC_DQ31 15D8 23D4 24C4 MD_DQ27 15D4 25D4 26C5
MA_WDQS1 14C8 19B4 20B5 MB_RDQS3 21C4 22C4 14D4 MC_RAS_N 15B5 23B8 24B8 MD_DQ28 15D4 25D4 26C5
MA_WDQS2 14C8 19C4 20C5 MB_VREF0 14A4 MC_RDQS0 23B4 24B4 15B8 MD_DQ29 15D4 25D4 26C5
MA_WDQS3 14D8 19C4 20C5 MB_VREF1 14A4 MC_RDQS1 23B4 24B4 15C8 MD_DQ30 15D4 25D4 26C5
MA_WE_N 14B5 19B8 20B8 MB_WDQS0 14B4 21B4 22B4 MC_RDQS2 23C4 24C4 15C8 MD_DQ31 15D4 25D4 26C5
MA_ZQ_BOT 20B5 MB_WDQS1 14C4 21B4 22B4 MC_RDQS3 23C4 24C4 15D8 MD_RAS_N 15B1 25B8 26B8
MA_ZQ_TOP 19B5 MB_WDQS2 14C4 21C4 22C4 MC_VREF0 15A7 MD_RDQS0 25B4 26B4 15B4
MB_A<11..0> 21C8 22C8 14C1 MB_WDQS3 14D4 21C4 22C4 MC_VREF1 15A8 MD_RDQS1 25B4 26B4 15C4
MB_A<12..0> 14C1 MB_WE_N 14B1 21B8 22B8 MC_WDQS0 15B8 23B4 24B4 MD_RDQS2 25C4 26C4 15C4
MB_BA<2..0> 14C1 21B8 22B8 MB_ZQ_BOT 22A5 MC_WDQS1 15C8 23B4 24B4 MD_RDQS3 25C4 26C4 15D4
MB_CAS_N 14B1 21B8 22B8 MB_ZQ_TOP 21A5 MC_WDQS2 15C8 23C4 24C4 MD_VREF0 15A3
MB_CKE 14B1 21B8 22B8 MC_A<11..0> 23C8 24C8 15C5 MC_WDQS3 15D8 23C4 24C4 MD_VREF1 15A4
MB_CLK0_DN 14C1 21C8 MC_A<12..0> 15C5 MC_WE_N 15B5 23B8 24B8 MD_WDQS0 15B4 25B4 26B4
MB_CLK0_DP 14C1 21D8 MC_BA<2..0> 15C5 23B8 24B8 MC_ZQ_BOT 24B5 MD_WDQS1 15C4 25B4 26B4
MB_CLK1_DN 14C1 22C8 MC_CAS_N 15B5 23B8 24B8 MC_ZQ_TOP 23B5 MD_WDQS2 15C4 25C4 26C4
MB_CLK1_DP 14C1 22D8 MC_CKE 15C5 23B8 24B8 MD_A<11..0> 25C8 26C8 15C1 MD_WDQS3 15D4 25C4 26C4
MB_CS0_N 14B1 21B8 MC_CLK0_DN 15C5 23C8 MD_A<12..0> 15C1 MD_WE_N 15B1 25B8 26B8
MB_CS1_N 14B1 21B1 22B8 MC_CLK0_DP 15C5 23D8 MD_BA<2..0> 15C1 25C8 26B8 MD_ZQ_BOT 26B5
MB_DM0 14B4 21B4 22B4 MC_CLK1_DN 15C5 24C8 MD_CAS_N 15B1 25B8 26B8 MD_ZQ_TOP 25B5
MB_DM1 14C4 21B4 22B4 MC_CLK1_DP 15D5 24D8 MD_CKE 15C1 25B8 26B8 MEMPORT1_DN 35C3 46B4
MB_DM2 14C4 21C4 22C4 MC_CS0_N 15B5 23B8 MD_CLK0_DN 15C1 25C8 MEMPORT1_DN_CM 46B2
MB_DM3 14D4 21C4 22C4 MC_CS1_N 15B5 23B1 24B8 MD_CLK0_DP 15C1 25D8 MEMPORT1_DP 35C3 46B4
MB_DQ0 14B4 21B5 22B5 MC_DM0 15B8 23B4 24B4 MD_CLK1_DN 15C1 26C8 MEMPORT1_DP_CM 46B2
MB_DQ1 14B4 21B5 22B5 MC_DM1 15C8 23B4 24B4 MD_CLK1_DP 15D1 26D8 MEMPORT2_DN 35B3 46C4
MB_DQ2 14B4 21B5 22B5 MC_DM2 15C8 23C4 24C4 MD_CS0_N 15B1 25B8 MEMPORT2_DN_CM 46C2
MB_DQ3 14B4 21B5 22B5 MC_DM3 15D8 23C4 24C4 MD_CS1_N 15B1 25B1 26B8 MEMPORT2_DP 35B3 46C4
MB_DQ4 14B4 21B5 22B5 MC_DQ0 15B8 23B4 24B4 MD_DM0 15B4 25B4 26B4 MEMPORT2_DP_CM 46C2
MB_DQ5 14B4 21B5 22B5 MC_DQ1 15B8 23B4 24B4 MD_DM1 15C4 25B4 26B4 MEMPORT3_DN 35B3 60B6
MB_DQ6 14B4 21B5 22B5 MC_DQ2 15B8 23B4 24B4 MD_DM2 15C4 25C4 26C4 MEMPORT3_DN_ARGON 49A8 60D3
MB_DQ7 14B4 21B5 22B5 MC_DQ3 15B8 23B4 24B4 MD_DM3 15D4 25C4 26C4 MEMPORT3_DN_ARGONYETI 60B3 60D6
MB_DQ8 14C4 21B5 22B5 MC_DQ4 15B8 23B4 24B4 MD_DQ0 15B4 25B4 26B5 MEMPORT3_DN_ARGON_CM 49A6
MB_DQ9 14C4 21B5 22B5 MC_DQ5 15B8 23B4 24B4 MD_DQ1 15B4 25B4 26B5 MEMPORT3_DN_FLASH 60A4
MB_DQ10 14C4 21B5 22B5 MC_DQ6 15B8 23B4 24B4 MD_DQ2 15B4 25B4 26B5 MEMPORT3_DN_YETI 60C4
MB_DQ11 14C4 21B5 22B5 MC_DQ7 15B8 23B4 24C4 MD_DQ3 15B4 25B4 26B5 MEMPORT3_DP 35B3 60B6
MB_DQ12 14C4 21B5 22B5 MC_DQ8 15C8 23B4 24B4 MD_DQ4 15B4 25B4 26B5 MEMPORT3_DP_ARGON 49A8 60D3
MB_DQ13 14C4 21B5 22B5 MC_DQ9 15C8 23B4 24B4 MD_DQ5 15B4 25B4 26B5 MEMPORT3_DP_ARGONYETI 60B3 60D6
MB_DQ14 14C4 21B5 22B5 MC_DQ10 15C8 23B4 24B4 MD_DQ6 15B4 25B4 26C5 MEMPORT3_DP_ARGON_CM 49A6
MB_DQ15 14C4 21B5 22B5 MC_DQ11 15C8 23B4 24B4 MD_DQ7 15B4 25B4 26C5 MEMPORT3_DP_FLASH 60A4
MB_DQ16 14C4 21C5 22C5 MC_DQ12 15C8 23B4 24B4 MD_DQ8 15C4 25B4 26B5 MEMPORT3_DP_YETI 60C4
MB_DQ17 14C4 21C5 22C5 MC_DQ13 15C8 23B4 24B4 MD_DQ9 15C4 25B4 26B5 MEM_A_VREF0 20A6 19B8 20B8
MB_DQ18 14C4 21C5 22C5 MC_DQ14 15C8 23C4 24B4 MD_DQ10 15C4 25B4 26B5 MEM_A_VREF1 19A6 19B8 20B8
MB_DQ19 14C4 21C5 22C5 MC_DQ15 15C8 23C4 24B4 MD_DQ11 15C4 25B4 26B5 MEM_B_VREF0 22A6 21B8 22B8
MB_DQ20 14C4 21C5 22C5 MC_DQ16 15C8 23C4 24C4 MD_DQ12 15C4 25C4 26B5 MEM_B_VREF1 21A6 21B8 22B8
MB_DQ21 14C4 21C5 22C5 MC_DQ17 15C8 23C4 24C4 MD_DQ13 15C4 25C4 26B5 MEM_CALA 13B7
MB_DQ22 14C4 21C5 22C5 MC_DQ18 15C8 23C4 24C4 MD_DQ14 15C4 25C4 26B5 MEM_CALB 13B7
MB_DQ23 14C4 21C5 22D5 MC_DQ19 15C8 23C4 24C4 MD_DQ15 15C4 25C4 26B5 MEM_C_VREF0 24A6 23B8 24B7
MB_DQ24 14D4 21C5 22C5 MC_DQ20 15C8 23C4 24C4 MD_DQ16 15C4 25C4 26C5 MEM_C_VREF1 23A6 23B8 24B7
MB_DQ25 14D4 21C5 22C5 MC_DQ21 15C8 23C4 24C4 MD_DQ17 15C4 25C4 26C5 MEM_D_VREF0 26A7 25B7 26B8
MB_DQ26 14D4 21C5 22C5 MC_DQ22 15C8 23C4 24D4 MD_DQ18 15C4 25C4 26C5 MEM_D_VREF1 25A6 25B7 26B8
MB_DQ27 14D4 21C5 22C5 MC_DQ23 15D8 23C4 24D4 MD_DQ19 15C4 25C4 26C5 MEM_RST 13B3 19C8 20C8 21C8
MB_DQ28 14D4 21C5 22C5 MC_DQ24 15D8 23C4 24C4 MD_DQ20 15C4 25C4 26C5 22C8 23C8 24C8 25C8 26C8
CONFIDENTIAL
MEM_SCAN_BOT_EN 12A1 20B8 22B8 24B8 PEX_SB_GPU_L0_DP 33C1 13D8 58A8 SMC_DBG_EN 58C6 34C6 VREG_1P8STBY_IN 56B8
26B8 PEX_SB_GPU_L0_DP_C 33C3 SMC_DBG_RXD 60C5 34D8 VREG_3P3_EN 34C3 56D8
MEM_SCAN_BOT_EN_BUFF 13B3 12A4 PEX_SB_GPU_L1_DN 33D1 13D8 58A8 SMC_DBG_RXD_R 58D4 60C8 VREG_3P3_EN_R 56D6
MEM_SCAN_EN 12D1 19B8 20B8 21B8 PEX_SB_GPU_L1_DN_C 33C3 SMC_DBG_TXD 34C3 58C6 VREG_CPU1_VCC 52B7
22B8 23B8 24B8 25B8 26B8 PEX_SB_GPU_L1_DP 33D1 13D8 58A8 SMC_DBG_TXD_R 34C4 VREG_CPU2_VCC 52C7
MEM_SCAN_EN_BUFF 13B3 12D4 PEX_SB_GPU_L1_DP_C 33C3 SMC_PWM0 34B3 28B8 VREG_CPU3_VCC 52D7
MEM_SCAN_TOP_EN 12B1 19B8 21B8 23B8 PIX_DATA<14..0> 13C3 28D6 SMC_PWM1 34B4 VREG_CPUPLL_ADJUST 56A2
25B8 PSU_V12P0_EN 34B3 49C5 SMC_RST_N 27D3 34D6 47A5 58D3 VREG_CPUPLL_IN 56A4
MEM_SCAN_TOP_EN_BUFF 13B3 12B4 PSU_V12P0_EN_R 49C2 SMC_RST_N_R 27D4 VREG_CPUPLL_R 56A1
MII_COL 39B7 40B6 36C7 PWRSW_N 34C3 49B8 SMC_RST_XDK_N 58C5 VREG_CPU_BG1 52A5
MII_CRS 39B7 40B6 36C7 PWRSW_N_R 49B7 SPDIF_R 36C4 VREG_CPU_BG2 52B5
MII_MDC_CLK_OUT 36D2 39C8 40B6 SATA_CLK_DN 27B1 33D6 SPI_CLK 58D6 35D6 VREG_CPU_BG3 52C5
MII_MDC_CLK_OUT_R 36D4 SATA_CLK_DN_R 27C4 SPI_MISO 35D2 58D8 VREG_CPU_BST1 52B6
MII_MDIO 36C7 39B8 40B6 SATA_CLK_DP 27C1 33D6 SPI_MISO_R 35D4 VREG_CPU_BST1_R 52A5
MII_RXD0 39C7 40B7 36C7 SATA_CLK_DP_R 27C4 SPI_MOSI 58D6 35D6 VREG_CPU_BST2 52C6
MII_RXD1 39C7 40B6 36C7 SATA_CLK_REF 27B1 33D6 SPI_SS_N 58D8 35D6 VREG_CPU_BST2_R 52C5
MII_RXD2 39C7 40B6 36C7 SATA_CLK_REF_R 27C4 STBY_CLK 27A1 34D6 VREG_CPU_BST3 52D6
MII_RXD3 39C7 40B6 36C7 SATA_CLK_SEL 33D6 STBY_CLK_R 27C4 VREG_CPU_BST3_R 52D5
MII_RXDV 39C7 40B6 36C7 SATA_RBIAS 36B6 TDR_DIFF_XDK1_DN 62A7 VREG_CPU_COMP 51A5
MII_RXER 39C7 40B6 36C7 SB_GPIO<0..15> 33B1 33B5 TDR_DIFF_XDK1_DP 62A7 VREG_CPU_COMP_R 51A6
MII_RX_CLK 39C7 40C6 36C8 SB_GPIO_RESERVED6 33B3 TDR_DIFF_XDK2_DP 62B7 VREG_CPU_CSCOMP 51C5
MII_RX_CLK_R 36C6 SB_GPIO_RESERVED16 33B3 TDR_DIFF_XDK3_DN 62C7 VREG_CPU_CSCOMP_R 51B6
MII_TXD0 36C3 39B7 40B6 SB_GPIO_RESERVED17 33B3 TDR_DIFF_XDK3_DP 62D7 VREG_CPU_CSREF 51A6
MII_TXD1 36C3 39B7 40B6 SB_GPIO_RESERVED18 33B3 TDR_DIIFF_XDK2_DN 62B7 VREG_CPU_CSREF_R 51A5
MII_TXD2 36C3 39B7 40B6 SB_GPIO_RESERVED19 33B3 TDR_SINGLE_XDK1 62C2 VREG_CPU_CSSUM 51B6
MII_TXD3 36C3 39C7 40B6 SB_GPIO_RESERVED20 33B3 TDR_SINGLE_XDK2 62D2 VREG_CPU_DELAY 51B3
MII_TXEN 36C3 39C7 40B6 SB_GPIO_RESERVED21 33B3 TDR_SINGLE_XDK3 62B2 VREG_CPU_DRVH1 52A5
MII_TX_CLK 39C7 40B6 36D8 SB_GPIO_RESERVED22 33B3 TEMP_RSET 28B6 VREG_CPU_DRVH2 52B5
MII_TX_CLK_R 36D6 SB_GPIO_RESERVED23 33B3 TILTSW_N 43B6 34B3 VREG_CPU_DRVH3 52D5
ODD_RX_DN 48A8 36B7 SB_GPIO_RESERVED24 33B3 TILTSW_N_R 43B7 VREG_CPU_DRV_EN 51B1 52D8
ODD_RX_DN_C 48A7 SB_GPIO_RESERVED25 33B3 TRAY_OPEN 34D8 48A1 VREG_CPU_EN 34B3 51D7
ODD_RX_DP 48A8 36B7 SB_GPIO_RESERVED26 33B3 TRAY_OPEN_R 34C6 VREG_CPU_FB 51A6
ODD_RX_DP_C 48A7 SB_GPIO_RESERVED27 33B3 TRAY_STATUS 48A4 34C6 VREG_CPU_FBRTN 51B5
ODD_TX_DN 36B3 48A8 SB_GPIO_RESERVED28 33B3 TRAY_STATUS_R 48A3 VREG_CPU_PHASE1 52A1 51C8
ODD_TX_DN_C 48A7 SB_GPIO_RESERVED29 33C3 USBPORTA2_DN 35C6 VREG_CPU_PHASE1_R 51C5
ODD_TX_DP 36B3 48B8 SB_GPIO_RESERVED30 33C3 USBPORTA2_DP 35C6 VREG_CPU_PHASE2 52C1 51C8
ODD_TX_DP_C 48B7 SB_GPIO_RESERVED31 33C3 USBPORTA3_DN 35C6 VREG_CPU_PHASE2_R 51C5
PCIEX_CLK_DN 27C1 33C6 SB_MAIN_PWRGD 34B1 34C6 USBPORTA3_DP 35C6 VREG_CPU_PHASE3 52D1 51C8
PCIEX_CLK_DN_R 27C4 SB_MAIN_PWRGD_R 34B4 VID_DACA_DN 28D4 VREG_CPU_PHASE3_R 51C5
PCIEX_CLK_DP 27C1 33C6 SB_RST_N 34B3 34C6 VID_DACA_DP 28D3 44D8 VREG_CPU_PWM1 51B3 52A7
PCIEX_CLK_DP_R 27C4 SB_SPDIF_OUT 36B1 28C6 VID_DACA_OUT 44D5 44C4 VREG_CPU_PWM2 51C3 52B7
PCIEX_INT 33B3 SB_TCLK 33A5 VID_DACB_DN 28D4 VREG_CPU_PWM3 51C3 52D7
PEX_GPU_SB_L0_DN 13C1 33C7 58A5 SB_TDI 33A5 VID_DACB_DP 28D3 44C8 VREG_CPU_PWRGD 51C2 34C1
PEX_GPU_SB_L0_DN_C 13D4 SB_TDO 33A5 VID_DACB_OUT 44C6 44C4 VREG_CPU_RAMPADJ 51C5
PEX_GPU_SB_L0_DP 13D1 33C7 58A5 SB_TMS 33A5 VID_DACC_DN 28D4 VREG_CPU_RAMPADJ_R 51D5
PEX_GPU_SB_L0_DP_C 13D4 SB_TRST 33A5 VID_DACC_DP 28D3 44C8 VREG_CPU_RT 51B3
PEX_GPU_SB_L1_DN 13D1 33C7 58A5 SB_USB_RBIAS 35B6 VID_DACC_OUT 44C6 44C4 VREG_CPU_SW1_R 52A2
PEX_GPU_SB_L1_DN_C 13D4 SCART_RGB 33B2 44A6 VID_DACD_DN 28D4 VREG_CPU_SW2_R 52B2
PEX_GPU_SB_L1_DP 13D1 33C7 58A5 SCART_RGB_OUT 44A3 VID_DACD_DP 28D3 44B8 VREG_CPU_SW3_R 52C2
PEX_GPU_SB_L1_DP_C 13D4 SCART_RGB_OUT_R 44A4 VID_DACD_OUT 44B6 44C4 VREG_CPU_SW4 51C5
PEX_ICAL 13C8 SCART_RGB_R 44A5 VID_HSYNC_OUT 44A4 44C4 VREG_CPU_VCC 51D6
PEX_NCAL 13D7 SMB_CLK 34B8 58C7 27B6 VID_HSYNC_OUT_R 28C3 44A7 VREG_CPU_VID<5..0> 50C2 51C2
PEX_PCAL 13D8 SMB_CLK_R 58C6 VID_VSYNC_OUT 44A6 44C4 VREG_EFUSE_EN 4D2 56C6
PEX_RBIAS0 33C6 SMB_DATA 27B7 34B8 58C3 VID_VSYNC_OUT_R 28C3 44A8 VREG_EFUSE_EN_C1 56C4
PEX_RBIAS1 33C6 SMB_DATA_R 58C5 VREG_1P8STBY_ADJ 56A7 VREG_EFUSE_EN_C2 56D3
PEX_SB_GPU_L0_DN 33C1 13D8 58A8 SMC_CPU_CHKSTOP_DETECT 34C8 58A1 VREG_1P8STBY_D1 56B8 VREG_EFUSE_EN_R 56C4
PEX_SB_GPU_L0_DN_C 33C3 SMC_CPU_CHKSTOP_DETECT_B 58A2 VREG_1P8STBY_D2 56B7 VREG_GPUPCIE_IN 56C4
CONFIDENTIAL
VREG_GPU_5VREF 53C3 53C6 VREG_V5P0_BST2 55C6 V_CMPAVSS_SATA 38B6
VREG_GPU_COMP 53C6 VREG_V5P0_COMP2 55B6 V_CPU_CORE_HF_GNDA_PLL 6C5
VREG_GPU_COMP_C 53C8 VREG_V5P0_COMP2_R 55B7 V_CPU_CORE_HF_VDDA_PLL 6C5
VREG_GPU_COMP_R 53C7 VREG_V5P0_CSL2 55C6 V_CPU_CORE_IF_GNDA_PLL 6C5
VREG_GPU_CPGD 53B6 VREG_V5P0_CSL2_R 55C6 V_CPU_CORE_IF_VDDA_PLL 6C5
VREG_GPU_CS1 53C6 VREG_V5P0_DH2 55C6 V_CPU_FSB_HF_GNDA_PLL 6C5
VREG_GPU_CS2 53C6 VREG_V5P0_DL2 55C6 V_CPU_FSB_HF_VDDA_PLL 6C5
VREG_GPU_CSREF 53C6 VREG_V5P0_EN 34B3 55A8 V_CPU_FSB_IF_GNDA_PLL 6B5
VREG_GPU_CSREF_R 53A8 VREG_V5P0_EN_R 55A6 V_CPU_FSB_IF_VDDA_PLL 6B5
VREG_GPU_EN_N 34C3 53B3 VREG_V5P0_FB2 55B8 V_CPU_GNDA_RNG 6B5
VREG_GPU_EN_N_R 53B1 VREG_V5P0_FB2_C 55B8 V_CPU_VDDA_RNG 6B5
VREG_GPU_GH1 53A1 54C7 VREG_V5P0_FB2_R 55B8 V_ENET 39A3 39B8 39B8 39D5
VREG_GPU_GH1_R 53A3 VREG_V5P0_SEL 34B3 47B8 40B3 40C7 45B6
VREG_GPU_GH2 53A1 54D7 VREG_V5P0_SEL_B1 47B7 V_EXPPORT 45D2 45B6 45D7
VREG_GPU_GH2_R 53A3 VREG_V5P0_SEL_B2 47B6 V_FAN1 43C3
VREG_GPU_GL1 53A1 54B7 VREG_V5P0_SEL_C 47B7 V_GAMEPORT1 46B7
VREG_GPU_GL1_R 53A3 VREG_V5P0_SEL_NGATE 47B6 V_GAMEPORT2 46D7
VREG_GPU_GL2 53A1 54C7 VREG_V5P0_SEL_PGATE 47B6 V_HANA_VAA_DAC33M 30C7
VREG_GPU_GL2_R 53A3 VREG_V5P0_SS2 55B5 V_HANA_VAA_RTS33S 30D6
VREG_GPU_ILIM 53C4 VREG_V5P0_SW2 55C6 V_HANA_VAA_XTAL_33S 30C7
VREG_GPU_NPNC 53C2 VREG_V5P0_SW2_S 55C7 V_HANA_VDD18S 31D3
VREG_GPU_PH1_R 54B3 VREG_V5P0_VMEM_PWRGD 34A8 55A7 V_HANA_VDDIO_33S_AVCC 31C7
VREG_GPU_PH2_R 54C3 VREG_VCS_COMP 57B6 V_HANA_VDDIO_33S_PVCC0 31B6
VREG_GPU_PHASE1 53D1 54B2 53B8 VREG_VCS_COMP_C 57B6 V_HDD 48B4
VREG_GPU_PHASE1_C 53D2 VREG_VCS_COMP_R 57A6 V_IR 43A3
VREG_GPU_PHASE2 54D2 53B8 VREG_VCS_CPUCORE_R 57B8 V_MEMPORT1 46D1 60C1
VREG_GPU_PWRGD 53A1 34D1 VREG_VCS_FB 57B5 V_MEMPORT2 46D2
VREG_GPU_ROSC 53B6 VREG_VCS_FB_COMP 57B3 V_PVDDA 16C4
VREG_GPU_SEN 53C6 VREG_VCS_FB_R 57B3 V_PVDDA_ED 16C5
VREG_GPU_VCCH 53C4 VREG_VCS_HDRV 57C4 V_PVDDA_FSB 16B5
VREG_GPU_VCCL 53C6 VREG_VCS_LDRV 57C4 V_PVDDA_MEM 16C5
VREG_GPU_VDRP 53C6 VREG_VCS_LTO 57C8 V_V3P3TOV1P8 54A6
VREG_GPU_VFB 53C6 VREG_VCS_NC 57B4 V_VDD18_USB 37C6
VREG_GPU_VFB_R 53D8 VREG_VCS_NC1 57B4 V_VDD33_USB 37B5
VREG_GPU_VFFB 53D8 62C5 VREG_VCS_RT 57C5 V_VDD_PEX_FB 38D6
VREG_GPU_VID0 53C3 62C5 VREG_VCS_SS_SD_N 57C7 V_VDD_SATA 38B6
VREG_GPU_VID1 53D3 62C5 VREG_VCS_VOUT_L 57C3 V_VREG_CPU 50B4 51D6 51D7 52D5
VREG_GPU_VID2 53D4 62C5 VREG_VCS_VP 57C5 52D8
VREG_GPU_VID3 53D4 62C5 VREG_VCS_VREF 57C5 V_VREG_GPU 50B1 53D4 53D7 54D7
VREG_GPU_VID4 53D4 62C5 VREG_VDD_PEX_ADJ 56A7 V_VREG_V1P8V5P0 55D4 32D4
VREG_PCIEX_ADJUST 56B3 VREG_VDD_PEX_R 56A5 V_VREG_VCS 57D2
VREG_PCIEX_R 56B1 VREG_V_CPUCORE_S 51A7 V_XPOD 48B3
VREG_V1P8_BST1 55C4 VREG_V_MEM_S_0 55B1 V_YETI 60C3
VREG_V1P8_COMP1 55B4 V_AVDD0_SATA 38B6 WSS_CNTL0 33B2 44B6
VREG_V1P8_COMP1_R 55B3 V_AVDD1_SATA 38C6 WSS_CNTL1 33B2 44B6
VREG_V1P8_CSL1 55C4 V_AVDD_PEX 38D6 WSS_CNTL_B 44B4
VREG_V1P8_CSL1_R 55C4 V_AVDD_USB 37C6 WSS_CNTL_E 44B5
VREG_V1P8_DH1 55C4 V_AVIP 44D3 29D3 WSS_CNTL_OUT 44B3
VREG_V1P8_DL1 55C4 V_AVSS0_SATA 38B6 WSS_CNTL_OUT_R 44B4
VREG_V1P8_EN 34B3 55A3 V_AVSS1_SATA 38C6 XUSB_CLK_BYP 33C6
VREG_V1P8_FB1 55A1 62B5 V_AVSS_PEX 38D6 XUSB_CLK_SEL 33C6
VREG_V1P8_FB1_C 55B1 V_AVSS_USB 37C6
VREG_V1P8_FB1_R 55A1 V_CMPAVDD18_USB 37C6
VREG_V1P8_SS1 55B4 V_CMPAVDD33_USB 37A7 37C2
VREG_V1P8_SW1 55C4 V_CMPAVDD_SATA 38B6
VREG_V1P8_SW1_S 55C3 V_CMPAVSS18_USB 37C6
VREG_V3P3_ADJ 56D5 V_CMPAVSS33_USB 37C6
CONFIDENTIAL
Title: Cref Part Report C1N6 CAPN_402 [40A5] C2C2 CAPN_402 [33D2] C2P28 CAPN_402 [38D3]
Design: falcon C1N7 CAPN_805 [40C4] C2C3 CAPN_402 [33C2] C2P29 CAPN_402 [38D1]
Date: May 8 12:04:43 2007 C1N8 CAPN_805 [40C5] C2C4 CAPN_402 [33C2] C2P30 CAPN_402 [38D2]
C1N9 CAPN_402 [39A5] C2C5 CAPN_805 [56A8] C2P31 CAPN_402 [38C6]
C1N10 CAPN_402 [39A4] C2C6 CAPN_402 [56A7] C2P32 CAPN_402 [38C7]
C1A2 CAPN_402 [45B3] C1N11 CAPN_402 [39A4] C2D1 CAPN_402 [25A2] C2P33 CAPN_402 [38D1]
C1A3 CAPN_402 [45D4] C1N12 CAPN_402 [32C6] C2D2 CAPN_402 [25A3] C2P34 CAPN_603 [37A7]
C1A4 CAPN_402 [45B5] C1N13 CAPN_402 [32B5] C2D3 CAPN_805 [23A4] C2P35 CAPN_402 [37A7]
C1A5 CAP_P_RDL [39A7] C1N14 CAPN_402 [40C4] C2D4 CAPN_402 [25A1] C2P37 CAPN_402 [37B2]
C1B1 CAPN_805 [39A6] C1P1 CAPN_402 [38A6] C2D5 CAPN_402 [12A3] C2P38 CAPN_402 [37B2]
C1B2 CAPN_402 [32B5] C1P2 CAPN_805 [38B8] C2D6 CAP_P_RDL [54A4] C2P39 CAPN_603 [38C2]
C1B3 CAPN_402 [32B5] C1P3 CAPN_603 [38B7] C2E1 CAPN_402 [23A3] C2P40 CAPN_402 [35B6]
C1B4 CAPN_402 [27A5] C1P4 CAPN_402 [38B7] C2E2 CAPN_805 [25A4] C2P41 CAPN_402 [37B7]
C1C1 CAPN_402 [32B5] C1P5 CAPN_603 [38B7] C2E3 CAPN_402 [23A1] C2P42 CAPN_402 [37C6]
C1C2 CAPN_402 [33A3] C1P6 CAPN_402 [38B7] C2E4 CAPN_402 [12D3] C2P43 CAPN_402 [37C6]
C1C3 CAPN_402 [48A7] C1P7 CAPN_805 [38B8] C2E5 CAPN_402 [42C5] C2P44 CAPN_402 [37A7]
C1C4 CAPN_402 [48A7] C1P8 CAPN_805 [38A7] C2E6 CAPN_805 [42C5] C2P45 CAPN_805 [37B7]
C1C5 CAPN_402 [48A7] C1P9 CAPN_402 [27A7] C2E8 CAPN_805 [23A3] C2P46 CAPN_603 [37C7]
C1C6 CAPN_402 [48B7] C1P10 CAPN_603 [38A7] C2F1 CAP_P_RDL [55B2] C2P47 CAPN_603 [37C7]
C1C7 CAPN_402 [32C6] C1P11 CAPN_402 [38A7] C2F2 CAPN_402 [32D5] C2P48 CAPN_603 [37A7]
C1C8 CAPN_402 [32D4] C1P13 CAPN_402 [28A5] C2F3 CAP_P_RDL [55B2] C2P50 CAPN_402 [28D7]
C1C9 CAPN_402 [36B6] C1R1 CAPN_402 [48A4] C2G1 CAPN_402 [32C5] C2P51 CAPN_603 [34D6]
C1C10 CAP_P_RDL [48A6] C1R2 CAPN_402 [58C7] C2G2 CAP_P_RDL [46B2] C2P52 CAPN_402 [38A7]
C1C11 CAP_P_RDL [48A5] C1R3 CAPN_402 [47B5] C2G3 CAPN_805 [46B2] C2R1 CAPN_402 [28D8]
C1C12 CAPN_402 [32B5] C1R4 CAPN_402 [48A1] C2M2 CAPN_402 [44A1] C2R2 CAPN_402 [28D8]
C1C13 CAPN_603 [48A5] C1T1 CAPN_603 [48B3] C2M3 CAPN_402 [44A2] C2R3 CAPN_805 [37B8]
C1C14 CAPN_603 [48A6] C1T2 CAPN_402 [48B3] C2M4 CAPN_402 [44A3] C2R4 CAPN_603 [54A4]
C1C15 CAPN_402 [32B7] C1T3 CAPN_402 [48B3] C2M5 CAPN_805 [44D4] C2R5 CAPN_805 [37C8]
C1D1 CAPN_603 [48A5] C1T4 CAPN_603 [48B3] C2N1 CAPN_402 [37A1] C2R6 CAPN_805 [37A8]
C1D2 CAPN_805 [38C2] C1T5 CAPN_603 [48B4] C2N3 CAPN_402 [44A1] C2R7 CAPN_402 [26A3]
C1D3 CAPN_402 [48A5] C1T6 CAPN_805 [60B2] C2N4 CAPN_402 [60C6] C2R8 CAPN_402 [26A1]
C1D4 CAPN_603 [48A6] C1U1 CAPN_805 [56D6] C2P1 CAPN_805 [38A2] C2R9 CAPN_402 [23A7]
C1D6 CAPN_603 [48A5] C1U2 CAPN_805 [46A3] C2P2 CAPN_402 [37B6] C2R10 CAPN_402 [26A1]
C1D7 CAPN_402 [58D6] C2A1 CAPN_402 [44D3] C2P3 CAPN_402 [37B6] C2R11 CAPN_402 [42C4]
C1D8 CAPN_402 [32C5] C2A3 CAPN_402 [44A2] C2P4 CAPN_603 [38A2] C2R12 CAPN_402 [12C3]
C1D9 CAP_P_RDL [48A6] C2A4 CAP_P_RDL [45D4] C2P5 CAPN_402 [37A1] C2R13 CAPN_402 [26A5]
C1D10 CAPN_402 [32B5] C2A6 CAPN_402 [44D5] C2P6 CAPN_402 [37A6] C2T1 CAPN_402 [24A3]
C1D11 CAP_P_RDL [47B5] C2A7 CAPN_1206 [41D6] C2P7 CAPN_402 [27A8] C2T2 CAPN_402 [25A7]
C1E1 CAPN_402 [48B7] C2A8 CAPN_402 [44B4] C2P8 CAPN_805 [37A8] C2T3 CAPN_402 [24A1]
C1E2 CAPN_402 [48C7] C2A9 CAPN_402 [29D3] C2P9 CAPN_402 [38B2] C2T4 CAPN_402 [32B6]
C1E3 CAPN_402 [48D7] C2B1 CAPN_805 [41C7] C2P10 CAPN_805 [38C7] C2T5 CAPN_603 [54A5]
C1E4 CAPN_402 [48D7] C2B2 CAPN_402 [41B2] C2P11 CAPN_402 [38B2] C2T6 CAPN_402 [26A4]
C1E5 CAP_P_RDL [48B4] C2B3 CAPN_402 [41C2] C2P12 CAPN_402 [38B3] C2T7 CAPN_805 [26B4]
C1F1 CAPN_402 [32C4] C2B4 CAPN_402 [41C5] C2P13 CAPN_402 [38B3] C2T8 CAPN_402 [60A2]
C1F2 CAPN_402 [32B5] C2B5 CAPN_402 [41C7] C2P14 CAPN_402 [38B2] C2T9 CAPN_402 [60B2]
C1F3 CAP_P_RDL [56D4] C2B6 CAPN_402 [41C7] C2P15 CAPN_402 [38D2] C2T10 CAPN_402 [60B3]
C1F4 CAP_P_RDL [46A2] C2B7 CAPN_603 [41D6] C2P16 CAPN_402 [38D3] C2V1 CAPN_805 [43A3]
C1F5 CAPN_603 [56D5] C2B8 CAPN_805 [41C5] C2P17 CAPN_402 [38D2] C2V2 CAPN_402 [43A3]
C1F6 CAPN_603 [46A2] C2B9 CAP_P_1206 [41B5] C2P18 CAPN_402 [33C6] C3A1 CAPN_402 [44C6]
C1G1 CAPN_402 [32B5] C2B10 CAP_P_1206 [41D5] C2P20 CAPN_603 [38C2] C3A2 CAPN_402 [44C6]
C1M1 CAPN_402 [45B4] C2B11 CAPN_805 [41C7] C2P21 CAPN_402 [38D3] C3A3 CAPN_402 [44D6]
C1M2 CAPN_805 [45D4] C2B12 CAPN_402 [58C4] C2P22 CAPN_402 [38D4] C3A4 CAPN_402 [44C7]
C1N1 CAPN_402 [39A6] C2B14 CAPN_402 [27A5] C2P23 CAPN_402 [37B1] C3A5 CAPN_402 [44C7]
C1N2 CAPN_402 [39A4] C2B15 CAPN_603 [58C4] C2P24 CAPN_402 [37B1] C3A6 CAPN_402 [44D7]
C1N3 CAPN_402 [39A5] C2B16 CAPN_402 [33A3] C2P25 CAPN_402 [33C7] C3A7 CAPN_402 [44B7]
C1N4 CAPN_402 [39A5] C2B17 CAPN_402 [27A4] C2P26 CAPN_402 [38D7] C3A8 CAPN_402 [44B6]
C1N5 CAPN_402 [39A5] C2C1 CAPN_402 [33D2] C2P27 CAPN_603 [38D7] C3A9 CAPN_603 [43C3]
CONFIDENTIAL
C3B1 CAPN_402 [27B2] C3U3 CAPN_402 [32B6] C4N21 CAPN_402 [31C1] C4R28 CAPN_402 [18D5]
C3B2 CAPN_402 [27A2] C3U4 CAPN_402 [26A4] C4N22 CAPN_402 [31C2] C4R29 CAPN_805 [18D1]
C3B4 CAPN_402 [27A1] C3U5 CAPN_603 [55B1] C4N23 CAPN_402 [30C7] C4R30 CAPN_805 [18C1]
C3B6 CAPN_402 [27D8] C3V5 CAPN_402 [46B2] C4N24 CAPN_805 [30C7] C4R31 CAPN_402 [15A2]
C3B7 CAPN_402 [27D8] C3V6 CAPN_603 [55D2] C4N25 CAPN_805 [30B7] C4R32 CAPN_402 [15A5]
C3B8 CAPN_402 [58B5] C3V7 CAPN_603 [55C4] C4N26 CAPN_402 [30A2] C4R33 CAPN_402 [12A6]
C3B9 CAPN_603 [58B4] C3V8 CAPN_402 [55A6] C4N27 CAPN_402 [30A3] C4R34 CAPN_402 [18B7]
C3B12 CAPN_402 [27A2] C4A1 CAPN_402 [32C5] C4N28 CAPN_402 [30A7] C4R35 CAPN_402 [18B6]
C3C1 CAPN_805 [56A5] C4B3 CAPN_402 [28A6] C4N29 CAPN_402 [30C7] C4R36 CAPN_402 [18B7]
C3C2 CAPN_805 [13A2] C4B4 CAPN_402 [28C2] C4N30 CAPN_402 [31C3] C4R37 CAPN_402 [18C8]
C3C5 CAPN_805 [23A4] C4B10 CAPN_402 [28B2] C4N31 CAPN_402 [30A5] C4R38 CAPN_402 [15A6]
C3C6 CAPN_805 [30C3] C4B11 CAPN_402 [28B2] C4N32 CAPN_402 [31C3] C4R39 CAPN_402 [18B8]
C3D1 CAPN_402 [25A2] C4B12 CAPN_402 [28C2] C4N33 CAPN_402 [31C2] C4R40 CAPN_402 [18B5]
C3D2 CAPN_402 [25A2] C4B13 CAPN_402 [27D6] C4N34 CAPN_402 [30A4] C4R41 CAPN_402 [18B6]
C3D3 CAPN_402 [24A7] C4C6 CAPN_805 [56B4] C4N35 CAPN_402 [30D6] C4R42 CAPN_402 [18A7]
C3D4 CAPN_402 [25A2] C4D1 CAPN_402 [13D3] C4N36 CAPN_805 [30D7] C4R43 CAPN_402 [18A5]
C3D5 CAPN_402 [25A1] C4D2 CAPN_402 [13D3] C4N37 CAPN_805 [30D7] C4R44 CAPN_402 [18C5]
C3D6 CAPN_402 [25A1] C4D3 CAPN_402 [13D3] C4N40 CAPN_402 [32C7] C4R45 CAPN_402 [12A6]
C3E1 CAPN_402 [23A2] C4D4 CAPN_402 [16D6] C4N41 CAPN_402 [31C3] C4R46 CAPN_402 [18B6]
C3E2 CAPN_402 [23A2] C4D5 CAPN_402 [16D6] C4N42 CAPN_402 [30A6] C4R47 CAPN_402 [18C7]
C3E3 CAPN_402 [23A2] C4D6 CAPN_603 [16D7] C4P1 CAPN_402 [30A2] C4R48 CAPN_402 [15A5]
C3E4 CAPN_402 [26A7] C4D7 CAPN_402 [13C3] C4P2 CAPN_402 [28B7] C4R49 CAPN_402 [18A8]
C3E5 CAPN_402 [23A2] C4F1 CAPN_402 [19A1] C4P3 CAPN_805 [31D3] C4R50 CAPN_402 [15A1]
C3E6 CAPN_402 [23A1] C4F2 CAPN_402 [20A7] C4P4 CAPN_402 [31D3] C4R51 CAPN_402 [15A5]
C3E7 CAPN_402 [23A1] C4F3 CAPN_402 [19A1] C4P5 CAPN_402 [30A4] C4R54 CAPN_402 [18D4]
C3E8 CAPN_402 [26A4] C4F4 CAPN_402 [21A2] C4P6 CAPN_402 [30A4] C4R55 CAPN_402 [18C7]
C3F1 CAPN_402 [19A2] C4F5 CAPN_402 [21A2] C4P7 CAPN_402 [31C2] C4R56 CAPN_402 [18B4]
C3F3 CAPN_402 [19A3] C4F6 CAPN_402 [19A1] C4P8 CAPN_402 [30A6] C4R57 CAPN_402 [18B4]
C3F5 CAPN_402 [26A4] C4F7 CAPN_402 [19A2] C4P9 CAPN_402 [30A2] C4R58 CAPN_402 [18A4]
C3F6 CAP_P_RDL [55B2] C4F8 CAPN_402 [21A2] C4P11 CAPN_402 [30A3] C4R59 CAPN_402 [18C4]
C3G3 CAPN_402 [32C5] C4F9 CAPN_402 [19A2] C4P13 CAPN_805 [30C2] C4R60 CAPN_402 [12A5]
C3N1 CAPN_402 [32B4] C4F10 CAPN_402 [21A3] C4P14 CAPN_402 [43C4] C4R61 CAPN_402 [15A2]
C3N2 CAPN_402 [32D6] C4F11 CAPN_402 [19A2] C4R3 CAPN_805 [14A6] C4R62 CAPN_402 [18A5]
C3N3 CAPN_805 [30C2] C4F12 CAPN_805 [19A4] C4R4 CAPN_402 [16C6] C4R63 CAPN_402 [18A6]
C3N6 CAPN_402 [27A7] C4F13 CAPN_402 [32D3] C4R5 CAPN_402 [16B6] C4R64 CAPN_402 [15A3]
C3N10 CAPN_402 [28D7] C4F14 CAPN_402 [26A3] C4R6 CAPN_402 [16C6] C4R65 CAPN_402 [12A5]
C3P1 CAPN_805 [31D2] C4F15 CAPN_402 [26A3] C4R7 CAPN_402 [16B6] C4R66 CAPN_402 [15A6]
C3P3 CAPN_805 [38D8] C4G1 CAPN_402 [55B1] C4R8 CAPN_402 [16C5] C4R67 CAPN_402 [18A6]
C3P4 CAPN_402 [28D8] C4N1 CAPN_402 [32A7] C4R9 CAPN_402 [18A5] C4R68 CAPN_603 [16C7]
C3R1 CAPN_402 [26A2] C4N3 CAPN_805 [31C8] C4R10 CAPN_402 [15A7] C4R69 CAPN_805 [18C1]
C3R2 CAPN_402 [26A2] C4N4 CAPN_805 [31B7] C4R11 CAPN_402 [18D7] C4R70 CAPN_402 [12A7]
C3R3 CAPN_402 [25D4] C4N5 CAPN_402 [31C7] C4R12 CAPN_402 [15A2] C4T1 CAPN_402 [18A7]
C3R4 CAPN_402 [26A2] C4N6 CAPN_805 [31C7] C4R13 CAPN_402 [18D5] C4T2 CAPN_402 [18A6]
C3R5 CAPN_805 [15A6] C4N7 CAPN_805 [31B6] C4R14 CAPN_402 [18C8] C4T3 CAPN_402 [18A8]
C3R6 CAPN_402 [26A1] C4N8 CAPN_805 [30B7] C4R15 CAPN_402 [15A2] C4T4 CAPN_402 [18B4]
C3R7 CAPN_402 [26A2] C4N9 CAPN_402 [31C7] C4R16 CAPN_402 [18D6] C4T5 CAPN_402 [18C4]
C3R8 CAPN_402 [13A1] C4N10 CAPN_402 [31C6] C4R17 CAPN_402 [18C7] C4T6 CAPN_402 [18C4]
C3R9 CAPN_402 [13A2] C4N11 CAPN_402 [31B6] C4R18 CAPN_402 [18A8] C4T7 CAPN_402 [15A2]
C3T1 CAPN_402 [24A3] C4N12 CAPN_402 [31C6] C4R19 CAPN_402 [15A1] C4T8 CAPN_402 [18A4]
C3T2 CAPN_402 [24A2] C4N13 CAPN_402 [31C6] C4R20 CAPN_402 [18D8] C4T11 CAPN_402 [18B8]
C3T3 CAPN_402 [24A2] C4N14 CAPN_402 [31C6] C4R21 CAPN_402 [18C6] C4T12 CAPN_402 [15A5]
C3T4 CAPN_402 [24C4] C4N15 CAPN_805 [30C8] C4R22 CAPN_402 [18C5] C4T13 CAPN_402 [12A5]
C3T5 CAPN_402 [24A2] C4N16 CAPN_402 [30C7] C4R23 CAPN_402 [15A6] C4T14 CAPN_402 [15A5]
C3T6 CAPN_402 [24A1] C4N17 CAPN_402 [30A4] C4R24 CAPN_402 [18B5] C4T15 CAPN_402 [18C8]
C3T7 CAPN_402 [24A2] C4N18 CAPN_402 [30A8] C4R25 CAPN_402 [15A8] C4T16 CAPN_402 [18A7]
C3U1 CAPN_402 [20A2] C4N19 CAPN_402 [30A7] C4R26 CAPN_402 [13A1] C4T17 CAPN_805 [18C1]
C3U2 CAPN_402 [20A3] C4N20 CAPN_402 [30A7] C4R27 CAPN_402 [12A7] C4T18 CAPN_402 [18B5]
CONFIDENTIAL
C4T19 CAPN_402 [18B5] C5B6 CAPN_603 [56B6] C5U5 CAPN_402 [21A7] C6T2 CAPN_402 [10D3]
C4T20 CAPN_402 [18B7] C5B7 CAP_P_RDL [49B3] C5V1 CAPN_402 [32C6] C6T3 CAPN_402 [11B7]
C4T21 CAPN_402 [18C6] C5C3 CAPN_402 [13A3] C6B1 CAPN_402 [32C5] C6T4 CAPN_402 [11D3]
C4T22 CAPN_402 [12A6] C5C5 CAPN_805 [56B1] C6B2 CAPN_1206 [54D5] C6T6 CAPN_402 [10C5]
C4T23 CAPN_402 [18C5] C5C6 CAPN_603 [54C3] C6B3 CAP_P_RDL [50B3] C6T7 CAPN_402 [5A5]
C4T24 CAPN_402 [18B5] C5C8 CAP_P_8X8 [50A1] C6B5 CAPN_1206 [50B2] C6T9 CAPN_402 [11B7]
C4T25 CAPN_402 [18B8] C5C9 CAP_P_8X8 [50A1] C6C1 CAP_P_RDL [50A2] C6T10 CAPN_402 [10D4]
C4T26 CAPN_402 [18C6] C5D2 CAPN_805 [18D3] C6C2 CAP_P_RDL [50A2] C6T11 CAPN_402 [11C3]
C4T27 CAPN_402 [14A6] C5D3 CAPN_805 [18C2] C6C3 CAP_P_RDL [50A3] C6T12 CAPN_402 [59C5]
C4T28 CAPN_805 [15A2] C5D4 CAPN_805 [18C2] C6D1 CAPN_402 [6C7] C6T13 CAPN_402 [11C6]
C4T29 CAPN_402 [14A6] C5D5 CAPN_805 [18B2] C6D4 CAPN_603 [6C6] C6T14 CAPN_402 [11C5]
C4T30 CAPN_402 [16C6] C5D6 CAPN_805 [18B2] C6E1 CAPN_805 [18C2] C6T16 CAPN_402 [11C7]
C4T31 CAPN_402 [14A2] C5E1 CAPN_402 [14A4] C6E2 CAPN_805 [18C3] C6T17 CAPN_402 [11D4]
C4T32 CAPN_402 [14A5] C5F1 CAPN_402 [22A7] C6F1 CAPN_402 [4A2] C6T18 CAPN_402 [11C4]
C4T33 CAPN_402 [14A2] C5F2 CAPN_402 [21A1] C6F3 CAP_P_RDL [55D8] C6T19 CAPN_402 [5A5]
C4T34 CAPN_402 [14A2] C5F3 CAPN_402 [21A1] C6G2 CAPN_402 [49D6] C6T21 CAPN_402 [11A6]
C4T35 CAPN_402 [14A6] C5F4 CAPN_402 [21A1] C6G3 CAPN_402 [49C6] C6T22 CAPN_402 [11B5]
C4T36 CAPN_402 [15A4] C5F5 CAPN_402 [21A2] C6G4 CAPN_402 [49C6] C6T24 CAPN_402 [11D6]
C4T37 CAPN_402 [16C6] C5F6 CAPN_805 [21A4] C6G5 CAP_P_RDL [49D6] C6T25 CAPN_402 [10B4]
C4T38 CAPN_402 [15A1] C5F8 CAP_P_RDL [21A4] C6N1 CAPN_402 [32B7] C6T26 CAPN_402 [10A5]
C4T39 CAPN_402 [14A1] C5G1 CAPN_402 [32C3] C6N2 CAPN_1206 [50B2] C6T27 CAPN_402 [5A5]
C4T40 CAPN_402 [14A8] C5G3 CAPN_402 [32C5] C6P1 CAPN_805 [56A4] C6T31 CAPN_402 [59C4]
C4T41 CAPN_402 [14A5] C5G4 CAP_P_RDL [46D2] C6R1 CAPN_402 [56A3] C6T32 CAPN_402 [5A4]
C4T42 CAPN_402 [14A5] C5G5 CAPN_402 [32C4] C6R2 CAPN_402 [6B7] C6T33 CAPN_402 [5A4]
C4T43 CAPN_402 [14A5] C5G6 CAPN_805 [46D2] C6R3 CAPN_402 [6B7] C6T34 CAPN_402 [59C5]
C4T44 CAPN_402 [14A5] C5N1 CAPN_402 [32A7] C6R4 CAPN_603 [6B6] C6T35 CAPN_402 [59C5]
C4T45 CAPN_402 [14A7] C5N2 CAPN_402 [32B4] C6R5 CAPN_603 [6B6] C6T36 CAPN_402 [59C5]
C4T46 CAPN_402 [14A3] C5N3 CAPN_805 [56B8] C6R6 CAPN_402 [5A4] C6U1 CAPN_603 [55B8]
C4T47 CAPN_805 [14A2] C5P1 CAPN_402 [56B3] C6R7 CAPN_805 [9D3] C6U2 CAPN_603 [55D7]
C4T48 CAPN_603 [16C7] C5R1 CAPN_805 [18B3] C6R10 CAPN_805 [9C3] C6V10 CAPN_402 [49B6]
C4U1 CAPN_402 [20A1] C5R2 CAPN_805 [18B3] C6R12 CAPN_402 [11A6] C6V11 CAPN_402 [49B6]
C4U2 CAPN_402 [20A1] C5R3 CAPN_805 [18A3] C6R13 CAPN_402 [11A7] C6V15 CAPN_402 [49B7]
C4U3 CAPN_402 [22A2] C5R4 CAPN_805 [18C3] C6R14 CAPN_402 [5A6] C7B1 CAPN_402 [32D5]
C4U4 CAPN_402 [22A2] C5R5 CAPN_805 [18C3] C6R15 CAPN_402 [5A7] C7B2 CAPN_1206 [54C5]
C4U5 CAPN_402 [20A1] C5R6 CAPN_805 [18A3] C6R16 CAPN_402 [10B6] C7B3 CAP_P_RDL [50B3]
C4U6 CAPN_402 [20A2] C5R7 CAPN_402 [16C5] C6R17 CAPN_402 [10C7] C7B4 CAPN_1206 [50B1]
C4U7 CAPN_402 [22A2] C5R8 CAPN_402 [18B5] C6R18 CAPN_402 [5A6] C7C1 CAP_P_RDL [50A3]
C4U8 CAPN_402 [20A2] C5R9 CAPN_402 [18A5] C6R19 CAPN_402 [10B6] C7C2 CAP_P_RDL [50A4]
C4U9 CAPN_402 [19A7] C5R10 CAPN_402 [18C5] C6R20 CAPN_402 [10B5] C7C3 CAP_P_RDL [50A2]
C4U10 CAPN_402 [22A3] C5R11 CAPN_805 [18A3] C6R21 CAPN_402 [10A5] C7D1 CAPN_603 [6A7]
C4U11 CAPN_402 [20A2] C5R12 CAPN_402 [18C5] C6R23 CAPN_402 [10B5] C7D2 CAPN_603 [6A6]
C4U12 CAPN_402 [26A3] C5R13 CAPN_402 [16A6] C6R24 CAPN_402 [11D5] C7D3 CAPN_805 [9C5]
C4V1 CAPN_402 [55B8] C5R14 CAPN_402 [18A5] C6R25 CAPN_402 [5A6] C7D4 CAPN_805 [9C4]
C4V6 CAPN_402 [46D2] C5R15 CAPN_402 [16A6] C6R26 CAPN_402 [11C7] C7D5 CAPN_805 [9B5]
C4V7 CAPN_603 [55D3] C5R16 CAPN_402 [18C5] C6R28 CAPN_402 [10C7] C7D7 CAPN_805 [9B4]
C4V8 CAPN_603 [55C6] C5R17 CAPN_402 [18A5] C6R29 CAPN_402 [10C7] C7D8 CAPN_805 [9C4]
C4V9 CAPN_402 [55B4] C5R18 CAPN_402 [12A6] C6R30 CAPN_402 [11B3] C7D11 CAPN_805 [9B5]
C4V10 CAPN_402 [55B3] C5R19 CAPN_603 [16A7] C6R32 CAPN_402 [10D5] C7D12 CAPN_805 [9C5]
C4V11 CAPN_402 [55B2] C5R20 CAPN_805 [18B3] C6R35 CAPN_402 [10A6] C7D18 CAPN_805 [9C4]
C4V12 CAPN_402 [55B7] C5T1 CAPN_402 [14A1] C6R36 CAPN_402 [10C5] C7D19 CAPN_805 [9C5]
C4V13 CAPN_402 [55B6] C5T2 CAPN_402 [14A1] C6R37 CAPN_402 [5A5] C7D23 CAPN_402 [58A5]
C4V14 CAPN_402 [55B5] C5T3 CAPN_402 [14A2] C6R39 CAPN_402 [10B7] C7E1 CAPN_805 [9C5]
C4V15 CAPN_603 [55C6] C5T4 CAPN_402 [14A2] C6R41 CAPN_402 [11A7] C7E2 CAPN_805 [9C5]
C5B1 CAPN_603 [56C7] C5U1 CAPN_402 [22A1] C6R42 CAPN_402 [10B7] C7E5 CAPN_805 [9B5]
C5B2 CAP_P_RDL [56C6] C5U2 CAPN_402 [22A1] C6R44 CAPN_402 [10D5] C7E6 CAPN_805 [9D5]
C5B3 CAPN_805 [56C8] C5U3 CAPN_402 [22A1] C6R47 CAPN_805 [18D2] C7E9 CAPN_805 [9B6]
C5B4 CAP_P_RDL [56B6] C5U4 CAPN_402 [22A2] C6T1 CAPN_805 [9A5] C7E10 CAPN_805 [9B6]
CONFIDENTIAL
C7F1 CAP_P_RDL [55D2] C7R66 CAPN_402 [11D3] C7T29 CAPN_402 [11D2] C8E3 CAP_P_RDL [50A8]
C7F3 CAP_P_RDL [55B8] C7R67 CAPN_402 [10A7] C7T30 CAPN_402 [11D2] C8F1 CAP_P_RDL [50A7]
C7F4 CAP_P_RDL [57C2] C7R68 CAPN_402 [10C5] C7T31 CAPN_402 [11C2] C8F2 CAPN_603 [57C4]
C7F5 CAPN_1206 [57C1] C7R69 CAPN_402 [10B5] C7T32 CAPN_805 [9B6] C8G1 CAPN_402 [51A5]
C7G2 CAPN_402 [32D7] C7R74 CAPN_402 [11B3] C7T33 CAPN_805 [9C6] C8G2 CAPN_402 [32C4]
C7G3 CAPN_1206 [57C2] C7R75 CAPN_402 [11B5] C7T37 CAPN_402 [10B4] C8G4 CAPN_1206 [57C3]
C7G4 CAPN_1206 [57C2] C7R76 CAPN_402 [10B7] C7T38 CAPN_402 [11D5] C8G5 CAP_P_RDL [51D5]
C7G5 CAPN_603 [57C1] C7R81 CAPN_402 [10C5] C7T39 CAPN_402 [11B4] C8N1 CAPN_603 [53C2]
C7G7 CAP_P_RDL [57C2] C7R82 CAPN_402 [11B3] C7T40 CAPN_402 [11B5] C8N3 CAPN_805 [53D6]
C7G8 CAPN_805 [60C2] C7R83 CAPN_402 [11B4] C7T41 CAPN_402 [11B5] C8N4 CAPN_402 [53B5]
C7G9 CAPN_402 [60C2] C7R89 CAPN_402 [10B4] C7T46 CAPN_402 [11A5] C8N5 CAPN_603 [53C7]
C7N1 CAPN_402 [32B7] C7R90 CAPN_805 [9C5] C7T47 CAPN_402 [11A5] C8P1 CAPN_603 [53C8]
C7N2 CAPN_402 [32A4] C7R91 CAPN_805 [9B4] C7T48 CAPN_402 [11A4] C8P2 CAPN_402 [53C7]
C7N3 CAPN_1206 [50B1] C7R95 CAPN_402 [11D4] C7T49 CAPN_402 [11B5] C8P3 CAPN_603 [53B7]
C7P1 CAPN_805 [56A1] C7R99 CAPN_402 [10A4] C7T50 CAPN_402 [11C5] C8P4 CAPN_603 [53A6]
C7R1 CAPN_402 [6C7] C7R100 CAPN_402 [10A4] C7T51 CAPN_402 [10C4] C8P5 CAPN_402 [58A3]
C7R2 CAPN_805 [9C6] C7R101 CAPN_402 [11C4] C7T54 CAPN_402 [11D7] C8U1 CAPN_603 [51B3]
C7R3 CAPN_805 [9D5] C7R102 CAPN_402 [10C5] C7T55 CAPN_402 [11B4] C8U2 CAPN_402 [51B2]
C7R4 CAPN_805 [9A4] C7R106 CAPN_402 [11C5] C7T56 CAPN_402 [11C5] C8U3 CAPN_603 [51B5]
C7R5 CAPN_805 [9B4] C7R110 CAPN_402 [11D5] C7T57 CAPN_402 [11C4] C8U4 CAPN_402 [51C5]
C7R7 CAPN_603 [6C6] C7R111 CAPN_402 [10C3] C7T58 CAPN_402 [11D5] C8U5 CAPN_402 [57B3]
C7R14 CAPN_402 [11C5] C7R112 CAPN_603 [4D6] C7T83 CAPN_805 [9B5] C8U6 CAPN_402 [51A6]
C7R19 CAPN_402 [10C6] C7R113 CAPN_603 [4D6] C7T84 CAPN_805 [9B5] C8U7 CAPN_603 [51A7]
C7R20 CAPN_402 [11C6] C7R114 CAPN_402 [6D5] C7T90 CAPN_402 [59C5] C8U8 CAPN_402 [51A5]
C7R21 CAPN_402 [11B7] C7R115 CAPN_402 [6D5] C7T91 CAPN_402 [59C4] C8U9 CAPN_402 [57C6]
C7R22 CAPN_402 [10D6] C7R116 CAPN_402 [6D5] C7T92 CAPN_402 [59C5] C8U10 CAPN_402 [51B4]
C7R23 CAPN_805 [9A5] C7R119 CAPN_805 [9C5] C7T93 CAPN_805 [9C6] C8V1 CAPN_603 [51B6]
C7R24 CAPN_805 [9A5] C7R120 CAPN_805 [9B5] C7T94 CAPN_805 [9D6] C8V15 CAPN_603 [51D6]
C7R25 CAPN_805 [9A4] C7R121 CAPN_805 [9B5] C7T98 CAPN_603 [56C2] C9A1 CAPN_603 [49D3]
C7R26 CAPN_805 [9B6] C7T1 CAPN_805 [9A6] C7T99 CAPN_603 [56C1] C9A2 CAPN_603 [49D2]
C7R27 CAPN_805 [9D4] C7T2 CAPN_402 [10A5] C7T100 CAPN_603 [56D3] C9A3 CAPN_402 [58C2]
C7R28 CAPN_805 [9C3] C7T3 CAPN_402 [10A7] C7T102 CAPN_805 [57C1] C9A4 CAPN_402 [49B2]
C7R29 CAPN_805 [9C3] C7T4 CAPN_805 [9B3] C7T103 CAPN_805 [57C1] C9A5 CAPN_603 [49D3]
C7R30 CAPN_805 [9A5] C7T5 CAPN_805 [9B4] C7U5 CAPN_603 [57C6] C9A6 CAPN_603 [49D3]
C7R31 CAPN_402 [11D7] C7T6 CAPN_805 [9A6] C7U6 CAPN_402 [57C6] C9B1 CAP_P_RDL [49D4]
C7R32 CAPN_402 [11A5] C7T7 CAPN_402 [11D2] C7U7 CAPN_402 [57A6] C9B2 CAPN_1206 [50B8]
C7R33 CAPN_402 [11A5] C7T8 CAPN_402 [11C2] C7U8 CAPN_402 [57B6] C9B3 CAPN_603 [53C2]
C7R34 CAPN_402 [10C6] C7T9 CAPN_402 [10D6] C7U9 CAPN_603 [57C4] C9B4 CAPN_1206 [50B6]
C7R35 CAPN_402 [10C6] C7T10 CAPN_402 [10C3] C7U10 CAPN_402 [57A6] C9C1 CAP_P_RDL [50B7]
C7R39 CAPN_402 [11B6] C7T11 CAPN_402 [11B5] C7U11 CAPN_402 [57A5] C9C2 CAPN_603 [53B3]
C7R40 CAPN_402 [11B6] C7T12 CAPN_402 [11C2] C7V2 CAPN_603 [57C1] C9C3 CAPN_1206 [50B5]
C7R41 CAPN_402 [11B6] C7T13 CAPN_402 [11C2] C8A1 CAPN_402 [49C3] C9C4 CAP_P_RDL [50B7]
C7R42 CAPN_402 [11C6] C7T14 CAPN_402 [11D2] C8A2 CAPN_402 [49C2] C9C5 CAPN_603 [52C1]
C7R43 CAPN_402 [10B6] C7T15 CAPN_402 [11C3] C8B1 CAP_P_RDL [49B3] C9C7 CAPN_402 [32B7]
C7R44 CAPN_402 [10D7] C7T16 CAPN_402 [11B2] C8B2 CAPN_1206 [50B4] C9D1 CAPN_1206 [52D2]
C7R48 CAPN_402 [10C4] C7T17 CAPN_402 [11B2] C8B3 CAPN_603 [53D2] C9D2 CAP_P_RDL [50B6]
C7R49 CAPN_402 [10D7] C7T18 CAPN_402 [11B2] C8B4 CAPN_1206 [50B2] C9D3 CAPN_1206 [52D3]
C7R50 CAPN_402 [10C5] C7T19 CAPN_402 [11A2] C8B6 CAPN_603 [54B3] C9D4 CAPN_1206 [52C3]
C7R51 CAPN_402 [10D5] C7T20 CAPN_402 [11A2] C8B7 CAPN_402 [53A7] C9E1 CAPN_1206 [52C2]
C7R52 CAPN_402 [10D5] C7T21 CAPN_402 [10D3] C8B8 CAPN_603 [53A7] C9E2 CAPN_402 [32C7]
C7R56 CAPN_402 [11C7] C7T22 CAPN_402 [10D4] C8B9 CAPN_805 [53D5] C9E3 CAP_P_RDL [50B7]
C7R57 CAPN_402 [10B5] C7T23 CAPN_402 [11A3] C8C1 CAP_P_RDL [50A5] C9E4 CAPN_603 [52B1]
C7R58 CAPN_402 [10B5] C7T24 CAPN_402 [11C3] C8C2 CAP_P_RDL [50A8] C9F1 CAPN_1206 [52A2]
C7R59 CAPN_402 [10B5] C7T25 CAPN_402 [11D6] C8D1 CAP_P_RDL [50A6] C9F2 CAPN_402 [32C7]
C7R60 CAPN_402 [10A5] C7T26 CAPN_402 [11A4] C8D4 CAP_P_RDL [50A5] C9F3 CAPN_603 [52A1]
C7R61 CAPN_402 [10A6] C7T27 CAPN_402 [10C4] C8E1 CAP_P_RDL [50A7] C9F4 CAPN_1206 [52A3]
C7R65 CAPN_402 [11A3] C7T28 CAPN_402 [11C5] C8E2 CAP_P_RDL [50A6] C9G1 CAPN_402 [46D6]
CONFIDENTIAL
C9G2 CAP_P_RDL [46D6] D2A1 DIOSOT23S_SOT [44D4] DB4P4 DBPAD_TP [28A2] FB2P1 FERRITE_603 [37A7]
C9G3 CAP_P_RDL [46B6] 23S DB4P5 DBPAD_TP [28B5] FB2P2 FERRITE_603 [38D7]
C9G4 CAPN_402 [46B6] D3A1 DIODE_SOT23 [43C3] DB6E1 DBPAD_TP [47C4] FB2P3 FERRITE_603 [37C7]
C9G5 CAPN_805 [46D6] D3V1 BAT54A_SOT23S [55D6] DB6E2 DBPAD_TP [47C4] FB2P4 FERRITE_603 [37C7]
C9G6 CAPN_805 [46B7] D5B1 DIODE_SMA [56B7] DB6E3 DBPAD_TP [47C4] FB2P5 FERRITE_603 [37A7]
C9N1 CAPN_402 [32B4] D5N1 DIODE_SOD123 [56B8] DB6E4 DBPAD_TP [47C4] FB2R1 FERRITE_603 [37B7]
C9P1 CAPN_603 [53C8] D5N2 DIODE_SOD123 [56B8] DB6G1 DBPAD_TP [55C8] FB4D1 FERRITE_603 [16D7]
C9P2 CAPN_805 [52D4] D8B1 ZENER_SOD123 [53C2] DB7R1 DBPAD_TP [4C1] FB4N5 FERRITE_603 [30D7]
C9P3 CAPN_805 [52D5] D8B2 DIODE_SOT23 [53D3] DB7R2 DBPAD_TP [4C6] FB4N6 FERRITE_603 [31C7]
C9P4 CAPN_805 [52D7] D8B3 DIOSOT23S_SOT [53D2] DB7U1 DBPAD_TP [57B4] FB4N7 FERRITE_603 [31B6]
C9T1 CAPN_805 [52C4] 23S DB7U2 DBPAD_TP [57C7] FB4N8 FERRITE_603 [30C7]
C9T2 CAPN_805 [52C5] D8B4 LED_SM [58B2] DB8F4 DBPAD_TP [57C5] FB4P1 FERRITE_603 [31D2]
C9T3 CAPN_805 [52C7] D9C1 DIODE_SOT23 [52D6] DB8M1 DBPAD_TP [49D2] FB4R1 FERRITE_603 [16C7]
C9U1 CAPN_805 [52A4] D9E1 DIODE_SOT23 [52C6] DB8M2 DBPAD_TP [49D2] FB4T1 FERRITE_603 [16C7]
C9U2 CAPN_805 [52B5] D9F1 DIODE_SOT23 [52B6] DB8M3 DBPAD_TP [49D2] FB5G1 FERRITE_603 [46D2]
C9U3 CAPN_805 [52A7] D9G1 DIOSOT23S_SOT [46C6] DB8N1 DBPAD_TP [49C3] FB5R1 FERRITE_603 [16B7]
CM2A1 CMCHOKE_SM [29D6] 23S DB8P1 DBPAD_TP [50B5] FB6D1 FERRITE_603 [6C7]
CM2A2 CMCHOKE_SM [29C6] D9G2 DIOSOT23S_SOT [46C6] DB8P2 DBPAD_TP [50B5] FB6R1 FERRITE_603 [6B7]
CM3A1 CMCHOKE_SM [29B6] 23S DB8U1 DBPAD_TP [57D6] FB6R2 FERRITE_603 [6B7]
CM3A2 CMCHOKE_SM [29A6] D9V1 DIOSOT23S_SOT [46A6] DB8U2 DBPAD_TP [57C6] FB7D1 FERRITE_603 [6A7]
CR1D1 MBT3904DUAL_S [47B6] 23S DB8U3 DBPAD_TP [57B4] FB7R1 FERRITE_603 [6D7]
OT D9V2 DIOSOT23S_SOT [46A6] DB8U4 DBPAD_TP [51C5] FT1N1 FTPAD_TP [33A2]
CR1D2 DIOSOT23S_SOT [48A2] 23S EG1A1 ESDGUARD_603 [45C4] FT1N2 FTPAD_TP [45D3]
23S DB1F1 DBPAD_TP [34A7] EG1A2 ESDGUARD_603 [45C5] FT1P1 FTPAD_TP [27B1]
CR1D3 DIOSOT23S_SOT [48A1] DB1N1 DBPAD_TP [40C5] EG1E1 ESDGUARD_603 [48C3] FT1P2 FTPAD_TP [27B1]
23S DB1N3 DBPAD_TP [39B5] EG1E2 ESDGUARD_603 [48C4] FT1R1 FTPAD_TP [47A8]
CR2A1 MBT3904DUAL_S [44B5] DB1N4 DBPAD_TP [39C7] EG1E3 ESDGUARD_603 [48C4] FT1R2 FTPAD_TP [47B3]
OT DB1N5 DBPAD_TP [33D6] EG1E4 ESDGUARD_603 [48C5] FT1R3 FTPAD_TP [42C7]
CR2M2 MBT3904DUAL_S [41A3] DB1P1 DBPAD_TP [33B2] EG2A1 ESDGUARD_402 [29D6] FT1R4 FTPAD_TP [42C7]
OT DB1P2 DBPAD_TP [33B2] EG2A2 ESDGUARD_402 [29D6] FT1R5 FTPAD_TP [42C7]
CR3A1 BAV99DUAL_SOT [44B8 44C8] DB2B1 DBPAD_TP [34B3] EG2A3 ESDGUARD_402 [29C6] FT1T1 FTPAD_TP [42C4]
363 DB2N3 DBPAD_TP [33B2] EG2A4 ESDGUARD_402 [29C6] FT1U1 FTPAD_TP [56D4]
CR3A2 BAV99DUAL_SOT [44D8 44C8] DB2N4 DBPAD_TP [33B2] EG2B1 ESDGUARD_603 [41B5] FT1U2 FTPAD_TP [34A7]
363 DB2N5 DBPAD_TP [33B2] EG2B2 ESDGUARD_603 [41C5] FT1V1 FTPAD_TP [46A1]
CR3M1 BAV99DUAL_SOT [29B4 29B3] DB2N6 DBPAD_TP [33B2] EG2G1 ESDGUARD_603 [46B1] FT2M1 FTPAD_TP [41D6]
363 DB2N7 DBPAD_TP [33B2] EG3A1 ESDGUARD_402 [29B5] FT2M2 FTPAD_TP [29D4]
CR3M2 BAV99DUAL_SOT [44A7 44A6] DB2N8 DBPAD_TP [33C6] EG3A2 ESDGUARD_402 [29B6] FT2M3 FTPAD_TP [29D4]
363 DB2N9 DBPAD_TP [33B2] EG3A3 ESDGUARD_402 [29A5] FT2M4 FTPAD_TP [29D4]
CR6T1 MBT3904DUAL_S [56C4] DB2N10 DBPAD_TP [33B2] EG3A4 ESDGUARD_402 [29A6] FT2M5 FTPAD_TP [29D4]
OT DB2N11 DBPAD_TP [33B2] EG3G1 ESDGUARD_603 [46B2] FT2N1 FTPAD_TP [41D7]
CR7V2 MBR0520L_SOD1 [57B4] DB2N12 DBPAD_TP [33B2] EG3M1 ESDGUARD_603 [29B2] FT2N2 FTPAD_TP [41C8]
23 DB2P1 DBPAD_TP [33C2] EG3M2 ESDGUARD_402 [29B4] FT2N3 FTPAD_TP [27D3]
D1A1 DIOSOT23S_SOT [45C6] DB2P2 DBPAD_TP [33C2] EG3M3 ESDGUARD_402 [29B3] FT2N4 FTPAD_TP [27B1]
23S DB2P3 DBPAD_TP [33C2] EG4G1 ESDGUARD_603 [46C2] FT2N5 FTPAD_TP [34C8]
D1A2 DIOSOT23S_SOT [45D6] DB2P4 DBPAD_TP [33B2] EG4G2 ESDGUARD_603 [46C2] FT2N6 FTPAD_TP [29B3]
23S DB2P5 DBPAD_TP [33B2] EG9G1 ESDGUARD_603 [46C5] FT2P1 FTPAD_TP [41B6]
D1B1 DIOSOT23S_SOT [45B6] DB2P6 DBPAD_TP [33B2] EG9G2 ESDGUARD_603 [46D5] FT2P2 FTPAD_TP [27A1]
23S DB2P7 DBPAD_TP [33B2] EG9V1 ESDGUARD_603 [46A5] FT2P3 FTPAD_TP [53A2]
D1E1 DIOSOT23S_SOT [48B6] DB2P8 DBPAD_TP [34A6] EG9V2 ESDGUARD_603 [46A5] FT2P4 FTPAD_TP [27C8]
23S DB2P9 DBPAD_TP [34A6] FB1B1 FERRITE_603 [39A6] FT2P5 FTPAD_TP [34B1]
D1E2 DIOSOT23S_SOT [48C6] DB2P15 DBPAD_TP [33D6] FB1N1 FERRITE_603 [40C5] FT2P6 FTPAD_TP [53B2]
23S DB3A1 DBPAD_TP [29C3] FB1P1 FERRITE_603 [38B7] FT2P7 FTPAD_TP [27D7]
D1E3 DIOSOT23S_SOT [48C5] DB3F1 DBPAD_TP [55C1] FB1P2 FERRITE_603 [38C7] FT2P10 FTPAD_TP [34C6]
23S DB4D1 DBPAD_TP [13C3] FB1P3 FERRITE_603 [38A7] FT2P11 FTPAD_TP [4D8]
D1E4 DIOSOT23S_SOT [48D5] DB4P1 DBPAD_TP [28A2] FB1P4 FERRITE_603 [38B7] FT2P12 FTPAD_TP [4D8]
23S DB4P2 DBPAD_TP [28A2] FB2B1 FERRITE_603 [41B3] FT2P13 FTPAD_TP [13D4]
D1F1 LED_SM [34A3] DB4P3 DBPAD_TP [28A2] FB2B2 FERRITE_603 [41D3] FT2P14 FTPAD_TP [13D8]
CONFIDENTIAL
FT2P15 FTPAD_TP [34C8] FT7R6 FTPAD_TP [4A7] L6G2 CMCHOKE_SM [49A6] Q7B2 FET_VREG_DPAK [54B5]
FT2P16 FTPAD_TP [51C2] FT7R7 FTPAD_TP [58A5] L7C1 INDUCTOR_TH [54B2] Q7C1 FET_VREG_DPAK [54B4]
FT2P17 FTPAD_TP [51C7] FT7T1 FTPAD_TP [4B3] L7F1 INDUCTOR_TH [55D5] Q7F1 FET_SOT23 [57C7]
FT2P18 FTPAD_TP [55A7] FT7T2 FTPAD_TP [4B3] L7G1 INDUCTOR_TH [57D1] Q7U1 NPN_SOT23 [57B7]
FT2P19 FTPAD_TP [55A3] FT7T3 FTPAD_TP [4B2] L8B1 INDUCTOR_TH [50B4] Q8B3 FET_SOT23 [53B1]
FT2P20 FTPAD_TP [35C6] FT7T4 FTPAD_TP [4B2] L8D1 INDUCTOR_TH [52D1] Q8B4 NPN_SOT23 [49A2]
FT2P21 FTPAD_TP [35C6] FT7T5 FTPAD_TP [4B2] L8E1 INDUCTOR_TH [52B1] Q8B5 NPN_SOT23 [49A3]
FT2P22 FTPAD_TP [35C6] FT7T6 FTPAD_TP [56D1] L8F1 INDUCTOR_TH [52A1] Q8B6 NPN_SOT23 [58B2]
FT2P23 FTPAD_TP [35C6] FT7T7 FTPAD_TP [4B3] L8F2 INDUCTOR_TH [57C2] Q8C1 FET_VREG_DPAK [52C3]
FT2P24 FTPAD_TP [34C8] FT7T8 FTPAD_TP [56C6] L9B1 INDUCTOR_TH [50B8] Q8F1 FET_VREG_DPAK [52A3]
FT2P25 FTPAD_TP [34A7] FT7T9 FTPAD_TP [50A5] L9G1 CMCHOKE_SM [46C7] Q8N1 PNP_2C_SOT223 [49B1]
FT2P26 FTPAD_TP [56A5] FT7U3 FTPAD_TP [57C1] L9V1 CMCHOKE_SM [46A7] Q9C1 FET_VREG_DPAK [52C4]
FT2R2 FTPAD_TP [27A1] FT7U4 FTPAD_TP [50A4] LB7G1 LABEL_SM [61D5] Q9D1 FET_VREG_DPAK [52D3]
FT2R3 FTPAD_TP [42C7] FT8N1 FTPAD_TP [49C3] MTG1B1 STD_MTG_HOLE_ [61C6] Q9D2 FET_VREG_DPAK [52D4]
FT2R4 FTPAD_TP [42C7] FT8P1 FTPAD_TP [53D7] TH Q9D3 FET_VREG_DPAK [52B3]
FT2R5 FTPAD_TP [42C7] FT8P2 FTPAD_TP [53D7] MTG1G1 STD_MTG_HOLE_ [61C6] Q9D4 FET_VREG_DPAK [52C3]
FT2R6 FTPAD_TP [42C7] FT8U1 FTPAD_TP [51B5] TH Q9E1 FET_VREG_DPAK [52C4]
FT2R7 FTPAD_TP [42C7] FT8U2 FTPAD_TP [51B5] MTG3C1 STD_MTG_HOLE_ [61B6] Q9E3 FET_VREG_DPAK [52B4]
FT2R8 FTPAD_TP [54A4] FT9N1 FTPAD_TP [49D3] TH Q9F1 FET_VREG_DPAK [52A4]
FT2U1 FTPAD_TP [55C1] J1A1 XENONRJ45USB_ [45B2] MTG3E1 STD_MTG_HOLE_ [61B4] Q9F2 FET_VREG_DPAK [52A4]
FT3M1 FTPAD_TP [29D4] TH TH Q9F4 FET_VREG_DPAK [52A3]
FT3M2 FTPAD_TP [29D4] J1C1 1X7SATA_TH [48A7] MTG5B1 STD_MTG_HOLE_ [61C5] R1A1 RESN_402 [39B2]
FT3M3 FTPAD_TP [29D4] J1D1 2X6HDR2_TH [48A2] TH R1A2 RESN_402 [39B2]
FT3M4 FTPAD_TP [29D4] J1D2 2X5HDR10_TH [58D7] MTG5C1 STD_MTG_HOLE_ [61A6] R1A3 RESN_402 [39C2]
FT3P1 FTPAD_TP [27C1] J1E1 XENONHDD_TH [48C2] TH R1A4 RESN_402 [39D2]
FT3P2 FTPAD_TP [27C1] J1E2 1X5HDR_TH [60A3] MTG5E1 STD_MTG_HOLE_ [61A4] R1A5 RESN_402 [45B5]
FT3P3 FTPAD_TP [34A7] J2A1 HDMI_1X19HDR [29C1] TH R1B1 RESN_603 [45C7]
FT3P4 FTPAD_TP [27D3] J2B1 2X7HDR14_TH [58C5] MTG5G1 STD_MTG_HOLE_ [61C5] R1B2 RESN_603 [45D7]
FT4N1 FTPAD_TP [28A6] J2D1 2X3HDR_TH [33A6] TH R1B3 RESN_402 [36B3]
FT4N2 FTPAD_TP [29C3] J2D2 2X4HDR_TH [13A8] MTG6C1 STD_MTG_HOLE_ [61A6] R1B4 RESN_402 [39B3]
FT4N4 FTPAD_TP [28A6] J3A1 XENONAVIP_TH [44C2] TH R1B5 RESN_402 [39B3]
FT4N5 FTPAD_TP [27B4] J3A2 1X3HDR_TH [43C2] MTG6E1 STD_MTG_HOLE_ [61B4] R1B6 RESN_402 [39C4]
FT4P1 FTPAD_TP [27D7] J3C1 PCIEXMIDBUS_S [58A7] TH R1B7 RESN_402 [39D4]
FT4P2 FTPAD_TP [27B1] M MTG8C1 STD_MTG_HOLE_ [61B6] R1B9 RESN_402 [36D7]
FT4P3 FTPAD_TP [27B1] J4F1 1X3HDR_TH [62B5] TH R1B10 RESN_402 [36C7]
FT4P4 FTPAD_TP [27D3] J4G1 1X2HDR_TH [62B4] MTG8E1 STD_MTG_HOLE_ [61A4] R1B11 RESN_402 [39B7]
FT5N1 FTPAD_TP [56C6] J4G2 XENONMU_TH [46C1] TH R1B12 RESN_402 [40B6]
FT5N2 FTPAD_TP [56B5] J5C1 2X3HDR_TH [27A6] MTG9B1 STD_MTG_HOLE_ [61C3] R1B13 RESN_402 [39C3]
FT5R1 FTPAD_TP [56C1] J5C2 2X3HDR_TH [13A5] TH R1C1 RESN_402 [39C7]
FT5R2 FTPAD_TP [50A2] J6G1 XENONRF_TH [49B5] MTG9G1 STD_MTG_HOLE_ [61C3] R1C2 RESN_402 [33B7]
FT6U1 FTPAD_TP [47C4] J7G3 2X6HDR_TH [60C3] TH R1C3 RESN_402 [36D3]
FT6U2 FTPAD_TP [47C4] J8B1 1X8HDR_TH [62C4] Q1G2 NPN_SOT23 [47A3] R1C4 RESN_402 [33B8]
FT6U3 FTPAD_TP [47C4] J8C1 2X5HDR_TH [58A3] Q1G3 PNP_SOT23 [28A4] R1C5 RESN_402 [33B8]
FT6U4 FTPAD_TP [47C4] J9A1 XENONPWR_TH [49C1] Q1V1 NPN_SOT23 [47A4] R1C6 RESN_402 [33B7]
FT6U5 FTPAD_TP [47C4] J9A2 1X2HDR_SM [58C2] Q2F3 FET_VREG_DPAK [55B3] R1C7 RESN_402 [33B8]
FT6U6 FTPAD_TP [47C4] J9G1 XENONGAME_TH [46B5] Q2N1 PNP_SOT23 [41A5] R1C8 RESN_402 [36B6]
FT6U7 FTPAD_TP [47C4] L1B1 CMCHOKE_SM [45C6] Q2N3 PNP_SOT23 [44A4] R1D2 RESN_402 [42B5]
FT6U8 FTPAD_TP [47C4] L2G1 CMCHOKE_SM [46B2] Q2P1 NPN_SOT23 [58A1] R1D3 RESN_402 [42B5]
FT6U9 FTPAD_TP [47D5] L3A1 INDUCTOR_1210 [44C7] Q3F1 FET_VREG_DPAK [55C3] R1D4 RESN_402 [42B5]
FT6U10 FTPAD_TP [47D5] L3A2 INDUCTOR_1210 [44C7] Q3M1 PNP_DPAK [43D3] R1D5 RESN_402 [47A6]
FT6U11 FTPAD_TP [47D5] L3A3 INDUCTOR_1210 [44D7] Q3M2 NPN_SOT23 [43D4] R1D6 RESN_402 [47B7]
FT6V1 FTPAD_TP [55C8] L3A4 INDUCTOR_1210 [44B7] Q6B1 FET_VREG_DPAK [54D5] R1E1 RESN_1210 [54A7]
FT7R1 FTPAD_TP [4A7] L3F1 INDUCTOR_TH [55C2] Q6B2 FET_VREG_DPAK [54C5] R1E2 RESN_402 [42C5]
FT7R2 FTPAD_TP [4A7] L4G1 CMCHOKE_SM [46C3] Q6C1 FET_VREG_DPAK [54C4] R1E3 RESN_1210 [54A7]
FT7R3 FTPAD_TP [56A1] L6C1 INDUCTOR_TH [54D2] Q6F1 FET_VREG_DPAK [55C7] R1F7 RESN_402 [56D7]
FT7R4 FTPAD_TP [4A7] L6F1 INDUCTOR_TH [55C7] Q6F2 FET_VREG_DPAK [55B7] R1F8 RESN_402 [56D7]
FT7R5 FTPAD_TP [4A7] L6G1 CMCHOKE_SM [49C6] Q7B1 FET_VREG_DPAK [54C5] R1G1 RESN_1206 [47B3]
CONFIDENTIAL
R1G2 RESN_402 [47B4] R2B19 RESN_402 [34A7] R2P4 RESN_402 [34C7] R3D2 RESN_402 [24A7]
R1G3 RESN_402 [43C6] R2C1 RESN_603 [38D7] R2P5 RESN_402 [33D7] R3D3 RESN_402 [24A7]
R1G4 RESN_402 [43C7] R2C3 RESN_402 [56A6] R2P6 RESN_402 [34C7] R3D4 RESN_402 [23D7]
R1M1 RESN_603 [39C2] R2D1 RESN_402 [42B6] R2P8 RESN_402 [33C6] R3D5 RESN_402 [23D7]
R1M2 RESN_603 [39B2] R2D2 RESN_402 [42C2] R2P9 RESN_402 [33D6] R3E1 RESN_402 [25A5]
R1M3 RESN_402 [45B5] R2D3 RESN_402 [42B6] R2P10 RESN_402 [34B2] R3E2 RESN_402 [26A8]
R1N1 RESN_402 [39B7] R2D4 RESN_402 [42B6] R2P11 RESN_402 [33C7] R3E3 RESN_402 [26A7]
R1N2 RESN_402 [39B7] R2D5 RESN_402 [42B6] R2P12 RESN_402 [34A2] R3E4 RESN_402 [25D7]
R1N3 RESN_402 [39B6] R2D6 RESN_402 [42C5] R2P13 RESN_402 [34A2] R3E5 RESN_402 [25D7]
R1N4 RESN_402 [39B6] R2D7 RESN_402 [42C6] R2P14 RESN_402 [35B6] R3F1 RESN_402 [19A5]
R1N5 RESN_402 [39B3] R2D8 RESN_402 [42B7] R2P15 RESN_402 [34B2] R3G4 RESN_603 [46B3]
R1N6 RESN_402 [39B4] R2D9 RESN_402 [13A7] R2P16 RESN_402 [33C7] R3M1 RESN_402 [29B2]
R1N7 RESN_402 [39B4] R2D10 RESN_402 [13A8] R2P17 RESN_603 [38C7] R3M2 RESN_402 [44A6]
R1N8 RESN_402 [40A3] R2D11 RESN_402 [12C1] R2P18 RESN_402 [58D4] R3M3 RESN_402 [44A7]
R1P1 RESN_402 [33B7] R2D12 RESN_402 [12C2] R2P19 RESN_402 [58A1] R3M5 RESN_402 [29C4]
R1P2 RESN_402 [33B8] R2D13 RESN_402 [60B4] R2R1 RESN_402 [23A7] R3M6 RESN_402 [29C4]
R1P3 RESN_402 [33B8] R2D14 RESN_402 [60B4] R2R2 RESN_402 [23A7] R3M7 RESN_402 [29B2]
R1P5 RESN_402 [33B7] R2E1 RESN_402 [13B4] R2R3 RESN_402 [24D7] R3M8 RESN_402 [43C4]
R1P6 RESN_402 [33B8] R2E2 RESN_402 [13B8] R2R4 RESN_402 [24D7] R3M9 RESN_402 [43D4]
R1P7 RESN_402 [35C6] R2E3 RESN_402 [13A7] R2R5 RESN_402 [12D2] R3N6 RESN_402 [49B8]
R1R1 RESN_402 [35D3] R2E4 RESN_402 [13B7] R2R6 RESN_402 [12A2] R3N7 RESN_402 [49B7]
R1R2 RESN_402 [47B7] R2E5 RESN_402 [12D2] R2R7 RESN_402 [60A4] R3N8 RESN_402 [58A2]
R1R3 RESN_402 [47B6] R2E6 RESN_1210 [54A7] R2R8 RESN_402 [60A4] R3P6 RESN_402 [34B1]
R1R4 RESN_402 [48A3] R2E7 RESN_1210 [54A7] R2T1 RESN_402 [12A1] R3P7 RESN_402 [34C2]
R1R5 RESN_402 [47B6] R2G2 RESN_402 [43B7] R2T2 RESN_402 [12B1] R3R1 RESN_402 [24A5]
R1U1 RESN_402 [56D5] R2G3 RESN_402 [43B6] R2T3 RESN_402 [25A7] R3T1 RESN_402 [26A5]
R1U2 RESN_402 [56D5] R2G5 RESN_603 [46A3] R2T4 RESN_402 [25A7] R3T2 RESN_402 [15B4]
R1U3 RESN_402 [34A4] R2M3 RESN_402 [34B7] R2T5 RESN_402 [26D7] R3U1 RESN_402 [20A5]
R1V1 RESN_402 [47A4] R2M4 RESN_402 [44A1] R2T6 RESN_402 [26D7] R3V1 RESN_402 [55C3]
R1V2 RESN_1206 [47B3] R2M5 RESN_402 [34B7] R2T7 RESN_805 [54A2] R3V3 RESN_402 [55A4]
R2A1 RESN_402 [44A2] R2M6 RESN_402 [44A2] R2T8 RESN_805 [54A2] R3V4 RESN_402 [55A7]
R2A2 RESN_402 [34B7] R2M9 RESN_402 [44A3] R2V1 RESN_402 [43A2] R3V5 RESN_402 [55A7]
R2A4 RESN_402 [44B5] R2M10 RESN_402 [44A4] R3A2 RESN_402 [43B3] R4B1 RESN_402 [27D7]
R2A5 RESN_402 [44B4] R2N1 RESN_402 [41A2] R3A3 RESN_402 [44C7] R4B2 RESN_402 [27D5]
R2A6 RESN_402 [44B5] R2N2 RESN_402 [41A4] R3A4 RESN_402 [44D7] R4B3 RESN_402 [28A2]
R2A7 RESN_402 [44B5] R2N3 RESN_402 [41B7] R3A6 RESN_402 [44C7] R4B4 RESN_402 [27A3]
R2A8 RESN_402 [44C5] R2N4 RESN_402 [33B6] R3A7 RESN_402 [43C3] R4B5 RESN_402 [27A2]
R2A9 RESN_402 [44B5] R2N5 RESN_402 [33B6] R3A9 RESN_402 [44B7] R4B6 RESN_402 [27B2]
R2A11 RESN_603 [29D7] R2N6 RESN_402 [33B7] R3A10 RESN_603 [29B7] R4B8 RESN_402 [27D6]
R2A12 RESN_603 [29C7] R2N7 RESN_402 [43A2] R3A11 RESN_603 [29B7] R4B9 RESN_402 [27D7]
R2A13 RESN_603 [29C7] R2N8 RESN_402 [33C2] R3A12 RESN_603 [29A7] R4B10 RESN_402 [28D2]
R2A14 RESN_603 [29B7] R2N9 RESN_402 [34C3] R3A13 RESN_603 [29A7] R4B11 RESN_402 [28D1]
R2B1 RESN_603 [41D6] R2N10 RESN_402 [36B3] R3B1 RESN_402 [27C7] R4B12 RESN_402 [28C6]
R2B2 RESN_402 [41B4] R2N11 RESN_402 [36B3] R3B2 RESN_402 [27D8] R4B13 RESN_402 [28D2]
R2B3 RESN_402 [41D4] R2N12 RESN_402 [36B3] R3B3 RESN_402 [58C4] R4B14 RESN_402 [28D1]
R2B4 RESN_402 [41B4] R2N13 RESN_402 [58C6] R3B4 RESN_402 [27C2] R4B15 RESN_402 [28B7]
R2B5 RESN_402 [41C4] R2N14 RESN_402 [58C4] R3B5 RESN_402 [27C2] R4B17 RESN_402 [27C7]
R2B6 RESN_603 [41D8] R2N15 RESN_402 [34D7] R3B6 RESN_402 [27B2] R4B18 RESN_402 [28C7]
R2B8 RESN_402 [33B6] R2N16 RESN_402 [60C7] R3C7 RESN_402 [27C2] R4B19 RESN_603 [28C1]
R2B9 RESN_402 [33B6] R2N19 RESN_402 [44A5] R3C8 RESN_402 [27D2] R4B20 RESN_603 [28B1]
R2B10 RESN_402 [33B7] R2N20 RESN_402 [44A1] R3C9 RESN_402 [27C2] R4B21 RESN_603 [28B1]
R2B11 RESN_402 [36C2] R2N21 RESN_402 [34D7] R3C15 RESN_402 [27C2] R4B22 RESN_603 [28C1]
R2B12 RESN_402 [36C3] R2N22 RESN_402 [41A5] R3C16 RESN_402 [27D2] R4B23 RESN_402 [28C2]
R2B13 RESN_402 [36C2] R2N23 RESN_402 [41A6] R3C21 RESN_0402 [56A5] R4B24 RESN_402 [27A3]
R2B14 RESN_402 [36C3] R2P1 RESN_402 [27D4] R3C22 RESN_402 [56A6] R4B25 RESN_402 [27B2]
R2B15 RESN_402 [36B2] R2P2 RESN_402 [33C7] R3C28 RESN_402 [13C8] R4B26 RESN_402 [27C2]
R2B16 RESN_402 [34A7] R2P3 RESN_402 [27D4] R3D1 RESN_402 [23A5] R4B27 RESN_402 [27C2]
CONFIDENTIAL
R4C1 RESN_402 [28B7] R4T5 RESN_402 [14A3] R6E2 RESN_402 [4A5] R7R15 RESN_402 [4B7]
R4C2 RESN_402 [28B6] R4T6 RESN_402 [14A7] R6G7 RESN_603 [49C7] R7R16 RESN_402 [4D7]
R4C3 RESN_402 [13A6] R4T7 RESN_402 [14A7] R6G8 RESN_603 [49C7] R7R17 RESN_402 [4C8]
R4C4 RESN_402 [13A5] R4T8 RESN_402 [14A3] R6G35 RESN_402 [60D4] R7R18 RESN_402 [4A7]
R4C5 RESN_402 [13A5] R4U1 RESN_402 [22A5] R6G36 RESN_402 [60D4] R7R19 RESN_402 [4A7]
R4C6 RESN_402 [13A3] R4U2 RESN_402 [20D7] R6G37 RESN_603 [49B6] R7R20 RESN_402 [4A8]
R4C7 RESN_402 [13A6] R4U3 RESN_402 [20D7] R6G38 RESN_603 [49A6] R7R21 RESN_402 [4A8]
R4C8 RESN_402 [27C2] R4U4 RESN_402 [19A7] R6R1 RESN_0402 [56A1] R7R22 RESN_402 [4A7]
R4C9 RESN_402 [27D2] R4U5 RESN_402 [19A7] R6R2 RESN_402 [56A2] R7R23 RESN_402 [4A7]
R4C10 RESN_402 [27D2] R4U6 RESN_402 [12A1] R6R3 RESN_402 [56A2] R7T2 RESN_402 [6C5]
R4C11 RESN_402 [27D2] R4V1 RESN_402 [55B3] R6R4 RESN_402 [4D7] R7T4 RESN_402 [50D5]
R4C12 RESN_402 [27D2] R4V2 RESN_402 [55B5] R6R5 RESN_402 [4C7] R7T5 RESN_402 [50D4]
R4C13 RESN_402 [27B2] R4V3 RESN_402 [55B5] R6R6 RESN_402 [4C8] R7T6 RESN_402 [50D5]
R4C15 RESN_402 [27B3] R4V5 RESN_402 [55A8] R6R8 RESN_402 [4C8] R7T8 RESN_402 [50D5]
R4C31 RESN_603 [56C4] R4V7 RESN_402 [55C6] R6T1 RESN_402 [56C5] R7T10 RESN_402 [56D4]
R4D1 RESN_402 [13C4] R4V9 RESN_402 [55B8] R6T3 RESN_402 [56D4] R7T11 RESN_402 [50C5]
R4D2 RESN_402 [13C4] R4V10 RESN_402 [55A6] R6T4 RESN_402 [56C5] R7T12 RESN_402 [50C4]
R4F1 RESN_402 [20A7] R4V11 RESN_402 [55C8] R6V1 RESN_402 [60C4] R7T13 RESN_402 [50C5]
R4F2 RESN_402 [20A8] R5B1 RESN_402 [56B6] R6V2 RESN_402 [60C4] R7T14 RESN_402 [50C4]
R4F3 RESN_402 [19D7] R5B2 RESN_402 [56A6] R7B2 RESN_402 [49B2] R7T15 RESN_402 [50C5]
R4F4 RESN_402 [19D7] R5B3 RESN_1206 [56B7] R7B6 RESN_805 [54B3] R7T16 RESN_402 [50C4]
R4F5 RESN_402 [21A5] R5C4 RESN_805 [56A4] R7D1 RESN_402 [4C7] R7T18 RESN_402 [4B6]
R4F6 RESN_402 [13B3] R5C5 RESN_402 [13A6] R7D2 RESN_402 [4C7] R7T19 RESN_402 [57C7]
R4F7 RESN_402 [12B1] R5C6 RESN_805 [56B4] R7E1 RESN_402 [50D6] R7U3 RESN_402 [4A5]
R4F8 RESN_402 [12C1] R5C8 RESN_402 [13A6] R7E2 RESN_402 [50D6] R7U4 RESN_402 [57B8]
R4G1 RESN_402 [55B1] R5C9 RESN_0402 [56B1] R7E3 RESN_402 [50D6] R7U5 RESN_402 [57B7]
R4G4 RESN_603 [46C3] R5C10 RESN_402 [13A6] R7E4 RESN_402 [50D6] R7U6 RESN_402 [57B5]
R4G5 RESN_603 [46D3] R5C11 RESN_402 [12D8] R7E5 RESN_402 [50D6] R7U7 RESN_402 [57B3]
R4G6 RESN_402 [55B1] R5C12 RESN_402 [12D8] R7E6 RESN_402 [50C6] R7U8 RESN_402 [57A6]
R4G7 RESN_402 [55A1] R5D1 RESN_402 [13D8] R7E7 RESN_402 [4A5] R7V4 RESN_402 [34C2]
R4G8 RESN_402 [55A1] R5D2 RESN_402 [13D7] R7E8 RESN_402 [4A4] R7V8 RESN_402 [60C4]
R4G9 RESN_402 [55C1] R5E1 RESN_402 [14A4] R7F1 RESN_402 [4A4] R8A1 RESN_402 [49C4]
R4N1 RESN_402 [30C7] R5E2 RESN_402 [14B4] R7F2 RESN_402 [4A5] R8A2 RESN_402 [49C3]
R4N2 RESN_402 [28C7] R5F1 RESN_402 [22A7] R7F3 RESN_402 [4A2] R8A3 RESN_402 [49A3]
R4N3 RESN_402 [28C7] R5F2 RESN_402 [22A7] R7F4 RESN_402 [4A2] R8A4 RESN_402 [49A3]
R4N4 RESN_402 [27B4] R5F3 RESN_402 [21D7] R7F6 RESN_603 [60D2] R8A5 RESN_402 [58B3]
R4N5 RESN_402 [27C7] R5F4 RESN_402 [21D7] R7F7 RESN_402 [4A2] R8B1 RESN_402 [53D3]
R4N6 RESN_402 [27C7] R5N1 RESN_402 [53B2] R7F9 RESN_402 [57C8] R8B2 RESN_402 [53A7]
R4P1 RESN_402 [27C7] R5P1 RESN_402 [56B2] R7G23 RESN_805 [57D1] R8B3 RESN_603 [53A6]
R4P2 RESN_402 [43C4] R5P2 RESN_402 [56B2] R7N1 RESN_805 [49A1] R8B4 RESN_603 [53C3]
R4P13 RESN_603 [56C4] R5P3 RESN_402 [13A6] R7N2 RESN_805 [49A1] R8B5 RESN_402 [49B3]
R4P14 RESN_603 [56C3] R5R1 RESN_402 [12D8] R7N3 RESN_805 [49A2] R8B6 RESN_402 [58B2]
R4R1 RESN_402 [15A7] R5R2 RESN_402 [12C8] R7N4 RESN_805 [49A1] R8B7 RESN_402 [53D3]
R4R2 RESN_402 [15A7] R5R3 RESN_402 [12A8] R7R1 RESN_402 [4B6] R8B8 RESN_402 [53D3]
R4R3 RESN_402 [13C8] R5U1 RESN_402 [22D7] R7R2 RESN_402 [4B6] R8B9 RESN_402 [53C3]
R4R4 RESN_402 [15B8] R5U2 RESN_402 [22D7] R7R3 RESN_402 [4A7] R8B10 RESN_402 [53C3]
R4R5 RESN_402 [15A8] R5U3 RESN_402 [21A7] R7R4 RESN_402 [4D7] R8C1 RESN_402 [53B2]
R4R6 RESN_402 [15A3] R5U4 RESN_402 [21A7] R7R5 RESN_402 [4A8] R8C2 RESN_402 [58A5]
R4R7 RESN_402 [15A3] R5V2 RESN_402 [43D6] R7R8 RESN_402 [4B7] R8C3 RESN_402 [58A4]
R4R8 RESN_402 [13B7] R5V3 RESN_402 [43D7] R7R9 RESN_402 [4B1] R8C4 RESN_402 [58A4]
R4R9 RESN_402 [12B8] R6C1 RESN_805 [56B3] R7R10 RESN_402 [4D7] R8C5 RESN_402 [58A4]
R4T1 RESN_402 [13B8] R6C2 RESN_805 [54D3] R7R11 RESN_402 [4D7] R8C6 RESN_402 [58A4]
R4T2 RESN_402 [15A4] R6D4 RESN_402 [4D5] R7R12 RESN_402 [4A8] R8C7 RESN_603 [53B6]
R4T3 RESN_402 [14A8] R6D5 RESN_402 [4D5] R7R13 RESN_402 [4A7] R8C8 RESN_402 [58A2]
R4T4 RESN_402 [14B8] R6E1 RESN_402 [4B2] R7R14 RESN_402 [4B5] R8C9 RESN_402 [53D7]
CONFIDENTIAL
R8F7 RESN_402 [51C7] R9V2 RESN_603 [46A7] TP7M2 TDRX2_TH [62D1] 6
R8F8 RESN_402 [51C2] RT1B1 THERMISTOR_12 [45D5] TP7R1 PROBE_SMT [4D2] U4U1 GDDR136_BGA13 [20C2 20C6]
R8G1 RESN_603 [51D6] 06 TP7R2 PROBE_SMT [4C2] 6
R8G3 RESN_402 [51A6] RT1R1 THERMISTOR_12 [48B3] TP7R3 PROBE_SMT [4C2] U4V1 ADP1823_LCC32 [55C5]
R8N1 RESN_402 [49B2] 06 TP7R4 PROBE_SMT [4C2] U5B1 NCP1117_DPAK [56C7]
R8N2 RESN_805 [53C2] RT1U1 THERMISTOR_18 [48B4] TP8A1 TDRX2_TH [62B1] U5B2 NCP1117_DPAK [56B7]
R8N3 RESN_805 [53A3] 12 TP8A2 TDRX2_TH [62C1] U5C1 NCP1117_SOT22 [56C3]
R8N4 RESN_805 [53A2] RT2G1 THERMISTOR_12 [46D3] TP8M1 TDRX4_TH [62A7] 3
R8N5 RESN_805 [53A3] 06 TP8M2 TDRX4_TH [62A7] U5F1 GDDR136_BGA13 [21C2 21B6]
R8N6 RESN_805 [53A2] RT2M1 THERMISTOR_12 [44D4] U1B1 BCM5241_LCC32 [40B4] 6
R8N7 RESN_805 [53D6] 06 U1B2 ICS1893BF_SSO [39C5] U5U1 GDDR136_BGA13 [22B6 22C2]
R8N17 RESN_402 [34D2] RT7C1 THERMISTOR_60 [53D8] P 6
R8N18 RESN_402 [34C2] 3 U1F1 NCP5662_DPAK [56D6] U6R1 NCP1117_SOT22 [56A3]
R8P1 RESN_603 [53C7] RT8F1 THERMISTOR_60 [51C6] U1F2 NCP1117_DPAK [46A3] 3
R8P3 RESN_402 [53C7] 3 U1G1 IR_WHOLDER_TH [43A4] U6T1 NCP502D_SC70 [56D2]
R8P4 RESN_402 [53C7] RT8G1 THERMISTOR_12 [46D7] U1R1 SI4501DY_SO8 [47B4] U6T2 LP2980_SOT23_ [56D2]
R8P5 RESN_603 [53B7] 06 U1U1 SN74LVC1G14_S [34A5] 5
R8P6 RESN_603 [53B7] RT8G2 THERMISTOR_12 [46B7] C70 U7D1 LOKI_BGA [4C4]
R8P7 RESN_402 [53C8] 06 U2B1 XDAC_SOIC14 [41C6] U7D1 LOKI_BGA [5C5]
R8P8 RESN_402 [58A2] ST1P1 SHORT_SM [38B7] U2C1 SB_BGA [33C4] U7D1 LOKI_BGA [6C3]
R8P9 RESN_402 [53D7] ST1P2 SHORT_SM [38B7] U2C1 SB_BGA [34C4] U7D1 LOKI_BGA [7C7 7C2 7C5]
R8U1 RESN_603 [51B2] ST1P3 SHORT_SM [38A7] U2C1 SB_BGA [35C5] U7D1 LOKI_BGA [8B7 8B4 8B2]
R8U2 RESN_402 [51B3] ST2F1 SHORT_SM [55C1] U2C1 SB_BGA [36C5] U7D1 LOKI_BGA [59B3]
R8U3 RESN_402 [51C5] ST2F2 SHORT_SM [55C3] U2C1 SB_BGA [37C4] U7E1 AT25020A_SOI8 [4A3]
R8U4 RESN_402 [51B2] ST2P1 SHORT_SM [38C7] U2C1 SB_BGA [38B5] U7F1 FET_VREG_DUAL [57C3]
R8U5 RESN_402 [51D5] ST2P2 SHORT_SM [37B7] U2D1 SN74LVC1G125_ [12B2] _1_SO-8
R8U6 RESN_402 [57B4] ST2P3 SHORT_SM [37C7] SC70 U7U2 IR3638_SSOP [57C4]
R8U7 RESN_402 [57C5] ST2P4 SHORT_SM [37A7] U2E1 NAND_TSOP [42B3] U8N1 NCP5331_LQFP3 [53C5]
R8U8 RESN_402 [57C6] ST3G1 SHORT_SM [55C3] U2E2 SN74LVC1G125_ [12D2] 2
R8U9 RESN_402 [57C6] ST4C1 SHORT_SM [28A7] SC70 U8U1 ADP3190A_TSSO [51C4]
R8U10 RESN_603 [51A7] ST4C2 SHORT_SM [28A7] U2R1 SN74LVC1G125_ [12A2] P28
R8U11 RESN_402 [51A5] ST4C3 SHORT_SM [28A7] SC70 U9P1 MOSDRIVER_SOI [52D6]
R8U12 RESN_402 [57A5] ST4C4 SHORT_SM [28A7] U2T1 NCP1117_DPAK [54A5] 8
R8U13 RESN_402 [51A7] ST4C5 SHORT_SM [28A7] U3D1 GDDR136_BGA13 [23C6 23C2] U9T1 MOSDRIVER_SOI [52B6]
R8U14 RESN_402 [57B2] ST5R1 SHORT_SM [53B7] 6 8
R8V1 RESN_603 [51B7] ST5R2 SHORT_SM [53D7] U3E1 GDDR136_BGA13 [25C2 25C6] U9U1 MOSDRIVER_SOI [52A6]
R8V2 RESN_603 [51B7] ST5V1 SHORT_SM [55C7] 6 8
R8V3 RESN_603 [51B6] ST6D1 SHORT_SM [6C7] U3P1 NCP1117_SOT22 [56A7] Y3B1 CRYSTAL_SM [27D8]
R8V4 RESN_603 [51B7] ST6F1 SHORT_SM [55C8] 3
R8V5 RESN_603 [51B6] ST6F2 SHORT_SM [55C7] U3R1 GDDR136_BGA13 [24C2 24C6]
R8V6 RESN_603 [51C6] ST6R1 SHORT_SM [6B7] 6
R8V7 RESN_603 [51C6] ST6R2 SHORT_SM [6A7] U3T1 GDDR136_BGA13 [26C6 26C2]
R8V9 RESN_603 [51C6] ST7D1 SHORT_SM [6A7] 6
R8V10 RESN_805 [51D6] ST7D2 SHORT_SM [57B2] U4C1 AT25020A_SOI8 [13A4]
R9B1 RESN_402 [53B2] ST7R1 SHORT_SM [6C7] U4C2 HANA_BGA225 [27C5]
R9C1 RESN_805 [52C2] ST7T1 SHORT_SM [51B4] U4C2 HANA_BGA225 [28C4]
R9E1 RESN_805 [52B2] ST7T2 SHORT_SM [51A8] U4C2 HANA_BGA225 [30C5]
R9F1 RESN_805 [52A2] ST8C1 SHORT_SM [53A8] U4C2 HANA_BGA225 [31B5]
R9G1 RESN_603 [46B7] ST8F1 SHORT_SM [51A7] U4D1 NBY2_BGA [12C6]
R9G2 RESN_603 [46C7] TP5A1 TDRX4_TH [62C7] U4D1 NBY2_BGA [13C5]
R9P1 RESN_805 [52D5] TP5A2 TDRX4_TH [62C7] U4D1 NBY2_BGA [14C7 14C3]
R9P2 RESN_805 [52D7] TP6A1 TDRX2_TH [62A1] U4D1 NBY2_BGA [15C7 15C3]
R9T1 RESN_805 [52C5] TP6A2 TDRX2_TH [62B1] U4D1 NBY2_BGA [16C3]
R9T2 RESN_805 [52C7] TP6D1 PROBE_SMT [4C7] U4D1 NBY2_BGA [17B7 17B2
R9U1 RESN_805 [52A5] TP7A1 TDRX4_TH [62B7] 17B5 17B3]
R9U2 RESN_805 [52B7] TP7A2 TDRX4_TH [62A7] U4D1 NBY2_BGA [59C8]
R9V1 RESN_603 [46A7] TP7M1 TDRX2_TH [62C1] U4F1 GDDR136_BGA13 [19C2 19C6]
CONFIDENTIAL

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CR-1 : @FALCON_LIB.

SCHEMATIC REV PCBA NUMBER REV BOM RELEASE DATE

I2S_MCLK(12.288MHZ) AUDIO ANA_XTAL_IN(27MHZ)

VMEM VR MEM EFUSE VR

IR EJECT MEM MEM BIND ARGON

IR EJECT MEM MEM BIND ARGON

12 IN FSB_GP_CP0_CLK_DP V28 GP_CP0_CLK_DP CP_GP0_CLK_DP AE27 FSB_CP_GP0_CLK_DP OUT 12

12 IN FSB_GP_CP0_FLAG_DP AB27 GP_CP0_FLAG_DP CP_GP0_FLAG_DP AH25 FSB_CP_GP0_FLAG_DP OUT 12

12 IN FSB_GP_CP0_DATA0_DP T26 GP_CP0_DATA0_DP CP_GP0_DATA0_DP AB26 FSB_CP_GP0_DATA0_DP OUT 12

12 IN FSB_GP_CP1_CLK_DP E28 GP_CP1_CLK_DP CP_GP1_CLK_DP M28 FSB_CP_GP1_CLK_DP OUT 12

12 IN FSB_GP_CP1_FLAG_DP J26 GP_CP1_FLAG_DP CP_GP1_FLAG_DP R28 FSB_CP_GP1_FLAG_DP OUT 12

12 IN FSB_GP_CP1_DATA0_DP C26 GP_CP1_DATA0_DP CP_GP1_DATA0_DP J28 FSB_CP_GP1_DATA0_DP OUT 12

CPU, FSB POWER + PLL POWER

CPU, CORE POWER

V_CPUCORE U7D1 IC V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE U7D1 IC V_CPUVCS

V_CPUCORE CPU, DECOUPLING

C7T94 C7E6 C7R3 C7R27 C6R7

C7T93 C7D12 C7E1 C7D8 C6R10

C7T32 C7E5 C7T83 C7R91

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

C7R26 C7D5 C7D11 C7T5

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

C7E9 C7R121 C7T84 C7R5

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

C7T1 C7R23 C6T1 C7R4

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%

C7R49 C7T9 C6R44 C7R52 C6T10 C7T21

C7R44 C7R22 C6R32 C7R51 C7T22 C6T2

C6R29 C7R35 C7R102 C7R50 C7T27 C7T10

C6R28 C7R34 C7R81 C6T6 C7R48 C7R111

C6R17 C7R19 C7R68 C6R36 C7T51

C7R76 C7R43 C7R69 C6R23 C7T37

C6R39 C6R16 C7R57 C7R58 C7R89

C6R42 C6R19 C6R20 C7R59 C6T25

C7R67 C7R61 C6R21 C7R60 C7R99

C7T3 C6R35 C6T26 C7T2 C7R100

C7R31 C7T25 C7T38 C7T58 C6T17 C7R66 C7T7 C7T29

C7T54 C6T24 C7R110 C6R24 C7R95 C6T4 C7T14 C7T30

C6T16 C6T13 C6T14 C7T56 C6T18 C7T15 C7T12 C7T31

C7R56 C7R20 C7T28 C7T50 C7R101 C7T24 C7T13

C6R26 C7R42 C7R14 C7R106 C7T57 C6T11 C7T8

C6T9 C7R41 C7T49 C7T11 C7T55 C7R74 C7T16

C6T3 C7R40 C6T22 C7T40 C7R83 C6R30 C7T17

C7R21 C7R39 C7T41 C7R75 C7T39 C7R82 C7T18

C6R41 C6T21 C7R33 C7T47 C7T26 C7T23 C7T19

C6R13 C6R12 C7R32 C7T46 C7T48 C7R65 C7T20

V_GPUCORE GPU, FSB

C4R27 C4R33 C4R45 C4T22 C5R18 C4R65 C4R60 C4T13

GPU, VIDEO + PCIEX + EEPROM + JTAG

33 IN PEX_SB_GPU_L1_DP B27 PEX_RX1_DP PEX_TX1_DP B26 PEX_GPU_SB_L1_DP_C C4D2

GPU, MEMORY CONTROLLER 0 PARTITION A & B

AK6 MA_VREF1 AG33 MB_VREF1

GPU, MEMORY CONTROLLER 1 PARTITION C & D

G1 MC_VREF1 AF1 MD_VREF1

GPU, PLL POWER + FSB POWER

GPU, CORE POWER + MEM POWER

C4R37 C4R17 C4R21 C4R22 C5R16 C4T5 C6E2 C6E1 C4T17

C4T25 C4R36 C4R41 C4T19 C4R40 C4R56 C5R2 C5D5

C4T11 C4R34 C4R35 C4T18 C5R8 C4T4 C5R1

C4T3 C4R42 C4R67 C4R62 C4R9 C4R58 C5R3

C4R18 C4T1 C4T2 C5R17 C5R9 C5R6

MEMORY PARTITION A, TOP

1 1 C3F3 C4F9 C4F11 C4F7 C3F1 C4F1 C4F6 C4F3