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FALCON(SCH_1):PAGE1
RULES:
1.)
2.)
3.)
(APPLIED WHEN POSSIBLE)
MSB TO LSB IS TOP TO BOTTOM
WHEN POSSIBLE: INPUTS ON LEFT,
ORDER OF PAGES=CHIP INTERFACES,
OUTPUTS ON RIGHT
TERMINATION, POWER, DECOUPLING PLEASE
FALCON
REFER TO THE XENON DESIGN SPEC
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS BOM RELEASE DATE XX/XX/06 PB NUMBER X80XXXX-00X
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE SIGNATURE DATE
10.)
12.)
13.)
SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
SUFFIX _P FOR P JUNCTION
SUFFIX _EN FOR ENABLE
DRN BY MICROSOFT XBOX
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS CHK BY TITLE
15.) PWRGD FOR POWER GOOD SCH, PBA, FALCON
ENGR
APVD
DRAWING
FALCON_FABD APVD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=COVER PAGE] Tue May 08 18:21:43 2007 APVD
CONFIDENTIAL
FALCON_RETAIL 1/82 1.0
CR-2 : @FALCON_LIB.FALCON(SCH_1):PAGE2
RJ45/USB AVIP
CONN CONN
FAN
CONN
* THIS IS OUT OF DATE * POWER
CONN
ENET
ENET_CLK(25MHZ) CLOCK DIAGRAM
PHY
GPU VR
DEBUG
CONN ANA
ANA
BCKUP
STBY_CLK(48MHZ) GPU VR
CNTL
SB SATA_CLK_REF(25MHZ)
SATA_CLK_DP/DN(100MHZ)
DVD PCIEX_CLK_DP/DN(100MHZ)
SATA AUD_CLK(24.576MHZ)
CONN CPU_CLK_DP/DN(100MHZ) RISCWATCH
PIX_CLK_OUT_DP/DN(100MHZ) CONN
GPU_CLK_DP/DN (100MHZ)
DVD
PWR
CONN MC_CLK1_DP/DN(800MHZ)
MC_CLK0_DP/DN(800MHZ)
ANA
BCKUP MEM
CLAM C+D
MD_CLK1_DP/DN(800MHZ)
MD_CLK0_DP/DN(800MHZ)
GPU CPU CPU
VR
MA_CLK1_DP/DN(800MHZ)
MA_CLK0_DP/DN(800MHZ)
MB_CLK1_DP/DN(800MHZ)
MB_CLK0_DP/DN(800MHZ)
1P8 VR
FLSH
HDD
CONN
TITAN JTAG
3P3 VR CONN
GAME
CONN
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
<PAGE_TITLE=CLOCK DIAGRAM> Tue May 08 11:47:32 2007
CONFIDENTIAL
FALCON_RETAIL 2/82 1.0
CR-3 : @FALCON_LIB.FALCON(SCH_1):PAGE3
RJ45/USB AVIP
CONN CONN POWER
FAN CONN
CONN
RESET/ENABLE DIAGRAM
EXT_PWR_ON_N
ENET AUD_CLAMP
PHY ENET_RST_N AUDIO PSU_V12P0_EN
AUD_RST_N DAC
GPU VR
HANA_CLK_OE
HANA_RST_N
HANA VREG_GPU_EN_N
GPU VR
CNTL
SMC_RST_N
SB_RST_N
DVD
SATA
SB VREG_GPU_PWRGD
EXT_PWR_ON_N
CONN CPU_CHECKSTOP_N
CPU_RST_N
CPU_PWRGD
GPU_RST_N RISCWATCH
DVD GPU_RST_DONE CONN
PWR
SMC_DBG_EN
CONN
VREG_CPU_PWRGD
CPU
VREG_3P3_EN
MEM_RST VR
MEM_SCAN_EN
MEM
CLAM C+D
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN
GPU CPU
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN
MEM_SCAN_EN
HDD 3P3 MEM_RST
CONN VR
CPU_PWRGD
TITAN JTAG
MEM CONN
DEBUG CLAM A+B
CONN VREG_1P8_EN_N VMEM VR EFUSE VR
VREG_5P0_EN_N CPU VR
5P0 VR CNTL
VREG_EFUSE_EN
VREG_CPU_EN
GAME
CONN
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=RESET/ENABLE DIAGRAM] Tue May 08 11:47:32 2007
CONFIDENTIAL
FALCON_RETAIL 3/82 1.0
CR-4 : @FALCON_LIB.FALCON(SCH_1):PAGE4
58 OUT CPU_RST_V1P1_N
34 CPU_RST_N 1 R7R4 2
CPU, CLOCKS + EEPROM + STRAPPING
IN
3.92K 1% R6D4
402 CH 1 27 IN CPU_CLK_DP 1 2
1 1 R7R16 2 C7R112
FT2P11 FTP 360PF 0 5% CPU_CLK_DP_C
6.19K 1% 10% 402 CH
1 50V
FT2P12 FTP 402 CH 2 EMPTY
603
CPU_PWRGD 1 R7R10 2 R6D5
34 IN CPU_PWRGD_V1P1_N
27 IN CPU_CLK_DN1 2
3.92K 1%
402 CH 0 5%
V_GPUCORE 1 R7R11 2 1 402 CH
C7R113
360PF U7D1 1 OF 10 IC
6.19K 1% 10%
V_GPUCORE 402 CH 50V CPU_CLK_DN_C TP7R1
2 R6R4 1
2 EMPTY LOKI
PROBE
603 AG23 AH15 CPU_CORE_IF_BGR_PLL 1
CORE_CLK_DP CORE_IF_BGR_PLL
1K 5% TP6D1 AF23 CORE_CLK_DN 2
1 1 402 CH PROBE
R6R6 1 AF1 C7 VREG_EFUSE_EN SMT
R6R9 2 HARD_RESET_B EFU_POWERON OUT 56
10K 2 R6R5 1 AD14 POWER_GOOD
10K 5%
5% 1K 5% SMT
EMPTY 402 CH FSB_CLK_DP AH21 AF20 CPU_FSB_HF_CLKOUT_DP
CH 402 FSB_CLK_DP FSB_HF_CLKOUT_DP OUT
402 2 FSB_CLK_DN AH20 FSB_CLK_DN FSB_HF_CLKOUT_DN AG20 CPU_FSB_HF_CLKOUT_DN OUT
2
CPU_FSB_CLK_SEL AE16 FSB_CLK_SEL FSB_IMPED_CAL_DP AH23 CPU_FSB_IMPED_CAL_DP OUT
FSB_IMPED_CAL_DN AH22 CPU_FSB_IMPED_CAL_DN OUT
1
CPU_EXT_CLK_EN AD16 EXT_CLK_EN
TP7R3
R6R8 CPU_PLL_BYPASS AF14 PROBE
1 PLL_BYPASS AH12 CPU_RES0_DP 1
10K RESISTOR0_DP
5% R6R7 1 CPU_PULSE_LIMIT_BYPASS AG14 RESISTOR0_DN AH13 CPU_RES0_DN 2
PULSE_LIMIT_BYPASS
EMPTY 10K R7R17 TP7R4
402 5% 10K 1 SMT PROBE
2 1 DB7R2
1
AF11 CPU_VDDS0_DP 1
CH 5% R7D1 VDDS0_DP
402 CH 10K R7D2 VDDS0_DN AH10 CPU_VDDS0_DN 2 TP7R2
2 402 5% 10K
5% V_GPUCORE PROBE
2 CH CPU_SYS_CONFIG0 AH3 SYS_CONFIG0 VDDS1_DP AG2 CPU_VDDS1_DP SMT 1
402 EMPTY CPU_SYS_CONFIG1 AE2 AH1 CPU_VDDS1_DN 2
402 SYS_CONFIG1 VDDS1_DN
2 2
CPU_POST_IN<0..4> SMT DB7R1
0 AF8 POST_IN0
V_GPUCORE 1 1 AG8 POST_IN1
TP
1 AH7 PSRO0_OUT AE14 CPU_PSRO0_OUT 1
R7R15 2 POST_IN2
100 R7R8 V_CPUCORE 3 AH8 POST_IN3
100 AH9
1
5% 4 POST_IN4
5% R7R9
EMPTY
402 EMPTY 10K
2 402 1 CPU_SPI_SI C4 B4 CPU_SPI_CLK 5%
2 4 IN SPI_SI SPI_CLK OUT 4
CH
R7T18 SPI_EN A3 CPU_SPI_EN OUT 4 402
LAYOUT: MUST BE ACCESSIBLE 10K SPI_SO A4 CPU_SPI_SO 4 2 2
5% OUT
CH AH18 CPU_TEMP_P R6E1
402 TEMP_DP IN 28 10K
2 OUT CPU_ANL_1 AE22 ANL_1 TEMP_DN AH19 CPU_TEMP_N OUT 28 5%
OUT CPU_ANL_2 AD22 ANL_2 CH
VID0 C5 CPU_VREG_APS0 OUT 50 402
57 CPU_SRVID A2 SRVID VID1 B6 CPU_VREG_APS1 50
1
OUT CPU_VGATE AH14 A5 CPU_VREG_APS2 OUT
VGATE VID2 OUT 50
VID3 B5 CPU_VREG_APS3 OUT 50
V_1P8 CPU_TEST_EN AF2 TE VID4 A6 CPU_VREG_APS4 OUT 50
V_GPUCORE VID5 C6 CPU_VREG_APS5 50
OUT
1 R7R1 2 1 1 1 FTP FT7T5
R7R14 X806937-001 1 FTP FT7T2 1 FTP FT7T4
1.40K 1% FTP FT7T1 1
402 CH 10K 1 FTP FT7T3
5% FTP FT7T7
1 1 1 1 1 CH CPU R7R1 R7R2
1 R7R2 2 402
R7R21 R7R12 R7R13 R7R22 R7R23 2 LOKI 1.40K 1K V_MEM V_MEM
10K 10K 10K 10K 10K 1K 1% ASPEN EMPTY 10K
5% 5% 5% 5% 5% 402 CH
CH CH CH CH CH
402 402 402 402 402
2 2 2 2 2 1 1
V_MEM C6F1
.1UF R7F3
0 1 2 3 4 10% 10K
U7E1 EMPTY 6.3V
2 X5R 5%
1 1 1 1 1 AT25020A 402 EMPTY
4 CPU_SPI_CLK R6E2 CPU_SPI_CLK_R 6 SCK VCC 8 402
R7R20 R7R5 R7R3 R7R19 R7R18 IN 5 2
1K 5% CPU_SPI_SO_R SDI
10K 10K 10K 10K 10K 402 CH SDO 2 CPU_SPI_SI_R 2 R7F7 1 CPU_SPI_SI 4
5% 5% 5% 5% 5% 7
OUT
HOLD_N* 1K 5%
EMPTY EMPTY EMPTY EMPTY EMPTY
4 CPU_SPI_SO R7E7 CPU_SPI_EN_R 1 CS_N* 402 CH
402 402 402 402 402 IN 3 4
1
2 2 2 2 2 1K 5% WP_N* GND
1 4 V_MEM 402 CH V_MEM R7F4
FT7R4 FTP 100
FT7R6 FTP
1 3
1 X800552-001 5%
2
FT7R2 FTP 2 R7E8 1 CH
FT7R1 FTP
1 1 1 402
FT7R5 FTP
1 0 R7U3 10K 5% 2
10K 402 CH
5%
CH 2 R7F1 1
402
2 R7F2 10K 5%
4 IN CPU_SPI_EN 402 EMPTY CPU_SPI_WP_N IN
1K 5%
402 CH
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] Tue May 08 18:24:08 2007
CONFIDENTIAL
FALCON_RETAIL 4/82 1.0
CR-5 : @FALCON_LIB.FALCON(SCH_1):PAGE5
CPU, FSB
U7D1 2 OF 10 IC
LOKI
X806937-001
V_GPUCORE
1 1 1 1 1 1 1 1 1 1 1
C6R15 C6R18 C6R14 C6R25 C6R37 C6T19 C6T7 C6T27 C6T33 C6T32 C6R6
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, FSB] Tue May 08 18:24:09 2007
CONFIDENTIAL
FALCON_RETAIL 5/82 1.0
CR-6 : @FALCON_LIB.FALCON(SCH_1):PAGE6
V_1P8
V_CPUPLL V_GPUCORE
U7D1 4 of 10 IC
FB7R1 1 1 1 LOKI
1 2 C7R115 C7R116 C7R114 AA25
.1UF .1UF .1UF VDD_FSB0
1K FB 10% 10% 10% VDD_FSB1 AB24
0.2A 603 6.3V 6.3V 6.3V AC25
2 X5R 2 X5R 2 X5R VDD_FSB2
1 0.7DCR 1 402 402 402 VDD_FSB3 AD24
C7R1 C7R7 AE25
.1UF 2.2UF VDD_FSB4
10% 10% VDD_FSB5 AF24
6.3V 6.3V AG25
2 X5R 2 X5R VDD_FSB6
402 ST7R1 603 VDD_FSB7 AH24
1 2 VDD_FSB8 B11
V_EFUSE VDD_FSB9 B15
SHORT VDD_FSB10 B19
2 R7T2 1 VDD_FSB11 B23
CPU_VDDE
VDD_FSB12 B27
FB6D1 10K 5% VDD_FSB13 C24
1 2 402 CH AH4 D8
VDD_IO VDD_FSB14
1K FB VDD_FSB15 D12
0.2A 603 A7 VDDE VDD_FSB16 D16
1 0.7DCR 1 B7 VDDE_SEC VDD_FSB17 D20
C6D1 C6D4 D25
.1UF 2.2UF VDD_FSB18
10% 10% V_CPU_CORE_HF_VDDA_PLL AG17 CORE_HF_VDDA_PLL VDD_FSB19 E24
6.3V 6.3V AF17 F25
2 X5R 2 X5R V_CPU_CORE_HF_GNDA_PLL CORE_HF_GNDA_PLL VDD_FSB20
402 603 VDD_FSB21 G24
ST6D1 V_CPU_CORE_IF_VDDA_PLL AH17 CORE_IF_VDDA_PLL VDD_FSB22 H25
1 2 V_CPU_CORE_IF_GNDA_PLL AH16 CORE_IF_GNDA_PLL VDD_FSB23 J24
VDD_FSB24 K25
SHORT V_CPU_FSB_HF_VDDA_PLL AD20 FSB_HF_VDDA_PLL VDD_FSB25 L24
V_CPU_FSB_HF_GNDA_PLL AE20 FSB_HF_GNDA_PLL VDD_FSB26 M25
VDD_FSB27 N24
FB6R1 V_CPU_FSB_IF_VDDA_PLL AD18 FSB_IF_VDDA_PLL VDD_FSB28 P25
1 2 V_CPU_FSB_IF_GNDA_PLL AE18 FSB_IF_GNDA_PLL VDD_FSB29 R24
1K FB VDD_FSB30 T24
0.2A 603 V_CPU_VDDA_RNG AH11 VDDA_RNG VDD_FSB31 U25
1 0.7DCR 1 V_CPU_GNDA_RNG AG11 GNDA_RNG VDD_FSB32 V24
C6R2 C6R4 W25
.1UF 2.2UF VDD_FSB33
10% 10% VDD_FSB34 Y24
6.3V 6.3V
2 X5R 2 X5R
402 ST6R1 603
1 2
SHORT
FB6R2
1 2
1K FB
0.2A 603
1 0.7DCR 1
C6R3 C6R5
.1UF 2.2UF
10% 10% X806937-001
6.3V 6.3V
2 X5R 2 X5R
402 603
ST6R2
1 2
SHORT
FB7D1
1 2
1K FB
0.2A 603
0.7DCR 1
C7D1 C7D2
1UF 2.2UF
10% 10%
16V 6.3V
EMPTY 2 X5R
603 603
ST7D1
1 2
SHORT
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, FSB POWER + PLL POWER] Tue May 08 18:24:09 2007
CONFIDENTIAL
FALCON_RETAIL 6/82 1.0
CR-7 : @FALCON_LIB.FALCON(SCH_1):PAGE7
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, CORE POWER] Tue May 08 18:24:10 2007
CONFIDENTIAL
FALCON_RETAIL 7/82 1.0
CR-8 : @FALCON_LIB.FALCON(SCH_1):PAGE8
CPU, POWER
U7D1 IC U7D1 IC
U7D1 IC
9 of 10 10 of 10
8 of 10
LOKI LOKI
LOKI
F22 VSS117 VSS175 L11 T4 VSS233 VSS291 Y20
AA1 VSS0 VSS58 AF3
F24 VSS118 VSS176 L13 T6 VSS234 VSS292 Y22
AA3 VSS1 VSS59 AF6
F26 VSS119 VSS177 L15 T8 VSS235
AA5 VSS2 VSS60 AF9
G1 VSS120 VSS178 L17 T10 VSS236
AA7 VSS3 VSS61 AF12
G3 VSS121 VSS179 L19 T12 VSS237
AA9 VSS4 VSS62 AF15
G5 VSS122 VSS180 L21 T14 VSS238
AA11 VSS5 VSS63 AF16
G7 VSS123 VSS181 L23 T16 VSS239
AA13 VSS6 VSS64 AF18
G9 VSS124 VSS182 M2 T18 VSS240
AA15 VSS7 VSS65 AF19
G11 VSS125 VSS183 M4 T20 VSS241
AA17 VSS8 VSS66 AF21
G13 VSS126 VSS184 M6 T22 VSS242
AA19 VSS9 VSS67 AF22
G15 VSS127 VSS185 M8 U1 VSS243
AA21 VSS10 VSS68 AG4
G17 VSS128 VSS186 M10 U3 VSS244
AA23 VSS11 VSS69 AG7
G19 VSS129 VSS187 M12 U5 VSS245
AA24 VSS12 VSS70 AG10
G21 VSS130 VSS188 M14 U7 VSS246
AA26 VSS13 VSS71 AG13
G23 VSS131 VSS189 M16 U9 VSS247
AB2 VSS14 VSS72 AG15
H2 VSS132 VSS190 M18 U11 VSS248
AB4 VSS15 VSS73 AG16
H4 VSS133 VSS191 M20 U13 VSS249
AB6 VSS16 VSS74 AG18
H6 VSS134 VSS192 M22 U15 VSS250
AB8 VSS17 VSS75 AG19
H8 VSS135 VSS193 M24 U17 VSS251
AB10 VSS18 VSS76 AG21
H10 VSS136 VSS194 M26 U19 VSS252
AB12 VSS19 VSS77 AG22
H12 VSS137 VSS195 N1 U21 VSS253
AB14 VSS20 VSS78 AG24
H14 VSS138 VSS196 N3 U23 VSS254
AB16 VSS21 VSS79 AG26
H16 VSS139 VSS197 N5 U24 VSS255
AB18 VSS22 VSS80 B2
H18 VSS140 VSS198 N7 U26 VSS256
AB20 VSS23 VSS81 B9
H20 VSS141 VSS199 N9 V2 VSS257
AB22 VSS24 VSS82 B13
H22 VSS142 VSS200 N11 V4 VSS258
AC1 VSS25 VSS83 B17
H24 VSS143 VSS201 N13 V6 VSS259
AC3 VSS26 VSS84 B21
H26 VSS144 VSS202 N15 V8 VSS260
AC5 VSS27 VSS85 B25
J1 VSS145 VSS203 N17 V10 VSS261
AC7 VSS28 VSS86 B28
J3 VSS146 VSS204 N19 V12 VSS262
AC9 VSS29 VSS87 D2
J5 VSS147 VSS205 N21 V14 VSS263
AC11 VSS30 VSS88 D6
J7 VSS148 VSS206 N23 V16 VSS264
AC13 VSS31 VSS89 D10
J9 VSS149 VSS207 P2 V18 VSS265
AC15 VSS32 VSS90 D14
J11 VSS150 VSS208 P4 V20 VSS266
AC17 VSS33 VSS91 D18
J13 VSS151 VSS209 P6 V22 VSS267
AC19 VSS34 VSS92 D22
J15 VSS152 VSS210 P8 W1 VSS268
AC21 VSS35 VSS93 D24
J17 VSS153 VSS211 P10 W3 VSS269
AC23 VSS36 VSS94 D26
J19 VSS154 VSS212 P12 W5 VSS270
AC24 VSS37 VSS95 E1
J21 VSS155 VSS213 P14 W7 VSS271
AC26 VSS38 VSS96 E3
J23 VSS156 VSS214 P16 W9 VSS272
AD2 VSS39 VSS97 E5
K2 VSS157 VSS215 P18 W11 VSS273
AD4 VSS40 VSS98 E7
K4 VSS158 VSS216 P20 W13 VSS274
AD6 VSS41 VSS99 E9
K6 VSS159 VSS217 P22 W15 VSS275
AD8 VSS42 VSS100 E11
K8 VSS160 VSS218 P24 W17 VSS276
AD10 VSS43 VSS101 E13
K10 VSS161 VSS219 P26 W19 VSS277
AD12 VSS44 VSS102 E15
K12 VSS162 VSS220 R1 W21 VSS278
AE3 VSS45 VSS103 E17
K14 VSS163 VSS221 R3 W23 VSS279
AE5 VSS46 VSS104 E19
K16 VSS164 VSS222 R5 W24 VSS280
AE7 VSS47 VSS105 E21
K18 VSS165 VSS223 R7 W26 VSS281
AE9 VSS48 VSS106 E23
K20 VSS166 VSS224 R9 Y2 VSS282
AE11 VSS49 VSS107 F2
K22 VSS167 VSS225 R11 Y4 VSS283
AE13 VSS50 VSS108 F4
K24 VSS168 VSS226 R13 Y6 VSS284
AE15 VSS51 VSS109 F6
K26 VSS169 VSS227 R15 Y8 VSS285
AE17 VSS52 VSS110 F8
L1 VSS170 VSS228 R17 Y10 VSS286
AE19 VSS53 VSS111 F10
L3 VSS171 VSS229 R19 Y12 VSS287
AE21 VSS54 VSS112 F12
L5 VSS172 VSS230 R21 Y14 VSS288
AE23 VSS55 VSS113 F14
L7 VSS173 VSS231 R23 Y16 VSS289
AE24 VSS56 VSS114 F16
L9 VSS174 VSS232 T2 Y18 VSS290
AE26 VSS57 VSS115 F18
VSS116 F20
X806937-001 X806937-001
X806937-001
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, POWER] Tue May 08 18:24:10 2007
CONFIDENTIAL
FALCON_RETAIL 8/82 1.0
CR-9 : @FALCON_LIB.FALCON(SCH_1):PAGE9
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
EMPTY X5R X5R X5R X5R
805 805 805 805 805
4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
EMPTY X5R X5R X5R X5R
805 805 805 805 805
C7R119
C7T33 C7D19 1 2 C7D4 C7R28
1 2 1 2 1 2 1 2
4.7UF 10%
4.7UF 10% 4.7UF 10% 6.3V 4.7UF 10% 4.7UF 10%
6.3V 6.3V EMPTY 6.3V 6.3V
X5R EMPTY 805 X5R X5R
805 805 805 805
C7D18
C7R2 C7D3 C7R90 1 2 C7R29
1 2 1 2 1 2 1 2
4.7UF 10%
4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 4.7UF 10%
6.3V 6.3V 6.3V EMPTY 6.3V
X5R X5R X5R 805 X5R
805 805 805 805
C7E2
C7R120 1 2 C7D7 C7T4
C7E10 1 2 1 2 1 2
1 2
4.7UF 10%
4.7UF 10% 6.3V 4.7UF 10% 4.7UF 10%
4.7UF 10% 6.3V X5R 6.3V 6.3V
6.3V EMPTY 805 X5R X5R
EMPTY 805 805 805
805
C7R30 C7R25
C7T6 C7R24 1 2 1 2
1 2 1 2
4.7UF 10% 4.7UF 10%
4.7UF 10% 4.7UF 10% 6.3V 6.3V
6.3V 6.3V X5R X5R
X5R X5R 805 805
805 805
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, DECOUPLING] Tue May 08 18:24:11 2007
CONFIDENTIAL
FALCON_RETAIL 9/82 1.0
CR-10 : @FALCON_LIB.FALCON(SCH_1):PAGE10
V_CPUCORE
CPU, DECOUPLING
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R
402 402 402 402 402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, DECOUPLING] Tue May 08 18:24:11 2007
CONFIDENTIAL
FALCON_RETAIL 10/82 1.0
CR-11 : @FALCON_LIB.FALCON(SCH_1):PAGE11
CPU, DECOUPLING
V_CPUCORE V_CPUVCS
N:EMPTIES
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R
402 402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R
402 402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R
402 402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CPU, DECOUPLING] Tue May 08 18:24:12 2007
CONFIDENTIAL
FALCON_RETAIL 11/82 1.0
CR-12 : @FALCON_LIB.FALCON(SCH_1):PAGE12
V_MEM
X801565-001
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, FSB] Tue May 08 18:24:13 2007
CONFIDENTIAL
FALCON_RETAIL 12/82 1.0
CR-13 : @FALCON_LIB.FALCON(SCH_1):PAGE13
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, VIDEO + PCIEX + EEPROM + JTAG] Tue May 08 18:24:13 2007
CONFIDENTIAL
FALCON_RETAIL 13/82 1.0
CR-14 : @FALCON_LIB.FALCON(SCH_1):PAGE14
20 19 BI MA_DQ23 AP15 MA_DQ23 MA_CLK1_DP AH10 MA_CLK1_DP OUT 20 22 21 BI MB_DQ23 AM23 MB_DQ23 MB_CLK1_DP AM33 MB_CLK1_DP OUT 22
20 19 BI MA_DQ22 AN15 MA_DQ22 MA_CLK1_DN AK10 MA_CLK1_DN OUT 20 22 21 BI MB_DQ22 AP23 MB_DQ22 MB_CLK1_DN AM34 MB_CLK1_DN OUT 22
20 19 BI MA_DQ21 AM15 MA_DQ21 MA_CLK0_DP AN12 MA_CLK0_DP OUT 19 22 21 BI MB_DQ21 AL23 MB_DQ21 MB_CLK0_DP AL33 MB_CLK0_DP OUT 21
20 19 BI MA_DQ20 AN14 MA_DQ20 MA_CLK0_DN AP12 MA_CLK0_DN OUT 19 22 21 BI MB_DQ20 AN23 MB_DQ20 MB_CLK0_DN AL34 MB_CLK0_DN OUT 21
20 19 BI MA_DQ19 AN16 MA_DQ19 MA_A<12..0> 22 21 BI MB_DQ19 AN25 MB_DQ19 MB_A<12..0>
MA_DQ18 AL13 AN4 12 OUT 19 20 MB_DQ18 AP22 AK32 12 OUT 21 22
20 19 BI MA_DQ18 MA_A12 22 21 BI MB_DQ18 MB_A12
20 19 BI MA_DQ17 AP17 MA_DQ17 MA_A11 AP7 11 22 21 BI MB_DQ17 AP25 MB_DQ17 MB_A11 AE29 11
20 19 BI MA_DQ16 AM13 MA_DQ16 MA_A10 AP4 10 22 21 BI MB_DQ16 AN21 MB_DQ16 MB_A10 AE34 10
20 19 OUT MA_WDQS2 AP14 MA_WDQS2 MA_A9 AP8 9 22 21 OUT MB_WDQS2 AN22 MB_WDQS2 MB_A9 AJ30 9
20 19 IN MA_RDQS2 AL15 MA_RDQS2 MA_A8 AN11 8 22 21 IN MB_RDQS2 AP24 MB_RDQS2 MB_A8 AK33 8
20 19 OUT MA_DM2 AP16 MA_DM2 MA_A7 AP9 7 22 21 OUT MB_DM2 AN24 MB_DM2 MB_A7 AJ33 7
MA_A6 AN10 6 MB_A6 AK34 6
20 19 BI MA_DQ15 AH16 MA_DQ15 MA_A5 AP11 5 22 21 BI MB_DQ15 AH26 MB_DQ15 MB_A5 AM32 5
20 19 BI MA_DQ14 AK20 MA_DQ14 MA_A4 AN9 4 22 21 BI MB_DQ14 AN32 MB_DQ14 MB_A4 AJ34 4
20 19 BI MA_DQ13 AK16 MA_DQ13 MA_A3 AN8 3 22 21 BI MB_DQ13 AK26 MB_DQ13 MB_A3 AE30 3
20 19 BI MA_DQ12 AH20 MA_DQ12 MA_A2 AN7 2 22 21 BI MB_DQ12 AN31 MB_DQ12 MB_A2 AF28 2
20 19 BI MA_DQ11 AH17 MA_DQ11 MA_A1 AN5 1 22 21 BI MB_DQ11 AN29 MB_DQ11 MB_A1 AE33 1
20 19 BI MA_DQ10 AJ19 MA_DQ10 MA_A0 AP6 0 22 21 BI MB_DQ10 AN30 MB_DQ10 MB_A0 AF29 0
20 19 BI MA_DQ9 AJ18 MA_DQ9 MA_BA<2..0> 22 21 BI MB_DQ9 AK28 MB_DQ9 MB_BA<2..0>
MA_DQ8 AH18 AP10 2 OUT 19 20 MB_DQ8 AK29 AH30 2 OUT 21 22
20 19 BI MA_DQ8 MA_BA2 22 21 BI MB_DQ8 MB_BA2
20 19 OUT MA_WDQS1 AK19 MA_WDQS1 MA_BA1 AM10 1 22 21 OUT MB_WDQS1 AK30 MB_WDQS1 MB_BA1 AH33 1
20 19 IN MA_RDQS1 AK17 MA_RDQS1 MA_BA0 AP5 0 22 21 IN MB_RDQS1 AN28 MB_RDQS1 MB_BA0 AG30 0
20 19 OUT MA_DM1 AM17 MA_DM1 22 21 OUT MB_DM1 AK27 MB_DM1
MA_CKE AN6 MA_CKE OUT 19 20 MB_CKE AG34 MB_CKE OUT 21 22
20 19 BI MA_DQ7 AK15 MA_DQ7 MA_WE_N* AJ9 MA_WE_N OUT 19 20 22 21 BI MB_DQ7 AK25 MB_DQ7 MB_WE_N* AF33 MB_WE_N OUT 21 22
20 19 BI MA_DQ6 AH11 MA_DQ6 MA_CAS_N* AK8 MA_CAS_N OUT 19 20 22 21 BI MB_DQ6 AH21 MB_DQ6 MB_CAS_N* AF32 MB_CAS_N OUT 21 22
20 19 BI MA_DQ5 AH15 MA_DQ5 MA_RAS_N* AK7 MA_RAS_N OUT 19 20 22 21 BI MB_DQ5 AH25 MB_DQ5 MB_RAS_N* AF31 MB_RAS_N OUT 21 22
20 19 BI MA_DQ4 AK11 MA_DQ4 MA_CS1_N* AK9 MA_CS1_N OUT 19 20 22 21 BI MB_DQ4 AK21 MB_DQ4 MB_CS1_N* AH34 MB_CS1_N OUT 21 22
20 19 BI MA_DQ3 AH13 MA_DQ3 MA_CS0_N* AL10 MA_CS0_N OUT 19 22 21 BI MB_DQ3 AH23 MB_DQ3 MB_CS0_N* AF34 MB_CS0_N OUT 21
20 19 BI MA_DQ2 AK12 MA_DQ2 22 21 BI MB_DQ2 AK22 MB_DQ2
20 19 BI MA_DQ1 AJ13 MA_DQ1 22 21 BI MB_DQ1 AJ23 MB_DQ1
20 19 BI MA_DQ0 AH12 MA_DQ0 22 21 BI MB_DQ0 AH22 MB_DQ0
20 19 OUT MA_WDQS0 AM12 MA_WDQS0 22 21 OUT MB_WDQS0 AM22 MB_WDQS0
20 19 IN MA_RDQS0 AJ14 MA_RDQS0 22 21 IN MB_RDQS0 AJ24 MB_RDQS0
20 19 OUT MA_DM0 AK14 MA_DM0 22 21 OUT MB_DM0 AK24 MB_DM0
1
X02125-001 1 X02125-001
R4T4
549 R5E2
1% 549 V_MEM
CH V_MEM 1% V_MEM
402 CH MEMORY CONTROLLER B, DECOUPLING
2 MA_VREF1 402
1 2 1
MB_VREF1
1 R4T7 R4T8
1 549 C4T47 C4T31 C4T34 C5T2 C4T39
C4T40 R4T3 1% 549
1 1% 4.7UF .22UF .22UF .22UF .22UF
.1UF 1.27K CH 10% 10% 10% 10% 10%
10% 1% V_MEM 1 CH 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V 402 C5E1 R5E1 402 X5R X5R X5R X5R X5R
2 X5R CH 2 MEMORY CONTROLLER A, DECOUPLING .1UF 1.27K 805 402 402 402 402
402 402 10% 1% 2
2 MA_VREF0 2 6.3V
CH
MB_VREF0
X5R
402 402
1 2 1
1 C4R3 C4T29 C4T32 C4T42 C4T44 1
R4T6 C4T45 4.7UF .22UF .22UF .22UF .22UF R4T5 C4T46
1.27K .1UF 10% 10% 10% 10% 10% 1.27K .1UF
1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 1% 10%
6.3V X5R X5R X5R X5R X5R 6.3V C4T33 C5T3 C5T4 C5T1
CH 2 X5R 805 402 402 402 402 CH 2 X5R .22UF .22UF .22UF .22UF
402 402 402 402 10% 10% 10% 10%
2 2 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R
402 402 402 402
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE C4T35 C4T27 C4T41 C4T43
R4T3, R4T6, R5E1, R4T5, R4R5, R4R2, R4T2, R4R7 .22UF .22UF .22UF .22UF
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
MEM VREF RESISTOR VALUE X5R X5R X5R X5R
THESE ARE THE GPU VREFS NEEDED 402 402 402 402
70% 1.27KOHM
FOR VARIOUS MEMORIES. CONSULT
72% 1.40KOHM
WITH MEM TEAM FOR USAGE.
73% 1.47KOHM
74% 1.54KOHM DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] Tue May 08 18:24:14 2007
CONFIDENTIAL
FALCON_RETAIL 14/82 1.0
CR-15 : @FALCON_LIB.FALCON(SCH_1):PAGE15
24 23 BI MC_DQ23 L1 MC_DQ23 MC_CLK1_DP J1 MC_CLK1_DP OUT 24 26 25 BI MD_DQ23 W2 MD_DQ23 MD_CLK1_DP AD6 MD_CLK1_DP OUT 26
24 23 BI MC_DQ22 K4 MC_DQ22 MC_CLK1_DN H1 MC_CLK1_DN OUT 24 26 25 BI MD_DQ22 W1 MD_DQ22 MD_CLK1_DN AD5 MD_CLK1_DN OUT 26
24 23 BI MC_DQ21 L2 MC_DQ21 MC_CLK0_DP F1 MC_CLK0_DP OUT 23 26 25 BI MD_DQ21 Y2 MD_DQ21 MD_CLK0_DP AE4 MD_CLK0_DP OUT 25
24 23 BI MC_DQ20 K3 MC_DQ20 MC_CLK0_DN E1 MC_CLK0_DN OUT 23 26 25 BI MD_DQ20 V4 MD_DQ20 MD_CLK0_DN AE3 MD_CLK0_DN OUT 25
24 23 BI MC_DQ19 N2 MC_DQ19 MC_A<12..0> 26 25 BI MD_DQ19 Y4 MD_DQ19 MD_A<12..0>
MC_DQ18 K2 A10 12 OUT 23 24 MD_DQ18 V1 AK5 12 OUT 25 26
24 23 BI MC_DQ18 MC_A12 26 25 BI MD_DQ18 MD_A12
24 23 BI MC_DQ17 N1 MC_DQ17 MC_A11 A7 11 26 25 BI MD_DQ17 AA1 MD_DQ17 MD_A11 AL2 11
24 23 BI MC_DQ16 J2 MC_DQ16 MC_A10 B10 10 26 25 BI MD_DQ16 V2 MD_DQ16 MD_A10 AM2 10
24 23 OUT MC_WDQS2 K1 MC_WDQS2 MC_A9 B6 9 26 25 OUT MD_WDQS2 V3 MD_WDQS2 MD_A9 AF5 9
24 23 IN MC_RDQS2 M1 MC_RDQS2 MC_A8 D1 8 26 25 IN MD_RDQS2 Y1 MD_RDQS2 MD_A8 AE5 8
24 23 OUT MC_DM2 M2 MC_DM2 MC_A7 A5 7 26 25 OUT MD_DM2 Y3 MD_DM2 MD_A7 AF2 7
MC_A6 A4 6 MD_A6 AF7 6
24 23 BI MC_DQ15 J6 MC_DQ15 MC_A5 C1 5 26 25 BI MD_DQ15 W6 MD_DQ15 MD_A5 AE7 5
24 23 BI MC_DQ14 N6 MC_DQ14 MC_A4 B5 4 26 25 BI MD_DQ14 AC7 MD_DQ14 MD_A4 AG2 4
24 23 BI MC_DQ13 J5 MC_DQ13 MC_A3 A6 3 26 25 BI MD_DQ13 W5 MD_DQ13 MD_A3 AM1 3
24 23 BI MC_DQ12 N7 MC_DQ12 MC_A2 B7 2 26 25 BI MD_DQ12 AC6 MD_DQ12 MD_A2 AJ2 2
24 23 BI MC_DQ11 L5 MC_DQ11 MC_A1 A9 1 26 25 BI MD_DQ11 AA5 MD_DQ11 MD_A1 AM3 1
24 23 BI MC_DQ10 M5 MC_DQ10 MC_A0 B8 0 26 25 BI MD_DQ10 AB5 MD_DQ10 MD_A0 AK2 0
24 23 BI MC_DQ9 L7 MC_DQ9 MC_BA<2..0> 26 25 BI MD_DQ9 AA7 MD_DQ9 MD_BA<2..0>
MC_DQ8 M3 B4 2 OUT 23 24 MD_DQ8 AB3 AG5 2 OUT 25 26
24 23 BI MC_DQ8 MC_BA2 26 25 BI MD_DQ8 MD_BA2
24 23 OUT MC_WDQS1 M7 MC_WDQS1 MC_BA1 A3 1 26 25 OUT MD_WDQS1 AB7 MD_WDQS1 MD_BA1 AH2 1
24 23 IN MC_RDQS1 K5 MC_RDQS1 MC_BA0 B9 0 26 25 IN MD_RDQS1 Y5 MD_RDQS1 MD_BA0 AJ5 0
24 23 OUT MC_DM1 K7 MC_DM1 26 25 OUT MD_DM1 Y7 MD_DM1
MC_CKE A8 MC_CKE OUT 23 24 MD_CKE AK1 MD_CKE OUT 25 26
24 23 BI MC_DQ7 H2 MC_DQ7 MC_WE_N* E7 MC_WE_N OUT 23 24 26 25 BI MD_DQ7 V7 MD_DQ7 MD_WE_N* AH1 MD_WE_N OUT 25 26
24 23 BI MC_DQ6 B2 MC_DQ6 MC_CAS_N* E8 MC_CAS_N OUT 23 24 26 25 BI MD_DQ6 P6 MD_DQ6 MD_CAS_N* AJ1 MD_CAS_N OUT 25 26
24 23 BI MC_DQ5 H5 MC_DQ5 MC_RAS_N* E9 MC_RAS_N OUT 23 24 26 25 BI MD_DQ5 V6 MD_DQ5 MD_RAS_N* AL1 MD_RAS_N OUT 25 26
24 23 BI MC_DQ4 C2 MC_DQ4 MC_CS1_N* E6 MC_CS1_N OUT 23 24 26 25 BI MD_DQ4 P5 MD_DQ4 MD_CS1_N* AH5 MD_CS1_N OUT 25 26
24 23 BI MC_DQ3 F2 MC_DQ3 MC_CS0_N* B3 MC_CS0_N OUT 23 26 25 BI MD_DQ3 U3 MD_DQ3 MD_CS0_N* AG1 MD_CS0_N OUT 25
24 23 BI MC_DQ2 E5 MC_DQ2 26 25 BI MD_DQ2 R5 MD_DQ2
24 23 BI MC_DQ1 F5 MC_DQ1 26 25 BI MD_DQ1 T5 MD_DQ1
24 23 BI MC_DQ0 E2 MC_DQ0 26 25 BI MD_DQ0 T7 MD_DQ0
24 23 OUT MC_WDQS0 D2 MC_WDQS0 26 25 OUT MD_WDQS0 R7 MD_WDQS0
24 23 IN MC_RDQS0 G5 MC_RDQS0 26 25 IN MD_RDQS0 U5 MD_RDQS0
24 23 OUT MC_DM0 G2 MC_DM0 26 25 OUT MD_DM0 U7 MD_DM0
2 1
X02125-001 X02125-001
R4R4 R3T2
549
1% V_MEM
549 V_MEM
1% V_MEM
CH
402 CH
1 402 MEMORY CONTROLLER D, DECOUPLING
2
2 1
MC_VREF1 MD_VREF1
R4R1 1
R4R6 1 1 1 1 1
1 549 549 C4T28 C4R15 C4R61 C4T38 C4R50
1% V_MEM 1 1% 4.7UF .22UF .22UF .22UF .22UF
1 R4R5 C4T36 R4T2 10% 10% 10% 10% 10%
C4R25 CH .1UF 1.27K CH 6.3V 6.3V 6.3V 6.3V 6.3V
.1UF 1.27K 402 MEMORY CONTROLLER C, DECOUPLING 10% 1% 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
10% 1% 1 6.3V 2 805 402 402 402 402
2 6.3V
CH
2 X5R CH
X5R MC_VREF0 402 402
402 402 2 MD_VREF0
2 1 1 1 1 1 1
1 C3R5 C4R38 C4R51 C4T14 C4R48
R4R2 C4R10 4.7UF .22UF .22UF .22UF .22UF 1
1.27K .1UF 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V R4R7 1
1% 10% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R C4R64 1 1 1 1
6.3V 1.27K .1UF C4T7 C4R31 C4R12 C4R19
CH 2 X5R 805 402 402 402 402
1% 10%
402 402 6.3V .22UF .22UF .22UF .22UF
2 CH 2 X5R 10% 10% 10% 10%
402 6.3V 6.3V 6.3V 6.3V
2
402 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
1 1 1 1
C4R23 C4R66 C4T12 C4R32
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE .22UF .22UF .22UF .22UF
10% 10% 10% 10%
R4T3, R4T6, R5E1, R4T5, R4R5, R4R2, R4T2, R4R7 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
GPU MEM VREF RESISTOR VALUE
THESE ARE THE GPU VREFS NEEDED
70% 1.27KOHM
FOR VARIOUS MEMORIES. CONSULT
72% 1.40KOHM
WITH MEM TEAM FOR USAGE.
73% 1.47KOHM
74% 1.54KOHM DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] Tue May 08 18:24:14 2007
CONFIDENTIAL
FALCON_RETAIL 15/82 1.0
CR-16 : @FALCON_LIB.FALCON(SCH_1):PAGE16
V_GPUCORE
FB4D1
1 2
120 FB
0.2A 603
0.5 DCR 1 1 1
C4D6 C4D5 C4D4
2.2UF .1UF 0.01UF
10% 10% 10%
6.3V 6.3V 16V
2 X5R 2 X5R 2 X7R
603 402 402
V_GPUCORE
V_GPUPCIE U4D1 8 OF 12 IC
GPU Y2 VERSION 1
FB4T1 VDD_FSB24 AA27
1 2 VDD_FSB23 AB28
120 FB V_PVDDA A20 PVDDA VDD_FSB22 AB32
0.2A 603
1 1 1 1 A21 PVSSA VDD_FSB21 AC27
0.5 DCR C4T48 C4T30 C4T37 C5R7 C4R8 AD28
.1UF .1UF VDD_FSB20
2.2UF .1UF 0.01UF 10% 10% C27 VDD_BSB1 VDD_FSB19 AD31
10% 10% 10% 6.3V 6.3V
6.3V 6.3V 16V 2 X5R 2 X5R C26 VSS_BSB1 VDD_FSB18 K28
2 X5R 2 X5R X7R 402 402 VDD_FSB17 K31
603 402 402 C25 L27
VDD_BSB0 VDD_FSB16
C24 VSS_BSB0 VDD_FSB15 M28
VDD_FSB14 M32
V_PVDDA_MEM AG10 PVDDA_MEM VDD_FSB13 N27
AG9 PVSSA_MEM VDD_FSB12 P28
FB4R1 VDD_FSB11 P31
1 2 V_PVDDA_ED A18 PVDDA_ED VDD_FSB10 R28
120 FB A19 PVSSA_ED VDD_FSB9 R32
0.2A 603 VDD_FSB8 T27
0.5 DCR 1 1
C4R68 C4R4 C4R6 B25 PVDDA_PEX VDD_FSB7 U28
2.2UF .1UF 0.01UF B24 PVSSA_PEX VDD_FSB6 U31
10% 10% 10%
6.3V 6.3V 16V VDD_FSB5 V27
2 X5R 2 X5R X7R V_PVDDA_FSB G34 PVDDA_FSB VDD_FSB4 V30
603 402 402 F34 W28
PVSSA_FSB VDD_FSB3
VDD_FSB2 W32
V_GPUPCIE VDD_FSB1 Y28
VDD_FSB0 Y31
X02125-001
1
C4R5 C4R7
.1UF 0.01UF
10% 10%
6.3V 16V
2 X5R X7R
402 402
FB5R1
1 2
120 FB
0.2A 603
0.5 DCR 1 1
C5R19 C5R13 C5R15
2.2UF .1UF 0.01UF
10% 10% 10%
6.3V 6.3V 16V
2 X5R 2 X5R X7R
603 402 402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, PLL POWER + FSB POWER] Tue May 08 18:24:14 2007
CONFIDENTIAL
FALCON_RETAIL 16/82 1.0
CR-17 : @FALCON_LIB.FALCON(SCH_1):PAGE17
V_GPUCORE V_GPUCORE
U4D1 IC
U4D1 IC 12 OF 12
U4D1 9 OF 12 IC
11 OF 12
GPU Y2 VERSION 1
GPU Y2 VERSION 1
E28 H14 GPU Y2 VERSION 1 F21 P18
VDD_CORE157 VDD_CORE78 V_MEM V_MEM VSS130 VSS65
D27 VDD_CORE156 VDD_CORE77 H16 A1 VSS260 VSS195 AJ15 F24 VSS129 VSS64 P22
E27 VDD_CORE155 VDD_CORE76 H18 AA3 VSS259 VSS194 AJ17 F26 VSS128 VSS63 P23
D26 H20 U4D1 10 OF 12 IC AA8 AJ20 F28 P24
VDD_CORE154 VDD_CORE75 VSS258 VSS193 VSS127 VSS62
E26 VDD_CORE153 VDD_CORE74 H22 GPU Y2 VERSION 1 AA11 VSS257 VSS192 AJ25 F31 VSS126 VSS61 P27
G26 VDD_CORE152 VDD_CORE73 H24 AA4 VDD_MEM111 VDD_MEM55 AL28 AA12 VSS256 VSS191 AJ27 G4 VSS125 VSS60 P32
G25 VDD_CORE151 VDD_CORE72 H26 AA6 VDD_MEM110 VDD_MEM54 AL30 AA13 VSS255 VSS190 AJ29 G7 VSS124 VSS59 R6
D24 VDD_CORE150 VDD_CORE71 H27 AB6 VDD_MEM109 VDD_MEM53 AL32 AA17 VSS254 VSS189 AJ31 G18 VSS123 VSS58 R11
E24 VDD_CORE149 VDD_CORE70 J27 AC5 VDD_MEM108 VDD_MEM52 AM5 AA18 VSS253 VSS188 AK4 G20 VSS122 VSS57 R12
E23 VDD_CORE148 VDD_CORE69 L11 AC8 VDD_MEM107 VDD_MEM51 AM7 AA22 VSS252 VSS187 AK18 G27 VSS121 VSS56 R13
G24 VDD_CORE147 VDD_CORE68 L12 AD4 VDD_MEM106 VDD_MEM50 AM9 AA23 VSS251 VSS186 AL3 G29 VSS120 VSS55 R17
D23 VDD_CORE146 VDD_CORE67 L13 AD7 VDD_MEM105 VDD_MEM49 AM16 AA24 VSS250 VSS185 AL5 G33 VSS119 VSS54 R18
G23 VDD_CORE145 VDD_CORE66 L17 AE8 VDD_MEM104 VDD_MEM48 AM19 AB4 VSS249 VSS184 AL7 H3 VSS118 VSS53 R22
F22 VDD_CORE144 VDD_CORE65 L18 AE28 VDD_MEM103 VDD_MEM47 AM26 AB8 VSS248 VSS183 AL9 H6 VSS117 VSS52 R23
G22 VDD_CORE143 VDD_CORE64 L22 AE31 VDD_MEM102 VDD_MEM46 AM27 AB14 VSS247 VSS182 AL12 H8 VSS116 VSS51 R24
G21 VDD_CORE142 VDD_CORE63 L23 AF3 VDD_MEM101 VDD_MEM45 AM29 AB15 VSS246 VSS181 AL16 H9 VSS115 VSS50 R27
D29 VDD_CORE141 VDD_CORE62 L24 AF6 VDD_MEM100 VDD_MEM44 AM31 AB16 VSS245 VSS180 AL19 H11 VSS114 VSS49 R31
E25 VDD_CORE140 VDD_CORE61 M11 AF27 VDD_MEM99 VDD_MEM43 AN2 AB19 VSS244 VSS179 AL22 H13 VSS113 VSS48 T4
AA14 VDD_CORE139 VDD_CORE60 M12 AF30 VDD_MEM98 VDD_MEM42 AP3 AB20 VSS243 VSS178 AL26 H15 VSS112 VSS47 T8
AA15 VDD_CORE138 VDD_CORE59 M13 AG4 VDD_MEM97 VDD_MEM41 C3 AB21 VSS242 VSS177 AL27 H17 VSS111 VSS46 T11
AA16 VDD_CORE137 VDD_CORE58 M17 AG7 VDD_MEM96 VDD_MEM40 C5 AB27 VSS241 VSS176 AL29 H19 VSS110 VSS45 T12
AA19 VDD_CORE136 VDD_CORE57 M18 AG13 VDD_MEM95 VDD_MEM39 C7 AB31 VSS240 VSS175 AL31 H21 VSS109 VSS44 T13
AA20 VDD_CORE135 VDD_CORE56 M22 AG15 VDD_MEM94 VDD_MEM38 C9 AC14 VSS239 VSS174 AM4 H23 VSS108 VSS43 T17
AA21 VDD_CORE134 VDD_CORE55 M23 AG17 VDD_MEM93 VDD_MEM37 C12 AC15 VSS238 VSS173 AM6 H25 VSS107 VSS42 T18
AB11 VDD_CORE133 VDD_CORE54 M24 AG20 VDD_MEM92 VDD_MEM36 C14 AC16 VSS237 VSS172 AM8 H28 VSS106 VSS41 T22
AB12 VDD_CORE132 VDD_CORE53 N11 AG23 VDD_MEM91 VDD_MEM35 C16 AC19 VSS236 VSS171 AM11 J4 VSS105 VSS40 T23
AB13 VDD_CORE131 VDD_CORE52 N12 AG25 VDD_MEM90 VDD_MEM34 C18 AC20 VSS235 VSS170 AM14 J8 VSS104 VSS39 T24
AB17 VDD_CORE130 VDD_CORE51 N13 AG28 VDD_MEM89 VDD_MEM33 D4 AC21 VSS234 VSS169 AM21 J28 VSS103 VSS38 U6
AB18 VDD_CORE129 VDD_CORE50 N17 AG32 VDD_MEM88 VDD_MEM32 D6 AC30 VSS233 VSS168 AM24 K6 VSS102 VSS37 U14
AB22 VDD_CORE128 VDD_CORE49 N18 AH3 VDD_MEM87 VDD_MEM31 D8 AD3 VSS232 VSS167 AM28 K27 VSS101 VSS36 U15
AB23 VDD_CORE127 VDD_CORE48 N22 AH6 VDD_MEM86 VDD_MEM30 E3 AD8 VSS231 VSS166 AM30 K32 VSS100 VSS35 U16
AB24 VDD_CORE126 VDD_CORE47 N23 AH8 VDD_MEM85 VDD_MEM29 F4 AD14 VSS230 VSS165 AN3 L3 VSS99 VSS34 U19
AC11 VDD_CORE125 VDD_CORE46 N24 AH9 VDD_MEM84 VDD_MEM28 F7 AD15 VSS229 VSS164 AN33 L8 VSS98 VSS33 U20
AC12 VDD_CORE124 VDD_CORE45 P14 AH14 VDD_MEM83 VDD_MEM27 F9 AD16 VSS228 VSS163 B19 L14 VSS97 VSS32 U21
AC13 VDD_CORE123 VDD_CORE44 P15 AH19 VDD_MEM82 VDD_MEM26 F11 AD19 VSS227 VSS162 B33 L15 VSS96 VSS31 U27
AC17 VDD_CORE122 VDD_CORE43 P16 AH24 VDD_MEM81 VDD_MEM25 F13 AD20 VSS226 VSS161 C4 L16 VSS95 VSS30 U32
AC18 VDD_CORE121 VDD_CORE42 P19 AH27 VDD_MEM80 VDD_MEM24 F15 AD21 VSS225 VSS160 C6 L19 VSS94 VSS29 V5
AC22 VDD_CORE120 VDD_CORE41 P20 AH29 VDD_MEM79 VDD_MEM23 G3 AD27 VSS224 VSS159 C8 L20 VSS93 VSS28 V14
AC23 VDD_CORE119 VDD_CORE40 P21 AH31 VDD_MEM78 VDD_MEM22 G6 AD32 VSS223 VSS158 C11 L21 VSS92 VSS27 V15
AC24 VDD_CORE118 VDD_CORE39 R14 AJ4 VDD_MEM77 VDD_MEM21 G8 AE6 VSS222 VSS157 C13 L28 VSS91 VSS26 V16
AD11 VDD_CORE117 VDD_CORE38 R15 AJ7 VDD_MEM76 VDD_MEM20 H4 AE27 VSS221 VSS156 C15 M4 VSS90 VSS25 V19
AD12 VDD_CORE116 VDD_CORE37 R16 AJ11 VDD_MEM75 VDD_MEM19 H7 AE32 VSS220 VSS155 C17 M8 VSS89 VSS24 V20
AD13 VDD_CORE115 VDD_CORE36 R19 AJ12 VDD_MEM74 VDD_MEM18 H10 AF4 VSS219 VSS154 C20 M14 VSS88 VSS23 V21
AD17 VDD_CORE114 VDD_CORE35 R20 AJ16 VDD_MEM73 VDD_MEM17 J3 AF8 VSS218 VSS153 C28 M15 VSS87 VSS22 W4
AD18 VDD_CORE113 VDD_CORE34 R21 AJ21 VDD_MEM72 VDD_MEM16 J7 AG3 VSS217 VSS152 C32 M16 VSS86 VSS20 W11
AD22 VDD_CORE112 VDD_CORE33 T14 AJ22 VDD_MEM71 VDD_MEM15 K8 AG6 VSS216 VSS151 D3 M19 VSS85 VSS21 W8
AD23 VDD_CORE111 VDD_CORE32 T15 AJ26 VDD_MEM70 VDD_MEM14 L4 AG8 VSS215 VSS150 D5 M20 VSS84 VSS19 W12
AD24 VDD_CORE110 VDD_CORE31 T16 AJ28 VDD_MEM69 VDD_MEM13 L6 AG12 VSS214 VSS149 D7 M21 VSS83 VSS18 W13
B18 VDD_CORE109 VDD_CORE30 T19 AJ32 VDD_MEM68 VDD_MEM12 M6 AG14 VSS213 VSS148 D9 M27 VSS82 VSS17 W17
B20 VDD_CORE108 VDD_CORE29 T20 AK3 VDD_MEM67 VDD_MEM11 N5 AG18 VSS212 VSS147 D19 M31 VSS81 VSS16 W18
C19 VDD_CORE107 VDD_CORE28 T21 AK13 VDD_MEM66 VDD_MEM10 N8 AG19 VSS211 VSS146 D21 N14 VSS80 VSS15 W22
C21 VDD_CORE106 VDD_CORE27 U11 AK23 VDD_MEM65 VDD_MEM9 P4 AG21 VSS210 VSS145 D31 N15 VSS79 VSS14 W23
C29 VDD_CORE105 VDD_CORE26 U12 AK31 VDD_MEM64 VDD_MEM8 P7 AG22 VSS209 VSS144 E4 N16 VSS78 VSS13 W24
C31 VDD_CORE104 VDD_CORE25 U13 AL4 VDD_MEM63 VDD_MEM7 R8 AG24 VSS208 VSS143 E18 N19 VSS77 VSS12 W27
C33 VDD_CORE103 VDD_CORE24 U17 AL6 VDD_MEM62 VDD_MEM6 T3 AG26 VSS207 VSS142 E20 N20 VSS76 VSS11 W31
C34 VDD_CORE102 VDD_CORE23 U18 AL8 VDD_MEM61 VDD_MEM5 T6 AG27 VSS206 VSS141 E22 N21 VSS75 VSS10 Y6
D17 VDD_CORE101 VDD_CORE22 U22 AL11 VDD_MEM60 VDD_MEM4 U4 AG29 VSS205 VSS140 E30 N28 VSS74 VSS9 Y11
D18 VDD_CORE100 VDD_CORE21 U23 AL14 VDD_MEM59 VDD_MEM3 U8 AG31 VSS204 VSS139 E32 N29 VSS73 VSS8 Y12
D20 VDD_CORE99 VDD_CORE20 U24 AL17 VDD_MEM58 VDD_MEM2 W3 AH4 VSS203 VSS138 F3 N30 VSS72 VSS7 Y13
D22 VDD_CORE98 VDD_CORE19 V11 AL21 VDD_MEM57 VDD_MEM1 W7 AH7 VSS202 VSS137 F6 P3 VSS71 VSS6 Y17
D30 VDD_CORE97 VDD_CORE18 V12 AL24 VDD_MEM56 VDD_MEM0 Y8 AH28 VSS201 VSS136 F8 P8 VSS70 VSS5 Y18
D32 VDD_CORE96 VDD_CORE17 V13 AH32 VSS200 VSS135 F10 P11 VSS69 VSS4 Y22
D34 VDD_CORE95 VDD_CORE16 V17 AJ3 VSS199 VSS134 F12 P12 VSS68 VSS3 Y23
E17 V18 X02125-001 AJ6 F14 P13 Y24
VDD_CORE94 VDD_CORE15 VSS198 VSS133 VSS67 VSS2
E19 VDD_CORE93 VDD_CORE14 V22 AJ8 VSS197 VSS132 F16 P17 VSS66 VSS1 Y27
E21 VDD_CORE92 VDD_CORE13 V23 AJ10 VSS196 VSS131 F19 VSS0 Y32
E31 VDD_CORE91 VDD_CORE12 V24
F17 VDD_CORE90 VDD_CORE11 W14
F18 W15 X02125-001 X02125-001
VDD_CORE89 VDD_CORE10
F20 VDD_CORE88 VDD_CORE9 W16
F23 VDD_CORE87 VDD_CORE8 W19
F25 VDD_CORE86 VDD_CORE7 W20
F27 VDD_CORE85 VDD_CORE6 W21
F29 VDD_CORE84 VDD_CORE5 Y14
F30 VDD_CORE83 VDD_CORE4 Y15
G19 VDD_CORE82 VDD_CORE3 Y16
G28 VDD_CORE81 VDD_CORE2 Y19
G32 VDD_CORE80 VDD_CORE1 Y20
H12 VDD_CORE79 VDD_CORE0 Y21
X02125-001 DRAWING
XENON_FABK MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, CORE POWER + MEM POWER] Tue May 08 18:24:14 2007
CONFIDENTIAL
FALCON_RETAIL 17/82 1.0
CR-18 : @FALCON_LIB.FALCON(SCH_1):PAGE18
GPU, DECOUPLING
V_GPUCORE V_GPUCORE V_GPUCORE
N:EMPTIES
C4R20 C4R11 C4R16 C4R28 C4R13 C4R54 C5D2 C6R47 C4R29
1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 10UF 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R X5R
402 402 402 402 402 402 805 805 805
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 10UF 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R X5R
402 402 402 402 402 402 805 805 805
C4R30
C4T15 C4R55 C4T26 C4T23 C5R10 C4R59 C5R5 C5D3 2 1
1 2 1 2 1 2 1 2 2 1 1 2 2 1 2 1
10UF 20%
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
X5R X5R X5R X5R X5R EMPTY X5R X5R 805
402 402 402 402 402 402 805 805
C4R69
C4R14 C4R47 C4T21 C4R44 C5R12 C4T6 C5R4 C5D4 2 1
1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1
10UF 20%
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
X5R X5R X5R X5R X5R EMPTY X5R X5R 805
402 402 402 402 402 402 805 805
C4R39 C5D6
1 2 C4T20 C4R46 C4T24 C4R24 C4R57 C5R20 2 1
1 2 1 2 1 2 1 2 1 2 2 1
.1UF 10% 4.7UF 10%
6.3V .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 6.3V
X5R 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
402 X5R X5R X5R X5R EMPTY X5R 805
402 402 402 402 402 805
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R X5R
402 402 402 402 402 402 805 805
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 805
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
EMPTY X5R X5R X5R X5R EMPTY X5R
402 402 402 402 402 402 805
C5R11
C4R49 C4T16 C4R63 C4R43 C5R14 C4T8 2 1
1 2 1 2 1 2 1 2 1 2 1 2
4.7UF 10%
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R
X5R X5R X5R X5R X5R EMPTY 805
402 402 402 402 402 402
.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 805
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=GPU, DECOUPLING] Tue May 08 18:24:14 2007
CONFIDENTIAL
FALCON_RETAIL 18/82 1.0
CR-19 : @FALCON_LIB.FALCON(SCH_1):PAGE19
1 1
R4F3 R4F4
60.4 60.4 V_MEM
1% 1%
CH CH
402 402 U4F1 IC
U4F1 IC
2 2
GDDR136
GDDR136 V1
MA_CLK0_DP T3 MA_DQ31 VDDQ<21> MF=0
14 IN MF=0 DQ31 BI 14 20 R12
T2 MA_DQ30 VDDQ<20>
DQ30 BI 14 20 R9 T12
R3 MA_DQ29 VDDQ<19> VSSQ<19>
DQ29 BI 14 20 R4 T9
R2 MA_DQ28 VDDQ<18> VSSQ<18>
DQ28 BI 14 20 R1 T4
M3 MA_DQ27 VDDQ<17> VSSQ<17>
DQ27 BI 14 20 N12 T1
N2 MA_DQ26 VDDQ<16> VSSQ<16>
DQ26 BI 14 20 N9 P12
L3 MA_DQ25 VDDQ<15> VSSQ<15>
DQ25 BI 14 20 V12 P9
M2 MA_DQ24 VDDQ<14> VSSQ<14>
DQ24 BI 14 20 N4 P4
J11 P2 MA_WDQS3 VDDQ<13> VSSQ<13>
CLK_DP WDQS3 IN 14 N1 P1
MA_CLK0_DN J10 P3 MA_RDQS3 VDDQ<12> VSSQ<12>
14 IN CLK_DN RDQS3 OUT 20 14 J9 L11
N3 MA_DM3 VDDQ<11> VSSQ<11>
DM3 IN 14 J4 L2
MEM_RST V9 VDDQ<10> VSSQ<10>
13 IN RESET E12 G11
T10 MA_DQ23 VDDQ<9> VSSQ<9>
MA_A<11..0> DQ23 BI 14 20 E9 G2
14 IN 11 L4 T11 MA_DQ22 VDDQ<8> VSSQ<8>
A11/A7 DQ22 BI 14 20 E4 D12
10 K2 R10 MA_DQ21 VDDQ<7> VSSQ<7>
A10/A8 DQ21 BI 14 20 E1 D9
9 M9 R11 MA_DQ20 VDDQ<6> VSSQ<6>
A9/A3 DQ20 BI 14 20 C12 D4
8 K11 M10 MA_DQ19 VDDQ<5> VSSQ<5>
A8/A10 DQ19 BI 14 20 C9 D1
7 L9 N11 MA_DQ18 VDDQ<4> VSSQ<4>
A7/A11 DQ18 BI 14 20 C4 B12
6 K10 L10 MA_DQ17 VDDQ<3> VSSQ<3>
A6/A2 DQ17 BI 14 20 C1 B9
5 H11 M11 MA_DQ16 VDDQ<2> VSSQ<2>
A5/A1 DQ16 BI 14 20 A12 B4
4 K9 P11 MA_WDQS2 VDDQ<1> VSSQ<1>
A4/A0 WDQS2 IN 14 A1 B1
3 M4 P10 MA_RDQS2 VDDQ<0> VSSQ<0>
A3/A9 RDQS2 OUT 20 14
2 K3 A2/A6 DM2 N10 MA_DM2 IN 14 V2 V3
1 H2 VDD<7> VSS<7>
A1/A5 M12 L12
0 K4 G10 MA_DQ15 VDD<6> VSS<6>
A0/A4 DQ15 BI 14 20 M1 L1
F11 MA_DQ14 VDD<5> VSS<5>
MA_BA<2..0> DQ14 BI 14 20 V11 G12
14 IN 2 H10 F10 MA_DQ13 VDD<4> VSS<4>
BA2/RAS_N DQ13 BI 14 20 F12 G1
1 G9 E11 MA_DQ12 VDD<3> VSS<3>
BA1/BA0 DQ12 BI 14 20 F1 A10
0 G4 C10 MA_DQ11 VDD<2> VSS<2>
BA0/BA1 DQ11 BI 14 20 A11 V10
C11 MA_DQ10 VDD<1> VSS<1>
DQ10 BI 14 20 A2 A3
MA_CKE H4 B10 MA_DQ9 VDD<0> VSS<0>
14 IN CKE/WE_N DQ9 BI 14 20
14 IN MA_WE_N H9 WE_N/CKE DQ8 B11 MA_DQ8 BI 14 20 K12 J3
MA_CAS_N F4 D11 MA_WDQS1 VDDA<1> NC<1>
14 IN CAS_N/CS_N WDQS1 IN 14 K1 J2
MA_RAS_N H3 D10 MA_RDQS1 VDDA<0> NC<0>
14 IN RAS_N/BA2 RDQS1 OUT 20 14
14 IN MA_CS0_N F9 CS_N/CAS_N DM1 E10 MA_DM1 IN 14 J12 VSSA<1>
MEM_SCAN_TOP_EN A9 G3 MA_DQ7 J1 VSSA<0>
12 IN MF DQ7 BI 14 20
DQ6 F2 MA_DQ6 BI 14 20
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MA_DQ5 BI 14 20
E2 MA_DQ4 X801995-011
DQ4 BI 14 20
19 IN MEM_A_VREF1 H1 VREF1 DQ3 C3 MA_DQ3 BI 14 20
20 IN MEM_A_VREF0 H12 VREF0 DQ2 C2 MA_DQ2 BI 14 20 MA_CS1_N
B3 MA_DQ1 IN 14
DQ1 BI 14 20
DQ0 B2 MA_DQ0 BI 14 20
WDQS0 D2 MA_WDQS0 IN 14
D3 MA_RDQS0 MX_CS1_N CONNECTED
RDQS0 OUT 20 14
E3 MA_DM0 TO J3 O SUPPORT 1G
DM0 IN 14
V_MEM RAM CONFIGS.
ZQ A4 MA_ZQ_TOP
1
1 X801995-011 R3F1
243
R4U4 1%
549 CH
1% 402
2 V_MEM
CH
402 PARTITION A DECOUPLING
2 V_MEM MEMORY A, TOP, DECOUPLING
MEM_A_VREF1 OUT 19 20
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=DUAL ETHERNET PHY] Tue May 08 18:24:15 2007
CONFIDENTIAL
FALCON_RETAIL 19/82 1.0
CR-20 : @FALCON_LIB.FALCON(SCH_1):PAGE20
V_MEM
MEMORY PARTITION A, BOTTOM
CHIP SELECT = 1, MIRROR FUNCTION = 1
1 1
R4U2 R4U3
60.4 60.4
1% 1%
CH CH
402 402
2 2 U4U1 IC
V_MEM
GDDR136
14 IN MA_CLK1_DP MF=1 DQ31 T3 MA_DQ23 BI 14 19 U4U1 IC
DQ30 T2 MA_DQ22 BI 14 19
R3 MA_DQ21 GDDR136
DQ29 BI 14 19 V1
R2 MA_DQ20 VDDQ<21> MF=1
DQ28 BI 14 19 R12
M3 MA_DQ19 VDDQ<20>
DQ27 BI 14 19 R9 T12
N2 MA_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 14 19 R4 T9
L3 MA_DQ17 VDDQ<18> VSSQ<18>
DQ25 BI 14 19 R1 T4
M2 MA_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 14 19 N12 T1
J11 P2 MA_WDQS2 VDDQ<16> VSSQ<16>
CLK_DP WDQS3 IN 14 N9 P12
MA_CLK1_DN J10 P3 MA_RDQS2 VDDQ<15> VSSQ<15>
14 IN CLK_DN RDQS3 OUT 19 14 V12 P9
N3 MA_DM2 VDDQ<14> VSSQ<14>
DM3 IN 14 N4 P4
MEM_RST V9 VDDQ<13> VSSQ<13>
13 IN RESET N1 P1
T10 MA_DQ31 VDDQ<12> VSSQ<12>
MA_A<11..0> DQ23 BI 14 19 J9 L11
14 IN 11 L9 T11 MA_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 14 19 J4 L2
10 K11 R10 MA_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 14 19 E12 G11
9 M4 R11 MA_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 14 19 E9 G2
8 K2 M10 MA_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 14 19 E4 D12
7 L4 N11 MA_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 14 19 E1 D9
6 K3 L10 MA_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 14 19 C12 D4
5 H2 M11 MA_DQ24 VDDQ<5> VSSQ<5>
A1/A5 DQ16 BI 14 19 C9 D1
4 K4 P11 MA_WDQS3 VDDQ<4> VSSQ<4>
A0/A4 WDQS2 IN 14 C4 B12
3 M9 P10 MA_RDQS3 VDDQ<3> VSSQ<3>
A9/A3 RDQS2 OUT 19 14 C1 B9
2 K10 N10 MA_DM3 VDDQ<2> VSSQ<2>
A6/A2 DM2 IN 14 A12 B4
1 H11 VDDQ<1> VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MA_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 14 19
MA_BA<2..0> DQ14 F11 MA_DQ6 BI 14 19 V2 V3
14 IN 2 H3 F10 MA_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 14 19 M12 L12
1 G4 E11 MA_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 14 19 M1 L1
0 G9 C10 MA_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 14 19 V11 G12
C11 MA_DQ2 VDD<4> VSS<4>
DQ10 BI 14 19 F12 G1
MA_CKE H9 B10 MA_DQ1 VDD<3> VSS<3>
14 IN WE_N/CKE DQ9 BI 14 19 F1 A10
MA_WE_N H4 B11 MA_DQ0 VDD<2> VSS<2>
14 IN CKE/WE_N DQ8 BI 14 19 A11 V10
MA_CAS_N F9 D11 MA_WDQS0 VDD<1> VSS<1>
14 IN CS_N/CAS_N WDQS1 IN 14 A2 A3
MA_RAS_N H10 D10 MA_RDQS0 VDD<0> VSS<0>
14 IN BA2/RAS_N RDQS1 OUT 19 14
14 IN MA_CS1_N F4 CAS_N/CS_N DM1 E10 MA_DM0 IN 14 K12 J3
VDDA<1> NC<1>
K1 VDDA<0> NC<0> J2
12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MA_DQ15 BI 14 19
DQ6 F2 MA_DQ14 BI 14 19 J12
MEM_SCAN_EN V4 F3 MA_DQ13 VSSA<1>
12 IN SCAN_EN DQ5 BI 14 19 J1
E2 MA_DQ12 VSSA<0>
DQ4 BI 14 19
20 IN MEM_A_VREF0 H1 VREF1 DQ3 C3 MA_DQ11 BI 14 19
19 IN MEM_A_VREF1 H12 VREF0 DQ2 C2 MA_DQ10 BI 14 19
B3 MA_DQ9 X801995-011
DQ1 BI 14 19
DQ0 B2 MA_DQ8 BI 14 19
WDQS0 D2 MA_WDQS1 IN 14
RDQS0 D3 MA_RDQS1 OUT 19 14
DM0 E3 MA_DM1 IN 14
ZQ A4 MA_ZQ_BOT
V_MEM
1
X801995-011 R3U1
243
1 1%
R4F1 CH
549 402
1% 2
V_MEM
CH
402
2 MEMORY A, BOTTOM, DECOUPLING
MEM_A_VREF0 OUT 19 20
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARTITION A, TOP] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
FALCON_RETAIL 20/82 1.0
CONFIDENTIAL
CR-21 : @FALCON_LIB.FALCON(SCH_1):PAGE21
1 1
R5F3 R5F4
60.4 60.4 V_MEM
1% 1%
CH CH
402 402 U5F1 IC
2 2
GDDR136
U5F1 IC V1 VDDQ<21> MF=1
R12 VDDQ<20>
GDDR136 R9 T12
MB_CLK0_DP T3 MB_DQ31 VDDQ<19> VSSQ<19>
14 IN MF=0 DQ31 BI 14 22 R4 T9
T2 MB_DQ30 VDDQ<18> VSSQ<18>
DQ30 BI 14 22 R1 T4
R3 MB_DQ29 VDDQ<17> VSSQ<17>
DQ29 BI 14 22 N12 T1
R2 MB_DQ28 VDDQ<16> VSSQ<16>
DQ28 BI 14 22 N9 P12
M3 MB_DQ27 VDDQ<15> VSSQ<15>
DQ27 BI 14 22 V12 P9
N2 MB_DQ26 VDDQ<14> VSSQ<14>
DQ26 BI 14 22 N4 P4
L3 MB_DQ25 VDDQ<13> VSSQ<13>
DQ25 BI 14 22 N1 P1
M2 MB_DQ24 VDDQ<12> VSSQ<12>
DQ24 BI 14 22 J9 L11
J11 P2 MB_WDQS3 VDDQ<11> VSSQ<11>
CLK_DP WDQS3 IN 14 J4 L2
MB_CLK0_DN J10 P3 MB_RDQS3 VDDQ<10> VSSQ<10>
14 IN CLK_DN RDQS3 OUT 22 14 E12 G11
N3 MB_DM3 VDDQ<9> VSSQ<9>
DM3 IN 14 E9 G2
MEM_RST V9 VDDQ<8> VSSQ<8>
13 IN RESET E4 D12
T10 MB_DQ23 VDDQ<7> VSSQ<7>
MB_A<11..0> DQ23 BI 14 22 E1 D9
14 IN 11 L4 T11 MB_DQ22 VDDQ<6> VSSQ<6>
A11/A7 DQ22 BI 14 22 C12 D4
10 K2 R10 MB_DQ21 VDDQ<5> VSSQ<5>
A10/A8 DQ21 BI 14 22 C9 D1
9 M9 R11 MB_DQ20 VDDQ<4> VSSQ<4>
A9/A3 DQ20 BI 14 22 C4 B12
8 K11 M10 MB_DQ19 VDDQ<3> VSSQ<3>
A8/A10 DQ19 BI 14 22 C1 B9
7 L9 N11 MB_DQ18 VDDQ<2> VSSQ<2>
A7/A11 DQ18 BI 14 22 A12 B4
6 K10 L10 MB_DQ17 VDDQ<1> VSSQ<1>
A6/A2 DQ17 BI 14 22 A1 B1
5 H11 M11 MB_DQ16 VDDQ<0> VSSQ<0>
A5/A1 DQ16 BI 14 22
4 K9 A4/A0 WDQS2 P11 MB_WDQS2 IN 14 V2 V3
3 M4 P10 MB_RDQS2 VDD<7> VSS<7>
A3/A9 RDQS2 OUT 22 14 M12 L12
2 K3 N10 MB_DM2 VDD<6> VSS<6>
A2/A6 DM2 IN 14 M1 L1
1 H2 VDD<5> VSS<5>
A1/A5 V11 G12
0 K4 G10 MB_DQ15 VDD<4> VSS<4>
A0/A4 DQ15 BI 14 22 F12 G1
F11 MB_DQ14 VDD<3> VSS<3>
MB_BA<2..0> DQ14 BI 14 22 F1 A10
14 IN 2 H10 F10 MB_DQ13 VDD<2> VSS<2>
BA2/RAS_N DQ13 BI 14 22 A11 V10
1 G9 E11 MB_DQ12 VDD<1> VSS<1>
BA1/BA0 DQ12 BI 14 22 A2 A3
0 G4 C10 MB_DQ11 VDD<0> VSS<0>
BA0/BA1 DQ11 BI 14 22
DQ10 C11 MB_DQ10 BI 14 22 K12 J3
MB_CKE H4 B10 MB_DQ9 VDDA<1> NC<1>
14 IN CKE/WE_N DQ9 BI 14 22 K1 J2
MB_WE_N H9 B11 MB_DQ8 VDDA<0> NC<0>
14 IN WE_N/CKE DQ8 BI 14 22
14 IN MB_CAS_N F4 CAS_N/CS_N WDQS1 D11 MB_WDQS1 IN 14
MB_RAS_N H3 D10 MB_RDQS1 J12 VSSA<1>
14 IN RAS_N/BA2 RDQS1 OUT 22 14 J1
MB_CS0_N F9 E10 MB_DM1 VSSA<0>
14 IN CS_N/CAS_N DM1 IN 14
1
1 R4F5
X801995-011
R5U4 243
549 1% V_MEM
1% CH
CH 402 MEMORY B, TOP, DECOUPLING
402 2 PARTITION B DECOUPLING
2 V_MEM
MEM_B_VREF1 OUT 21 22
C4F10 C5F5 C4F8 C4F5 C4F4 C5F2 C5F3 C5F4
.22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
10% 10% 10% 10% 10% 10% 10% 10%
1 1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C5F6 1 C5F8 X5R X5R X5R X5R X5R X5R X5R X5R
R5U3 4.7UF 220UF 402 402 402 402 402 402 402 402
C5U5 10% 20%
1.27K .1UF 6.3V 10V
1% 10% 2 X5R ELEC
6.3V 805
2 RDL
CH X5R
402 402
2
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARITION A, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
FALCON_RETAIL 21/82 1.0
CONFIDENTIAL
CR-22 : @FALCON_LIB.FALCON(SCH_1):PAGE22
V_MEM
1 1
R5U2 R5U1
60.4 60.4
1% 1%
CH CH
402 402 U5U1 IC
2 2 V_MEM
GDDR136
14 IN MB_CLK1_DP MF=1 DQ31 T3 MB_DQ23 BI 14 21 U5U1 IC
DQ30 T2 MB_DQ22 BI 14 21
R3 MB_DQ21 GDDR136
DQ29 BI 14 21 V1
R2 MB_DQ20 VDDQ<21> MF=1
DQ28 BI 14 21 R12
M3 MB_DQ19 VDDQ<20>
DQ27 BI 14 21 R9 T12
N2 MB_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 14 21 R4 T9
L3 MB_DQ17 VDDQ<18> VSSQ<18>
DQ25 BI 14 21 R1 T4
M2 MB_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 14 21 N12 T1
J11 P2 MB_WDQS2 VDDQ<16> VSSQ<16>
CLK_DP WDQS3 IN 14 N9 P12
MB_CLK1_DN J10 P3 MB_RDQS2 VDDQ<15> VSSQ<15>
14 IN CLK_DN RDQS3 OUT 21 14 V12 P9
N3 MB_DM2 VDDQ<14> VSSQ<14>
DM3 IN 14 N4 P4
MEM_RST V9 VDDQ<13> VSSQ<13>
13 IN RESET N1 P1
T10 MB_DQ31 VDDQ<12> VSSQ<12>
MB_A<11..0> DQ23 BI 14 21 J9 L11
14 IN 11 L9 T11 MB_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 14 21 J4 L2
10 K11 R10 MB_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 14 21 E12 G11
9 M4 R11 MB_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 14 21 E9 G2
8 K2 M10 MB_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 14 21 E4 D12
7 L4 N11 MB_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 14 21 E1 D9
6 K3 L10 MB_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 14 21 C12 D4
5 H2 M11 MB_DQ24 VDDQ<5> VSSQ<5>
A1/A5 DQ16 BI 14 21 C9 D1
4 K4 P11 MB_WDQS3 VDDQ<4> VSSQ<4>
A0/A4 WDQS2 IN 14 C4 B12
3 M9 P10 MB_RDQS3 VDDQ<3> VSSQ<3>
A9/A3 RDQS2 OUT 21 14 C1 B9
2 K10 N10 MB_DM3 VDDQ<2> VSSQ<2>
A6/A2 DM2 IN 14 A12 B4
1 H11 VDDQ<1> VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MB_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 14 21
MB_BA<2..0> DQ14 F11 MB_DQ6 BI 14 21 V2 V3
14 IN 2 H3 F10 MB_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 14 21 M12 L12
1 G4 E11 MB_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 14 21 M1 L1
0 G9 C10 MB_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 14 21 V11 G12
C11 MB_DQ2 VDD<4> VSS<4>
DQ10 BI 14 21 F12 G1
MB_CKE H9 B10 MB_DQ1 VDD<3> VSS<3>
14 IN WE_N/CKE DQ9 BI 14 21 F1 A10
MB_WE_N H4 B11 MB_DQ0 VDD<2> VSS<2>
14 IN CKE/WE_N DQ8 BI 14 21 A11 V10
MB_CAS_N F9 D11 MB_WDQS0 VDD<1> VSS<1>
14 IN CS_N/CAS_N WDQS1 IN 14 A2 A3
MB_RAS_N H10 D10 MB_RDQS0 VDD<0> VSS<0>
14 IN BA2/RAS_N RDQS1 OUT 21 14
14 IN MB_CS1_N F4 CAS_N/CS_N DM1 E10 MB_DM0 IN 14 K12 J3
VDDA<1> NC<1>
MEM_SCAN_BOT_EN A9 G3 MB_DQ15 K1 VDDA<0> NC<0> J2
12 IN MF DQ7 BI 14 21
DQ6 F2 MB_DQ14 BI 14 21 J12
MEM_SCAN_EN V4 F3 MB_DQ13 VSSA<1>
12 IN SCAN_EN DQ5 BI 14 21 J1
E2 MB_DQ12 VSSA<0>
DQ4 BI 14 21
22 IN MEM_B_VREF0 H1 VREF1 DQ3 C3 MB_DQ11 BI 14 21
21 IN MEM_B_VREF1 H12 VREF0 DQ2 C2 MB_DQ10 BI 14 21
B3 MB_DQ9 X801995-011
DQ1 BI 14 21
DQ0 B2 MB_DQ8 BI 14 21
WDQS0 D2 MB_WDQS1 IN 14
RDQS0 D3 MB_RDQS1 OUT 21 14
V_MEM DM0 E3 MB_DM1 IN 14
ZQ A4 MB_ZQ_BOT
1
1 R4U1
X801995-011
R5F1 243
549 1%
1% CH
CH 402 V_MEM
402 2
2
MEM_B_VREF0 21 22
MEMORY B, BOTTOM, DECOUPLING
OUT
1
C4U10 C5U4 C4U7 C4U4 C4U3 C5U1 C5U2 C5U3
R5F2 C5F1 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
1.27K .1UF 10% 10% 10% 10% 10% 10% 10% 10%
1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V X5R X5R X5R X5R X5R X5R X5R X5R
CH X5R 402 402 402 402 402 402 402 402
402 402
2
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARITION B, TOP] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
FALCON_RETAIL 22/82 1.0
CONFIDENTIAL
CR-23 : @FALCON_LIB.FALCON(SCH_1):PAGE23
1 1
R3D5 R3D4
60.4 60.4 V_MEM
1% 1%
CH CH U3D1 IC
402 402 U3D1 IC
2 2 GDDR136
GDDR136 V1 VDDQ<21> MF=0
15 IN MC_CLK0_DP MF=0 DQ31 T3 MC_DQ31 BI 15 24 R12 VDDQ<20>
DQ30 T2 MC_DQ30 BI 15 24 R9 VDDQ<19> VSSQ<19> T12
DQ29 R3 MC_DQ29 BI 15 24 R4 VDDQ<18> VSSQ<18> T9
DQ28 R2 MC_DQ28 BI 15 24 R1 VDDQ<17> VSSQ<17> T4
DQ27 M3 MC_DQ27 BI 15 24 N12 VDDQ<16> VSSQ<16> T1
DQ26 N2 MC_DQ26 BI 15 24 N9 VDDQ<15> VSSQ<15> P12
DQ25 L3 MC_DQ25 BI 15 24 V12 VDDQ<14> VSSQ<14> P9
DQ24 M2 MC_DQ24 BI 15 24 N4 VDDQ<13> VSSQ<13> P4
J11 CLK_DP WDQS3 P2 MC_WDQS3 IN 15 N1 VDDQ<12> VSSQ<12> P1
15 IN MC_CLK0_DN J10 CLK_DN RDQS3 P3 MC_RDQS3 OUT 24 15 J9 VDDQ<11> VSSQ<11> L11
DM3 N3 MC_DM3 IN 15 J4 VDDQ<10> VSSQ<10> L2
13 IN MEM_RST V9 RESET E12 VDDQ<9> VSSQ<9> G11
MC_A<11..0> DQ23 T10 MC_DQ23 BI 15 24 E9 VDDQ<8> VSSQ<8> G2
15 IN 11 L4 T11 MC_DQ22 E4 D12
A11/A7 DQ22 BI 15 24 VDDQ<7> VSSQ<7>
10 K2 A10/A8 DQ21 R10 MC_DQ21 BI 15 24 E1 VDDQ<6> VSSQ<6> D9
9 M9 A9/A3 DQ20 R11 MC_DQ20 BI 15 24 C12 VDDQ<5> VSSQ<5> D4
8 K11 A8/A10 DQ19 M10 MC_DQ19 BI 15 24 C9 VDDQ<4> VSSQ<4> D1
7 L9 A7/A11 DQ18 N11 MC_DQ18 BI 15 24 C4 VDDQ<3> VSSQ<3> B12
6 K10 A6/A2 DQ17 L10 MC_DQ17 BI 15 24 C1 VDDQ<2> VSSQ<2> B9
5 H11 A5/A1 DQ16 M11 MC_DQ16 BI 15 24 A12 VDDQ<1> VSSQ<1> B4
4 K9 A4/A0 WDQS2 P11 MC_WDQS2 IN 15 A1 VDDQ<0> VSSQ<0> B1
3 M4 A3/A9 RDQS2 P10 MC_RDQS2 OUT 24 15
2 K3 A2/A6 DM2 N10 MC_DM2 IN 15 V2 VDD<7> VSS<7> V3
1 H2 A1/A5 M12 VDD<6> VSS<6> L12
0 K4 A0/A4 DQ15 G10 MC_DQ15 BI 15 24 M1 VDD<5> VSS<5> L1
MC_BA<2..0> DQ14 F11 MC_DQ14 BI 15 24 V11 VDD<4> VSS<4> G12
15 IN 2 H10 F10 MC_DQ13 F12 G1
BA2/RAS_N DQ13 BI 15 24 VDD<3> VSS<3>
1 G9 BA1/BA0 DQ12 E11 MC_DQ12 BI 15 24 F1 VDD<2> VSS<2> A10
0 G4 BA0/BA1 DQ11 C10 MC_DQ11 BI 15 24 A11 VDD<1> VSS<1> V10
DQ10 C11 MC_DQ10 BI 15 24 A2 VDD<0> VSS<0> A3
15 IN MC_CKE H4 CKE/WE_N DQ9 B10 MC_DQ9 BI 15 24
15 IN MC_WE_N H9 WE_N/CKE DQ8 B11 MC_DQ8 BI 15 24 K12 VDDA<1> NC<1> J3
15 IN MC_CAS_N F4 CAS_N/CS_N WDQS1 D11 MC_WDQS1 IN 15 K1 VDDA<0> NC<0> J2
15 IN MC_RAS_N H3 RAS_N/BA2 RDQS1 D10 MC_RDQS1 OUT 24 15
15 IN MC_CS0_N F9 CS_N/CAS_N DM1 E10 MC_DM1 IN 15 J12 VSSA<1>
J1 VSSA<0>
12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MC_DQ7 BI 15 24
DQ6 F2 MC_DQ6 BI 15 24
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ5 BI 15 24 X801995-011
DQ4 E2 MC_DQ4 BI 15 24
23 IN MEM_C_VREF1 H1 VREF1 DQ3 C3 MC_DQ3 BI 15 24
24 IN MEM_C_VREF0 H12 VREF0 DQ2 C2 MC_DQ2 BI 15 24
DQ1 B3 MC_DQ1 BI 15 24
DQ0 B2 MC_DQ0 15 24
MC_CS1_N 15
D2 MC_WDQS0 BI IN
WDQS0 IN 15
RDQS0 D3 MC_RDQS0 OUT 24 15
DM0 E3 MC_DM0 IN 15
ZQ A4 MC_ZQ_TOP
V_MEM 1
X801995-011 R3D1
243
1 1% V_MEM
CH
R2R1 402 MEMORY C, TOP, DECOUPLING
549 2
1% PARTITION C DECOUPLING
CH V_MEM
402
2 C2E1 C3E2 C3E1 C3E3 C3E5 C3E7 C3E6 C2E3
MEM_C_VREF1 23 24 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
OUT 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R X5R X5R
1 1 1 402 402 402 402 402 402 402 402
1 C2D3 C3C5 C2E8
4.7UF 4.7UF 4.7UF
10% 10% 10%
R2R2 C2R9 6.3V 6.3V 6.3V
1.27K .1UF 2 X5R 2 X5R 2 X5R
1% 10% 805 805 805
6.3V
CH X5R
402 402
2
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARTITION B, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
FALCON_RETAIL 23/82 1.0
CONFIDENTIAL
CR-24 : @FALCON_LIB.FALCON(SCH_1):PAGE24
1 1
R2R4 R2R3
60.4 60.4
1% 1%
CH CH V_MEM
402 402 U3R1 IC
2 2 V_MEM
GDDR136
MC_CLK1_DP T3 MC_DQ23 U3R1 IC
15 IN MF=1 DQ31 BI 15 23
DQ30 T2 MC_DQ22 BI 15 23 1 GDDR136
DQ29 R3 MC_DQ21 BI 15 23 C3T4 V1 VDDQ<21> MF=1
DQ28 R2 MC_DQ20 15 23 .1UF R12 VDDQ<20>
M3 MC_DQ19 BI 10%
R9 T12
DQ27 BI 15 23 6.3V VDDQ<19> VSSQ<19>
DQ26 N2 MC_DQ18 15 23
2 X5R R4 VDDQ<18> VSSQ<18> T9
L3 MC_DQ17 BI 402 R1 T4
DQ25 BI 15 23 VDDQ<17> VSSQ<17>
DQ24 M2 MC_DQ16 BI 15 23 N12 VDDQ<16> VSSQ<16> T1
J11 CLK_DP WDQS3 P2 MC_WDQS2 IN 15 N9 VDDQ<15> VSSQ<15> P12
15 IN MC_CLK1_DN J10 CLK_DN RDQS3 P3 MC_RDQS2 OUT 23 15 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MC_DM2 IN 15 N4 VDDQ<13> VSSQ<13> P4
13 IN MEM_RST V9 RESET N1 VDDQ<12> VSSQ<12> P1
MC_A<11..0> DQ23 T10 MC_DQ31 BI 15 23 J9 VDDQ<11> VSSQ<11> L11
15 IN 11 L9 T11 MC_DQ30 J4 L2
A7/A11 DQ22 BI 15 23 VDDQ<10> VSSQ<10>
10 K11 A8/A10 DQ21 R10 MC_DQ29 BI 15 23 E12 VDDQ<9> VSSQ<9> G11
9 M4 A3/A9 DQ20 R11 MC_DQ28 BI 15 23 E9 VDDQ<8> VSSQ<8> G2
8 K2 A10/A8 DQ19 M10 MC_DQ27 BI 15 23 E4 VDDQ<7> VSSQ<7> D12
7 L4 A11/A7 DQ18 N11 MC_DQ26 BI 15 23 E1 VDDQ<6> VSSQ<6> D9
6 K3 A2/A6 DQ17 L10 MC_DQ25 BI 15 23 C12 VDDQ<5> VSSQ<5> D4
5 H2 A1/A5 DQ16 M11 MC_DQ24 BI 15 23 C9 VDDQ<4> VSSQ<4> D1
4 K4 A0/A4 WDQS2 P11 MC_WDQS3 IN 15 C4 VDDQ<3> VSSQ<3> B12
3 M9 A9/A3 RDQS2 P10 MC_RDQS3 OUT 23 15 C1 VDDQ<2> VSSQ<2> B9
2 K10 A6/A2 DM2 N10 MC_DM3 IN 15 A12 VDDQ<1> VSSQ<1> B4
1 H11 A5/A1 A1 VDDQ<0> VSSQ<0> B1
0 K9 A4/A0 DQ15 G10 MC_DQ7 BI 15 23
MC_BA<2..0> DQ14 F11 MC_DQ6 BI 15 23 V2 VDD<7> VSS<7> V3
15 IN 2 H3 F10 MC_DQ5 M12 L12
RAS_N/BA2 DQ13 BI 15 23 VDD<6> VSS<6>
1 G4 BA0/BA1 DQ12 E11 MC_DQ4 BI 15 23 M1 VDD<5> VSS<5> L1
0 G9 BA1/BA0 DQ11 C10 MC_DQ3 BI 15 23 V11 VDD<4> VSS<4> G12
DQ10 C11 MC_DQ2 BI 15 23 F12 VDD<3> VSS<3> G1
15 IN MC_CKE H9 WE_N/CKE DQ9 B10 MC_DQ1 BI 15 23 F1 VDD<2> VSS<2> A10
15 IN MC_WE_N H4 CKE/WE_N DQ8 B11 MC_DQ0 BI 15 23 A11 VDD<1> VSS<1> V10
15 IN MC_CAS_N F9 CS_N/CAS_N WDQS1 D11 MC_WDQS0 IN 15 A2 VDD<0> VSS<0> A3
15 IN MC_RAS_N H10 BA2/RAS_N RDQS1 D10 MC_RDQS0 OUT 23 15
15 IN MC_CS1_N F4 CAS_N/CS_N DM1 E10 MC_DM0 IN 15 K12 VDDA<1> NC<1> J3
K1 VDDA<0> NC<0> J2
12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MC_DQ15 BI 15 23
DQ6 F2 MC_DQ14 BI 15 23 J12 VSSA<1>
12 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ13 BI 15 23 J1 VSSA<0>
DQ4 E2 MC_DQ12 BI 15 23
24 IN MEM_C_VREF0 H1 VREF1 DQ3 C3 MC_DQ11 BI 15 23
23 IN MEM_C_VREF1 H12 VREF0 DQ2 C2 MC_DQ10 BI 15 23 X801995-011
DQ1 B3 MC_DQ9 BI 15 23
DQ0 B2 MC_DQ8 BI 15 23
WDQS0 D2 MC_WDQS1 IN 15
RDQS0 D3 MC_RDQS1 OUT 23 15
DM0 E3 MC_DM1 IN 15
V_MEM
ZQ A4 MC_ZQ_BOT
1
1 X801995-011 R3R1
243
R3D3 1%
549 CH
1% V_MEM
402
CH 2 MEMORY C, BOTTOM, DECOUPLING
402
2
MEM_C_VREF0 OUT 23 24
DRAWING
[PAGE_TITLE=MEMORY PARITION C, TOP] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT PROJECT NAME
FALCON_RETAIL
PAGE
24/82
REV
1.0
CONFIDENTIAL
CR-25 : @FALCON_LIB.FALCON(SCH_1):PAGE25
1 1
R3E5 R3E4 MD_CLK0
60.4 60.4 V_MEM
1% 1% STITCHING CAP
CH CH U3E1 IC
402 402 V_MEM
2 2 U3E1 IC GDDR136
V1 VDDQ<21> MF=0
GDDR136 R12
MD_CLK0_DP T3 MD_DQ31 VDDQ<20>
15 IN MF=0 DQ31 BI 15 26 1 R9 T12
T2 MD_DQ30 C3R3 VDDQ<19> VSSQ<19>
DQ30 BI 15 26 R4 T9
R3 MD_DQ29 .1UF VDDQ<18> VSSQ<18>
DQ29 BI 15 26 10% R1 T4
R2 MD_DQ28 VDDQ<17> VSSQ<17>
DQ28 BI 15 26 6.3V N12 T1
DQ27 M3 MD_DQ27 15 26
2 X5R VDDQ<16> VSSQ<16>
MD_DQ26 BI 402 N9 VDDQ<15> VSSQ<15> P12
DQ26 N2 15 26
L3 MD_DQ25 BI V12 VDDQ<14> VSSQ<14> P9
DQ25 BI 15 26 N4 P4
M2 MD_DQ24 VDDQ<13> VSSQ<13>
DQ24 BI 15 26 N1 P1
J11 P2 MD_WDQS3 VDDQ<12> VSSQ<12>
CLK_DP WDQS3 IN 15 J9 L11
MD_CLK0_DN J10 P3 MD_RDQS3 VDDQ<11> VSSQ<11>
15 IN CLK_DN RDQS3 OUT 26 15 J4 L2
N3 MD_DM3 VDDQ<10> VSSQ<10>
DM3 IN 15 E12 G11
MEM_RST V9 VDDQ<9> VSSQ<9>
13 IN RESET E9 G2
T10 MD_DQ23 VDDQ<8> VSSQ<8>
MD_A<11..0> DQ23 BI 15 26 E4 D12
15 IN 11 L4 T11 MD_DQ22 VDDQ<7> VSSQ<7>
A11/A7 DQ22 BI 15 26 E1 D9
10 K2 R10 MD_DQ21 VDDQ<6> VSSQ<6>
A10/A8 DQ21 BI 15 26 C12 D4
9 M9 R11 MD_DQ20 VDDQ<5> VSSQ<5>
A9/A3 DQ20 BI 15 26 C9 D1
8 K11 M10 MD_DQ19 VDDQ<4> VSSQ<4>
A8/A10 DQ19 BI 15 26 C4 B12
7 L9 N11 MD_DQ18 VDDQ<3> VSSQ<3>
A7/A11 DQ18 BI 15 26 C1 B9
6 K10 L10 MD_DQ17 VDDQ<2> VSSQ<2>
A6/A2 DQ17 BI 15 26 A12 B4
5 H11 M11 MD_DQ16 VDDQ<1> VSSQ<1>
A5/A1 DQ16 BI 15 26 A1 B1
4 K9 P11 MD_WDQS2 VDDQ<0> VSSQ<0>
A4/A0 WDQS2 IN 15
3 M4 A3/A9 RDQS2 P10 MD_RDQS2 OUT 26 15 V2 V3
2 K3 N10 MD_DM2 VDD<7> VSS<7>
A2/A6 DM2 IN 15 M12 L12
1 H2 VDD<6> VSS<6>
A1/A5 M1 L1
0 K4 G10 MD_DQ15 VDD<5> VSS<5>
A0/A4 DQ15 BI 15 26 V11 G12
F11 MD_DQ14 VDD<4> VSS<4>
MD_BA<2..0> DQ14 BI 15 26 F12 G1
15 IN 2 H10 F10 MD_DQ13 VDD<3> VSS<3>
BA2/RAS_N DQ13 BI 15 26 F1 A10
1 G9 E11 MD_DQ12 VDD<2> VSS<2>
BA1/BA0 DQ12 BI 15 26 A11 V10
0 G4 C10 MD_DQ11 VDD<1> VSS<1>
BA0/BA1 DQ11 BI 15 26 A2 A3
C11 MD_DQ10 VDD<0> VSS<0>
DQ10 BI 15 26
15 IN MD_CKE H4 CKE/WE_N DQ9 B10 MD_DQ9 BI 15 26 K12 J3
MD_WE_N H9 B11 MD_DQ8 VDDA<1> NC<1>
15 IN WE_N/CKE DQ8 BI 15 26 K1 J2
MD_CAS_N F4 D11 MD_WDQS1 VDDA<0> NC<0>
15 IN CAS_N/CS_N WDQS1 IN 15
15 IN MD_RAS_N H3 RAS_N/BA2 RDQS1 D10 MD_RDQS1 OUT 26 15 J12
MD_CS0_N F9 E10 MD_DM1 VSSA<1>
15 IN CS_N/CAS_N DM1 IN 15 J1 VSSA<0>
12 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MD_DQ7 BI 15 26
DQ6 F2 MD_DQ6 BI 15 26
MEM_SCAN_EN V4 F3 MD_DQ5 X801995-011
12 IN SCAN_EN DQ5 BI 15 26
DQ4 E2 MD_DQ4 BI 15 26
25 IN MEM_D_VREF1 H1 VREF1 DQ3 C3 MD_DQ3 BI 15 26
26 IN MEM_D_VREF0 H12 VREF0 DQ2 C2 MD_DQ2 BI 15 26
DQ1 B3 MD_DQ1 15 26
MD_CS1_N 15
B2 MD_DQ0 BI IN
DQ0 BI 15 26
WDQS0 D2 MD_WDQS0 IN 15
RDQS0 D3 MD_RDQS0 OUT 26 15
DM0 E3 MD_DM0 IN 15
ZQ A4 MD_ZQ_TOP
V_MEM 1
X801995-011 R3E1
243
1% V_MEM
1
CH
R2T4 402 MEMORY D, TOP, DECOUPLING
549 2 PARTITION D DECOUPLING
1% V_MEM
CH
402
2 C2D2 C2D1 C3D1 C3D2 C3D4 C3D6 C3D5 C2D4
.22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
MEM_D_VREF1 OUT 25 26 10% 10% 10% 10% 10% 10% 10% 10%
1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C2E2 X5R X5R X5R X5R X5R X5R X5R X5R
4.7UF 402 402 402 402 402 402 402 402
10%
1 6.3V
2 X5R
R2T3 C2T2 805
1.27K .1UF
1% 10%
6.3V
CH X5R
402 402
2
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARTITION C, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
FALCON_RETAIL 25/82 1.0
CONFIDENTIAL
CR-26 : @FALCON_LIB.FALCON(SCH_1):PAGE26
1 1
R2T5 R2T6
60.4 60.4
1% 1%
CH CH
402 402
2 2
U3T1 IC
GDDR136 V_MEM
15 IN MD_CLK1_DP MF=1 DQ31 T3 MD_DQ23 BI 15 25 U3T1 IC
DQ30 T2 MD_DQ22 BI 15 25
R3 MD_DQ21 GDDR136
DQ29 BI 15 25 V1
R2 MD_DQ20 VDDQ<21> MF=1
DQ28 BI 15 25 R12
M3 MD_DQ19 VDDQ<20>
DQ27 BI 15 25 R9 T12
N2 MD_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 15 25 R4 T9
L3 MD_DQ17 VDDQ<18> VSSQ<18>
DQ25 BI 15 25 R1 T4
M2 MD_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 15 25 N12 T1
J11 P2 MD_WDQS2 VDDQ<16> VSSQ<16>
CLK_DP WDQS3 IN 15 N9 P12
MD_CLK1_DN J10 P3 MD_RDQS2 VDDQ<15> VSSQ<15>
15 IN CLK_DN RDQS3 OUT 25 15 V12 P9
N3 MD_DM2 VDDQ<14> VSSQ<14>
DM3 IN 15 N4 P4
MEM_RST V9 VDDQ<13> VSSQ<13>
13 IN RESET N1 P1
T10 MD_DQ31 VDDQ<12> VSSQ<12>
MD_A<11..0> DQ23 BI 15 25 J9 L11
15 IN 11 L9 T11 MD_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 15 25 J4 L2
10 K11 R10 MD_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 15 25 E12 G11
9 M4 R11 MD_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 15 25 E9 G2
8 K2 M10 MD_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 15 25 E4 D12
7 L4 N11 MD_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 15 25 E1 D9
6 K3 L10 MD_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 15 25 C12 D4
5 H2 M11 MD_DQ24 VDDQ<5> VSSQ<5>
A1/A5 DQ16 BI 15 25 C9 D1
4 K4 P11 MD_WDQS3 VDDQ<4> VSSQ<4>
A0/A4 WDQS2 IN 15 C4 B12
3 M9 P10 MD_RDQS3 VDDQ<3> VSSQ<3>
A9/A3 RDQS2 OUT 25 15 C1 B9
2 K10 N10 MD_DM3 VDDQ<2> VSSQ<2>
A6/A2 DM2 IN 15 A12 B4
1 H11 VDDQ<1> VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MD_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 15 25
MD_BA<2..0> DQ14 F11 MD_DQ6 BI 15 25 V2 V3
15 IN 2 H3 F10 MD_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 15 25 M12 L12
1 G4 E11 MD_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 15 25 M1 L1
0 G9 C10 MD_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 15 25 V11 G12
C11 MD_DQ2 VDD<4> VSS<4>
DQ10 BI 15 25 F12 G1
MD_CKE H9 B10 MD_DQ1 VDD<3> VSS<3>
15 IN WE_N/CKE DQ9 BI 15 25 F1 A10
MD_WE_N H4 B11 MD_DQ0 VDD<2> VSS<2>
15 IN CKE/WE_N DQ8 BI 15 25 A11 V10
MD_CAS_N F9 D11 MD_WDQS0 VDD<1> VSS<1>
15 IN CS_N/CAS_N WDQS1 IN 15 A2 A3
MD_RAS_N H10 D10 MD_RDQS0 VDD<0> VSS<0>
15 IN BA2/RAS_N RDQS1 OUT 25 15
15 IN MD_CS1_N F4 CAS_N/CS_N DM1 E10 MD_DM0 IN 15 K12 VDDA<1> NC<1> J3
V_MEM K1 VDDA<0> NC<0> J2
12 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MD_DQ15 BI 15 25
DQ6 F2 MD_DQ14 BI 15 25
MEM_SCAN_EN V4 F3 MD_DQ13 J12 VSSA<1>
12 IN SCAN_EN DQ5 BI 15 25 J1
E2 MD_DQ12 VSSA<0>
DQ4 BI 15 25
26 IN MEM_D_VREF0 H1 VREF1 DQ3 C3 MD_DQ11 BI 15 25 1
MEM_D_VREF1 H12 C2 MD_DQ10 C2T7
25 IN VREF0 DQ2 BI 15 25 4.7UF
B3 MD_DQ9 10% X801995-011
DQ1 BI 15 25
B2 MD_DQ8 6.3V
DQ0 BI 15 25 2 X5R
WDQS0 D2 MD_WDQS1 IN 15 805
RDQS0 D3 MD_RDQS1 OUT 25 15
DM0 E3 MD_DM1 IN 15
V_MEM
ZQ A4 MD_ZQ_BOT
1
1 X801995-011 R3T1
243
R3E3 1% V_MEM
549 CH
1% 402 MEMORY D, BOTTOM, DECOUPLING
CH 2
402
2
MEM_D_VREF0 OUT 25 26
V_MEM C2R7 C3R1 C3R2 C3R4 C3R7 C3R6 C2R10 C2R8
.22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
10% 10% 10% 10% 10% 10% 10% 10%
MEMORY D, BOTTOM, DECOUPLING 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1 X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402
R3E2 C3E4
1.27K .1UF
1% 10%
6.3V C2R13 C2T6 C3E8 C3F5 C3U4 C4F14 C4F15 C4U12
CH X5R .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF
402 402 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402
DRAWING
PROJECT NAME PAGE REV
[PAGE_TITLE=MEMORY PARTITION D, BOTTOM] FALCON_FABD
Tue May 08 18:24:15 2007
MICROSOFT
FALCON_RETAIL 26/82 1.0
CONFIDENTIAL
CR-27 : @FALCON_LIB.FALCON(SCH_1):PAGE27
V_12P0
HANA, CLOCKS + STRAPPING R4C11 1 R4C9 2
33 5% 49.9 1%
402 CH 402 CH
HANA_V_12P0_DET_R
CPU_CLK_DP OUT 4
1 R4B9 2 1 R4B8 2 1 R4B2 2 1 FTP FT4P4
CPU_CLK_DN OUT 4
1 R3B2 2 ANA_VRST_OK 34 R4C12 1 R4C10 2
1% 1K 1% 75 1% 68.1 OUT
1M 5% CH 402 1 CH 402 CH 402 ANA_V12P0_PWRGD OUT 34 49
1 C4B13 SMC_RST_N 33 5% 49.9 1%
402 CH FT2P7 FTP 470PF OUT 34 47 58
5% 402 CH 402 CH
50V 1
Y3B1
1 R4B1 2
2 EMPTY 1
27MHZ 402 U4C2 1 OF 4 IC R2P3 FTP FT2N3
1 2 1K 1 R3C8 1 R3C16 2
5% 10K HANA 5% FTP FT3P4
CH 402
SM CH 33 5% 49.9 1%
XTAL HANA_V_12P0_DET B6 V_12P0_DET V_RST_OK E11 402 402 CH 402 CH
34 ANA_RST_N M2 CORE_RST_N* V_12P0_OK D10 2
2 2 IN 1 2 R2P1 1 GPU_CLK_DP OUT 13
C3B7 C3B6 FT4P1 FTP
HANA_POR_BYPASS E12 POR_BYPASS SMC_RST_N* M3 SMC_RST_N_R
GPU_CLK_DN
22PF 22PF OUT 13
5% 5% 10K 5%
1 50V
1 50V 402 CH R3C7 1 R3C15 2
NPO NPO
402 402 33 5% 49.9 1%
402 CH 402 CH
HANA_XTAL_IN P2 XTAL_IN CPU_CLK_DP R14 CPU_CLK_DP_R
HANA_XTAL_OUT R2 XTAL_OUT CPU_CLK_DN P14 CPU_CLK_DN_R
1 R4B4 2 AUD_CLK
1 1 1 OUT 36
C2P7 C3N6 C1P9 1 1 33 5%
.1UF .1UF .1UF C1B4 C2B14 1 402 CH 1
10% V_3P3STBY 10% 10% .1UF .1UF C2B17 C3B12
6.3V 6.3V 6.3V 10% 10% .1UF 10PF
2 X5R 2 X5R 2 X5R 6.3V 6.3V 10% 5%
402 402 402 2 X5R 2 X5R 2 6.3V
2 50V
402 402 X5R EMPTY
402 402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=HANA, CLOCKS + STRAPING] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 27/82 1.0
CR-28 : @FALCON_LIB.FALCON(SCH_1):PAGE28
28 OUT BRD_TEMP_N
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=HANA, VIDEO + FAN + JTAG] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 28/82 1.0
CR-29 : @FALCON_LIB.FALCON(SCH_1):PAGE29
R2A11
0 5%
603 CH
44 IN V_AVIP
NA 1
SM FTP FT2M2
1
CM2A1 EMPTY 1
FTP FT2M3 C2A9
.1UF
CMCHOKE 1 10%
28 IN HDMI_TX2_DP 1 2 FTP FT2M4 6.3V
1 2 X5R
FTP FT2M5 402
1
FTP FT3M1
28 IN HDMI_TX2_DN 4 3
1
ESDB-MLP7 ESDB-MLP7 FTP FT3M2
1
402 402 1
X801560-001 FTP FT3M3 J2A1 HDR
EG2A2 EG2A1
1 HDMI
R2A12 FTP FT3M4
DIO DIO HDMI_TX2_DP_CM 1 TMDS_DATA2_DP
0 5% 2 TMDS_DATA2_SHD
603 CH HDMI_TX2_DN_CM 3 TMDS_DATA2_DN
2
HDMI_TX1_DP_CM 4 TMDS_DATA1_DP
5 TMDS_DATA1_SHD
HDMI_TX1_DN_CM 6 TMDS_DATA1_DN
HDMI_TX0_DP_CM 7 TMDS_DATA0_DP
R2A13 8 TMDS_DATA0_SHD
HDMI_TX0_DN_CM 9 TMDS_DATA0_DN
0 5% HDMI_TXC_DP_CM 10 TMDS_CLK_DP
603 CH 11 TMDS_CLK_SHD
NA HDMI_TXC_DN_CM 12 TMDS_CLK_DN
SM 1 HDMI_CEC 13 CEC
DB3A1
CM2A2 EMPTY V_5P0STBY 14 RESERVED
15 SCL
HDMI_TX1_DP 1 CMCHOKE 2 16
28 IN SDA
17 DDC_CEC_GND
18 5VCC
HDMI_TX1_DN 4 3
1 1 19 HOT_PLUG_DET
28 IN ESDB-MLP7 ESDB-MLP7 R3M5 R3M6 23 ME4
1
1
402 402 2K 2K 22
X801560-001 ME3
EG2A4 EG2A3 1% 1% 1 21 ME2
HDMI_HPD_PIN
CH CH FTP FT4N2
R2A14 20 ME1
DIO DIO 402 402
2 2
0 5% X806395-002
603 CH HDMI_DDC_CLK
34 28 IN
2
2
28 44 IN HDMI_DDC_DATA 1
FTP FT2N6
34
44 1 R3M7 2 HDMI_HPD 28
OUT
R3A10 CR3M1 CR3M1 10K 5%
402 CH
0 5% 2 5
603 CH
NA 6 3 PGB0010603
1
1
SM 603
CM3A1 EMPTY 1 4 R3M1 EG3M1
ESDB-MLP7 47K
ESDB-MLP7
1
HDMI_TX0_DP CMCHOKE 402 5%
1
28 1 2 BAV99 BAV99 402 DIO
IN DIO EG3M2 DIO CH
EG3M3 402
EMPTY
2
2
HDMI_TX0_DN 4 3 EMPTY
28 IN ESDB-MLP7 ESDB-MLP7
1
402 402
2
X801560-001
2
EG3A2 EG3A1
R3A11 DIO DIO
0 5%
603 CH
2
R3A12
0 5%
603 CH
NA
SM
CM3A2 EMPTY
HDMI_TXC_DP 1 CMCHOKE 2
28 IN
28 IN HDMI_TXC_DN 4 3
ESDB-MLP7 ESDB-MLP7
1
402 402
X801560-001
EG3A4 EG3A3
R3A13 DIO DIO
0 5%
603 CH
2
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=CONN, HDMI] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 29/82 1.0
CR-30 : @FALCON_LIB.FALCON(SCH_1):PAGE30
120 FB
0.2A 603
1
C4N360.5 DCR C4N37 C4N35
4.7UF 4.7UF .1UF
10% 10% 10%
6.3V 6.3V 6.3V
X5R 2 X5R X5R
805 805 402 V_1P8STBY
U4C2 3 OF 4 IC
HANA
V_3P3 D12 VAA_RTS33S VAA_VID_PLL M12
D11 AVSS_RTS33S AVSS_VID_PLL M13
FB4N8
1 2 V_HANA_VAA_DAC33M E9 VAA_DAC33M3 VAA_GP_PLL R7
60 FB D9 VAA_DAC33M2 AVSS_GP_PLL P7
0.5A 603 C9 VAA_DAC33M1
0.1DCR 1 1
C4N15 C4N24 C4N23 C4N29 D8 AVSS_DAC33M1 VAA_100M_PLL_A N15
4.7UF 4.7UF .1UF .1UF AVSS_100M_PLL_A1 P15
10% 10% 10% 10% V_3P3STBY
6.3V 6.3V 6.3V 6.3V C7 VAA_DAC33M0 AVSS_100M_PLL_A0 R15
X5R 2 X5R X5R 2 X5R D7 AVSS_DAC33M0
805 805 402 402 R12
VAA_100M_PLL_D
C6 VAA_POR33S AVSS_100M_PLL_D P12
VDDIO18S_100M_PLL2 M10
VSSIO18S_100M_PLL2 N12
V_3P3STBY VDDIO18S_100M_PLL1 N9
VSSIO18S_100M_PLL1 N11
VDDIO18S_100M_PLL0 M9
VSSIO18S_100M_PLL0 N10
VDDIO18S_PIX_PLL L13
VSSIO18S_PIX_PLL L12
1 1
C4N25 C4N8
4.7UF 4.7UF
10% 10%
6.3V 6.3V X802478-003
2 X5R 2 X5R
805 805
V_1P8STBY
V_3P3STBY
1 1 1 1 1 1 1 1 1 1
C4N31 C4N17 C4P5 C4N34 C4P6 C4N27 C4P11 C4P1 C4P9 C4N26
1 1 1 1 1 1 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
C4N18 C4N19 C4N20 C4N28 C4P8 C4N42 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
.1UF .1UF .1UF .1UF .1UF .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10% 10% 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 402 402 402 402 402 402 402 402 402 402
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=HANA, POWER + DECOUPLING] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 30/82 1.0
CR-31 : @FALCON_LIB.FALCON(SCH_1):PAGE31
V_3P3STBY
U4C2 4 of 4 IC V_1P8STBY
HANA FB4P1
E13 VDD33S3 VDD18S21 L11 V_HANA_VDD18S 1 2
J4 VDD33S2 VDD18S20 K11 120 FB
J3 VDD33S1 VDD18S19 G11 0.5A 603
1 1 0.2DCR 1
C3 VDD33S0 VDD18S18 J10 C4P4 C4P3 C3P1
VDD18S17 H10 .1UF 4.7UF 4.7UF
V_3P3STBY 10% 10% 10%
F4 VSSIO_33S_AVSS8 VDD18S16 J9 6.3V 6.3V 6.3V
E4 VSSIO_33S_AVSS7 VDD18S15 H9 2 X5R 2 X5R 2 X5R
FB4N6 F3 M8 402 805 805
V_HANA_VDDIO_33S_AVCC
VSSIO_33S_AVSS6 VDD18S14
1 2 G4 VDDIO_33S_AVCC5 VDD18S13 L8
120 FB G3 VDDIO_33S_AVCC4 VDD18S12 K8
0.5A 603 C2 VDDIO_33S_AVCC3 VDD18S11 G8
0.2DCR 1 1 1 1
C4N3 C4N6 C4N9 C4N10 C4N14 C4N13 G1 VDDIO_33S_AVCC2 VDD18S10 F8
4.7UF 4.7UF .1UF .1UF .1UF .1UF C1 VDDIO_33S_AVCC1 VDD18S9 L7
10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V G2 VDDIO_33S_AVCC0 VDD18S8 K7
X5R 2 X5R X5R 2 X5R 2 X5R 2 X5R VDD18S7 G7
805 805 402 402 402 402 A1 F7
VSSIO_33S_AVSS5 VDD18S6
E1 VSSIO_33S_AVSS4 VDD18S5 J6
J1 VSSIO_33S_AVSS3 VDD18S4 H6
1 1 1 1 1 1 1
E2 VSSIO_33S_AVSS2 VDD18S3 J5 C4N32 C4N30 C4N41 C4N33 C4N22 C4P7 C4N21
V_3P3STBY E3 VSSIO_33S_AVSS1 VDD18S2 H5 .1UF .1UF .1UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10% 10%
J2 VSSIO_33S_AVSS0 VDD18S1 E5 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VDD18S0 D5 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
H3 402 402 402 402 402 402 402
VDDIO_33S_PVDD1
VSS35 J13
D3 VDDIO_33S_PVCC0 VSS34 H13
1
C4N5 C4N12 VSS33 G13
.1UF .1UF VSS32 F13
10% 10%
6.3V 6.3V H4 VSSIO_33S_PVSS1 VSS31 D13
2 X5R X5R D4 VSSIO_33S_PVSS0 VSS30 K12
402 402 M11
VSS29
VSS28 J11
VSS27 H11
VSS26 L10
V_3P3STBY VSS25 K10
VSS24 G10
FB4N7 VSS23 F10
1 2 V_HANA_VDDIO_33S_PVCC0 VSS22 E10
VSS21 L9
120 FB K9
0.2A 603 VSS20
0.5 DCR 1 VSS19 G9
C4N4 C4N7 C4N11 F9
4.7UF 4.7UF .1UF VSS18
10% 10% 10% VSS17 J8
6.3V 6.3V 6.3V H8
X5R 2 X5R X5R VSS16
805 805 402 VSS15 E8
VSS14 J7
VSS13 H7
VSS12 L6
VSS11 K6
VSS10 G6
VSS9 F6
VSS8 E6
VSS7 L5
VSS6 K5
VSS5 G5
VSS4 F5
VSS3 C5
VSS2 L4
VSS1 C4
VSS0 R1
X802478-003
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=HANA, POWER + DECOUPLING] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 31/82 1.0
CR-32 : @FALCON_LIB.FALCON(SCH_1):PAGE32
0.01UF 10% 0.01UF 10% .1UF 10% .1UF 10% .1UF 10% 0.01UF 10%
16V 16V 6.3V 6.3V 6.3V 16V
X7R X7R X5R X5R X5R X7R
402 402 402 402 402 402
C4N1
1 2
0.01UF 10%
16V
X7R
402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=POWER TRACE EMI CAPS] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 32/82 1.0
CR-33 : @FALCON_LIB.FALCON(SCH_1):PAGE33
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=SB, PCIEX + SMM GPIO + JTAG] Tue May 08 18:24:16 2007
CONFIDENTIAL
FALCON_RETAIL 33/82 1.0
CR-34 : @FALCON_LIB.FALCON(SCH_1):PAGE34
SB, SMC
V_3P3STBY V_12P0
27 IN STBY_CLK
27 IN SMC_RST_N
2
R8N17
C2P51 4.7K
1UF 5%
48 TRAY_OPEN 2 R2N15 1 10% CH
OUT 16V
33 5% X7R 402
402 CH 603 1
VREG_GPU_PWRGD IN 53
58 44 EXT_PWR_ON_N 2 R2N21 1
IN U2C1 2 of 6 IC 1 R8N18 2
10K 5%
402 CH SB VERSION 106 SMC_DBG_TXD OUT 58 1.82K 1%
HDMI_DDC_DATA 402 CH
29 44 28 BI Y12 STBY_CLK
1
FT2N5 FTP
FT2P10 FTP
1 C17 SMC_RST_N*
55 BI VREG_V5P0_VMEM_PWRGD
X02047-012 V_1P8STBY
FT3P3 FTP
1
FT2P25 FTP
1
FT1U2 FTP
1 1 1
1 R2P12 R2P13
DB1F1 10K 10K
34 BI DBG_LED0 5% 5%
V_5P0DUAL CH CH
V_5P0DUAL U1U1 IC 402 402
1 2 2 2
SN74LVC1G14
R2B16 R2B19 5 VCC D1F1 ARGON_DATA
2K 2K DBG_LED0 2 4 1 R1U3 2 2 1 BI 49
1% 1% 34 IN IN OUT DBG_LED0_LED_R DBG_LED0_LED
ARGON_CLK
3 1 BI 49
GND N/C 249 1% YELLOW
CH EMPTY 402 CH
V_3P3STBY 402 402 LED SM
2 1 X801189-001
U2C1 3 of 6 IC
SB VERSION 106
58 SPI_CLK U3 SPI_CLK SPI_MISO AB5 SPI_MISO_R
2 R1R1 1 SPI_MISO 58
IN SPI_MOSI Y5
OUT
58 IN SPI_MOSI 33 5%
58 IN SPI_SS_N AA5 SPI_SS_N*<UP> 402 CH
42 BI FLSH_DATA<7..0> Y2 W1 FLSH_CLE
7 FLSH_DATA7 FLSH_CLE 42
AA2
OUT
6 FLSH_DATA6
42 OUT FLSH_WP_N 5 Y3 FLSH_DATA5 FLSH_CE_N* V3 FLSH_CE_N OUT 42
4 AA3 FLSH_DATA4
V_3P3STBY 3 AB3 FLSH_DATA3 FLSH_RE_N* V2 FLSH_RE_N OUT 42
2 Y4 FLSH_DATA2
1 AA4 FLSH_DATA1 FLSH_WE_N* W3 FLSH_WE_N OUT 42
2 R1P7 1 0 AB4 FLSH_DATA0
2.2K 5% FLSH_ALE W2 FLSH_ALE OUT 42
402 CH Y1 FLSH_WP_N*<DN>
42 IN FLSH_READY V1 FLSH_READY
FT2P22 FTP
1 USBPORTA3_DP W18 USBA_D3_DP USBB_D4_DP Y10 ARGONPORT_DP BI 49
FT2P23 FTP
1 USBPORTA3_DN Y18 USBA_D3_DN USBB_D4_DN W10 ARGONPORT_DN BI 49
X02047-012
SB_USB_RBIAS
1
1 R2P14
C2P40
.1UF 113
10% 1%
6.3V
2 EMPTY CH
402 402
2
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=SB, FLASH + USB + SPI] Tue May 08 18:24:17 2007
CONFIDENTIAL
FALCON_RETAIL 35/82 1.0
CR-36 : @FALCON_LIB.FALCON(SCH_1):PAGE36
40 39 IN MII_COL B5 MII_COL
40 39 MII_CRS A5 MII_CRS
R2B11 I2S_MCLK 41
IN MII_MDIO OUT
40 39 E1 MII_MDIO 47 5%
BI
R2B14 402 CH I2S_BCLK 28 41
OUT
47 5%
27 IN AUD_CLK A8 AUD_CLK I2S_MCLK_OUT C7 I2S_MCLK_R 402 CH R2B13 I2S_SD
B8 I2S_BCLK_R OUT 28 41
I2S_BCLK_OUT
I2S_SD A7 I2S_SD_R 47 5%
B7 I2S_WS_R
R2B12 402 CH I2S_WS
I2S_WS OUT 28 41
SPDIF C6 SPDIF_R 47 5%
402 CH 1 R2B15 2 SB_SPDIF_OUT 28
OUT
47 5%
402 CH
48 IN HDD_RX_DP N4 SATA1_RX_DP SATA1_TX_DP R2 HDD_TX_DP OUT 48
48 IN HDD_RX_DN P4 SATA1_RX_DN SATA1_TX_DN P2 HDD_TX_DN OUT 48
1 R2N12 2
48 IN ODD_RX_DP L3 SATA0_RX_DP SATA0_TX_DP N1 ODD_TX_DP OUT 48 10K 5%
48 IN ODD_RX_DN M3 SATA0_RX_DN SATA0_TX_DN M1 ODD_TX_DN OUT 48 402 CH
SATA_RBIAS U2 1 R2N11 2
SATA_RBIAS
10K 5%
402 CH
1 1 R2N10 2
1 X02047-012
C1C9 R1C8 10K 5%
.1UF 374 402 CH
10% 1%
6.3V
2 X5R CH 1 R1B3 2
402 402
2 10K 5%
402 CH
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=SB, ETHERNET + AUDIO + SATA] Tue May 08 18:24:17 2007
CONFIDENTIAL
FALCON_RETAIL 36/82 1.0
CR-37 : @FALCON_LIB.FALCON(SCH_1):PAGE37
U2C1 5 of 6 IC V_1P8STBY
SB VERSION 106
VDD18_AUX<9> J18
VDD18_AUX<8> H18
VDD18_AUX<7> G18
V_1P8STBY VDD18_AUX<6> J15
VDD18_AUX<5> H15
VDD18_AUX<4> R14
VDD18_AUX<3> H14 SB BALLS V18 AND V19 ARE IN THE
VDD18_AUX<2> R12 LOWER RIGHT HAND OF THE CHIP
VDD18_AUX<1> P12 THEY HAVE BEEN ISOLATED
VDD18_AUX<0> R9 FOR BETTER POWER ROUTING
VDD33_AUX<14> V19 V_CMPAVDD33_USB IN 37
FB2P4 VDD33_AUX<13> D19
1 2 V_AVDD_USB AB13 AVDD_USB VDD33_AUX<12> V18
120 FB V_AVSS_USB AA13 AVSS_USB VDD33_AUX<11> F18 V_3P3STBY
0.2A 603 VDD33_AUX<10> E18
0.5 DCR 1 1
C2R5 C2P47 C2P43 V_CMPAVDD18_USB Y13 CMPAVDD18_USB VDD33_AUX<9> E17
4.7UF 2.2UF .1UF V_CMPAVSS18_USB W13 CMPAVSS18_USB VDD33_AUX<8> D17
10% 10% 10%
6.3V 6.3V 6.3V VDD33_AUX<7> E16
X5R 2 X5R 2 X5R V_VDD18_USB V13 E15
805 603 402 VDD18_USB<9> VDD33_AUX<6>
ST2P3 V12 W5
1 2 VDD18_USB<8> VDD33_AUX<5>
V11 VDD18_USB<7> VDD33_AUX<4> V5
V10 VDD18_USB<6> VDD33_AUX<3> U5
SHORT
V9 VDD18_USB<5> VDD33_AUX<2> W4
V8 VDD18_USB<4> VDD33_AUX<1> V4
FB2P3 V7 VDD18_USB<3> VDD33_AUX<0> U4
1 2 Y6 VDD18_USB<2>
W6 VDD18_USB<1> VSS_USB<25> Y19
120 FB V6 W19
0.2A 603 VDD18_USB<0> VSS_USB<24>
0.5 DCR 1 1 VSS_USB<23> AB18
C2P46 C2P42 Y14 AA18
2.2UF .1UF CMPAVDD33_USB VSS_USB<22>
10% 10% V_CMPAVSS33_USB W14 CMPAVSS33_USB VSS_USB<21> Y17
6.3V 6.3V W17
2 X5R 2 X5R VSS_USB<20>
ST2P2 603 402 V_VDD33_USB V17 VDD33_USB<3> VSS_USB<19> AB16
1 2 V16 VDD33_USB<2> VSS_USB<18> AA16
V15 VDD33_USB<1> VSS_USB<17> Y15
SHORT V14 VDD33_USB<0> VSS_USB<16> W15
VSS_USB<15> AB14 V_1P8STBY
FB2R1 VSS_USB<14> AA14
1 2 VSS_USB<13> AB12
120 FB VSS_USB<12> AA12
0.5A 603 VSS_USB<11> Y11
1 0.2DCR 1 1 1 1
C2R3 C2P45 C2P41 C2P2 C2P3 VSS_USB<10> W11
1
4.7UF 10UF .1UF .1UF .1UF VSS_USB<9> AB10 C2P38 C2P37 C2P23 C2P24
10% 20% 10% 10% 10% .1UF .1UF .1UF .1UF
6.3V 6.3V 6.3V 6.3V 6.3V VSS_USB<8> AA10
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 10% 10% 10% 10%
VSS_USB<7> Y9 6.3V 6.3V 6.3V 6.3V
805 805 402 402 402
VSS_USB<6> W9 2 X5R X5R X5R X5R
AB8 402 402 402 402
VSS_USB<5>
VSS_USB<4> AA8
VSS_USB<3> Y7
VSS_USB<2> W7
VSS_USB<1> AB6
VSS_USB<0> AA6
V_3P3STBY X02047-012
37 V_CMPAVDD33_USB V_3P3STBY
FB2P5 OUT
1 2
120 FB
0.2A 603
0.5 DCR 1 1 1
C2R6 C2P48 C2P44 C2P6 C2N1 C2P5
4.7UF 2.2UF .1UF .1UF .1UF .1UF
10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 X5R 2 X5R 2 X5R X5R X5R
805 ST2P4 603 402 402 402 402
1 2
SHORT
FB2P1
1 2
120 FB
0.2A 603
0.5 DCR 1 1
C2P8 C2P34 C2P35
4.7UF 2.2UF .1UF
10% 10% 10%
6.3V 6.3V 6.3V
X5R 2 X5R 2 X5R
805 603 402
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FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
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CONFIDENTIAL
FALCON_RETAIL 37/82 1.0
CR-38 : @FALCON_LIB.FALCON(SCH_1):PAGE38
V_SBPCIE V_1P8
V_1P8
1 R2C1 2 U2C1 6 of 6 IC
0 5% SB VERSION 106
603 CH U19 V_1P8
VDD18<17>
STUFF THIS WHEN NOT USING V_SBPCIE REGULATOR VDD18<16> U18
VDD18<15> R15
VDD18<14> P15
VDD18<13> M15
V_SBPCIE VDD18<12> M14 1 1 1 1 1 1 1 1 1
J12
C2P22 C2P21 C2P16 C2P28 C2P30 C2P17 C2P15 C2P33 C2P29
VDD18<11> .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
FB2P2 VDD18<10> H12 10% 10% 10% 10% 10% 10% 10% 10% 10%
1 2 L19 R11 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
V_AVDD_PEX AVDD_PEX VDD18<9> 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
120 FB V_AVSS_PEX L20 AVSS_PEX VDD18<8> J11 402 402 402 402 402 402 402 402 402
0.2A 603 VDD18<7> H11
1 0.5 DCR 1 1
C3P3 C2P27 C2P26 V_VDD_PEX_FB T18 VDD_PEX<4> VDD18<6> M9
4.7UF 2.2UF 0.01UF R18 VDD_PEX<3> VDD18<5> H9
10% 10% 10%
6.3V 6.3V 16V P18 VDD_PEX<2> VDD18<4> R8
2 X5R 2 X5R 2 X7R N18 VDD_PEX<1> VDD18<3> P8
805 ST2P1 603 402 M18 M8
1 2 VDD_PEX<0> VDD18<2> V_3P3
VDD18<1> J8
U22 VSS_PEX<15> VDD18<0> H8 V_1P8
SHORT
T22 VSS_PEX<14>
R22 VSS_PEX<13> VDD33<13> E14
R2P17 M22 VSS_PEX<12> VDD33<12> E13
0 5% K22 VSS_PEX<11> VDD33<11> E12
603 CH U21 VSS_PEX<10> VDD33<10> E11
1 1 1 1
C2P10 C2P32 C2P31 P21 VSS_PEX<9> VDD33<9> E10 C2P39 C2P20 C1D2
4.7UF .1UF 0.01UF N21 VSS_PEX<8> VDD33<8> E9 1UF 1UF 4.7UF
10% 10% 10% 10% 10% 10%
6.3V 6.3V 16V M21 VSS_PEX<7> VDD33<7> D8 16V 16V 6.3V
2 X5R 2 X5R 2 X7R K21 VSS_PEX<6> VDD33<6> D7 X7R X7R 2 X5R
805 402 402 T20 D6 603 603 805
VSS_PEX<5> VDD33<5>
R20 VSS_PEX<4> VDD33<4> G5
P20 VSS_PEX<3> VDD33<3> D5
T19 VSS_PEX<2> VDD33<2> F4
V_1P8 N19 VSS_PEX<1> VDD33<1> E4
M19 VSS_PEX<0> VDD33<0> D4
FB1P2
1 2 V_AVDD1_SATA J3 AVDD1_SATA VSS<41> N15
120 FB V_AVSS1_SATA J2 AVSS1_SATA VSS<40> L15
0.2A 603 VSS<39> K15 V_3P3
1 1 0.5 DCR 1 1
C1P2 C1P7 C1P5 C1P6 V_AVDD0_SATA H1 AVDD0_SATA VSS<38> P14
4.7UF 4.7UF 2.2UF .1UF V_AVSS0_SATA H2 AVSS0_SATA VSS<37> N14
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V VSS<36> L14
2 X5R 2 X5R 2 X5R 2 X5R V_CMPAVDD_SATA U1 CMPAVDD_SATA VSS<35> K14
805 805 ST1P2 603 402 T1 J14 1 1 1 1 1
V_CMPAVSS_SATA CMPAVSS_SATA VSS<34>
1 2 R13 C2P13 C2P12 C2P14 C2P11 C2P9
VSS<33> .1UF .1UF .1UF .1UF .1UF
V_VDD_SATA T5 VDD_SATA<5> VSS<32> P13 10% 10% 10% 10% 10%
SHORT 6.3V 6.3V 6.3V 6.3V 6.3V
R5 VDD_SATA<4> VSS<31> N13 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
P5 VDD_SATA<3> VSS<30> M13 402 402 402 402 402
FB1P1 N5 VDD_SATA<2> VSS<29> L13
1 2 M5 VDD_SATA<1> VSS<28> K13
L5 VDD_SATA<0> VSS<27> J13
120 FB H13
0.2A 603 VSS<26>
0.5 DCR 1 1 T4 VSS_SATA<18> VSS<25> N12
C1P3 C1P4 R4 M12
2.2UF .1UF VSS_SATA<17> VSS<24>
10% 10% M4 VSS_SATA<16> VSS<23> L12
6.3V 6.3V L4 K12
2 X5R 2 X5R VSS_SATA<15> VSS<22>
ST1P1 603 402 K4 VSS_SATA<14> VSS<21> P11
1 2 J4 VSS_SATA<13> VSS<20> N11 V_3P3
T3 VSS_SATA<12> VSS<19> M11
SHORT R3 VSS_SATA<11> VSS<18> L11
P3 VSS_SATA<10> VSS<17> K11
FB1P4 N3 VSS_SATA<9> VSS<16> R10
1 2 K3 VSS_SATA<8> VSS<15> P10
1
120 FB T2 VSS_SATA<7> VSS<14> N10 C2P4 C2P1
0.2A 603 N2 VSS_SATA<6> VSS<13> M10 1UF 4.7UF
0.5 DCR 1 1 10% 10%
C1P10 C1P11 M2 VSS_SATA<5> VSS<12> L10 16V 6.3V
2.2UF .1UF L2 VSS_SATA<4> VSS<11> K10 X7R 2 X5R
10% 10% 603 805
6.3V 6.3V K2 VSS_SATA<3> VSS<10> J10
2 X5R 2 X5R R1 VSS_SATA<2> VSS<9> H10
ST1P3 603 402 P1 P9
1 2 VSS_SATA<1> VSS<8>
L1 VSS_SATA<0> VSS<7> N9
VSS<6> L9
SHORT
VSS<5> K9
VSS<4> J9
FB1P3 VSS<3> N8
1 2 VSS<2> L8
VSS<1> K8
120 FB A15
0.5A 603 VSS<0>
0.2DCR 1 1 1
C1P8 C2P52 C1P1
10UF .1UF .1UF
20% 10% 10%
6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R X02047-012
805 402 402
DRAWING
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CONFIDENTIAL
FALCON_RETAIL 38/82 1.0
CR-39 : @FALCON_LIB.FALCON(SCH_1):PAGE39
ENET_RX_DP BI 40 45
1
R1A4
39 IN V_ENET 61.9
1%
1 CH
402
R1B7 2
1K
5% ENET_RX_DP_R
CH 1
402
ENET_CLK 2 R1M1
27 IN ENET_POAC_R 0
OUT 45
U1B2 IC
STUFF FOR BROADCOM 5%
1 EMPTY FOR ICS CH
1
ICS1893BF 603
R1B6 R1B13 2
10K 332
47 REF_IN VDD<7> 48 5% 1% ENET_RX_DN_R
1 ENET_REF_CLK_OUT 46 REF_OUT VDD<6> 45 CH
DB1N4 EMPTY
VDD<5> 33 402
ENET_RST_N 23 14 2 402 1
RESET_N* VDD<4>
2
33 IN
VDD<3> 7 R1A3
36 40 MII_RX_CLK 34 RXCLK VDD<2> 24 61.9
2 OUT MII_RXDV 32 22
ENET_ACT_N OUT 40 45 1%
36 40 OUT RXDV VDD<1>
R1C1 MII_RXER 35 18 CH
36 40 OUT RXER VDD<0> 402
10K 2
5% MII_RXD3 28 12
36 40 OUT RXD<3> TP_AP
CH MII_RXD2 29 13 ENET_RX_DN
402 36 40 OUT RXD<2> TP_AN BI 40 45
1 36 40 OUT MII_RXD1 30 RXD<1>
36 40 OUT MII_RXD0 31 RXD<0> TP_BP 16 ENET_TX_DP BI 40 45
TP_BN 15
36 40 OUT MII_TX_CLK 37 TXCLK
36 IN MII_TXEN 38 TXEN P4RD 8
1
P3TD 6
36 IN MII_MDC_CLK_OUT MII_TXD3 42 4 R1A1
36 IN TXD<3> P2LI
36 MII_TXD2 41 TXD<2> P1CL 3 61.9
IN MII_TXD1 40 1 ENET_P2LI_R 1%
39 V_ENET 2 R1B11 1 36 IN TXD<1> P0AC OUT 45
CH
IN 36 IN MII_TXD0 39 TXD<0> 402
1.5K 1% 10/100 9 1 2
402 CH
ENET_P4RD
ENET_P3TD
ENET_P1CL
27 MDC
MII_MDIO 26 36
R1B4
40 36 BI MDIO VSS<6> 10K ENET_TX_DP_R
VSS<5> 25 5%
36 40 OUT MII_COL 43 COL VSS<4> 21 CH 1
36 40 OUT MII_CRS 44 CRS VSS<3> 17 1 402
VSS<2> 11 2 R1M2
10 5
R1N6 0
ENET_AMDIX_EN AMDIX_EN VSS<1> 10K
2
ENET_LINK_N OUT 40 45 5%
2 R1N4 1 VSS<0> 5%
CH
20 100TCSR 1 CH 1 1 603
100 5% 19 10TCSR 402 2
402 EMPTY R1N7 2 R1N5 R1B5
10K 10K 1K ENET_TX_DN_R
5% 5% 5%
39 V_ENET 2 R1N1 1 ENET_100BIAS X800188-002 CH CH CH 1
IN 402 402 402
9.53K 1% ENET_10BIAS
2 2 2 R1A2
402 CH 61.9
1 ENET_10_100_OUT
EMPTY FOR BROADCOM 1%
2 2 DB1N3 STUFF FOR ICS CH
R1N2 R1N3 AMDIX_EN HAS INTERNAL PULLUP 402
1.58K 2K AUTO MDIX IS ON BY DEFAULT 2
1% 1%
CH CH
402 402 10/100 PIN IS FOR OUTPUT
1 1 INDICATION OF CONNECTION SPEED ENET_TX_DN BI 40 45
ETHERNET ADDRESS="00001"
V_3P3
FB1B1
1 2 V_ENET 39 40 45
OUT
60 0.1DCR
0.5A 603
2
1 C1A5 C1B1 C1N1 C1N4 C1N5 C1N3 C1N9 C1N11 C1N2 C1N10
100UF 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
16V 1 X5R X5R X5R X5R X5R X5R X5R X5R X5R
2 ELEC 805 402 402 402 402 402 402 402 402
RDL
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CONFIDENTIAL
FALCON_RETAIL 39/82 1.0
CR-40 : @FALCON_LIB.FALCON(SCH_1):PAGE40
BDCM PHY
V_1P8
FB1N1
2 1 ENET_AVDD OUT 40
60 EMPTY
0.5A 603
0.1DCR 1 1
C1N7 C1N14
1 10UF .1UF
C1N8 20% 10%
4.7UF 6.3V 6.3V
10% 2 EMPTY 2 EMPTY
6.3V 805 402
2 EMPTY
805
ENET_RDAC
39 36 BI MII_MDIO 13 MDIO GND 33
31 REGVDDIN 1
40 IN ENET_AVDD 32 REGVDDOUT R1N8
1.27K
1 1%
C1N6
.1UF X801554-002 LCC32 EMPTY
10% 402
2 6.3V 2
EMPTY
402
V_12P0
FB2B2
2 R2B3 1 AUD_CLAMP_R 1 2
1 C2B10
FTP FT2M1 10UF 1K 5% 1K 0.7DCR
V_3P3 1 2 AUD_AC_R 402 CH 0.2A 603
1
10% 10% 603 470PF
6.3V 6.3V 5%
2 X5R X5R EG2B2
50V
805 402 X801161-001 1 X7R
U2B1 IC EMPTY 402
XDAC
2
14 DVDD
FT2N2 FTP
1 36 IN I2S_WS 2 WS VOUTL 10 AUD_VOUTL AUD_L_OUT OUT 44
5 NC AVREF 8 AUD_ACAP
33 IN AUD_RST_N 12 PDN
AUD_DCAP 11 DVREF AGND 7
1 C2B4 C2B8 PGB0010603
.1UF 10UF
1
1 DGND 603
R2N3 C2B1 C2B6 10% 20%
2
10UF .1UF 6.3V 6.3V EG2B1
1K 20% 10% X5R X5R X801161-001
5% 6.3V 6.3V 402 805 R2B4
X5R X5R X02238-003 EMPTY 10K
CH 805 402 5%
402
2 CH 2
C2B2
2
402 470PF
1 5%
50V
1 X7R
402
C2B9
10UF
1 2 AUD_AC_L
FB2B1
20% 16V 2 R2B2 1 1 2
TANT AUD_CLAMP_L
1206 1K 5% 1K 0.7DCR
402 CH 0.2A 603
FT2P1 FTP
1
CR2M2
MBT3904 3 6
1 R2N23 2 AUD_CLAMP_B1
4.7K 5%
402 CH 1
R2N22
1K
5%
CH
402
2
DRAWING
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[PAGE_TITLE=SB OUT, AUDIO] Tue May 08 18:24:17 2007
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FALCON_RETAIL 41/82 1.0
CR-42 : @FALCON_LIB.FALCON(SCH_1):PAGE42
FLSH_DATA0 N: RETAIL=16MB
N: XDK=64MB
0 1
FLSH_DATA1
0 8MB 16MB
1 32MB 64MB
V_3P3STBY
X802184-001 TSOP
DRAWING
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[PAGE_TITLE=SB OUT, FLASH] Tue May 08 18:24:17 2007
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FALCON_RETAIL 42/82 1.0
CR-43 : @FALCON_LIB.FALCON(SCH_1):PAGE43
V_3P3STBY
BINDING BUTTON
FAN CONTROL
1 V_12P0
R5V3
SWITCH 10K
TH 5%
2 R3M9 1
CH
SW5G1 402 5.11K 1%
THR
2 402 CH
2
4 1 BINDSW_N_R
2 R5V2 1 BINDSW_N 34 FAN1_Q1_C 1 Q3M1
3 2
OUT MJD210
10K 5% 3 XSTR
402 CH 3
X02246-002 28 FAN1_OUT 1 Q3M2 3
IN MMBT2222
XSTR D3A1
2 1N4148
V_3P3STBY SOT23
1 DIO
FAN1_Q1_E
2
C4P14
ODD EJECT BUTTON 1 2700PF
10%
R1G4 50V J3A2
SWITCH 1 X7R 1X3HDR
10K 402 2
TH 5% V_FAN1 1
CH R3M8 2
SW1G1 402 100 3
2 5% C3A9
THR 1UF
CH 10% CONN
2 R1G3 1 402 16V
FAN1_FDBK_R
4 1 EJECTSW_N_R EJECTSW_N OUT 34 48 1 1 X7R
3 2 10K 5% R3A7 603
402 CH 30.1K
X02246-002 1%
CH
402
2 R4P2 1 2
IR MODULE
V_3P3STBY
TILT SWITCH, SOLICO N: X800550-003 HOLDS ALL THREE TILT SWITCHES
TMEC ONLY HAS 3 PINS WHICH REQUIRES A DIFFERENT
SM UNIQUE PART NUMBER TO HOLD THE SYMBOL NAME 1 R2V1 2
SW2G2 N: BOM MUST CALL OUT X800550-003 WITH QTY 1 AND V_IR
SM LIST ALL THREE REF DES. FACTORY CHOOSES FROM THERE 49.9 1%
402 CH 2
4 1 1
3 2 C2V1 C2V2 R2N7
.1UF
4.7UF 10% 10K
10% 6.3V 5%
X800550-003 6.3V 2 X5R CH
U1G1 IC X5R 402
805 402
1
IR
VCC 3
DATA 1 IR_DATA OUT 34
GND 2
TILT SWITCH, TMEC ME2 5
ME1 4
EMPTY
SW2G3
TH X803473-002
1
3 2
X813350-001
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
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FALCON_RETAIL 43/82 1.0
CR-44 : @FALCON_LIB.FALCON(SCH_1):PAGE44
L3A3 OUT 29
1 2 V_5P0
28 IN VID_DACA_DP VID_DACA_OUT OUT 44 DAC STANDARD ADVANCED SDTV HDTV SCART VGA
.27UH IND RT2M1
DIO
BAV99
SOT363
1 0.45A 1210 1 2 V_AVIP
NA
6
1% 62PF 75PF
5% 5% C2M5 C2A1
V_3P3 CH
50V 50V 28 HANA_SPDIF_OUT 4.7UF 470PF B N/A C(CHROMA) PR PR R R
402 2 NPO 2 NPO IN 10% 5%
2 402 402 2 6.3V 50V
X5R X7R
2
1 805 402
C2A6 C N/A N/A PB PB B B
SOT23S
BAV99
22PF
3
5%
DIO
50V
2 NPO D CVBS(COMP) CVBS(COMP) CVBS N/A CVBS CVBS
402
D2A1
L3A2
28 VID_DACB_DP 1 2 VID_DACB_OUT 44
IN OUT
.27UH IND
1
J3A1 CONN
DIO
BAV99
SOT363
R3A3 1 1 29 V_AVIP
75 C3A5 C3A2 27 V_AVIP_RET
CR3A2
1% 62PF 75PF
V_3P3 CH 5% 5%
402 50V 50V 44 IN VID_DACA_OUT 4 VID_DACA_OUT
2
2 NPO 2 NPO 2 VID_DACA_RET
402 402
5
1
28 IN OUT 44 44 IN VID_DACD_OUT
CH
1%
5 VID_DACD_RET AV_MODE2 28 AV_MODE2 OUT 34 44
.27UH IND
R2A8
BAV99
DIO
24 AV_MODE1
SOT363
9 VID_HSYNC_RET
1.82K
R3A6
402
75 1 1 GND<2> 26
C3A4 C3A1
CR3A1
2
1% 62PF 75PF 44 IN VID_VSYNC_OUT 12 VID_VSYNC_OUT GND<1> 22
V_3P3 CH 5% 5%
WSS_CNTL1 1 R2A6 2 10 VID_VSYNC_RET GND<0> 18
50V 50V 33 WSS_CNTL_B
402 2 NPO 2 NPO IN
2 5.36K 1% CR2A1 25 34
2
402 402
1
R2A9 2
R2A4 2
CH
CH
1%
5%
2
C2A8 X806743-001 TH
75PF
L3A4 5%
50V
VID_DACD_DP 1 2 VID_DACD_OUT 1 NPO
10K
402
402
28 44
301
IN OUT 402
1
1
.27UH IND
DIO
BAV99
1
SOT363
0.45A 1210
R3A9 NA
3
SCART_RGB_OUT
75 C3A7 2
1% 62PF C3A8 V_3P3STBY
CR3A1
CH 5% 75PF
V_3P3 50V 5%
402 1 NPO 50V
2 402 1 NPO
402 1 1 1 1
5
1 R2M9 2 1 1 1 1
3
2 R2M10 1
28 44
BAV99
DIO
16V
2
DIO
BAV99
X7R
10K
402
6
402
LAYOUT:PLACE CLOSE TO CONNECTOR
V_3P3STBY
CR3M2
EMI CAPS
2
V_5P0DUAL
RT1B1
V_EXPPORT
2 1 V_EXPPORT OUT 45
45 IN
1.1A THRMSTR
0.21DCR 1206 1 C2A4 2 2 1
D1A2 C1A3 C1M2 FTP FT1N2
220UF 470PF 4.7UF
R1B2 2 20% 5% 10%
10V 50V 6.3V
2 ELEC 1 X7R 1 X5R
0 5% 3 RDL 402 805
603 CH
1
NA
SM BAV99
L1B1 EMPTY SOT23S
CMCHOKE DIO
35 BI EXPPORT_DN 1 2 EXPPORT_DN_CM
35 BI EXPPORT_DP 4 3 EXPPORT_DP_CM
D1A1
X801560-001
2 PGB0010603 PGB0010603
1
603 603
3 EG1A2 EG1A1
R1B1 1 EMPTY EMPTY
0 5%
603 CH BAV99
2
SOT23S J1A1 CONN
DIO
XENON RJ45/USB COMBO
12 VBUS
13 D-
IN ARGON_NTX 14 D+
D1B1 15 GND
2
V_EXPPORT 2
C1A4
45 IN 470PF 16
5% OMNI
3 50V
1 X7R 39 ENET_P2LI_R 1 LED_LEFT_A
402 IN
1 40 39 IN ENET_LINK_N 2 LED_LEFT_C
39 IN ENET_POAC_R 3 LED_RIGHT_A
BAV99 ENET_ACT_N 4
SOT23S 40 39 IN LED_RIGHT_C
DIO
40 39 IN ENET_TX_DP 11 XFMER2_P
V_ENET 1 R1M3 2 ENET_TX_CT 10
39 IN XFMER2_C
0 5% 40 39 IN ENET_TX_DN 7 XFMER2_N
402 EMPTY
40 39 IN ENET_RX_DP 9 XFMER1_P
1 R1A5 2 ENET_RX_CT 6 XFMER1_C
0 5% 40 39 IN ENET_RX_DN 5 XFMER1_N
402 EMPTY
8 CAP
C1M1 C1A2
.1UF .1UF 20 EMI4
10% 10%
6.3V 6.3V 19 EMI3
X5R X5R 18 EMI2
402 402 21 EMI1
17 ME1
X806148-001
DRAWING
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[PAGE_TITLE=CONN, RJ45 + USB COMBO] Tue May 08 18:24:18 2007
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FALCON_RETAIL 45/82 1.0
CR-46 : @FALCON_LIB.FALCON(SCH_1):PAGE46
V_MEMPORT1 OUT 60
V_MPORT
V_5P0DUAL
RT2G1 FB5G1
RT8G1 2 1 2 1 V_MEMPORT2
2 1 V_GAMEPORT2 120 FB
1.1A THRMSTR 0.5A 603
1.1A THRMSTR 0.21DCR 1206 0.2DCR 1 C5G4 1 2
0.21DCR 1206 2 2 C4V6 C5G6
1 C9G2 220UF 470PF 4.7UF
C9G5 C9G1 20% 5% 10%
4.7UF 220UF 470PF 10V
10% 20% 5% 50V 6.3V
6.3V 10V 50V 2 ELEC 2 X7R 1 X5R
1 ELEC 1 RDL 402 805
X5R 2 X7R
805 RDL 402 PGB0010603
1
603 R4G5
EG9G2
0 5%
603 CH
EMPTY
V_5P0DUAL NA
SM
L4G1 EMPTY
2
D9G2
2 MEMPORT2_DN 1 CMCHOKE 2 MEMPORT2_DN_CM
35 BI
1 R9G2 2
0 5% 3
603 CH MEMPORT2_DP 4 3 MEMPORT2_DP_CM
1 35 BI
NA PGB0010603 PGB0010603
SM X801560-001
1
BAV99 603 603
L9G1 EMPTY SOT23S PGB0010603 EG4G2 EG4G1 J4G2 CONN
DIO
1
GAMEPORT2_DN 4 CMCHOKE 3 603
35 BI XENON MU
EG9G1 DIO DIO
1 GND
EMPTY
R4G4 2 VBUS
GAMEPORT2_DP 1 2 3
2
35 BI 0 5% D-
TH 603 CH 4 D+
5
2
X801560-001 D9G1 J9G1 CONN GND
2 XENON GAME 6 GND
CONN 7
3 VBUS
1 VBUS 8 D-
1 R9G1 2 1
GAMEPORT2_DN_CM 2 D- 2 2 9 D+
GAMEPORT2_DP_CM 3 D+ 1 C2G2 C3V5 C2G3 10 GND
0 5% 4 220UF 470PF 4.7UF
603 CH GND 20% 5% 10%
BAV99 10V 14
50V 6.3V EMI4
SOT23S
5 2 ELEC 1 X7R 1 X5R 13
DIO VBUS RDL 402 805 EMI3
GAMEPORT1_DN_CM 6 D- R3G4 12 EMI2
GAMEPORT1_DP_CM 7 D+ 11 EMI1
V_5P0DUAL 8 GND 0 5%
603 CH 15
RT8G2 NA ME4
9 EMI1 16 ME3
2 1 V_GAMEPORT1 10 EMI2
SM 17
L2G1 EMPTY
ME2
18 ME1
1.1A THRMSTR 11
0.21DCR 1206 2 ME1 MEMPORT1_DN 1 CMCHOKE 2 MEMPORT1_DN_CM
2 1 C9G3 C9G4 12 ME2
35 BI MTGA<8-1>
C9G6 220UF 470PF
4.7UF 20% 5% MTGB<8-1>
10% 10V 50V MTGC<8-1>
1 6.3V
2 ELEC 1 X7R X800245-003 35 MEMPORT1_DP 4 3 MEMPORT1_DP_CM
X5R RDL 402 BI
805
X800059-001 TH
X801560-001
PGB0010603 PGB0010603
1
603 603
V_5P0DUAL EG3G1 EG2G1
D9V2 R2G5 DIO DIO
2 PGB0010603 0 5%
R9V2 603 CH
1
603
2
0 5% 3 EG9V2
603 CH
1 EMPTY
NA
SM BAV99
L9V1 EMPTY V_5P0 V_MPORT
2
SOT23S
DIO U1F2 IC
GAMEPORT1_DN 4 CMCHOKE 3
35 BI PGB0010603
NCP1117
1
603 3 2 1
IN OUT FTP FT1V1
EG9V1
35 BI GAMEPORT1_DP 1 2 1 ADJUST/GND
EMPTY 1
D9V1 1 C1F6 1 C1F4
X801560-001 C1U2 0.1UF 100UF
2 1.0UF X800499-001 10% 20%
2
DRAWING
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FALCON_RETAIL 46/82 1.0
CR-47 : @FALCON_LIB.FALCON(SCH_1):PAGE47
BLEEDER_C1
BLEEDER_C2
57 57
CH 58 58
402
1 59 59
60 60
61 61
3 62 62
1 Q1G2 63 63
MMBT2222
VREG_5P0_SEL XSTR 64 64
VREG_5P0_SEL NGATE/PGATE V_5P0DUAL 3 2 65 65
27 SMC_RST_N 2 R1V1 1 BLEEDER_B 1 Q1V1 66 66
IN MMBT2222 67 67
HIGH LOW V_5P0STBY 10K 5% XSTR 68 68
402 CH 2 69 69
LOW HIGH V_5P0
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=[MISC, V_5P0 DUAL, DEBUG MAPPING] Tue May 08 18:24:20 2007
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CR-48 : @FALCON_LIB.FALCON(SCH_1):PAGE48
V_5P0
D1E4
2
3
C1E4
36 IN HDD_TX_DP 1 2
1
0.01UF 10%
16V BAV99
X7R
402 SOT23S
DIO
HDD_TX_DP_C HDD SATA AND POWER
HDD_TX_DN_C
D1E3
C1E3 J1E1 CONN
36 IN HDD_TX_DN 1 2 2
XENON HDD
0.01UF 10% 3 1 CONN
16V GND
X7R 2 D+
402 1 3 D-
4 GND
BAV99 5 D-
SOT23S 6 D+
DIO 7 GND
V_5P0 8 GND
9 GND
D1E2 10 GND
2 PGB0010603 PGB0010603 PGB0010603 PGB0010603 11 V_HDD
12
1
603 603 603 603 V_HDD
EG1E4 EG1E3 EG1E2 EG1E1 13 V_HDD
3
C1E2 14 V_XPOD
36 OUT HDD_RX_DN 1 2
1 EMPTY EMPTY EMPTY EMPTY
15 EMI1
0.01UF 10% 16
16V EMI2
BAV99
2
X7R
402 SOT23S
DIO 17 ME1
HDD_RX_DN_C 18 ME2
HDD_RX_DP_C
MTGA<8-1>
V_5P0 MTGB<8-1>
D1E1 RT1U1
C1E1
36 OUT HDD_RX_DP 1 2 2 2 1 V_HDD X800351-002 TH
0.01UF 10% 3 1.5A THRMSTR
16V 0.11DCR 1812 1 C1E5 C1T5 C1T4 C1T3
X7R 100UF 1UF 1UF 470PF
402 1 20% 10% 10% 5%
16V 16V 16V 50V
2 ELEC X7R X7R X7R
BAV99 RDL 603 603 402
SOT23S
DIO
V_5P0DUAL
RT1R1
ODD SATA 2 1 V_XPOD
V_3P3 V_3P3
ODD_TX_DP 1
C1C6
2 ODD_TX_DP_C
ODD POWER DECOUPLING 1.1A
0.21DCR
THRMSTR
1206 C1T1 C1T2
36 IN 1UF 470PF
0.01UF 10%
10%
16V
5%
50V
ODD POWER AND CONTROL
16V V_12P0 V_3P3 X7R X7R
X7R 603 402
402 CR1D2
CR1D3
2
C1C5 J1C1 2
36 IN ODD_TX_DN 1 2 ODD_TX_DN_C SATA 1 C1C10 1 C1C11
C1C14 C1C13 C1D6 C1R1 3
3
9 100UF 1UF 0.1UF 100UF 1UF .1UF
0.01UF 10% 20% 10% 10% 20% 10% 10%
16V 16V 16V 25V 16V 16V 6.3V 1
X7R 1 ELEC X7R X7R ELEC X7R X5R 1
402 2 2 RDL 603 603 2 RDL 603 402
BAV99
3
TRAY_STATUS 1 R1R4 2 TRAY_STATUS_R SOT23S BAV99
4 34 OUT SOT23S
C1C4 EMPTY
36 ODD_RX_DN 1 2 ODD_RX_DN_C 5 100 5% EMPTY
OUT 6 402 CH
0.01UF 10% V_5P0 V_3P3
16V 7 J1D1
X7R 8 V_5P0 1 EJECTSW_N
402 IN 43
4 3 TRAY_OPEN IN 34
C1C3 CONN 1 C1D9 V_12P0 6 5
ODD_RX_DP 1 2 C1D4 C1D1 C1D3 8 7
36 OUT ODD_RX_DP_C 100UF 1UF 1UF .1UF
20% 10% 10% 10% 10 9 1
0.01UF 10% 16V 16V 16V 6.3V 12 11 C1R4
16V 2 ELEC X7R X7R X5R 75PF
X7R RDL 603 603 402 5%
402 50V
CONN 2 NPO
402
DRAWING
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FALCON_RETAIL 48/82 1.0
CR-49 : @FALCON_LIB.FALCON(SCH_1):PAGE49
V_3P3STBY V_12P0 1
DB8M1
1
1 FTP FT9N1 1
DB8M2
DB8M3
1 C6G5 2
C6G2
100UF 470PF 1 1 1 1
20% 5% 1 C9B1 C9A1 C9A5 C9A6 C9A2
16V 50V 1500UF 0.1UF 0.1UF 0.1UF 0.1UF
2 ELEC 1 X7R 20% 10% 10% 10% 10%
RDL 402 16V J9A1 CONN
25V 25V 25V 25V
2 ALUM 2 X7R 2 X7R 2 X7R 2 X7R XENON PWR
RDL 603 603 603 603
1 GND
2 GND
3 GND
4 V12P0
5 V12P0
6 V12P0
1 R6G7 2 34 PSU_V12P0_EN 2 R8A2 1 PSU_V12P0_EN_R 7 PSU_EN
IN
0 5% 1 100 5%
603 CH 402 CH 1 1 8 VSB5P0
R8A1 C8A1 C8A2
NA .1UF 470PF
SM 10K 10% 5% 9 EMI1
5% 6.3V 50V 10
L6G1 EMPTY CH
2 X5R 2 EMPTY EMI2
402 402 402 13 EMI3
ARGONPORT_DN 4 CMCHOKE 3 2 14 EMI4
35 BI
11 ME1
TH 12 ME2
ARGONPORT_DP 1 2 J6G1 CONN
35 BI
MTGA<8-1>
XENON RF
X801560-001 1 1 1 MTGB<8-1>
C6G3 C6G4 1 CONN V_5P0STBY DB8N1
VCC
470PF 470PF ARGON_DN_CM 2 D- 1
5% 5% FTP FT8N1 X811487-001 TH
50V 50V ARGON_DP_CM 3 D+
2 EMPTY 2 EMPTY 4 GND
1 R6G8 2 402 402
0 5% 5 SPARE 1 C5B7 1 C8B1 1
6
C9A4
603 CH C_DATA 100UF 100UF 470PF
7 C_CLK 20% 20% 5%
16V 16V 50V
8 GND ELEC ELEC 2 X7R
USE LC NETWORK FOR USB 1.1 9 NTX
2 RDL 2 RDL 402
V_3P3STBY
USE USB CHOKE FOR USB 2.0
10 EMI1
11 EMI2
1
R3N7 12 ME1
10K 13 ME2
5% 34 BI ARGON_DATA
CH 34 BI ARGON_CLK V_5P0STBY V_12P0
402
2 X800095-001
2 2
PWRSW_N 2 R3N6 1 PWRSW_N_R
C6V11 C6V10 1 1
34 IN 470PF 470PF
10K 5% 5% 5% V_12P0
2 50V 50V R8B5 R7B2
402 CH
C6V15 1 X7R 1 X7R 2.2K 2.2K
470PF 402 402 5% 5%
5% CH CH
50V 402 402
1 X7R 2 2 3
402
R6G37 2 2 R8N1 1 1 Q8N1
1 BLEEDER_V12P0_B2
BCP51
549 1% XSTR
0 5%
BLEEDER_V12P0_C1
BLEEDER_V12P0_C2
402 CH 2 4
603 EMPTY
NA BLEEDER_V12P0_LOAD
SM
L6G2 EMPTY 1 1 1 1
MEMPORT3_DP_ARGON 4 CMCHOKE 3 R7N3 R7N1 R7N4 R7N2
60 MEMPORT3_DP_ARGON_CM 10 10 10 10
BI
1% 1% 1% 1%
3
CH CH CH CH
1 Q8B4 805 805 805 805
60 BI MEMPORT3_DN_ARGON 1 2 MEMPORT3_DN_ARGON_CM MMBT2222 2 2 2 2
3 XSTR
2
X801560-001 2 R8A4 1 BLEEDER_V12P0_B1 1 Q8B5
MMBT2222
2.2K 5% XSTR
402 CH 2
1 R6G38 2
56 5% 27 ANA_V12P0_PWRGD 2 R8A3 1
603 EMPTY IN
2.2K 5%
402 CH
DRAWING
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FALCON_RETAIL 49/82 1.0
CR-50 : @FALCON_LIB.FALCON(SCH_1):PAGE50
4 CPU_VREG_APS5 R7E3 5
IN
0 5% V_GPUCORE
4 CPU_VREG_APS4 402 CH R7E1 4
IN
0 5%
4 CPU_VREG_APS3 R7E5 402 CH
3
IN N: WATERNOSE=011100=1.1625V
0 5% 1 1 1 1 1 1 N: DD1.0 REQUIRES VID0 RC
4 CPU_VREG_APS2 402 CH R7E4 2 N: DD2.0 NO STUFF RC
IN R7T6 R7T4 R7T8 R7T7 R7T5 R7T9
0 5% 10K 10K 10K 10K 10K 10K N: LOKI=100001=1.05V
4 CPU_VREG_APS1 R7E2 402 CH
1
5% 5% 5% 5% 5% 5%
IN CH EMPTY EMPTY EMPTY EMPTY CH
0 5% 402 402 402 402 402 402
CPU_VREG_APS0 402 CH R7E6 0 2 2 2 2 2 2
4 IN
1K 5%
402 CH 5 4 3 2 1 0
VREG_CPU_VID<5..0> OUT 51
1 1 1 1 1 1
R7T13 R7T11 R7T15 R7T14 R7T12 R7T16
10K 10K 10K 10K 10K 10K
5% 5% 5% 5% 5% 5%
EMPTY CH CH CH CH EMPTY
402 402 402 402 402 402
2 2 2 2 2 2
1 DB8P1
1 DB8P2 V_GPUCORE
V_CPUCORE
1 FTP FT7T9
1 FTP FT5R2
N:CPU OUTPUT FILTER N:GPU OUTPUT FILTER
1 C8C2 1 C8E3 1 C8E1 1 C8F1 1 C8E2 1 C8D1 1 C8C1 1 C8D4 1 C7C2 1 C7C1 1 C6C3 1 C7C3 1 C6C2 1 C6C1 1 C5C8 1 C5C9
820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2.5V 2.5V
2 EMPTY 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 EMPTY 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 ALUM 2 EMPTY 2 EMPTY
RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL RDL 8X8 8X8
1
FTP FT7U4
DRAWING
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CR-51 : @FALCON_LIB.FALCON(SCH_1):PAGE51
3188 3190A
VREG_CPU_CSSUM 2
C8U10
1000PF N: TARGET FSW=233KHZ
10%
V_CPUCORE 50V
1 X7R
LAYOUT:ATTACH TO 1 402
CLOSEST INDUCTOR FT8U2 FTP
ST8F1
1 2 VREG_CPU_CSREF 1 R8G3 2 VREG_CPU_CSREF_R
10 1%
SHORT 402 CH 2
C8G1
1000PF
10%
50V
1 X7R
VREG_V_CPUCORE_S
402
ST7T2
R8U13
1 2 C8U7
1 2 1 VREG_CPU_FB
2 5% 0
SHORT EMPTY 402 10% 0.1UF
2 C8U8
25V 22PF
EMPTY 5%
603 50V
1 NPO
402
1 R8U10 2 C8U6 1 R8U11 2
1 2 VREG_CPU_COMP_R VREG_CPU_COMP
1% 1.33K 330PF 5% 24.3K 1%
CH 603 50V 402 CH
X7R
402
DRAWING
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[PAGE_TITLE=VREGS, CPU CONTROLLER] Tue May 08 18:24:18 2007
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FALCON_RETAIL 51/82 1.0
CR-52 : @FALCON_LIB.FALCON(SCH_1):PAGE52
50 IN V_VREG_CPU
D9C1 3
1N4148
C9P3 3
50 V_VREG_CPU 1 R9P2 2 VREG_CPU3_VCC 1 3
VREG_CPU_BST3 1 2
D
Q9D2 D Q9D1
IN 1 1
2.2 1% NTD60N02R C9D3 C9D1
805 EMPTY SOT23 0.01UF 10% DPAK NTD60N02R 4.7UF 4.7UF
EMPTY 50V DPAK 10% 10%
1 EMPTY 1 16V 16V
C9P4 805 1 2 X5R 2 EMPTY
1.0UF G S EMPTY 1206 1206
10% C9P2 G S
16V
1 R9P1 2 VREG_CPU_BST3_R 1 2 EMPTY 2 VREG_CPU_PHASE3 51
2 EMPTY
2 OUT
805 2.2 1% 0.015UF 5%
U9P1 EMPTY 805 EMPTY 16V V_CPUCORE
EMPTY
MOS DRIVER 805
4 VCC BST 1 L8D1
51 VREG_CPU_PWM3 2 IN DRVH 8 VREG_CPU_DRVH3 2 1
VREG_CPU_DRV_EN IN 3 7
51 IN OD_N* SW EMPTY 0.6UH
6 PGND DRVL 5 TH 30A
1
NA
VREG_CPU_BG3
3 3 R9C1
X801233-001 2.2
D Q9C1 D Q8C1 1%
EMPTY
NTD85N02R NTD85N02R 805
2
DPAK DPAK
1 1
G S EMPTY G S EMPTY VREG_CPU_SW3_R
2 2
1
C9C5
4700PF
10%
50V
D9E1 2 EMPTY
1N4148 603
1 R9T2 2 VREG_CPU_BST2 C9T2
VREG_CPU2_VCC 1 3 1 2 3 3
2.2 1% D Q9E1 D Q9D4 1 1
805 CH SOT23 0.01UF 10% C9D4 C9E1
DIO 50V 4.7UF 4.7UF
1 X7R NTD60N02R NTD60N02R
C9T3 805 10% 10%
1.0UF DPAK DPAK 16V 16V
10% 1 R9T1 2 C9T1 1 1 2 EMPTY 2 X5R
16V VREG_CPU_BST2_R 1 2 1206 1206
2 G S G S EMPTY VREG_CPU_PHASE2
X7R FET OUT 51
805 2.2 1% 0.015UF 5% 2 2
U9T1 IC 805 CH 16V
X7R
MOS DRIVER 805
4 VCC BST 1 L8E1
51 VREG_CPU_PWM2 2 IN DRVH 8 VREG_CPU_DRVH2 2 1
IN
3 OD_N* SW 7
IND 0.6UH
6 PGND DRVL 5 1 TH 30A
R9E1 NA
VREG_CPU_BG2
X801233-001 3 3 2.2
1%
D Q9E3 D Q9D3 EMPTY
805
NTD85N02R NTD85N02R 2
DPAK DPAK
1 1
G S G S
FET FET VREG_CPU_SW2_R
2 2
1
C9E4
4700PF
10%
D9F1 50V
1N4148 2 EMPTY
1 R9U2 2 VREG_CPU_BST1 C9U2 603
VREG_CPU1_VCC 1 3 1 2
3 3
2.2 1% 0.01UF 10% D Q9F1 D Q9F4
805 CH 1 SOT23 50V
1 1
C9U3 DIO X7R
C9F4 C9F1
4.7UF 4.7UF
1.0UF 805 NTD60N02R NTD60N02R 10% 10%
10% 1 R9U1 2 C9U1 16V 16V
16V VREG_CPU_BST1_R 1 2 DPAK DPAK 2 2
2 1 1 X5R EMPTY
X7R 2.2 1% G S G S 1206 1206 VREG_CPU_PHASE1 OUT 51
805
805 CH 0.015UF 5% FET EMPTY
U9U1 IC 16V 2 2
X7R
MOS DRIVER 805
4 VCC BST 1 L8F1
51 VREG_CPU_PWM1 2 IN DRVH 8 VREG_CPU_DRVH1 2 1
IN 3 7
OD_N* SW IND 0.6UH
6 PGND DRVL 5 TH 30A
1
NA
VREG_CPU_BG1
3 3 R9F1
X801233-001 2.2
D Q9F2 D Q8F1 1%
EMPTY
NTD85N02R NTD85N02R 805
2
DPAK DPAK
1 1 VREG_CPU_SW1_R
G S G S
FET FET
2 2
1
C9F3
4700PF
10%
50V
2 EMPTY
603
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
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FALCON_RETAIL 52/82 1.0
CR-53 : @FALCON_LIB.FALCON(SCH_1):PAGE53
VREG_GPU_EN_N_R
603 402
SHORT CH 1 1
603 C8N4 X800631-001 1
1 0.01UF
10%
16V R5N1
2 R8P5 1
2 X7R 10K
54 IN VREG_GPU_PHASE2 402 5%
7.5K 1% CH
603 CH 402
V_GPUCORE 1 2
C8P3
0.1UF
10% 1 R9B1 2
25V 34 IN VREG_GPU_EN_N
2 X7R
603 1 10K 5%
FT2P6 FTP 402 CH
54 53 VREG_GPU_PHASE1 2 R8P6 1
IN
7.5K 1%
603 CH
V_GPUCORE 1 VREG_GPU_PWRGD OUT 34
C8P4
0.1UF 1
10% FTP FT2P3
25V
2 X7R
603 VREG_GPU_GH2_R
1 R8N5 2 VREG_GPU_GH2 OUT 54
0 1A
805 CH
VREG_GPU_GL2_R
1 R8N6 2 VREG_GPU_GL2 OUT 54
ST8C1 0 1A
1 2 VREG_GPU_CSREF_R 2 R8B2 1 805 CH
2K 1% VREG_GPU_GH1_R 1 R8N3 2 VREG_GPU_GH1 54
SHORT 402 CH 2
OUT
0 1A
2 R8B3 805 CH
C8B8 VREG_GPU_GL1_R 1 R8N4 2 VREG_GPU_GL1
0.1UF 750K OUT 54
10% C8B7 1% 0 1A
25V 1 2
1 X7R CH 805 CH
603 603
470PF 5% 1
50V
X7R
402
DRAWING
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[PAGE_TITLE=VREGS, GPU CONTROLLER] Tue May 08 18:24:19 2007
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FALCON_RETAIL 53/82 1.0
CR-54 : @FALCON_LIB.FALCON(SCH_1):PAGE54
50 IN V_VREG_GPU
3 C6B2
D Q6B1 4.7UF
10%
16V
X5R
NTD60N02R 1206
1
DPAK V_GPUCORE
53 IN VREG_GPU_GH2
G S
FET VREG_GPU_PHASE2 OUT 53
2
L6C1
2 1
IND 0.6UH
1 TH 30A
3 3 NA
D Q6B2 D Q6C1 R6C2
2.2
1%
NTD85N02R NTD85N02R CH
DPAK DPAK 805
53 VREG_GPU_GL2 1 1 2
IN G S G S
FET FET
2 2
VREG_GPU_PH2_R
2
C5C6
3 C7B2 4700PF
4.7UF 10%
D Q7B1 10% 1 50V
16V X7R
X5R 603
NTD60N02R 1206
DPAK
53 VREG_GPU_GH1 1
IN G S
FET
2
L7C1
2 1
IND 0.6UH
1 TH 30A
3 3 NA
D Q7B2 D Q7C1 R7B6
2.2 VREG_GPU_PHASE1 OUT 53
1%
NTD85N02R NTD85N02R CH
DPAK DPAK 805
53 VREG_GPU_GL1 1 1 2
IN G S G S
FET FET
2 2
VREG_GPU_PH1_R
2
C8B6
4700PF
10%
50V
1 X7R
603
V_5P0
V_1P8
U2T1 IC
NCP1117
1 R2E7 2 V_V3P3TOV1P8 3 IN OUT 2 1 FTP FT2R8
10 5% V_1P8 V_MEM
1210 CH 1 ADJUST/GND
1 1 1 C2D6
C2T5 C2R4
1 R2E6 2 0.1UF X800500-001 0.1UF 100UF
1 R2T8 2
10% 10% 20%
10 5% 25V DPAK 25V 16V
1210 CH
2 X7R 2 X7R 2 ELEC 0 1A
603 1.8V 603 RDL 805 EMPTY
1 R1E3 2 R2T7
1 2
10 5%
1210 CH 0 1A
805 EMPTY
1 R1E1 2
10 5%
1210 CH
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=VREGS, GPU OUTPUT PHASE 1,2] Tue May 08 18:24:19 2007
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FALCON_RETAIL 54/82 1.0
CR-55 : @FALCON_LIB.FALCON(SCH_1):PAGE55
V_12P0
L7F1
1 2 V_VREG_V1P8V5P0 32
OUT
1.6UH NA
10A TH
17
28
1 X7R X7R 10V DB3F1
FTP FT6V1 NTD60N02R 603 603 U4V1 IC 2 NTD60N02R
X7R DPAK
DPAK 603 1 1
FT2U1 FTP
PV
IN
1 29 VREG LDOSD 27 G S
ST6F1
S G FET
2 VREG_V5P0_BST2 11 BST2 BST1 23 VREG_V1P8_BST1 2
1 2 ST2F1
ADP1823
VREG_V5P0_DH2 12 DH2 DH1 22 VREG_V1P8_DH1 2 1
SHORT ST6F2 ST2F2
1 2 VREG_V5P0_SW2 13 SW2 SW1 21 VREG_V1P8_SW1 1 2 VREG_V1P8_SW1_S
1 VREG_V5P0_SW2_S SHORT
1 R4V7 2 VREG_V5P0_CSL2 14 20 VREG_V1P8_CSL1
1 R3V1 2 1
R4V11 SHORT CSL2 CSL1 SHORT
0 7.5K 1% VREG_V5P0_DL2 16 DL2 DL1 18 VREG_V1P8_DL1 7.5K 1% R4G9
5% 402 CH 402 CH 0
ST5V1 15 19 5%
EMPTY 1 2 PGND2 PGND1 VREG_V1P8_CSL1_R
402 L6F1 ST3G1 EMPTY
2 7 COMP2 COMP1 32
1 2 VREG_V5P0_CSL2_R 1 2 402
SHORT 2
9 SS2 SS1 30 L3F1
1.7UH 4 SHORT
13.8A TH 1 2
5 UV2
1.7UH 4
VREG_V1P8_COMP1
6 FB2 FB1 1
13.8A TH
VREG_V5P0_COMP2
GNDSLUG
X7R 2 ALUM NTD60N02R 10 24 1UF
603 RDL POK2 POK1 20% 20% 20% 10%
DPAK 3 FREQ NTD60N02R 4V 4V 4V 16V
1 2 EMPTY POLY POLY X7R
SYNC 2 2 2
GND
DPAK RDL RDL RDL 603
1 S G 1
S 1
VREG_V5P0_SS2
2 G FET
VREG_V1P8_SS1
R4V9 LCC32 X807026-001 2 R4G1
VREG_V1P8_FB1_C
357
464
4
33
1%
ADI_FREQ
1%
CH
VREG_V5P0_FB2_C
402
1 CH
2 402
1
R4G6 2
1 R4V3 2 ADI_VREG 1.91K
C4V12 1 R4V4 2 55 1 R4V1 2 C4V11 1%
R4V6 1 2 VREG_V5P0_COMP2_R IN VREG_V1P8_COMP1_R 1 2
1.82K 10K 5% CH
1% 820PF 10% 7.5K 1% 402 CH 18.2K 1% 330PF 5% 402 1
1 50V 402 CH 402 CH 50V 2 C4G1
C4V1 CH X7R 1 R4V2 2 X7R 2700PF
3300PF 402 10%
10% 2 402 C4V13 C4V10 402 50V
50V 1 2 10K 5% 1 2 2
2 X7R 1 402 EMPTY 1 X7R
402 C4V14 C4V9 402
220PF 5% .1UF 82PF 5%
50V .1UF FREQ PIN 3: 10% 50V
NPO 10% 6.3V NPO
VREG_V5P0_FB2 402 2 6.3V 0 300KHZ 2 X5R 402 VREG_V1P8_FB1
X5R 1 600KHZ 402
402 OUT 62
1 VREG_V5P0_VMEM_PWRGD 1
34 OUT
R4V5 R4G7
243
1% 75
VREG_V1P8_EN 1%
CH ADI_VREG 1 R4V10 2 IN 34
402 55 IN CH
2 10K 5% 1 FTP FT2P19
402
402 CH 2
1 V_MEM R4G6 R4G7 R4G8
VREG_V1P8_FB1_R
R3V3 1.9V 1.91K 75 806
1K 1.95V 1.91K 43.2 806
5% 1
2.0V 1.91K 267 549
CH R4G8
34 VREG_V5P0_EN 1 R3V5 2 VREG_V5P0_EN_R 402 2.1V 1.91K 301 464
IN 2 806
1 47K 5% 1%
FT2P18 FTP 1 402 CH CH
THESE ARE THE VOLTAGES NEEDED 402
R3V4 1 FOR VARIOUS MEMORIES. CONSULT 2
1K C3V8 WITH MEM TEAM FOR USAGE.
5% .22UF
CH 10%
402 6.3V
2
2 X5R
402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
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FALCON_RETAIL 55/82 1.0
CR-56 : @FALCON_LIB.FALCON(SCH_1):PAGE56
VREG_EFUSE_EN_C1
VREG_V3P3_ADJ
R1F7 X7R
1 U6T1 IC
1K 805
5% R1U2 NCP502D
X807964-001
CH 475 1 5 1
402 1% VIN VOUT FTP FT7T6
2 EMPTY VREG_EFUSE_EN_C2 3 ENABLE GND 2
1 R1F8 2 402
VREG_3P3_EN_R 2 C7T98 C7T99
1K 5% NC 4 1UF 1UF
402 CH CR6T1 10% 10%
16V 16V
TYPE PART # R1U1 R1U2 MBT3904 3 6 X810988-001 2.9V X7R EMPTY
V_5P0STBY V_3P3STBY FIXED X807964-001 EMPTY EMPTY 603 603
SC70
U5B1 IC ADJ X807089-001 1.27K 475 5 2
NCP1117
3 IN OUT 2 1 FTP FT5N1 VREG_EFUSE_EN 2 R6T4 1 THIS IS ACTUALLY A 3.3V PART
4 IN VREG_EFUSE_EN_R
4 1 XSTR
NCP612 FAMILY. NEED TO MAKE NEW SYMBOL
1 ADJUST/GND 1K 5%
1 1 402 CH
1 C5B1 1 C5B2 FT7T8 FTP
C5B3 0.1UF 100UF 2 V_3P3
1.0UF X800499-001 10% 20%
10% DPAK 25V 16V R6T1
2 16V 2 X7R 2 ELEC 10K R4C31 1 R4P14 2
X7R 3.3V 603 RDL 5% 1 2
805 0 5%
CH 0 5% 603 EMPTY V_GPUPCIE
402 603 CH
1
V_GPUCORE U5C1 IC
V_5P0 V_5P0STBY 1 R4P13 2
NCP1117 N: TARGET IS 1.25V
VREG_GPUPCIE_IN 3 IN OUT 2 1 FTP FT5R1
0 5%
603 EMPTY 1 ADJUST/GND OUT/TAB 4 1 1
2 2 IF USING U5B2 AS A FIXED - SET TO 1.8V 1 R5P2 R5C9
C4C6 1K 1
D5N1 D5B1 R5B1 = EMPTY 1.0UF X800501-001
DIO DIO 10% 1% 1%
R5B2 = 0 OHM SOT223
SOD123 SMA 16V CH CH
1 MBR130L 1 S1A 2 X7R 1.2V 402 0402
VREG_1P8STBY_D1 VREG_1P8STBY_D2
805 2 2
2 IF USING U5B2 AS AN ADJUSTABLE - SET TO 1.816V
2 R5B1 = 549 OHM
D5N2 VREG_PCIEX_ADJUST
VREG_PCIEX_R
DIO
R5B3 R5B2 = 221 OHM
1 1
SOD123 5%
MBR130L GPU R4P13 R4C31 R4P14 U5C1
1 1 R5P1
CH C5P1
1206 B13L EMPTY STUFF EMPTY STUFF 0
1 V_1P8STBY .1UF 5%
GUNGA STUFF EMPTY STUFF EMPTY 10%
U5B2 IC 6.3V CH
PLACEHOLDERS
2 X5R 402
NCP1117 402 2 1
VREG_1P8STBY_IN 3 IN OUT 2 1 FTP FT5N2 C5C5
4.7UF
10%
1 ADJUST/GND 6.3V
1 1 1 2 X5R
C5N3 C5B6 1 C5B4 V_3P3 805
1.0UF R5B1 100UF 1 R6C1 2
10% X800500-001 0.1UF
16V 549 10% 20%
2 X7R DPAK 1%
2 25V 16V 1 R5C6 2 0 1A
805 1.8V EMPTY X7R
603
2 ELEC
RDL 805 CH
402 0 1A V_CPUPLL
2 805 EMPTY
V_1P8 U6R1 EMPTY
VREG_1P8STBY_ADJ 1 R5B2 2 NCP1117
N: TARGET IS 2.20V
1 R5C4 2 VREG_CPUPLL_IN
3 IN OUT 2 1
0 5% FTP FT7R3
V_3P3 402 CH V_SBPCIE 0 1A
805 CH 1 ADJUST/GND OUT/TAB 4 1 1
U3P1 EMPTY
1 R6R3 R6R1
NCP1117 C6P1 499 1
3 2 1 1.0UF X800501-001 1% 1%
IN OUT FTP FT2P26 10% SOT223
16V EMPTY CH
1 4 1 1 2 X7R 1.8V 402 0402
ADJUST/GND OUT/TAB 805 2 2
1 R3C22 R3C21
C2C5
VREG_CPUPLL_R
X800501-001 549 1 VREG_CPUPLL_ADJUST
1.0UF 1% 1%
10% SOT223
16V EMPTY EMPTY
2 X7R 1.2V 402 0402
805 2 2 1
1
VREG_VDD_PEX_R
R7G23
0
805
2 1A 1
CH
L7G1
DB8U1 1 V_12P0
V_VREG_VCS 1 2
TP
CPU_SRVID 1.6UH EMPTY
4 IN 2 2 2 2 2 TH
C8G4 C7G3 C7G4 1 C7G7 C7V2 C7G5 10A 1
1 4.7UF 4.7UF 4.7UF 1500UF 0.1UF 0.1UF NA
C7F5
V_CPUCORE 10% 10% 10% 20% 10% 10% 4.7UF
16V 16V 16V 16V 25V 25V 10%
R7T19 C7U9 C8F2 1 1 1 1 1 16V
0
DB8U2 1 VREG_VCS_VREF
1UF 1UF X5R
1206
X5R
1206
X5R
1206
2 EMPTY
RDL
X7R
603
X7R
603
2 X5R
TP 10% 10%
5% 1206
16V 16V
EMPTY 1 2 X7R X7R
402 1 603 603
2 R8U8 R8U9
0 0 R8U7
5% 5% 0
V_12P0 5%
EMPTY CH V_CPUVCS
402 402 EMPTY
IRF8915PBF
10
2 1 402
4
U7F1
2 U7U2 IC FET
3
VC
VCC
2
R7F9 NC0
VREG_VCS_VP 4 GATE0 1
10K 2 VP VREG_VCS_HDRV DRN0 5 L8F2 FTP FT7U3
HDRV 9
5% DB7U2 VREG_VCS_SS_SD_N 3 SRC0 DRN0 6 VREG_VCS_VOUT_L 2 1
1 13 SS IR3638
EMPTY TP 6 VREG_VCS_LDRV
11 LDRV IND 1.7UH
402 3 1 2 VREG_VCS_RT NC2
Q7F1 C7U5 C7U6 DB8F4 1 2 GATE1 DRN1 7 TH 13.8A
V_CPUCORE 12 COMP PGND 8 4
1
GND
1 10% 10% 1 DRN1
2 2
NC1
2N7002 1 C7F4
NC
SRC1
16V 6.3V 1 FB C7T103 C7T102
2 SOT23 2 X7R 1 X5R 1 SSOP 820UF 4.7UF 4.7UF
2
603 402 C8U9 R7U6 X811812-001 SO-8
20% 10% 10%
.1UF 0 X807111-001 6.3V 6.3V 6.3V
3 ALUM 1 1
5
7
X5R X5R
14
10% 402 2 RDL
1 R7U4 2 1 Q7U1 2 6.3V 805 805
1
MMBT2222 X5R EMPTY
1K 5% VREG_VCS_CPUCORE_R EMPTY 402 5% VREG_VCS_NC CR7V2
402 EMPTY 2 MBR0520L
1 SOD123
2
EMPTY
1
DB7U1
R7U6 SWITCH FREQ VREG_VCS_NC1
STUFF 400KHZ 1
DB8U3
EMPTY 200KHZ
R8U14 ST7D2
1 R7U5 2 C7U8 VREG_VCS_FB 1 R7U7 2 VREG_VCS_FB_R 1 2 2 1
VREG_VCS_COMP_C 1 2 VREG_VCS_COMP
10K 1% 0 5%
15K 1% 3300PF 10% 402 CH 402 EMPTY SHORT
402 EMPTY 50V
EMPTY
402
1 R8U6 2 C8U5
VREG_VCS_FB_COMP 1 2
C7U7 C7U11
1 2 1 2 2.67K 1% 2700PF 10%
402 EMPTY 50V
47PF 5% 220PF 5% EMPTY
50V 50V 402
EMPTY NPO
402 402
1 1
R7U8 R8U12
4.02K GAIN=20% WITH R7U7=10K, R8U12=49.9K
1% 33.2K
1% OUTPUT = CPU_SRVID(1+GAIN)
CH
402 CH
2 402
2
VREG_VCS_COMP_R
1
C7U10
0.01UF
10%
16V
2 X7R
402
DRAWING
FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
Tue May 08 18:24:20 2007 FALCON_RETAIL 57/82 1.0
CONFIDENTIAL
CR-58 : @FALCON_LIB.FALCON(SCH_1):PAGE58
HDR C1D7
.1UF
10% 1 R2P18 2
6.3V SMC_RST_N IN 27
X5R 100 5%
402
402 CH
V_3P3STBY V_5P0STBY
J9A2
1X2HDR
1
SMC_RST_XDK_N
2
C2B12 C2B15
.1UF 1UF SM
10% 10% HDR C9A3
6.3V 16V .1UF
X5R X7R 10%
402 603 6.3V
J2B1 X5R
V_3P3 402
2X7HDR_14
33 IN KER_DBG_TXD 2 1
34 IN SMC_DBG_TXD 4 3
34 OUT SMC_DBG_EN 6 5
8 7
SMB_CLK_R 10 9 SMB_DATA_R 1 R2N14 2 SMB_DATA 27 34
12 11
BI
100 5%
1 13 402 CH
C1R2
.1UF
10% HDR 1 R3B3 2
6.3V EXT_PWR_ON_DBG EXT_PWR_ON_N OUT 44 58 34
2 X5R 27 34 SMB_CLK 1 R2N13 2
402 BI 1K 5%
100 5% 402 CH
402 CH V_5P0STBY V_12P0
1
1 D8B4
C3B8 C3B9 GREEN
.1UF 1UF SM
10% 10%
6.3V 16V 2 LED
2 X5R X7R
402 603 1 CPU_CHECKSTOP_N_LED
R8B6
2K
1%
CH
402
2
CPU_CHECKSTOP_N_LED_B
CPU_CHECKSTOP_N_LED_C
3
1 R8A5 2 1 Q8B6
MMBT2222
1K 5% XSTR V_3P3STBY
402 CH 2
PCIEX DEBUG CONNECTOR
N: DEBUG BOARDS ONLY
I225 2
SM V_1P8 R2P19
J3C1 EMPTY V_1P8 10K
5%
PCIEX
CH
MIDBUS 402
2 1 PEX_GPU_SB_L0_DP
IN 13 2 2 2 2 1
PEX_SB_GPU_L0_DP PEX_GPU_SB_L0_DN
2
33 4 3 13
IN IN R8C3 R8C4 R8C5 R8C6 1 R8P8 SMC_CPU_CHKSTOP_DETECT
33 IN PEX_SB_GPU_L0_DN 6 5 10K 10K 10K 10K C8P5 BI 34
8 7 PEX_GPU_SB_L1_DP 13 5% 5% 5% 5% .1UF 10K
PEX_SB_GPU_L1_DP PEX_GPU_SB_L1_DN
IN 10% 5% SMC_CPU_CHKSTOP_DETECT_B
33 10 9 13 EMPTY EMPTY EMPTY EMPTY 6.3V 3
IN PEX_SB_GPU_L1_DN
IN 402 402 402 402 2 X5R EMPTY
33 IN 12 11
1 1 1 1 402 402 1 R3N8 2 1 Q2P1
14 13 1 MMBT2222
16 15 1K 5% EMPTY
402 EMPTY 2
18 17 J8C1
20 19 2X5HDR
22 21
CPU_RST_V1P1_N 2 R8C2 1 CPU_RST_N_2_R 2 1 CPU_CHECKSTOP_N_R
1 R8C8 2 CPU_CHECKSTOP_N
24 23 4 IN IN 59
1K 5% 4 3 0 5%
402 CH 6 5 402 CH
X801071-001 59 OUT CPU_TMS 8 7 CPU_TCLK OUT 59
59 OUT CPU_TRST_N 10 9 EXT_PWR_ON_N OUT 44 58 34
59 IN CPU_TDO
59 OUT CPU_TDI HDR
N: FOOTPRINT PADS 13-24 REMOVED.
N: REMOVED PADS FREE UP NEEDED 1 1
FT7R7 FTP C7D23
BOARD SPACE FOR ROUTING. .1UF
10%
6.3V
2 X5R
402
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FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=XDK. DEBUG CONN] Tue May 08 18:24:19 2007
CONFIDENTIAL
FALCON_RETAIL 58/82 1.0
CR-59 : @FALCON_LIB.FALCON(SCH_1):PAGE59
X806937-001
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FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=DEBUG BOARD, CPU + GPU DEBUG BREAKOUT] Tue May 08 18:24:19 2007
CONFIDENTIAL
FALCON_RETAIL 59/82 1.0
CR-60 : @FALCON_LIB.FALCON(SCH_1):PAGE66
2 R6G36 1 V_MEM
5% 0
60 BI MEMPORT3_DN_ARGONYETI EMPTY 402 MEMPORT3_DN_ARGON BI 49
60 BI MEMPORT3_DP_ARGONYETI MEMPORT3_DP_ARGON BI 49 2
2 R6G35 1 R7F6
0
5% 0 5%
EMPTY 402 CH
603
J7G3 1
2X6HDR
2 R6V2 1 1 2 V_YETI
5% 0 3 4 N: CONNECTED TO V_MEMPORT
EMPTY 402 MEMPORT3_DN_YETI 5 6 FOR BETTER ROUTING
MEMPORT3_DP_YETI 7 8
9 10
2 R6V1 1 11 12 V_MEMPORT1 46
IN
5% 0
EMPTY 402 HDR 1 2
C7G9 C7G8
.1UF 4.7UF
10% 10%
6.3V 6.3V
1 R7V8 2
2 EMPTY 1 EMPTY
34 IN CPU_PWRGD CPU_PWRGD_R 402 805
5% 1K
CH 402
2 R2D14 1
5% 0
35 BI MEMPORT3_DN EMPTY 402 MEMPORT3_DN_ARGONYETI V_5P0 V_1P8
BI 60 V_3P3
35 BI MEMPORT3_DP MEMPORT3_DP_ARGONYETI BI 60
2 R2D13 1
C2T9
1 2
5% 0
EMPTY 402
1 2 .1UF 10%
J1E2 C2T10 C1T6 6.3V
.1UF 4.7UF EMPTY
1X5HDR 10% 10% 402
2 R2R8 1 6.3V 6.3V
1 2 EMPTY 1 EMPTY C2T8
5% 0 2 402 805 1 2
EMPTY 402 MEMPORT3_DN_FLASH 3
MEMPORT3_DP_FLASH 4 .1UF 10%
6.3V
2 R2R7 1 5 EMPTY
402
5% 0 EMPTY
EMPTY 402
TH
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FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=XDK, DEBUG LEDS, BDCM PHY] Tue May 08 18:24:20 2007
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CR-61 : @FALCON_LIB.FALCON(SCH_1):PAGE67
1
1375X250_TARGET
X801181-001
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG3C1 MTG3E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG6C1 MTG8E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
STD STD
MTG5C1 MTG5E1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
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FALCON_FABD MICROSOFT PROJECT NAME PAGE REV
[PAGE_TITLE=LABELS AND MOUNTING, PCI SWIZ] Tue May 08 18:24:20 2007
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CR-62 : @FALCON_LIB.FALCON(SCH_1):PAGE68
EMPTY
TH
TP8A1 EMPTY
TDRX2
THIS IS ON THE MOTHERBOARD
THE REST IS ON A SEPARATE BOARD ON THE FAN CUTOUT 1 SIG
2 GND
1 DP
2 GND
3 DN
4 GND
TP6A1 EMPTY
TP8M1 EMPTY TDRX2
TDRX4 1 SIG
2 GND
TDR_DIFF_XDK1_DP 1 DP
2 GND
TDR_DIFF_XDK1_DN 3 DN
4 GND
TP8M2 EMPTY
TDRX4
1 DP
2 GND
3 DN
4 GND