8 7 6 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 D C B A DRAWING CSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 47 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CONTENTS MLB_BAFFIN BOM Configuration BOM Configuration PD Parts CPU DMI/PEG/FDI/RSVD CPU Clock/Misc/JTAG/CFG CPU DDR3 Interfaces CPU Power CPU Ground CPU Decoupling 1 [10] CPU Decoupling 2 [11] PCH RTC/HDA/JTAG/SATA/CLK PCH DMI/FDI/PM/GFX/PCI PCH PCI-E/USB PCH GPIO/MISC/NCTF PCH Power PCH DECOUPLING CPU/PCH Merged XDP Chipset Support 1 Chipset Support 2 LPDDR3 VREF MARGINING LPDDR3 DRAM Channel A (0-31) LPDDR3 DRAM Channel A (32-63) LPDDR3 DRAM Channel B (0-31) LPDDR3 DRAM Channel B (32-63) LPDDR3 DRAM Termination USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C Support USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR WIFI/BT: MODULE 1 WIFI/BT: MODULE 2 Camera/DFR 1 Camera/DFR 2 Camera/DFR 3 Berkelium - 1 Berkelium - 2 T208 Support Connectors&ESD External A USB3 Connector MESA SMC SMC Shared Support SMC Project Support SMBus Connections Power Sensors: High Side Power Sensors: Load Side Power Sensors: Extended Power Sensors: Extended 2 Thermal Sensors Sensor Extended 3 Fans SPI Debug Connector HDA Bridge AUDIO JACK CODEC AUDIO Speaker Amps & Conn 5 SYNC J80_MLB J80_MLB_BAFFIN_CLEAN J80_MLB X363_AGOTETI J80_MLB J80_MLB J80_MLB J80_MLB J80_DTUZMAN_MLB_BAFFIN X363_SEAN X363_SAKKOC J80_MLB X363_SAKKOC X363_SAKKOC X363_SAKKOC J80_MLB X363_SAKKOC X363_SAKKOC X363_SAKKOC J80_MLB J80_MLB J80_MLB J80_MLB J80_MLB J80_MLB J80_MLB J80_MLB X363_AGOTETI X362_GKOO J80_MLB X362_MLB X362_MLB J80_ZIFENGSHEN_MLB_BAFFIN X363_SAKKOC J80_MLB X363_SAKKOC X362_T208 X362_T208 X362_T208 X362_T208 X362_T208 X363_SAMANTHA J80_MLB X362_P49 X363_ZIFENGSHEN J80_ZIFENGSHEN_MLB_BAFFIN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN X363_ZIFENGSHEN J80_MLB X363_AUDIO X363_AUDIO X363_AUDIO DATE 07/07/2015 12/02/2015 11/16/2015 01/21/2016 11/06/2015 11/06/2015 08/16/2015 08/17/2015 11/22/2015 02/01/2016 04/14/2016 11/06/2015 04/14/2016 04/29/2016 01/25/2016 11/06/2015 01/25/2016 04/29/2016 01/14/2016 11/06/2015 11/06/2015 11/06/2015 11/06/2015 11/06/2015 11/06/2015 11/06/2015 11/06/2015 08/08/2016 08/08/2016 11/06/2015 03/30/2016 03/29/2016 12/04/2015 04/29/2016 11/06/2015 04/29/2016 03/22/2016 04/25/2016 01/27/2016 03/15/2016 06/30/2016 01/08/2016 08/26/2015 01/08/2016 04/14/2016 11/19/2015 04/14/2016 04/14/2016 04/14/2016 04/14/2016 04/14/2016 04/14/2016 04/14/2016 05/19/2016 04/14/2016 11/06/2015 01/11/2016 01/25/2016 01/25/2016 Schematic / PCB #'s DESCRIPTION REFERENCE DES CRITICAL 051-00647 1 SCHEM,MLB-BAFFIN,X363G SCH CRITICAL 820-00281 1 PCBF,MLB-BAFFIN,X363G PCB CRITICAL WWW.AliSaler.Com 8 CSA 65 66 69 70 71 72 73 74 76 78 79 80 81 82 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 120 121 122 123 124 125 126 127 128 130 141 142 7 BOM OPTION 1 REV ECN DESCRIPTION OF REVISION CONTENTS AUDIO Speaker Amps & Conn AUDIO JACK CONNECTOR DC-In & Battery Connectors PBUS Supply & Battery Charger CORE & SA IMVP IC CORE IMVP POWER BLOCK SA IMVP IC GT & GTX IMVP POWER BLOCK Power - 5V 3.3V Supply PMIC-1 & Power Control PMIC-1 1.2V 0.6V VCCIO PMIC-1 1V 1.8V VCCPCH PMIC-1 Aliases & TPs Power FETs LCD Backlight Driver eDP Display Connector POLARIS_CONTROLLER POLARIS POWER POLARIS GND Connector TEMP SENSORS NAND 1/2 NAND 2/2 POLARIS PMIC SSD NAND VR SSD SUPPORT Lifeboat Constraints eDP Mux GPU PCC BAFFIN PCI-E Baffin CORE/FB POWER Baffin FRAME BUFFER I/F Baffin 1V05 GPU / 1V35 FB Power Supply GDDR5 Frame Buffer A GDDR5 Frame Buffer B GFX IMVP VCore Regulator [106] Baffin GPIOs,CLK & Straps Baffin DP/GPIO Baffin VSS & MISC USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C Support USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR Power Aliases - 1 Power Aliases - 2 Signal Aliases Memory Bit/Byte Swizzle ICT & FCT 1 ICT & FCT 2 NC & No Test Desense Caps Desense Caps Project Specific Constraints 639 BOM Configuration 639 BOM Configuration 2 SYNC DATE 01/25/2016 X363_AUDIO 11/06/2015 J80_MLB J80_MLB 11/06/2015 J80_MLB 11/06/2015 J80_DTUZMAN_MLB_BAFFIN 12/10/2015 J80_DTUZMAN_MLB_BAFFIN 09/03/2015 J80_DTUZMAN_MLB_BAFFIN 11/18/2015 J80_DTUZMAN_MLB_BAFFIN 09/03/2015 J80_DTUZMAN_MLB_BAFFIN 12/09/2015 12/08/2015 J80_MLB 11/06/2015 J80_MLB X363_ZIFENGSHEN 04/14/2016 J80_SILUCHEN_MLB_BAFFIN 12/08/2015 12/11/2015 J80_SAKKOC_MLB_BAFFIN 12/03/2015 J80_DTUZMAN_MLB_BAFFIN 12/03/2015 J80_ZIFENGSHEN_MLB_BAFFIN 04/01/2016 X363_JSAMUELS 05/18/2016 X363_JSAMUELS 04/01/2016 X363_JSAMUELS 04/01/2016 X363_JSAMUELS 11/06/2015 J80_MLB 08/09/2016 X363_JSAMUELS 08/09/2016 X363_JSAMUELS 08/09/2016 X363_JSAMUELS 04/01/2016 X363_JSAMUELS 04/15/2016 X363_ZIFENGSHEN 01/20/2016 X363_BBABADI 05/18/2016 Constraints 08/22/2015 dpmux 01/27/2016 X363_SEAN 01/27/2016 X363_SEAN 02/01/2016 X363_SEAN 04/29/2015 J80_SEAN 12/08/2015 J80_DTUZMAN_MLB_BAFFIN 04/29/2015 J80_SEAN 04/29/2015 J80_SEAN 12/08/2015 J80_DTUZMAN_MLB_BAFFIN 01/28/2016 X363_SEAN X363_SEAN 01/27/2016 01/27/2016 X363_SEAN J80_MLB 11/06/2015 11/06/2015 J80_MLB 12/07/2015 J80_AGOTETI_MLB_BAFFIN J80_MLB 11/06/2015 11/06/2015 J80_MLB 03/30/2016 X362_MLB 03/29/2016 X362_MLB 12/04/2015 J80_ZIFENGSHEN_MLB_BAFFIN 08/16/2015 J80_MLB 01/14/2016 X363_SAKKOC 01/13/2016 X363_SAKKOC 11/06/2015 J80_MLB 04/14/2016 X363_SAKKOC 12/10/2015 J80_BBABADI_MLB_BAFFIN 01/26/2016 X363_BBABADI 04/15/2016 X363_ZIFENGSHEN 05/18/2016 DESENSE X363_ZIFENGSHEN 06/02/2016 07/23/2015 J80_MLB 07/23/2015 J80_MLB This is the PVT design 10 0006897289 ENGINEERING RELEASED 2016-08-24 D C B A DRAWING TITLE SCHEM,MLB-BAFFIN,X363 DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE SHEET IV ALL RIGHTS RESERVED 5 4 3 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 6 CK APPD DATE LAST_MODIFICATION=Wed Aug 24 09:57:44 2016 LAST_MODIFIED=Wed Aug 24 09:57:44 2016 QTY PAGE 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 2 3 SCHEM,MLB_BAFFIN,X363G TITLE=MLB_BAFFIN ABBREV=ABBREV PART NUMBER 4 1 1 OF 145 1 OF 121 SIZE D 8 7 6 5 BOM Variants 4 3 2 1 X363 BOM Groups TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 685-00076 COMMON PARTS,MLB-BAFFIN,X363 X363_COMMON 985-00126 DEV,MLB-BAFFIN,X363 X363_DEVEL:PVT 985-00232 DEV,MLB-BAFFIN,PVT,X363 X363_DEVEL:PVT TABLE_BOMGROUP_HEAD BOM GROUP TABLE_BOMGROUP_ITEM BOM OPTIONS TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639 BOMs have been moved to the end of the schematic TABLE_BOMGROUP_ITEM X363_COMMON1 SOC:HYNIX,SE:PROD,SKIP_5V3V3:AUDIBLE,DIPLEXER:MURATA,T208_PROG:REV5,BOARD_ID:17,VCCHDA:S0 X363_COMMON2 XDP:YES,SAMCONN,SOC_BOOT:SPI,DPMUX_XTAL:NO,GPUCLK:OSC,BAFFIN,AP_TEMP,VCCPLLOC:S3,WIFI_SAK:NO X363_COMMON3 CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,OTHERRC:YES,DDRRC:YES,TBTRC:YES,TPADRC:YES,LID_FEATURE_ON X363_COMMON4 EDP:YES,CPUPEG:X8X4X4,TBTTHRM_SNS,GPUTHRM_SNS,S3_STATE:YES,GPU_ROM:YES,SVID_PU:CORE TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM X363_PROGPARTS D TABLE_BOMGROUP_ITEM ALTERNATE,COMMON,X363_COMMON1,X363_COMMON2,X363_COMMON3,X363_COMMON4,X363_PROGPARTS X363_COMMON D BOOTROM_PROG:DVT,BT_PROG:DVT,WIFI_PROG:DVT,UPCROM_PROG:DVT,SMC_PROG:PVT,DPMUXMCU:PROG,PCC:NO TABLE_BOMGROUP_ITEM X363_DEVEL:ENG ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG,GPUROM:BLANK,PCC:YES X363_DEVEL:DVT ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG X363_DEVEL:PVT ALTERNATE,XDP_CONN,USBC_DBG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM ENGISNS TABLE_BOMGROUP_ITEM TBTISNS,LOADISNS,TPADISNS,DDRISNS,OTHERISNS Module Parts PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION Strategic Silicon 337S00227 1 CPU,SKY,SR2FT,R1,PRQ,4/2,2.9,BGA1440 U0500 CRITICAL CPU_SKL:2.9 337S00228 1 CPU,SKY,SR2FU,R1,PRQ,4/2,2.7,BGA1440 U0500 CRITICAL CPU_SKL:2.7 PART# 337S00229 1 CPU,SKY,SR2FQ,R1,PRQ,4/2,2.6,BGA1440 U0500 CRITICAL CPU_SKL:2.6 337S00227 08 CPU 998-04701 1 INTERPOSER,INTEL,BGA1440,MM940989 U0500 CRITICAL CPU_SKL:SOCKET 337S00228 08 CPU 337S00258 1 IC,SKL PCH-H,SFF,SR2NH,PRQ,D1,BGA939 U1100 CRITICAL 337S00229 08 CPU 353S00961 4 IC,CD3215,ACE,C0,USB PWR SW,BLNK,BGA96 U3100,U3200,UB300,UB400 CRITICAL 333S00050 07 MAIN MEMORY 338S00254 2 IC,TBT,ALPINE RIDGE DP,QT5S,QS,C1,BGA337 U2800,UB000 CRITICAL 333S00070 07 MAIN MEMORY 353S01016 1 IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM U7000 CRITICAL 335S00149 02 SSD NAND 338S00221 1 IC,PMU,P650839,7X7MM.BGA168 U7800 CRITICAL 335S00204 02 SSD NAND 338S00142 1 U6300 CRITICAL 335S00205 02 SSD NAND 337S00330 1 UA000 CRITICAL 335S00219 02 SSD NAND TABLE_STRATEGIC_HEAD STRATEGIC VALUE COMMENT TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM C IC,CODEC,CLIFDEN,CS42L83A,B0,WLCSP49 IC,GPU,BAFFIN,ULA,A1,PS,BGA769 TABLE_STRATEGIC__ITEM BAFFIN_ULA C TABLE_STRATEGIC__ITEM 337S00331 1 IC,GPU,BAFFIN,PROA,A1,PS,BGA769 UA000 CRITICAL BAFFIN_PROA 339S00154 02 SSD CONTROLLER 337S00332 1 IC,GPU,BAFFIN,LEA,A1,PS,BGA769 UA000 CRITICAL BAFFIN_LEA 339S00155 02 SSD CONTROLLER 998-04866 1 INTERPOSER,AMD,C989,BGA769,VDDCI/MVDD UA000 CRITICAL STARDUST:VDDCI_MVDD 338S00166 02 SSD PMIC 998-04867 1 INTERPOSER,AMD,C988,BGA769,VDDC UA000 CRITICAL STARDUST:VDDC 337S00225 08 GPU 677-04532 2 SUBASSY (T&R) PCBA, AMR, INTERPOSER, X363 J5250,J5260 CRITICAL 337S00285 08 GPU 337S00286 08 GPU 333S00044 07 VIDEO MEMORY 333S00043 07 VIDEO MEMORY 333S00078 07 VIDEO MEMORY 333S00074 07 VIDEO MEMORY 333S00075 07 VIDEO MEMORY 343S00135 10 T208 343S00136 10 T208 343S00137 10 T208 338S00138 10 T208 338S00193 09 BERKELIUM 353S3978 02 MOJAVE 338S00097 02 SECURE ELEMENT TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM Development/Base BOMs PART NUMBER QTY DESCRIPTION TABLE_STRATEGIC__ITEM REFERENCE DES CRITICAL BOM OPTION 685-00076 1 COMMON PARTS,MLB-BAF,X363 BASE CRITICAL BASE_BOM 985-00126 1 DEV,MLB-BAF,X363 DEVEL CRITICAL DEVEL_BOM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM WIFI/BT Diplexers PART NUMBER 155S0979 QTY TABLE_STRATEGIC__ITEM DESCRIPTION 3 FLTR,DIPLEXER,2.45/5.54GHZ,0805 REFERENCE DES CRITICAL U3810,U3820,U3830 CRITICAL BOM OPTION DIPLEXER:MURATA TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM B B TABLE_STRATEGIC__ITEM GPU Options TABLE_STRATEGIC__ITEM 338S00254 08 ALPINE RIDGE 353S00961 09 ACE 338S00142 09 CLIFDEN 353S00604 07 AUDIO AMP 353S4316 08 BAYSIDE 338S00221 08 BANJO 353S00853 09 TUBA 339S00056 05 ICEBOCK 359S00006 08 GREEN CLOCK 353S00795 09 DEBUG MUX TABLE_STRATEGIC__ITEM TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS TABLE_STRATEGIC__ITEM TABLE_BOMGROUP_ITEM 2GB_MC_BAFFIN FB_2GB_MICRON,VRAM:GRP1 TABLE_STRATEGIC__ITEM TABLE_BOMGROUP_ITEM 2GB_HY_BAFFIN FB_2GB_HYNIX,VRAM:GRP1 TABLE_STRATEGIC__ITEM TABLE_BOMGROUP_ITEM 2GB_SM_BAFFIN FB_2GB_SAMSUNG,VRAM:GRP2 TABLE_STRATEGIC__ITEM TABLE_BOMGROUP_ITEM 4GB_SM_BAFFIN FB_4GB_SAMSUNG,VRAM:GRP1 Main DRAM Parts TABLE_BOMGROUP_ITEM 4GB_MC_BAFFIN FB_4GB_MICRON,VRAM:GRP1 TABLE_STRATEGIC__ITEM TABLE_STRATEGIC__ITEM PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_STRATEGIC__ITEM 333S00050 333S00070 QTY IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178 IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178 U2300,U2400,U2500,U2600 U2300,U2400,U2500,U2600 CRITICAL CRITICAL 16G_SAMSUNG_2133 TABLE_STRATEGIC__ITEM 16G_MICRON_2133 Main DRAM SPD Straps FB VDRAM Parts PART NUMBER 4 4 TABLE_BOMGROUP_HEAD DESCRIPTION REFERENCE DES CRITICAL BOM GROUP BOM OPTION BOM OPTIONS TABLE_BOMGROUP_ITEM A 333S00044 333S00043 333S00078 333S00074 333S00075 4 4 4 4 4 IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA UA400,UA450,UA500,UA550 IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA UA400,UA450,UA500,UA550 IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA UA400,UA450,UA500,UA550 IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA UA400,UA450,UA500,UA550 IC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA UA400,UA450,UA500,UA550 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL FB_2GB_MICRON RAM_16G_SAMSUNG_2133 16G_SAMSUNG_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG0:L RAM_16G_MICRON_2133 16G_MICRON_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG1:L TABLE_BOMGROUP_ITEM FB_2GB_HYNIX FB_2GB_SAMSUNG SYNC_MASTER=J80_MLB FB_4GB_SAMSUNG PAGE TITLE SYNC_DATE=07/07/2015 BOM Configuration FB_4GB_MICRON DRAWING NUMBER Apple Inc. Sub-BOM DIPLEXER 685-00085 REVISION R TABLE_BOMGROUP_HEAD BOM NUMBER 051-00647 BOM NAME BOM OPTIONS DIPLEXERS,MURATA,X363G DIPLEXER:MURATA TABLE_BOMGROUP_ITEM NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 2 OF 145 2 OF 121 SIZE D A 8 7 6 5 4 3 2 1 Programmable Parts PART NUMBER D QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 338S1231 1 IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA U5000 CRITICAL SMC_PROG:BLANK 341S00701 1 IC,SMC-B1,EXT (v2.37F7) PVT,X363G U5000 CRITICAL SMC_PROG:PVT 335S00013 1 IC,SPI SERIAL FLASH,64M BITS,3V,8P SOIC,QE=1 U6100 CRITICAL BOOTROM_PROG:BLANK 341S00699 1 IC,EFI ROM (V0193), DVT, X363G U6100 CRITICAL BOOTROM_PROG:DVT Macronix/Winbond 353S00926 2 IC,CD3215,ACE,B03,BLNK,BGA96 U2890,UB090 CRITICAL UPCROM_PROG:BLANK Blank 341S00707 1 T29,AR1 (V10.5) PVT, X363G U2890 CRITICAL UPCROM_PROG:DVT Winbond 341S00708 1 T29,AR2 (V10.5) PVT, X363G UB090 CRITICAL UPCROM_PROG:DVT Winbond 335S00024 1 IC,SERIAL-FLASH,2MBIT,4V,8-USON,2x3x,6MM U3750 CRITICAL BT_PROG:BLANK 341S00695 1 IC,BT ROM (V28), DVT, X362/X363 U3750 CRITICAL BT_PROG:DVT 341S00709 1 WIFI ROM (P107) DVT,NEW,WW1,X362/X363 U3710 CRITICAL WIFI_PROG:DVT 341S3565 1 IC, EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2 U9800 CRITICAL DPMUXMCU:PROG 335S0724 1 IC,1Mbit SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG UA701 CRITICAL GPUROM:BLANK Blank TI Blank D Blank Macronix/Winbond Rohm/On Semi Blank C C B B A SYNC_MASTER=J80_MLB_BAFFIN_CLEAN SYNC_DATE=12/02/2015 PAGE TITLE BOM Configuration DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 3 OF 145 3 OF 121 SIZE D A 8 7 6 Pogo Pins APN 870-01771 SMT Bosses PG0410 BS0401 BS0400 SM USB-C Left BOT side - North 1 1 POGO-2.3OD-4.63H-SM SM 1 1 POGO-2.3OD-4.63H-SM SM TH0401 TH-NSP 3.4OD1.75ID-1.12H-SM USB-C Right BOT side - South 1 1 APN 860-00435 3.4OD1.75ID-1.45H-SM TH0410 TH-NSP DFR Touch BOT side 1 1 1 1 BS0480 3.4OD1.75ID-2.12H-SM 1 TH0411 TH-NSP 1 BM0402 2.8OD1.2ID-1.55H-SM PG0421 SM TH0420 TH-NSP 3.4OD1.75ID-1.9H-SM 1 PG0430 DFR Display BOT side - Left 3.4OD1.75ID-1.9H-SM 1 DFR Display BOT side - Right C 3.4OD1.75ID-1.9H-SM 2 1 Keyboard BOT side - Left 1 POGO-2.3OD-4.63H-SM SM 3.4OD1.75ID-1.9H-SM 1 1 1 Trackpad BOT side - Left 3.4OD1.75ID-1.9H-SM 1 1 2 TH0450 TH-NSP 1 2.8OD1.2ID-1.55H-SM BS0460 1 3.4OD1.75ID-1.57H-SM 3.4OD1.75ID-1.57H-SM Lifeboat BOT side - North 1 TH0451 TH-NSP 2 BS0461 TH0460 TH-NSP 1 1 2 POGO-2.3OD-4.06H-SM BS0470 BS0701 eDP TOP side - Left 1 TBT Right - BOT side - South 1 1 SH0430 T208 - TOP side SM APN 806-07814 SHLD-FENCE-M8-X379 1 OMIT_TABLE SH0440 SM SSD - BOT side - North C SSD - TOP side APN 806-06584 SHLD-FENCE-MLB-M8-X379 1 SSD - BOT side - South OMIT_TABLE SH0450 SSD - BOT side SM APN 806-06585 SHLD-FENCE-MLB-M8-X379 SSD - TOP side - North OMIT_TABLE 1 SSD - TOP side - South Diplexer - BOT side SH0460 APN 806-06591 SM SHLD-FENCE-MLB-M8-X379 Frame Buffer Memory - BOT side - Left 1 OMIT_TABLE SH0470 VRAM - BOT side SM Frame Buffer Memory - BOT side - Right APN 806-08026 SL-1.1X0.4-1.4X0.7 SHLD-FENCE-MLB-M8-X379 B 2 2.7X1.8R-1.4ID-0.91H-SM 1 APN 806-06588 SHLD-FENCE-MLB-M8-X379 1 2.7X1.8R-1.4ID-0.91H-SM SM 1 2.8OD1.2ID-1.55H-SM APN 860-00469 PG0401 TH0461 TH-NSP BM0408 SM B TBT Right - BOT side - North SL-1.1X0.4-1.4X0.7 PG0400 POGO-2.3OD-4.06H-SM AR Left - BOT side SM BM0407 2.8OD1.2ID-1.55H-SM APN 870-01772 1 SH0420 SL-1.1X0.4-1.4X0.7 Lifeboat BOT side - South 1 OMIT_TABLE SL-1.1X0.4-1.4X0.7 1 APN 860-00413 1 SL-1.1X0.4-1.4X0.7 BM0406 PG0470 1 TH0441 TH-NSP 1 Trackpad BOT side - Right APN 806-06586 SHLD-FENCE-MLB-M8-X379 TBT Left - BOT side - South SL-1.1X0.4-1.4X0.7 2.8OD1.2ID-1.55H-SM BS0451 POGO-2.3OD-4.63H-SM SM TH0440 TH-NSP BM0405 BS0450 AR Right - BOT side SH0410 SM T208 - TOP side - South 2 PG0471 TBT Left - BOT side - North T208 through holes are non-plated... for now 1 Keyboard BOT side - Right DRAM - BOT side OMIT_TABLE 1 T208 - TOP side - North 2.8OD1.2ID-1.55H-SM BS0441 3.4OD1.75ID-1.9H-SM D SHLD-FENCE-MLB-M8-X379 SL-1.1X0.4-1.4X0.7 BM0404 BS0440 1 1 1 POGO-2.3OD-4.63H-SM SM TH0421 TH-NSP 2.8OD1.2ID-1.55H-SM BS0431 SH0400 APN 806-06590 System Memory - BOT side - Right SL-1.1X0.4-1.4X0.7 BM0403 BS0430 1 1 2 APN 806-06521 OMIT_TABLE SM SL-1.1X0.4-1.4X0.7 1 POGO-2.3OD-4.63H-SM 1 SL-1.1X0.4-1.4X0.7 2 USB-C Right BOT side - Left System Memory - BOT side - Left SL-1.1X0.4-1.4X0.7 BM0401 APN 806-06600 BS0420 Shield Can Fence SL-1.1X0.4-1.4X0.7 2.8OD1.2ID-1.55H-SM APN 806-06520 PG0420 TH0400 TH-NSP 1 BS0411 USB-C Right BOT side - North 1 1 APN 998-2691 3.09OD1.4ID-3.25H-SM 2 3.4OD1.75ID-1.12H-SM 2 Shield Can TH BM0400 USB-C Left BOT side - South 1 BS0410 PG0411 3 APN 860-00452 3.4OD1.75ID-1.12H-SM 3.4OD1.75ID-1.12H-SM 4 Rubber Mount Standoffs APN 860-00392 POGO-2.3OD-4.63H-SM D 5 eDP TOP side - Right BM0409 2.8OD1.2ID-1.55H-SM 1 2 TOUCH-COWLING-HOOK-X378 1 BS0704 SM Shield Can Omit Table BM0410 2.8OD1.2ID-1.55H-SM APN 806-07958 DFR Touch - TOP side 1 PART NUMBER 2 806-08023 1 SHIELD,FENCE,DRAM,X378 SH0400 CRITICAL 806-08019 1 SHIELD,FENCE,ALPINE RIDGE,RIGHT,X378 SH0410 CRITICAL 806-08021 1 SHIELD,FENCE,ALPINE RIDGE,LEFT,X378 SH0420 CRITICAL 806-07918 1 SHIELD,NAND,TOP,ALT,X363 SH0440 CRITICAL 806-07917 1 SHIELD,NAND,BOTTOM,ALT,X363 SH0450 CRITICAL 1 806-08024 1 SHIELD,DIPLEX,EG,X378 SH0460 CRITICAL 2 806-08026 1 FENCE,VRAM,EG,X378 SH0470 CRITICAL BM0411 2.8OD1.2ID-1.55H-SM APN 860-00500 1 BM0485 2.8OD1.2ID-3.5H-SM 2 BM0483 2.8OD1.2ID-1.55H-SM QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 1 BM0486 2 A 2.8OD1.2ID-3.5H-SM SYNC_MASTER=J80_MLB PAGE TITLE 1 APN 860-00500 SYNC_DATE=11/16/2015 PD Parts 2 DRAWING NUMBER BM0484 2.8OD1.2ID-3.5H-SM Apple Inc. BM0487 1 REVISION R 2.8OD1.2ID-3.5H-SM 2 051-00647 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=MECHANICALS WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 4 OF 145 4 OF 121 SIZE D A 6 5 PPVCCIO_S0_CPU OMIT_TABLE 1 13 113 13 113 13 113 13 IN IN IN IN 113 13 IN 113 13 IN 113 13 IN 113 13 IN 113 13 113 13 OUT 113 13 OUT 113 13 OUT OUT 113 13 113 13 OUT 113 13 OUT 113 13 OUT D8 E6 D5 J8 DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3> A8 B6 A5 B4 DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3> B8 C6 B5 D4 SYM 1 OF 13 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 C PEG_RCOMP G2 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 PEG_GPU_D2R_N<0> PEG_GPU_D2R_N<1> PEG_GPU_D2R_N<2> PEG_GPU_D2R_N<3> PEG_GPU_D2R_N<4> PEG_GPU_D2R_N<5> PEG_GPU_D2R_N<6> PEG_GPU_D2R_N<7> PCIE_TBT_X_D2R_N<0> PCIE_TBT_X_D2R_N<1> PCIE_TBT_X_D2R_N<2> PCIE_TBT_X_D2R_N<3> PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_N<2> PCIE_TBT_T_D2R_N<3> PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 D25 F24 D23 F22 D21 F20 D19 F18 E17 E16 E15 E14 E13 E12 E11 E10 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 E25 E24 E23 E22 E21 E20 E19 E18 D17 F16 D15 F14 D13 F12 D11 F10 111 PEG_GPU_D2R_P<0> PEG_GPU_D2R_P<1> PEG_GPU_D2R_P<2> PEG_GPU_D2R_P<3> PEG_GPU_D2R_P<4> PEG_GPU_D2R_P<5> PEG_GPU_D2R_P<6> PEG_GPU_D2R_P<7> PCIE_TBT_X_D2R_P<0> PCIE_TBT_X_D2R_P<1> PCIE_TBT_X_D2R_P<2> PCIE_TBT_X_D2R_P<3> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_D2R_P<2> PCIE_TBT_T_D2R_P<3> PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 A25 C24 A23 C22 A21 C20 A19 C18 B17 B16 B15 B14 B13 B12 B11 B10 PEG_GPU_R2D_C_N<0> OUT PEG_GPU_R2D_C_N<1> OUT PEG_GPU_R2D_C_N<2> OUT PEG_GPU_R2D_C_N<3> OUT PEG_GPU_R2D_C_N<4> OUT PEG_GPU_R2D_C_N<5> OUT PEG_GPU_R2D_C_N<6> OUT PEG_GPU_R2D_C_N<7> OUT PCIE_TBT_X_R2D_C_N<0> OUT PCIE_TBT_X_R2D_C_N<1> OUT PCIE_TBT_X_R2D_C_N<2> OUT PCIE_TBT_X_R2D_C_N<3> OUT PCIE_TBT_T_R2D_C_N<0> OUT PCIE_TBT_T_R2D_C_N<1> OUT PCIE_TBT_T_R2D_C_N<2> OUT PCIE_TBT_T_R2D_C_N<3> OUT IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 IN 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 IN 111 111 111 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 B U0500 SKYLAKE-4+4E PLACE_NEAR=U0500.G2:5mm CPU_PEG_RCOMP B25 B24 B23 B22 B21 B20 B19 B18 A17 C16 A15 C14 A13 C12 A11 C10 IN 111 111 IN 111 111 IN 111 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 IN 111 PEG_GPU_R2D_C_P<0> OUT PEG_GPU_R2D_C_P<1> OUT PEG_GPU_R2D_C_P<2> OUT PEG_GPU_R2D_C_P<3> OUT PEG_GPU_R2D_C_P<4> OUT PEG_GPU_R2D_C_P<5> OUT PEG_GPU_R2D_C_P<6> OUT PEG_GPU_R2D_C_P<7> OUT PCIE_TBT_X_R2D_C_P<0> OUT PCIE_TBT_X_R2D_C_P<1> OUT PCIE_TBT_X_R2D_C_P<2> OUT PCIE_TBT_X_R2D_C_P<3> OUT PCIE_TBT_T_R2D_C_P<0> OUT PCIE_TBT_T_R2D_C_P<1> OUT PCIE_TBT_T_R2D_C_P<2> OUT PCIE_TBT_T_R2D_C_P<3> OUT 111 111 111 111 BGA NC_DDI1_ML_C_N<0> NC_DDI1_ML_C_P<0> NC_DDI1_ML_C_N<1> NC_DDI1_ML_C_P<1> NC_DDI1_ML_C_N<2> NC_DDI1_ML_C_P<2> NC_DDI1_ML_C_N<3> NC_DDI1_ML_C_P<3> K37 K36 J34 J35 H36 H37 J38 J37 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 NC_DDI2_ML_C_N<0> NC_DDI2_ML_C_P<0> NC_DDI2_ML_C_N<1> NC_DDI2_ML_C_P<1> NC_DDI2_ML_C_N<2> NC_DDI2_ML_C_P<2> NC_DDI2_ML_C_N<3> NC_DDI2_ML_C_P<3> H33 H34 G38 F37 F35 F34 E36 E37 DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 NC_DDI3_ML_N<2> NC_DDI3_ML_P<2> NC_DDI3_ML_N<3> NC_DDI3_ML_P<3> E33 F33 B33 C33 DDI3_TXN2 DDI3_TXP2 DDI3_TXN3 DDI3_TXP3 NC_DDI3_ML_N<0> NC_DDI3_ML_P<0> NC_DDI3_ML_N<1> NC_DDI3_ML_P<1> Port D pins out of order to match Intel symbol. D34 C34 B34 B36 DDI3_TXN0 DDI3_TXP0 DDI3_TXN1 DDI3_TXP1 SYM 11 OF 13 111 DP_INT_IG_ML_N<0> DP_INT_IG_ML_N<1> DP_INT_IG_ML_N<2> DP_INT_IG_ML_N<3> EDP_TXP0 EDP_TXP1 EDP_TXP2 EDP_TXP3 D29 F28 A29 C28 DP_INT_IG_ML_P<0> DP_INT_IG_ML_P<1> DP_INT_IG_ML_P<2> DP_INT_IG_ML_P<3> 89 113 89 113 89 113 D 89 113 89 113 89 113 PPVCCIO_S0_CPU 89 113 89 113 5 8 109 89 113 1 89 113 R0530 1% 1/16W MF-LF 2 402 CPU_EDP_RCOMP DDI1_AUXN DDI1_AUXP E27 D27 NC_DDI1_AUXCH_C_N NC_DDI1_AUXCH_C_P DDI2_AUXN DDI2_AUXP E26 F26 NC_DDI2_AUXCH_C_N NC_DDI2_AUXCH_C_P DDI3_AUXN DDI3_AUXP B27 A27 NC_DDI3_AUXCH_N NC_DDI3_AUXCH_P SKYLAKE-4+4E 111 111 E29 E28 B29 B28 D37 A33 U0500 111 EDP_TXN0 EDP_TXN1 EDP_TXN2 EDP_TXN3 EDP_RCOMP EDP_DISP_UTIL 111 111 DP_INT_IG_AUX_N DP_INT_IG_AUX_P 24.9 111 111 B26 C26 PLACE_NEAR=U0500.D37:5mm NC 111 111 111 111 111 111 OMIT_TABLE 111 111 EDP_AUXN EDP_AUXP C 111 111 1 OMIT_TABLE R0510 111 PCI EXPRESS BASED INTERFACE SIGNALS OUT DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3> DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI D 113 BGA 2 5 8 109 1% 1/16W MF-LF 2 402 SKYLAKE-4+4E E8 F6 E5 J9 3 24.9 U0500 DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3> 4 EDP 7 DIGITAL DISPLAY INTERFACES 8 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP0501 TP0502 TP 1 TP 1 TP0503 TP0504 TP0505 1 TP 1 TP TP CPU_DC_B2_C1 CPU_DC_B38_C38 CPU_DC_BR2_BR1 CPU_DC_C1_B2 CPU_DC_C38_B38 1 NC NC 111 B2 B38 BP1 BR2 C1 C38 BR33 AT13 NC 111 BGA NCTF NCTF NCTF NCTF NCTF NCTF SYM 13 OF 13 OPC_RCOMP BT29 OPCE_RCOMP BR25 OPCE_RCOMP2 BP25 CPU_EOPIO_RCOMP CPU_OPC_OPIO_RCOMP CPU_OPC_OPIO_RCOMP_ED2 PROC_TRIGIN H23 PROC_TRIGOUT J23 PCH_CPU_TRIGGER CPU_PCH_TRIGGER_R PCH_DISPA_BCLK PCH_DISPA_SDO CPU_PROC_AUD_SDO_R PROC_AUDIO_CLK G27 PROC_AUDIO_SDI G25 PROC_AUDIO_SDO G29 SKTOCC* ZVM* 111 DDR_VTT_CNTL BT13 111 AW13 NC MSM* IN 1 IN 20 IN 20 OUT CPU_PCH_PM_DOWN_R R0521 1 R0522 1 R0523 49.9 49.9 1% 1/20W MF 2 201 5 PM_MEMVTT_EN PM_DOWN BP31 13 5 1% 1/20W MF 2 201 49.9 1% 1/20W MF 2 201 71 5 111 111 111 CPU Daisy-Chain Strategy: 111 111 Each corner of CPU has two testpoints. Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP's on each corner. 111 111 111 111 B 111 111 R0524 111 111 5 111 CPU_PCH_TRIGGER_R 1 30 2 CPU_PCH_TRIGGER OUT 13 CPU_PCH_PM_DOWN OUT 13 PCH_DISPA_SDI OUT 20 5% 1/20W MF 201 111 111 R0525 5 CPU_PCH_PM_DOWN_R 1 20 2 5% 1/20W MF 201 R0526 5 CPU_PROC_AUD_SDO_R 1 20 2 5% 1/20W MF 201 A SYNC_MASTER=X363_AGOTETI PAGE TITLE SYNC_DATE=01/21/2016 CPU DMI/PEG/FDI/RSVD DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 5 OF 145 5 OF 121 SIZE D A 8 7 6 5 110 11 8 6 4 3 2 1 PP1V0_S3 PLACE_NEAR=U0500.BM30:10mm 1 R0604 49.9 1% 1/20W MF 2 201 11 8 6 U0500 PP1V0_S0SW Note: Confirm values for 0603 and 0601. Different for J145 PP1V0_S3 BGA BN1 NC 1 R0605 1K 65 47 46 CPU_PROCHOT_L R0601 1K 1% 1/16W MF-LF 2 402 46 PLACE_NEAR=U0500.BR30:5mm R0603 1 499 47 13 OUT CPU_CATERR_L BM30 CATERR* BI CPU_PECI BT34 PECI CPU_PROCHOT_R_L 2 1% 402 1/16W MF-LF OUT PROC_SELECT* BR30 PM_THRMTRIP_L 13 IN 13 IN 13 IN J31 PM_SYNC CPU_RESET_L CPU_PWRGD BM34 BP35 BT31 PROCHOT* 1 PROC_PRDY* BP27 PROC_PREQ* BL30 XDP_CPU_PRDY_L XDP_CPU_PREQ_L (IPD) PROC_TCK BR28 (IPU) PROC_TMS BP28 (IPU) PROC_TRST* BP30 XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L (IPU) (IPU) THERMTRIP* PM_SYNC RESET* PROCPWRGD CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2> DDR_RCOMP0 G1 DDR_RCOMP1 H1 DDR_RCOMP2 J2 SYM 2 OF 13 (IPU) XDP_CPU_TDI XDP_CPU_TDO PROC_TDI BL32 PROC_TDO BT28 OUT 13 18 115 IN 13 18 115 IN 18 115 IN 18 115 IN 13 18 115 IN 18 115 OUT 18 115 R0614 162 1% 1/16W MF-LF 2 402 1 1 R0613 121 R0612 200 1% 1/16W MF-LF 2 402 1% 1/16W MF-LF 2 402 JTAG 48 47 46 13 BI 1% 1/16W MF-LF 2 402 1 D SKYLAKE-4+4E DDR3 110 18 11 8 THERMAL 110 PWR D OMIT_TABLE C 12 IN 113 12 IN 113 12 IN 113 12 IN 113 12 IN 113 12 IN CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P D31 E31 (IPU) (IPU) (IPU) (IPU) CLK24N CLK24P CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P C36 D35 PCI_BCLKN PCI_BCLKP CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P A32 B31 BCLKN BCLKP CLOCK 113 BPM0* BPM1* BPM2* BPM3* XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> BR27 BT27 BM31 BT30 BI 18 BI 18 BI 18 BI 18 C PLACE_NEAR=U0500.BT31:157mm R0611 1 10K 5% 1/16W MF-LF 402 2 OMIT_TABLE U0500 SKYLAKE-4+4E P2MM PP0600 SM PP PP PP0603 6 1 TP_CPU_RSVD_N29 6 TP_CPU_RSVD_AE29 6 P2MM SM PP0602 TP_CPU_RSVD_R14 P2MM SM PP0601 1 PP 1 SM PP 1 TP_CPU_RSVD_AA14 [7] :PEG DEFER TRAINING [6:5] :PCIE BIFURCATION [4] :eDP ENABLE/DISABLE [3] :PCIE x4 LANE REVERSAL [2] :PCIE x16 LANE REVERSAL RSVD_TP RSVD_TP TP_CPU_RSVD_TP_BL33 TP_CPU_RSVD_TP_BM33 BL33 BM33 RSVD_TP RSVD_TP D1 RSVD_TP R0649 NOSTUFF 1 R0648 1K 1 109 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 1 = DISABLED 0 = ENABLED 1 = NORMAL OPERATION 0 = LANES REVERSED 1 = NORMAL OPERATION 0 = LANES REVERSED 1K 5% 1/20W MF 201 2 5% 1/20W MF 201 2 NOSTUFF 1 R0643 1K 5% 1/20W MF 2 201 V30 V12 V29 Y35 PPVCC_S0_CPU 55 8 6 6 6 6 NOSTUFF R0641 1 1K 5% 1/20W MF 201 2 CPU_CFG<16> CPU_CFG<9> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0> NOSTUFF 1 6 18 18 6 6 18 18 6 6 18 115 18 6 115 6 18 6 18 18 6 18 6 18 6 R0640 18 6 1K 18 6 5% 1/20W MF 2 201 18 18 6 18 18 18 18 18 A NOSTUFF R0647 CPUCFG6_PD R0646 1K 1 1 5% 1/20W MF 201 2 1K 5% 1/20W MF 201 2 CPUCFG5_PD 1 R0645 1K 5% 1/20W MF 2 201 BK24 BK16 BJ16 BJ24 TP_CPU_RSVD_TP_BK24 TP_CPU_RSVD_TP_BK16 TP_CPU_RSVD_TP_BJ16 TP_CPU_RSVD_TP_BJ24 CFG_RCOMP BT25 CPU_CFG_RCOMP CFG16 CFG18 CFG17 CFG19 BP23 BN22 BN23 BP22 CPU_CFG<16> CPU_CFG<18> CPU_CFG<17> CPU_CFG<19> RSVD RSVD RSVD RSVD AU13 AY13 J24 J3 RSVD RSVD RSVD RSVD BR17 BN33 BP16 BR16 RSVD RSVD RSVD BP17 BR35 BR31 RSVD RSVD BN35 BT17 RSVD C30 RSVD_TP RSVD_TP BT2 BR1 (IPU) TP_CPU_RSVD_R14 TP_CPU_RSVD_N29 TP_CPU_RSVD_AE29 TP_CPU_RSVD_AA14 VSS VSS VSS VCC R14 N29 AE29 AA14 RSVD RSVD RSVD RSVD BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19 CFG0 (IPU) CFG1 (IPU) CFG2 (IPU) CFG3 (IPU) CFG4 (IPU) CFG5 (IPU) CFG6 (IPU) CFG7 (IPU) CFG8 (IPU) CFG9 (IPU) CFG10 (IPU) CFG11 (IPU) CFG12 (IPU) CFG13 (IPU) CFG14 (IPU) CFG15 (IPU) (IPU) These can be placed close to J1800 and only for debug access NOSTUFF RSVD_TP RSVD_TP RSVD_TP RSVD_TP SYM 12 OF 13 RESERVED 6 B CFG CFG CFG CFG CFG BJ34 BJ33 TP_CPU_RSVD_TP_D1 P2MM BGA TP_CPU_RSVD_TP_BJ34 TP_CPU_RSVD_TP_BJ33 EDP:YES R0644 1K 1 5% 1/20W MF 201 2 CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4> CPU_CFG<2> NOSTUFF 1 6 18 18 CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> 6 18 W3 W2 VSS VSS V6 W1 18 B NC NC NC NC NC NC NC NC NC NC NC NC NC NC TP_CPU_RSVD_TP_BT2 CPU_DC_BR1_BR2 1 TP TP0610 SYNC_MASTER=J80_MLB 6 18 NC NC NC 6 18 6 18 G3 G13 BT16 RSVD RSVD RSVD RSVD RSVD RSVD H24 E30 F30 PAGE TITLE NC NC NC 5% 1/20W MF 2 201 7 CPU Clock/Misc/JTAG/CFG Apple Inc. R0642 1K SYNC_DATE=11/06/2015 DRAWING NUMBER 051-00647 REVISION R TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS CPUPEG:X8X8 CPUCFG5_PD TABLE_BOMGROUP_ITEM CPUCFG6_PD,CPUCFG5_PD 6 5 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 TABLE_BOMGROUP_ITEM To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs. WWW.AliSaler.Com 1% 1/16W MF-LF 2 402 6 18 CPUPEG:X8X4X4 8 R0690 49.9 18 TP-P5 VSS VSS 1 18 1 6 OF 145 6 OF 121 SIZE D A 7 6 5 4 3 OMIT_TABLE 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 113 C B 112 112 BI BI 113 112 113 112 BI 113 112 BI 113 112 BI 113 112 BI BI 113 112 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI BI BI BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 113 112 BI 113 112 BI BI BI BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 113 112 112 MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63> BI BI BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BT11 BR11 BT8 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 DDR0_DQ0 DDR0_DQ1 DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQ16 DDR0_DQ17 DDR0_DQ18 DDR0_DQ19 DDR0_DQ20 DDR0_DQ21 DDR0_DQ22 DDR0_DQ23 DDR0_DQ24 DDR0_DQ25 DDR0_DQ26 DDR0_DQ27 DDR0_DQ28 DDR0_DQ29 DDR0_DQ30 DDR0_DQ31 DDR0_DQ32 DDR0_DQ33 DDR0_DQ34 DDR0_DQ35 DDR0_DQ36 DDR0_DQ37 DDR0_DQ38 DDR0_DQ39 DDR0_DQ40 DDR0_DQ41 DDR0_DQ42 DDR0_DQ43 DDR0_DQ44 DDR0_DQ45 DDR0_DQ46 DDR0_DQ47 DDR0_DQ48 DDR0_DQ49 DDR0_DQ50 DDR0_DQ51 DDR0_DQ52 DDR0_DQ53 DDR0_DQ54 DDR0_DQ55 DDR0_DQ56 DDR0_DQ57 DDR0_DQ58 DDR0_DQ59 DDR0_DQ60 DDR0_DQ61 DDR0_DQ62 DDR0_DQ63 U0500 SKYLAKE-4+4E NOSTUFF 1 1 0 2 5% 1/20W MF 201 R0701 21 OUT 0 5% 1/20W MF 201 R0703 DDR0_PAR 2 MEM_A_ALERT CPU_DIMM_VREFCA DDR0_PAR AU5 DDR0_ALERT* BN13 DDR_VREF_CA RSVD BJ23 DDR0_CKN0 DDR0_CKP0 DDR0_CKE0 AG2 AG1 AT1 DDR0_CKN1 DDR0_CKP1 DDR0_CKE1 AK1 AK2 AT2 DDR0_CLKN2 DDR0_CLKP2 DDR0_CKE2 AK3 AL3 AT3 DDR0_CLKN3 DDR0_CLKP3 DDR0_CKE3 AL1 AL2 AT5 DDR0_CS0* DDR0_CS1* DDR0_CS2* DDR0_CS3* AD5 AE2 AD2 AE5 DDR0_ODT0 DDR0_ODT1 DDR0_ODT2 DDR0_ODT3 VSS DDR0_MA3 DDR0_MA4 DDR0_ECC0 DDR0_ECC1 DDR0_ECC2 DDR0_ECC3 DDR0_ECC4 DDR0_ECC5 DDR0_ECC6 DDR0_ECC7 DDR0_DQSN0 DDR0_DQSN1 DDR0_DQSN2 DDR0_DQSN3 DDR0_DQSN4 DDR0_DQSN5 DDR0_DQSN6 DDR0_DQSN7 DDR0_DQSN8 DDR0_DQSP0 DDR0_DQSP1 DDR0_DQSP2 DDR0_DQSP3 DDR0_DQSP4 DDR0_DQSP5 DDR0_DQSP6 DDR0_DQSP7 DDR0_DQSP8 AD3 AE4 AE1 AD4 MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0> MEM_A_CLK_N<1> MEM_A_CLK_P<1> MEM_A_CKE<1> NC NC NC NC MEM_A_CKE<2> MEM_A_CKE<3> MEM_A_CS_L<0> MEM_A_CS_L<1> OUT OUT OUT BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 BR5 BL3 BP9 BL9 BG3 BD3 BG9 BC9 BA3 BP5 BK3 BR9 BJ9 BF3 BC3 BF9 BB9 AY3 113 112 BI 113 112 BI 113 112 BI OUT 23 26 113 113 112 BI OUT 23 26 113 113 112 BI OUT 22 26 113 112 BI 113 112 BI 113 112 BI OUT OUT 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 23 26 23 26 OUT 22 23 26 113 112 BI OUT 22 23 26 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI OUT 22 23 26 NC NC NC NC NC NC NC NC NC NC BI 112 BI 112 113 113 BI 112 113 BI 112 113 BI 112 BI 112 113 BI 112 113 BI 112 113 112 BI 113 112 BI 113 112 BI 113 113 112 BI 113 112 BI 113 NC MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> BI 22 26 NC NC NC MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7> 112 22 26 113 NC NC MEM_A_ODT<0> 113 22 26 113 U38 AP5 AP2 21 OUT CPU_DIMMA_VREFDQ BP13 DDR0_VREF_DQ 21 OUT CPU_DIMMB_VREFDQ BR13 DDR1_VREF_DQ BJ26 RSVD AP1 AT4 AP3 AN3 AN1 AU1 AU4 AN2 AU3 AU2 DDR0_CAA0 DDR0_CAA1 DDR0_CAA2 DDR0_CAA3 DDR0_CAA4 DDR0_CAA5 DDR0_CAA6 DDR0_CAA7 DDR0_CAA8 DDR0_CAA9 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT 113 26 22 OUT MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9> RSVD RSVD RSVD RSVD_TP RSVD_TP RSVD DDR0_CAB0 DDR0_CAB1 DDR0_CAB2 DDR0_CAB3 DDR0_CAB4 DDR0_CAB5 DDR0_CAB6 DDR0_CAB7 DDR0_CAB8 DDR0_CAB9 AJ8 B30 BH30 BJ13 BJ14 BJ21 AE3 AD1 AG4 AH4 AH5 AN4 AH1 AH2 AP4 AH3 2 1 OMIT_TABLE NC BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 113 112 BI 113 112 BI 113 112 BI 113 112 BI 113 112 BI MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> 1 0 NC 1 NC A AG3 SYMBGA 3 OF 13 MEMORY CHANNEL DDR0 D 113 R0702 2 5% 1/20W MF 201 0 R0704 2 5% 1/20W MF 201 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 W8 W7 V10 V11 W11 W10 V7 V8 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 DDR1_PAR MEM_B_ALERT AJ7 AR8 DDR1_DQ0 DDR1_DQ1 DDR1_DQ2 DDR1_DQ3 DDR1_DQ4 DDR1_DQ5 DDR1_DQ6 DDR1_DQ7 DDR1_DQ8 DDR1_DQ9 DDR1_DQ10 DDR1_DQ11 DDR1_DQ12 DDR1_DQ13 DDR1_DQ14 DDR1_DQ15 DDR1_DQ16 DDR1_DQ17 DDR1_DQ18 DDR1_DQ19 DDR1_DQ20 DDR1_DQ21 DDR1_DQ22 DDR1_DQ23 DDR1_DQ24 DDR1_DQ25 DDR1_DQ26 DDR1_DQ27 DDR1_DQ28 DDR1_DQ29 DDR1_DQ30 DDR1_DQ31 DDR1_DQ32 DDR1_DQ33 DDR1_DQ34 DDR1_DQ35 DDR1_DQ36 DDR1_DQ37 DDR1_DQ38 DDR1_DQ39 DDR1_DQ40 DDR1_DQ41 DDR1_DQ42 DDR1_DQ43 DDR1_DQ44 DDR1_DQ45 DDR1_DQ46 DDR1_DQ47 DDR1_DQ48 DDR1_DQ49 DDR1_DQ50 DDR1_DQ51 DDR1_DQ52 DDR1_DQ53 DDR1_DQ54 DDR1_DQ55 DDR1_DQ56 DDR1_DQ57 DDR1_DQ58 DDR1_DQ59 DDR1_DQ60 DDR1_DQ61 DDR1_DQ62 DDR1_DQ63 DDR1_PAR DDR1_ALERT* NC NC NC NC NC NC MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9> OUT 23 26 113 OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT OUT 23 26 113 113 26 24 OUT 113 26 24 OUT MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9> AM6 AR11 AN7 AN8 AN10 AR9 AR10 AN11 AT9 AR7 DDR1_CAA0 DDR1_CAA1 DDR1_CAA2 DDR1_CAA3 DDR1_CAA4 DDR1_CAA5 DDR1_CAA6 DDR1_CAA7 DDR1_CAA8 DDR1_CAA9 U0500 SKYLAKE-4+4E SYMBGA 4 OF 13 MEMORY CHANNEL DDR1 8 RSVD BJ27 DDR1_CKN0 DDR1_CKP0 DDR1_CKE0 AN9 AM9 AT8 MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0> DDR1_CKN1 DDR1_CKP1 DDR1_CKE1 AM8 AM7 AT10 MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<1> DDR1_CLKN2 DDR1_CLKP2 DDR1_CKE2 AM10 AM11 AT7 NC NC DDR1_CLKN3 DDR1_CLKP3 DDR1_CKE3 AJ11 AJ10 AT11 NC NC DDR1_CS0* DDR1_CS1* DDR1_CS2* DDR1_CS3* AF11 AE7 AF10 AE10 DDR1_ODT0 DDR1_ODT1 DDR1_ODT2 DDR1_ODT3 AF7 AE8 AE9 AE11 VSS NC OUT 24 26 113 OUT 24 26 113 OUT 24 26 OUT 25 26 113 OUT 25 26 113 OUT 24 26 MEM_B_CKE<2> OUT 25 26 MEM_B_CKE<3> OUT 25 26 OUT 24 25 26 OUT 24 25 26 OUT 24 25 26 MEM_B_CS_L<0> MEM_B_CS_L<1> D NC NC MEM_B_ODT<0> NC NC NC Y38 C DDR1_MA3 DDR1_MA4 DDR1_ECC0 DDR1_ECC1 DDR1_ECC2 DDR1_ECC3 DDR1_ECC4 DDR1_ECC5 DDR1_ECC6 DDR1_ECC7 AL5 AL6 NC NC AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 DDR1_DQSN0 DDR1_DQSN1 DDR1_DQSN2 DDR1_DQSN3 DDR1_DQSN4 DDR1_DQSN5 DDR1_DQSN6 DDR1_DQSN7 DDR1_DQSN8 AA3 U3 AC9 W9 P3 L3 R9 M9 AY9 DDR1_DQSP0 DDR1_DQSP1 DDR1_DQSP2 DDR1_DQSP3 DDR1_DQSP4 DDR1_DQSP5 DDR1_DQSP6 DDR1_DQSP7 DDR1_DQSP8 AB3 V3 AA9 V9 R3 M3 P9 L9 AW9 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD BK28 BK26 BK27 BK23 BK21 BJ35 BJ28 BJ36 DDR1_CAB0 DDR1_CAB1 DDR1_CAB2 DDR1_CAB3 DDR1_CAB4 DDR1_CAB5 DDR1_CAB6 DDR1_CAB7 DDR1_CAB8 DDR1_CAB9 AF9 AF8 AH11 AH10 AH8 AK5 AH9 AH7 AK6 AJ9 NC NC NC NC NC NC NC NC MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7> BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 BI 112 113 NC MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7> B NC NC NC NC NC NC NC NC NC MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9> OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 OUT 25 26 113 SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 CPU DDR3 Interfaces DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=CPU & CHIPSET II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 7 OF 145 7 OF 121 SIZE D A 8 7 6 5 4 PPVCC_S0_CPU PPVCCGT_S0_CPU PPVCCSA_S0_CPU 3 6 8 55 109 OMIT_TABLE 8 55 109 8 53 109 NC NC NC NC PLACE_NEAR=U0500.AG37:50.8mm PLACE_NEAR=U0500.AH38:50.8mm PLACE_NEAR=U0500.M38:50.4mm 1 1 R0864 100 1 R0865 100 5% 1/20W MF 2 201 R0866 109 D 8 65 8 65 8 65 5 8 109 PPVCCIO_S0_CPU 5 8 109 OMIT_TABLE 110 18 11 6 AH36 NC AH35 NC VCCGTX_SENSE VSSGTX_SENSE BJ17 NC BJ19 NC BJ20 NC BK17 NC BK19 NC BK20 NC BL16 NC BL17 NC BL18 NC BL19 NC BL20 NC BL21 NC BM17 NC BN17 NC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC BL15 NC BM16 NC VCCOPC_SENSE VSSOPC_SENSE PP1V0_S3 CPU_VCCST_PWRGD_R 11 8 6 8 110 VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX H30 H13 PP1V0_S0SW B G30 H29 U0500 SKYLAKE-4+4E BGA SYM 6 OF 13 POWER VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSTG VCCSTG VCCEOPIO VCCEOPIO VCCEOPIO BN15 NC BM15 NC VCCEOPIO_SENSE VSSEOPIO_SENSE AG12 G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27 PLACE_NEAR=U0500.H14:50.8mm 1 5% 1/20W MF 2 201 CPU_VCCIOSENSE_P 109 110 11 8 6 PP1V0_S3 PP1V2_S3_CPUDDR 8 PLACE_NEAR=U0500.Y12:5mm 1 R0841 CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N OUT 8 71 OUT 9 71 PPVCCSA_S0_CPU 70 IN CPU_VCCST_PWRGD 1 60.4 CPU_VCCST_PWRGD_R 109 110 11 8 6 55 8 6 PPVCC_S0_CPU PP1V0_S3 1 65 8 OUT 65 9 OUT CPU_VCCSENSE_P CPU_VCCSENSE_N R0800 56.2 1 R0810 100 5% 1/20W MF 2 201 65 NC NC NC NC 1% 1/20W MF 2 201 R0802 220 1 CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R 2 5% 1/20W MF 201 TP_CPU_RSVD_TP75 TP_CPU_RSVD_TP76 R0811 65 CPU_VCCSASENSE_P CPU_VCCSASENSE_N VCCSA_SENSE M38 VSSSA_SENSE M37 PP1V0_S3 VCCPLL H28 VCCPLL J28 OUT 8 65 OUT 9 65 OUT CPU_VIDSCLK 1 0 TP_CPU_RSVD_TP78 R0812 11 110 PP1V2_S0SW BI CPU_VIDSOUT 1 0 2 5% 1/16W MF-LF 402 1 C0802 1UF 20% 2 6.3V X6S-CERM 0201 1 C0803 1UF 20% 2 6.3V X6S-CERM 0201 109 55 8 6 PPVCC_S0_CPU Place on bottom side of U0500 OUT 65 8 OUT CPU_VCCGTSENSE_N CPU_VCCGTSENSE_P SYM 7 OF 13 POWER BGA SKYLAKE-4+4E U0500 VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE33 BE34 BE35 BE36 BE37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ37 BJ38 BL36 BL37 BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37 BT37 8 55 109 65 9 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AL13 AL29 AL30 AL31 AL32 AL35 AL36 AL37 AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT OMIT_TABLE A RSVD RSVD RSVD RSVD U36 V13 VCC VCC AG37 AG38 VCC_SENSE VSS_SENSE BL26 BN16 BL28 BL27 RSVD RSVD RSVD RSVD BH31 BH32 BH29 VIDALERT* VIDSCK VIDSOUT Y7 VSS Y8 E2 E1 VSS RSVD_TP RSVD_TP E3 Y9 Y13 W4 W34 Y10 W5 Y14 W12 Y37 W33 Y11 RSVD_TP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 5% 1/16W MF-LF 402 65 109 BL25 BL22 BL24 BL23 CPU_VIDALERT_L IN VDDQC C0801 NC NC NC NC 8 1% 1/20W MF 201 8 53 109 1 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 20% 2 10V X5R-CERM 0402-7 1% 1/16W MF-LF 2 402 2 Y12 RSVD RSVD RSVD RSVD 10UF R0840 1K VCC_OPC_1P8 BL14NC VCC_OPC_1P8 BM14NC PPVCCGT_S0_CPU 8 71 PULL-UPS FOR SENSE LINES J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34 M35 M36 VCCPLL_OC BH13 VCCPLL_OC G11 R0861 100 VCCIO_SENSE H14 VSSIO_SENSE J14 VCCST VCCST_PWRGD BP15 NC BR15 NC BT15 NC VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCGT_SENSE AH38 VSSGT_SENSE AH37 C AF29 NC AF30 NC AF31 NC AF32 NC AF33 NC AF34 NC AG13 NC AG14 NC AG31 NC AG32 NC AG33 NC AG34 NC AG35 NC AG36 NC AH13 NC AH14 NC AH29 NC AH30 NC AH31 NC AH32 NC AJ13 NC AJ14 NC BL31 BL34 BM22 BM24 AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6 5% 1/20W MF 2 201 CPU_VCCSASENSE_P CPU_VCCGTSENSE_P CPU_VCCSENSE_P PPVCCIO_S0_CPU PP1V2_S3_CPUDDR 8 100 5% 1/20W MF 2 201 2 AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AB30 AB31 AA38 AB29 V14 V31 V32 V33 V34 V35 V36 V37 V38 W13 W14 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U0500 SKYLAKE-4+4E BGA SYM 5 OF 13 1 PPVCC_S0_CPU VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38 K13 K14 L13 L14 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y36 6 8 55 109 D C B SYNC_MASTER=J80_MLB SYNC_DATE=08/16/2015 PAGE TITLE CPU Power DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 8 OF 145 8 OF 121 SIZE D A 8 7 6 5 4 3 2 1 OMIT_TABLE OMIT_TABLE AU34 AU33 AU12 AU11 AU10 AU9 AU8 AU7 AU6 AT30 AT29 AT6 AR38 AR37 AR5 AR14 AR13 AR4 AR1 AP34 AP33 AP12 AR3 AR2 AP9 AP11 AP8 AP10 AN12 AN6 AN5 AN30 AN29 AM38 AM37 AM12 AM5 AM2 AM4 AM1 AM3 AL34 AL33 AL14 AL8 AL12 AL7 AL4 AK30 AK29 AL10 AL9 AK4 AJ38 AJ37 AJ6 AJ3 AJ5 AJ2 AJ4 D C B U0500 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SKYLAKE-4+4E BGA SYM 8 OF 13 GROUND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AJ1 AH34 AH33 AG29 AH12 AG11 AH6 AG30 AG10 AG8 AF14 AG7 AG6 AF13 AF4 AF3 AF2 AF1 AF12 AE34 AE33 AE6 AD30 AD11 AD29 AD10 AD12 AD8 AD7 AD9 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AD6 AB6 AC38 AC37 AC12 AA30 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6 AA29 AW2 AW29 AW3 AW30 AW4 AW5 AY12 AV37 AY14 AY33 AY34 B9 BA10 AV38 AW1 AW12 BA37 BA38 BA6 BA7 BA8 BA9 BB1 BB12 BA11 BA12 BB2 BB6 BC12 BB29 BC13 BC14 BC33 BB3 BC34 BB30 BC6 BB4 BD10 BB5 BD37 BD38 BD6 BD7 BD8 BD9 BE1 BE2 BE29 BD11 BE3 BE30 BE4 BD12 BE6 BF12 BF33 BF34 BF6 BG12 BG13 BN2 BN19 BN20 BN21 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U0500 SKYLAKE-4+4E BGA SYM 9 OF 13 GROUND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BG14 BE5 BG38 BG6 BH1 BH10 BH11 BH12 BH14 BH2 BH3 BH4 BH5 BG37 BH9 BJ12 BJ15 BJ18 BJ22 BJ25 BJ29 BH6 BJ30 BH7 BJ31 BJ32 BK13 BK14 BH8 BK29 BK6 BL13 BL29 BL35 BL38 BL6 BM11 BM12 BM13 BM18 BM2 BM21 BM23 BM25 BM26 BM27 BM28 BM29 BM3 BM5 BM6 BM7 BM8 BM9 BK15 BK18 BK22 BK25 U6 BN24 G8 G9 H11 H12 H18 D CPU_VCCGTSENSE_N OUT 8 65 CPU_VCCIOSENSE_N OUT 8 71 OUT 8 65 OUT 8 65 CPU_VCCSASENSE_N CPU_VCCSENSE_N C 1 100 5% 1/20W MF 2 201 100 R0965 100 5% 1/20W MF 2 201 5% 1/20W MF 2 201 1 R0966 100 5% 1/20W MF 2 201 A36 A37 BM38 BM35 N34 G6 A34 A4 A3 B3 B37 BR38 BT3 BT35 BT36 BT4 C2 D38 VSS VSS VSS VSS VSS VSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS 1 TP 1 TP TP0900 TP0901 TP-P5 TP-P5 SYM 10 OF 13 BGA H22 H25 H32 H35 J10 J18 J22 G23 G24 G26 J32 J33 J25 J4 J7 K1 K10 J36 K11 K2 K3 K38 K4 K5 K7 L29 K8 K9 L33 L34 M12 M13 L30 M6 M14 N1 N10 N11 N12 N4 N2 N5 N6 N7 N3 N33 N9 N8 P12 P37 P38 P6 R12 T10 R29 T11 T12 T13 R30 T1 T3 T14 T2 T34 T4 T5 T7 T33 U37 T8 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SKYLAKE-4+4E 1 R0963 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U0500 1 B CPU_DC_BR38_BT36 CPU_DC_BT36_BR38 OMIT_TABLE R0961 SYNC_MASTER=J80_MLB BN29 BN12 BN30 BN31 BN34 BN4 BN7 BN9 BP12 BP14 BN14 BP18 BP21 BN18 BP26 BP29 BP33 BP34 BP7 BR12 BP24 BR14 BR18 BR21 BR24 BR26 BR29 BR36 BR7 BT12 BT14 BT18 BT21 BT24 BT26 BT32 BT5 BT9 C11 C13 C15 BR34 C21 C23 C25 C27 C29 C31 C37 C5 C17 C8 C9 D10 D12 C19 D16 D18 D20 D22 D24 D26 D28 D3 D30 D33 D6 D14 E34 E35 E38 E4 E9 F11 F13 F15 F17 F19 F2 F21 F23 F25 F27 F29 F3 F31 F36 D9 F4 G10 F5 G12 G14 G16 F8 G18 G20 G22 F9 G28 G4 G5 A SYNC_DATE=08/17/2015 PAGE TITLE CPU Ground DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 9 OF 145 9 OF 121 SIZE D A 8 7 6 5 4 2 1 Vcc CPU Core Decoupling from 20140905 BOM CPU VCORE Decoupling Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Apple Implementation: 109 3 Board Edge: 2x 220uF, 4x 47uF rest on the back side PPVCC_S0_CPU Place on bottom side of U0500 1 C1000 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 D C1001 C1002 1 1UF 20% 2 4V CERM-X6S 0201 C1003 20% 2 4V CERM-X6S 0201 C1004 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1005 1 1UF 20% 2 4V CERM-X6S 0201 C1006 20% 2 4V CERM-X6S 0201 C1007 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1008 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 1 C1009 1 1UF C1010 1 1UF 20% 2 4V CERM-X6S 0201 C1011 1 1UF 20% 2 4V CERM-X6S 0201 C1012 1 1UF 20% 2 4V CERM-X6S 0201 C1013 1 1UF 20% 2 4V CERM-X6S 0201 C1014 1 1UF 20% 2 4V CERM-X6S 0201 C1015 1 1UF 20% 2 4V CERM-X6S 0201 C1016 1 1UF 20% 2 4V CERM-X6S 0201 C1017 1 1UF 20% 2 4V CERM-X6S 0201 C1018 1 1UF 20% 2 4V CERM-X6S 0201 C1019 20% 2 4V CERM-X6S 0201 C1020 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1021 1 1UF 20% 2 4V CERM-X6S 0201 C1022 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 D Place on bottom side of U0500 1 C1023 1 1UF C1024 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 C1025 C1026 1UF 20% 2 4V CERM-X6S 0201 C1027 1 1 1UF 20% 2 4V CERM-X6S 0201 C1028 1 1UF 20% 2 4V CERM-X6S 0201 C1029 1UF 20% 2 4V CERM-X6S 0201 C1030 1 1 1UF 20% 2 4V CERM-X6S 0201 C1031 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 1 C1032 1 1UF C1033 1 1UF 20% 2 4V CERM-X6S 0201 C1034 1 1UF 20% 2 4V CERM-X6S 0201 C1035 1 1UF 20% 2 4V CERM-X6S 0201 C1036 1 1UF 20% 2 4V CERM-X6S 0201 C1037 1 1UF 20% 2 4V CERM-X6S 0201 C1038 1 1UF 20% 2 4V CERM-X6S 0201 C1039 1 1UF 20% 2 4V CERM-X6S 0201 C1040 1 1UF 20% 2 4V CERM-X6S 0201 C1041 1 1UF C1043 1 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 C1042 1 1UF 20% 2 4V CERM-X6S 0201 C1044 1 1UF 20% 2 4V CERM-X6S 0201 C1045 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 Place on bottom side of U0500 1 C1046 1 1UF C1047 1UF NOSTUFF C1048 1 20UF C10A1 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C1049 C1050 1 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C10A0 1 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 1 1 1 1UF 20% 2 4V CERM-X6S 0201 C1051 1 1UF 20% 2 4V CERM-X6S 0201 C1052 1UF 20% 2 4V CERM-X6S 0201 20UF 20% 2 2.5V X6S-CERM 0402-1 1 20% 2 4V CERM-X6S 0201 C10A4 1 20UF 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2.5V 2 X6S-CERM 0402-1 1 C10A5 1 20UF C10A6 1 20UF 20% 2 2.5V X6S-CERM 0402-1 C10A7 1 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 4V CERM-X6S 0201 NOSTUFF C10A8 1 20UF 1 C1055 1 1UF C10A9 1 C10B0 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 C1056 1 1UF 20% 2 4V CERM-X6S 0201 C1057 1 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 20UF 20% 2.5V 2 X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 C1054 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C10A3 1 1UF NOSTUFF C10A2 C1053 1 C1058 1 1UF 20% 2 4V CERM-X6S 0201 C1059 1UF 20% 2 4V CERM-X6S 0201 C10B1 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10B2 20UF 20% 2 2.5V X6S-CERM 0402-1 C1060 C10B3 1 20UF C10B4 1 20UF 1 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 C10B5 C10B6 1 C1062 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C10B7 1 20UF 20% 2.5V 2 X6S-CERM 0402-1 1 20% 2 4V CERM-X6S 0201 NOSTUFF 20UF 20% 2 2.5V X6S-CERM 0402-1 C1061 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 1 1 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 1 1 NOSTUFF C10B8 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF C10B9 1 20UF C10C0 1 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C10C1 20UF 1 NOSTUFF C10C3 1 20UF C10C4 1 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF C10C5 20UF 20% 2.5V 2 X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C10C6 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10C7 20UF 20% 2 2.5V X6S-CERM 0402-1 C C NOSTUFF 1 C10D0 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10D1 20UF 20% 2 2.5V X6S-CERM 0402-1 C10D2 1 1 20UF C10D3 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C10D4 20UF 20% 2 2.5V X6S-CERM 0402-1 1 NOSTUFF C10D5 1 20UF C10D6 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C10D7 1 20UF C10E0 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 NOSTUFF C10E1 1 20UF C10E2 1 20UF 20% 2 2.5V X6S-CERM 0402-1 Noise Floor caps NOSTUFF C10E3 1 20UF 20% 2 2.5V X6S-CERM 0402-1 C10N1 1 12PF 20% 2 2.5V X6S-CERM 0402-1 C10N2 12PF 5% 25V 2 NP0-C0G 0201 5% 2 25V NP0-C0G 0201 1 C10N3 12PF 5% 2 25V NP0-C0G 0201 1 C10N4 12PF 1 C10N5 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 1 C10N6 12PF 1 C10N7 12PF 5% 2 25V NP0-C0G 0201 5% 25V 2 NP0-C0G 0201 Place near inductors on bottom side. NOSTUFF 1 C10Z1 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1068 1 220UF 3 C1069 1 220UF 20% 2 2V ELEC SM-COMBO 3 C1070 1 220UF 20% 2 2V ELEC SM-COMBO 3 20% 2 2V ELEC SM-COMBO C1071 1 220UF 3 C1072 1 220UF 20% 2 2V ELEC SM-COMBO 3 NOSTUFF 1 C10Z2 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10Z3 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10Z4 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10Z5 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C10Z6 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C10Z7 20UF 20% 2.5V 2 X6S-CERM 0402-1 NOSTUFF 1 NOSTUFF C10Z8 1 20UF NOSTUFF C10Z9 1 20UF 20% 2 2.5V X6S-CERM 0402-1 C10ZA 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C10ZB 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C10ZC 20UF 20% 2 2.5V X6S-CERM 0402-1 C1073 220UF 20% 2 2V ELEC SM-COMBO 3 20% 2 2V ELEC SM-COMBO B B 116 109 PP1V2_S3_CPUDDR Place on bottom side of U0500 U0500. 1 C1080 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1081 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1082 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1083 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1084 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1085 20UF 20% 2 2.5V X6S-CERM 0402-1 CPU VDDQ Decoupling Intel recommendation: 10x 10uF 0402, 4x 22uF 0602 Apple Implementation: Place on bottom side of U0500 1 C1090 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1091 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1092 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1093 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1094 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1095 20UF 20% 2 2.5V X6S-CERM 0402-1 CPU VCCIO Decoupling Intel recommendation: 3x 10uF 0402 (opposite CPU) Apple Implementation: A 109 PPVCCIO_S0_CPU Place near U0500 Placeon near bottom U0500 Place side on near bottom U0500side on bottom side SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN PAGE TITLE 1 C1086 20UF 20% 2.5V 2 X6S-CERM 0402-1 1 C1087 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1088 20UF 20% 2.5V 2 X6S-CERM 0402-1 1 C1089 20UF 20% 2.5V 2 X6S-CERM 0402-1 1 C108A 20UF SYNC_DATE=11/22/2015 CPU Decoupling 1 [10] DRAWING NUMBER 20% 2.5V 2 X6S-CERM 0402-1 Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884) WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 10 OF 145 10 OF 121 SIZE D A 8 7 6 5 4 Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201 Apple Implementation: 109 1 Board Edge: 4x220uF, 7x 47uF rest on back side PPVCCGT_S0_CPU Place on bottom side of U0500 1 C1100 1 1UF C1101 C1102 1 1UF 20% 2 4V CERM-X6S 0201 D 2 Vcc GT Slice Core Decoupling from 20140905 BOM CPU VGTSlice Decoupling 116 3 1 1UF 20% 2 4V CERM-X6S 0201 C1103 1 1UF 20% 2 4V CERM-X6S 0201 C1104 1 1UF 20% 2 4V CERM-X6S 0201 C1105 1 1UF 20% 2 4V CERM-X6S 0201 C1106 20% 2 4V CERM-X6S 0201 C1107 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1108 1 1UF 20% 2 4V CERM-X6S 0201 C1109 1 1UF 20% 2 4V CERM-X6S 0201 C1110 20% 2 4V CERM-X6S 0201 C1111 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1112 1 1UF 20% 2 4V CERM-X6S 0201 C1113 1 1UF 20% 2 4V CERM-X6S 0201 C1114 1 1UF 20% 2 4V CERM-X6S 0201 C1115 1 1UF 20% 2 4V CERM-X6S 0201 C1116 1 1UF 20% 2 4V CERM-X6S 0201 C1117 1 1UF 20% 2 4V CERM-X6S 0201 C1118 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 1 C1119 C1120 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1121 20% 2 4V CERM-X6S 0201 C1122 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C1123 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 D Place on bottom side of U0500 1 C1124 1 1UF C1125 1UF 1 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 C1126 1 C1127 1 1UF 20% 2 4V CERM-X6S 0201 C1128 1 1UF 20% 2 4V CERM-X6S 0201 C1129 1 1UF C1131 1 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 C1130 1 1UF 20% 2 4V CERM-X6S 0201 C1132 1 1UF 20% 2 4V CERM-X6S 0201 C1133 1 1UF 20% 2 4V CERM-X6S 0201 C1134 1UF 20% 2 4V CERM-X6S 0201 C1135 1 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 C1136 C1137 1 1UF 20% 2 4V CERM-X6S 0201 C1138 1 1UF 20% 2 4V CERM-X6S 0201 C1139 1 1UF 20% 2 4V CERM-X6S 0201 C1140 1 1UF 20% 2 4V CERM-X6S 0201 C1141 1 1UF 20% 2 4V CERM-X6S 0201 C1142 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 1 C1143 1UF 20% 2 4V CERM-X6S 0201 1 C1144 1 1UF C1145 1UF 20% 2 4V CERM-X6S 0201 C1146 1 1 1UF 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 C1147 20% 2 4V CERM-X6S 0201 Place on bottom side of U0500 1 C1148 1 1UF C11A0 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF C11A1 1 20UF C11A2 20% 2 2.5V X6S-CERM 0402-1 1 1 1 20UF C11A4 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C1154 20% 4V 2 CERM-X6S 0201 20% 2 2.5V X6S-CERM 0402-1 C11A6 1 20% 2 4V CERM-X6S 0201 20UF 20% 2 2.5V X6S-CERM 0402-1 C11A7 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 1 1UF 20UF 20% 2 2.5V X6S-CERM 0402-1 1 1 C1157 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11B0 1 20UF C11B1 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 20% 2 2.5V X6S-CERM 0402-1 1 C11B3 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1160 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1161 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C1163 1 1UF 20% 2 4V CERM-X6S 0201 C1164 1 C11B7 20UF 20% 2 2.5V X6S-CERM 0402-1 1 1UF 20% 2 4V CERM-X6S 0201 C11B8 1 20UF C11B9 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C11C0 20UF 20% 2 2.5V X6S-CERM 0402-1 1 20% 2 2.5V X6S-CERM 0402-1 1 C11C2 20UF 20% 2 2.5V X6S-CERM 0402-1 C1166 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C11C1 20UF 1 20% 2 4V CERM-X6S 0201 NOSTUFF 1 C1165 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C11B6 1 C1162 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C11B5 1 1UF 20% 4V 2 CERM-X6S 0201 NOSTUFF C11B4 1 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C11B2 1 1UF 20% 2 4V CERM-X6S 0201 20UF NOSTUFF C1159 1 NOSTUFF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF C1158 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C11A9 1 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C11A8 C1156 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 1 C1155 1 1UF NOSTUFF C11A5 1 C1153 1UF NOSTUFF 20UF 20% 2 2.5V X6S-CERM 0402-1 1 20% 2 4V CERM-X6S 0201 NOSTUFF C11A3 C1152 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 20UF 20% 2 2.5V X6S-CERM 0402-1 C1151 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 1 1 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF C1150 1 1UF 20% 2 4V CERM-X6S 0201 1 C1149 1 C1167 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 1 NOSTUFF C11C3 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11C4 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11C5 1 20UF NOSTUFF C11C6 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C11C7 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11C8 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11C9 20UF 20% 2 2.5V X6S-CERM 0402-1 C11F0 20UF C 20% 2 2.5V X6S-CERM 0402-1 1 1 C11F1 20UF 20% 2 2.5V X6S-CERM 0402-1 C1168 1 220UF 3 20% 2 2V ELEC SM-COMBO 1 C11F2 1 20UF 20UF 20% 2.5V 2 X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 C1169 1 220UF 3 C11F3 1 C11F4 20UF 20% 2 2.5V X6S-CERM 0402-1 C1170 1 220UF 20% 2 2V ELEC SM-COMBO 3 1 C11F5 1 20UF 20% 2 2.5V X6S-CERM 0402-1 1 3 C11F7 1 20UF 20% 2 2.5V X6S-CERM 0402-1 C1171 20% 2 2V ELEC SM-COMBO 1 20UF 220UF 20% 2 2V ELEC SM-COMBO C11F6 C11E0 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C11E1 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11D0 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF NOSTUFF 1 1 C11E2 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11E3 1 20UF C11E4 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 1 C11E5 1 20UF C11D4 1 20UF 20% 2 2.5V X6S-CERM 0402-1 C11D3 20UF 20% 2 2.5V X6S-CERM 0402-1 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 NOSTUFF C11D2 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11D1 20UF 20% 2 2.5V X6S-CERM 0402-1 C C1172 220UF 3 20% 2 2V ELEC SM-COMBO B B CPU VCCSTG Decoupling 110 18 8 6 CPU VCCPLL and VCCST PP1V0_S0SW 110 109 PP1V0_S3 110 8 6 PP1V0_S3 Place near U0500 on bottom side PPVCCSA_S0_CPU Place on bottom side of U0500 U100. 1 C11H0 1 1UF C11J0 47UF 20% 2 6.3V POLY-TANT 0805 1 NOSTUFF C11H2 1UF 20% 2 4V CERM-X6S 0201 NOSTUFF 1 C11H1 1UF 20% 2 4V CERM-X6S 0201 A 8 Decoupling 20% 2 4V CERM-X6S 0201 1 C11I0 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C11I1 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C11I2 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11I3 20UF 20% 2 2.5V X6S-CERM 0402-1 NOSTUFF 1 C11I4 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11I5 20UF 20% 2 2.5V X6S-CERM 0402-1 1 C11I6 20UF 20% 2 2.5V X6S-CERM 0402-1 1 1 C11I7 C11L1 1UF 20UF 20% 2 4V CERM-X6S 0201 20% 2 2.5V X6S-CERM 0402-1 1 C11L2 1 1UF 1 1UF 20% 2 4V CERM-X6S 0201 C11M2 1UF 20% 2 4V CERM-X6S 0201 20% 2 4V CERM-X6S 0201 Place near U0500 on bottom side NOSTUFF 1 C11M1 C11J1 47UF SYNC_MASTER=X363_SEAN 20% 2 6.3V POLY-TANT 0805 PAGE TITLE SYNC_DATE=02/01/2016 CPU Decoupling 2 [11] CPU VCCSA Decoupling 1 Apple Inc. Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_ 2x 220uF, 1x 22uF on board edge, everything else on back side Apple Implementation: C11K9 220UF 3 DRAWING NUMBER 20% 2 2V ELEC SM-COMBO 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884) WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 11 OF 145 11 OF 121 SIZE D A 8 7 6 5 4 3 2 1 OMIT_TABLE U1100 SKL-PCH-SFF H65946 FCBGA SYM 4 OF 12 SYSTEM POWER MANAGEMENT 48 SMC_PCH_SUSACK_L IN 115 NOSTUFF R1204 46 18 12 114 115 5% 1/20W MF 0201 2 114 115 48 70 35 20 73 46 18 PM_SYSRST_L AJ4 SYS_RESET* IN PM_PCH_SYS_PWROK AK3 SYS_PWROK IN PM_PCH_PWROK AJ11 PCH_PWROK 46 29 12 70 46 20 12 PCIE_WAKE_L IN GPP_A8/CLKRUN* AK14 LPC_CLKRUN_L BI GPP_A14/SUS_STAT*/ESPI_RESET* AM15 LPC_PWRDWN_L OUT 46 GPD8/SUSCLK AH12 PM_CLK32K_SUSCLK_R OUT 47 GPD10/SLP_S5* AG10 PM_SLP_S5_L OUT 12 20 46 73 GPD5/SLP_S4* AK10 PM_SLP_S4_L OUT 12 20 43 46 70 73 GPD4/SLP_S3* AK9 PM_SLP_S3_L OUT 12 20 27 46 70 73 76 89 101 GPD6/SLP_A* AG11 NC_PCH_SLP_A_L GPP_B13/PLTRST* IN PM_RSMRST_L AF12 RSMRST* SMC_PCH_SUSWARN_L AJ16 PM_PWRBTN_L AM10 GPD3/PWRBTN* SSD_SR_EN_L AL12 GPD1/ACPRESENT AM12 GPD0/BATLOW* SLP_SUS* AH13 PM_SLP_SUS_L AK11 NC_PCH_SLP_LAN_L IN (IPU-RSMRST#) GPP_A13/SUSWARN* /SUSPWRDNACK IN PM_BATLOW_L OUT PM_SLP_S0_L AM22 GPP_B12/SLP_S0* SLP_LAN* 111 NC_PCH_SLP_WLAN_L AH10 GPD9/SLP_WLAN* GPD2/LAN_WAKE* AL9 SMC_WAKE_SCI_L 20 NC_PCH_PME_L AG16 GPP_A11/PME* GPD11/LANPHYPC AJ13 NC_PCH_LANPHYPC AUD_PWR_EN AG18 GPP_B2/VRALERT* AH20 BT_LOW_PWR_L (IPU) GPP_A12/BMBUSY*/ISH_GP6 IN 46 35 12 12 19 1 20K 5% 1/20W MF 2 201 12 RTC_RESET_L AH8 RTCRST* 12 12 70 73 OUT 20 12 46 IN 20 12 35 OUT GPP_A0/RCIN*/ESPI_ALERT1* GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME*/ESPI_CS0* GPP_A6/SERIRQ/ESPI_CS1* GPP_A7/PIRQA*/ESPI_ALERT0* AM13 AK12 AK13 AG20 AM14 AL14 AH14 AJ18 PCH_RCIN_L_PU LPC_AD_R<0> R1440 LPC_AD_R<1> R1441 LPC_AD_R<2> R1442 LPC_AD_R<3> R1443 LPC_FRAME_R_L R1444 LPC_SERIRQ SMC_RUNTIME_SCI_L GPD7/RSVD AL11 NC_PCH_GPD7 R1211 SSD_SR_EN_L 1 3.0K 1 2 5% 1/20W MF 201 1 1 1 1 1 33 33 33 33 33 2 2 2 2 2 12 46 BI 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L BI 46 89 BI 46 89 BI 46 89 110 BI 46 89 OUT 46 89 PLACE_NEAR=U1100.AL14:1.25mm 115 46 18 12 17 16 14 5% 1/20W MF 201 PP3V3_SUS R1247 PM_SYSRST_L 2 12 46 IN C 20 110 17 16 15 PP3V3_SUS U1100 10% 2 10V X5R 402-1 SKL-PCH-SFF H65946 FCBGA 27 OUT OUT 101 OUT 101 OUT 113 87 OUT 113 87 OUT CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIE_CLK100M_TBT_X_N PCIE_CLK100M_TBT_X_P F3 F4 CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P G2 G3 PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P E2 E1 CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 48 12 103 111 OUT 111 OUT 111 OUT 111 OUT 111 OUT 111 OUT 111 OUT 111 OUT 111 OUT 111 OUT R1234 XCLK_BIASREF E4 OUT 111 OUT 111 OUT 111 OUT 20 OUT 20 OUT K2 K3 L1 L2 NC_CLKOUT_PCIE_8_N NC_CLKOUT_PCIE_8_P M3 M4 NC_CLKOUT_PCIE_9_N NC_CLKOUT_PCIE_9_P M2 M1 NC_CLKOUT_PCIE_10_N NC_CLKOUT_PCIE_10_P R6 R7 GPP_A10/CLKOUT_LPC1 AH15 CLKOUT_PCIE_N10 CLKOUT_PCIE_P10 NC_CLKOUT_PCIE_12_N NC_CLKOUT_PCIE_12_P N3 N2 CLKOUT_PCIE_N12 CLKOUT_PCIE_P12 NC_CLKOUT_PCIE_13_N NC_CLKOUT_PCIE_13_P P5 P6 CLKOUT_PCIE_N13 CLKOUT_PCIE_P13 NC_CLKOUT_PCIE_14_N NC_CLKOUT_PCIE_14_P N5 N6 NC_CLKOUT_PCIE_15_N NC_CLKOUT_PCIE_15_P M6 M7 46 12 110 46 12 1% 1/20W MF 201 12 LPC_CLK24M_SMC_R R1235 22 1 PLACE_NEAR=U1100.AJ14:1.4mm LPC_CLK24M_DPMUX_UC_R 2 46 12 59 12 LPC_CLK24M_SMC 1% 111 OUT 111 OUT 111 OUT 111 OUT CLKOUT_PCIE_N14 CLKOUT_PCIE_P14 CLKOUT_PCIE_N15 CLKOUT_PCIE_P15 1 2 1 2 1 2 1 2 SMC_RUNTIME_SCI_L LPC_CLKRUN_L PCH_RCIN_L_PU R1207 R1208 R1251 100K 10K 100K 1 2 1 2 1 2 1/20W MF 12 46 BI 201 19 12 CAMERA_PWR_EN 12 73 70 46 43 20 12 NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP CLKOUT_CPUBCLK_N J3 CLKOUT_CPUBCLK_P J4 CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P OUT 6 113 OUT 6 113 CLKOUT_CPUNSSC_N H1 CLKOUT_CPUNSSC_P H2 CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P OUT 6 113 OUT 6 113 CLKOUT_CPUPCIBCLK_N J1 CLKOUT_CPUPCIBCLK_P J2 CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P OUT 6 113 OUT 6 113 OUT 18 113 115 OUT 18 113 115 19 12 73 70 12 47K AP_CLKREQ_L_R ENETSD_CLKREQ_L CAMERA_CLKREQ_L TBT_X_CLKREQ_L_R TBT_T_CLKREQ_L_R SSD_CLKREQ_L_R BI R1206 R1214 R1215 R1216 10K 100K 100K 100K PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L AP_S0IX_WAKE_SEL PM_SLP_SUS_L R1230 R1231 R1232 R1233 R1236 R1237 100K 100K 100K 100K 100K 100K 20 IN 20 IN 20 IN 20 6 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 5% 1/20W MF 201 5% 1/20W MF 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 201 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 B 14 20 73 110 20 SYNC_MASTER=X363_SAKKOC GPP_H0/SRCCLKREQ6* GPP_H1/SRCCLKREQ7* GPP_H2/SRCCLKREQ8* GPP_H3/SRCCLKREQ9* GPP_H4/SRCCLKREQ10* GPP_H5/SRCCLKREQ11* GPP_H6/SRCCLKREQ12* GPP_H7/SRCCLKREQ13* GPP_H8/SRCCLKREQ14* GPP_H9/SRCCLKREQ15* AM25 AH26 AL25 AF26 AK26 AL26 AJ27 AH27 AM26 AK27 PAGE TITLE TBT_W_CLKREQ_L EG_CLKREQ_OUT_L AP_S0IX_WAKE_SEL AP_S0IX_WAKE_L TBT_X_CIO_PWR_EN TBT_T_CIO_PWR_EN TBT_W_CIO_PWR_EN TBT_X_USB_PWR_EN TBT_T_USB_PWR_EN TBT_W_USB_PWR_EN IN 20 111 5 SYNC_DATE=04/14/2016 PCH RTC/HDA/JTAG/SATA/CLK DRAWING NUMBER OUT 12 19 IN 12 19 Apple Inc. OUT 29 OUT 103 OUT 20 OUT 29 OUT 103 OUT 20 BOM_COST_GROUP=CPU & CHIPSET 7 1 5% 20 IN BI PP3V3_S0 LPC_SERIRQ AUD_PWR_EN CAMERA_PWR_EN AP_S0IX_WAKE_L PP3V3_S0 1 201 1 201 1 201 CLOCKS & CONTROL AL20 AM19 AK20 AL19 AH22 AK22 89 76 73 70 46 27 20 12 101 70 46 20 12 PCI EXPRESS GPP_B5/SRCCLKREQ0* GPP_B6/SRCCLKREQ1* GPP_B7/SRCCLKREQ2* GPP_B8/SRCCLKREQ3* GPP_B9/SRCCLKREQ4* GPP_B10/SRCCLKREQ5* 15 13 12 20 CLKOUT_ITPXDP_N L6 CLKOUT_ITPXDP_P L5 CLKOUT_PCIE_N9 CLKOUT_PCIE_P9 CLKOUT_PCIE_N11 CLKOUT_PCIE_P11 PP1V0_SUS 114 CLKOUT_PCIE_N8 CLKOUT_PCIE_P8 T6 T5 1 73 46 20 12 CLKOUT_PCIE_N7 CLKOUT_PCIE_P7 NC_CLKOUT_PCIE_11_N NC_CLKOUT_PCIE_11_P 2.7K 100K 100K 1K 10K 110 GPP_A16/CLKOUT_48 AL16 EG_PEG_CLK100M_N EG_PEG_CLK100M_P 2 PLACE_NEAR=U1100.E4:1.25mm GPP_A9/CLKOUT_LPC0 AJ14 CLKOUT_PCIE_N6 CLKOUT_PCIE_P6 PCH_DIFFCLK_BIASREF 2 111 NC_CLKOUT_PCIE_6_N NC_CLKOUT_PCIE_6_P 46 29 12 R1248 R1209 R1210 R1212 2 OUT K6 K5 46 12 PCIE_WAKE_L SMC_WAKE_SCI_L PM_PWRBTN_L PM_BATLOW_L 100K OUT 111 NC_CLKOUT_PCIE_2_N NC_CLKOUT_PCIE_2_P 19 12 2 111 CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PP3V3_S5 20 113 100K OUT F2 F1 OUT 17 16 20 2 111 NC_CLKOUT_PCIE_1_N NC_CLKOUT_PCIE_1_P 110 IN 100K OUT SYSCLK_CLK24M_PCH NC_PCH_CLK24M_XTALOUT 2 111 XTAL24_IN B4 XTAL24_OUT B3 2 OUT CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 100K 35 J5 J6 100K 113 PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P R1241 R1242 R1243 R1244 R1245 R1246 OUT 2 35 100K 113 SYM 2 OF 12 /ESPI_CLK WWW.AliSaler.Com 100K 12 OMIT_TABLE 27 8 PP3V3_S4 12 1UF A 201 12 C1203 B MF 1 201 1 201 1 201 1 201 1 201 1 201 10% 10V 2 X5R 402-1 SRTCRST* 1/20W 20 2 1UF 1 AJ8 INTRUDER* 5% 114 47K C1202 1 12 PCH_SRTCRST_L AJ10 2 D 2 RTC_RESET_L PCH_INTRUDER_L 1 5% 1/20W MF 2 201 47K C 12 10K 100K 12 46 R1238 R1239 R1240 PCH_SRTCRST_L PCH_INTRUDER_L RTCX1 RTCX2 ESPI/LPC 5% 1/20W MF 201 2 R1203 OUT AL8 AM8 RTC 20K 1 IN 20 SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2 PP3V3_S0 R1205 12 20 15 13 12 R1213 BT_LOW_PWR_L 110 CLOCK SIGNALS 5% 1/20W MF 2 201 AG12 110 16 17 109 R12021 1M WAKE* (IPD-DeepSx) 20 /SX_EXIT_HOLDOFF* PP3V0_G3H R1201 PM_DSW_PWRGD DSW_PWROK AG23 59 12 1 AF8 (OD) PLT_RST_L 12 103 NC_PCH_DRAM_RESET_L DRAM_RESET* OUT OUT 48 12 AM11 GPP_A15/SUSACK* (IPU) IN 1 0 D 73 46 AL15 4 3 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 12 OF 145 12 OF 121 SIZE D A 8 7 6 5 4 3 2 1 OMIT_TABLE U1100 SKL-PCH-SFF H65946 FCBGA OUT 113 5 OUT 113 5 OUT 113 5 OUT 113 5 OUT 113 PP3V3_S0 113 5 OUT 113 5 OUT 113 5 IN 113 5 IN 113 5 IN 113 5 IN 113 5 IN 113 5 IN 113 5 IN 113 5 IN B19 A19 DMI_S2N_N<1> DMI_S2N_P<1> C20 B20 DMI_TXN1 DMI_TXP1 DMI_S2N_N<2> DMI_S2N_P<2> A21 B21 DMI_TXN2 DMI_TXP2 DMI_S2N_N<3> DMI_S2N_P<3> C22 D22 DMI_TXN3 DMI_TXP3 DMI_N2S_N<0> DMI_N2S_P<0> E20 F20 DMI_RXN0 DMI_RXP0 DMI_N2S_N<1> DMI_N2S_P<1> F19 G19 DMI_RXN1 DMI_RXP1 DMI_N2S_N<2> DMI_N2S_P<2> F21 E21 DMI_RXN2 DMI_RXP2 DMI_N2S_N<3> DMI_N2S_P<3> G22 F22 DMI_TXN0 DMI_TXP0 AC4 THERMTRIP* AC5 PM_THRMTRIP_L_R PECI AB5 PCH_PECI DMI_RXN3 DMI_RXP3 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 5% 1/20W MF 5% 1/20W MF 201 5% 1/20W MF 201 2 1 1 NC_PCH_STRP_BSSB_SEL_GPIO 13 201 SPI_CS0_R_L 13 2 2 2 5% 5% 5% 5% 1/20W 1/20W 1/20W 1/20W MF 201 MF 201 MF 201 MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 5% 1/20W 1/20W MF 201 MF 201 TPAD_SPI_CS_L 13 AUD_SPI_CS_L 13 AUD_SPI_MOSI 13 TPAD_SPI_MOSI 13 BT_PWRRST_L 13 AUD_SPI_CLK 13 AUD_SPI_MISO 13 TPAD_SPI_CLK 13 TPAD_SPI_MISO 13 BT_TIMESTAMP 13 20 13 OUT 13 35 OUT 18 OUT 14 OUT 13 20 CPU_RESET_L OUT 6 PRDY* AE4 XDP_CPU_PRDY_L OUT 6 18 115 PREQ* AE6 XDP_CPU_PREQ_L OUT 6 18 115 PCH_TRIGIN PCH_TRIGOUT AD7 AB6 PM_DOWN PM_SYNC AD5 AE7 R1314 PLACE_NEAR=U1100.AB6:1.27mm 5 1 CPU_PCH_PM_DOWN PM_SYNC_R 2 5 IN R1319 PLACE_NEAR=U1100.AE7:1.27mm 6 OUT PM_THRMTRIP_L IN CPU_PECI BI 6 46 47 48 6 47 D NO STUFF R1331 5% 1/20W MF 2 201 AC6 IN CPU_PWRGD 100K PLTRST_PROC* CPU_PCH_TRIGGER PCH_CPU_TRIGGER_R 1/20W 0201 1/20W 201 1/20W 201 1 6 18 115 1 2 33 5% 1/20W 33 5% PCH_CPU_TRIGGER MF 201 PM_SYNC 1/20W MF 201 OUT 5 OUT 6 R1326 150K 5% 1/20W MF 2 201 U1100 43 1 OUT SKL-PCH-SFF H65946 57 13 XDP_CPU_TRST_L OMIT_TABLE FCBGA NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 43 114 43 114 43 114 35 SYM 1 OF 12 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD TP1 TP2 18 ITP_PMODE AF1 ITP_PMODE AG6 JTAG_TCK 115 18 IN XDP_PCH_TCK 115 18 XDP_PCH_TDI (IPU) IN AF5 JTAG_TDI 115 18 XDP_PCH_TDO (Undriven) OUT AF6 JTAG_TDO (IPU) AG5 JTAG_TMS AF4 JTAGX XDP_PCH_TMS 20 IN PCH_JTAGX HDA_SDO AJ6 HDA_SDOUT_R HDA_RST_R_L HDA_RST* AM5 PCH_DISPA_BCLK_R PCH_DISPA_SDI PCH_DISPA_SDO_R DISPA_BCLK AE3 DISPA_SDI AE1 DISPA_SDO AD4 GPP_D5/I2S0_SFRM GPP_D6/I2S0_TXD GPP_D7/I2S0_RXD GPP_D8/I2S0_SCLK GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1 GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0 20 IN 201 MF 1/20W 5% 201 MF 1/20W 5% 2 1 33 2 1 33 R1310 PLACE_NEAR=U1100.AJ7:1.27mm R1311 PLACE_NEAR=U1100.AM6:1.27mm HDA_SDI0 AK5 HDA_SDI1 AK6 AH9 AG9 18 HDA_SYNC_R HDA_SYNC AM6 (IPD) 115 HDA_BIT_CLK_R HDA_BCLK AJ7 NC_PCH_TP1_AH9 NC_PCH_TP1_AG9 20 B A25 AA6 AA7 AF24 AH11 AL4 AL5 B11 B25 C11 C19 C2 D19 D2 H5 H6 W5 Y5 Y6 AUDIO 2 1 5% MF 2 5% MF 2 5% MF AF2 1 RSVD & TP PINS 47K 47K 1K 150K 100K 47K 47K 47K 47K 100K 1 620 2 AC30 AD31 AE30 AC31 AB32 AB31 AA33 AA32 R1327 R1328 R1329 R1330 BT_I2S_SYNC_R BT_I2S_R2D_R BT_I2S_D2R_R BT_I2S_CLK_R TP_PCH_DMIC_CLK1 20 TP_PCH_DMIC_DATA1 20 TP_PCH_DMIC_CLK0 20 TP_PCH_DMIC_DATA0 20 201 MF 1/20W 5% 201 MF 1/20W 5% 201 MF 1/20W 5% 201 MF 201 201 201 201 MF MF MF MF 1/20W 5% 1/20W 1/20W 1/20W 1/20W 5% 5% 5% 5% 2 1 33 2 1 33 2 1 33 2 2 2 2 2 1 1 1 1 1 33 33 33 33 33 HDA_BIT_CLK HDA_SYNC HDA_SDIN0 NC_HDA_SDIN1 R1313 PLACE_NEAR=U1100.AJ6:1.5mm R1312 PLACE_NEAR=U1100.AM5:2.27mm R1320 PLACE_NEAR=U1100.AE3:1.27mm 58 OUT 58 115 OUT 58 HDA_RST_L OUT 58 PCH_DISPA_SDO BT_I2S_SYNC BT_I2S_R2D BT_I2S_D2R BT_I2S_CLK C 58 IN HDA_SDOUT PCH_DISPA_BCLK R1321 PLACE_NEAR=U1100.AD4:1.27mm OUT OUT IN OUT BI 20 20 20 35 OUT 35 IN 35 BI 35 JTAG 1K 1K 1 CPU_TRST* 16 17 110 OMIT 0 BT_PWRRST_L BT_TIMESTAMP XDP_PCH_OBSDATA_A2 XDP_PCH_OBSDATA_B2 NC_PCH_STRP_BSSB_SEL_GPIO AH21 AM21 W28 U29 AK23 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B23/SML1ALERT*/PCHHOT* R1308 R1309 R1315 PCH_PROCPWRGD PROCPWRGD 12 13 15 110 PP3V3_SUS C OUT 12 13 15 110 PP3V3_S0 R1318 R1341 R1304 R1300 R1303 R1307 R1316 R1301 R1302 R1305 R1306 R1317 5 DMI_S2N_N<0> DMI_S2N_P<0> CPU/MISC 5 DMI D 113 SYM 5 OF 12 B OMIT_TABLE U1100 SKL-PCH-SFF H65946 FCBGA SYM 3 OF 12 57 OUT SPI_CLK_R 57 13 OUT SPI_CS0_R_L AJ24 111 OUT NC_SPI_CS1_L AK25 SPI0_CS1* (IPU) 111 OUT NC_SPI_CS2_L AG25 SPI0_CS2* (IPU) 57 18 BI SPI_MOSI_R AM23 SPI0_MOSI (IPD) 57 BI SPI_MISO AH25 SPI0_MISO (IPU) 57 18 BI SPI_IO<2> AM24 SPI0_IO2 (IPU) 57 BI SPI_IO<3> AK24 SPI0_IO3 (IPU) (IPU) GSPI SPI0_CS0* A AK21 AJ21 AJ20 AK19 AL23 AJ23 AH23 AH24 AUD_SPI_CS_L AUD_SPI_CLK AUD_SPI_MISO AUD_SPI_MOSI TPAD_SPI_CS_L_R TPAD_SPI_CLK_R TPAD_SPI_MISO_R TPAD_SPI_MOSI_R 13 13 13 13 201 201 201 201 MF MF MF MF NC_CLINK_CLK 115 CL_DATA AG2 NC_CLINK_DATA 115 CL_RST* AH4 NC_CLINK_RESET_L 115 CL_CLK AG3 C-LINK SPI0_CLK SPI AJ26 GPP_B15/GSPI0_CS* GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI GPP_B19/GSPI1_CS* GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI 1/20W 1/20W 1/20W 1/20W 5% 5% 5% 5% 2 2 2 2 1 1 1 1 33 33 0 33 R1322 R1323 R1324 R1325 TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI OUT 13 43 OUT 13 43 114 IN 13 43 114 OUT 13 43 114 SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 PCH DMI/FDI/PM/GFX/PCI DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 13 OF 145 13 OF 121 SIZE D A 8 7 6 5 4 3 OMIT_TABLE 29 IN 29 OUT 29 OUT USB3_EXTA_D2R_N USB3_EXTA_D2R_P F5 G5 USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P D4 D5 V4 V3 USB3_1_TXN USB3_1_TXP USB2N_2 USB2P_2 W2 W3 USB_UPC_PCH_TA_N USB_UPC_PCH_TA_P G6 F6 USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB2N_3 USB2P_3 U6 U7 USB_CAMERA_DFR_N USB_CAMERA_DFR_P B6 A6 USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP USB2N_4 USB2P_4 Y1 Y2 USB3_TEST_D2R_N USB3_TEST_D2R_P G7 H7 USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB2N_5 USB2P_5 U4 T4 USB3_TEST_R2D_N USB3_TEST_R2D_P C6 B7 USB2N_6 USB2P_6 AA4 AA3 USB2N_7 USB2P_7 T1 T2 D NC NC IN 114 IN 114 OUT 114 OUT U1100 USB2N_1 USB2P_1 NC NC 114 U1100 D7 E7 NC NC C8 B8 NC NC NC NC NC NC NC NC NC NC C SKL-PCH-SFF H65946 USB3_1_RXN USB3_1_RXP FCBGA SYM 7 OF 12 USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP USB2N_8 USB2P_8 USB_TEST_N USB_TEST_P 103 BI 103 BI 38 113 BI 38 113 BI 114 BI 114 USB_UPC_PCH_XB_N USB_UPC_PCH_XB_P BI 29 103 BI 103 USB2N_9 USB2P_9 R3 R4 NC_USB2N_9 NC_USB2P_9 B9 A8 USB3_5_TXN USB3_5_TXP USB2N_10 USB2P_10 AB3 AB2 NC_USB2N_10 NC_USB2P_10 F9 G9 USB3_6_RXN USB3_6_RXP USB2N_11 USB2P_11 R2 R1 USB_UPC_PCH_XA_N USB_UPC_PCH_XA_P C9 D9 USB3_6_TXN USB3_6_TXP USB2N_12 USB2P_12 AC1 AC2 NC_USB2N_12 NC_USB2P_12 USB2N_13 USB2P_13 P1 P2 NC_USB2N_13 NC_USB2P_13 USB2N_14 USB2P_14 AD2 AD1 NC_USB2N_14 NC_USB2P_14 GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2* GPP_E12/USB2_OC3* W30 U31 U33 V31 GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7 P30 N29 P31 L29 BI 29 BI 29 XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3 A 2 1 2 1 2 1 2 5% 5% 5% 5% 1/20W 1/20W 1/20W 1/20W MF NC_PCH_GPP_F15 NC_PCH_GPP_F16 NC_PCH_GPP_F17 NC_PCH_GPP_F18 USB2_COMP USB2_COMP V1 USB2_ID W6 USB2_ID USB2_VBUSSENSE U2 USB2_VBUSSENSE MF MF MF SSD_PWR_EN XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3 201 201 201 201 14 14 14 14 13 OUT 14 29 14 29 14 103 14 103 14 XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3 WWW.AliSaler.Com 8 1 TP 1TP-P5 TP 1TP-P5 TP 1TP-P5 TP 1TP-P5 TP 1TP-P5 TP TP-P5 7 F18 E18 PCIE8_RXN PCIE8_RXP PCIE14_RXN/SATA1B_RXN PCIE14_RXP/SATA1B_RXP E28 F27 B18 C18 PCIE8_TXN PCIE8_TXP PCIE14_TXN/SATA1B_TXN PCIE14_TXP/SATA1B_TXP A27 B27 F25 G25 PCIE11_RXN PCIE11_RXP PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP H27 G27 A24 B24 PCIE11_TXN PCIE11_TXP PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP A28 B28 F26 E26 PCIE12_RXN PCIE12_RXP PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP G28 F29 C25 D25 PCIE12_TXN PCIE12_TXP PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP B29 C29 PCIE_AP_D2R_N PCIE_AP_D2R_P E10 F10 PCIE1_RXN/USB3_7_RXN PCIE1_RXP/USB3_7_RXP PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP G29 G30 PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0> PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P B12 A12 PCIE1_TXN/USB3_7_TXN PCIE1_TXP/USB3_7_TXP PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP B30 C30 PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0> E11 F11 PCIE2_RXN/USB3_8_RXN PCIE2_RXP/USB3_8_RXP PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP H29 H28 PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> D12 C12 PCIE2_TXN/USB3_8_TXN PCIE2_TXP/USB3_8_TXP PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP C31 B31 PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1> G12 F12 PCIE3_RXN/USB3_9_RXN PCIE3_RXP/USB3_9_RXP PCIE19_RXN/SATA6_RXN J29 PCIE19_RXP/SATA6_RXP J28 PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2> B13 C13 PCIE3_TXN/USB3_9_TXN PCIE3_TXP/USB3_9_TXP PCIE19_TXN/SATA6_TXN D32 PCIE19_TXP/SATA6_TXP C32 PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2> E13 F13 PCIE4_RXN/USB3_10_RXN PCIE4_RXP/USB3_10_RXP PCIE20_RXN/SATA7_RXN K28 PCIE20_RXP/SATA7_RXP K29 PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3> B14 A14 PCIE4_TXN/USB3_10_TXN PCIE4_TXP/USB3_10_TXP PCIE20_TXN/SATA7_TXN E31 PCIE20_TXP/SATA7_TXP E32 PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3> XDP_PCH_OBSFN_C0 XDP_PCH_OBSDATA_A0 XDP_PCH_OBSDATA_A1 W31 Y30 W29 GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2 V32 V33 W33 XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_PCH_OBSDATA_B1 XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1 XDP_PCH_OBSDATA_D2 XDP_PCH_OBSDATA_D3 XDP_PCH_OBSFN_C1 U30 T32 T30 T28 R32 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7 GPP_F5/DEVSLP3 GPP_F6/DEVSLP4 GPP_F7/DEVSLP5 GPP_F8/DEVSLP6 GPP_F9/DEVSLP7 T33 P27 P29 R29 N28 TBT_X_PCI_RESET_L TBT_T_PCI_RESET_L SSD_RESET_L NC_HDD_PWR_EN SSD_PWR_EN TBT_POC_RESET NC_PCH_CAM_RESET NC_PCH_CAM_EXT_BOOT_L NC_WOL_EN T29 R31 M29 P33 GPP_F10/SCLOCK GPP_F11/SLOAD GPP_F12/SDATAOUT1 GPP_F13/SDATAOUT0 GPP_E8/SATALED* U27 XDP_PCH_OBSDATA_B3 A10 B10 PCIE_RCOMPP PCIE_RCOMPN 113 35 OUT 113 35 OUT 14 29 14 103 NC NC 14 103 IN 111 IN 111 IN 111 IN 111 NC NC NC NC PLACE_NEAR=U1100.V1:10.0mm NC NC 1 R1410 R1411 1K 5% 1/20W MF 2 201 14 87 114 115 113 14 113 14 14 29 14 14 29 14 14 103 14 14 103 14 113 14 113 14 14 TP1882 TP1883 TP1884 TP1885 TP1886 TP1887 XDP_PCH_OBSDATA_C0 XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3 B26 C26 NC NC 14 XDP_PCH_OBSFN_C0 XDP_PCH_OBSDATA_A0 XDP_PCH_OBSDATA_A1 XDP_PCH_OBSDATA_B1 XDP_PCH_OBSDATA_B2 XDP_PCH_OBSDATA_B3 PCIE13_TXN/SATA0B_TXN PCIE13_TXP/SATA0B_TXP 14 29 1 FCBGA SYM 8 OF 12 PCIE/SATA/USB3 NC NC NC NC NC NC D NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C 14 113 14 113 OUT 87 113 OUT 87 14 14 OUT 77 113 OUT 77 14 14 OUT 77 113 OUT 77 14 113 14 113 OUT 77 113 OUT 77 R1470 113 1% 1/20W MF 2 201 14 14 R1400 1% 1/20W MF 2 201 1 PCIE7_TXN PCIE7_TXP NC NC 100 10K 10K 10K 10K C16 B16 14 1 R1460 R1461 R1420 R1421 D27 D28 14 103 201 PCIE13_RXN/SATA0B_RXN PCIE13_RXP/SATA0B_RXP NC NC 12 20 73 110 MF PCIE7_RXN PCIE7_RXP NC NC 18 OUT 18 OUT 18 OUT 18 OUT 18 OUT 29 15 OUT 20 OUT 20 OUT 20 OUT 12 16 17 110 1/20W G15 G16 NC NC 14 5% B23 C23 NC NC B 2 PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP NC NC 5% 1/20W MF 2 201 1 PCIE6_TXN PCIE6_TXP NC NC 1K 100K A15 B15 NC NC 1 R1462 E24 F24 NC_USB2N_8 NC_USB2P_8 AA2 AA1 USB3_5_RXN USB3_5_RXP PP3V3_S0 PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP NC_USB2N_6 NC_USB2P_6 BI E15 F15 PCIE6_RXN PCIE6_RXP NC NC USB_UPC_PCH_TB_N USB_UPC_PCH_TB_P PCIE5_TXN PCIE5_TXP B22 A22 NC NC 29 D14 C14 PCIE9_TXN/SATA0A_TXN PCIE9_TXP/SATA0A_TXP NC NC NC NC BI PCIE5_RXN PCIE5_RXP SKL-PCH-SFF H65946 F23 E23 NC NC BI G14 F14 PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP NC NC F8 G8 PP3V3_SUS 1 OMIT_TABLE USB2 IN USB3 29 2 PCH_PCIE_RCOMPP PCH_PCIE_RCOMPN PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0> MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0> IN 87 113 IN 87 113 PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> IN 77 113 IN 77 113 PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2> MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2> IN 77 113 IN 77 113 PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3> PCIE_AP_D2R_N PCIE_AP_D2R_P MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3> PCIE_AP_D2R_N PCIE_AP_D2R_P IN 77 113 IN 77 113 IN 35 113 IN 35 113 MAKE_BASE=TRUE MAKE_BASE=TRUE OUT 18 OUT 18 B 14 OUT 20 OUT 20 OUT 20 87 114 OUT 20 OUT 14 87 114 115 115 14 SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/14/2016 PAGE TITLE PCH PCI-E/USB DRAWING NUMBER Apple Inc. 051-00647 REVISION R BI 18 NOTICE OF PROPRIETARY PROPERTY: BRANCH MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT MAKE_BASE=TRUE BI 18 BI 18 MAKE_BASE=TRUE BI 18 MAKE_BASE=TRUE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=CPU & CHIPSET 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 14 OF 145 14 OF 121 SIZE D A 1K R1531 1K 5% 1/20W MF 201 2 5% 1/20W MF 2 201 RAMCFG2:L R1532 1 1K 5% 1/20W MF 201 2 RAMCFG3:L 1 RAMCFG4:L R1533 1 1K 15 100K 1 100K 1 2 5% 2 5% 15 EDP_IG_PANEL_PWR_EN 15 89 EDP_IG_BKLT_EN 15 89 1/20W 1/20W MF 201 MF 201 15 15 5% 1/20W MF 2 201 20 OUT 89 15 OUT 89 15 OUT 111 OUT 20 OUT 57 15 OUT RAM Configuration Straps TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS QTY RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L DESCRIPTION REFERENCE DESIGNATOR(S) 89 OUT 89 OUT 89 OUT 89 OUT TABLE_BOMGROUP_ITEM TABLE_5_HEAD PART# 89 OUT 20 OUT 20 OUT BOM OPTION TABLE_5_ITEM 117S0006 0 RES,MF,1/20W,1KOHM,5%,0201,SMD PROTO 0 = 0x1F = 1 1 1 1 1 (-01 PCB) BOARD_ID:1F 20 OUT PROTO 0B = 0x1E = 1 1 1 1 0 (-02 PCB) 20 OUT PROTO 1 = 0x1D = 1 1 1 0 1 (-03 PCB) 20 OUT 20 OUT 29 15 OUT 29 15 OUT 29 15 IN TABLE_5_ITEM 117S0006 1 RES,MF,1/20W,1KOHM,5%,0201,SMD R1540 BOARD_ID:1E 117S0006 1 RES,MF,1/20W,1KOHM,5%,0201,SMD R1541 BOARD_ID:1D TABLE_5_ITEM TABLE_5_ITEM 117S0006 2 RES,MF,1/20W,1KOHM,5%,0201,SMD R1541,R1540 BOARD_ID:1C 117S0006 1 RES,MF,1/20W,1KOHM,5%,0201,SMD R1542 BOARD_ID:1B 117S0006 2 RES,MF,1/20W,1KOHM,5%,0201,SMD R1542,R1540 BOARD_ID:1A PROTO 2 = 0x1C = 1 1 1 0 0 (-04 & -05 PCB) TABLE_5_ITEM EVT1 = 0x1B = 1 1 0 1 1 (-06 PCB) 103 TABLE_5_ITEM EVT2 = 0x1A = 1 1 0 1 0 (-07 PCB) TABLE_5_ITEM 117S0006 2 RES,MF,1/20W,1KOHM,5%,0201,SMD R1542,R1541 BOARD_ID:19 117S0006 3 RES,MF,1/20W,1KOHM,5%,0201,SMD R1542,R1541,R1540 BOARD_ID:18 DVT = 0x19 = 1 1 0 0 1 (-08 PCB) TABLE_5_ITEM DVT1-1 = 0x18 = 1 1 0 0 0 (-09 PCB) TABLE_5_ITEM 117S0006 1 RES,MF,1/20W,1KOHM,5%,0201,SMD R1543 BOARD_ID:17 117S0006 2 RES,MF,1/20W,1KOHM,5%,0201,SMD R1543,R1540 BOARD_ID:16 117S0006 2 RES,MF,1/20W,1KOHM,5%,0201,SMD R1543,R1541 BOARD_ID:15 117S0006 3 RES,MF,1/20W,1KOHM,5%,0201,SMD R1543,R1541,R1540 BOARD_ID:14 TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM C MLB_BOARD_ID4 MLB_BOARD_ID3 MLB_BOARD_ID2 MLB_BOARD_ID1 MLB_BOARD_ID0 MLB_ID4:L 1 MLB_ID3:L R1544 1K 5% 1/20W MF 201 2 1 R1543 1K 5% 1/20W MF 201 2 MLB_ID2:L 1 R1542 1K 5% 1/20W MF 201 2 MLB_ID1:L 1 MLB_DEV_L MLB_ID0:L 1 R1541 1K R1540 1 1K 5% 1/20W MF 2 201 5% 1/20W MF 2 201 103 29 27 15 OUT 29 15 OUT 101 15 PVT = 0x17 = 1 0 1 1 1 (-10 PCB) 0x16 = 1 0 1 1 0 20 OUT 20 0x15 = 1 0 1 0 1 IN 20 IN 0x14 = 1 0 1 0 0 20 IN 20 IN 15 29 15 15 103 15 20 15 IN IN IN NC_ENET_LOW_PWR EDP_IG_PANEL_PWR_EN EDP_IG_BKLT_EN NC_EDP_IG_BKLT_PWM NC_TCON_RESET_L SPIROM_USE_MLB DP_X_SNK0_HPD_IG DP_X_SNK1_HPD_IG DP_T_SNK0_HPD_IG DP_T_SNK1_HPD_IG 5% 1/20W MF 2 201 FCBGA R28 M28 P32 N31 N30 L27 GPP_F14 GPP_F19/EDP_VDDEN GPP_F20/EDP_BKLTEN GPP_F21/EDP_BKLTCTL GPP_F22 GPP_F23 AH3 AJ5 AG7 AH7 GPP_I0/DDPB_HPD0 GPP_I1/DDPC_HPD1 GPP_I2/DDPD_HPD2 GPP_I3/DDPE_HPD3 DP_INT_IG_HPD AH2 GPP_I4/EDP_HPD NC_PCH_DDPB_CTRLCLK PCH_DDPB_CTRLDATA AH1 AG1 GPP_I5/DDPB_CTRLCLK GPP_I6/DDPB_CTRLDATA NC_PCH_DDPC_CTRLCLK PCH_DDPC_CTRLDATA AJ2 AK2 NC_PCH_DDPD_CTRLCLK PCH_DDPD_CTRLDATA AL3 AH5 GPP_I9/DDPD_CTRLCLK GPP_I10/DDPD_CTRLDATA AM27 AK28 AJ29 JTAG_TBT_X_TMS JTAG_TBT_T_TMS JTAG_TBT_W_TMS AG27 AH28 AG28 GPP_H13/SML3CLK GPP_H14/SML3DATA GPP_H15/SML3ALERT* DPMUX_UC_IRQ NC_ENET_MEDIA_SENSE NC_BKLT_FAULT_INT_L AM28 AL28 AK29 GPP_H16/SML4CLK GPP_H17/SML4DATA GPP_H18/SML4ALERT* NC_SDCONN_STATE_CHANGE NC_SDCONN_OC_L AM29 AL29 GPP_H19/ISH_I2C0_SDA GPP_H20/ISH_I2C0_SCL TBT_X_CIO_PLUG_EVENT_L TBT_T_CIO_PLUG_EVENT_L NC_TBT_W_PLUG_EVENT_L AH29 AL30 AL31 SYM 9 OF 12 GPP_I7/DDPC_CTRLCLK GPP_I8/DDPC_CTRLDATA JTAG_ISP_TDO JTAG_ISP_TDI JTAG_ISP_TCK GPP_G0/FAN_TACH_0 GPP_G1/FAN_TACH_1 GPP_G2/FAN_TACH_2 GPP_G3/FAN_TACH_3 GPP_G4/FAN_TACH_4 GPP_G5/FAN_TACH_5 GPP_G6/FAN_TACH_6 GPP_G7/FAN_TACH_7 N33 M33 M32 M31 L30 L33 L32 L31 SSD_BOOT_L NC_TP_PCH_GPP_G1 NC_TP_PCH_GPP_G2 NC_TP_PCH_GPP_G3 NC_TP_PCH_GPP_G4 NC_TP_PCH_GPP_G5 NC_TP_PCH_GPP_G6 NC_TP_PCH_GPP_G7 GPP_G8/FAN_PWM_0 GPP_G9/FAN_PWM_1 GPP_G10/FAN_PWM_2 GPP_G11/FAN_PWM_3 J32 J33 K30 K33 NC_TP_PCH_GPP_G8 PCH_BT_ROM_BOOT SOC_S2R_ACK_L SOC_PCH_DBELL_L GPP_G12/GSXDOUT GPP_G13/GSXSLOAD GPP_G14/GSXDIN GPP_G15/GSXSRESET* GPP_G16/GSXCLK H32 H31 K31 J31 F31 SOC_SWD_CLK PCH_SWD_IO PCH_SWD_MUX_SEL PCH_SOC_DBELL_L PCH_SOC_FORCE_DFU GPP_G17/ADR_COMPLETE G31 PCH_SOC_WDOG GPP_G18/NMI* GPP_G19/SMI* G33 H33 PCH_SOC_DFU_STATUS SOC_PANIC_L GPP_G20 GPP_G21 GPP_G22 GPP_G23 E33 E30 F32 F33 GPP_H10/SML2CLK GPP_H11/SML2DATA GPP_H12/SML2ALERT* GPP_H21/ISH_I2C1_SDA GPP_H22/ISH_I2C1_SCL GPP_H23 42 20 15 42 15 37 20 15 15 15 38 20 15 115 111 111 111 111 111 D 111 111 111 15 35 15 38 15 20 38 15 20 42 15 42 15 42 15 20 37 38 37 IN SOC_S2R_ACK_L SOC_SWD_CLK PCH_SWD_IO PCH_SOC_DBELL_L DEBUGUART_SEL_SOC SOC_PANIC_L SOC_PCH_DBELL_L 15 38 IN 1 BI 20 114 115 OMIT_TABLE NOSTUFF U1100 114 87 15 42 15 SKL-PCH-SFF H65946 35 15 BI 20 BI 20 PP1V8_SUS 17 16 R1561 R1537 R1538 R1539 R1546 R1557 R1562 NO STUFF 100K 100K 100K 100K 100K 100K 100K R1550 R1547 R1560 R1563 SSD_BOOT_L PCH_SWD_MUX_SEL PCH_BT_ROM_BOOT 100K 100K 100K 100K 36 35 20 OUT 12 16 17 110 114 16 17 110 12 13 110 IN 91 IN 43 15 43 15 R1553 R1554 R1555 R1529 R1535 R1502 R1503 R1504 R1505 R1506 R1507 R1508 R1509 R1512 R1520 R1521 R1522 R1525 R1515 R1526 R1599 R1524 R1523 R1513 R1511 R1527 R1528 R1536 R1548 R1549 R1551 R1552 B A 10K 10K 10K 100K 100K 47K 47K 47K 47K 47K 47K 1K 1K 10K 47K 47K 47K 100K 100K 100K 100K 100K 1 47K 100K 100K 1K 1K 100K 100K 100K 47K 100K 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 2 1 2 1 2 1 2 1 1 1 2 2 2 5% 5% 1/20W 1/20W MF 201 MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 5% 1/20W 1/20W MF 201 MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 5% 1/20W 1/20W MF 201 MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 2 1 2 1 2 1 2 BOMOPTION=OMIT 1 2 BOMOPTION=OMIT 1 2 1 1 2 2 1 2 1 2 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 NO STUFF JTAG_TBT_X_TMS JTAG_TBT_T_TMS JTAG_TBT_W_TMS TBT_X_CIO_PLUG_EVENT_L TBT_T_CIO_PLUG_EVENT_L PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L ALS_SOC_UART_D2R ALS_SOC_UART_R2D I2C_SSD_SDA I2C_SSD_SCL JTAG_ISP_TDO SOC_UART_D2R SOC_UART_R2D SOC_UART_RTS_L TPAD_SPI_INT_L SPIROM_USE_MLB TPAD_SPI_IF_EN OUT 91 OUT OUT 15 27 29 86 15 15 29 101 103 OUT 15 15 20 OUT 47 15 29 AK16 AM18 AL18 AH16 AH18 AK15 AG15 SSD_DEBUGI2C_SEL_PCH AP_DEV_WAKE NC_ISOLATE_CPU_MEM_L PCH_STRP_TOPBLK_SWP_L AG22 AG21 AM20 AL22 GPP_A17/ISH_GP7 GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5 GPP_B0 GPP_B1 GPP_B11 GPP_B14/SPKR 15 103 15 15 35 15 15 35 15 15 35 15 15 35 15 15 20 15 20 15 86 20 15 IN 20 IN 20 IN 15 86 15 15 29 103 15 15 15 20 15 15 20 15 15 15 15 43 15 15 57 114 20 15 43 OUT MLB_RAMCFG0 MLB_RAMCFG1 MLB_RAMCFG2 MLB_RAMCFG3 AD28 AD29 AC27 AC29 GPP_D0/SPI1_CS* GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI SPKR_ID0_NC NC_SPKR_ID1 NC_PCH_BSSB_CLK NC_PCH_BSSB_DATA AB28 AB29 AB30 Y31 GPP_D9 GPP_D10 GPP_D11 GPP_D12 MLB_BOARD_ID0 MLB_BOARD_ID1 MLB_BOARD_ID2 MLB_BOARD_ID3 Y27 AA29 AA28 Y29 GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL GPP_D15/ISH_UART0_RTS* GPP_D16/ISH_UART0_CTS* MLB_BOARD_ID4 MLB_DEV_L Y33 AA31 GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 MLB_RAMCFG4 TBT_W_PCI_RESET_L AC33 AC32 GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL GPPD/INTEGRATED SENSOR/UART/I2C PP3V3_S0 76 15 NC_CAMERA_RESET_L AP_RESET_L LCD_IRQ_L TBT_X_DPMUX_SEL TBT_T_DPMUX_SEL TPAD_SPI_IF_EN TPAD_SPI_INT_L GPPC/SMLINK/I2C/UART OUT GPPB 114 20 GPPA/ INTEGRATED SENSOR SYM 6 OF 12 PP3V3_SUS PP3V3_SUS GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT* AJ30 AK31 AK32 SMBUS_PCH_CLK SMBUS_PCH_DATA NC_PCH_STRP_TLSCONF GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT* AJ32 AH31 AH33 SML_PCH_0_CLK SML_PCH_0_DATA NC_PCH_STRP_ESPI GPP_C6/SML1CLK GPP_C7/SML1DATA AH32 AG32 SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS* GPP_C11/UART0_CTS* AG29 AF28 AF30 AF29 PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS*/ISH_UART1_RTS* GPP_C15/UART1_CTS*/ISH_UART1_CTS* AG33 AH30 AG31 AF33 SOC_UART_D2R SOC_UART_R2D SOC_UART_RTS_L SOC_UART_CTS_L GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL AE33 AF31 I2C_SSD_SDA I2C_SSD_SCL GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL AE29 AE27 NC_I2C_UPC_SDA NC_I2C_UPC_SCL GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS* GPP_C23/UART2_CTS* AD33 AD32 AE32 AE31 ALS_SOC_UART_D2R ALS_SOC_UART_R2D LCD_PSR_EN PCH_UART2_CTS_L WWW.AliSaler.Com 7 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 5% 5% 5% 5% 5% 5% 5% 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W MF MF MF MF MF MF MF 201 201 201 201 201 201 201 5% 1/20W MF 201 5% 5% 1/20W 1/20W MF MF 201 201 5% 1/20W MF 201 C OUT BI 49 49 IN 20 OUT 49 BI 49 IN 20 OUT 49 BI 49 IN 15 35 OUT 15 35 OUT 15 35 IN 15 35 B 15 20 15 20 15 15 BI OUT BI OUT 15 86 15 86 20 20 PROJ-SPECIFIC PULLUP, GPPBCH RAIL 15 20 15 20 15 15 NO STUFF LCD_IRQ_L SOC_UART_CTS_L JTAG_ISP_TDI JTAG_ISP_TCK SPKR_ID0_NC NC_SPKR_ID1 TBT_POC_RESET SSD_DEBUGI2C_SEL_PCH LCD_PSR_EN PCH_UART2_CTS_L AP_DEV_WAKE 15 76 114 15 SYNC_MASTER=X363_SAKKOC 15 29 SYNC_DATE=04/29/2016 PAGE TITLE PCH GPIO/MISC/NCTF 15 29 15 DRAWING NUMBER 15 20 Apple Inc. 14 29 103 051-00647 REVISION R 15 86 15 15 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 15 BOM_COST_GROUP=CPU & CHIPSET 8 1 PP1V8_SSD_FMC 84 83 82 81 80 78 77 FCBGA MLB BOARD ID Configuration Straps R1556 5% 1/20W MF 2 201 15 15 37 100K 15 109 38 15 15 87 114 OUT DEBUGUART_SEL_SOC NC_AUD_IPHS_SWITCH_EN NC_AUD_IP_PERIPHERAL_DET NC_AUD_I2C_INT_L 38 15 R1545 1K 1 U1100 R1534 RAMCFG_SLOT 2 SKL-PCH-SFF H65946 114 D 3 OMIT_TABLE 1K 5% 1/20W MF 2 201 4 GPPG 1 R1558 R1559 15 5 GPPF/ BACKLIGHT MLB_RAMCFG0 MLB_RAMCFG1 MLB_RAMCFG2 MLB_RAMCFG3 MLB_RAMCFG4 RAMCFG1:L R1530 1 6 GPPI/DISPLAY RAMCFG0:L 7 GPPH/I2C/INTEGRATED SENSOR /SMLINK 8 1 15 OF 145 15 OF 121 SIZE D A 8 7 6 5 4 3 2 L1600 FERR-220-OHM-2A OMIT_TABLE PP1V_SUS_PCH_VCCUSB2HDAPLL_F 1 17 U1100 0603 C1600 SKL-PCH-SFF H65946 1 1 3.0PF SYM 10 OF 12 POWER AUDIO PLL PRIMARY WELL 110 17 PP1V0_SUS D C AA14 AA15 AA16 AA17 AA18 AA19 AB15 N12 N13 P15 P16 P17 P18 P19 P20 R15 R16 R17 R18 R19 R20 T11 U14 U15 U16 U17 U18 U19 V14 V15 V16 V17 V18 V19 Y14 Y15 Y16 Y17 Y18 Y19 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 AB12 AC14 AD14 VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3 PP1V_SUS_PCH_VCCHDAPLL_F VCCHDAPLL_1P0 AC11 MOD PHY PRIMARY VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCMPHY_1P0 VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3 DEEP SX WELL K19 L14 L15 L16 L17 L18 L19 PP1V0_SUS 17 110 PP3V3_S5 AC20 AD20 P10 P11 VOLTAGE=1.0V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 12 17 110 ANALOG PLL USB3/ PCIE2/SATA2/PCIE3 VCCAMPHYPLL_1P0 K24 VCCAMPHYPLL_1P0 L24 PP1V_SUSSW_PCH_VCCAMPHYPLL_F 17 MIPI PLL PP1V_SUSSW_PCH_VCCAMPHYPLL_F VCCMIPIPLL_1P0 K21 17 GPPA PRIMARY WELL VCCPGPPA AC19 PP3V3_SUS VCCPGPPBCH AA22 VCCPGPPBCH AA23 VCCPGPPBCH AB23 PP3V3_SUS 13 17 110 VCCPGPPD V22 VCCPGPPD W22 VCCPGPPD W23 PP3V3_SUS 17 110 VCCPGPPEF T23 VCCPGPPEF U23 PP3V3_SUS PP3V3_SUS GPPB/GPPC/GPPH PRIMARY WELL 12 15 17 110 GPPD PRIMARY WELL PRIMARY WELL HVCMOS PP3V3_SUS 17 14 12 110 GPPE/GPPEF PRIMARY WELL GPPG PRIMARY WELL 17 PP1V_S5_PCH_DCPDSW AD19 PCIE PLL EBB PRIMARY 110 17 PP1V0_SUS K22 L22 B VCCAPLLEBB_1P0 VCCAPLLEBB_1P0 15 16 17 110 GPPD 1.8V PP1V8_SUS 15 16 17 109 DCPRTC AD18 PPDCPRTC_PCH 17 VCCRTC AC17 PP3V0_G3H 12 17 109 VCCPGPPG P23 DCPDSW_1P0 15 16 17 110 RTC WELL SUPPLY THERMAL SENSOR PW 110 17 PP3V3_S0 T12 VCCATS RTC LOGIC PW/VRM PP3V3_SUS VCCRTCPRIM_3P3 AD16 110 110 110 PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_SUS K10 M10 M11 K13 L12 SPI VCCCLK1 PP3V3_SUS VCCSPI AC22 VCCSPI AD22 17 110 ANALOG PLL USB2/VRM VCCCLK2 VCCCLK2 CLOCK BUFFERS PRIMARY 1.0 V 110 17 110 VCCCLK3 VCCCLK4 PP1V_SUS_PCH_VCCUSB2HDAPLL_F VCCUSB2PLL_1P0 AB10 VCCUSB2PLL_1P0 AC10 17 L1602 FERR-220-OHM-2A 17 16 15 109 PP1V8_SUS 1 2 0603 VCCHDA:SUS A 17 PP1V_SUS_PCH_VCCCLK5_F J11 J12 VCCCLK5 VCCCLK5 L1601 FERR-220-OHM-2A 109 17 PP1V8_S0 1 2 0603 VCCHDA:S0 HD AUDIO POWER AD13 VCCHDA WWW.AliSaler.Com 7 3.0PF 1 +/-0.1PF 25V NP0-C0G 2 0201 PP1V8_S0_PCH_VCCHDA_F 8 C1601 6 1 C1603 0.1UF 10% 2 6.3V X5R 0201 SKL-PCH-SFF H65946 SKL-PCH-SFF H65946 C1602 10% 2 6.3V X5R 0201 U1100 U1100 0.1UF +/-0.1PF 25V NP0-C0G 2 0201 FCBGA OMIT_TABLE OMIT_TABLE 2 A11 A13 A16 A18 A20 A23 A26 A29 A5 A7 A9 AA10 AA11 AA12 AA13 AA20 AA21 AA24 AA27 AA30 AA5 AB1 AB11 AB13 AB14 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB24 AB27 AB33 AB4 AB7 AC12 AC13 AC15 AC16 AC18 AC21 AC23 AC24 AC28 AC3 AC7 AD10 AD11 AD12 AD15 AD17 AD21 AD23 AD24 AD27 AD3 AD30 AD6 AE2 AE28 AE5 AF10 AF11 AF13 AF14 AF15 AF16 AF18 AF19 AF20 AF21 AF22 AF23 AF25 AF27 AF3 AF32 AF7 AF9 AG13 AG14 AG19 AG24 AG26 AG30 AG4 AG8 AH19 AH6 AJ12 AJ15 AJ19 AJ22 FCBGA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SYM 11 OF 12 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AJ25 AJ28 AJ3 AJ31 AJ9 AK18 AK30 AK4 AK7 AK8 AL10 AL13 AL21 AL24 AL27 AL6 AL7 AM16 AM7 AM9 B5 C10 C15 C21 C24 C27 C28 C3 C4 C5 C7 D10 D11 D13 D15 D16 D18 D20 D21 D23 D24 D26 D29 D3 D30 D31 D6 D8 E12 E14 E16 E19 E22 E25 E27 E29 E3 E5 E6 E8 E9 F16 F28 F30 F7 G1 G10 G11 G13 G18 G20 G21 G23 G24 G26 G32 G4 H3 H30 H4 J10 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J27 J30 J7 K1 K11 K12 K14 K15 K16 K17 K18 K20 K23 K27 K32 K4 K7 L10 L11 L13 L20 L21 L23 L28 L3 L4 L7 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M27 M30 M5 N1 N10 N11 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N27 N32 N4 N7 P12 P13 P14 P21 P22 P24 P28 P3 P4 P7 R10 R11 R12 R13 R14 R21 R22 R23 R24 R27 R30 R33 R5 T10 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T24 T27 SYM 12 OF 12 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 T3 T31 T7 U1 U10 U11 U12 U13 U20 U21 U22 U24 U28 U3 U32 U5 V10 V11 V12 V13 V2 V20 V21 V23 V24 V27 V28 V29 V30 V5 V6 V7 W1 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W24 W27 W32 W4 W7 Y10 Y11 Y12 Y13 Y20 Y21 Y22 Y23 Y24 Y28 Y3 Y32 Y4 Y7 D1 C1 B1 A2 A3 A4 B2 A30 A31 A32 A33 B33 C33 D33 B32 AJ33 AK33 AL33 AM33 AM32 AM31 AM30 AL32 AM4 AM3 AM2 AM1 AL1 AK1 AJ1 AL2 D C B SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/25/2016 PAGE TITLE PCH Power DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE BOM_COST_GROUP=CPU & CHIPSET 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT Current data from LPT EDS (doc #486708, Rev 1.0). 5 FCBGA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.8V 1 1 16 OF 145 16 OF 121 SIZE D A 8 7 6 5 4 3 2 1 1000PF CAPS ARE INTEL PLACEHOLDERS & ALL PLACENEAR NEED TO BE UPDATED PP1V0_SUS 110 16 PLACE_NEAR=U1100.U17:1MM PLACE_NEAR=U1100.N12:1MM 1 C1743 C1750 1UF 12PF 10% 2 6.3V CERM 402 16 PP1V_S5_PCH_DCPDSW 1 5% 25V NP0-C0G 2 0201 C1730 1 1 0.1UF C1731 0.1UF 10% 2 16V X5R-CERM 0201 10% 2 16V X5R-CERM 0201 C1732 1 1 0.1UF C1733 C1700 0.1UF 10% 2 16V X5R-CERM 0201 1 22UF 10% 2 16V X5R-CERM 0201 1 C1701 D 16 C1751 1 1 12PF C1736 47UF 5% 25V NP0-C0G 2 0201 C1737 1 20% 2 6.3V POLY-TANT 0805 1UF 20% 2 6.3V X6S-CERM 0201 C1734 1 1 0.1UF 1 C1735 1UF 0.1UF 10% 2 16V X5R-CERM 0201 C1738 20% 2 6.3V X6S-CERM 0201 10% 2 16V X5R-CERM 0201 PP1V8_SUS PLACE_NEAR=U1100.P23:1MM C1708 C1747 20% 2 6.3V X6S-CERM 0201 10% 2 6.3V CERM 402 PLACE_NEAR=U1100.L17:2.1MM PP1V0_SUS 16 15 1UF 1UF 20% 6.3V X5R-CERM-1 2 603 PLACE_NEAR=U1100.L17:1.4MM 110 109 VOLTAGE=1V PLACE_NEAR=U1100.V17:1MM 1 PLACE_NEAR=U1100.AD19:1MM 110 16 13 PLACE_NEAR=U1100.P23:1MM 1 1 22UF C1714 0.1UF 10% 20% 6.3V X5R-CERM-1 2 603 2 16V X5R-CERM 0201 PLACE_NEAR=U1100.AA23:1MM PP3V3_SUS 110 PLACE_NEAR=U1100.L17:1MM 1 1 C1702 16 PP3V3_SUS 0.1UF 1UF 1 10% 2 16V X5R-CERM 0201 20% 2 6.3V X6S-CERM 0201 D PLACE_NEAR=U1100.W22:1MM C1710 C1716 0.1UF 10% 2 16V X5R-CERM 0201 PLACE_NEAR=U1100.U23:1MM 110 16 PLACE_NEAR=U1100.K22:1MM PP1V0_SUS 110 16 15 PP3V3_SUS 110 PLACE_NEAR=U1100.K22:1MM 1 C1739 1 0.1UF 16 C1703 20% 2 6.3V X6S-CERM 0201 16 15 12 C 20% 2 6.3V X6S-CERM 0201 109 C1709 1 16 12 PP3V0_G3H PLACE_NEAR=U1100.AC17:1MM PLACE_NEAR=U1100.AC17:1MM C1746 1 0.1UF 10% 2 16V X5R-CERM 0201 16 C1718 1UF PP3V3_SUS 0.1UF 110 1 PLACE_NEAR=U1100.AC19:1MM 110 1 PLACE_NEAR=U1100.T12:1MM C1713 10% 2 16V X5R-CERM 0201 PLACE_NEAR=U1100.AD18:1MM PPDCPRTC_PCH PP3V3_S0 0.1UF 1UF 10% 2 16V X5R-CERM 0201 VOLTAGE=3.3V 1 16 C1721 1 1UF 10% 2 16V X5R-CERM 0201 C1722 0.1UF 10% 2 16V X5R-CERM 0201 20% 2 6.3V X6S-CERM 0201 PLACE_NEAR=U1100.AD16:1MM PP3V3_SUS PLACE_NEAR=U1100.AD16:1MM 1 C1745 1 1UF 20% 2 6.3V X6S-CERM 0201 C1715 C PCH SIDE RAIL SIDE 0.1UF 10% 2 16V X5R-CERM 0201 OMIT_TABLE L1700 2.2UH-240MA-0.221OHM PLACE_NEAR=U1100.AD13:1MM 109 PP1V8_S0 16 PLACE_NEAR=U1100.AD13:1.2MM 1 C1749 1 16 14 12 C1748 20% 2 6.3V X5R-CERM-1 603 C1744 1 C1752 12PF 47UF 5% 2 25V NP0-C0G 0201 20% 2 6.3V POLY-TANT 0805 C1754 C1717 110 16 12 VOLTAGE=1V PP1V_SUSSW_PCH_VCCAMPHYPLL_F 2 MAKE_BASE=TRUE 1 1 PLACE_NEAR=U1100.K24:3MM 12PF 1UF 20% 2 6.3V X6S-CERM C1740 C1704 C1705 0.1UF 10% 20% 16V 2 6.3V X5R-CERM 2 POLY-TANT 0201 0805 PLACE_NEAR=U1100.K24:1MM 0201 PP1V_SUSSW_PCH_VCCAMPHYPLL_F PP1V_SUSSW_PCH_VCCAMPHYPLL_F PLACE_NEAR=U1100.L24:1MM 1 1 47UF 5% 25V NP0-C0G 2 0201 1 C1719 1UF 20% 2 6.3V X6S-CERM 0201 1 16 16 1UF 20% 2 6.3V X6S-CERM 0201 PLACE_NEAR=U1100.K21:1MM OMIT_TABLE C1720 L1701 0.1UF 2.2UH-240MA-0.221OHM 10% 2 16V X5R-CERM 0201 110 PP1V0_SUS 1 C1755 1 12PF PP1V_SUS_PCH_VCCCLK5_F 2 MAKE_BASE=TRUE 1 PLACE_NEAR=U1100.J12:3MM 12PF 1 5% 25V NP0-C0G 2 0201 C1723 1 0.1UF 20% 10V CERM 2 402 1 C1724 2.2UH-240MA-0.221OHM PP1V0_SUS 1 C1756 3.0PF C1707 10% 2 16V X5R-CERM 0201 2 6.3V X6S-CERM 0.1UF 1UF 20% 0201 B PLACE_NEAR=U1100.J11:1MM 1 PP3V3_SUS VOLTAGE=1V PP1V_SUS_PCH_VCCUSB2HDAPLL_F 2 MAKE_BASE=TRUE 0603 1 PLACE_NEAR=U1100.AC10:3.6MM C1742 C1711 0.1UF 10% 20% 2 6.3V 2 16V X5R-CERM POLY-TANT 0201 0805 PLACE_NEAR=U1100.AC10:2.1MM PLACE_NEAR=U1100.AC22:1MM PP1V_SUS_PCH_VCCUSB2HDAPLL_F PP1V_SUS_PCH_VCCUSB2HDAPLL_F PLACE_NEAR=U1100.AB10:1MM 1 1 47UF +/-0.1PF 25V NP0-C0G 2 0201 1 C1741 L1702 20% 2 10V CERM 402 PLACE_NEAR=U1100.AC20:1MM 16 16 OMIT_TABLE 0.1UF 110 110 PP1V_SUS_PCH_VCCCLK5_F PLACE_NEAR=U1100.J11:1MM 1 1 20% 2 6.3V POLY-TANT 0805 PLACE_NEAR=U1100.J12:1MM PLACE_NEAR=U1100.P10:1MM C1753 C1706 47UF 5% 25V NP0-C0G 2 0201 PP3V3_S5 VOLTAGE=1V 0603 PLACE_NEAR=U1100.AD14:1MM B 1 PLACE_NEAR=U1100.AB12:1MM PP3V3_SUS 1 1 22UF 10% 2 16V X5R-CERM 0201 PP1V0_SUS 0603 0.1UF 110 110 C1712 16 16 1UF 20% 2 6.3V X6S-CERM 0201 PLACE_NEAR=U1100.AC11:1MM C1757 0.1UF 10% 2 16V X5R-CERM 0201 PART NUMBER 113S0022 QTY 3 DESCRIPTION REFERENCE DES RES,MF,1A MAX,0OHM,5%,0603 A CRITICAL BOM OPTION L1700,L1701,L1702 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE PCH DECOUPLING DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT Current data from LPT EDS (doc #486708, Rev 1.0). WWW.AliSaler.Com 8 BOM_COST_GROUP=CPU & CHIPSET 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 17 OF 145 17 OF 121 SIZE D A 8 7 6 5 6 6 6 6 IN IN XDP_BPM_L<1> IN XDP_BPM_L<2> IN XDP_BPM_L<3> 110 TP1800 TP1801 TP1802 TP1803 1K 5% 1/20W MF 201 2 PLACE_NEAR=U0500.BN28:2.54MM 115 13 6 BI 115 13 6 IN 115 73 18 6 IN 6 IN 6 IN 6 IN PP3V3_SUS XDP_PRESENT_CPU XDP_CPU_PREQ_L XDP_CPU_PRDY_L CPU_CFG<2> CPU_CFG<3> 1K 6 5% 1/20W MF 201 2 73 46 12 48 46 PM_RSMRST_L IN R1800 R1802 10 PLACE_NEAR=U1100.AM10:3MM 57 13 SPI_MOSI_R IN 1 2 PLACE_NEAR=U1100.AF12:3.8MM PM_PWRBTN_L OUT 1K XDP:YES R1803 1K 5% 1/20W 115 18 6 20 1 2 R1835 0 6 IN 6 IN OBSDATA_A2 OBSDATA_A3 5% 1/20W MF 201 1 2 OBSDATA_B0 OBSDATA_B1 CPU_CFG<6> CPU_CFG<7> OBSDATA_B2 OBSDATA_B3 1/20W MF 201 18 13 OUT 2 XDP:YES 5% 1/20W MF 0201 PLACE_NEAR=J1800.58:28MM HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 SDA SCL TCK1 TCK0 NC NC XDP_PCH_TCK XDP:YES 1 NC SPI_MOSI_R_CONN 5% OBSFN_B0 OBSFN_B1 CPU_CFG<4> CPU_CFG<5> XDP_PM_RSMRST_L XDP_CPU_PWRBTN_L XDP:YES PLACE_NEAR=U1100.AM23:2.54MM PCH_JTAGX OUT IN XDP:YES XDP_CPU_TCK OUT 6 201 MF 115 C IN C1804 61 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 OBSDATA_A0 OBSDATA_A1 NC NC R18041 62 NO_XNET_CONNECTION CPU_CFG<0> CPU_CFG<1> XDP:YES 11 8 6 PP1V0_S0SW M-ST-SM1 XDP_PIN_1 OBSFN_A0 OBSFN_A1 PLACE_NEAR=J1800.48:2.54MM 110 DF40RC-60DP-0.4V R18011 PULL CFG<3> LOW WHEN XDP PRESENT D 115 1 NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug. J1800 XDP:YES 110 2 PP1V0_SUS XDP_CONN 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 3 Primary / Merged (CPU/PCH) Micro2-XDP Extra BPM Testpoints XDP_BPM_L<0> 4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 0.1UF 10% 6.3V 2 CERM-X5R 0201 C1800 0.1UF CPU_CFG<17> CPU_CFG<16> OBSDATA_C0 OBSDATA_C1 CPU_CFG<8> CPU_CFG<9> OBSDATA_C2 OBSDATA_C3 CPU_CFG<10> CPU_CFG<11> 10% 6.3V CERM-X5R 2 0201 64 63 518S0847 6 IN 6 IN 6 IN 6 IN 6 IN 6 CPU_CFG<19> CPU_CFG<18> IN 6 IN 6 115 18 13 XDP_PCH_TDI R1891 51 PLACE_NEAR=U1100.AF5:28MM 18 13 XDP_PCH_TMS R1892 18 6 XDP_CPU_TDO R1810 51 PLACE_NEAR=U0500.BT28:28MM XDP_CPU_TCK R1813 OBSDATA_D0 OBSDATA_D1 CPU_CFG<12> CPU_CFG<13> IN 6 IN 6 OBSDATA_D2 OBSDATA_D3 CPU_CFG<14> CPU_CFG<15> IN 6 IN 6 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NC_ITPXDP_CLK100MP NC_ITPXDP_CLK100MN 115 1 18 13 IN 12 113 115 IN 12 113 115 XDP:YES 2 1 2 1 2 51 1 R1898 51 PROPER WAY TO TERMINATE? 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 D XDP:YES 2 1 2 1 NOSTUFF 2 1 PLACE_NEAR=U1100.AG6:28MM XDP_PCH_TRST_L MF XDP:YES 51 R1897 1/20W XDP:YES 51 PLACE_NEAR=U0500.BR28:28MM XDP_PCH_TCK 5% XDP:YES PLACE_NEAR=U1100.AG5:28MM NOSTUFF 2 1 R1830 1K XDP:YES 5% 1/20W MF 2 201 R1806 PLACE_NEAR=U0500.E8:2.54MM ITP_PMODE XDP_DBRESET_L 0 1 PM_SYSRST_L 2 BI 12 46 115 5% 1/20W MF 0201 13 IN TDO TRSTn TDI TMS XDP_PRESENT# 1 18 6 18 ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR. R1821 XDP:YES C1801 1 C1806 0.1UF 0.1UF 10% 2 6.3V CERM-X5R 0201 0 1 PLACE_NEAR=J1800.51:2.54MM R1822 10% 2 6.3V CERM-X5R 0201 0 R1823 R1824 2 XDP:YES 1 PLACE_NEAR=J1800.53:2.54MM PLACE_NEAR=J1800.43:28MM PLACE_NEAR=J1800.47:28MM PLACE_NEAR=J1800.44:28MM R1890 51 PLACE_NEAR=U1100.AF6:28MM 115 0 2 XDP:YES 1 PLACE_NEAR=J1800.55:2.54MM PLACE_NEAR=J1800.42:28MM XDP_PCH_TDO 115 OBSFN_D0 OBSFN_D1 XDP:YES 1 IN 18 13 115 XDP:YES 1 OBSFN_C0 OBSFN_C1 115 0 2 XDP:YES 1 2 PLACE_NEAR=J1800.57:2.54MM 5% 1/20W 5% 1/20W 5% 1/20W 5% 1/20W C XDP_CPU_TDO IN 6 18 115 XDP_CPU_TRST_L OUT 6 13 115 XDP_CPU_TDI OUT 6 115 XDP_CPU_TMS OUT 6 115 MF 0201 MF 0201 MF 0201 MF 0201 XDP:YES XDP_PCH_TDO XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS PCH XDP Signals 110 PP3V3_SUS 73 18 PP3V3_SUS U1830 XDP:YES 1 2 A 14 BI BI XDP_PCH_OBSDATA_A3 BI XDP_PCH_OBSDATA_B0 14 BI XDP_PCH_OBSDATA_C0 14 BI XDP_PCH_OBSDATA_C1 14 BI XDP_PCH_OBSDATA_C2 14 BI XDP_PCH_OBSDATA_C3 14 BI XDP_PCH_OBSDATA_D0 14 BI XDP_PCH_OBSDATA_D1 14 BI XDP_PCH_OBSDATA_D2 14 BI XDP_PCH_OBSDATA_D3 14 BI XDP_PCH_OBSFN_C1 14 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 TP1870 TP1871 TP1872 TP1873 TP1874 TP1875 TP1876 TP1877 TP1878 TP1879 TP1880 TP1881 Y 4 (OD) 1 NC NC NC 5 GND SPI_IO2_STRAP_L NC 1.5K 2 SPI_IO<2> OUT 13 5% 1/20W MF XDP:YES 201 (STRAP TO PCH) NO_XNET_CONNECTION PLACE_NEAR=U1830.4:2.54MM 49.9 3 13 XDP_PCH_OBSDATA_A2 5% 1/20W MF 2 201 13 18 115 R1831 PLACE_NEAR=U1830.4:7.54MM SOT891 100K B OUT C1830 74AUP1G07GF R1850 13 18 115 10% 2 10V X5R-CERM 0201 VCC Non-XDP Signals OUT 18 0.1UF XDP:YES 6 110 13 18 115 XDP:YES 1 These signals do not connect to the Primary (Merged) XDP connector in this architecture. The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere. PCH/XDP Signals 73 18 IN MF 1 B 57 R1832 1 2 1% NOSTUFF 201 1/20W NO_XNET_CONNECTION XDP_PRESENT_L OUT 73 NEED TO CONNECT TO VCCST, *STG POWER LOGIC DESIGN: X502/MLB LAST CHANGE: Mon Jun 15 22:04:28 2015 A SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/25/2016 PAGE TITLE CPU/PCH Merged XDP Unused GPIOs have TPs. USB Overcurrents are aliased, do not cause USB OC# events during PCH debug. DRAWING NUMBER Apple Inc. JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DEBUG WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 18 OF 145 18 OF 121 SIZE D A 8 7 6 5 4 3 2 PCH ME Disable Strap System 32kHz / 12MHz / 24MHz Clock Generator PPVRTC_U1900_RC 20 SPI_DESCRIPTOR_OVERRIDE_L IN 46 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=2.9V BYPASS=U1900.17:18:5MM 1 C1900 1 2.2UF SLG3AP3444 5% 1/20W MF 2 201 DMP31D0U SOT23 HDA_SDOUT_R OUT PCH IPD = 9-50k STQFN 20 20 20 CRITICAL 20 C1907 SYSCLK_CLK24M_X2 113 2 113 SYSCLK_CLK24M_X2_R 5% 1/20W MF 0201 4 3 +/-0.1PF 50V CER-C0G 0201 CRITICAL 32.768K_A 10 32.768K_B 13 24M_A 3 24M_B 6 24M_C 16 19 X2 20 X1 12M 7 NO STUFF SYSCLK_CLK32K_PCH SYSCLK_CLK32K_CAMERA_BT_AP SYSCLK_CLK24M_PCH NC_SYSCLK_CLK24M_CAMERA NC_SYSCLK_CLK24M_SSD SYSCLK_CLK12M_SMC 13 20 20 PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. ***** Circuit does not support HDA voltage >3.3V. 20 20 20 46 R1901 1M 24MHZ-10PPM-8PF-40OHM 1 VIO_32K_B VIOE_24M_A VIOE_24M_B VIOE_24M_C OE_12M GND 1 Y1900 2 C 0 1 IN VOUT 17 4 9 14 18 2 IN 46 R1900 9.5PF 1 IN PPVIO_32K_B_RC PPVIO_VIOE_A_RC NC_PPVIOE_CAMCLK NC_PPVIOE_SSDCLK SMC_CLK12M_EN 12 2 5 15 8 R1930 1K Q1930 20% 2 6.3V X5R-CERM 0201 U1900 SPI_DESCRIPTOR_OVERRIDE D PP1V8_S0 D 3 IN S 109 PP2V9_SYSCLK 2 VDD 1 D VRTC 11 G 1 PPVDD_U1900_RC 20 1 2.5X2.0MM-SM 5% 1/20W MF 2 201 CRITICAL C C1908 9.5PF 1 2 113 SYSCLK_CLK24M_X1 NOTE: 30 PPM or better required for SKL PCH +/-0.1PF 50V CER-C0G 0201 B B PCIe Wake Muxing 110 PP3V3_S5 AP_S0IX_WAKE_SEL SEL CRITICAL A 1 R1910 100K 5% 1/20W MF 2 201 C1910 1 0.1UF 10% 6.3V 2 CERM-X5R 0201 L H U1910 PI5A3157BC6E 6 SEL SC70 B1 1 IN 12 OUTPUT PCIE_WAKE_L (B0) AP_S0IX_WAKE_L (B1) AP_S0IX_WAKE_L OUT SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016 PAGE TITLE Chipset Support 1 12 DRAWING NUMBER 051-00647 1 5 VCC GND Apple Inc. 2 REVISION R 0 35 IN AP_PCIE_WAKE_L 4 3 A B0 PCIE_WAKE_L OUT 12 VER 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 19 OF 145 19 OF 121 SIZE D A 8 7 6 5 Platform Reset Connections 114 5 PLT_RST_L IN 2 SC70-HF 4 U2071 1 3 10% 16V X5R-CERM 0201 0 PLT_RST_L 2 5% 100K 2 1/20W 5% NOSTUFF 2 100K 2 10K 100K 2 2 PP3V3_S0 C R2080 R2082 47K R2083 47K 2 1/20W MF 201 5% 1/20W MF 201 R2005 1/20W MF 1 2 1 2 1 2 1/20W 20 IN 14 87 114 SMC_LRESET_L 46 201 MF 1/20W 101 1/20W 201 MF 35 5% 1/20W 1/20W 201 MF 5% 1/20W PP1V8_S4 1 LDO MF 1 201 R2087 201 3.3 MF 1 201 R2086 AP_CLKREQ_L 5% MF R2085 TBT_T_CLKREQ_L 5% 5% 1/20W 2 IN 19 IN NC_PCH_CLK24M_XTALOUT 1 MF 1K 1K 1K 1K 1 201 2 2 2 2 12 12 12 12 SSD_CLKREQ_L_R 15 PCH_DDPC_CTRLDATA 5% PCH_DDPD_CTRLDATA 15 5% 201 TBT_X_CLKREQ_L_R 1/20W 1/20W 1 2.2K 1 2.2K 201 1 NC_TBT_W_PLUG_EVENT_L SOC_UART_D2R SOC_UART_R2D 2.2K NC_PPVIOE_CAMCLK R2090 AP_CLKREQ_L_R C2015 20K 5% 1/20W MF 201 2 1 0 ALS_SOC_UART_D2R 42 15 ALS_SOC_UART_R2D ALS_SOC_UART_R2D 42 13 PCH_JTAGX PCH_JTAGX 18 DBGLED_S5 SYSCLK_CLK32K_OSC_SOC 2 PLACE_NEAR=U3900.AA22:3mm 5% 1/20W MF 0201 0 1 SOC_CLK_32K 2 OUT 37 5% 1/20W MF NOSTUFF 0201 NOSTUFF A DBGLED A R2012 20 PP1V8_S4 IN 1 LDO C2003 3.3 PPVIO_32K_B_RC 2 5% 1/20W MF 201 1 20% 6.3V 2 X5R 0201-1 D2090 GRN-90MCD-5MA-2.85V R2093 1 C2002 1 0.1UF PCH_DISPA_BCLK 13 PCH_DISPA_SDI Q2090 DMN5L06VK-7 SOT563 DBGLED 2 G A D2092 DMN5L06VK-7 SOT563 5 G S 1 DBGLED A D2093 20% 6.3V 2 X5R 0201-1 114 101 IN 73 70 46 43 12 IN 89 76 73 70 46 27 12 IN 70 46 12 IN 12 PCH_DISPA_SDO 15 NC_PCH_DDPB_CTRLCLK 15 NC_PCH_DDPC_CTRLCLK NC_PCH_DDPC_CTRLCLK 15 NC_PCH_DDPD_CTRLCLK NC_PCH_DDPD_CTRLCLK 12 NC_PCH_SLP_A_L NC_PCH_SLP_A_L 12 NC_PCH_LANPHYPC NC_PCH_LANPHYPC 12 NC_PCH_GPD7 Q2091 DMN5L06VK-7 D 6 2 G 3.3 2 5% 1/20W MF 201 1 C2004 1 0.1UF D2095 GRN-90MCD-5MA-2.85V 13 NC_PCH_TP1_AH9 NC_PCH_TP1_AH9 13 NC_PCH_TP1_AG9 NC_PCH_TP1_AG9 15 NC_PCH_BSSB_CLK 15 NC_PCH_BSSB_DATA 109 PLACE_SIDE=BOTTOM SILK_PART=S0_ON 20 IN PP3V3_G3H F = 1.7MHz Q2091 DMN5L06VK-7 1 C2009 1.0UF 1 20% 6.3V 2 X5R 0201-1 D 3 3.3 2 5% 1/20W MF 201 VER 3 5 G 109 20 IN PP3V3_G3H F = 1.7MHz 1 1.0UF 20% 6.3V 2 X5R 0201-1 MAKE_BASE=TRUE MAKE_BASE=TRUE NC_PCH_BSSB_CLK MAKE_BASE=TRUE NC_PCH_BSSB_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE NC_PCH_GPD7 NC_PCH_SLP_LAN_L NC_PCH_SLP_LAN_L MAKE_BASE=TRUE 15 NC_ISOLATE_CPU_MEM_L NC_ISOLATE_CPU_MEM_L NC_CLKOUT_PCIE_13_N NC_CLKOUT_PCIE_13_N 12 20 20 12 NC_CLKOUT_PCIE_13_P NC_CLKOUT_PCIE_13_P 12 20 MAKE_BASE=TRUE MAKE_BASE=TRUE NC_PCH_PME_L MAKE_BASE=TRUE 12 MAKE_BASE=TRUE MAKE_BASE=TRUE 14 NC_PCH_CAM_RESET NC_PCH_CAM_RESET 14 NC_PCH_CAM_EXT_BOOT_L NC_PCH_CAM_EXT_BOOT_L 14 NC_WOL_EN NC_WOL_EN 15 NC_ENET_LOW_PWR NC_ENET_LOW_PWR MAKE_BASE=TRUE 15 NC_I2C_UPC_SDA MAKE_BASE=TRUE 15 NC_I2C_UPC_SCL NC_PCH_PME_L MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE SOC_PCH_DBELL_L SOC_PCH_DBELL_L SOC_SWD_CLK SOC_SWD_CLK PCH_SOC_DBELL_L MAKE_BASE=TRUE NC_I2C_UPC_SDA MAKE_BASE=TRUE NC_I2C_UPC_SCL PCH_SOC_DBELL_L 19 NC_SYSCLK_CLK24M_CAMERA NC_SYSCLK_CLK24M_CAMERA 19 NC_SYSCLK_CLK24M_SSD NC_SYSCLK_CLK24M_SSD 15 NC_PCH_STRP_TLSCONF NC_PCH_STRP_TLSCONF 15 NC_PCH_STRP_ESPI NC_PCH_STRP_ESPI MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_PCH_STRP_BSSB_SEL_GPIO 13 MAKE_BASE=TRUE MAKE_BASE=TRUE NC_PCH_STRP_BSSB_SEL_GPIO MAKE_BASE=TRUE LPC_CLK24M_DPMUX_UC_R LPC_CLK24M_DPMUX_UC_R PPVDD_U1900_RC C2011 1 NC_CAMERA_RESET_L NC_CAMERA_RESET_L 0.1UF 10% 2 6.3V CERM-X5R 0201 3.3 5% 1/20W MF 201 2 19 UNUSED NETS in J80 C2005 0.1UF 15 MAKE_BASE=TRUE 10% 2 6.3V X5R SYNC_MASTER=X363_SAKKOC 0201 MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V PPVRTC_U1900_RC ENETSD_CLKREQ_L OUT 12 CAMERA_CLKREQ_L OUT 12 OUT 12 TBT_W_CLKREQ_L 19 SYNC_DATE=01/14/2016 PAGE TITLE Chipset Support 2 DRAWING NUMBER Apple Inc. 051-00647 REVISION R 1 C2007 0.1UF 10% 2 6.3V CERM-X5R 0201 1 TBT_W_CIO_PWR_EN C2008 0.1UF TBT_W_USB_PWR_EN 10% 2 6.3V X5R 0201 IN 12 IN 12 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=CPU & CHIPSET 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 7 B MAKE_BASE=TRUE MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V R2015 S 4 NC_HDD_PWR_EN MAKE_BASE=TRUE C2000 1 1 MAKE_BASE=TRUE MAKE_BASE=TRUE 19 SOT563 S 1 14 C MAKE_BASE=TRUE MAKE_BASE=TRUE 10% 2 6.3V CERM-X5R 0201 R2014 12 20 MAKE_BASE=TRUE NC_HDD_PWR_EN 20 12 DBGLED NC_PCH_DRAM_RESET_L NC_SPKR_ID1 0.1UF 10% 2 6.3V CERM-X5R 0201 NC_PCH_DRAM_RESET_L MAKE_BASE=TRUE MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.0V PPVIO_VIOE_A_RC MAKE_BASE=TRUE NC_SPKR_ID1 5 20 12 42 15 37 41 MAKE_BASE=TRUE NC_PCH_DDPB_CTRLCLK 38 15 OUT 15 5 C2001 10% 2 6.3V CERM-X5R 0201 SOC_PMU_CLK_32K NC_TCON_RESET_L 15 PCH_DISPA_SDI 2 NC_TCON_RESET_L 5 RC Filter -3dB @ 240KHz PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L WWW.AliSaler.Com 8 20 12 19 C2010 73 46 12 IN NC ALIASES BYPASS=U1900.02:18:5MM DBGLED_S0_D DBGLED VER 3 S 4 1.0UF 1 0402 K PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON SOT563 VER 3 1 DBGLED_S0 DBGLED_S0I3_D DBGLED D 3 C2006 5% 1/20W MF 201 2 0402 K PLACE_SIDE=BOTTOM SILK_PART=S3_ON 1 20K GRN-90MCD-5MA-2.85V 0402 VER 3 R2095 5% 1/20W MF 201 2 DBGLED_S3_D DBGLED D 6 1 DBGLED_S0I3 Q2090 PCH_DISPA_BCLK PCH_DISPA_SDO 0.1UF 10% 2 6.3V CERM-X5R 0201 PP1V0_SUS IN F = 500kHz DBGLED 20K GRN-90MCD-5MA-2.85V K PLACE_SIDE=BOTTOM SILK_PART=STBY_ON DBGLED_S4_D DBGLED A 1 5% 1/20W MF 201 2 0402 K PLACE_SIDE=BOTTOM SILK_PART=S5_ON D2091 110 DBGLED 20K GRN-90MCD-5MA-2.85V 0402 K (For development only) DBGLED A MAKE_BASE=TRUE 13 12 DBGLED_S3 DBGLED 12 5% 1/20W MF 0201 MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.8V 2 DBGLED_S4 MAKE_BASE=TRUE MAKE_BASE=TRUE R2026 1.0UF 5% 1/20W MF 201 2 76 114 MAKE_BASE=TRUE 35 OUT R2018 SYSCLK_CLK32K_OSC_Y1901 OUT 3 SYSCLK_CLK32K_WIFIBT 2 0 1 ALS_SOC_UART_D2R 19 5% 1/20W MF 0201 2.50X2.00-SM-COMBO 1 EN/DIS 0 2 20K OUT R2043 AP_CLKREQ_L_R Y2001 32.768KHZ-25PPM-15PF-5.5V 10% 2 10V X5R-CERM 0201 R2092 IN BKLT_PWM_MLB2TCON MAKE_BASE=TRUE BYPASS=U1900.12:18:5MM R2091 PP2003 SYSCLK_CLK32K_CAMERA_BT_AP MAKE_BASE=TRUE 2 1 D SM PP SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2 MAKE_BASE=TRUE NC ALIASES 2 Power State Debug LEDs 1 115 TBT_T_CLKREQ_L_R 109 DBGLED 1 SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2 MAKE_BASE=TRUE BKLT_PWM_MLB2TCON 19 NC_PPVIOE_SSDCLK R2013 DBGLED IN 42 MAKE_BASE=TRUE MF PP3V3_S5 19 42 15 37 15 110 PP2002 GREENCLK CLOCK OUT ALIASES SOC_UART_D2R SOC_UART_R2D 13 MF R2052 NC_TBT_W_PLUG_EVENT_L MAKE_BASE=TRUE MF 201 15 MAKE_BASE=TRUE 12 OUT NC_PPVIOE_SSDCLK TBT_X_CLKREQ_L_R TBT_T_CLKREQ_L_R 0.01UF 10% 2 6.3V CERM-X5R 0201 R2051 NC_SDCONN_OC_L SM PP SIGNAL ALIASES MAKE_BASE=TRUE MAKE_BASE=TRUE 73 20 14 12 1/20W NC_SDCONN_OC_L R2017 1 PP2001 MAKE_BASE=TRUE 19 NC_PPVIOE_CAMCLK SSD_CLKREQ_L_R J80 & J80G Display Port DDPB, DDPC,DDPD PP3V3_S0 5% 15 TP_PCH_DMIC_DATA0 13 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 2 PCH_DDPB_CTRLDATA NC_SDCONN_STATE_CHANGE 1 115 GND 15 NC_SDCONN_STATE_CHANGE 89 4 VCC C2014 SM PP P2MM MAKE_BASE=TRUE MAKE_BASE=TRUE SYSCLK_CLK24M_PCH SYSCLK_CLK24M_PCH PPVCC_RTC_OSC 0.1UF R2050 15 TP_PCH_DMIC_CLK0 13 MAKE_BASE=TRUE MIN_NECK_WIDTH=0.1750 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.8V 1 20% 6.3V 2 X5R 0201-1 110 NC_BKLT_FAULT_INT_L NC_PCH_CLK24M_XTALOUT 1 1.0UF B 15 NC_BKLT_FAULT_INT_L 15 5% 1/20W MF 201 C2013 NC_ENET_MEDIA_SENSE GreenCLK VIOEs 5% 1/20W R2016 109 SSD_RESET_L 1 201 1 P2MM MAKE_BASE=TRUE MAKE_BASE=TRUE 101 15 35 36 114 R2084 TP_PCH_DMIC_DATA1 MAKE_BASE=TRUE 14 AP_RESET_L TBT_X_CLKREQ_L 5% 12 PCIE CLKREQS MF 27 113 TBT_W_PCI_RESET_L 201 PP2000 P2MM NC_ENET_MEDIA_SENSE 1 SM PP MAKE_BASE=TRUE 27 29 TBT_T_PCI_RESET_L SSD_CLKREQ_L 5% NC_AUD_I2C_INT_L 1 MAKE_BASE=TRUE TBT_T_PCI_RESET_L 87 115 1 NC_AUD_I2C_INT_L TP_PCH_DMIC_CLK1 13 14 TBT_X_PCI_RESET_L 201 5% 12 14 20 73 110 47K MF 201 1 P2MM MAKE_BASE=TRUE 89 IN 100K MAKE_BASE=TRUE 201 MF R2004 DPMUX_UC_IRQ R2089 TBT_X_PCI_RESET_L 1/20W 5% 47K R2081 100K 1/20W R2003 1 NC_AUD_IP_PERIPHERAL_DET MAKE_BASE=TRUE 5% 1 NC_AUD_IP_PERIPHERAL_DET 15 15 MF R2002 1 15 MAKE_BASE=TRUE 89 OUT 15 R2001 1 NC_AUD_IPHS_SWITCH_EN 13 5% 1/20W MF 201 2 R2000 1 INTEL SKL DEBUG NC_AUD_IPHS_SWITCH_EN 89 MAKE_BASE=TRUE R2072 5% 1/20W MF 0201 2 1 201 LPC_CLK24M_DPMUX_UC 2 1% 1/20W MF 2 201 R2073 1 IN MF 4.99K NOSTUFF 35 20 12 1/20W DPMUX_LRESET_L 5% 1/20W MF 201 DPMUX_UC_IRQ 15 PLACE_NEAR=U2071:5MM PLACE_NEAR=R2001:5MM 100K 22 MAKE_BASE=TRUE 1 Unbuffered 1 LPC_CLK24M_DPMUX_UC_R R2070 5% 1/20W MF 2 201 2 R2006 1 5% LPC_CLK24M_DPMUX_UC_R 20 12 100K 0.1UF 114 100K MAKE_BASE=TRUE 15 R2007 PLT_RST_L_BUF 1 C2071 D IN 2 2 NC ALIASES 3 15 CRITICAL MC74VHC1G08 1 35 20 12 114 35 20 12 PLT_RST_L Scrub for Layout Optimization PP3V3_S0 3 DPMUX Connections Buffered 110 4 1 20 OF 145 20 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D CPU-Based Margining NOTE: CPU DAC output DDR3 (1.5V) DDR3L (1.35V) LPDDR3 (1.2V) step sizes: 7.70mV per step 6.99mV per step ?.??mV per step PP1V2_S3 VRef Dividers 1 109 R2221 8.2K 1% 1/20W MF 201 2 R2223 7 IN CPU_DIMMA_VREFDQ 1 10 1% 1/20W MF 201 C 1 PP0V6_S3_MEM_VREFDQ_A 2 PLACE_NEAR=R2221.2:1mm 8.2K 1% 1/20W MF 201 2 C2220 10% 2 6.3V X5R-CERM 0201 R2220 MEM_VREFDQ_A_RC 1 CPU_DIMMB_VREFDQ 1 10 1% 1/20W MF 0201 1 R2240 1 24.9 2 1% 1/20W MF 201 1 R2261 8.2K 1% 1/20W MF 201 2 PP0V6_S3_MEM_VREFCA_A 2 PLACE_NEAR=R2261.2:1mm MEM_VREFCA_A_RC 109 8.2K 1% 1/20W MF 201 2 C2260 10% 2 6.3V X5R-CERM 0201 MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1450 R2262 1 0.022UF B 109 1% 1/20W MF 201 2 R2263 5.1 MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000 8.2K C2240 1 8.2K R2242 1 MEM_VREFDQ_B_RC CPU_DIMM_VREFCA R2241 1% 1/20W MF 2 201 PLACE_NEAR=R2241.2:1mm 10% 2 6.3V X5R-CERM 0201 IN 1 PP0V6_S3_MEM_VREFDQ_B 0.022UF 7 C 2 2 1% 1/20W MF 201 1 24.9 1% 1/20W MF 201 R2243 IN 109 R2222 1 0.022UF 7 MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1450 B R2260 1 24.9 2 1% 1/20W MF 201 A SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 LPDDR3 VREF MARGINING DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DRAM WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 22 OF 145 21 OF 121 SIZE D A 8 7 6 5 4 3 2 1 LPDDR3 CHANNEL A (0-31) D D U2300 U2300 LPDDR3-16GB LPDDR3-16GB FBGA IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 26 7 IN 26 7 IN 113 26 7 IN 113 26 7 IN 26 23 7 IN C 26 23 7 IN MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9> MEM_A_CKE<0> MEM_A_CKE<1> K3 CKE0 K4 CKE1 MEM_A_CLK_P<0> MEM_A_CLK_N<0> J3 CK_T J2 CK_C MEM_A_CS_L<0> MEM_A_CS_L<1> L3 CS0* L4 CS1* L8 G8 P8 D8 26 23 7 IN MEM_A_ODT<0> 243 1% 1/20W MF 201 2 R2301 1 243 1% 1/20W MF 201 2 C2340 1 1 0.047UF 109 23 109 23 PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A NC NC NC NC NC NC NC NC NC NC NC NC C2341 B A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13 NC NC NC 109 25 24 23 22 C4 K9 R3 C2300 0.1UF 25 24 23 22 C2320 1.0UF 20% 2 10V X5R-CERM 0201-1 25 24 23 22 NU DQS0_T DQS1_T DQS2_T DQS3_T L10 G10 P10 D10 MEM_A_DQS_P<1> MEM_A_DQS_P<0> MEM_A_DQS_P<2> MEM_A_DQS_P<3> 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 116 116 109 109 109 116 109 25 24 23 22 25 24 23 22 25 24 23 22 25 24 23 22 NC 1 C2301 0.1UF 1 C2302 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2303 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2304 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2305 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2306 10UF 20% 2 4V X6S-CERM 0402-2 1 C2307 10UF 20% 2 4V X6S-CERM 0402-2 PP1V8_S3_MEM PP1V2_S3 PP1V2_S3 PP1V2_S3 A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9 F2 G2 H3 L2 M2 A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11 (2 OF 2) VDD1 OMIT_TABLE VSS CRITICAL VDD2 VSSCA VDDCA VSSQ VDDQ B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2 C C3 D3 F4 G3 G4 P3 M4 J4 B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12 B PP1V2_S3 1 109 MEM_A_DQS_N<1> MEM_A_DQS_N<0> MEM_A_DQS_N<2> MEM_A_DQS_N<3> DM0 DM1 DM2 DM3 10% 16V 2 X5R-CERM 0201 10% 2 16V X5R-CERM 0201 109 L11 G11 P11 D11 CRITICAL BI PP1V2_S3 1 116 DQS0_C DQS1_C DQS2_C DQS3_C OMIT_TABLE H4 VREFCA J11 VREFDQ 10% 6.3V 2 X5R 201 116 MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<15> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<14> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<3> MEM_A_DQ<1> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<2> MEM_A_DQ<0> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<16> MEM_A_DQ<22> MEM_A_DQ<18> MEM_A_DQ<23> MEM_A_DQ<17> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<21> MEM_A_DQ<24> MEM_A_DQ<26> MEM_A_DQ<31> MEM_A_DQ<25> MEM_A_DQ<28> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<27> B3 ZQ0 B4 ZQ1 0.047UF 10% 6.3V 2 X5R 201 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 J8 ODT MEM_A_ZQ<0> MEM_A_ZQ<1> R2300 1 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 A3 A4 A5 A6 A10 U3 U4 U5 U6 U10 EDFA232A1MA-GD-F 26 7 FBGA P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8 (1 OF 2) EDFA232A1MA-GD-F 113 R2 P2 N2 N3 M3 F3 E3 E2 D2 C2 1 C2321 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2322 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2323 10UF 20% 2 4V X6S-CERM 0402-2 1 C2324 10UF 20% 2 4V X6S-CERM 0402-2 PP1V2_S3 1 C2310 1.0UF A 20% 2 10V X5R-CERM 0201-1 1 C2311 1.0UF 20% 2 10V X5R-CERM 0201-1 1 PLACEMENT_NOTE: C2312 10UF 10uF caps are shared between DRAM. Distribute evenly. 20% 2 4V X6S-CERM 0402-2 SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 LPDDR3 DRAM Channel A (0-31) DRAWING NUMBER 116 109 25 24 23 22 PP1V8_S3_MEM Apple Inc. 1 C2330 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2331 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2332 10UF 20% 2 4V X6S-CERM 0402-2 1 C2333 051-00647 REVISION R 10UF 20% 2 4V X6S-CERM 0402-2 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 23 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DRAM WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 22 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 LPDDR3 CHANNEL A (32-63) D D U2400 U2400 LPDDR3-16GB LPDDR3-16GB FBGA IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 26 7 IN 26 7 IN 113 26 7 IN 113 26 7 IN 26 22 7 IN C 26 22 7 IN MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9> MEM_A_CKE<2> MEM_A_CKE<3> K3 CKE0 K4 CKE1 MEM_A_CLK_P<1> MEM_A_CLK_N<1> J3 CK_T J2 CK_C MEM_A_CS_L<0> MEM_A_CS_L<1> L3 CS0* L4 CS1* L8 G8 P8 D8 26 22 7 IN MEM_A_ODT<0> 243 1% 1/20W MF 201 2 R2401 1 243 1% 1/20W MF 201 2 C2440 1 1 0.047UF 109 22 109 22 PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A NC NC NC NC NC NC NC NC NC NC NC NC C2441 B A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13 NC NC NC 109 25 24 23 22 C4 K9 R3 C2400 0.1UF 25 24 23 22 C2420 1.0UF 20% 2 10V X5R-CERM 0201-1 25 24 23 22 NU DQS0_T DQS1_T DQS2_T DQS3_T L10 G10 P10 D10 MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<4> MEM_A_DQS_P<7> 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 116 116 109 109 109 116 109 25 24 23 22 25 24 23 22 25 24 23 22 25 24 23 22 NC 1 C2401 0.1UF 1 C2402 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2403 1.0UF 20% 10V 2 X5R-CERM 0201-1 1 C2404 1.0UF 20% 10V 2 X5R-CERM 0201-1 1 C2405 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2406 10UF 20% 2 4V X6S-CERM 0402-2 1 C2407 10UF 20% 2 4V X6S-CERM 0402-2 PP1V8_S3_MEM PP1V2_S3 PP1V2_S3 PP1V2_S3 A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9 F2 G2 H3 L2 M2 A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11 (2 OF 2) VDD1 OMIT_TABLE VSS CRITICAL VDD2 VSSCA VDDCA VSSQ VDDQ B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2 C C3 D3 F4 G3 G4 P3 M4 J4 B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12 B PP1V2_S3 1 109 MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<4> MEM_A_DQS_N<7> DM0 DM1 DM2 DM3 10% 2 16V X5R-CERM 0201 10% 16V 2 X5R-CERM 0201 109 L11 G11 P11 D11 CRITICAL BI PP1V2_S3 1 116 DQS0_C DQS1_C DQS2_C DQS3_C OMIT_TABLE H4 VREFCA J11 VREFDQ 10% 6.3V 2 X5R 201 116 MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<41> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<40> MEM_A_DQ<49> MEM_A_DQ<53> MEM_A_DQ<55> MEM_A_DQ<51> MEM_A_DQ<54> MEM_A_DQ<52> MEM_A_DQ<48> MEM_A_DQ<50> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<62> MEM_A_DQ<59> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<58> MEM_A_DQ<63> MEM_A_DQ<60> MEM_A_DQ<61> B3 ZQ0 B4 ZQ1 0.047UF 10% 6.3V 2 X5R 201 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 J8 ODT MEM_A_ZQ<2> MEM_A_ZQ<3> R2400 1 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 A3 A4 A5 A6 A10 U3 U4 U5 U6 U10 EDFA232A1MA-GD-F 26 7 FBGA P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8 (1 OF 2) EDFA232A1MA-GD-F 113 R2 P2 N2 N3 M3 F3 E3 E2 D2 C2 1 C2421 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2422 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2423 10UF 20% 4V 2 X6S-CERM 0402-2 1 C2424 10UF 20% 2 4V X6S-CERM 0402-2 PP1V2_S3 1 C2410 1.0UF A 20% 2 10V X5R-CERM 0201-1 1 C2411 1.0UF 20% 2 10V X5R-CERM 0201-1 1 PLACEMENT_NOTE: C2412 10UF 10uF caps are shared between DRAM. Distribute evenly. 20% 2 4V X6S-CERM 0402-2 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE LPDDR3 DRAM Channel A (32-63) DRAWING NUMBER 116 109 25 24 23 22 PP1V8_S3_MEM Apple Inc. 1 C2430 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2431 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2432 10UF 20% 2 4V X6S-CERM 0402-2 1 C2433 051-00647 REVISION R 10UF 20% 2 4V X6S-CERM 0402-2 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 24 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DRAM WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 23 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 LPDDR3 CHANNEL B (0-31) D D U2500 U2500 LPDDR3-16GB LPDDR3-16GB FBGA IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 26 7 IN 26 7 IN 113 26 7 IN 113 26 7 IN 26 25 7 IN C 26 25 7 IN MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9> MEM_B_CKE<0> MEM_B_CKE<1> K3 CKE0 K4 CKE1 MEM_B_CLK_P<0> MEM_B_CLK_N<0> J3 CK_T J2 CK_C MEM_B_CS_L<0> MEM_B_CS_L<1> L3 CS0* L4 CS1* L8 G8 P8 D8 26 25 7 IN MEM_B_ODT<0> 243 1% 1/20W MF 201 2 R2501 1 243 1% 1/20W MF 201 2 C2540 1 1 0.047UF 109 25 109 25 PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_B NC NC NC NC NC NC NC NC NC NC NC NC C2541 B A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13 NC NC NC 109 25 24 23 22 C4 K9 R3 C2500 0.1UF 10% 2 16V X5R-CERM 0201 109 25 24 23 22 NU DQS0_T DQS1_T DQS2_T DQS3_T L10 G10 P10 D10 MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<0> MEM_B_DQS_P<3> BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 116 116 109 109 109 116 109 25 24 23 22 25 24 23 22 25 24 23 22 25 24 23 22 NC 1 C2501 0.1UF 10% 2 16V X5R-CERM 0201 C2520 1.0UF 20% 2 10V X5R-CERM 0201-1 25 24 23 22 MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<0> MEM_B_DQS_N<3> DM0 DM1 DM2 DM3 112 1 C2502 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2503 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2504 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2505 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2506 10UF 20% 2 4V X6S-CERM 0402-2 1 C2507 10UF 20% 2 4V X6S-CERM 0402-2 PP1V8_S3_MEM PP1V2_S3 PP1V2_S3 PP1V2_S3 A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9 F2 G2 H3 L2 M2 A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11 (2 OF 2) VDD1 OMIT_TABLE VSS CRITICAL VDD2 VSSCA VDDCA VSSQ VDDQ B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2 C C3 D3 F4 G3 G4 P3 M4 J4 B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12 B PP1V2_S3 1 109 L11 G11 P11 D11 CRITICAL BI PP1V2_S3 1 116 DQS0_C DQS1_C DQS2_C DQS3_C OMIT_TABLE H4 VREFCA J11 VREFDQ 10% 2 6.3V X5R 201 116 MEM_B_DQ<8> MEM_B_DQ<15> MEM_B_DQ<12> MEM_B_DQ<9> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<20> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<16> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<19> MEM_B_DQ<3> MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DQ<7> MEM_B_DQ<5> MEM_B_DQ<2> MEM_B_DQ<6> MEM_B_DQ<4> MEM_B_DQ<26> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<31> MEM_B_DQ<27> MEM_B_DQ<25> MEM_B_DQ<28> MEM_B_DQ<24> B3 ZQ0 B4 ZQ1 0.047UF 10% 6.3V 2 X5R 201 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 J8 ODT MEM_B_ZQ<0> MEM_B_ZQ<1> R2500 1 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 A3 A4 A5 A6 A10 U3 U4 U5 U6 U10 EDFA232A1MA-GD-F 26 7 FBGA P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8 (1 OF 2) EDFA232A1MA-GD-F 113 R2 P2 N2 N3 M3 F3 E3 E2 D2 C2 1 C2521 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2522 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2523 10UF 20% 2 4V X6S-CERM 0402-2 1 C2524 10UF 20% 2 4V X6S-CERM 0402-2 PP1V2_S3 1 C2510 1.0UF A 20% 2 10V X5R-CERM 0201-1 1 C2511 1.0UF 20% 2 10V X5R-CERM 0201-1 1 PLACEMENT_NOTE: C2512 10UF 10uF caps are shared between DRAM. Distribute evenly. 20% 2 4V X6S-CERM 0402-2 SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 LPDDR3 DRAM Channel B (0-31) DRAWING NUMBER 116 109 25 24 23 22 PP1V8_S3_MEM Apple Inc. 1 C2530 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2531 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2532 10UF 20% 2 4V X6S-CERM 0402-2 1 C2533 051-00647 REVISION 10.0.0 R 10UF 20% 2 4V X6S-CERM 0402-2 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 25 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DRAM WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 24 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 LPDDR3 CHANNEL B (32-63) D D U2600 U2600 LPDDR3-16GB LPDDR3-16GB FBGA IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 113 26 7 IN 26 7 IN 26 7 IN 113 26 7 IN 113 26 7 IN 26 24 7 IN C 26 24 7 IN MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9> MEM_B_CKE<2> MEM_B_CKE<3> K3 CKE0 K4 CKE1 MEM_B_CLK_P<1> MEM_B_CLK_N<1> J3 CK_T J2 CK_C MEM_B_CS_L<0> MEM_B_CS_L<1> L3 CS0* L4 CS1* L8 G8 P8 D8 26 24 7 IN MEM_B_ODT<0> 243 1% 1/20W MF 201 2 R2601 1 243 1% 1/20W MF 201 2 C2640 1 1 0.047UF 109 24 109 24 PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_B NC NC NC NC NC NC NC NC NC NC NC NC C2641 B A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13 NC NC NC 109 25 24 23 22 C4 K9 R3 C2600 0.1UF 25 24 23 22 C2620 1.0UF 20% 2 10V X5R-CERM 0201-1 25 24 23 22 NU DQS0_T DQS1_T DQS2_T DQS3_T L10 G10 P10 D10 MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<4> MEM_B_DQS_P<7> 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 BI 112 116 116 109 109 109 116 109 25 24 23 22 25 24 23 22 25 24 23 22 25 24 23 22 NC 1 C2601 0.1UF 1 C2602 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2603 1.0UF 20% 10V 2 X5R-CERM 0201-1 1 C2604 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2605 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2606 10UF 20% 2 4V X6S-CERM 0402-2 1 C2607 10UF 20% 2 4V X6S-CERM 0402-2 PP1V8_S3_MEM PP1V2_S3 PP1V2_S3 PP1V2_S3 A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9 F2 G2 H3 L2 M2 A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11 (2 OF 2) VDD1 OMIT_TABLE VSS CRITICAL VDD2 VSSCA VDDCA VSSQ VDDQ B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2 C C3 D3 F4 G3 G4 P3 M4 J4 B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12 B PP1V2_S3 1 109 MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<4> MEM_B_DQS_N<7> DM0 DM1 DM2 DM3 10% 2 16V X5R-CERM 0201 10% 2 16V X5R-CERM 0201 109 L11 G11 P11 D11 CRITICAL BI PP1V2_S3 1 116 DQS0_C DQS1_C DQS2_C DQS3_C OMIT_TABLE H4 VREFCA J11 VREFDQ 10% 2 6.3V X5R 201 116 MEM_B_DQ<47> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<44> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<48> MEM_B_DQ<53> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<49> MEM_B_DQ<38> MEM_B_DQ<34> MEM_B_DQ<39> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<35> MEM_B_DQ<62> MEM_B_DQ<59> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<63> MEM_B_DQ<58> MEM_B_DQ<60> MEM_B_DQ<61> B3 ZQ0 B4 ZQ1 0.047UF 10% 6.3V 2 X5R 201 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 J8 ODT MEM_B_ZQ<2> MEM_B_ZQ<3> R2600 1 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 A3 A4 A5 A6 A10 U3 U4 U5 U6 U10 EDFA232A1MA-GD-F 26 7 FBGA P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8 (1 OF 2) EDFA232A1MA-GD-F 113 R2 P2 N2 N3 M3 F3 E3 E2 D2 C2 1 C2621 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2622 1.0UF 20% 2 10V X5R-CERM 0201-1 1 C2623 10UF 20% 2 4V X6S-CERM 0402-2 1 C2624 10UF 20% 2 4V X6S-CERM 0402-2 PP1V2_S3 1 C2610 1.0UF A 20% 2 10V X5R-CERM 0201-1 1 C2611 1 1.0UF PLACEMENT_NOTE: C2612 10UF 20% 2 10V X5R-CERM 0201-1 10uF caps are shared between DRAM. Distribute evenly. 20% 2 4V X6S-CERM 0402-2 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE LPDDR3 DRAM Channel B (32-63) DRAWING NUMBER 116 109 25 24 23 22 PP1V8_S3_MEM Apple Inc. 1 C2630 1.0UF 1 C2631 1.0UF 20% 10V 2 X5R-CERM 0201-1 20% 2 10V X5R-CERM 0201-1 1 C2632 10UF 20% 2 4V X6S-CERM 0402-2 1 C2633 051-00647 REVISION R 10UF 20% 2 4V X6S-CERM 0402-2 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 26 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DRAM WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 25 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK D 116 113 22 7 113 22 7 IN 113 22 7 IN 113 22 7 IN 113 22 7 IN 113 22 7 IN 113 22 7 22 7 IN IN 22 7 IN 113 22 7 IN 113 22 7 IN 113 22 7 IN 113 22 7 IN 113 22 7 IN 113 23 7 IN 113 23 7 IN 113 23 7 IN 113 23 7 IN 113 C IN 23 7 IN 113 23 7 IN 113 23 7 IN 23 7 IN 23 7 IN 23 7 IN 113 113 23 7 IN 113 23 7 IN 113 23 7 IN 113 23 7 IN 23 22 7 IN 23 22 7 IN 23 22 7 IN MEM_A_CAA<9> MEM_A_CAA<8> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<5> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CKE<1> MEM_A_CKE<0> MEM_A_CAA<4> MEM_A_CAA<3> MEM_A_CAA<2> MEM_A_CAA<1> MEM_A_CAA<0> MEM_A_CAB<9> MEM_A_CAB<8> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<5> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CKE<2> MEM_A_CKE<3> MEM_A_CAB<4> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<1> MEM_A_CAB<0> MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0> R2700 R2701 R2702 R2703 R2704 R2705 R2706 R2707 R2708 R2709 R2710 R2711 R2712 R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 R2721 R2722 R2723 R2724 R2725 R2726 R2727 R2728 R2729 R2730 68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39 39 82 82 68 68 68 68 68 82 82 82 109 PP0V6_S0_DDRVTT 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 116 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF 1 C2700 113 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2701 1 0.47UF C2703 1 0.47UF 1 20% 2 4V CERM-X5R-1 201 C2705 1 0.47UF 20% 2 4V CERM-X5R-1 201 C2707 1 0.47UF C2708 20% 2 4V CERM-X5R-1 201 1 C2709 C2721 12PF 0.47UF IN 113 24 7 IN 113 24 7 IN 113 24 7 IN 113 24 7 IN 24 7 IN IN 24 7 IN 113 24 7 IN 113 24 7 IN 113 24 7 IN 113 24 7 IN 113 24 7 IN 113 25 7 IN 113 25 7 IN 113 25 7 IN 113 25 7 IN 113 25 7 IN 113 25 7 IN 113 25 7 IN 25 7 IN 25 7 IN 25 7 IN 113 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2706 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2704 0.47UF 20% 2 4V CERM-X5R-1 201 24 7 24 7 20% 2 4V CERM-X5R-1 201 IN 113 113 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2702 24 7 113 25 7 IN 113 25 7 IN 113 25 7 IN 113 25 7 IN 25 24 7 IN 25 24 7 IN 25 24 7 IN MEM_B_CAA<9> MEM_B_CAA<8> MEM_B_CAA<7> MEM_B_CAA<6> MEM_B_CAA<5> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CKE<1> MEM_B_CKE<0> MEM_B_CAA<4> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<1> MEM_B_CAA<0> MEM_B_CAB<9> MEM_B_CAB<8> MEM_B_CAB<7> MEM_B_CAB<6> MEM_B_CAB<5> MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<2> MEM_B_CKE<3> MEM_B_CAB<4> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<1> MEM_B_CAB<0> MEM_B_CS_L<0> MEM_B_CS_L<1> MEM_B_ODT<0> 5% 2 25V NP0-C0G 0201 20% 2 4V CERM-X5R-1 201 R2740 R2741 R2742 R2743 R2744 R2745 R2746 R2747 R2748 R2749 R2750 R2751 R2752 R2753 R2754 R2755 R2756 R2757 R2758 R2759 R2760 R2761 R2762 R2763 R2764 R2765 R2766 R2767 R2768 R2769 R2770 68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39 39 82 82 68 68 68 68 68 82 82 82 109 D PP0V6_S0_DDRVTT 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF C2710 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2711 1 0.47UF 1 20% 2 4V CERM-X5R-1 201 C2713 1 0.47UF 20% 2 4V CERM-X5R-1 201 C2715 1 0.47UF 20% 2 4V CERM-X5R-1 201 C2717 1 0.47UF C C2718 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2716 0.47UF 20% 4V 2 CERM-X5R-1 201 1 C2714 0.47UF 20% 2 4V CERM-X5R-1 201 1 C2712 0.47UF 20% 4V 2 CERM-X5R-1 201 20% 2 4V CERM-X5R-1 201 C2719 1 0.47UF C2741 12PF 20% 2 4V CERM-X5R-1 201 5% 2 25V NP0-C0G 0201 CRITICAL CRITICAL 1 1 1 C2720 C2740 22UF 22UF 20% 2 6.3V X5R-CERM-1 603 20% 6.3V 2 X5R-CERM-1 603 B B A SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 LPDDR3 DRAM Termination DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DRAM WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 27 OF 145 26 OF 121 SIZE D A 7 6 PP3V3_UPC_XB_LDO 10% 2 6.3V CERM 402 5% 1/20W MF 201 2 113 29 IN 113 29 IN PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0> U2890 8MBIT-3.0V CLK USON 29 TBT_X_SPI_CS_L 1 CS* 27 TBT_X_ROM_WP_L 3 WP*(IO2) 7 HOLD*(IO3) TBT_X_ROM_HOLD_L DI(IO0) 5 DO(IO1) 2 TBT_X_SPI_MOSI TBT_X_SPI_MISO 29 OMIT_TABLE CRITICAL 29 IN 113 29 IN 113 29 IN 113 29 IN 113 29 IN 113 29 IN 10K PU ON CLOCKS PAGE 12 IN 12 IN 20 OUT SNK0 AC Coupling 113 99 C2820 DP_X_SNK0_ML_C_P<0> IN 113 99 C2821 DP_X_SNK0_ML_C_N<0> IN 99 IN DP_X_SNK0_ML_C_P<1> 99 IN DP_X_SNK0_ML_C_N<1> C 99 99 99 IN DP_X_SNK0_ML_C_P<3> IN DP_X_SNK0_ML_C_N<3> 99 C2826 1 C2827 1 0.1UF GND_VOID=TRUE 113 0.1UF GND_VOID=TRUE 113 99 BI C2828 DP_X_SNK0_AUXCH_C_P 99 BI 1 0.1UF GND_VOID=TRUE 113 1 0.1UF GND_VOID=TRUE 113 1 C2825 DP_X_SNK0_ML_C_N<2> IN 1 0.1UF GND_VOID=TRUE 113 C2823 C2824 DP_X_SNK0_ML_C_P<2> IN 1 0.1UF GND_VOID=TRUE 113 C2822 0.1UF GND_VOID=TRUE 113 1 0.1UF GND_VOID=TRUE 113 1 0.1UF GND_VOID=TRUE C2829 DP_X_SNK0_AUXCH_C_N 1 0.1UF 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_X_SNK0_ML_P<0> 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_X_SNK0_ML_P<1> 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_X_SNK0_ML_P<2> 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 0201 DP_X_SNK0_ML_N<0> 0201 0201 DP_X_SNK0_ML_N<1> 0201 0201 DP_X_SNK0_ML_N<2> 0201 27 113 DP_X_SNK1_ML_C_P<0> IN GND_VOID=TRUE 113 99 DP_X_SNK1_ML_C_N<0> IN GND_VOID=TRUE 113 99 DP_X_SNK1_ML_C_P<1> IN GND_VOID=TRUE B 113 99 DP_X_SNK1_ML_C_N<1> IN C2830 113 99 DP_X_SNK1_ML_C_P<2> IN GND_VOID=TRUE 113 99 DP_X_SNK1_ML_C_N<2> IN 0.1UF 99 DP_X_SNK1_ML_C_P<3> IN GND_VOID=TRUE 113 99 DP_X_SNK1_ML_C_N<3> IN C2832 99 BI DP_X_SNK1_AUXCH_C_P GND_VOID=TRUE 113 99 BI DP_X_SNK1_AUXCH_C_N 1 0.1UF C2833 1 0.1UF C2834 1 0.1UF C2835 1 0.1UF C2836 1 C2837 1 0.1UF 0.1UF GND_VOID=TRUE 113 1 0.1UF GND_VOID=TRUE 113 1 C2831 GND_VOID=TRUE A 1 1 1 100K 1M 1M 1 1M 1 1M 2 2 5% 5% 2 5% 2 5% 2 5% 2 5% R2862 1/20W MF R2872 1/20W MF 201 201 R2860 C2838 1 C2839 1 0.1UF 0.1UF 89 29 27 113 1/20W MF 201 R2861 1/20W MF 201 TBT_XA_LSRX 100K DP_X_SNK0_ML_P<3> 27 113 DP_X_SNK0_ML_N<3> 27 113 0201 0201 DP_X_SNK0_AUXCH_P 0201 DP_X_SNK0_AUXCH_N 0201 5% 1/20W MF 201 2 V19 T19 AC5 PCIE_REFCLK_100_IN_P PCIE_REFCLK_100_IN_N PCIE_CLKREQ* FCBGA PCIE_RX1_P PCIE_RX1_N PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_C_N<0> OUT 29 113 OUT 29 113 PCIE_TX1_P PCIE_TX1_N P23 P22 PCIE_TBT_X_D2R_C_P<1> PCIE_TBT_X_D2R_C_N<1> OUT 29 113 OMIT_TABLE OUT 29 113 PCIE_TX2_P PCIE_TX2_N K23 K22 PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_C_N<2> OUT 29 113 OUT 29 113 PCIE_TX3_P PCIE_TX3_N F23 F22 PCIE_TBT_X_D2R_C_P<3> PCIE_TBT_X_D2R_C_N<3> OUT 29 113 OUT 29 113 D 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 89 29 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 0201 DP_X_SNK1_ML_N<0> 0201 DP_X_SNK1_ML_P<1> 0201 DP_X_SNK1_ML_N<1> 0201 113 27 113 27 113 27 113 27 113 27 113 27 113 27 113 27 IN 29 BI DP_X_SNK1_ML_P<2> 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_X_SNK1_ML_P<3> 0201 DP_X_SNK1_ML_N<2> 0201 0201 DP_X_SNK1_ML_N<3> 0201 DP_X_SNK1_AUXCH_P 0201 DP_X_SNK1_AUXCH_N 0201 AB7 AC7 DPSNK0_ML0_P DPSNK0_ML0_N DP_X_SNK0_ML_P<1> DP_X_SNK0_ML_N<1> AB9 AC9 DPSNK0_ML1_P DPSNK0_ML1_N DP_X_SNK0_ML_P<2> DP_X_SNK0_ML_N<2> AB11 AC11 DPSNK0_ML2_P DPSNK0_ML2_N DP_X_SNK0_ML_P<3> DP_X_SNK0_ML_N<3> AB13 AC13 DPSNK0_ML3_P DPSNK0_ML3_N DP_X_SNK0_AUXCH_P DP_X_SNK0_AUXCH_N Y11 W11 DP_X_SNK0_HPD AA2 DP_X_SNK0_DDC_CLK DP_X_SNK0_DDC_DATA 113 27 113 27 113 27 113 27 27 113 27 113 27 OUT 113 27 1 113 27 113 27 Y5 R4 29 DP_X_SNK1_ML_P<1> DP_X_SNK1_ML_N<1> AB17 AC17 DPSNK1_ML1_P DPSNK1_ML1_N DP_X_SNK1_ML_P<2> DP_X_SNK1_ML_N<2> AB19 AC19 DPSNK1_ML2_P DPSNK1_ML2_N DP_X_SNK1_ML_P<3> DP_X_SNK1_ML_N<3> AB21 AC21 DPSNK1_ML3_P DPSNK1_ML3_N 27 113 29 2 27 113 BI 1% 201 MF 1/20W 101 29 IN 29 15 IN 101 29 IN 101 29 OUT 27 113 2 27 113 4.75K 1/20W 0.5% 0201 R2855 PLACE_NEAR=U2800.H6:2MM 27 113 GND_VOID=TRUE 27 113 113 30 30 BI BI 2 DP_XA_AUXCH_P 0201 16V 10% X5R-CERM 1 DP_XA_AUXCH_N 1 0201 C2810 2 16V 10% X5R-CERM PLACE_NEAR=U2800.H19:6MM Y4 V4 T4 W4 TBT_X_RBIAS TBT_X_RSENSE H6 J6 R2854 OUT 29 DPSRC_ML2_P DPSRC_ML2_N L2 L1 NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_N<2> OUT 29 OUT 29 DPSRC_ML3_P DPSRC_ML3_N J2 J1 NC_DP_X_SRC_ML_P<3> NC_DP_X_SRC_ML_N<3> OUT 29 OUT 29 DPSRC_AUX_P DPSRC_AUX_N W19 Y19 NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N OUT 29 OUT 29 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6 TEST_PWR_GOOD TDI TMS TCK TDO MISC RBIAS RSENSE G1 DP_X_SRC_HPD DP_X_SRC_RBIAS U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1 I2C_TBT_X_SDA I2C_TBT_X_SCL TBT_X_ROM_WP_L 27 TBT_X_TMU_CLK_OUT SMC_PME_S4_DARK_L TBT_X_CIO_PLUG_EVENT_L TBT_X_HDMI_DDC_DATA TBT_X_HDMI_DDC_CLK TBT_X_TMU_CLK_IN I2C_TBT_XA_INT_L I2C_TBT_XB_INT_L TBT_X_USB_PWR_EN TBT_X_FORCE_PWR PM_BATLOW_L PM_SLP_S3_L TBT_X_CIO_PWR_EN E1 TBT_X_TEST_EN AB5 TBT_X_TEST_PWR_GOOD F4 USBC_X_RESET_L D22 D23 TBT_X_XTAL25M_IN TBT_X_XTAL25M_OUT EE_DI EE_DO EE_CS* EE_CLK AB3 AC4 AC3 AB4 UPC_X_SPI_MOSI UPC_X_SPI_MISO UPC_X_SPI_CS_L UPC_X_SPI_CLK A9 B9 USBC_XA_R2D_C_P<1> USBC_XA_R2D_C_N<1> A19 B19 PA_TX0_P PA_TX0_N PB_TX0_P PB_TX0_N USBC_XA_D2R_P<1> USBC_XA_D2R_N<1> B21 A21 PA_RX0_P PA_RX0_N PB_RX0_P PB_RX0_N DP_XA_AUXCH_C_P 113 DP_XA_AUXCH_C_N Y15 W15 PA_DPSRC_AUX_P PA_DPSRC_AUX_N USB_UPC_XA_P USB_UPC_XA_N E20 D20 PA_USB2_D_P PA_USB2_D_N 113 32 OUT 113 32 OUT 113 32 OUT 113 32 IN 113 32 IN 29 BI 29 BI OUT IN 30 29 27 IN TBT_XA_LSTX TBT_XA_LSRX DP_XA_HPD TBTTHMSNS_X_D1_P NC PB_USB2_D_P PB_USB2_D_N V18 PCIE_ATEST AC1 TEST_EDM L15 N15 FUSE_VQPS_64 FUSE_VQPS_128 DEBUG OUT OUT 29 BI IN 103 IN IN 29 IN 12 20 46 70 73 76 89 101 IN 29 PU 30 31 IN 29 33 IN 29 113 OUT 29 113 29 27 33 R2837 29 5% 1/20W MF 2 201 29 not used 1 114 1 at PCH R2827 100K R2825 5% 1/20W MF 2 201 100 R2829 5% 1/20W MF 2 201 100 5% 1/20W MF 2 201 B 29 To SPI Flash 29 29 32 113 OUT A13 B13 USBC_XB_D2R_P<1> USBC_XB_D2R_N<1> Y16 W16 DP_XB_AUXCH_C_P DP_XB_AUXCH_C_N E19 D19 USB_UPC_XB_P USB_UPC_XB_N TBT_XB_LSTX TBT_XB_LSRX DP_XB_HPD TBT_XB_USB2_RBIAS IN 32 113 IN 32 113 GND_VOID=TRUE C2812 1 2 DP_XB_AUXCH_P 10% 16V 0201 X5R-CERM C2813 1 2 DP_XB_AUXCH_N 10% 16V 0201 X5R-CERM 0.1UF BI 29 BI 29 OUT 27 31 IN 27 31 IN 27 31 0.1UF BI 31 113 BI 31 113 GND_VOID=TRUE PLACE_NEAR=U2800.F19:5MM D6 W13 W18 29 29 32 113 MONDC_DPSNK_0 MONDC_DPSNK_1 C PU at PCH 1 OUT E18 1 IN 29 30 31 USBC_XB_R2D_C_P<1> USBC_XB_R2D_C_N<1> USB2_ATEST 2.2K 2.2K 5% 1/20W MF 2 201 IN A11 B11 ATEST_P ATEST_N R2836 2.2K 91 91 32 113 A23 B23 R2835 103 1 OUT OUT F19 MF 201 2 1 27 33 5% 1/20W MF 2 201 5% 1/20W MF 2 201 PP3V3_S5_TBT_X_SW 29 29 101 32 113 PB_USB2_RBIAS 2.2K 14K OUT OUT PA_USB2_RBIAS R2834 BI USBC_XB_R2D_C_P<2> USBC_XB_R2D_C_N<2> H19 1 BI 32 113 PB_LSTX PB_LSRX PB_DPSRC_HPD 1/20W 1% IN PA_LSTX PA_LSRX PA_DPSRC_HPD MONDC_SVR 1 32 113 B4 B5 G2 THERMDA THERMDA PLACE_NEAR= U2800.N6:2MM IN A5 A4 M4 AC23 AB23 USE NEAREST GND BALL (AC22) FOR THERM_D_N 113 PB_DPSRC_AUX_P 113 PB_DPSRC_AUX_N PP3V3_S5_TBT_X_SW R2852 N6 XTAL_25_IN XTAL_25_OUT 3.01K 2 1% 1/20W MF 201 29 PB_TX1_P PB_TX1_N 30 27 499 29 PA_TX1_P PA_TX1_N OUT OUT OUT A17 B17 32 54 NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_N<1> USBC_XA_R2D_C_P<2> USBC_XA_R2D_C_N<2> 113 113 1 N2 N1 USBC_XB_D2R_P<2> USBC_XB_D2R_N<2> IN GND_VOID=TRUE DPSRC_ML1_P DPSRC_ML1_N B7 A7 32 C2811 29 PB_RX1_P PB_RX1_N 113 0.1UF OUT PA_RX1_P PA_RX1_N IN 0.1UF 29 A15 B15 32 27 113 JTAG_TBT_TDI JTAG_TBT_X_TMS JTAG_TBT_TCK JTAG_ISP_TDO 1 OUT TEST_EN DPSNK_RBIAS TBT_X_PCIE_BIAS NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_N<0> DPSRC_RBIAS DPSNK1_DDC_CLK DPSNK1_DDC_DATA N16 R2851 20 29 IN DPSRC_ML0_P DPSRC_ML0_N DPSRC_HPD DPSNK1_HPD TBT_X_PCI_RESET_L USBC_XA_D2R_P<2> USBC_XA_D2R_N<2> 113 PLACE_NEAR=U2800.J6:2MM 27 113 DPSNK1_AUX_P DPSNK1_AUX_N L4 R2 R1 RESET* 27 113 1 Y8 N4 Y18 PLACE_NEAR=U2800.Y18:2MM R2850 27 113 Y6 DP_X_SNK_RBIAS 1 14K TF Y12 W12 PCIE_RBIAS DPSNK0_DDC_CLK DPSNK0_DDC_DATA DPSNK1_ML0_P DPSNK1_ML0_N DP_X_SNK1_AUXCH_P DP_X_SNK1_AUXCH_N PERST* DPSNK0_HPD AB15 AC15 DP_X_SNK1_DDC_CLK DP_X_SNK1_DDC_DATA IN DPSNK0_AUX_P DPSNK0_AUX_N DP_X_SNK1_ML_P<0> DP_X_SNK1_ML_N<0> DP_X_SNK1_HPD 103 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 27 29 5% 1/20W MF 201 2 DP_X_SNK1_ML_P<0> 113 PLACE_NEAR=U2800.N16:2MM DP_X_SNK0_ML_P<0> DP_X_SNK0_ML_N<0> 27 113 27 30 1 NC NC NC R2853 499 1% 1/20W MF 2 201 LAST_MODIFIED=Wed Aug 24 09:57:49 2016 DRAWING SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE USB-C HIGH SPEED 1 DRAWING NUMBER Apple Inc. 051-00647 REVISION R R2871 TBT_XB_LSRX 27 31 MF 201 PCIE_CLK100M_TBT_X_P PCIE_CLK100M_TBT_X_N TBT_X_CLKREQ_L 27 30 27 31 1/20W PCIE_RX3_P PCIE_RX3_N 27 113 1% 1/20W MF 201 2 TBT_XB_LSTX MF 201 H23 H22 27 113 27 31 R2870 1/20W PCIE_TBT_X_R2D_P<3> PCIE_TBT_X_R2D_N<3> OUT R28301 27 29 30 DP_XB_HPD V23 V22 CRITICAL TBT_XA_USB2_RBIAS DP_XA_HPD TBT_XA_LSTX PCIE_RX2_P PCIE_RX2_N 113 30 27 100K M23 M22 27 113 113 1 PCIE_TBT_X_R2D_P<2> PCIE_TBT_X_R2D_N<2> 27 113 SNK1 AC Coupling 99 T23 T22 27 113 100K 113 PCIE_TBT_X_R2D_P<1> PCIE_TBT_X_R2D_N<1> 27 113 R2831 GND_VOID=TRUE TBT-AR-4C-CNTRL PCIE_TX0_P PCIE_TX0_N 9 4 113 29 GND EPAD GND_VOID=TRUE U2800 SOURCE PORT 0 29 PCIE_RX0_P PCIE_RX0_N LC GPIO D W25Q80DVUXIE 6 1 SYM 1 OF 2 VCC TBT_X_SPI_CLK Y23 Y22 POC GPIO 5% 1/20W MF 2 201 PORT B 5% 1/20W MF 2 201 1UF 3.3K TBT PORTS 3.3K 3.3K 2 C2890 SINK PORT 0 R2890 5% 1/20W MF 201 2 R2892 SINK PORT 1 3.3K R2893 3 29 1 1 4 PORT A 1 1 8 R2891 1 5 PCIE GEN3 8 C23 C22 MONDC_CIO_0 MONDC_CIO_1 MONDC_DPSRC AB2 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=TBT WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 28 OF 145 27 OF 121 SIZE D A 6 SOURCED BY INTERNAL SWITCH 1 C2930 1.0UF 20% 2 6.3V X5R 0201-1 1 C2931 1 1.0UF C2932 1 1.0UF 20% 2 6.3V X5R 0201-1 C2933 1 1.0UF 20% 2 6.3V X5R 0201-1 C2934 1 1.0UF 20% 2 6.3V X5R 0201-1 PP0V9_TBT_X_DP C2935 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V C2936 1 1.0UF 20% 2 6.3V X5R 0201-1 5 1.0UF 20% 2 6.3V X5R 0201-1 20% 2 6.3V X5R 0201-1 SOURCED BY INTERNAL SWITCH D 29 1 C2964 1.0UF 20% 2 6.3V X5R 0201-1 1 C2965 1.0UF 20% 2 6.3V X5R 0201-1 1 C2966 1 1.0UF C2984 1.0UF 20% 2 6.3V X5R 0201-1 1 C2985 1.0UF 1.0UF 20% 2 6.3V X5R 0201-1 20% 2 6.3V X5R 0201-1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V 1.0UF 20% 6.3V 2 X5R 0201-1 C2946 1 1.0UF 20% 6.3V 2 X5R 0201-1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V 29 PP0V9_TBT_X_CIO PP3V3_TBT_X_ANA_PCIE PP3V3_TBT_X_ANA_USB2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 1 1 PP0V9_TBT_X_USB SOURCED BY INTERNAL SWITCH MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V C2945 29 SOURCED BY INTERNAL SWITCH 20% 2 6.3V X5R 0201-1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V C2967 SOURCED BY INTERNAL SWITCH 1 PP0V9_TBT_X_PCIE C2947 1.0UF 1 20% 6.3V 2 X5R 0201-1 C2920 1.0UF 20% 2 6.3V X5R 0201-1 1 C2921 1.0UF 20% 2 6.3V X5R 0201-1 SOURCED BY INTERNAL SWITCH C B A WWW.AliSaler.Com 8 7 6 L8 L11 L12 M8 T11 T12 L6 M6 V11 V12 V13 VCC0P9_DP VCC0P9_DP TBT-AR-4C-CNTRL VCC0P9_DP VCC0P9_DP SYM 2 OF 2 FCBGA VCC0P9_DP OMIT_TABLE VCC0P9_DP CRITICAL VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK U2800 M13 M15 M16 L19 N19 L18 M18 N18 VCC0P9_PCIE VCC0P9_PCIE VCC0P9_PCIE VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 R15 R16 VCC0P9_USB VCC0P9_USB R8 R9 R11 R12 VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO L16 J16 A6 A8 A10 A12 A14 A16 A18 A20 A22 B6 B8 B10 B12 B14 B16 B18 B20 B22 D8 D9 D11 D12 D13 D15 D16 D18 E8 E9 E11 E15 E16 E22 E23 F9 F20 F16 G22 G23 H1 H2 H12 H13 H15 H16 H20 J5 J19 J20 J18 J22 J23 K1 K2 L5 L20 L22 L23 M1 M2 M5 M19 M20 N5 N20 N22 N23 P1 P2 R5 R18 R19 R20 R22 4 VCC3P3_LC R6 VCC3P3_SX F8 VCC3P3_S0 R13 VCC3P3A VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR VCC0P9_SVR VCC0P9_SVR VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_SENSE VCC 7 VCC3P3_ANA_PCIE VCC3P3_ANA_USB2 VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA 5 2 1 PP3V3_TBT_X_LC 29 PP3V3_S5_TBT_X_SW PP3V3_TBT_X_F 1 A2 A3 B3 L9 M9 E12 E13 F11 F12 F13 F15 J9 SVR_VSS SVR_VSS SVR_VSS A1 B1 B2 F18 H18 J11 H11 R23 T1 T2 T5 T20 U23 U22 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 M11 1 VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 H9 SVR_IND SVR_IND SVR_IND VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 29 33 C1 C2 D1 VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR_SENSE GND 8 C2991 C2990 C2994 1.0UF 1.0UF 47UF 20% 6.3V 2 X5R 0201-1 20% 2 6.3V X5R 0201-1 C2995 1 1 L2990 1.0UH-20%-2.1A-0.128OHM 1 C2981 20% 2 6.3V X5R 0201-1 20% 6.3V CER-X5R 2 0603 20% 6.3V CER-X5R 2 0603 PP3V3_TBT_X_S0 1 C2975 C2976 1 10UF 1 10UF 1 10UF 20% 20% 6.3V 2 6.3V 2 CERM-X5R CERM-X5R 0402-4 0402-4 BYPASS=U2800.A2:A1:3MM 116 C2977 10% 2 16V X5R-CERM 0201 1.0UF CRITICAL 47UF C2980 0.1UF FROM USB-C PORT CONTROLLER (UPC) 2 0603 1 1 SOURCED BY INTERNAL SWITCH MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 29 110 116 D C2978 10UF 20% 2 6.3V CERM-X5R 0402-4 20% 6.3V 2 CERM-X5R 0402-4 PP0V9_TBT_X_SVR MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V 1 CRITICAL L2950 VR0V9_IND_TBT_X 1 1 1 C2911 1.0UF 20% 2 6.3V X5R 0201-1 5% 2 25V NP0-C0G 0201 2 C2910 1.0UF 12PF 0.68UH-20%-6.1A-0.020OHM DIDT=TRUE SWITCH_NODE=TRUE C2917 20% 2 6.3V X5R 0201-1 1 C2912 1.0UF 20% 2 6.3V X5R 0201-1 1 C2913 1.0UF 20% 2 6.3V X5R 0201-1 C2914 1 1.0UF 20% 2 6.3V X5R 0201-1 1 C2915 1.0UF 20% 2 6.3V X5R 0201-1 1 C2916 1.0UF 20% 2 6.3V X5R 0201-1 1210 1 C2950 47UF PP0V9_TBT_X_LVR 20% 2 6.3V CER-X5R 0603 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V 1 C2951 47UF 20% 2 6.3V CER-X5R 0603 1 C2952 INTERNAL SWITCHING VR OUTPUT 47UF 20% 6.3V 2 CER-X5R 0603 SOURCED BY INTERNAL SWITCH C2992 C2993 1 1.0UF 1 1.0UF 20% 6.3V 2 X5R 0201-1 20% 6.3V 2 X5R 0201-1 C2954 C2955 1 10UF 1 10UF 20% 6.3V 2 CERM-X5R 0402-4 C 20% 6.3V 2 CERM-X5R 0402-4 2x 10uF outside BGA area Add XW or alias on support page XW ISOLATE GND OF SVR_IND CAPS AND GND OF VCC3P3_SVR CAPS FROM SYSTEM GND IN LAYOUT (SEE INTEL LAYOUT GUIDELINES) P0V9_TBT_X_SVR_AGND 29 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=0V XW2900 SM 1 2 TBTTHMSNS_X_D1_N OUT B 54 PLACE_NEAR=U2800.AC22:2MM NO_XNET_CONNECTION=1 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE USB-C HIGH SPEED 2 DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=TBT 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 29 OF 145 28 OF 121 SIZE D A 8 7 TMU CLKs OMIT MAKE_BASE=TRUE R3025 5% 1/20W TBT_X_TMU_CLK_OUT 27 6 MAKE_BASE=TRUE TBT_X_TMU_CLK_OUT MF 15 1 201 TBT_T_TMU_CLK_IN TBT_T_TMU_CLK_IN R3026 100K 2 PLACE_NEAR=U2800.V2:5mm 1 5% MF R3089 ACE Debug Support 101 30 29 UPC_X_5V_EN R3032 5% 1/20W MF Ridge PDs PP3V3_G3H 109 1 201 100K R3038 2 D 10K 1 SMC_USBC_INT_L 5% 1/20W MF 201 DP_X_SRC_HPD 1M 1 27 27 27 27 NC_DP_X_SRC_ML_P<3..0> NC_DP_X_SRC_ML_N<3..0> NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N 104 NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N 103 31 30 105 31 30 2 30 5% 1/20W MF 201 27 DP_X_SNK1_DDC_CLK 1 MAKE_BASE=TRUE 100K 30 30 30 2 30 5% 1/20W MF 201 DP_X_SNK1_DDC_CLK 31 30 R3070 27 MAKE_BASE=TRUE DP_X_SNK1_DDC_DATA 1 100K DP_X_SNK1_DDC_DATA F3000 29 27 6AMP-32V-0.0095OHM 1 2 PP20V_USBC_XA_VBUS_F PP20V_USBC_XA_VBUS 30 29 89 27 30 89 27 30 27 PLACE_NEAR=Q3200:5MM CRITICAL 0603 31 30 29 740S0135 28 31 29 13 TBT_X_CIO_PLUG_EVENT_L DP_X_SNK0_HPD DP_X_SNK1_HPD DP_XA_HPD TBT_POC_RESET PP3V3_TBT_X_LC TBT_X_XTAL25M_OUT 1 R3006 4 USBC_DBG 2 29 27 25MHZ-25PPM-20PF-50OHM 29 C3003 2.00X1.60-SM 29 20PF TBT_X_XTAL25M_IN 1 103 46 29 2 29 31 30 5% 25V C0G 0201 27 B 27 R3094 R3095 R3096 R3097 R3098 R3090 R3091 R3092 R3093 TBT_X_SPI_CLK TBT_X_SPI_CS_L 27 TBT_X_SPI_MOSI 27 TBT_X_SPI_MISO ROM I2C_TBT_XB_INT_L I2C_UPC_X_SCL2 I2C_UPC_X_SDA2 SMC_USBC_INT_L TBT_X_SPI_CLK_DBG UPC_XA_UART_TX USBC DEBUG CONN 1 2 1 15 2 1 15 1 2 3 4 5 6 7 8 9 10 11 12 1 1 15 15 1 15 1 15 1 15 1 15 TBT_X_SPI_CLK_DBG 29 1/20W MF 201 5% 1/20W MF 201 IN 5% 1/20W MF 201 IN 31 UPC_XB_SPI_MOSI 31 UPC_XB_SPI_MISO 31 2 UPC_XB_SPI_CLK 101 UPC_XB_SPI_CS_L 5% 1/20W MF 201 IN 5% 1/20W MF 201 OUT 2 2 5% 2 UPC_X_SPI_CLK 1/20W MF 201 UPC_X_SPI_CS_L IN 5% 1/20W MF 201 IN 5% 1/20W MF 201 IN 201 OUT 2 2 5% UPC_X_SPI_MOSI UPC_X_SPI_MISO 1/20W MF PP3V3_UPC_XB_LDO PP3V3_UPC_XB_LDO PP3V3_UPC_XB_LDO PP3V3_UPC_XA_LDO PP3V3_UPC_XA_LDO 31 30 30 30 29 31 29 A 105 104 103 116 PP20V_USBC_XA_VBUS PP20V_USBC_XB_VBUS PPDCIN_G3H 31 30 30 PP5V_S4_X_USBC 31 PP5V_S4_X_USBC 116 34 PP5V_S4_X_USBC 110 28 PP3V3_TBT_X_S0 I2C_UPC_X_SDA2 29 I2C_UPC_X_SDA2 30 I2C_UPC_X_SCL2 31 I2C_UPC_X_SCL2 MF 1 201 5% 1/20W 5% 5% R3084 0 R3082 2 5% 1 SMBUS_SMC_4_G3H_SDA SMBUS_SMC_4_G3H_SDA 2 201 49 49 PLACE_NEAR=U5000:5mm R3042 1 5% 1/20W MF 33 SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SCL 2 201 49 49 1/20W MF R3034 1/20W MF D 100K 1 2 201 NO_STUFF 1 201 100K RIDGE 0.9V SVR XW 2 1/20W 1 TBT_X_PCI_RESET_L USBC_X_RESET_L PP3V3_S5_TBT_X_SW PP0V9_TBT_X_PCIE PP0V9_TBT_X_USB PP0V9_TBT_X_CIO 20 27 31 2 R3085 0 0 1 USB_UPC_XB_P 31 28 2 USB_UPC_XB_N UPC_X_5V_EN TBT 27 R3086 0 1 5% MF USB2_UPC_XB_P 28 28 2 MAKE_BASE=TRUE 27 29 MAKE_BASE=TRUE 27 29 MAKE_BASE=TRUE 27 29 MAKE_BASE=TRUE 27 34 1 MAKE_BASE=TRUE 2 5% MF USB2_UPC_XB_N 103 J3000 104 101 103 30 30 U3200 (Write: 0x7E Read: 0x7F) 14 TBT_X_CIO_PWR_EN I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XB_INT_L 12 TBT_X_USB_PWR_EN PM_BATLOW_L C 31 31 31 12 MAKE_BASE=TRUE 12 46 103 MAKE_BASE=TRUE SMC_PME_S4_DARK_L SMC_PME_S4_DARK_L 31 30 105 USB_UPC_PCH_XB_N 30 Sec ACE 14 MAKE_BASE=TRUE SMC_PME_S4_DARK_L 27 I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L MAKE_BASE=TRUE TBT_X_USB_PWR_EN PM_BATLOW_L 27 I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L I2C_TBT_XB_INT_L 1/20W 0201 TBT_X_CIO_PWR_EN 31 30 27 29 USB_UPC_PCH_XB_P U3100 (Write: 0x70 Read: 0x71) 1/20W 0201 R3087 0 USB2_UPC_XB_N Pri ACE Alpine Ridge U2800 (MASTER) MAKE_BASE=TRUE MAKE_BASE=TRUE 2 TBT to ACE 27 5% 1/20W MF 0201 NOSTUFF MF 0201 USB2_UPC_XB_P 1 NO_XNET_CONNECTION=1 27 33 28 33 XW3000 SM P0V9_TBT_X_SVR_AGND 48 57 64 76 114 5% 1/20W MF 0201 NOSTUFF MF 0201 13 14 1 2 46 47 48 103 3 4 5 6 7 8 9 10 11 12 15 16 I2C_TBT_XA_INT_L I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_UPC_XA_DBG_CTL_SDA I2C_UPC_XA_DBG_CTL_SCL UPC_XA_UART_RX 27 29 29 27 UPC_X_SPI_CLK UPC_X_SPI_CLK 29 27 UPC_X_SPI_CS_L UPC_X_SPI_CS_L 29 27 UPC_X_SPI_MOSI UPC_X_SPI_MOSI 27 29 27 29 30 30 29 27 30 31 103 JTAG_TBT_TCK 27 31 Ace 101 JTAG_TBT_TDI 27 R3044 1 0 1 0 2 5% 2 5% JTAG_ISP_TCK 1/20W MF 0201 JTAG_ISP_TDI 1/20W MF 0201 103 TP_UPC_XA_SWD_DATA ? 30 15 31 AR 31 27 29 31 31 30 29 15 TP3001 1 TP TP3002 TP-P5 1 TP TP3003 TP-P5 1 TP TP3004 TP-P5 TP_UPC_XB_SWD_DATA TP_UPC_XB_SWD_CLK 27 29 UPC_X_SPI_MISO UPC_T_SPI_CLK UPC_T_SPI_CLK 103 101 UPC_T_SPI_MOSI UPC_T_SPI_MOSI 31 103 101 UPC_T_SPI_MISO UPC_T_SPI_MISO MAKE_BASE=TRUE IN SMC_USBC_INT_L IN SMC_USBC_INT_L 30 31 PP3V3_S4 1 R3079 0 2 5% MF PP3V3_UPC_XB_LDO 47 46 114 47 46 MAKE_BASE=TRUE PP3V3_UPC_XA_LDO 30 30 OUT 14 15 103 113 113 XDP_PCH_OBSDATA_C1 14 113 JTAG_TBT_T_TMS MAKE_BASE=TRUE PP3V3_S4 113 15 27 15 101 113 103 110 MOJO SMC_DEBUGPRT_TX_L SMC 31 SMC_DEBUGPRT_RX_L 113 PP20V_USBC_XA_VBUS MAKE_BASE=TRUE PP20V_USBC_XB_VBUS MAKE_BASE=TRUE PPDCIN_G3H PP5V_S4_X_USBC MAKE_BASE=TRUE MAKE_BASE=TRUE PP3V3_TBT_X_S0 DCI PCH USB3 32 14 OUT MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=20V 50 64 114 116 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 14 14 IN IN USB3_EXTA_R2D_C_P X5R-CERM 1 16V X5R-CERM USB3_EXTA_D2R_P USB3_EXTA_D2R_N MAKE_BASE=TRUE C3020 USB3_EXTA_R2D_P 2 10% 1 16V USB2_UPC_XA_P 30 USB2_UPC_XA_N MAKE_BASE=TRUE USB2_UPC_XA_N MAKE_BASE=TRUE 0201 PCIE_TBT_X_R2D_C_N<1> IN PCIE_TBT_X_R2D_C_P<2> IN PCIE_TBT_X_R2D_C_N<2> IN PCIE_TBT_X_R2D_C_P<3> 0201 X5R 6.3V GND_VOID=TRUE 111 0201 X5R 6.3V GND_VOID=TRUE 111 111 0201 X5R 6.3V GND_VOID=TRUE 0201 X5R 6.3V GND_VOID=TRUE 111 27 IN IN 27 IN 27 IN PCIE_TBT_X_R2D_C_N<3> 0201 27 27 IN IN USB3_EXTA_R2D_N 2 10% MAKE_BASE=TRUE 0201 R3076 0 1 2 5% MF 2 5% MF 0201 5 4 X5R 6.3V PCIE_TBT_X_D2R_C_N<0> 0201 X5R 6.3V PCIE_TBT_X_D2R_C_P<1> 0201 X5R 6.3V PCIE_TBT_X_D2R_C_N<1> 0201 X5R 6.3V PCIE_TBT_X_D2R_C_P<2> 0201 113 27 X5R 6.3V IN PCIE_TBT_X_D2R_C_N<2> IN PCIE_TBT_X_D2R_C_P<3> IN PCIE_TBT_X_D2R_C_N<3> 0201 USB3_EXTA_D2R_P USB3_EXTA_D2R_N 113 IN 30 IN 30 113 USB3_EXTA_R2D_P 27 27 0201 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 2 20% 1 0201 X5R X5R X5R 6.3V 2 20% 1 2 20% 1 6.3V 2 20% 1 6.3V C3040 PCIE_TBT_X_R2D_P<0> OUT 27 113 PCIE_TBT_X_R2D_N<0> OUT 27 113 PCIE_TBT_X_R2D_P<1> OUT 27 113 PCIE_TBT_X_R2D_N<1> OUT 27 113 PCIE_TBT_X_R2D_P<2> OUT 27 113 PCIE_TBT_X_R2D_N<2> OUT 27 113 PCIE_TBT_X_R2D_P<3> OUT 27 113 PCIE_TBT_X_R2D_N<3> OUT 27 113 0.22UF C3041 0.22UF C3042 0.22UF C3043 0.22UF C3044 0.22UF C3045 0.22UF C3046 0.22UF C3047 0.22UF C3050 0.22UF PCIE_TBT_X_D2R_P<0> C3051 0.22UF C3052 0.22UF C3053 0.22UF C3054 0.22UF C3055 0.22UF C3056 0.22UF C3057 PCIE_TBT_X_D2R_N<0> USB_UPC_PCH_XA_N 111 113 OUT 111 113 OUT 111 113 OUT 111 113 OUT 111 113 OUT 111 113 OUT 111 113 OUT 111 113 GND_VOID=TRUE PCIE_TBT_X_D2R_P<1> GND_VOID=TRUE PCIE_TBT_X_D2R_N<1> GND_VOID=TRUE PCIE_TBT_X_D2R_P<2> GND_VOID=TRUE PCIE_TBT_X_D2R_N<2> GND_VOID=TRUE PCIE_TBT_X_D2R_P<3> GND_VOID=TRUE PCIE_TBT_X_D2R_N<3> 0.22UF SYNC_DATE=08/08/2016 OUT USB-C Support 30 DRAWING NUMBER Apple Inc. USB_UPC_PCH_XA_P OUT GND_VOID=TRUE SYNC_MASTER=X363_AGOTETI USB3_EXTA_R2D_N 051-00647 REVISION R 14 14 1/20W 0201 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 3 B GND_VOID=TRUE 30 OUT BOM_COST_GROUP=TBT 6 6.3V PCIE_TBT_X_D2R_C_P<0> 1/20W 0201 R3077 0 1 X5R 1 PAGE TITLE C3021 0.1UF USB3_EXTA_R2D_C_N IN TP_USBC_XA_RESET_L 0.1UF 32 111 0201 X5R 6.3V GND_VOID=TRUE 2 20% 31 MAKE_BASE=TRUE TP_USBC_XA_RESET_L OUT PCIE_TBT_X_R2D_C_P<1> 114 113 14 IN 103 MAKE_BASE=TRUE MAKE_BASE=TRUE 111 0201 X5R 6.3V GND_VOID=TRUE 27 29 14 MAKE_BASE=TRUE SMC_DEBUGPRT_RX_L OUT PCIE_TBT_X_R2D_C_N<0> MAKE_BASE=TRUE MAKE_BASE=TRUE 31 29 46 103 XDP_PCH_OBSDATA_C0 JTAG_TBT_X_TMS SMC_DEBUGPRT_TX_L IN 111 113 1/20W 0201 1/20W 0201 OUT MAKE_BASE=TRUE 2 MAKE_BASE=TRUE 114 SMC_USBC_INT_L TBT_X_CIO_PLUG_EVENT_L 5% MF IN 0201 X5R 6.3V GND_VOID=TRUE 15 103 TBT_POC_RESET MAKE_BASE=TRUE JTAG_TBT_T_TMS PP3V3_S4 113 MAKE_BASE=TRUE R3078 0 JTAG_TBT_X_TMS 113 JTAG_ISP_TDO 1 IN MAKE_BASE=TRUE JTAG_ISP_TDO UPC_XB_FAULT_L IN 113 MAKE_BASE=TRUE TBT_POC_RESET TBT_X_CIO_PLUG_EVENT_L IN 113 MAKE_BASE=TRUE UPC_T_SPI_CS_L UPC_XA_FAULT_L 111 MAKE_BASE=TRUE IN TP-P5 30 MAKE_BASE=TRUE UPC_T_SPI_CS_L 27 113 PCIE_TBT_X_R2D_C_P<0> MAKE_BASE=TRUE 101 101 30 1 TP TP_UPC_XA_SWD_CLK 30 101 GND_VOID=TRUE MAKE_BASE=TRUE UPC_X_SPI_MISO 15 PLACE_NEAR=U1100.AK28:10mm 27 29 27 29 R3043 PLACE_NEAR=U1100.AJ29:10mm Ridge PCIE Caps MAKE_BASE=TRUE USB2_UPC_XA_P WWW.AliSaler.Com MF 2 R3081 10 MAKE_BASE=TRUE 7 1/20W I2C_UPC_X_SCL2 29 NO_STUFF R3033 SMC_RESET_L 0 UPC_X_5V_EN UPC_X_5V_EN 30 29 30 8 5% 33 MAKE_BASE=TRUE 31 32 SIGNAL ALIASES 16 RIDGE JTAG ISOLATION 5% 2 31 R3041 1 2 2 505070-1220 POWER ALIASES MAKE_BASE=TRUE 31 1/20W NOSTUFF 103 27 5% USB_UPC_XA_N 103 100 I2C_UPC_X_SDA2 M-ST-SM Y3000 2 AR/ACE SPI BUS SERIES R'S R3036 0 1 201 MF USB_UPC_XA_P 27 505070-1220 5% 25V C0G 0201 CRITICAL 2 5% 1/20W MF 201 1 201 MF 1M to/from Ridge OUT 1 5% 1/20W 3 NOSTUFF 1/20W NOSTUFF Place on bottom 20PF TBT_X_XTAL25M_OUT_R 2 5% UPC_XB_HPD_RX 31 29 ACE DEBUG CONN 1 IN R3035 UPC_XA_HPD_RX 30 29 31 C3002 30 28 14 15 25MHz xtal 0113 USBC_XB_CC2 UPC_XB_HPD_RX 31 29 31 30 27 R3007 MAKE_BASE=TRUE UPC_XA_HPD_RX 30 29 31 6AMP-32V-0.0095OHM 1 2 PP20V_USBC_XB_VBUS_F PP20V_USBC_XB_VBUS GND GND GND GND GND GND GND GND GND GND Place on bottom F3001 C MAKE_BASE=TRUE RIDGE DEBUG CONN USBC_DBG 31 32 MAKE_BASE=TRUE J3001 0603 USBC_XB_CC1 USBC_XB_CC2 M-ST-SM CRITICAL PLACE_NEAR=U5000:5mm ACE PDs 2 PLACE_NEAR=Q3100:5MM FUSES FOR UPC 31 30 32 27 5% 1/20W MF 201 MAKE_BASE=TRUE MAKE_BASE=TRUE USBC_XA_CC2 USBC_XB_CC1 GND ALIASES R3069 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 NC_DP_X_SRC_ML_P<3..0> NC_DP_X_SRC_ML_N<3..0> 1 MAKE_BASE=TRUE 2 5% 1/20W MF 201 IF DP SRC NOT USED DP_X_SNK0_DDC_DATA 100K 31 1 I2C SERIES R'S NC_UPC_XB_I2C_ADDR IN 2 5% 1/20W MF 201 DP_X_SNK0_DDC_DATA R3040 27 MAKE_BASE=TRUE 100K 2 MAKE_BASE=TRUE NC ALIASES / NO TEST 31 R3068 27 DP SRC OPTIONS 1 DP_X_SNK0_DDC_CLK 29 46 103 31 114 R3067 DP_X_SNK0_DDC_CLK 27 2 31 114 402 30 32 MAKE_BASE=TRUE USBC_XA_CC2 30 TP_UPC_XB_DBG_UART_RX ACE/SMC I2C PU USBC_XA_CC1 30 114 R3088 OMIT NOSTUFF 2 1 TP_UPC_XB_DBG_UART_TX 1/20W 201 MAKE_BASE=TRUE USBC_XA_CC1 30 UPC_XA_DBG_UART_RX 3 ACE B RPD STRAPPING 30 114 NONE NONE NONE 402 2 4 ACE A RPD STRAPPING NOSTUFF 2 1 UPC_XA_DBG_UART_TX NONE NONE NONE USBC 5V EN PD 5 1 30 OF 145 29 OF 121 SIZE D A 8 7 6 5 4 3 2 1 PRIMARY ACE USB-C PORT CONTROLLER (UPC) CRITICAL Q3100 FDPC4044 D D FUSE 29 PPDCIN_G3H PP20V_USBC_XA_VBUS C3101 GND 31 29 PP1V8_UPC_XA_LDOD PP1V1_UPC_XA_LDO_BMC 29 1M 1 1M 1 2 R3109 5% 2 1/20W 1/20W 29 30 I2C_UPC_XA_DBG_CTL_SDA 29 30 MF R3108 5% I2C_UPC_XA_DBG_CTL_SCL MF 201 201 TESTPOINTS MUST BE PRESENT FOR GPIO0, GPIO1 (EVEN IN PRODUCTION) USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR OUT 29 114 29 114 31 29 27 IN 31 29 27 IN USE GPIO3 FOR POWER_GATE_EN ON BANSURI DESIGNS 105 IN 29 27 OUT 29 104 103 29 OUT 31 29 OUT 29 OUT 29 IN GND I2C_ADDR PRIMARY ONLY CRITICAL R3103 1 30 29 15K 1 1M 2 5% R3105 1/20W MF UPC_XA_UART_RX 0.1% 1/20W TF-LF 0201 2 29 30 31 201 TO SMC B REAR PORT: CONNECT UPC SPI TO ROM FRONT PORT: GROUND UPC SPI 30 29 29 BI 29 BI 29 OUT 29 BI 29 BI 29 OUT 29 OUT 29 OUT 29 IN 29 OUT 29 29 31 30 29 L3000 31 29 90-OHM-0.1A EXCX4CE SYM_VER-1 29 29 USB2_UPC_XA_P BI 1 USB2_UPC_XA_N BI 4 2 IN OUT 27 IN 27 OUT 3 PLACE_NEAR=U3100:5mm PP3V3_S4 PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO NO_XNET_CONNECTION=1 A 1 R3110 100K 113 27 BI 113 27 BI BI 29 BI 29 BI 29 BI UPC_XA_DBG_UART_TX UPC_XA_DBG_UART_RX TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN DP_XA_HPD UPC_XA_HPD_RX UPC_X_5V_EN SMC_PME_S4_DARK_L UPC_XA_FAULT_L B2 C2 D10 G11 C10 E10 G10 D7 H6 GND GND UPC_XA_R_OSC PRIMARY ONLY PRIMARY ONLY D1 I2C_SDA1 D2 I2C_SCL1 C1 I2C_IRQ1* I2C_UPC_X_SDA2 I2C_UPC_X_SCL2 SMC_USBC_INT_L A5 I2C_SDA2 B5 I2C_SCL2 B6 I2C_IRQ2* GND GND GND GND A3 B4 A4 B3 TP_UPC_XA_SWD_DATA TP_UPC_XA_SWD_CLK F4 SWD_DATA G4 SWD_CLK UPC_XA_UART_RX UPC_XA_UART_TX F2 UART_RX E2 UART_TX TBT_XA_LSTX TBT_XA_LSRX L4 LSX_R2P K4 LSX_P2R USB_UPC_XA_F_P USB_UPC_XA_F_N L5 USB_RP_P K5 USB_RP_N DP_XA_AUXCH_P DP_XA_AUXCH_N J1 AUX_P J2 AUX_N USB3_EXTA_D2R_P USB3_EXTA_D2R_N USB3_EXTA_R2D_P USB3_EXTA_R2D_N L2 K2 L3 K3 LDO_BMC E1 LDO_1V8A K1 LDO_1V8D A2 LDO_3V3 G1 VOUT_3V3 H2 VDDIO B1 VIN_3V3 H1 1 2.2UF C3105 1 1.0UF 0.47UF 20% 2 6.3V X5R 0201-1 20% 2 4V X5R-CERM 0201 10% 2 6.3V CERM-X5R 0201 SENSEP B10 SENSEN A10 1 C3108 10UF 20% 2 6.3V CERM-X5R 0402-1 0.47UF 10% 2 6.3V CERM-X5R 0201 HV_GATE1 B9 HV_GATE2 A9 C_CC1 L9 C_CC2 L10 USBC_XA_CC1 USBC_XA_CC2 RPD_G1 K9 RPD_G2 K10 USBC_XA_CC1 USBC_XA_CC2 BI 29 BI 29 1 C_USB_TP K6 C_USB_TN L6 USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N BI 32 BI 32 C_USB_BP K7 C_USB_BN L7 USBC_XA_USB_DBG_BOT_P USBC_XA_USB_DBG_BOT_N BI 32 BI 32 C_SBU1 K8 C_SBU2 L8 SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000 BI 29 32 MIN_LINE_WIDTH=0.0900 BI MIN_NECK_WIDTH=0.2000 USBC_XA_SBU1 USBC_XA_SBU2 BI 32 115 BI 32 115 C3114 220PF 10% 2 16V CER-X7R 0201 1 C3113 220PF 10% 2 16V CER-X7R 0201 B GROUND NC L11 NC or GND to dissipate heat DEBUG1 DEBUG2 DEBUG3 DEBUG4 SYNC_MASTER=X362_GKOO R3111 SYNC_DATE=08/08/2016 USB-C PORT CONTROLLER A DRAWING NUMBER 5% 1/20W MF 2 201 GND Apple Inc. 29 051-00647 REVISION R PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 31 OF 145 II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 C C3109 100K NO_XNET_CONNECTION=1 1 UPC_XA_SS SS H7 PAGE TITLE 1 C3106 BGA F1 I2C_ADDR G2 R_OSC I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XA_INT_L C3104 CRITICAL OMIT_TABLE U3100 F10 BUSPOWERZ E4 DEBUG_CTL1 D5 DEBUG_CTL2 1 CD3215A GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 I2C_UPC_XA_DBG_CTL_SCL I2C_UPC_XA_DBG_CTL_SDA MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.1V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5% 1/20W MF 2 201 29 E11 MRESET F11 RESET* MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V A1 D6 E5 E6 E7 F5 G5 H4 H5 G8 H8 L1 B8 D8 E8 F6 F7 F8 G6 G7 29 TBT_POC_RESET TP_USBC_XA_RESET_L HV FET/SENSE 31 29 TYPE-C 29 DIGITAL CORE I/O AND CONTROL PP3V3_UPC_XA_LDO 33 PORT MUX C PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES H11 J10 J11 K11 20% 2 6.3V CERM-X5R 0402-1 10UF VBUS VBUS VBUS VBUS C3100 1 PP_CABLE H10 PP5V_S4_X_USBC 29 A6 A7 A8 B7 CAP FOR PP_5V0 ON VR PAGE 29 PP1V8_UPC_XA_LDOA PP_HV PP_HV PP_HV PP_HV 103 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V UPC_XA_GATE2 P3V3_TBT_X_SX_EN_R A11 B11 C11 D11 104 105 PP3V3_UPC_XA_LDO PP_5V0 PP_5V0 PP_5V0 PP_5V0 105 109 PP3V3_G3H 104 TP_Q3100_DRAIN 10% 2 35V X5R 0402 PP3V3_UPC_XA_LDO 29 31 103 MAX 100uF TOTAL ON RAIL UPC_XA_GATE1 1UF 29 S1 NC MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=20V 1 8 1 G1 G2 4 3 2 S2 PP20V_USBC_XA_VBUS_F 29 Add on support page 5 PWR-CLIP-33 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 30 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 SECONDARY ACE USB-C PORT CONTROLLER (UPC) CRITICAL Q3200 FDPC4044 PWR-CLIP-33 FUSE 29 Add on support page 29 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=20V NC PPDCIN_G3H PP20V_USBC_XB_VBUS C3201 10% 2 35V X5R 0402 PP3V3_G3H 114 30 29 27 30 29 27 PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES PP3V3_UPC_XB_LDO 29 105 1 1 1M 1M 2 R3209 5% 2 1/20W R3208 5% 1/20W I2C_UPC_XB_DBG_CTL_SCL MF 103 30 29 201 CRITICAL R3203 1 31 15K 1 1M 2 5% 1/20W 31 0.1% 1/20W TF-LF 0201 2 R3205 MF 201 UPC_XA_UART_TX IN 29 29 NEED 0.1% 29 30 31 BI BI 29 29 TO SMC B BI 29 BI 29 REAR PORT: CONNECT UPC SPI TO ROM FRONT PORT: GROUND UPC SPI OUT OUT 29 OUT 29 OUT 29 IN 29 OUT 29 29 31 30 29 L3200 90-OHM-0.1A 30 29 OUT EXCX4CE SYM_VER-1 USB2_UPC_XB_P BI USB2_UPC_XB_N 2 29 3 PLACE_NEAR=U3200.K5:5mm PP3V3_S4 PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO NO_XNET_CONNECTION=1 113 27 BI 113 27 BI A 1 R3210 100K 5% 1/20W MF 2 201 27 IN 27 OUT 42 BI 42 BI 29 BI 29 BI A3 B4 A4 B3 TP_UPC_XB_SWD_DATA TP_UPC_XB_SWD_CLK F4 SWD_DATA G4 SWD_CLK UPC_XA_UART_TX UPC_XA_UART_RX F2 UART_RX E2 UART_TX L4 LSX_R2P K4 LSX_P2R USB_UPC_XB_F_P USB_UPC_XB_F_N L5 USB_RP_P K5 USB_RP_N DP_XB_AUXCH_P DP_XB_AUXCH_N J1 AUX_P J2 AUX_N SOC_SWCLK_DBG SOC_SWDIO_DBG SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L L2 K2 L3 K3 LDO_1V8A K1 LDO_1V8D A2 LDO_3V3 G1 VOUT_3V3 H2 VDDIO B1 VIN_3V3 H1 H11 J10 J11 K11 VBUS VBUS VBUS VBUS PP_CABLE H10 A6 A7 A8 B7 LDO_BMC E1 C UPC_XB_SS SENSEP B10 SENSEN A10 1 C3209 0.47UF 10% 2 6.3V CERM-X5R 0201 HV_GATE1 B9 HV_GATE2 A9 C_CC1 L9 C_CC2 L10 USBC_XB_CC1 USBC_XB_CC2 RPD_G1 K9 RPD_G2 K10 USBC_XB_CC1 USBC_XB_CC2 BI 29 BI 29 C_USB_TP K6 C_USB_TN L6 USBC_XB_USB_TOP_P USBC_XB_USB_TOP_N BI 32 BI 32 C_USB_BP K7 C_USB_BN L7 USBC_XB_USB_BOT_P USBC_XB_USB_BOT_N BI 32 BI 32 BI 32 115 BI 32 115 C_SBU1 K8 C_SBU2 L8 SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ TBT_XB_LSTX TBT_XB_LSRX 20% 2 4V X5R-CERM 0201 20% 2 6.3V CERM-X5R 0402-1 USBC_XB_SBU1 USBC_XB_SBU2 1 C3214 220PF 10% 2 16V CER-X7R 0201 1 29 32 BI 29 32 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 C3213 220PF 10% 2 16V CER-X7R 0201 B GROUND NC L11 NC or GND to dissipate heat DEBUG1 DEBUG2 DEBUG3 DEBUG4 R3211 1 SYNC_MASTER=J80_MLB 100K NO_XNET_CONNECTION=1 BI GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 29 BI 4 PLACE_NEAR=U3200.L5:5mm A5 I2C_SDA2 B5 I2C_SCL2 B6 I2C_IRQ2* UPC_XB_SPI_CLK UPC_XB_SPI_MOSI UPC_XB_SPI_MISO UPC_XB_SPI_CS_L 10% 2 6.3V CERM-X5R 0201 A1 D6 E5 E6 E7 F5 G5 H4 H5 G8 H8 L1 B8 D8 E8 F6 F7 F8 G6 G7 29 1 D1 I2C_SDA1 D2 I2C_SCL1 C1 I2C_IRQ1* I2C_UPC_X_SDA2 I2C_UPC_X_SCL2 SMC_USBC_INT_L C3204 2.2UF 10UF 20% 2 6.3V X5R 0201-1 SS H7 E4 DEBUG_CTL1 D5 DEBUG_CTL2 I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XB_INT_L C3208 0.47UF BGA F1 I2C_ADDR G2 R_OSC I2C_UPC_XB_DBG_CTL_SCL I2C_UPC_XB_DBG_CTL_SDA 1 1.0UF 1 C3206 CD3215A GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 F10 BUSPOWERZ NC_UPC_XB_I2C_ADDR UPC_XB_R_OSC 29 31 B2 C2 D10 G11 C10 E10 G10 D7 H6 GND 31 201 I2C_UPC_XB_DBG_CTL_SDA MF 104 TP_UPC_XB_DBG_UART_TX TP_UPC_XB_DBG_UART_RX 29 TBT_X_CIO_PWR_EN BI TBT_X_USB_PWR_EN BI DP_XB_HPD 27 OUT UPC_XB_HPD_RX 29 UPC_X_5V_EN 29 OUT SMC_PME_S4_DARK_L 29 OUT UPC_XB_FAULT_L 29 OUT 29 U3200 HV FET/SENSE 114 C3205 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V 1 CRITICAL OMIT_TABLE TYPE-C OUT E11 MRESET F11 RESET* DIGITAL CORE I/O AND CONTROL TESTPOINTS MUST BE PRESENT FOR GPIO0, GPIO1 (EVEN IN PRODUCTION) TBT_POC_RESET USBC_X_RESET_L_R 1 VOUT_3V3 FOR RIDGE, OR FLOAT IF UNUSED MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V PORT MUX 33 PP_5V0 PP_5V0 PP_5V0 PP_5V0 20% 2 6.3V CERM-X5R 0402-1 PP_HV PP_HV PP_HV PP_HV C3200 A11 B11 C11 D11 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V PP1V1_UPC_XB_LDO_BMC 10UF IN 29 PP1V8_UPC_XB_LDOD PP5V_S4_X_USBC 30 29 105 P3V3_TBT_X_SX_EN_R 33 PP1V8_UPC_XB_LDOA PP3V3_UPC_XB_LDO CAP FOR PP_5V0 ON VR PAGE C 104 PP3V3_UPC_XB_LDO GND 29 29 30 103 MAX 100uF TOTAL ON RAIL UPC_XB_GATE1 TP_Q3200_DRAIN UPC_XB_GATE2 1UF 109 S1 PP20V_USBC_XB_VBUS_F 1 29 8 1 G1 G2 4 3 2 S2 D 5 D PAGE TITLE 5% 1/20W MF 201 2 GND SYNC_DATE=11/06/2015 USB-C PORT CONTROLLER B DRAWING NUMBER 051-00647 29 Apple Inc. PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 32 OF 145 31 OF 121 SIZE D A 6 3 SM 1610 1 ESDA25P35-1U1M 0.01UF D3302 D 5.5V-6.2PF 0201 CRITICAL 1 C3306 0.01UF 10% 2 25V X5R-CERM 0201 1 0.01UF 10% 25V 2 X5R-CERM 0201 CRITICAL 1 C3307 0.01UF 10% 2 25V X5R-CERM 0201 C3302 10% 0201 CRITICAL 1 C3308 0.01UF 10% 2 25V X5R-CERM 0201 PWR CRITICAL 1 CRITICAL C3303 1 0.01UF 0.01UF 10% 10% 25V 2 X5R-CERM 2 25V X5R-CERM 0201 0201 CRITICAL 1 C3312 CRITICAL C3309 1 0.01UF C3305 0.01UF 10% 2 25V X5R-CERM 0201 10% 2 25V X5R-CERM 0201 BYPASS=J3300.59::2MM BYPASS=J3300.59::2MM BYPASS=J3300.59::2MM BYPASS=J3300.59::2MM BYPASS=J3300.59::2MM 61 63 65 67 69 71 73 75 77 79 81 83 85 GND 0.22UF 6.3V X5R-CERM USBC_XB_R2D_C_N<2> IN 27 113 USBC_XB_R2D_C_P<2> IN 27 113 0201 0201 USBC_XB_USB_TOP_P USBC_XB_USB_TOP_N USBC_XB_D2R_N<2> USBC_XB_D2R_P<2> USBC_XB_SBU1 31 BI 31 27 113 OUT 27 113 5.5V-6.2PF DZ3353 1 C3370 USBC_XA_R2D_P<1> GND_VOID=TRUE 1 2 10% GND_VOID=TRUE C3371 1 2 10% 0.22UF 6.3V 0201 0.22UF 6.3V X5R-CERM 0201 GND_VOID=TRUE GND_VOID=TRUE 2 1 2 1 2 1 GND_VOID=TRUE GND_VOID=TRUE PP20V_USBC_XA_VBUS_CONN PART NUMBER 138S0683 QTY 2 1 32 114 2 1 115 GND_VOID=TRUE GND_VOID=TRUE USBC_XA_R2D_C_P<1> IN 27 113 USBC_XA_R2D_C_N<1> IN 27 113 1 2 1 BI 30 BI 30 OUT 27 113 OUT 27 113 BI 29 30 SBU2 TBT_R2D0 USB2 BOT TBT_D2R0 CC1 2 B 1 116 DESCRIPTION 2 2 30 115 BI USBC_XA_D2R_P<1> USBC_XA_D2R_N<1> USBC_XA_CC1 60 62 64 66 68 70 72 74 76 78 80 82 84 86 X5R-CERM GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE 114 SBU1 1 USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N OUT 31 115 TBT_D2R1 2 0201-THICKSTNCL 1 ESD8011 2 GND_VOID=TRUE USBC_XA_R2D_N<1> TP_J3300_P56 USB2 TOP OUT BI TBT_R2D1 C X3DFN2-THICKSTNCL 1 2 D3357 1 ESD8011 2 BI CC2 GND_VOID=TRUE GND_VOID=TRUE X3DFN2-THICKSTNCL ESD8011 X3DFN2-THICKSTNCL D3358 X3DFN2-THICKSTNCL ESD8011 1 GND_VOID=TRUE GND_VOID=TRUE BYPASS=J3300.59::2MM 0.01UF 2 25V X5R-CERM 10% X5R-CERM 5.5V-6.2PF 10% 25V 2 X5R-CERM C3301 2 0201-THICKSTNCL 1 0.01UF 1 6.3V GND_VOID=TRUE X3DFN2-THICKSTNCL C3300 C3393 ESD8011 PLACE VBUS CAP NEAR EACH VBUS PIN CRITICAL 10% 0.22UF 29 31 BI USBC_XA_SBU2 BYPASS=J3300.59::2MM BYPASS=J3300.59::2MM CRITICAL 2 D3322 1 ESDA25P35-1U1M A GND_VOID=TRUE GND_VOID=TRUE 1 D3356 0201-THICKSTNCL DZ3352 ESD8011 X3DFN2-THICKSTNCL D3350 ESD8011 X3DFN2-THICKSTNCL D3351 ESD8011 CRITICAL D3301 GND_VOID=TRUE GND_VOID=TRUE 59 BYPASS=J3300.59::2MM 1610 1 BYPASS=J3300.59::2MM PP20V_USBC_XA_VBUS_CONN 1 1 2 1 GND_VOID=TRUE ESD8011 D3325 ESD8011 D3326 X3DFN2-THICKSTNCL 1 2 C3392 USBC_XB_CC2 GND_VOID=TRUE DZ3302 A VOLTAGE=20V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 K 1UF 10% 25V 2 X5R 402 1 2 0201 GND_VOID=TRUE 2 D3329 1 2 1 2 1 X3DFN2-THICKSTNCL NSR20F40NX_G 1 SM OMIT_TABLE C3304 1 2 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE ESD8011 D3300 DSN2 K 2 XW3300 PP20V_USBC_XA_VBUS CRITICAL 2 0201 GND_VOID=TRUE GND_VOID=TRUE 10% 2 25V X5R-CERM GND_VOID=TRUE GND_VOID=TRUE D3304 VOLTAGE=20V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 29 ESD8011 1 X3DFN2-THICKSTNCL D3327 5.5V-6.2PF 0201-THICKSTNCL DZ3301 GND_VOID=TRUE GND_VOID=TRUE USBC_XA_R2D_N<2> X3DFN2-THICKSTNCL X5R-CERM 2 ESD8011 6.3V 2 D3320 0.22UF X3DFN2-THICKSTNCL 10% ESD8011 2 D3355 1 2 X3DFN2-THICKSTNCL GND_VOID=TRUE 0201 ESD8011 X5R-CERM GND_VOID=TRUE GND_VOID=TRUE D3321 6.3V GND_VOID=TRUE GND_VOID=TRUE 5.5V-6.2PF C3372 2 D3352 X3DFN2-THICKSTNCL GND_VOID=TRUE 0.22UF 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 DZ3351 10% GND_VOID=TRUE GND_VOID=TRUE USBC_XA_R2D_P<2> 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 0201-THICKSTNCL BI 2 C3359 1 SIGNAL D 0.01UF 10% 2 25V X5R-CERM 0201 USBC_XB_R2D_P<2> 58 5.5V-6.2PF OUT GND_VOID=TRUE 1 PWR DZ3300 27 30 29 1 F-ST-SM 57 1 USBC_XB_R2D_N<2> 20759-056E-02 2 0201 114 0201-THICKSTNCL OUT 113 C3373 USBC_XA_R2D_C_N<2> USBC_XA_D2R_P<2> USBC_XA_D2R_N<2> USBC_XA_CC2 1 2 ESD8011 CC2 IN 1 2 X3DFN2-THICKSTNCL IN 1 2 OUT 10% 2 25V X5R-CERM BYPASS=J3300.58::2MM J3300 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE USBC_XA_R2D_C_P<2> 1 2 D3328 TBT_D2R1 27 1 USBC_XA_USB_DBG_BOT_N USBC_XA_USB_DBG_BOT_P USBC_XA_SBU1 TBT_R2D1 113 1 2 ESD8011 27 2 TP_J3300_P2 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL C3358 0.01UF 10% 2 25V X5R-CERM 0201 BYPASS=J3300.58::2MM GND_VOID=TRUE GND_VOID=TRUE X3DFN2-THICKSTNCL BI GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE 2 USBC_XB_R2D_P<1> 0201 D3312 30 X5R-CERM 5.5V-6.2PF 113 BI 6.3V DZ3303 SBU1 30 0.22UF 0201-THICKSTNCL 115 BI 10% X3DFN2-THICKSTNCL USB2 BOT 30 ESD8011 D3354 GND_VOID=TRUE 2 ESD8011 BI 1 D3324 BI 31 USB2 BOT GND_VOID=TRUE C3355 1 0.01UF 10% 25V 2 X5R-CERM 0201 CRITICAL 1 0.01UF 10% 2 25V X5R-CERM 0201 USBC_XB_R2D_N<1> 0201 X3DFN2-THICKSTNCL BI 31 X5R-CERM D3353 31 6.3V X3DFN2-THICKSTNCL OUT 115 OUT C3390 USBC_XB_R2D_C_P<1> USBC_XB_D2R_N<1> USBC_XB_D2R_P<1> USBC_XB_SBU2 USBC_XB_USB_BOT_N USBC_XB_USB_BOT_P 0.22UF ESD8011 27 GND_VOID=TRUE 5.5V-6.2PF 113 IN 10% 0201-THICKSTNCL SBU2 27 2 DZ3350 TBT_D2R0 113 1 ESD8011 TBT_R2D0 GND_VOID=TRUE CRITICAL C3362 1 BYPASS=J3300.58::2MM C3357 1 CRITICAL C3353 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL C3356 0.01UF X3DFN2-THICKSTNCL C3391 USBC_XB_R2D_C_N<1> IN X3DFN2-THICKSTNCL 27 GND_VOID=TRUE ESD8011 113 BI 1 1 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL USBC_XB_CC1 D3349 31 29 CRITICAL C3352 BYPASS=J3300.58::2MM CC1 B 1 0.01UF 10% 2 25V X5R-CERM 0201 A CRITICAL C3351 1 D3359 10% 25V 2 X5R 402 CRITICAL C3350 X3DFN2-THICKSTNCL 1UF A CRITICAL K 1 ESD8011 NSR20F40NX_G C3354 BYPASS=J3300.58::2MM BYPASS=J3300.58::2MM BYPASS=J3300.58::2MM BYPASS=J3300.58::2MM BYPASS=J3300.58::2MM BYPASS=J3300.58::2MM X3DFN2-THICKSTNCL D3370 DSN2 OMIT_TABLE K 1 PLACE VBUS CAP NEAR EACH VBUS PIN PP20V_USBC_XB_VBUS_CONN 1 ESD8011 2 CRITICAL C 2 VOLTAGE=20V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 XW3350 PP20V_USBC_XB_VBUS 29 4 D3323 VOLTAGE=20V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 5 D3360 7 X3DFN2-THICKSTNCL 8 CAP,CER,X5R,1UF,10%,25V,0402 REFERENCE DES CRITICAL BOM OPTION CRITICAL C3304, C3354 NOSTUFF LAST CHANGE: Wed Apr 1 22:57:37 2015 A SYNC_MASTER=X362_MLB SYNC_DATE=03/30/2016 PAGE TITLE USB-C CONNECTOR A DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 33 OF 145 32 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D TBT X "POC" Power-up Reset NOSTUFF MAKE_BASE=TRUE P3V3_TBT_X_SX_EN_R 1 R3400 402 0 2 MF-LF 5% 1/16W CRITICAL U3400 IN SLG5AP1449V R3401 P3V3_TBT_X_SX_EN_R P3V3_TBT_X_SX_EN_R 0 1 2 P3V3_TBT_X_SX_EN STDFN 1 ON 5% 1/20W MF 201 1 R3404 100K 5% 1/20W MF 2 201 D 2 S 3 PP3V3_S5 110 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 116 C PP3V3_S5_TBT_X_SW GND PP3V3_S5_TBT_X_SW 28 29 PP3V3_S5_TBT_X_SW 27 U3401 1 CRITICAL R3402 100K VCC 1% 1/20W MF 2 201 IN U3401 TPS3895ADRY USON MAKE_BASE=TRUE USBC_X_RESET_L_R 1 USBC_X_RESET_L_R 1 ENABLE TBTXPOCRST_SNS 3 SENSE SENSE_OUT 4 CT 5 Output Push-pull Delay 440us +/- 20us Vth 2.508V nominal USBC_X_RESET_L GND R3403 24.9K OUT 27 29 TBTXPOCRST_CT C3400 2 31 6 31 IN 4 C 30 1 100PF 5% 25V 2 C0G 0201 1% 1/20W MF 2 201 NOSTUFF R3431 10K 1 B 2 5% 1/20W MF 201 1 K NOSTUFF B 1.0UF D3400 SC2 NOSTUFF C3431 A 20% 2 6.3V X5R 0201-1 DSF01S30SCAP DESIGN: X502/DEV_MLB_U LAST CHANGE: Wed Feb 18 17:12:24 2015 A SYNC_MASTER=X362_MLB SYNC_DATE=03/29/2016 PAGE TITLE USB-C CONNECTOR B DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 . 10.0.0 1 34 OF 145 33 OF 121 SIZE D A 8 116 34 29 7 6 PP5V_S4_X_USBC 5 110 108 4 PP5V_S4 116 109 108 3 1 2 XW3501 2 2 SM 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 10UF VOLTAGE=5V 1 27.4K R3531 2 0.1% 1/20W MF 2 0201 NO_XNET_CONNECTION=1 VCC 2.2UF 27.4K 0.1% 1/20W MF 0201 2 C3522 10% 10V X6S-CERM 0402 29 NO_XNET_CONNECTION=1 1 R3517 191K 1 C3517 22PF 5% 50V 2 C0G 0201 0.1% 1/20W MF 2 0201 10 FB P5VUSBCX_SREF 7 11 OCSET NC 4 RTN 13 FSEL P5VUSBCX_SET0 8 SET0 P5VUSBCX_SET1 9 SET1 6 VID0 P5VUSBCX_RTN_DIV R3518 NOSTUFF 95.3K 0.1% 1/20W MF 2 0201 R3513 5 1 BOOT 18 UGATE 17 PGOOD P5VUSBCX_SET_R D FDPC1012S LLP P5VUSBCX_DRVH_R MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE P5VUSBCX_LL MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUE DIDT=TRUE R3539 2 0 5% 1/20W MF 0201 CRITICAL V+ 8 V+ 9 1 1 1 C3526 10PF 5% 2 50V C0G 0201 1 R3504 10K 0.1% 1/20W MF 2 0201-1 1 R3502 10K 0.1% 1/20W MF 2 0201-1 11K P5VUSBCX_DRVH 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE P5VUSBCX_DRVL 2 3 4 1.5UH-20%-12.5A-0.017OHM HSG 1 2 PIMB062D-SM SW PP5V_S4_X_USBC 0.002 L3500 P5VUSBCX_R 1 3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1% 1/2W MF 0306 C3505 1 2.2UF C3506 20% 25V X5R-CERM 2 0402-1 LSG 7 1 C3509 150UF 20% 25V X5R-CERM 2 0402-1 20% 2 6.3V TANT-POLY CASE-B1S-1 1 C3508 1 150UF C3507 150UF 20% 2 6.3V TANT-POLY CASE-B1S-1 20% 2 6.3V TANT-POLY CASE-B1S-1 P5VUSBCX_N R3521 Vout = 5.23V Freq = 500 kHz Max OCP = 13.9A Nom OCP = 11.6A Min OCP = 9.37A 1 2.74K 2 1 2.2UF P5VUSBCX_P VID1 GND 29 34 116 2 4 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 1% 1/20W C3570 MF 201 2 2200PF PGND 2 1 10% 25V CER-X7R 0201 2 1% 1/20W MF 201 1 R3530 CRITICAL R3500 C 20% 2 25V X5R-CERM 0402-1 CRITICAL 0 5% 1/20W MF 201 2.2UF 10% 16V X7R-CERM 0402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE 3 1 14 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE LGATE 1 P5VUSBCX_OCSET C3501 C3516 P5VUSBCX_VBST PHASE 16 SREF 12 VO 1 2 CRITICAL P5VUSBCX_VO 0.1UF 10% 16V X5R-CERM 0201 UTQFN 15 EN P5VUSBCX_SENSE_DIV P5VUSBCX_FSEL C3523 PVCC ISL95870AH UPC_X_5V_EN 20% 2 25V X5R-CERM 0402-1 2.2UF 33UF Q3501 U3500 IN 20% 16V 2 TANT-POLY CASE-B3 1 GND GND GND 1 1 20% 16V 2 TANT-POLY CASE-B3 20% 16V 2 TANT-POLY CASE-B3 1 0.1UF 2.2 5% 1/20W MF 201 2 33UF C3500 C3502 1 5 6 10 R3503 P5VUSBCX_SENSE_DIV_R 20 P5VUSBCX_RTN_DIV_R 20% 10V X5R-CERM 0402-1 1 C3503 CRITICAL 1 2 D 2 1 19 1 C3521 R3509 1 CRITICAL 1 33UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE PP5V_USBCX_VCC XW3502 SM C3504 P5VUSBCX_BOOT_RC 2.2 5% 1/20W MF 201 1 PPBUS_G3H CRITICAL R3501 2 1 R3572 C 2.74K 1% 1/20W MF 2 201 C3515 10PF 5% 2 50V C0G 0201 XW3500 SM P5VUSBCX_AGND MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 2 PLACE_NEAR=U3500.2:1mm B B A SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN PAGE TITLE SYNC_DATE=12/04/2015 TBT 5V REGULATOR DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 35 OF 145 34 OF 121 SIZE D A 8 7 PP3V3_S4_BT PP3V3_S4_BT MAKE_BASE=TRUE LBEE5UQ1HG-844 35 PP3V3_S4_BT 35 PP3V3_S4_WLAN_SW 35 PP3V3_S4_WLAN_SW 35 PP3V3_S4_WLAN_SW 4 3 PP3V3_S4_BT 35 2 PP3V3_S4_WLAN_SW 1 35 C3758 1 12PF 35 PP3V3_S4_WLAN_SW C3757 12PF 5% 2 25V NP0-C0G 0201 1 5% 25V 2 NP0-C0G 0201 PP3V3_S4_BT 1 C3704 C3705 1 10UF 35 0.1UF 20% 2 6.3V CERM-X5R 0402-4 10% 2 35V CER-X5R 0201 35 PP3V3_S4_WLAN_SW FOR JTAG MODE REMOVE R3735 NO_XNET_CONNECTION=1 PP3V3_S4_BT R3735 1 10UF 10UF 20% 2 6.3V CERM-X5R 0402-4 5% 25V 2 NP0-C0G 0201 20% 2 6.3V CERM-X5R 0402-4 FEM SUPPLY SHUNT CAPACITORS PLACE ON THE TOP SIDE CLOSE TO U3730 NOSTUFF R3731 35 WLAN_STRAP_1 R3734 1 1 5% 1/20W MF 201 2 5% 1/20W MF 201 2 48 35 35 35 STRAP_0 HI:SROM (Default) STRAP_1 LO:16kb SROM BI 113 36 BI 113 36 BI 113 36 BI 113 36 BI 47 63 78 61 74 85 2G_ANT_CORE0 2G_ANT_CORE1 2G_ANT_CORE2 5G_ANT_CORE0 5G_ANT_CORE1 5G_ANT_CORE2 1 CORE2_5G_CTL2_WLAN_JTAG_TDO 35 R3701 1K 5% 1/20W MF 2 201 35 35 1 R3759 5% 1/20W MF 2 201 35 35 35 35 Q3701 35 DMN32D2LFB4 DFN1006H4-3 97 98 99 100 58 59 65 66 BT_SPI2_MOSI BT_SPI2_CSN BT_SPI2_MISO BT_SPI2_CLK 35 35 10% 2 35V CER-X5R 0201 6 113 7 113 10 9 13 12 PCIE_RDP PCIE_RDN PCIE_TDP PCIE_TDN PCIE_REFCLK_PC PCIE_REFCLK_NC LBEE5UQ1HG-844 2 PCIE_WAKE_CL 15 AP_PCIE_WAKE_L PCIE_CLKREQ* 16 AP_CLKREQ_L PCIE_PRST* 17 AP_RESET_CONN_L LGA SYM 1 OF 2 WL_JTAG_TDI/GPIO_3 WL_JTAG_TMS WL_JTAG_TCK WL_JTAG_TRST* WL_JTAG_SEL WLAN_EXT_POR* WL_JTAG_TDO BT_UART_CTS*/BT_JTAG_TMS BT_UART_RTS*/BT_JTAG_TCK BT_UART_RXD/BT_JTAG_TDI BT_UART_TXD/BT_JTAG_TDO 41 42 36 37 BT_SWDIO BT_SWDCLK 57 56 SPROM_CLK SPROM_DOUT SPROM_CS SPROM_DIN WL_XTAL32 BT_XTAL32 4 25 BT_HOST_WAKE/BT_HOST_WAKE* BT_DEV_WAKE 33 35 BT_SPI2_MOSI BT_SPI2_CSN BT_SPI2_MISO BT_SPI2_CLK BT_PCM_SYNC BT_PCM_IN BT_PCM_OUT BT_PCM_CLK 49 50 52 53 OUT GND_VOID=TRUE 14 113 OUT 14 113 IN 12 113 IN 12 113 OUT 19 35 35 13 31 BT_JTAG_SEL 34 BT_RX_ACTIVE BT_UART_CTS_R2D_L BT_UART_RTS_D2R_L BT_UART_R2D BT_UART_D2R BT_SWDIO BT_SWDCLK 35 R3753 1 5% 1/20W MF 201 2 2MBIT 35 6 SCLK BT_SPI2_CLK 35 BT_SPI2_CSN 1K BT_SPI2_MOSI 1 CS* 3 WP* 7 HOLD* BT_SFLASH_CS_L 2 5% 1/20W MF 201 SO/SIO1 2 GND 4 BT_SFLASH_WP_L SMC_PME_S4_DARK_L 35 BT_LOW_PWR_L BT_I2S_SYNC BT_I2S_R2D BT_I2S_D2R BT_I2S_CLK THRM PAD SMC_WIFI_PWR_EN WLAN_UART_TX 35 WLAN_UART_RX 35 48 46 36 PP3V3_S4_WLAN_SW WLAN_JTAG_TCK WLAN_JTAG_TMS 35 WLAN_JTAG_TDI 35 CORE2_5G_CTL2_WLAN_JTAG_TDO WLAN_JTAG_TRST_L 35 WLAN_JTAG_SEL 35 35 C3711 0.1UF 10% 2 35V CER-X5R 0201 VCC 35 U3710 CAS93C86B 35 35 35 UDFN8 3 DI 1 CS 2 SK SPROM_DOUT SPROM_CS SPROM_CLK NC 7 PE DO 4 ORG 6 SPROM_DIN 35 35 20 WIFI_SROM_ORG 2 OMIT_TABLE 114 R3712 10K 36 20 15 35 19 1 13 13 R3777MF BT_UART_D2R 35 SMC_BT_PWR_EN 110 R3764 13 0 2 1/20W NC 35 1 35 8 CRITICAL VCC NO STUFF 35 35 20 12 IN U3760 BT_UART_RTS_D2R_L 2 BT_UART_D2R PLT_RST_L 0 X2-DFN2010 A1 1 1OE 5 A2 7 2OE Y1 6 PCH_BT_UART_CTS_L OUT 15 Y2 3 PCH_BT_UART_D2R OUT 15 B GND 4 2 BT UART RX & CTS ISOLATION CIRCUIT AP_CLKREQ_L AP_RESET_L AP_PCIE_WAKE_L PP3V3_S4_WLAN_SW 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 110 R3774 1 BT_LOW_PWR_L 35 SMC_PME_S4_DARK_L 35 SMC_BT_PWR_EN 35 BT_UART_D2R 35 BT_UART_R2D 35 BT_UART_CTS_R2D_L BT_UART_RTS_D2R_L BT_SPI2_CLK 35 BT_SPI2_CSN 35 BT_SPI2_MISO 35 BT_SPI2_MOSI 35 BT_ROM_BOOT_L BT_TIMESTAMP BT_SWDIO 35 BT_SWDCLK 35 SYSCLK_CLK32K_WIFIBT 0 PP3V3_S4 1 4 C3774 0.1UF 8 CRITICAL VCC NO STUFF 48 35 2 5% 1/20W MF 201 10% 35V 2 CER-X5R 0201 U3770 46 74LVC2G126 15 IN 15 IN 35 20 12 IN 35 35 114 PCH_BT_UART_RTS_L 2 PCH_BT_UART_R2D PLT_RST_L 1 BT_ROM_BOOT_L BT_TIMESTAMP 13 35 MAKE_BASE=TRUE Y1 6 BT_UART_CTS_R2D_L 35 Y2 3 BT_UART_R2D 35 GND 4 2 5% 1/20W MF 201 35 MAKE_BASE=TRUE 0 X2-DFN2010 A1 1 1OE 5 A2 7 2OE R3775 NO STUFF SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016 PAGE TITLE WIFI/BT: MODULE 1 20 35 DRAWING NUMBER PP3V3_S4_WLAN_SW 35 42 BOM_COST_GROUP=WIRELESS WWW.AliSaler.Com 10% 2 35V CER-X5R 0201 NO STUFF 40 1 41 5 C3764 74LVC2G126 Apple Inc. R MF 201 6 20 35 0.1UF 3 REVISION BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 2 SIZE 051-00647 D 10.0.0 dvt-fab10 37 OF 145 35 OF 121 NOTICE OF PROPRIETARY PROPERTY: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 7 5% 1 201 PP3V3_S4 II NOT TO REPRODUCE OR COPY IT 8 100K 2 5% 1/20W MF 201 35 46 5% GND EPAD C BT UART TX & RTS ISOLATION CIRCUIT 13 35 48 WLAN SERIAL EEPROM 5% 1/20W MF 201 12 IN MAKE_BASE=TRUE F-ST-SM 39 48 1 1 35 48 OUT BT_LOW_PWR_L J3701 35 BT_SFLASH_HOLD_L 35 100K SYSCLK_CLK32K_WIFIBT AA25D-S038VA1 BT_SPI2_MISO 1 WL_CLK32K DEBUG CONNECTOR MX25L2006EZUI-12G R3754 1 SI/SIO0 5 2 SYM_VER_3 WIFI_DBG USON 100K 5% 1/20W MF 201 10% 2 35V CER-X5R 0201 U3750 5% 1/20W MF 201 2 35 35 0.1UF VCC OMIT_TABLE 100K 5% 1/20W MF 201 2 BT_UART_R2D 35 36 DFN1006H4-3 C3756 9 100K PP3V3_S4_BT 1 R3776 Q3702 35 100K 5% 1/20W MF 201 R3765 1 2 35 114 8 R3752 100K BT_UART_RTS_D2R_L 35 PP3V3_S4_WLAN_SW 1 1 1 35 35 IN R3767 35 PP3V3_S4_BT R3751 10K 14 113 14 113 5% 1/20W MF 201 DMN32D2LFB4 BLUETOOTH SERIAL FLASH 1 2 MF 201 35 35 BT_UART_CTS_R2D_L 35 IN R3766 5% 38 39 40 44 46 48 51 54 60 62 64 67 69 73 75 76 77 79 80 82 83 84 86 87 1 3 5 8 11 14 18 20 26 GND GND GND GND GND GND GND GND GND IN BT_ROM_BOOT_L BT_TIMESTAMP BT_RST* PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 3 D 35 10% 6.3V X7R 0201 1 29 BT_GPIO_2/BT_JTAG_TRST_N 28 BT_GPIO_3 27 BT_GPIO_4 GND_VOID=TRUE 1 10% 6.3V X7R 0201 GND_VOID=TRUE 2 SYM_VER_3 NC 1 36 IN 2 R3762 20 35 BI 0.1UF GND_VOID=TRUE 0.1UF PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N 10% 2 35V CER-X5R 0201 C3760 C3759 91 C0_FEMCTRL_2/STRAP_0 90 C2_FEMCTRL_2/STRAP_1 WLAN_STRAP_0 WLAN_STRAP_1 SPROM_CLK SPROM_DOUT SPROM_CS SPROM_DIN 35 270K PCH_BT_ROM_BOOT 93 72 71 70 94 21 92 0.1UF C3702 0.1UF C3703 10% 2 35V CER-X5R 0201 C3701 1 20% 6.3V 2 CERM-X5R 0402-4 U3730 22 WL_GPIO_6/UART_RX 23 WL_GPIO_7/UART_TX WLAN_JTAG_SEL WLAN_EXT_POR_L 35 NOSTUFF IN 36 WLAN_JTAG_TDI WLAN_JTAG_TMS WLAN_JTAG_TCK WLAN_JTAG_TRST_L 35 WLAN_STRAP_0 15 BI 113 50_G_0_MATCH 50_G_1_MATCH 50_G_2_MATCH 50_A_0_MATCH 50_A_1_MATCH 50_A_2_MATCH 1 10UF BT_RX_ACTIVE/BT_GPIO_5 43 35 35 36 WLAN_UART_RX WLAN_UART_TX 48 35 10K 10K 113 C3739 2 S PP3V3_S4_WLAN_SW 45 BT_RF1 NC SROM_STRAPS 35 5% 1/20W MF 201 C3738 D 35 3 D 12PF 5% 2 25V NP0-C0G 0201 C3737 1 0.1UF 35 G 1 1 WL_VDDIO 19 12PF +/-0.1PF 2 25V NP0-C0G 0201 C3741 BT_OTP_VDD3P3V 30 1 BT_VDDIO 32 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 C3742 1 VDD_BT 24 3.0PF 20% 2 6.3V CERM-X5R 0402-4 C3763 VDD3P3_FEM_CORE2 81 VDD3P3_FEM_CORE0 55 10UF 5% 2 25V NP0-C0G 0201 1 VDD3P3_FEM_CORE1 68 12PF +/-0.1PF 2 25V NP0-C0G 0201 C3762 1 VDD3P3_REG1P8 88 3.0PF C3736 1 VDD3P3_REG1P2 96 C3740 1 1 PP3V3_S4_BT WLAN_1P2V_EN VDD3P3_PAD 89 C3761 1 1P2V_EN 95 1 0 VDD3P3 2 2 9 A THRM_PAD MAKE_BASE=TRUE 8 B THRM_PAD PP3V3_S4_WLAN_SW 36 35 2 S C 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 PP3V3_S4_BT 5 D LGA SYM 2 OF 2 5 VOLTAGE=3.3V U3730 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 35 G 1 110 6 SHEET 1 A 8 7 6 5 4 3 2 1 CRITICAL R3814 50_0_ANT C3817 2 3 4 0 1 2 113 5% 1/20W MF 201 1 0.1PF 2 COM CRITICAL 1 C3816 0.1PF HI 4 LO 6 GND +/-0.05PF 2 25V C0G 0201 +/-0.05PF 25V 2 C0G 0201 36 110 50_0_COM 1 C3812 SMC_WIFI_PWR_EN 2 ON TDFN 2 50_G_0_MATCH D 3 S 5 1 1 C3810 0.2PF +/-0.05PF 2 25V COG-CERM 0201 +/-0.05PF 25V COG-CERM 2 0201 PP3V3_S4_WLAN_SW 35 113 NO STUFF 0.2PF SLG5AP1443V 48 46 36 35 2 0201 NO STUFF U3840 CAP 1 50_G_0_DIPLEXER VDD 7 0201 L3811 2.4NH+/-0.1NH-0.6A 113 WIFI_SW_CAP D CRITICAL 5 3 1 113 CRITICAL PP3V3_S4_WLAN SM R3810 F-ST-SM 1 U3810 DPX205950DT CRITICAL 20449-001E-03 WLAN Power Switch 0.2PF 35 113 1 J3810 1 +/-0.05PF 25V COG-CERM 2 0201 OMIT_TABLE CRITICAL 5% 1/20W MF 201 NO STUFF C3815 50_A_0_MATCH 2 CRITICAL D 0 1 L3813 CORE0 DIPLEXER AND MATCHING 50_A_0_DIPLEXER 2.8NH-+/-0.1NH-0.6A-0.12OHM 113 35 36 1 8 GND C3841 4700PF 10% 2 10V X7R 201 CRITICAL R3824 +/-0.05PF 25V COG-CERM 2 0201 20449-001E-03 SM R3820 F-ST-SM 113 50_1_ANT CRITICAL C3827 2 3 4 0 1 2 113 5% 1/20W MF 201 1 0.1PF 1 2 COM 50_1_COM CRITICAL C3826 0.2PF +/-0.05PF 25V 2 C0G 0201 HI 4 LO 6 L3821 2.4NH+/-0.1NH-0.6A 113 1 50_G_1_DIPLEXER C3822 0201 35 113 NO STUFF 1 1 C3820 0.2PF +/-0.05PF 2 25V COG-CERM 0201 +/-0.05PF 25V COG-CERM 2 0201 PP3V3_S4_WLAN 1 50_G_1_MATCH 0.2PF Delay = 130ms +/- 20% PP3V3_S4_WLAN_SW 2 NO STUFF Supervisor & CLKREQ# Isolation 36 35 0201 CRITICAL GND +/-0.05PF 2 25V COG-CERM 0201 5 3 1 1 U3820 DPX205950DT CRITICAL 35 113 C L3823 J3820 1 0.2PF OMIT_TABLE CRITICAL 5% 1/20W MF 201 2 CRITICAL C3825 50_A_1_MATCH 2 CRITICAL C 0 1 1 CORE1 DIPLEXER AND MATCHING 50_A_1_DIPLEXER 2.4NH+/-0.1NH-0.6A 113 36 110 C3851 0.1UF R3834 35 OUT AP_RESET_CONN_L 1 0 AP_RESET_CONN_R_L 2 4 RESET* 1 MR* 3 AP_RESET_L IN 15 20 35 114 2 3 4 5% 1/20W MF 201 EN 6 OUT 8 7 IN SMC_WIFI_PWR_EN PAD GND 9 5 113 1 50_2_ANT C3837 2 113 50_2_COM 2 COM HI 4 LO 6 0201 NO STUFF 1 1 0.2PF 35 36 46 48 CRITICAL C3836 0.2PF +/-0.05PF 25V COG-CERM 2 0201 NC (OD) THRM IN SM 0.8NH-+/-0.05NH-1.1A-0.04OHM F-ST-SM DLY +/-0.05PF 2 25V COG-CERM 0201 B 2 35 113 0201 DPX205950DT L3830 20449-001E-03 WIFI_SAK:YES U3830 CRITICAL J3830 5% 1/20W MF 201 +/-0.05PF 25V C0G 2 0201 OMIT_TABLE CRITICAL + - R3859 1 50_A_2_MATCH 2 1 TDFN VREF C3835 0.1PF SLG4AP041V 2 SENSE CRITICAL 0 1 L3833 U3850 50_A_2_DIPLEXER 2.4NH+/-0.1NH-0.6A VDD WLAN_3V3_VMON 113 CORE2 DIPLEXER AND MATCHING 1 1% 1/20W MF 201 2 B CRITICAL 232K CRITICAL CRITICAL GND L3831 2.4NH+/-0.1NH-0.6A 5 3 1 R3856 10% 2 25V X6S-CERM 0201 1 113 1 50_G_2_DIPLEXER 2 50_G_2_MATCH 35 113 0201 R3857 1 C3832 100K NO STUFF 1 1 0.2PF 5% 1/20W MF 201 2 C3830 0.2PF +/-0.05PF 2 25V COG-CERM 0201 +/-0.05PF 25V COG-CERM 2 0201 NO STUFF WIFI_SAK:NO R3854 A 1 0 2 SYNC_MASTER=J80_MLB 5% 1/20W MF 201 SYNC_DATE=11/06/2015 PAGE TITLE WIFI/BT: MODULE 2 DRAWING NUMBER Apple Inc. R BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=WIRELESS WWW.AliSaler.Com 8 7 6 5 4 3 REVISION NOTICE OF PROPRIETARY PROPERTY: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 2 SIZE 051-00647 D 10.0.0 dvt-fab10 38 OF 145 36 OF 121 SHEET 1 A T208 IC,RTM2,DEV,PN549A1,P61D0 U3905 CRITICAL SE:DEV 338S00097 1 IC,RTM2,MP,PN549A1,P61D0 U3905 CRITICAL SE:PROD PP_STOCKHOLM_TVDD STOCKHOLM PLACE_NEAR=U3901.8:2mm 1 0.22UF 41 5% 1/20W MF 2 201 38 PP1V1_SLEEP3_BUCK2 2 NOSTUFF 2 1 R3952 SOC_JTAG_SEL NC NC NC NC NC NC 37 10K 5% 1/20W MF 201 M7 needed stronger PU but should be fixed on M8 1 R3951 1K 5% 1/20W MF 201 41 39 38 37 2 AOP_DETECT_0 AD26 AOP_DETECT_1 AD27 NC NC PP1V8_SLEEP2_SW3A 2 10K 5% 1/20W MF 201 NC M25 DDR0_CKE NC L27 DDR0_CS AOP_PSENSE_CTRL_4 AOP_PSENSE_CTRL_5 AOP_PSENSE_CTRL_6 AOP_PSENSE_CTRL_7 1 R3973 PMU_TO_SOC_RESET_L 41 37 AOP_PLED_0 AOP_PLED_1 AOP_PLED_2 AOP_PLED_3 AOP_PLED_4 AOP_PLED_5 AOP_PLED_6 AOP_PLED_7 UFBGA (1 OF 7) M26 DDR0_CK_P M27 DDR0_CK_N 1 NC NC C3960 PLACE_NEAR=U3900.AA22:3mm R3990 41 20 IN SOC_PMU_CLK_32K 0 1 GREENCLK SOC_CLK_32K 2 20 37 SOC 5% 1/20W MF 0201 R3925 41 B IN PMU_TO_SOC_CLK_32K 0 1 SOC PMU 2 NOSTUFF 5% 1/20W MF 0201 PLACE_NEAR=U3900.AA22:3mm PP1V1_SLEEP1_SW2 240 NC NC 1% 1/20W MF 201 SOC_PAD_ZQ_A 1 1% 1/20W MF 201 240 2 R3902 DDR0_DQ_0 DDR0_DQ_1 DDR0_DQ_2 DDR0_DQ_3 DDR0_DQ_4 DDR0_DQ_5 DDR0_DQ_6 DDR0_DQ_7 DDR0_DQ_8 DDR0_DQ_9 DDR0_DQ_10 DDR0_DQ_11 DDR0_DQ_12 DDR0_DQ_13 DDR0_DQ_14 DDR0_DQ_15 SEP_I2C_SDA 5 SDA 37 38 BI 9 NC NC 42 37 BI 42 IN NC NC NC NC NC TP_SOC_CLKOUT 41 37 41 37 TP_SOC_JTAG_TRST_L AB11 JTAG_TRSTN SOC_SWDIO SOC_SWCLK TP_SOC_JTAG_TDI TP_SOC_JTAG_TDO OUT NC NC NC NC 1.0UF U3905 D1 NC DFR_TOUCH_SPI_MISO DFR_TOUCH_SPI_MOSI DFR_TOUCH_SPI_CLK AOP_SPI0_MISO AC22 AOP_SPI0_MOSI AC23 AOP_SPI0_SCLK AD21 NC NC NC OMIT_TABLE U3900 M8-LPDDR4-H-A-FUSE UFBGA (2 OF 7) AOP_LSPI_MISO AA20 AOP_LSPI_MOSI AB22 AOP_LSPI_SCLK AD25 AB13 AOP_DDR_REQ AOP_SPI_CS_TRIG_0 AOP_SPI_CS_TRIG_1 AOP_SPI_CS_TRIG_2 AOP_SPI_CS_TRIG_3 AOP_SPI_CS_TRIG_4 AOP_SPI_CS_TRIG_5 AOP_SPI_CS_TRIG_6 AOP_SPI_CS_TRIG_7 AOP_SPI_CS_TRIG_8 AOP_SPI_CS_TRIG_9 AOP_SPI_CS_TRIG_10 AOP_SPI_CS_TRIG_11 AOP_SPI_CS_TRIG_12 AOP_SPI_CS_TRIG_13 AOP_SPI_CS_TRIG_14 AOP_SPI_CS_TRIG_15 AE11 WDOG SOC_WDOG_RST 42 114 OUT 41 IN 42 OUT 42 OUT 42 OUT SOC_TO_STOCKHOLM_DWLD_REQ SOC_VDD_HI_LO AE12 SOC_VDD_HI_LO NC NC AC11 AOP_DOCK_ATTENTION AC12 AOP_DOCK_CONNECT 37 NC PCH_SOC_DBELL_LIN 15 20 NC PMU_TO_SOC_IRQ_L NC NC NC IN 41 37 20 41 38 IN OUT 41 37 IN AA22 RT_CLK32768 SOC_CLK_32K AB24 AWAKE_PWRGOOD AD11 AWAKE_REQ AA12 COLD_RESETN PMU_TO_SOC_AWAKE_PWRGD SOC_AWAKE_REQ PMU_TO_SOC_RESET_L UART_SOC_TO_STOCKHOLM_TXD 38 IN 38 OUT UART_STOCKHOLM_TO_SOC_TXD 38 IN UART_SOC_TO_STOCKHOLM_RTS_L 38 OUT UART_STOCKHOLM_TO_SOC_RTS_L 38 IN NC NC NC 1 R3943 78.7K 1% 1/20W MF 201 2 AOP_UART0_CTSN AOP_UART0_RTSN AOP_UART0_RXD AOP_UART0_TXD AC17 AE18 AE17 AA15 AOP_UART1_CTSN AOP_UART1_RTSN AOP_UART1_RXD AOP_UART1_TXD AA16 AE19 AD17 AC18 37 PPSVDD_STOCKHOLM NC NC NC NC NC 45 37 37 A1 E1 E3 E4 F4 B3 B4 E6 SMX_RST* SMX_CLK ESE_IO1 SPIM_MOSI SPIM_MISO SPIM_SCK NC 41 40 38 37 C3 XTAL2 1 NC NC 1 SOC_DDR_RREF 41 37 41 IN IN M24 DDR0_RESET_N N24 DDR0_RREF PMU_TO_SOC_SLEEP1_PWRGD PMU_TO_SOC_SYS_ALIVE L24 DDR0_RET_N P24 DDR0_SYS_ALIVE AOP_I2C0_SCL AB20 AOP_I2C0_SDA AE26 MESA_I2C_SCL MESA_I2C_SDA AOP_I2C1_SCL AE27 AOP_I2C1_SDA AA19 ALS_SCL_I2C_1V8 ALS_SDA_I2C_1V8 T208 DFU_STATUS Isolation 42 38 37 109 42 38 37 A R3981 38 IN DFU_STATUS 0 1 2 5% 1/20W MF 0201 6 SOT833 U3910 B Y 3 PCH_SOC_DFU_STATUS 37 SOC_SPI_BOOT_STATUS 1 5% 1/20W MF 0201 37 4 15 SOC_WDOG_RST BI 5% 1/20W MF 2 201 37 42 1 R3972 42 2.2K 41 38 B 08 Y 7 PCH_SOC_WDOG 1 4 5% 1/20W MF 2 201 SOC_PMU_I2C_SCL 41 38 NOSTUFF 109 1 OUT R3960 3.0K 15 5% 1/20W MF 2 201 R3971 100K 5% 1/20W MF 2 201 5% 1/20W MF 201 2 R3911 2.2K 5% 1/20W MF 2 201 PP1V8_S0 A U3910 1 R3905 SEP_I2C_SDA 8 74LVC2G08GT/S505 SOT833 300K 2 2.2K 1 SEP_I2C_SCL 38 37 109 2 1 WWW.AliSaler.Com 8 OUT 10% 6.3V 2 CERM-X5R 0201 08 R3980 0 37 42 R3904 C3950 0.1UF 8 74LVC2G08GT/S505 A OUT 1 1 42 37 42 37 6 C3926 0.1UF NC G1 NC 10% 2 6.3V CERM-X5R 0201 C3920 B OMIT_TABLE 4MX8-1.8V R3941 UFDFPN SOC_ROM_SPI_CLK_R IN 6 C DQ0 5 SOC_ROM_SPI_MOSI_R DQ1 2 SOC_ROM_SPI_MISO_R IN 42 N25Q032A11E 38 IN SOC_ROM_SPI_CS_L 1 3 7 S* W*/VPP/DQ2 HOLD*/DQ3 OUT 42 VSS THRM_PAD PP1V8_S0SW_DFR 1 R3912 2.2K 1 R3915 2.2K 5% 1/20W MF 2 201 R3916 2.2K 5% 1/20W MF 2 201 5% 1/20W MF 2 201 TABLE_5_HEAD 114 DFR_TOUCH_ROM_I2C_SCL 42 38 PART# QTY DESCRIPTION ALS_SCL_I2C_1V8 ALS_SDA_I2C_1V8 1 SOC_PMU_I2C_SDA 42 38 114 PP1V8_S0 R3961 R3906 1K 3.0K 5% 1/20W MF 2 201 5% 1/20W MF 2 201 114 114 76 38 76 38 I2C_CAM_SCL I2C_CAM_SDA DFR_TOUCH_ROM_I2C_SDA 42 37 114 1 1 PP1V8_S0SW_DFR 1K 1 REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION R3917 5% 1/20W MF 2 201 1 SOC_TO_STOCKHOLM_DWLD_REQ R3918 4.7K 5% 1/20W MF 2 201 SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016 1 5 PAGE TITLE Camera/DFR 1 R3940 DRAWING NUMBER 100K 5% 1/20W MF 2 201 DFRDRV_I2C_SCL 42 38 U3906 IC,FLASH,SERIAL,SPI,4MX8,4X3MM,DFN8 NOSTUFF 4.7K 5% 1/20W MF 2 201 42 38 114 37 1 R3907 114 335S00203 DFRDRV_I2C_SDA Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=T151 7 PP_STOCKHOLM_VMID 1 VOLTAGE=1.8V TABLE_5_ITEM SOC_WDOG_RESET can be driven high outside of S0 U3910 creates version that is only high in S0 PP1V8_S0 1 5 BI 45 114 T208 WDOG Isolation PP1V8_S0 DFU_SPI_STATUS 45 114 38 37 DFU_STATUS can be driven high outside of S0 U3910 creates version that is only high in S0 109 OUT 42 37 F2 SE2_PWR_REQ SE2_SVDD_IN C VCC SOC_ROM_SPI_RST_L 114 F7 37 U3906 SOC_ROM_SPI_WP_L PP1V8_AWAKE_SW3C NC A4 NC A7 NC A6 NC D5 NC G7 NC G6 NC F6 RXP NC RXN F5 NC TX1 G3 NC TX2 G5 NC WKUP_REQ E5 SOC_TO_STOCKHOLM_DEV_WAKE 4 NC 40 38 37 41 F1 ESE_DWPM_DBG ESE_DWPS_DBG R3942 5% 1/20W MF 2 201 42 I2C Pullups PP1V8_AWAKE_SW3C 10% 2 6.3V CERM-X5R 0201 10% 2 6.3V CERM-X5R 0201 5% 1/20W MF 2 201 41 40 38 37 0.1UF 0.1UF 10K R26 PAD_ZQ_A C3915 PP1V8_AWAKE_SW3C NC NC NC NC 1 NC NC NC 1 4MB SPI ROM NC NC NC NC NC NC AOP_SWD_TCK_OUT AE16 AOP_SWD_TMS0 AD16 AOP_SWD_TMS1 AB16 VOLTAGE=1.8V VMID 10K AOP_I2S0_MCK AA9 AOP_I2S1_MCK AB9 PPSVDD_STOCKHOLM SPIM_IRQ SIM_SWIO GPIO0 SPIM_NSS TX_PWR_REQ PN66VEU3-A101D004 UFLGA IRQ SVDD_REQ DWL CLK_REQ NFC_CLK_XTAL1 RX TX CTS RTS VEN NC A5 NC B2 A2 NC A3 NC C1 B1 D2 SOC_TO_STOCKHOLM_EN AE20 NC AB17 MESA_PWR_EN OUT AB18 SOC_TO_STOCKHOLM_DEV_WAKE AE21 SOC_SPI_BOOT_STATUS AD19 NC AA17 NC AC19 NC AE22 NC AE23 NC AB19 NC AA18 NC AE24 NC AD20 NC AC21 NC Y18 NC AE25 NC AOP_UART2_RXD AD18 AOP_UART2_TXD Y16 W26 DDR0_DQS_P_1 W27 DDR0_DQS_N_1 SOC_TO_STOCKHOLM_DWLD_REQ 37 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO 20% 2 6.3V X5R 0201-1 OMIT_TABLE Y12 AOP_DDR_PWRGOOD SOC_SLEEP1_REQ 37 41 E27 DDR0_DQS_P_0 F27 DDR0_DQS_N_0 C3918 20% 2 6.3V X5R 0201-1 AE10 CFSB_AOP PMU_TO_SOC_SLEEP1_PWRGD 41 DFR_TOUCH_SPI_CS_L AC13 AD10 AD9 AA11 PMU_TO_SOC_RESET_L IN IN NC NC AA24 W24 AA21 Y24 AE13 AE14 AB15 Y14 AE15 AD15 AA14 AC16 AB12 JTAG_SEL 1 NC AOP_PSPI_MISO AD24 AOP_PSPI_MOSI Y20 AOP_PSPI_SCLK AB21 AOP_MON_0 AOP_MON_1 AOP_MON_2 AOP_MON_3 AOP_MON_4 AOP_MON_5 AOP_MON_6 AOP_MON_7 42 114 OUT SOC_JTAG_SEL 37 NC D C3917 1.0UF 10% 2 6.3V CERM-X5R 0201 PP1V8_AWAKE_SW3C 41 40 38 37 1 C3916 0.1UF 1 R3901 2 41 NC NC E26 F26 G26 H26 G27 K25 H27 K26 AA25 Y25 W25 Y26 V26 U26 T26 T27 DDR0 32K CLK OPTION NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC AC10 Y10 AC14 AA13 AD12 AD13 AC15 AB14 AOP_PSPI_CS_TRIG_3 AD22 AOP_PSPI_CS_TRIG_4 AD23 J26 DDR0_DMI_0 V27 DDR0_DMI_1 100PF 5% 2 25V C0G 0201 SCL DFR_TOUCH_RESET_L AOP_PDM_CLK AA10 AOP_PDM_DAT AB10 M8-LPDDR4-H-A-FUSE 5% 1/20W MF 201 SEP_I2C_SCL 6 37 U3900 1K IN 7 4 OMIT_TABLE NOSTUFF SOC_SWDIO 42 37 41 39 DDR0_CA_0 DDR0_CA_1 DDR0_CA_2 DDR0_CA_3 DDR0_CA_4 DDR0_CA_5 37 1 PP1V8_AWAKE_SW3C VSS THM_P 1 C L25 L26 N26 N27 P26 P25 PP1V8_AWAKE_SW3C R3953 39 37 38 41 10K 10% 2 6.3V X5R-CERM 0201 unstuff R3951 and stuff R3952 to enable boundary scan PP1V8_SLEEP2_SW3A 40 41 R3970 10% 2 6.3V CERM-X5R 0201 1 41 1% 1/20W MF 201 0.47UF MLP PP1V8_SLEEP2_SW3A VOLTAGE=1.8V SVDD B7 ESE_VDD C5 C3900 1 1 E2 E1 E0 WC* C3902 2 PPVDD_STOCKHOLM AVDD D7 VOLTAGE=1.1V 0201 2 1 VOLTAGE=1.8V EEPROM 499 1 VDD18_LPPLL AA23 SEP_ROM_WC PP1V1_SLEEP1_PLL_DDR_FILT 2 VDDIO11_PLL_DDR U21 1 VDDIO11_RET_DDR N25 41 PP1V1_SLEEP1_SW2 PP1V8_SLEEP2_LPPLL_FILT U3901 M24128 3 C3919 20% 2 6.3V X5R 402 R3900 VCC 120-OHM-0.1A-1.5-OHM 20% 2 6.3V X5R 0201-1 4.7UF SEP ROM 8 VOLTAGE=1.8V C3925 1.0UF PP3V3_S0_LEFT TVSS PVSS 10% 2 6.3V CERM-X5R 0201 1 G4 C2 C3903 BOM OPTION 1 110 0.1UF D CRITICAL 338S00147 PP1V8_AWAKE_SW3C 1 L3900 REFERENCE DES 9 10 41 39 38 37 DESCRIPTION VUP G2 TVDD E7 SOC:HYNIX QTY DVSS DVSS CRITICAL PART NUMBER B6 C4 U3900 IC,M8+512MB 20NM DDR,A12,S,SCK,BGA700 BOM OPTION 1 8 CRITICAL 2 AVSS AVSS AVSS 1 REFERENCE DES 3 D4 D6 F3 343S00136 DESCRIPTION 4 C6 C7 B5 D3 QTY 5 VDD VBAT SIM_PMU_VCC PVDD PART NUMBER 6 VSS 7 E2 8 1 39 OF 145 37 OF 121 SIZE D A 6 5 PP1V8_AWAKE_SW3C 1 R4023 38 100K 38 5% 1/20W MF 2 201 41 41 37 E3 REQUEST_DFU1 D1 REQUEST_DFU2 SOC_REQUEST_DFU1 SOC_REQUEST_DFU2 PMU_TO_SOC_VDD_OK IN PP1V8_AWAKE_SW3C 2 R4017 OUT PP1V1_SLEEP1_SW2 41 PP3V0_AWAKE_LDO7 38 41 R4022 1 UFBGA (3 OF 7) USB_VBUS K6 OMIT_TABLE USB_CAMERA_DFR_P USB_CAMERA_DFR_N BI 10K 5% 1/20W MF 2 201 14 113 BI 14 113 R4001 NC USB_REXT H4 SOC_USB_REXT 1 200 5% 1/20W MF 2 201 1 C NC NC NC 39 IN 39 IN 39 IN 39 IN 39 OUT 42 IN 114 114 IN 42 45 IN 37 OUT 42 IN SOC_BOARD_ID_3 SOC_BOARD_REV_0 SOC_BOARD_REV_1 SOC_BOARD_REV_2 PP1V8_AWAKE_SW3C DFR_DISP_RST_L DFR_TOUCH_INT_L MESA_SNSR_INT SOC_TO_STOCKHOLM_EN DFR_DISP_INT NC NC SOC_PMU_I2C_SCL SOC_PMU_I2C_SDA DFR_TOUCH_ROM_I2C_SCL DFR_TOUCH_ROM_I2C_SDA OUT 41 37 BI 114 42 37 OUT 114 42 37 BI 114 114 42 37 DFRDRV_I2C_SCL DFRDRV_I2C_SDA OUT 42 37 B8 C8 A8 D8 BI NC NC B 42 39 IN 42 39 OUT 42 39 OUT 37 OUT 45 IN 42 OUT 42 OUT SOC_ROM_SPI_MISO SOC_ROM_SPI_MOSI SOC_ROM_SPI_CLK SOC_ROM_SPI_CS_L MESA_SPI_MISO MESA_SPI_MOSI MESA_SPI_CLK NC SOC_XTAL_24M_I TMR32_PWM0 D18 TMR32_PWM1 E18 TMR32_PWM2 A23 R4003 2 4.02K 2 1 D5 NC B3 NC C4 PCH_ALS_TO_SOC_UART_TXD B4 SOC_TO_PCH_ALS_UART_TXD UART2_RTSN UART2_CTSN UART2_RXD UART2_TXD E6 A4 B5 D6 UART4_RXD UART4_TXD UART5_RXD UART5_TXD I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA I2C2_0_SCL I2C2_0_SDA I2C2_1_SCL I2C2_1_SDA E10 D10 B10 A10 SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN I2S0_BCLK I2S0_LRCK I2S0_DIN I2S0_DOUT I2S1_BCLK I2S1_LRCK I2S1_DIN I2S1_DOUT SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN I2S2_BCLK I2S2_LRCK I2S2_DIN I2S2_DOUT AA8 XI0 AB8 XO0 OUT 42 114 38 114 38 114 76 37 OUT IN 42 OUT 42 OUT 37 IN 37 IN 37 OUT 37 MIPIC_CLK_P MIPIC_CLK_N L1 MIPI1C_DPCLK L2 MIPI1C_DNCLK I2C_CAM_SDA I2C_CAM_SCL UFBGA (4 OF 7) 5% 1/20W MF 2 201 OMIT_TABLE NC NC NC NC A12 RMII_CLK A11 RMII_CRSDV NC NC NC B11 RMII_RXD_0 F10 RMII_RXD_1 B12 RMII_RXER NC NC NC E11 RMII_TXD_0 C10 RMII_TXD_1 C11 RMII_TXEN NC NC B14 SD_CLKOUT E13 SD_CMD_IO A14 C13 F12 B13 MIPID_CLK_P MIPID_CLK_N MIPI0D_DPCLK J2 MIPI0D_DNCLK J1 SOC_REQUEST_DFU2 38 BI 42 114 BI 42 114 OUT 42 114 OUT 42 114 R4004 SOC_MIPI0D_REXT MIPI0D_REXT K2 DISP_VSYNC C2 DISP_TE D2 D12 ENET_MDC C12 ENET_MDIO MIPID_DATA_P MIPID_DATA_N MIPI0D_DPDATA0 H1 MIPI0D_DNDATA0 H2 B2 ISP0_SDA A2 ISP0_SCL 38 DFR_DISP_VSYNC DFR_DISP_TE 1 IN 42 114 IN 42 114 PLACE_NEAR=U3900.K2:3mm 1% 1/20W MF 201 PP1V8_AWAKE_SW3C 1 4.02K 2 37 38 40 41 R4024 100K C 5% 1/20W MF 2 201 NAND_CEN_0 D17 NAND_CEN_1 B20 A13 SDIO_IRQ NC E12 WL_HOST_WAKE NC NC B1 SWD_TMS2 F5 SWD_TMS3 NC C1 ANALOGMUX_OUT NC NC NC NC NC NC NC NAND_REN A20 NAND_WEN A18 NC NC MON_0 MON_1 MON_2 MON_3 MON_4 MON_5 MON_6 MON_7 H6 BB_HSIC_DATA F2 BB_HSIC_STROBE SOC_NAND_CEN_0 NAND_ALE D15 NAND_CLE C16 NAND_IO_0 NAND_IO_1 NAND_IO_2 NAND_IO_3 NAND_IO_4 NAND_IO_5 NAND_IO_6 NAND_IO_7 SD_DATA_IO_0 SD_DATA_IO_1 SD_DATA_IO_2 SD_DATA_IO_3 NC NC NC NC NC B15 F14 D13 A15 R4037 10K 5% 1/20W MF 2 201 K1 MIPI1C_REXT NC NC NC NC NC NC NC NC C14 B16 E14 A16 38 BI NC NC NC NC B17 C15 E15 A17 114 76 37 NC A5 B6 C5 C6 38 114 To/From PCH for ALS UART_SOC_TO_STOCKHOLM_RTS_L UART_STOCKHOLM_TO_SOC_RTS_L UART_STOCKHOLM_TO_SOC_TXD UART_SOC_TO_STOCKHOLM_TXD UART3_RTXD E7 E8 B7 C7 A7 A9 C9 B9 E9 UART1_RTSN UART1_CTSN UART1_RXD UART1_TXD 114 M3 MIPI1C_DPDATA0 M2 MIPI1C_DNDATA0 SOC_MIPI1C_REXT To/From PCH for logging/debug 42 10K M8-LPDDR4-H-A-FUSE MIPIC_DATA_P MIPIC_DATA_N 1% 1/20W MF 201 IN 1 R4036 37 38 40 41 U3900 NC NC NC UART0_RXD A6 PCH_TO_SOC_UART_TXD UART0_TXD D7 SOC_TO_PCH_UART_TXD 1 PP1V8_AWAKE_SW3C 37 38 40 41 SOC_REQUEST_DFU1 NOSTUFF PLACE_NEAR=U3900.K1:2mm 1% 1/20W MF 201 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 PP1V8_AWAKE_SW3C 42 110 SOC_USB_VBUS USB_ID J3 37 38 39 41 R4042 PLACE_NEAR=U3900.H4:2mm C23 F20 C22 E20 D25 C24 D21 C25 E19 D20 C21 A22 B22 B23 D19 F18 C19 B21 SOC_BOOT_CONFIG_0 113 10% 2 6.3V X5R-CERM 0201 E2 CLK32K_OUT DFR_CLKIN_RESET_L NC NC 41 37 0.22UF USB_DP G1 USB_DM G2 M8-LPDDR4-H-A-FUSE T6 TST_CLKOUT 1/20W MF 201 NOSTUFF VDD11_XTAL Y8 U3900 PP1V8_AWAKE_SW3C D C4050 10K A3 TESTMODE 2.2K 5% C4003 PP3V3_S4_SOC_PMU C3 HOLD_RESET TP_SOC_TST_CKOUT CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND 0201 1 D3 CFSB SOC_BOOT:SPI 38 37 41 39 1 10% 2 6.3V CERM-X5R 0201 10% 2 6.3V CERM-X5R 0201 2 VOLTAGE=1.1V C4008 0.1UF 0.1UF R3 DROOP_N PMU_TO_SOC_AWAKE_PWRGD IN P1 DFU_STATUS F4 FORCE_DFU VDD_FIXED_USB J5 SOC_FORCE_DFU DFU_STATUS VDD30_USB H3 OUT VDD18_USB J6 37 VDD18_TSADC J22 47K VDD11_UVD H10 10% 2 6.3V CERM-X5R 0201 R4035 1 PP1V1_SLEEP1_XTAL_FILT VDD11_PLL_SOC0 J12 VDD11_PLL_SOC1 H12 SOC_BOOT:DFU 38 C4000 0.1UF 5% 1/20W MF 2 201 1 120-OHM-0.2A-0.5-OHM 1 1 PP0V8_SLEEP1_SW1 L4010 PP1V1_SLEEP1_SW2 PP1V8_S4 42 41 1 41 VDD18_AMUX G4 10% 2 6.3V CERM-X5R 0201 1 K4 N4 0.1UF 41 10% 2 6.3V CERM-X5R 0201 10% 2 6.3V CERM-X5R 0201 10% 2 6.3V CERM-X5R 0201 20% 2 6.3V X5R 0201-1 0.1UF 0.1UF PP1V1_SLEEP1_SW2 C4005 PP0V8_SLEEP1_SW1 0.1UF VDD_FIXED_MIPI C4001 41 1 C4004 C4007 L4 M4 1 1 1 1.0UF VDD18_MIPI PP1V8_AWAKE_SW3C 41 39 38 37 C4006 1 VDD_FIXED_HSIC G5 10% 2 6.3V CERM-X5R 0201 109 PP3V0_AWAKE_LDO7 41 38 0.1UF 2 PP1V8_AWAKE_SW3C 41 C4002 3 VDD12_HSIC G3 1 D 4 G24 G23 V23 U23 F24 F3 41 7 VDD18_EFUSE1 VDD18_EFUSE2 VDD18_EFUSE3 VDD18_EFUSE4 VDD18_EFUSE5 VDD18_EFUSE6 8 E16 A19 B18 D16 C17 A21 B19 E17 NC NC NC NC NC NC NC NC N3 NC P6 DFR_TOUCH_PANEL_DETECT P4 DFR_TOUCH_GPIO2 P3 DFR_TOUCH_ROM_WC N2 SOC_PANIC_L P5 S2R_ACK_L 38 R4 SOC_PCH_DBELL_L P2 NC 42 114 BI BI OUT OUT IN 42 114 42 114 15 B 15 20 MIPIC FILTERING L4002 SEP_GPIO0 D24 SEP_GPIO1 E21 NC NC SEP_SPI0_MISO D22 SEP_SPI0_MOSI F22 SEP_SPI0_SCLK E24 NC NC NC GND_VOID=TRUE 114 SEP_I2C_SCL E22 SEP_I2C_SDA D23 SEP_I2C_SCL SEP_I2C_SDA 38 MIPIC_DATA_P 1 4 2 3 114 38 L4003 SYM_VER-1 GND_VOID=TRUE 38 BI 76 BI 76 MIPIC_CLK_P PLACE_NEAR=J8500:2.54mm GND_VOID=TRUE 1 4 2 3 GND_VOID=TRUE 114 MIPI_DATA_CONN_N 3.25-OHM-0.1A-2.4GHZ TAM0605-4SM 37 BI MIPI_DATA_CONN_P GND_VOID=TRUE MIPIC_DATA_N 37 OUT GND_VOID=TRUE SYM_VER-1 GND_VOID=TRUE 38 114 PLACE_NEAR=J8500:2.54mm 3.25-OHM-0.1A-2.4GHZ TAM0605-4SM MIPI_CLK_CONN_P OUT 76 OUT 76 GND_VOID=TRUE MIPIC_CLK_N MIPI_CLK_CONN_N L4004 R4010 1 499K 2 113 T208 SOC_S2R_ACK_L bi-directional Isolation SOC_XTAL_24M_O 110 1% 1/20W MF 201 1 42 PP3V3_S0_LEFT 109 1 38 15 SOC_S2R_ACK_L BI S2R_ACK_L 4 PCH 1 12PF 5% 1/20W MF 2 201 12PF 5% 50V 2 C0G-CERM 0201 R4080 200K C4040 5% 2 50V C0G-CERM 0201 SYM_VER_1 C4041 2 38 S2R_ACK_L T208 1 6 NOSTUFF 74LVC1G08FW5 B U4080 A Y DFN1010 4 SOC_S2R_ACK_L OUT 15 38 5% 1/20W MF 2 201 3 T208 R4070 47K NC 38 42 38 37 SOC_BOOT:DFU 1 PCH NC 5 109 15 NOSTUFF 1 1 S 2 SOC_XTAL_24M_O_R D 113 R4082 110 PP5V_S0 1 IN C4070 10% 2 6.3V CERM-X5R 0201 PCH_SOC_FORCE_DFU 2 1 1 0.1UF 10% 2 10V X5R-CERM 0201 B U4070 A Y DFN1010 4 SOC_FORCE_DFU SYNC_MASTER=X362_T208 38 SYNC_DATE=03/22/2016 PAGE TITLE NC Camera/DFR 2 T208 3 DRAWING NUMBER NC DMN32D2LFB4 Apple Inc. DFN1006H4-3 R4071 1 0 051-00647 REVISION R 2 5% 201 1/20W SOC_BOOT:SPI MF NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=T151 WWW.AliSaler.Com 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 7 C4062 SOC_BOOT:DFU 74LVC1G08FW5 6 5 Q4000 to act as bi-directional islation for SOC_S2R_ACK_L When in system S0 and M8 AWAKE, FET will be on & line will be pulled high Below S0, SOC_S2R_ACK_L will be low and FET will be open (isolated from M8 power rails) When M8 enters S2R, FET will be on, PP1V8_AWAKE_SW3C will turn off and SOC_S2R_ACK_L will be low 8 76 114 0.1UF PCH Q4000 PP5V_S0_ALSCAM_F VOLTAGE=5V SOC_FORCE_DFU should be pulled up to S4 In the SOC_BOOT:DFU option U4070 prevents it from leaking into PCH PP1V8_S0 SOC_BOOT:DFU 1 2 0402A T208 FORCE_DFU Isolation NOSTUFF 10% 2 6.3V CERM-X5R 0201 5% 1/20W MF 2 201 G 3 2 1 C4080 115 10K 3 24.000MHZ-30PPM-9.5PF-60OHM A 1% 1/20W MF 2 0201 T208 SOC_S2R_ACK_L Isolation (NOSTUFF) PP1V8_S0 0.1UF 1 0.00 Y4000 1.60X1.20MM-SM 1 PP1V8_AWAKE_SW3C R4020 42 38 37 FERR-120-OHM-1.5A 1 40 OF 145 38 OF 121 SIZE D A 7 6 5 4 3 2 1 4.3UF 4 2 20% 4V CER-X5R 0402 4.3UF 4 20% 4V CER-X5R 0402 AB23 W12 W16 W18 Y13 Y15 Y19 Y22 Y9 PP1V8_SLEEP2_SW3A 41 37 1 C4112 1 1.0UF 0.1UF 10% 6.3V 2 X5R 0201 20% 2 6.3V X5R 0201-1 PP1V8_AWAKE_SW3C 41 39 38 37 1 C4113 C4114 1 1.0UF VDD_SOC VDDIO18_AOP E5 F19 F21 F7 F9 VDDIO18_GRP0 G10 G12 G14 G16 R5 VDDIO18_GRP1 C4115 0.1UF 20% 2 6.3V X5R 0201-1 VDD2 10% 2 6.3V CERM-X5R 0201 H23 VDD18_FMON 41 1 AB25 AB26 B25 B26 D28 F28 H28 J23 K23 L23 M23 N23 P23 R23 R27 T23 U27 U28 Y28 PP1V1_SLEEP1_SW2 C4116 1 0.1UF 3 1 3 C4117 10% 2 6.3V CERM-X5R 0201 2 C4118 4.3UF 4 2 20% 4V CER-X5R 0402 4.3UF 4 20% 4V CER-X5R 0402 B PP0V8_SLEEP2_BUCK1 41 1 W10 W15 W19 Y21 C4119 0.1UF 10% 2 6.3V CERM-X5R 0201 41 39 L17 M14 M18 M20 M22 M8 N11 N5 P12 P14 P18 P20 P22 P8 T12 T14 T18 T20 T22 V13 V21 W13 W9 Y23 PP0V8_SLEEP1_SW1 1 C4121 1 0.1UF 3 1 3 C4122 10% 2 6.3V CERM-X5R 0201 2 1 4 20% 2 6.3V X5R 0201-1 4.3UF 2 20% 4V CER-X5R 0402 C4141 1.0UF C4123 1 4 4.3UF 20% 4V CER-X5R 0402 C4142 2.2UF 20% 2 6.3V X5R-CERM 0201 A VDDIO11_DDR VDD_SOC_AON VDD_SRAM_AON VDD_SRAM VDD_SRAM V14 V16 V18 V20 W17 W21 Y11 F13 F17 F23 F6 F8 G11 G13 G15 G18 G21 G9 H17 H20 H22 J11 J13 J17 J7 K14 K20 K22 K5 K8 L11 C4109 2.2UF 20% 2 6.3V X5R-CERM 0201 1 4 20% 4V CER-X5R 0402 3 1 4 C4111 4.3UF 2 20% 4V CER-X5R 0402 PP0V6_SLEEP2_LDO0 4 41 1 20% 4V CER-X5R 0402 3 C4110 2 4.3UF C4120 0.1UF 10% 2 6.3V CERM-X5R 0201 PP0V8_SLEEP1_SW1 4.3UF 20% 4V CER-X5R 0402 A1 A25 A26 A28 AA1 AA26 AA27 AA28 AA4 AB27 AB28 AC20 AC26 AC9 AD14 AD28 AD5 AE1 AE28 B27 B28 C18 C20 C26 C28 D11 D14 D26 D27 D4 D9 E1 E23 E25 E28 F1 F16 F25 G20 G25 G28 G7 H11 H13 H15 H19 H21 H24 H25 H5 H7 H9 J10 J14 J16 J18 J20 J24 J25 J27 J4 J8 K11 K13 K15 K17 K19 K21 K24 K3 K7 K9 L10 L12 L14 L16 L18 L20 U3900 M8-LPDDR4-H-A-FUSE UFBGA (6 OF 7) OMIT_TABLE VSS VSS L22 L28 L3 L6 L8 M11 M13 M15 M17 M19 M21 M5 M9 N10 N12 N14 N16 N18 N20 N22 N28 N8 P11 P13 P15 P17 P19 P21 P27 P9 R10 R12 R14 R16 R18 R20 R22 R24 R25 R8 T11 T13 T15 T17 T19 T21 T24 T25 T7 T9 U10 U12 U14 U16 U18 U20 U22 U24 U25 U6 U8 V11 V15 V17 V19 V24 V25 V28 V7 V9 W14 W20 W22 W28 W6 W8 Y17 Y27 U3900 M8-LPDDR4-H-A-FUSE UFBGA (7 OF 7) AC8 CFSB_MAR T208_PROG:REV0 T208_PROG:REV1 T208_PROG:REV2 T208_PROG:REV3 T208_PROG:REV4 T208_PROG:REV5 MAR_SYSALIVE AC6 T2 MAX_RX_IP T1 MAX_RX_IM MAR_TX_THROTTLE_N AD2 MAR_BT_RFIC_IRQ AB1 MAR_WL_RFIC_IRQ AC1 R1 MAX_RX_QP R2 MAX_RX_QM MAR_RFIC_PDET_0 AC2 MAR_RFIC_PDET_1 AB2 V1 MAX_TX_IP V2 MAX_TX_IM MAR_VDD1V2_PWR_REQ AB3 MAR_VDD1V2_FORCE_PWM AD1 W1 MAX_TX_QP W2 MAX_TX_QM MAR_RF_SWITCH_CTRL_0 AD8 MAR_RF_SWITCH_CTRL_1 AE7 MAR_RF_SWITCH_CTRL_2 AE9 U1 MAX_TX_BTAP U2 MAX_TX_BTAM MAR_RFIC_EN AA7 MAR_PA_EN AC7 MAR_PA_CTRL AD7 Y1 MAX_TX_WLETP Y2 MAX_TX_WLETM T3 MAX_FREF T5 MAX_TEST_OUT M7 N7 R6 R7 U7 V4 V6 AA3 M6 P7 T8 V8 W5 W7 Y4 Y5 Y6 Y7 MAR_ETIC_GPIO_0 AD6 MAR_ETIC_GPIO_1 AE8 CKPLUS_WAIVE=PWRTERM2GND MAR_RFFE_SCLK AD3 MAR_RFFE_SDATA AA5 CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND C MAR_SPARE_0 AA2 MAR_SPARE_1 AB4 MAR_SPARE_2 AC3 CKPLUS_WAIVE=PWRTERM2GND VDD_SOC_MAR CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND MAR_SPI_CLK MAR_SPI_CS MAR_SPI_DATA_0 MAR_SPI_DATA_1 MAR_SPI_DATA_2 MAR_SPI_DATA_3 MAR_SPI_DATA_4 MAR_SPI_DATA_5 MAR_SPI_DATA_6 MAR_SPI_DATA_7 CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND VDD_SRAM_MAR CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND VDDIO18_MAR CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND AD4 AE2 AC4 AB5 AE3 AE4 AE5 AA6 AC5 AB6 MAR_COEX_UART_RXD AB7 MAR_COEX_UART_TXD AE6 T208 BOARD REV/BOARD ID S/W READ FLOW 1. 2. 3. 4. SET GPIO AS INPUT DISABLE PU AND ENABLE PD READ DISABLE PD AND ENABLE PU PP1V8_AWAKE_SW3C B 37 38 39 41 41 39 38 37 T208_CONFIG2_H T208_CONFIG1_H R4100 2.2K 5% 1/20W MF 201 5% 1/20W MF 201 R4102 5% 1/20W MF 201 ID_3 reserved for DEV 38 SOC_BOARD_ID_3 38 SOC_BOARD_REV_2 SOC_BOARD_REV_1 42 38 38 SOC_BOARD_REV_0 42 38 38 42 38 R4104 2.2K 5% 1/20W MF 201 Camera/DFR 3 DRAWING NUMBER Apple Inc. T208_CONFIG2_H,T208_CONFIG0_H 051-00647 REVISION R TABLE_BOMGROUP_ITEM NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=T151 WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 TABLE_BOMGROUP_ITEM T208_CONFIG1_H 2.2K 5% 1/20W MF 201 SYNC_DATE=04/25/2016 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 2.2K 5% R4106 SYNC_MASTER=X362_T208 TABLE_BOMGROUP_ITEM T208_CONFIG1_H, T208_CONFIG0_H R4105 SOC_ROM_SPI_MOSI SOC_ROM_SPI_CLK PAGE TITLE T208_CONFIG2_H NOSTUFF 1/20W MF 201 SOC_ROM_SPI_MISO TABLE_BOMGROUP_ITEM T208_CONFIG2_H,T208_CONFIG1_H,T208_CONFIG0_H T208_CONFIG2_H,T208_CONFIG1_H 2.2K 5% BOARD ID[3:0] MODE 1XXX T202 DEV 0010 T208 P0) P0) P1) P2) P2/X362 localEVT) EVT/X362 EVT1) BOM OPTIONS R4103 1/20W MF 201 PP1V8_AWAKE_SW3C (X362 (X363 (X362 (X362 (X363 (X363 NOSTUFF NOSTUFF 2.2K 38 BOARD REV[3:0] MODE 1111 T208_Rev0 1110 T208_Rev1 1101 T208_Rev2 1100 T208_Rev3 1011 T208_Rev4 1010 T208_Rev5 PP1V8_AWAKE_SW3C T208_CONFIG0_H R4101 2.2K TABLE_BOMGROUP_HEAD BOM GROUP D OMIT_TABLE 2 2 C4108 1 2 1 C4107 10% 2 6.3V CERM-X5R 0201 C 3 4.3UF 4 2 1 2 1 0.1UF 3 C4104 C4103 10% 2 6.3V CERM-X5R 0201 3 2 1 1 3 1 C4106 1 2 1 OMIT_TABLE 0.1UF 1 PP1V1_SLEEP3_BUCK2 41 A27 AC25 AC27 B24 J28 K27 M1 M28 P28 T28 (5 OF 7) C4102 VSS_MXL D VDD1 CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND U3 V3 W3 W4 Y3 10% 6.3V 2 CERM-X5R 0201 1 2 20% 2 6.3V X5R 0201-1 UFBGA 1 0.1UF M8-LPDDR4-H-A-FUSE 2 1.0UF C4101 PP0V6_SLEEP1_BUCK0 1 1 E4 F11 F15 G17 G19 G22 G6 G8 H14 H16 H18 H8 J15 J19 J21 J9 K10 K12 K16 K18 L13 L15 L19 L21 L5 L7 L9 M10 M12 M16 N13 N15 N17 N19 N21 N6 N9 P10 P16 R11 R13 R15 R17 R19 R21 R9 T10 T16 U11 U13 U15 U17 U19 U9 V10 V12 V22 W11 W23 2 C4100 1 U3900 1 A24 AC24 AC28 C27 K28 N1 R28 PP1V8_SLEEP3_BUCK3 41 CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND VDD12_MAR_PLL VDD12_MAR_LV VDD12_MAR_HV VDD12_MAR_BG T4 U4 V5 U5 8 1 41 OF 145 39 OF 121 SIZE D A 8 7 6 5 4 3 2 1 Berkelium PP0V8_SLEEP2_BUCK1 FB for Bucks 40 41 110 8 Q4201 SON2X2 PLACE_NEAR=U4200.F12:2mm PP3V3_S4_SOC_PMU PP0V8_SLEEP1_SW1 CRITICAL PLACE_NEAR=U4200.A7:2mm CRITICAL C4204 1 1 15UF 1 15UF 20% 2 6.3V CERM 0402 NC 40 110 SW1_EXT_ON 1 C4219 2.2UF BUCK0_LX A6 SOC_PMU_BUCK0_LX 1 2 PLACE_NEAR=U4200.M4:2mm C4220 C4218 M4 N2 L8 L3 PLACE_NEAR=U4200.L8:2mm NC NC NC NC PP3V0_AWAKE_LDO7 NC 1 110 41 40 PP3V3_S4_SOC_PMU NC NC NC VOLTAGE=1.8V PP1V8_ALWAYS_LDO9 C4227 0.22UF 20% 2 10V CERM-X5R 0201 1 NC C4226 0.022UF 10% 2 6.3V X5R-CERM 0201 41 1 VOLTAGE=0.6V M5 N4 M1 N3 N5 M2 M10 M6 M9 N7 2 B 1 0 2 PP1V8_SLEEP3_BUCK3 40 41 MCFK2012-SM 1 C4208 15UF 40 C4209 1 15UF 20% 2 6.3V CERM 0402 20% 2 6.3V CERM 0402 1 PP0V6_SLEEP1_BUCK0 C4210 2.2UF 40 41 C4230 1 2.2UF VDD_SOC 501MA MAX 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V X5R-CERM 0201 C L4203 SOC_PMU_BUCK1_LX BUCK1_FB D9 SOC_PMU_BUCK1_FB 1 MCFK1608T1R0M NA 1 CRITICAL C4211 1 4.2UF 40 PP0V8_SLEEP2_BUCK1 C4231 1 4.2UF 10% 2 16V X5R-CERM 0402-1 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE VDD_HVLDO_237 VDD_HVLDO_45 VDD_HVLDO_RTC VDD_HVLDO_SW6 CRITICAL 2 1 C4233 VDD_SRAM_AON VDD_SRAM VDD_SOC_AON C4232 4.7UF 4.7UF 20% 6.3V 2 CER-X5R 0402 20% 2 6.3V CER-X5R 0402 10% 2 16V X5R-CERM 0402-1 40 41 VDD_FIXED_MIPI VDD_FIXED_USB 300MA MAX CRITICAL CRITICAL Mirror Capacitors in Layout CRITICAL Place same side as PMU L4204 VDD2 VDDQ 1.0UH-1.3A-0.326OHM LDO2_OUT LDO3_OUT LDO4_OUT LDO5_OUT LDO7_OUT SW4_OUT BUCK2_LX A3 SOC_PMU_BUCK2_LX BUCK2_FB C2 SOC_PMU_BUCK2_FB 1 2 MCFK1608T1R0M NA 1 CRITICAL CRITICAL C4238 1 10UF 40 C4239 10UF 20% 6.3V 2 CERM-X5R 0402 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE CRITICAL 20% 2 6.3V CERM-X5R 0402 1 PP1V1_SLEEP3_BUCK2 C4240 1 4.7UF 40 41 VDD11_XTAL C4241 CRITICAL 460MA MAX 4.7UF 20% 2 6.3V CER-X5R 0402 20% 2 6.3V CER-X5R 0402 Mirror Capacitors in Layout 2.2UF 20% 6.3V X5R-CERM 0201 40 41 Mirror Capacitors in Layout H1 BB_OUT 20% 2 6.3V X5R-CERM 0201 41 CRITICAL CRITICAL MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE G1 BB_LX2 2.2UF 20% 2 6.3V X5R-CERM 0201 PP1V1_SLEEP3_BUCK2 L4202 PP3V3_S4_SOC_PMU 1 2 CRITICAL Place same side as PMU J3 BB_FB 1 0 1.0UH-1.82A-0.203OHM BUCK1_LX A9 41 40 1 CRITICAL Place same side as PMU 1.0UH-1.3A-0.326OHM 110 40 41 SYM 1 OF 2 20% 2 6.3V CERM 0402 PLACE_NEAR=U4200.E1:3mm PP0V8_SLEEP1_SW1 5% 1/16W MF-LF 402 WLCSP 15UF C 1 SOC_PMU_BUCK3_FB 40 U4200 C4207 2 R4203 D2346A1-OTP-CE CRITICAL 0 5% 1/16W MF-LF 402 BUCK0_FB C9 SOC_PMU_BUCK0_FB C6 SW0_EXT D7 SW1_EXT E1 BB_LX1 PP3V3_S4_SOC_PMU 41 40 VDD_MAIN_BUCK0 VDD_MAIN_BUCK1 VDD_MAIN_BUCK2 VDD_MAIN_BUCK3 VDD_MAIN_BUCK4 PLACE_NEAR=U4200.A2:2mm 1 SOC_PMU_BUCK2_FB 40 C4206 20% 2 6.3V CERM 0402 D R4202 15UF 20% 2 6.3V CERM 0402 40 41 5% 1/16W MF-LF 402 CRITICAL C4205 SOC_PMU_BUCK1_FB NC 41 40 41 40 PP3V3_S4_SOC_PMU VBAT_S K10 110 PP0V6_SLEEP1_BUCK0 R4201 NC NC NC 7 C4202 40 VBAT K12 VBAT L12 VBAT M12 4 41 40 2 5% 1/16W MF-LF 402 20% 2 6.3V CERM 0402 PLACE_NEAR=U4200.K11:2mm 110 0 1 15UF VDD_MAIN_SW4 L2 S 1 20% 2 6.3V CERM 0402 SOC_PMU_BUCK0_FB 40 CRITICAL 15UF CSD58892Q2 G C4203 NC SW1_EXT_ON PLACE_NEAR=U4200.D1:2mm ACT_DIODE* K3 40 3 1 R4200 40 41 110 CRITICAL D D PP3V3_S4_SOC_PMU VDD_MAIN_BBCORE J1 6 VDD_MAIN_CHG K11 VDD_MAIN_CHG L11 VDD_MAIN_CHG M11 5 VDD_MAIN_BB D1 2 A7 A8 A2 F12 G12 1 PP3V3_S4_SOC_PMU 41 40 20% 2 6.3V X5R-CERM 0201 B10 SW1_IN 41 40 PP0V8_SLEEP1_SW1 A11 SW1_OUT C10 LDO0_OUT 41 40 41 PP1V1_SLEEP3_BUCK2 L4205 LDO1_OUT LDO6_OUT LDO8_OUT LDO9_OUT AUX_PWR_OUT PP0V8_SLEEP2_BUCK1 PP0V6_SLEEP2_LDO0 CRITICAL Place same side as PMU 1.0UH-1.3A-0.326OHM 41 40 C4228 2.2UF N10 N9 N6 M8 N8 VDD_MAIN_LDO_16 VDD_MAIN_LDO_8 VDD_MAIN_LDO_9 VDD_MAIN_LDO_AUX CKPLUS_WAIVE=PWRTERM2GND SOC_PMU_BUCK3_LX BUCK3_FB D10 SOC_PMU_BUCK3_FB BUCK4_LX H12 B12 SW3_IN 41 37 PP1V8_SLEEP2_SW3A B11 SW3A_OUT C11 SW3B_OUT C12 SW3C_OUT 41 38 37 PP1V8_AWAKE_SW3C NC VSS_BB VSS_BUCK0 VSS_BUCK1 VSS_BUCK2 VSS_BUCK3 VSS_BUCK4 K1 SW5_IN L1 SW5_OUT NC K2 SW6_OUT MCFK1608T1R0M NA C4234 4.7UF 20% 2 6.3V CER-X5R 0402 CRITICAL CRITICAL CRITICAL 1 C4235 4.7UF 20% 6.3V 2 CER-X5R 0402 CRITICAL 1 C4236 4.7UF 20% 2 6.3V CER-X5R 0402 1 C4237 B 100MA MAX 4.7UF 20% 2 6.3V CER-X5R 0402 Mirror Capacitors in Layout NC NC F1 A5 A10 A4 D12 J12 VSS1 VSS2 VSS3 VSS3 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS4 VSS6 VSS7 VSS8 VSS8 VSS8 VSS8 VSS8 VSS8 VSS8 VSS9 VSS9 VSS9 VSS9 A NC VDD1 VDD18_USB VDDIO18_GRP0 PP1V8_SLEEP3_BUCK3 Not using Buck4 BUCK4_FB J10 PP1V8_SLEEP3_BUCK3 2 40 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE B1 SW2_IN 41 40 1 1 C1 SW2_OUT PP1V1_SLEEP1_SW2 BUCK3_LX E12 SYNC_MASTER=X362_T208 SYNC_DATE=01/27/2016 Berkelium - 1 B2 B9 C4 C5 E5 E6 H5 H6 F5 F6 G5 G6 M3 M7 G8 H7 H8 E7 F7 F8 G7 A1 A12 N1 N12 PAGE TITLE DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=T151 WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 42 OF 145 40 OF 121 SIZE D A 8 7 6 5 4 3 2 1 Berkelium - 2 BUCK0 D 117 39 PP0V6_SLEEP1_BUCK0 T208 POWER ALIASES PP0V6_SLEEP1_BUCK0 39 PP0V8_SLEEP2_BUCK1 PP0V8_SLEEP2_BUCK1 39 PP0V6_SLEEP2_LDO0 PP0V6_SLEEP2_LDO0 VOLTAGE=0.6V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE 40 40 D U4200 D2346A1-OTP-CE BUCK1 B4 VBUS_DET* SHDN RESET_IN1 RESET_IN2 INCKT_OTP PP1V8_SLEEP2_SW3A 1 E11 B7 B8 SYS_ALIVE ACTIVE_REQUEST ACTIVE_PWRGOOD SLEEP1_REQUEST SLEEP1_PWRGOOD SOC_VDD_CORE_HI_LO D11 D6 E9 D5 E10 F2 R4305 5% 1/20W MF 2 201 C IRQ* RESET* VDD_OK 41 10K PMU_TO_SOC_SYS_ALIVE 37 41 NOSTUFF NOSTUFF R4307 2 C4300 3.92K 1% 100PF 1 5% 2 25V C0G 0201 1/20W MF 201 OMIT XW4300 SHORT-8L-0.1MM-SM 1 2 PMU_TCAL_GND B 10% 2 16V X5R-CERM 0201 R4308 200K 0.1% 1/20W TF 0201 1 BUTTON1 BUTTON2 BUTTON3 DBLCLICK_DET E2 D3 D4 C3 C4302 1 0.1UF C4303 0.01UF 10% 2 25V X5R-CERM 0201 10% 2 16V X5R-CERM 0201 L9 L6 N11 J5 L7 D2 TCAL VREF IREF VDD_RTC_DIG VDD_RTC VPUMP AMUX_IN1 AMUX_IN2 AMUX_IN3 AMUX_IN4 AMUX_OUT VSS8 VSS8 VSS8 VSS8 VSS8 0.1UF PMU_VDD_RTC PMU_VPUMP 2 C4301 PMU_IREF 1 1 H4 NTC1 NTC2 NTC3 NTC4 TBAT C7 B5 B6 C8 D8 F9 F10 F11 G9 G10 G11 H9 H10 H11 J11 K6 L4 J6 K5 L5 J9 J2 K4 J4 L10 To T208, Device ID=0x3C, READ=0x79, WRITE-0x78 R4320 MF 0 1/20W 201 1 2 SMBUS_SOC_PMU_SCL IN 49 1 2 SMBUS_SOC_PMU_SDA 49 BI R4321 5% 1/20W 201 0 MF To SMC, Device ID=0x3C, READ=0x79, WRITE-0x78 PP3V3_S4_SOC_PMU 41 40 110 37 38 BB_FORCE_PWM SW1 39 PP0V8_SLEEP1_SW1 PP0V8_SLEEP1_SW1 40 NC NC R4302 41 100K OUT 37 OUT 37 OUT 38 OUT IN OUT IN PP0V8_SLEEP1_SW1 5% 1/20W MF 201 BUCK2 PP1V1_SLEEP3_BUCK2 PP1V1_SLEEP3_BUCK2 37 38 SW2 37 39 PP1V1_SLEEP1_SW2 PP1V1_SLEEP1_SW2 C 40 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=1.1V 37 41 BB_FORCE_PWM NC NC NC NC R4301 100K 5% 1/20W MF 201 R4303 5% 1/20W MF 201 100K PP1V1_SLEEP1_SW2 37 PP1V1_SLEEP1_SW2 38 41 SOC_PMU_INCKT_OTP 37 39 41 37 OUT 40 37 PMU_SOC_VBUS_DET_L NC NC NC NC NC NC NC NC NC NC NC NC NC NC 37 PP1V1_SLEEP3_BUCK2 PMU_SOC_UWAKE_L 37 41 OUT IN 38 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=1.1V 41 PMU_TO_SOC_CLK_32K 38 PP0V8_SLEEP1_SW1 41 PMU_TO_SOC_SYS_ALIVE SOC_AWAKE_REQ PMU_TO_SOC_AWAKE_PWRGD SOC_SLEEP1_REQ PMU_TO_SOC_SLEEP1_PWRGD SOC_VDD_HI_LO VOLTAGE=0.8V PP0V8_SLEEP1_SW1 41 PMU_TO_SOC_IRQ_L PMU_TO_SOC_RESET_L PMU_TO_SOC_VDD_OK PMU_SOC_UWAKE_L 40 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=0.6V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE PMU_SOC_VBUS_DET_L SMC_SOCPMU_RESET SOC_PMU_INCKT_OTP LDO0 5% 37 38 BI 41 PP1V1_SLEEP1_SW2 38 PP1V1_SLEEP1_SW2 38 PP1V1_SLEEP1_SW2 37 R4315 0 5% 1/20W MF 201 BUCK3 39 PP1V8_SLEEP3_BUCK3 PP1V8_SLEEP3_BUCK3 40 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=1.8V SW3A 39 37 PP1V8_SLEEP2_SW3A PP1V8_SLEEP2_SW3A 37 40 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=1.8V PP1V8_SLEEP2_SW3A We can remove R4304 this once we verify grounding is ok 37 PP1V8_SLEEP2_SW3A NC NC NC NC NC SW3C PP1V8_AWAKE_SW3C 38 41 PP1V8_AWAKE_SW3C B 37 38 40 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=1.8V PP1V8_AWAKE_SW3C 38 PP1V8_AWAKE_SW3C NC NC NC NC NC LDO7 38 PP3V0_AWAKE_LDO7 37 38 39 PP3V0_AWAKE_LDO7 40 MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE VOLTAGE=3.0V E8 J7 J8 K8 K7 PMU_VREF UWAKE* GPIO1 GPIO2 GPI3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 PMU_TCAL_PWR 1 K9 G2 H2 H3 B3 IN 2 BB_FORCE_PWM SOC_PMU_I2C_SCL SOC_PMU_I2C_SDA SMBUS_SOC_PMU_BR_SCL SMBUS_SOC_PMU_BR_SDA 1 E3 E4 G3 G4 VOLTAGE=0.8V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE 2 I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA 1 SYM 2 OF 2 2 IN CLK_32K_ALT CLK_32K_IN 1 37 20 SOC_PMU_CLK_32K F4 F3 2 NC 1 WLCSP Signal Aliases 46 SMC_SOCPMU_RESET SMC_SOCPMU_RESET 41 MAKE_BASE=TRUE A SYNC_MASTER=X362_T208 SYNC_DATE=03/15/2016 PAGE TITLE Berkelium - 2 DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=T151 WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 43 OF 145 41 OF 121 SIZE D A 8 7 6 5 4 3 2 1 T208 Support PP1V8_S0SW_DFR DFR Connectors 5% 1/20W MF 2 201 MIPID FILTERING 43 47 48 114 1 C4490 R4490 100PF 2 S 3 D D SMC_LID 5% 2 25V C0G 0201 Q4400 DMN32D2LFB4 DFN1006H4-3 DFR Touch Conn J4402 R4492 F-ST-SM 1 24 114 42 37 5% 1/20W MF 201 PP1V8_S0SW_DFR DFR_TOUCH_SPI_CS_L DFR_TOUCH_SPI_MOSI_R IN 114 38 37 114 38 37 114 114 37 2 42 DFR_TOUCH_ROM_I2C_SCL DFR_TOUCH_ROM_I2C_SDA DFR_TOUCH_RESET_L 114 42 37 PP1V8_S0SW_DFR 110 PP5V_S0_T139 IN BI IN R4481 DFR_TOUCH_PANEL_DETECT DFR_DISP_VSYNC 1 4 3 6 5 8 7 10 9 12 11 DFR_TOUCH_SPI_MISO_R DFR_TOUCH_SPI_CLK_R 14 13 16 15 18 17 20 19 22 21 1 2 DFR_TOUCH_ROM_WC PP1V8_S0SW_DFR 2 PP1V8_S0SW_DFR 114 37 42 114 1 2200PF 10% 10V X7R-CERM 0201 2 2 2 U4405 DFR_DISP_PWR_EN 7 CAP 2 ON TDFN D 3 S 5 Bus 10% 2 6.3V CERM-X5R 0201 9 1 Y+ 2 Y- U4408 TQFN PCH_SWD_MUX_SEL IN M+ 5 M- 4 PI3USB102EZLE INT PU SOC 50k 15 5% 1/20W MF 201 2 42 110 10 SEL D+ 7 D- 6 OE* C4470 1 10% 6.3V X5R 0201 2 114 VOLTAGE=3.3V MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900 PP3V3_S0SW_DFR Part SLG5AP1443V Type Load Switch R(on) @ 3.3V 17 mOhm Typ 19 mOhm Max Current 2.5A Max 6 5 GND 9 12 11 14 13 GND 16 15 18 17 20 19 22 21 24 23 GND SOC_XB_DBG1_1V8 SOC_XB_DBG2_1V8 AP1 42 42 IN BI 15 20 8 Read GND_VOID=TRUE 0x79 VOLTAGE=1.8V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DFRDRV_I2C_SCL DFRDRV_I2C_SDA 1 3 2 MIPID_DATA_P 38 114 IN 38 114 GND_VOID=TRUE U4404 IN BI 1 1UF C4401 IN 4 EN 3 PP3V3_S5_T139 DFR_DISP_PWR_EN 42 110 1 42 76 IN 2 10V X5R-CERM 0402 C4402 1UF EPAD GND 10% 2 10V X5R-CERM 0402 37 38 114 XDFN-COMBO 1 OUT 1UF 10% 37 38 114 NCP160AMX180 EDP: 32.6mA C4471 1 MIPID_DATA_N 10% 2 10V X5R-CERM 0402 29 R4453 37 0xA1 37 Mesa EEPROM 101000x (0x50/0x51) 0xA1/A3 IN 0111001 (0x39) 0 0 1 39 38 2 DFR_TOUCH_SPI_MOSI_R IN 0x72 MESA_SPI_MOSI 1 PLACE_NEAR=U3900.D10:5mm 42 114 39 38 0xA2 IN 2 MESA_SPI_CLK 39 38 SOC_BOOT:SPI MESA_SPI_MOSI_R OUT SOC_ROM_SPI_CLK 45 0 2 MESA_SPI_CLK_R 0 37 2 SOC_ROM_SPI_MOSI_R 37 OUT 5% 1/20W MF 201 R4452 1 0 IN SOC_BOOT:SPI R4451 1 5% 1/20W MF 201 R4457 1 PLACE_NEAR=U3906.2:5mm 2 SOC_ROM_SPI_MISO_R SOC_ROM_SPI_MOSI IN IN 100 5% 1/20W MF 201 PLACE_NEAR=U3900.B10:5mm 5% 1/20W MF 201 PLACE_NEAR=U3900.B9:5mm 38 0 1 42 114 5% 1/20W MF 2 201 DFR_TOUCH_SPI_CLK_R R4456 PLACE_NEAR=U3900.C9:5mm SOC_ROM_SPI_MISO OUT 5% 1/20W MF 201 0xA0/A2 0xA3 1010001 (0x51) R4454 R4455 DFR_TOUCH_SPI_CLK 42 114 R4450 1 0x98 0x73 2 DFR_TOUCH_SPI_MISO_R DFR_TOUCH_SPI_MOSI PLACE_NEAR=U3900.AB21:5mm IN PLACE_NEAR=J4402.7:5mm 5% 1/20W MF 201 PLACE_NEAR=U3900.Y20:5mm 0xA0 AOP0 0 1 DFR_TOUCH_SPI_MISO OUT 38 3 IN PLACE_NEAR=J4401:2.54mm 25 0x78 0x99 M34128 EEPROM 4 VOLTAGE=1.8V MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900 PP1V8_S0SW_DFR Write 1010100 (0x4C) SEP 38 114 GND_VOID=TRUE GND_VOID=TRUE MIPID_DATA_CONN_N 8-bit Address Tesla ALS IN PLACE_NEAR=J4401:5mm 30 AP2_0 AOP1 SYM_VER-1 MIPID_DATA_CONN_P 15 PCH (When SEL driven high) 3.25-OHM-0.1A-2.4GHZ TAM0605-4SM GND_VOID=TRUE GND_VOID=TRUE 37 SOC_SWD_CLK PCH_SWD_IO MIPID_CLK_N 2 SPI TERM 1010000 (0x50) Touch EEPROM D U4405 0011110 (0x3C) PMU 38 114 L4400 7 10 IN C 7-bit Address Device AP0 ACE (Default) GND B 3 26 0.1UF EDP: 182mA 8 C4444 VCC SOC BI 100K SLG5AP1443V 0.1UF 37 1 PLACE_NEAR=U4408:2mm 1 SOC_SWCLK SOC_SWDIO DFR_DISP_INT 114 DFR_DISP_RESET_L OUT 3 1 4 MIPID_CLK_P GND_VOID=TRUE MIPID_CLK_CONN_N T208 I2C Mapping PP3V3_S4_SOC_PMU OUT 38 20% 6.3V X5R 0201-1 SWD DEBUG MUX 37 114 1 PLACE_NEAR=J4401:2.54mm GND_VOID=TRUE GND_VOID=TRUE C4400 GND 42 38 OUT 1.0UF VDD C 110 R4400 3 PP3V3_S5_T139 C4410 NOSTUFF IN DFR_DISP_VSYNC DFR_DISP_TE OUT 4 GND_VOID=TRUE 27 GND SYM_VER-1 MIPID_CLK_CONN_P GND_VOID=TRUE NC 3.3V DFR Switch 1 76 42 NC 5 PP1V8_S0SW_DFR 42 37 A Y DFN1010 4 38 114 1 5% 1/20W MF 201 U4406 38 114 P3V3S0SW_RAMP 10K 26 5% 1/20W MF 201 74LVC1G08FW5 B 1 DFR_DISP_SMC_RST_L IN 6 2 DFR_DISP_RST_L IN 38 114 37 42 114 R4480 42 38 114 114 38 8 38 OUT IN 2 0.1UF R4485 5% 1/20W MF 2 201 42 114 IN C4403 4.7K 42 114 DFR_TOUCH_INT_L DFR_CLKIN_RESET_L 28 3.25-OHM-0.1A-2.4GHZ TAM0605-4SM GND_VOID=TRUE DF40PG(1.5)-26DS-04V(51) 10% 2 6.3V CERM-X5R 0201 76 25 4.7K 1 38 42 114 OUT 1 NOSTUFF 38 114 BI L4401 DFR Disp Conn J4401 2 MF 201 PP1V8_S0 1 BI DFR_TOUCH_LID DFR_TOUCH_GPIO2 NOSTUFF F-ST-SM 109 38 37 42 23 114 1 5% 1/20W 100K AA07-S022VA1 0 2 24K 5 R4491 G 1 SYM_VER_2 1 37 42 114 2 SOC_ROM_SPI_CLK_R SOC_BOOT:SPI OUT 37 B 45 OUT 5% 1/20W MF 201 T208 LEVEL SHIFTING I2C_ALS_SCL I2C_ALS_SDA OUT BI 76 114 47K 5% 1/20W MF 201 38 OUT IN IN 1 47K 38 5% 1/20W MF 201 OUT 10% 2 16V X5R-CERM 0201 SOC_UART_LS_EN 5% 1/20W MF 201 VL 10% 2 16V X5R-CERM 0201 VCC T208 SWD MUX U4401 NLSX5014MU_G 12 EN UQFN 42 IOVCC[1] SOC_UART_R2D IN 3 IOLV[2] IOVCC[2] 9 SOC_UART_D2R OUT PCH_ALS_TO_SOC_UART_TXD 4 IOLV[3] IOVCC[3] 8 SOC_TO_PCH_ALS_UART_TXD 5 IOLV[4] IOVCC[4] 7 SOC_TO_PCH_UART_TXD 10% 2 16V X5R-CERM 0201 R4460 1 100K ALS_SOC_UART_R2D IN 20 ALS_SOC_UART_D2R OUT 20 20 42 C4461 VL VCC 10% 2 16V X5R-CERM 0201 U4402 SOC_XB_DBG1_1V8 SOC_XB_DBG2_1V8 2 IO/VL1 3 IO/VL2 UDFN IO/VCC1 7 IO/VCC2 6 ACE DBG SOC_SWCLK_DBG SOC_SWDIO_DBG MAKE_BASE=TRUE SOC_SWCLK_DBG SOC_SWDIO_DBG SOC_SWD_LS_EN 5 EN SYNC_MASTER=X362_T208 GND SYNC_DATE=06/30/2016 PAGE TITLE T208 Support 6 DRAWING NUMBER Apple Inc. 051-00647 REVISION 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 44 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=T151 WWW.AliSaler.Com 7 6 5 4 31 MAKE_BASE=TRUE R 8 31 20 PCH GND 38 42 110 0.1UF 5% 1/20W MF 201 NLSX4402 10 PCH_TO_SOC_UART_TXD C4460 0.1UF 0.1UF 100K 2 IOLV[1] T208 GND 1 C4441 8 0.1UF 1 PP3V3_S4_SOC_PMU 1 5% 1/20W MF 201 C4440 R4444 11 47K 1 1 47K R4440 4 SOC_ALS_LS_EN 38 5% 1/20W MF 201 R4443 38 1/20W 201 MF 5% R4442 R4441 1 2 76 114 2 IO/VCC1 7 I2C_ALS_SCL_R IO/VCC2 6 I2C_ALS_SDA_R R4421 100 5 EN PP1V8_S4 38 4 IN 2 IO/VL1 3 IO/VL2 1/20W MF 201 ALS 2 37 ALS_SCL_I2C_1V8 ALS_SDA_I2C_1V8 1 BI 201 MF 5% 1 37 UDFN 1 NLSX4402 T208 A 100 1/20W R4472 1K 5% 1 8 U4403 1 R4420 5% 1/20W MF 201 1 1K 10% 2 16V X5R-CERM 0201 VL VCC R4471 2 2 0.1UF 1/20W MF 201 2 1 C4451 2 R4470 100K 5% 0.1UF 10% 2 16V X5R-CERM 0201 1 1 C4450 2 1 109 38 110 PP3V3_S0_LEFT 2 110 1 PP1V8_S0 PP3V3_S0_LEFT PP1V8_S0 2 37 42 38 37 2 109 109 ACE SWD DBG ALS/DEBUG UART 1 ALS I2C 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 42 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 KBD CONNECTOR F-ST-SM 114 114 43 115 114 56 115 114 56 110 109 114 114 114 114 43 PP5V_S0_FAN_CONN FAN_LT_TACH FAN_LT_PWM PP5V_S0_KBD PP3V3_G3H 43 KBD_BLC_GSSOUT 43 KBD_BLC_GSLAT 110 PP3V3_S4 43 KBD_BLC_GSSIN 43 KBD_BLC_XBLANK 48 114 XW4500 SM DF40PC-40DS-0.4V-51 2 D R4510 J4500 1 114 43 GND_FAN 1 4 5 6 7 8 PP5V_S0_FAN_CONN 9 10 VOLTAGE=5V 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 13 TPAD_SPI_CLK 1 0 5% 1/20W MF 201 2 VOLTAGE=0V 3 XW4502 SM 1 2 PP5V_S0 56 110 J4501 NOSTUFF C4511 DF40C-50DS-0.4V-51 F-ST-SM 1 12PF 5% 25V NP0-C0G 0201 PP5V_S4 110 117 CRITICAL 2 114 48 48 114 L4500 FAN_RT_TACH FAN_RT_PWM 114 FERR-120-OHM-1.5A 56 114 115 56 114 115 SMC_LID SMC_PME_S4_WAKE_L SMC_ACTUATOR_DISABLE_L TPAD_SPI_INT_L_CONN 48 47 42 2 1 114 0402A 43 13 43 114 13 114 43 2 PP5V_S0_KBD KBD_I2C_SDA KBD_INT_L KBD_I2C_SCL SMC_LSOC_RST_L KBD_BLC_GSSCK VOLTAGE=5V 43 110 C4500 1 110 0.1UF 43 114 10% 25V 2 X5R 402 43 114 43 114 43 114 46 2 3 4 5 6 7 8 9 10 TPAD_SPI_MOSI TPAD_SPI_CS_L_CONN TPAD_SPI_MISO TPAD_SPI_IF_EN_CONN TPAD_SPI_CLK_CONN 11 12 13 14 15 16 17 18 19 20 PP5V_S4_TPAD_CONN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PP3V3_S4_TPAD 43 110 1 PP3V3_S0 SMC_VIBE_L 48 114 43 114 114 518S00177 (RCPT, 0.3A per pin) MATE WITH PLUG 516S00054 C 1 TPAD CONNECTOR D 43 GND_FAN 2 ACT_GND 43 F4500 109 2.5A-16V-0.1OHM PPBUS_S4_HS_TPAD 1 2 PPVIN_S4_TPAD_FUSE SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA KBD_INT_L KBD_I2C_SDA 49 49 43 114 43 114 KBD_I2C_SCL KBD_BLC_XBLANK KBD_BLC_GSSIN 43 114 43 114 43 114 KBD_BLC_GSSOUT KBD_BLC_GSSCK KBD_BLC_GSLAT 43 114 43 114 43 114 XW4501 SM 114 43 ACT_GND VOLTAGE=0V PPVIN_S4_TPAD_FUSE 1 2 C 43 114 VOLTAGE=12.6V 1812 516S00187, MATE WITH 516S00188 B B TRACKPAD ISOLATION GATES/FET 110 110 43 PP3V3_S4_TPAD 110 1 110 C4520 43 73 70 46 20 12 PM_SLP_S4_L 1 TPAD_SPI_IF_EN_CONN 43 114 13 TPAD_SPI_CS_L 3 D Y DFN1010 4 C4540 5% 1/20W MF 2 201 10% 16V 2 X5R-CERM 0201 R4530 100K 5% 1/20W MF 2 201 5 74LVC1G08GW TPAD_SPI_CS_L_CONN 43 114 15 SOT353 4 TPAD_SPI_INT_L B U4540 Y A 1 TPAD_SPI_INT_L_CONN 43 114 2 3 3 NC R4531 2 0 0 1 5% 1/20W MF 201 R4520 2 R4540 100K NC 5 1 R4541 2 NOSTUFF 5% 1/20W MF 201 A 1 0.1UF 74LVC1G08FW5 B A DMN32D2LFB4 DFN1006H4-3 SYM_VER_3 6 U4520 PP3V3_S0 2 S TPAD_SPI_IF_EN 2 43 Q4530 G 1 110 15 1 1 10% 2 16V X5R-CERM 0201 PP3V3_SUS PP3V3_S4_TPAD 0.1UF PP3V3_S4_TPAD 43 0 1 5% 1/20W MF 201 NOSTUFF NOSTUFF SYNC_MASTER=X363_SAMANTHA PAGE TITLE SYNC_DATE=01/08/2016 Connectors&ESD DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=KEYBOARD WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 45 OF 145 43 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D Debug Stuff Was Here C C B B A SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=08/26/2015 External A USB3 Connector DRAWING NUMBER Apple Inc. 051-00647 REVISION 10.0.0 R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 47 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DEBUG WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 44 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE MOJAVE 16V BOOST 42 45 PP3V3_S4_T151 1 C4910 DIDT=TRUE VOLTAGE=3.3V 0402 10UF 20% 2 6.3V CERM-X5R 0402-9 A2 VIN MOJAVE_EN_M 45 1 2 5% 1/20W MF 0201 45 1 1 PMID C1 PP17V0_MOJAVE_LDOIN 1 C4925 2.2UF 20% 2 25V X5R 0402-3 VOLTAGE=17V 20% 2 25V X5R 0402-3 1 45 C4926 EDP:12.5mA 42 1 5% 1/20W MF 0201 1 38 R4912 0 MESA_SPI_MISO OUT 1 2 1 D R4954 680 MESA_BOOST_EN 45 114 1 MESA_BOOST_EN_CONN 2 5% 1/20W MF 201 C4951 1 45 114 C4954 100PF 5% 2 25V C0G 0201 MESA_SPI_MISO_CONN R4911 0 SMC_ONOFF_L OUT 1 MENU_KEY_L 2 5% 1/20W MF 201 C4952 56PF 5% 25V 2 NP0-C0G 0201 1 45 114 C4955 100PF 5% 2 25V C0G 0201 FL4900 PP16V0_MESA 1 PP16V0_MESA_CONN 2 Option to feed LDO from 5V in case of dropout issue C4927 1 MESA FLEX CONNECTOR 45 114 VOLTAGE=16V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000 0201 Proto1 Connector for X434/X435 Support PLUG (516S00115) - X434/ X435 Jumper Recptacle (516S00203) - X362/X363 MLB 100PF C 5% 2 25V C0G 0201 114 U4910 NCP160AMX300 PP3V3_S4_T151 C4911 4 45 PP1V8_MESA 3 IN XDFN-COMBO OUT 1 EN 1UF 1 GND EPAD 2 10% 2 10V X5R-CERM 0402 45 J4900 505066-1220 VOLTAGE=3.0V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 45 C4916 F-ST-SM 14 1UF MESA_SPI_MISO_CONN 114 45 MESA_SNSR_INT_CONN 114 45 MESA_BOOST_EN_CONN MESA_I2C_SDA 114 45 37 MESA_I2C_SCL 114 45 37 10% 2 10V X5R-CERM 0402 114 45 FL4910 80-OHM-25%-500MA 45 C PP3V0_MESA_CONN EDP:100mA PP3V0_MESA 5 1 5% 80-OHM-25%-500MA 45 45 100PF VOLTAGE=0V 3.0V MESA 110 C4953 0201 5% 25V 2 NP0-C0G 0201 PLACE_NEAR=J4900:3MM 1 45 114 2 25V C0G 56PF 1 MESA_SNSR_INT_CONN 2 5% 1/20W MF 201 C4950 MESA_SPI_CLK_CONN 5% 1/20W MF 0201 P16V0_AGND 2 2 5% 1/20W MF 201 C4923 OUT 1 5% 2 25V NP0-C0G 0201 1 5% 2 25V NP0-C0G 0201 20% 2 25V X5R 0402-3 XW4900 SHORT-0201 2 IN R4953 680 MESA_SNSR_INT 56PF R4951 56 MESA_SPI_CLK_R 56PF 2.2UF R4916 0 MESA_BOOST_EN C4924 2.2UF C2 LDOIN R4915 0 PP3V3_S4_T151 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=16V PP16V0_MESA VOUT C3 B2 EN_M A3 EN_S NOSTUFF 110 1 BGA B1 SW B3 AGND 110 MESA_SPI_MOSI_CONN 2 5% 1/20W MF 0201 LM3638 A1 PGND D 1.0UH-0.4A-0.636OHM 1 2 PP3V3_S4_MESA_SW IN 1 U4900 MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200 L4901 R4950 0 MESA_SPI_MOSI_R PP3V0_MESA 1 PP3V0_MESA_CONN 2 C4920 1 2.2UF C4921 2.2UF 20% 20% 2 6.3V X5R-CERM 2 6.3V X5R-CERM 0201 0201 1 C4922 C4928 20% 10% 16V 2 X5R-CERM 0201 2.2UF C4929 1 0.1UF 2 6.3V X5R-CERM 0201 2 1 4 3 6 5 8 7 10 9 12 11 16 15 PP1V8_MESA_CONN 45 114 MESA_SPI_MOSI_CONN MENU_KEY_L MESA_SPI_CLK_CONN PP16V0_MESA_CONN 45 114 45 114 45 114 45 114 45 114 VOLTAGE=3.0V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 0201 1 13 1 100PF 5% 25V 2 C0G 0201 Mesa Power Sequencing Requirements Power On: 1V8 -> 3V3 -> 16V0 B B 1.8V MESA PP1V8_MESA_CONN U4920 LP5907SNX-1.825 PP3V3_S4_T151 1 4 VIN C4912 1UF 10% 2 10V X5R-CERM 0402 37 IN MESA_PWR_EN X2SON PP1V8_MESA VOUT 1 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000 3 EN 1 I2C pullups on same rail as EEPROM VCC R4920 2.2K 45 EDP:1.5mA C4914 1UF 114 45 37 10% 2 10V X5R-CERM 0402 GND EPAD 5 45 2 110 1 45 114 114 45 37 IN MESA_I2C_SCL BI MESA_I2C_SDA 5% 1/20W MF 2 201 1 R4921 2.2K 5% 1/20W MF 2 201 FL4920 80-OHM-25%-500MA 45 PP1V8_MESA 1 PP1V8_MESA_CONN 2 0201 1 C4918 1 2.2UF C4917 45 114 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000 100PF 20% 2 6.3V X5R-CERM 0201 5% 2 25V C0G 0201 A SYNC_MASTER=X362_P49 SYNC_DATE=01/08/2016 PAGE TITLE MESA DRAWING NUMBER Apple Inc. 051-00647 REVISION R BOM_COST_GROUP=T151 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 49 OF 145 45 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D U5000 TM4EA231H6ZXRI 89 12 BI 89 12 BI 89 12 BI 89 12 BI 12 IN 89 12 IN 20 IN 12 C OUT 12 IN 12 OUT 12 OUT 114 49 BI 114 49 BI 49 BI 49 BI 48 BI 48 BI 114 49 BI 114 49 BI 48 BI 48 BI 114 49 BI 114 49 BI 114 56 OUT 56 IN 56 OUT 56 IN 47 OUT 48 OUT 48 IN 48 BI 89 OUT 48 BI 19 OUT 48 47 47 103 OUT 48 IN 48 47 IN 48 47 29 IN 70 47 BI 48 47 IN 43 48 48 103 101 BI IN 114 114 OUT 48 114 B BI 12 IN IN IN 29 IN 48 47 IN 70 20 12 IN 89 76 73 70 27 20 12 IN 73 70 43 20 12 IN 73 20 12 IN 48 47 45 IN 114 48 IN 48 OUT 48 48 36 35 IN OUT LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK24M_SMC LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ LPC_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L SMC_WAKE_SCI_L D10 B13 C11 A13 H10 C12 C13 G10 G11 F10 G12 (OD) (OD) B11 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA D13 D12 N4 L5 N10 K8 N9 M9 L9 L8 N5 M5 (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_FAN_1_CTL SMC_FAN_1_TACH SMC_TOPBLK_SWP_L SMC_SENSOR_PWR_EN H13 H11 A12 B12 K4 A9 SMC_DEV_SUPPLY_L SMC_ACTUATOR_DISABLE_L SMC_GFX_SELF_THROTTLE TP_SYS_ONEWIRE SMC_CLK12M_EN SMC_PCH_SUSACK_L L12 M12 N13 L11 K3 K2 (IPU) (OD) (IPD) (OD) CPU_PECI_R SMC_PECI_L C6 C7 SMC_CHGR_INT_L NC_SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_PMIC_INT_L SMC_SENSOR_ALERT_L SMC_VIBE_L SMC_LID_LEFT J10 H12 (OD) SMC_PCH_SUSWARN_L SMC_USBC_INT_L SMC_BC_ACOK PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L SMC_DEBUGPRT2_RX_L SMC_DEBUGPRT2_TX_L SMC_LID_RIGHT SMC_WIFI_PWR_EN OMIT_TABLE PM6 PM7 PK6 PK7 PN2 PN3 PN4 PN5 PN6 PN7 PH2 PH3 D2 D1 F1 M6 N6 L7 M7 N7 PQ0 PQ1 PQ2 PQ3 PQ4 PQ5 PQ6 PQ7 PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 PE5 PE4 PB4 PB5 PD3 PD2 PD1 PD0 PK0 PK1 PK2 PK3 PE7 PE6 PN1 PN0 G4 G3 G2 G1 C2 C3 A1 A2 A3 B3 A4 B4 D4 D3 C1 B1 H4 H3 H1 H2 C4 C5 B5 A5 SMC_CPU_HI_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_CPUGT_ISENSE SMC_CPU_ISENSE SMC_GPU_CORE_ISENSE SMC_GPU_CORE_VSENSE SMC_DDR1V2_ISENSE SMC_GPU_VDDCI_ISENSE SMC_GPU_VDDCI_VSENSE SMC_GPU_1V8_ISENSE SMC_GPU_FB_ISENSE SMC_SSDLIM_ISENSE SMC_GPU_FBIC_ISENSE SMC_GPU_HS_ISENSE SMC_CPUSA_ISENSE SMC_CPUDDR_ISENSE SMC_CPUSA_VSENSE SMC_CPU_VSENSE SMC_CPUGT_VSENSE SMC_CPU_IMON_ISENSE SMC_CPUGT_IMON_ISENSE PC7 PC6 PC4 PC5 PJ5 PJ4 M1 N1 M3 M2 B6 A6 CPU_PROCHOT_L SMC_VCCIO_CPU_DIV2 PM_THRMTRIP_L PB0 PB1 PB6 PB7 E11 D11 E3 E4 SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L PM_RSMRST_L SMC_GFX_PWR_LEVEL_L PF0 PF1 PF2 PF3 PF4 PF5 L10 N11 N12 M11 K10 M10 NC_SPI_SMC_MISO NC_SPI_SMC_MOSI NC_SPI_SMC_CLK NC_SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK PA0/U0RX PA1/U0TX PL7 PL6 PG4 M8 PG5 N8 SMC_CBC_ON SMC_GFX_OVERTEMP PH0 L2 PH1 L1 ALL_SYS_PWRGD SMC_THRMTRIP PH4 PH5 PH6 PH7 K1 J3 J2 J4 PJ0 PJ1 PJ2 PJ3 D8 A8 B8 C8 PM_PWRBTN_L PM_SYSRST_L TCON_BKLT_PWM SMC_ADAPTER_EN SMC_OOB1_D2R_L SMC_OOB1_R2D_L SMC_SOCPMU_RESET TP_SMC_DEBUGPRT_EN_L PM_BATLOW_L PM3 G13 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 48 IN 6 47 65 IN 47 IN 6 13 47 48 OUT CPU_CATERR_L SMC_BT_PWR_EN SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT IN PP3V3_G3H 47 76 109 L5001 BYPASS=U5000.E6::5MM FERR-30-OHM-2.2A-0.035-OHM 1 2 PP3V3_S5_SMC_VDDA BYPASS=U5000.F8::5MM BYPASS=U5000.E6::5MM BYPASS=U5000.G6::5MM BYPASS=U5000.F6::5MM IN OUT 1 C5002 1.0UF 20% 2 6.3V X5R 0201-1 1 C5003 0.1UF 10% 2 10V X5R-CERM 0201 1 C5004 0.1UF 10% 2 10V X5R-CERM 0201 1 C5005 0.1UF 10% 2 10V X5R-CERM 0201 1 1 C5006 1 C5007 0.1UF 10% 2 10V X5R-CERM 0201 1 C5008 0.1UF 10% 10V 2 X5R-CERM 0201 1 C5009 0.1UF 76 48 IN 47 BI 10% 2 10V X5R-CERM 0201 (IPU) 47 OUT 47 IN 29 47 114 OUT 29 47 114 BI (OD) (OD) BUF_SMC_RESET_L F11 (OD) SMC_WIFI_EVENT_L SMC_WAKE_L NC_SMC_HIB_L A11 M13 L13 OUT 48 OUT 48 OUT 48 SMC_CLK32K NC_SMC_XOSC1 K11 K12 IN SYSCLK_CLK12M_SMC NC_SMC_OSC1 F13 F12 OSC0 OSC1 K13 VBAT MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V 73 IN 12 73 114 PC0/SWCLK/TCK PC1/SWDIO/TMS PC3/SWO/TDO PC2/TDI 48 89 IN 70 73 OUT 47 OUT 18 48 IN OUT 47 1 C5010 1 1.0UF 48 OUT 48 OUT 41 OUT 48 OUT 12 29 103 C5017 1.0UF 20% 2 6.3V X5R 0201-1 IN 47 57 114 C 47 47 NC B7 NC E6 E7 F6 F7 F8 G6 G7 G8 H6 H7 VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS D7 H9 J1 J9 J13 VDDC VDDC VDDC VDDC VDDC VREFA+ E1 VREFA- E2 47 PP3V0_S5_AVREF_SMC 55 53 51 50 48 47 GNDA F2 GNDA F4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XW5000 SM GND_SMC_AVSS 2 1 PLACE_NEAR=U5000.A10:6MM A10 D5 D6 D9 E5 E8 E9 E10 F5 F9 G5 G9 H5 H8 J5 J6 J7 J8 K9 1 C5020 1 0.01UF C5021 1.0UF 20% 10% 2 10V X5R-CERM 0201 2 6.3V X5R 0201-1 BYPASS=U5000.E1:F2:1MM BYPASS=U5000.E1:F2:1MM B BYPASS=U5000.J1::5MM BYPASS=U5000.H9::5MM BYPASS=U5000.J13::5MM BYPASS=U5000.H9::5MM BYPASS=U5000.J9::5MM BYPASS=U5000.D7::5MM BYPASS=U5000.D7::5MM BYPASS=U5000.J9::5MM 12 18 115 48 47 57 114 XOSC0 XOSC1 64 IN SMC_TCK SMC_TMS SMC_TDO SMC_TDI B9 C9 C10 B10 VDDA F3 PP1V2_S5_SMC_VDDC IN PK4 WAKE* HIB* IN 48 48 RST* OMIT_TABLE 12 18 73 115 IN OUT TM4EA231H6ZXRI BGA 35 OUT 10% 2 10V X5R-CERM 0201 U5000 6 OUT IN (IPD) 19 12 C5001 SYM 2 OF 2 19 OUT 1 0.1UF 5% 1/20W MF 2 201 10% 10V 2 X5R-CERM 0201 BYPASS=U5000.H7::5MM R5002 1M 0.1UF BYPASS=U5000.H6::5MM BYPASS=U5000.G8::5MM 47 70 73 IN MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 0402 47 SPI_DESCRIPTOR_OVERRIDE_L N2 N3 L4 M4 PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PJ7 PJ6 K6 J11 J12 K7 A7 L6 E13 E12 BGA SYM 1 OF 2 PB2/I2C0SCL PB3/I2C0SDA PA6 PA7 PF6 PF7 PG0 PG1 PG2 PG3 PG6 PG7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 L3 K5 (IPD when sampling) PL3 PL2 PL1 PL0 PM5 PL4 PL5 PM4 PM2 PM0 PM1 PK5 20% 2 6.3V X5R 0201-1 1 C5015 0.1UF 10% 2 10V X5R-CERM 0201 1 C5016 0.1UF 10% 2 10V X5R-CERM 0201 1 C5014 1.0UF 20% 2 6.3V X5R 0201-1 1 C5012 0.1UF 10% 2 10V X5R-CERM 0201 1 C5013 1 0.1UF 10% 2 10V X5R-CERM 0201 C5011 0.1UF 10% 2 10V X5R-CERM 0201 NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail. A NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups. SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016 PAGE TITLE SMC DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=SMC WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 50 OF 145 46 OF 121 SIZE D A 8 7 6 5 4 SMC AVREF Supply 3 2 PROCHOT/THRMTRIP Support 1 PECI Support U5165 PP1V0_S3 TS3330-COMBO QFN 109 PP3V3_G3H D 5 IN C5165 CRITICAL NC0 NC1 NC2 NC3 NC4 1 4 GND 1.0UF 20% 6.3V 2 X5R 0201-1 CRITICAL R5158 PP3V0_S5_AVREF_SMC OUT 8 1 2 3 6 7 MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.1000 VOLTAGE=3.0V NC NC NC NC NC 46 65 46 6 CPU_PROCHOT_L BI 1 100 2 Q5150 SMC_PROCHOT_L 1% 1/20W MF 201 DMN32D2LFB4 6 D PLACE_NEAR=Q5159.6:5MM C5166 1 10UF 20% 6.3V CERM-X5R 2 0402-1 1 C5167 SYM_VER_2 SOT563 1 G 46 0.1UF 10% 2 10V X5R-CERM 0201 1 S 46 48 50 51 53 55 From SMC IN 46 46 OUT OUT PM_THRMTRIP_L 1 100 2 R5134 CPU_PECI_R To SMC R5159 48 46 13 6 C5134 SMC_THRMTRIP_L 1 47PF 3 D PLACE_NEAR=Q5159.3:5MM 5% 25V C0G 2 0201 PLACE_NEAR=Q5150.2:5MM Q5159 DMN5L06VK-7 SOT563 33 1 NOSTUFF 1% 1/20W MF 201 D S 2 SMC_PECI_L IN G 2 SMC_PROCHOT GND_SMC_AVSS D 3 DFN1006H4-3 Q5159 DMN5L06VK-7 VER 3 MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V 47 110 1 5% 1/20W MF 201 R5151 CPU_PECI 2 6 13 BI From/To CPU/PCH 330 5% 1/20W MF 2 201 VER 3 4 S G 5 SMC_THRMTRIP IN 46 47 C C SMC_BC_ACOK SMC_BC_ACOK 46 47 48 MAKE_BASE=TRUE 110 47 PP1V0_S3 1 R5197 100K 1% 1/20W MF 2 201 R5112 12 Top-Block Swap IN PM_CLK32K_SUSCLK_R 1 22 2 SMC_CLK32K OUT 46 46 SMC_VCCIO_CPU_DIV2 5% 1/20W MF 201 PP3V3_S0 1 110 R5196 100K Place near CPU 1% 1/20W MF 2 201 R5182 1 1K 5% 1/20W MF 201 2 46 SMC_TOPBLK_SWP_L IN R5183 1 1K 2 PCH_STRP_TOPBLK_SWP_L OUT 15 5% 1/20W MF 201 B 109 76 46 110 48 110 114 103 48 46 48 46 29 46 70 46 114 48 46 45 48 46 114 48 43 42 114 46 29 114 46 29 114 57 46 46 46 114 57 46 48 47 46 46 47 46 46 73 70 46 PP3V3_G3H PP3V3_S4 PP3V3_S0 SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_WIFI_EVENT_L SMC_PMIC_INT_L SMC_ONOFF_L SMC_SENSOR_ALERT_L SMC_LID NOSTUFF R5166 R5167 R5168 R5169 R5170 R5172 R5171 100K 100K 100K 100K 10K 10K 330K SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L NOSTUFF SMC_TMS NOSTUFF SMC_TDO NOSTUFF SMC_TDI NOSTUFF SMC_TCK NOSTUFF SMC_BC_ACOK SMC_ADAPTER_EN SMC_THRMTRIP SMC_DELAYED_PWRGD SMC_PM_G2_EN R5175 R5176 R5177 R5178 R5179 R5180 R5187 R5185 R5186 R5191 R5192 20K 20K 10K 10K 10K 10K 100K 100K 10K 100K 100K A B 1 2 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 2 1 2 1 2 1 2 5% 5% 5% 5% 5% 5% 5% 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W MF MF MF MF MF MF MF 201 201 201 201 201 201 201 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W MF MF MF MF MF MF MF MF MF MF MF 201 201 201 201 201 201 201 201 201 201 201 SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN PAGE TITLE SYNC_DATE=11/19/2015 SMC Shared Support DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=SMC WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 51 OF 145 47 OF 121 SIZE D A 7 6 SMC12 ADC Assignments OUT SMC_PBUS_VSENSE OUT SMC_BMON_ISENSE OUT SMC_DCIN_ISENSE 46 OUT SMC_DCIN_VSENSE 46 OUT SMC_CPUGT_ISENSE 46 OUT SMC_CPU_ISENSE 46 OUT SMC_GPU_CORE_ISENSE 46 OUT SMC_GPU_CORE_VSENSE OUT SMC_DDR1V2_ISENSE 46 OUT SMC_GPU_VDDCI_ISENSE 46 OUT SMC_GPU_VDDCI_VSENSE 46 OUT SMC_GPU_1V8_ISENSE OUT SMC_GPU_FB_ISENSE 46 46 46 D 46 46 46 OUT SMC_SSDLIM_ISENSE 46 OUT SMC_GPU_FBIC_ISENSE OUT SMC_GPU_HS_ISENSE OUT SMC_CPUSA_ISENSE OUT SMC_CPUDDR_ISENSE 46 46 46 C 46 OUT SMC_CPUSA_VSENSE 46 OUT SMC_CPU_VSENSE 46 OUT SMC_CPUGT_VSENSE 46 OUT SMC_CPU_IMON_ISENSE OUT SMC_CPUGT_IMON_ISENSE 46 SMC_CPU_HI_ISENSE MAKE_BASE=TRUE IN 50 MAKE_BASE=TRUE IN 50 MAKE_BASE=TRUE IN 50 SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE IN 50 SMC_DCIN_VSENSE MAKE_BASE=TRUE IN 50 SMC_CPUGT_ISENSE MAKE_BASE=TRUE IN 53 MAKE_BASE=TRUE SMC_CPU_ISENSE IN 51 MAKE_BASE=TRUE SMC_GPU_CORE_ISENSE IN 55 MAKE_BASE=TRUE SMC_GPU_CORE_VSENSE IN 55 MAKE_BASE=TRUE IN 51 MAKE_BASE=TRUE IN 55 SMC_GPU_VDDCI_VSENSE MAKE_BASE=TRUE IN 55 SMC_GPU_1V8_ISENSE MAKE_BASE=TRUE IN 55 MAKE_BASE=TRUE SMC_DDR1V2_ISENSE SMC_GPU_VDDCI_ISENSE SMC_GPU_FB_ISENSE 55 MAKE_BASE=TRUE IN MAKE_BASE=TRUE SMC_SSDLIM_ISENSE IN 53 SMC_GPU_FBIC_ISENSE MAKE_BASE=TRUE IN 55 SMC_GPU_HS_ISENSE MAKE_BASE=TRUE IN 55 MAKE_BASE=TRUE SMC_CPUSA_ISENSE IN 53 51 MAKE_BASE=TRUE IN MAKE_BASE=TRUE SMC_CPUSA_VSENSE IN 53 SMC_CPU_VSENSE MAKE_BASE=TRUE IN 55 MAKE_BASE=TRUE SMC_CPUGT_VSENSE IN 55 MAKE_BASE=TRUE SMC_CPU_IMON_ISENSE IN 51 55 IN MAKE_BASE=TRUE 53 55 46 46 46 TP_SYS_ONEWIRE TP_SMC_DEBUGPRT_EN_L NC_SMC_DP_HPD_L TP_SYS_ONEWIRE MAKE_BASE=TRUE TP_SMC_DEBUGPRT_EN_L MAKE_BASE=TRUE NC_SMC_DP_HPD_L SM SW5227 8 7 6 5 SOX-152HNT SMC_ONOFF_L 1 SM 45 46 47 48 114 OUT 2 SMC_RESET_L OUT 29 57 64 76 114 R5252 1 2 3 4 HALL_SENSOR_LEFT PP3V3_G3H SW5200 EVQPUA02K Thermal Alerts 51 NOSTUFF SMC_CPUHI_COMP_ALERT_L IN 1 CPUTHMSNS_THM_L 100 1 R5214 100 1 R5220 TBTTHMSNS_X_THM_L IN 1 100 IN R5221 TBTTHMSNS_T_THM_L 100 1 TBTTHMSNS_X_ALERT_L IN 1 100 R5211 100 TBTTHRM_ALRT:SMC SMC_SENSOR_ALERT_L 2 OUT 46 47 5% 1/20W MF 201 CRITICAL R5256 Q5290 1 114 43 46 89 114 48 47 46 45 46 46 46 NC_SPI_SMC_MISO NC_SPI_SMC_MOSI NC_SPI_SMC_CLK NC_SPI_SMC_CS_L NC_SPI_SMC_CLK NC_SPI_SMC_CS_L 115 115 115 115 TRUE TRUE TRUE TRUE BOM OPTIONS CPUTHRM:BOTH CPUTHRM:THRM CPUTHRM:ALRT CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC CPUTHRM_THRM:SMC CPUTHRM_ALRT:SMC 5 IN SMC_LSOC_RST_L 1 IN SMC_ONOFF_L 2 35 IN SMC_PME_S4_WAKE_L IN SMC_PME_S4_DARK_L BOM GROUP BOM OPTIONS TBTTHRM:BOTH TBTTHRM:THRM TBTTHRM:ALRT TBTTHRM:NONE TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU 47 46 OUT SMC_PCH_SUSWARN_L MAKE_BASE=TRUE SMC_PCH_SUSACK_L IN MAKE_BASE=TRUE 48 46 SMC_PCH_SUSWARN_L SMC_PCH_SUSACK_L SMC_SENSOR_PWR_EN MAKE_BASE=TRUE IN OUT R5274 1 43 109 R5275 46 02 SMC_4FINGERS_RST OUT SMC_DEBUGPRT2_TX_L 46 1 PP3V3_G3H BYPASS=U5255.6::5MM SMC_SENSOR_PWR_EN 50 PM_PWRBTN_L MAKE_BASE=TRUE PM_PWRBTN_L SMC_PME_S4_WAKE_L SMC_BC_ACOK 47 46 A SMC_BC_ACOK MAKE_BASE=TRUE SMC_BC_ACOK SMC_DEBUGPRT2_RX_L 49 SMBUS_SMC_4_G3H_SDA SMBUS_SMC_4_G3H_SDA 46 SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SCL 46 49 SMBUS_SMC_2_S4_SDA SMBUS_SMC_2_S4_SDA 46 46 SMC_OOB1_D2R_L SMC_OOB1_D2R_L 77 80 114 46 SMC_OOB1_R2D_L MAKE_BASE=TRUE SMC_OOB1_R2D_L 1 46 46 SMC_ACTUATOR_DISABLE_L MAKE_BASE=TRUE SMC_CHGR_INT_L MAKE_BASE=TRUE WWW.AliSaler.Com 8 SMC_ACTUATOR_DISABLE_L SMC_CHGR_INT_L 7 35 WLAN_UART_TX 2 OUT OUT 5% 1/20W MF 201 2 R5277 29 46 47 103 1 0 46 1 B R5281 5% 1/20W MF 2 201 SMC_DEBUGPRT2_R_TX 1 R5278 0 TP-P6 1 TP-P6 PLACE_SIDE=BOTTOM R5257 A TP5200 SMC_DEBUGPRT2_R_RX 2 5% 1/20W MF 0201 1 109 10K 2 5% 1/20W MF 0201 1 35 PP3V3_G3H 100K TP5201 A 5% 1/20W MF 2 201 LID_FEATURE_OFF 3 R5255 1 10K 2 SMC_LID OUT 42 43 47 114 5% 1/20W MF 201 46 36 35 48 46 SMC_WIFI_PWR_EN SMC_SENSOR_PWR_EN R5295 R5294 10K 10K 1 2 5% 1/20W MF 201 5% 1/20W MF 201 NOSTUFF 1 2 NOSTUFF NC R5259 SMC_DEV_SUPPLY_L 0 1 2 SMC_DEV_SUPPLY_R_L SYNC_MASTER=X363_ZIFENGSHEN PAGE TITLE R5260 46 77 80 114 TCON_BKLT_PWM 2 C5257 1 BKLT_PWM_TCON2MLB BUF_SMC_RESET_L 76 114 5% 1/20W MF 201 1 10% 10V X7R-CERM 2 0201 43 10 DRAWING NUMBER Apple Inc. 051-00647 REVISION R 1 1000PF 10% 16V X7R-CERM 2 0201 SMC Project Support 46 76 NOSTUFF C5270 NOSTUFF GND_SMC_AVSS 46 47 50 51 53 55 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE BOM_COST_GROUP=SMC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 64 6 SYNC_DATE=04/14/2016 114 5% 1/20W MF 201 3300PF 114 CRITICAL NC 46 49 MAKE_BASE=TRUE 74LVC1G32 SOT891 4 SMC_LID_R 5 46 MAKE_BASE=TRUE SMC_LID_LEFT 2 U5255 2 SMC_LID_RIGHT 0 1 PLACE_SIDE=BOTTOM 46 47 114 50 SMBUS_SMC_4_G3H_SCL MAKE_BASE=TRUE 48 46 64 SMBUS_SMC_4_G3H_SCL MAKE_BASE=TRUE SMC_LID_LEFT_R WLAN_UART_RX 2 0 10% 10V X5R-CERM 2 0201 12 49 MAKE_BASE=TRUE 0 0.1UF 48 R5273 5% 1/20W MF 2 201 R5280 1 1 6 46 18 0 CRITICAL 5% 1/20W MF 201 LID_FEATURE_ON C5255 TABLE_BOMGROUP_ITEM 5% 1/20W MF 0201 1 74 TABLE_BOMGROUP_ITEM R5276 64 U5256 12 SMC_SENSOR_PWR_EN TABLE_BOMGROUP_ITEM PLACE_SIDE=BOTTOM NOSTUFF MAKE_BASE=TRUE 48 TABLE_BOMGROUP_ITEM 5% 1/20W MF 0201 SMC_PME_S4_DARK_L 109 TABLE_BOMGROUP_ITEM 10K 5% 1/20W MF 201 2 PLACE_SIDE=BOTTOM NOSTUFF SN74LVC1G02 SOT553-5 4 1 100K MAKE_BASE=TRUE 12 TABLE_BOMGROUP_ITEM PP3V3_S4 R5258 46 TABLE_BOMGROUP_ITEM C 1 S4 SMC Wake Sources 43 10% 16V X7R-1 2 0201 NOSTUFF BOM GROUP 10% 10V X5R-CERM 2 0201 3 NC_SPI_SMC_MISO NC_SPI_SMC_MOSI 1 1000PF 0.1UF 5% 1/20W MF 201 2 G 1 PP3V3_G3H C5256 100K DMN32D2LFB4 46 48 OUT Specify one of these BOM GROUPs. TBTTHRM_ALRT:SMC 1 2 SMC_LID_RIGHT 5% 1/20W MF 201 48 109 C5260 10K TABLE_BOMGROUP_HEAD 2 TBTTHMSNS_T_ALERT_L IN TBTTHRM_THRM:SMC 2 5% 1/20W MF 201 5% 1/20W MF 201 54 1 TABLE_BOMGROUP_HEAD TBTTHRM_THRM:SMC 2 5% 1/20W MF 201 54 HALL_SENSOR_RIGHT PP3V3_G3H Specify one of these BOM GROUPs. CPUTHRM_ALRT:SMC 2 5% 1/20W MF 201 SYM_VER_2 46 D R5253 1 2 3 4 OMIT_TABLE DFN1006H4-3 B 1 10% 16V X7R-1 2 0201 NOSTUFF CPUTHRM_THRM:SMC CPUTHMSNS_ALERT_L IN 2 2 5% 1/20W MF 201 54 100 5% 1/20W MF 201 R5216 IN 8 7 6 5 R5217 89 IN 48 109 SM 54 SMC_GFX_OVERTEMP 48 J5260 BYPASS=U5256.5::5MM 2 S SMC_LID_LEFT_R AMR-MLB-X502 MAKE_BASE=TRUE 3 D 2 Hall Effect Pads - Right SILK_PART=PWR_BTN PLACE_SIDE=BOTTOM PM_THRMTRIP_L OUT 10K 5% 1/20W MF 201 1000PF 110 47 46 13 6 1 C5250 OMIT_TABLE R5210 MAKE_BASE=TRUE J5250 BOMOPTION=DBG_BTN 54 SMC_CPUGT_IMON_ISENSE SMC_GFX_PWR_LEVEL_L 2 54 SMC_CPUDDR_ISENSE SMC_GFX_PWR_LEVEL_L 0603-NSP 1 AMR-MLB-X502 CRITICAL 1 SMC12 Pin Assignments 46 BOMOPTION=DBG_BTN PLACE_SIDE=BOTTOM SILK_PART=RESET_BTN BOMOPTION=OMIT RES 2 Hall Effect Pads - Left Debug RESET "Buttons" PLACE_SIDE=TOP SILK_PART=PWR_BTN R5226 3 2 SMC_CPU_HI_ISENSE 4 Debug Power "Buttons" 3 SM 1 OUT 46 5 4 8 1 52 OF 145 48 OF 121 SIZE D A 8 7 6 5 LYNX POINT LP S0 "SMBus 0" Connections 110 49 1K 5% 1/20W MF 201 2 (MASTER) D 1 1 2 R5301 J8500 R5350 SMC 1K 1 1.5K U5000 5% 1/20W MF 2 201 1 (MASTER) thru 5% 1/20W MF 2 201 PP3V3_G3H SMC (Write: 0x20 Read: 0x21) 1.5K 5% 1/20W MF 201 2 109 16 addresses R5351 R53801 1 2.0K U5000 (Write: 0x3E Read: 0x3F) ( when VRR_FLAG = 0 ) R5381 Battery Charger 2.0K 5% 1/20W MF 201 2 (MASTER) 5% 1/20W MF 2 201 ISL6259 - U7000 (Write: 0x12 Read: 0x13) 15 SMBUS_PCH_CLK 114 46 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL 76 114 114 46 SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SCL 64 15 SMBUS_PCH_DATA 114 46 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA 76 114 114 46 SMBUS_SMC_5_G3_SDA SMBUS_SMC_5_G3_SDA 64 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE DPMUX Connections MAKE_BASE=TRUE MAKE_BASE=TRUE Banjo Battery U7800 J6950 (Write: 0x16 Read: 0x17) 70 (Write: 0x68 Read: 0x69) SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SCL 63 70 SMBUS_SMC_5_G3_SDA SMBUS_SMC_5_G3_SDA 63 SMC SMBus "3" S0 DPMUX IC U9800 110 (MASTER) 89 NC_I2C_DPMUX_A_SCL NC_I2C_DPMUX_A_SCL 89 NC_I2C_DPMUX_A_SDA NC_I2C_DPMUX_A_SDA SMC SMBus "2" S4 Connections MAKE_BASE=TRUE C SMC DPMUX Connections 110 98 89 R5305 1 DPMUX IC 2.0K U9800 5% 1/20W MF 201 2 (MASTER) 1 R5371 1 5% 1/20W MF 201 2 5% 1/20W MF 201 2 1K U5000 (MASTER) PP3V3_S0 R5370 1 48 SMBUS_SMC_2_S4_SCL 48 SMBUS_SMC_2_S4_SDA Berkelium U4200 1K 2.0K 5% 1/20W MF 2 201 SMBUS_SOC_PMU_SCL 41 SMBUS_SOC_PMU_SDA 41 MAKE_BASE=TRUE 89 I2C_DPMUX_UC_SDA I2C_DPMUX_UC_SDA SMBUS_SMC_2_S4_SCL R5373 1 0 1 15 SML_PCH_0_CLK 15 SML_PCH_0_DATA 110 U5710 SMBUS_SMC_3_SCL 54 56 SMBUS_SMC_3_SDA SMBUS_SMC_3_SDA 54 SMBUS_SMC_2_S4_SCL 53 SMBUS_SMC_2_S4_SDA 53 SMC SMBUS "4" G3H CONNECTIONS 2.0K 5% 1/20W MF 201 2 (MASTER) MAKE_BASE=TRUE 1 SMC CPU, Mem, Airflow, Fixstack Prox R5361 2.0K TMP513AISAR:U5870 5% 1/20W MF 2 201 R53201 1 1.5K R5321 5% 1/20W MF 2 201 46 SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SCL 54 46 SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SDA 54 MAKE_BASE=TRUE MAKE_BASE=TRUE (WRITE: 0X70 READ: 0X71) 48 SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SCL 29 48 SMBUS_SMC_4_G3H_SDA SMBUS_SMC_4_G3H_SDA 29 MAKE_BASE=TRUE MAKE_BASE=TRUE USB-C PORT CONTROLLER XB USB-C PORT CONTROLLER TA CD3215A (ACE) - U3200 CD3215A (ACE) - UB300 103 SMBUS_SMC_4_G3H_SCL 103 SMBUS_SMC_4_G3H_SDA GPU UA000 (WRITE: 0X7E READ: 0X7F) SMBUS_SMC_4_G3H_SCL 29 SMBUS_SMC_4_G3H_SDA 29 (Write: 0x82 Read: 0x83) (Write: 0x98 Read: 0x99) 100 SMBUS_SMC_1_S0_SCL 100 CD3215A (ACE) - U3100 (Write: 0xB8 Read: 0xB9) GPU THERM U0500 USB-C PORT CONTROLLER XA 1.5K 5% 1/20W MF 201 2 (WRITE: 0X40 READ: 0X41) LYNX POINT LP B PP3V3_G3H U5000 TMP442A: UA960 SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SDA USB-C PORT CONTROLLER TB 99 CD3215A (ACE) - UB400 99 (WRITE: 0X4E READ: 0X4F) (Write: 0x88 Read: 0x89) 15 (Write: 0x96 Read: 0x97) (Write: 0x14 Read: 0x15) 2 R53601 U5000 LYNX POINT LP S0 "SMLink 1" Connections 15 TMP461: U5800 (MASTER) MAKE_BASE=TRUE 54 SMBUS_SMC_3_SCL PP3V3_S0 SMC SMBUS_SMC_3_SDA 56 8.2K 5% 1/20W MF 2 201 54 U6000 SMC SMBus "1" S0 Connections R5311 SMBUS_SMC_3_SCL TBT & Airflow Right 109 PP3V3_S0 (MASTER) 0 (Write: 0x90 Read: 0x91) CARBON 53 EADC2 5% 1/20W MF 0201 LYNX POINT LP S0 "SMLink 0" Connections 5% 1/20W MF 201 2 54 (Write: 0xD5 Read: 0xD4) R5372 8.2K SMBUS_SMC_3_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA 103 SMBUS_SMC_4_G3H_SCL 103 SMBUS_SMC_4_G3H_SDA SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016 PAGE TITLE SMBus Connections DRAWING NUMBER Apple Inc. 051-00647 REVISION R SMLink 1 is slave port to access PCH. NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SMC WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 C TMP461: U5850 SMBUS_SMC_3_SDA 2 UGLY HACK 1 54 53 SMBUS_SMC_2_S4_SDA 5% 1/20W MF 0201 R53101 SMBUS_SMC_3_SCL TBT & Airflow Left SMBUS_SMC_3_SCL 43 (Write: 0x10 Read: 0x11) MAKE_BASE=TRUE U0500 MAKE_BASE=TRUE (Write: 0x92 Read: 0x93) J4501 U5700 MAKE_BASE=TRUE MAKE_BASE=TRUE LYNX POINT LP 46 SMBUS_SMC_3_SDA MAKE_BASE=TRUE TMP105: J9510 Trackpad EADC1 SMBUS_SOC_PMU_SCL SMBUS_SOC_PMU_SDA I2C_DPMUX_UC_SCL 49 5% 1/20W MF 2 201 (Write: 0x99 Read: 0x98) I2C_DPMUX_UC_SCL 110 SMBUS_SMC_3_SCL X100 Temp 2.0K 5% 1/20W MF 201 2 46 R5391 (Write: 0x78 Read: 0x79) R5306 89 B 114 1 2.0K (MASTER) 114 Connections R53901 U5000 PP3V3_S4 D PP3V3_S0 SMC MAKE_BASE=TRUE 110 A 1 SMC SMBus "5" G3H Connections Internal DP 110 PP3V3_S0 R5300 U0500 3 SMC SMBus "0" S0 Connections PP3V3_S0 LYNX POINT LP 4 1 53 OF 145 49 OF 121 SIZE D A 8 7 6 5 4 3 CPU High Side Current Sense (IC0R) Gain: 100x, EDP: 16.8 A Rsense: 0.001 (R5400) Vsense: 16.8 mV, Range: 30 A SMC ADC: 00 (PRODUCTION) 109 D (to CPU High Side Threshold Alert circuit) 10% 2 6.3V CERM-X5R 0201 3 0612 1 3 MF-3 1W 1% INA214 SC70 CRITICAL R5409 OUT 100x REF 4 IN+ ISNS_HS_COMPUTING_P 4 PLACE_NEAR=U5400.4:10MM R5400 CRITICAL 2 CPUHI_IOUT 6 1 1 1 4.53K 2 SMC_CPU_HI_ISENSE 1% 1/20W MF 201 R5405 15K 1 48 IN 48 OUT 0.1UF PLACE_NEAR=U5000.G4:5MM PPBUS_G3H 109 R5410 0.005 1% 1/3W MF 0306-SHORT 2 4 PPBUS_HS_OTH5V UQFN CRITICAL OTHERISNS ISNS_HS_OTHER5V_N 4 IN5 IN- REF 8 PLACE_NEAR=U5410.4:5:10MM 1 NC 1 NC 7 200x NC NC 1 453K 1% 1/20W MF 201 R5415 1 OUT C5419 1% 1/20W MF 2 201 48 OMIT R5440 1 0.005 1% 1/3W MF 0306-SHORT 2 4 109 PPBUS_HS_OTH3V3 INA210A UQFN 2 IN+ 3 IN+ OTHERRC:YES PLACE_NEAR=U5700.3:5MM CRITICAL OTHERISNS ISNS_HS_OTHER3V3_N 4 IN5 IN- REF 8 PLACE_NEAR=U5440.4:5:10MM 1 NC 1 NC 7 200x B 110 55 53 52 51 50 NC NC GND IN U5450 2 IN+ 3 IN+ 4 IN5 IN- PLACE_NEAR=R8400.3:5MM 50 51 52 53 UQFN 5 REF 8 1 NC 1 NC 7 100x SMC_DCIN_VSENSE 453K 1% 1/20W MF 201 1 4.75K 1% 1/20W MF 201 2 EADC2_OTHER3V3_HI_ISENSE 2 OUT 0.22UF 20% 2 6.3V X5R 0201 OTHERRC:YES PLACE_NEAR=U5710.4:5MM GND_EADC2_COM 1% 1/20W MF 201 50 51 52 53 48 OUT 114 C5499 0.22UF 20% 6.3V PLACE_NEAR=U5000.C2:5MM X5R 2 0201 PLACE_NEAR=U5000.C2:5MM GND_SMC_AVSS 64 Charger Gain: 20x, EDP: 4.6 A Rsense: 0.020 (R7020) PLACE_NEAR=U5000.G1:5MM SMC ADC: 03 (PRODUCTION) R5439 45.3K 2 1 SMC_DCIN_ISENSE CHGR_AMON IN 1% 1/20W MF 201 C5429 1 48 OUT 46 47 48 50 51 53 55 DC-IN (AMON) Current Sense (ID0R) Charger Gain: 20x, EDP: 7.2 A PLACE_NEAR=U5000.G2:5MM Rsense: 0.005 (R7060) SMC ADC: 02 R5429 (PRODUCTION) 300K 2 1 CHGR_BMON SMC_BMON_ISENSE 114 64 IN C5449 1% 1/20W MF 201 2 PDCINVSENS_EN_L_DIV Charger (BMON) Current Sense (IPBR) 53 1 R5499 1 69.8K 1% 1/20W MF 2 201 3300PF 1 48 C5439 2200PF 10% 2 10V X7R-CERM 0201 53 55 OUT PLACE_NEAR=U5000.G1:5MM GND_SMC_AVSS 46 47 48 50 51 53 55 B LOADISNS 1 453K 2 1% 1/20W MF 201 R5455 6.04K NC NC R5459 OUT 53 C5459 PART NUMBER 0.22UF 20% 2 6.3V X5R 0201 1% 1/20W MF 2 201 9 PLACE_NEAR=U5700.22:5MM EADC1_LCDBKLT_ISENSE 1 LOADISNS PLACE_NEAR=U5450.10:5MM LOADRC:YES PLACE_NEAR=U5700.22:5MM GND_EADC1_COM 50 51 52 53 QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 117S0008 2 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5419,C5449 OTHERRC:NO 117S0008 1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5459 LOADRC:NO 117S0008 1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5469 TPADRC:NO OMIT R5460 0.005 110 1% 1/3W MF 0306-SHORT 2 PPBUS_S4_HS_TPAD 4 PLACE_NEAR=U5460.4:7MM 1 3 PLACE_NEAR=U5460.3:7MM ISNS_TPAD_P A PP3V3_S4SW_SNS 4 VIN+ VIN- SOT23-5 OPA2340 0.1UF 2 10% 6.3V CERM-X5R 2 0201 OUT 1 ISNS_X239_IOUT_BUF 1 1% 1/20W MF 2 201 55 53 52 51 50 110 PP3V3_S4SW_SNS C5462 0.1UF 2 1 10% 6.3V CERM-X5R 2 0201 Gain: 1000uA/V * 24.9KOhm = 24.9 7 TPADISNS CRITICAL TPADISNS 6 U5462 1 10K 2 8 5 1% 1/20W MF 201 6 OPA2340 MSOP 7 V+ ISNS_X239_INT_NI U5462 V- 4 TPADISNS V- R5468 4 1 10K 1% 1/20W MF 201 TPADISNS BYPASS=U5462.8::5MM 2 TPADISNS 10K R5469 1 4.53K 2 SMC_TPAD_ISENSE 1% 1/20W MF 201 1 TPADISNS 2 53 PAGE TITLE C5469 SYNC_DATE=04/14/2016 Power Sensors: High Side 0.22UF 20% 6.3V TPADRC:YES X5R DRAWING NUMBER Apple Inc. 0201 051-00647 REVISION R GND_EADC2_COM 50 51 52 53 2 1% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 4 BOM_COST_GROUP=SENSORS 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT ISNS_X239_INT_I 5 SYNC_MASTER=X363_ZIFENGSHEN OUT PLACE_NEAR=U5710.5:5MM R5467 1 PLACE_NEAR=U5710.5:5MM ISNS_X239_IOUT_INT MSOP 1 V+ R5461 24.9K 8 3 TPADISNS PLACE_NEAR=U5460.1:5MM BYPASS=U5460.5::5MM TPADISNS WWW.AliSaler.Com ISNS_X239_IOUT U5460 GND PP3V3_S4SW_SNS 109 TPADISNS CRITICAL INA139 55 53 52 51 50 R5465 3 5 V+ 1 OUT ISNS_TPAD_N TPADISNS CRITICAL 8 P-CHANNEL R5491 1 1 15K Rthevenin = 4573 Ohms C5450 GND C5460 1% 1/20W MF 201 2 G PLACE_NEAR=U5000.G2:5MM GND_SMC_AVSS 46 47 48 50 51 ISNS_LCDBKLT_IOUT OUT 10 CRITICAL Gain: 49.8x, EDP: 2.61 A (Transient) Rsense: 0.02 (R5460) Vsense: 52.2 mV, Range: 3.31 A EADC2: CH7 PPBUS_G3H 109 IN 55 53 52 51 50 R5498 1 31.6K PPDCIN_G3H 64 29 C PLACE_NEAR=U5000.C2:5MM D R5449 R5445 Trackpad Actuator X239 Current Sense (ITAR) 110 DCIN_S5_VSENSE 10% 2 10V X7R-CERM 0201 BYPASS=U5450.6::5MM INA214A LOADISNS ISNS_LCDBKLT_N 1% 1/20W MF 201 2 4 OTHERISNS PLACE_NEAR=U5440.10:5MM 10% 2 6.3V CERM-X5R 0201 6 75 IN 200K G 0.1UF V+ 75 R5492 1 LOADISNS 1 PLACE_NEAR=R8400.4:5MM ISNS_LCDBKLT_P D 3 LCD Backlight Current Sense (IBLR) Gain: 100x. EDP: 0.87 A Rsense: 0.025 (R8400) Vsense: 21.75 mV, Range: 1.32 A EADC1: CH0 PP3V3_S4SW_SNS DCINVSENS_EN_L 6 1 114 50 51 53 55 SOT963 S OTHERISNS PLACE_NEAR=U5710.4:5MM HS_OTHER3V3_IOUT OUT 10 PLACE_NEAR=U5000.G3:5MM GND_SMC_AVSS 46 47 48 Q5490 2 C5441 9 117 U5440 PLACE_NEAR=U5440.2:3:10MM 3 ISNS_HS_OTHER3V3_P 2 X5R 0201 DMC31D5UDJ SMC_BC_ACOK IN C5489 CRITICAL 0.22UF 0.1UF 6 109 PBUSVSENS_EN_L_DIV 48 OUT 0.22UF 20% 6.3V PLACE_NEAR=U5000.G3:5MM 1% 1/20W MF 201 2 S V+ 1 5.49K Enables DC-In VSense divider when AC present. 20% 2 6.3V X5R 0201 10% 2 6.3V CERM-X5R 0201 SMC_PBUS_VSENSE R5489 1 N-CHANNEL 116 1 Rthevenin = 4573 Ohms P-CHANNEL 1 53 OTHERISNS BYPASS=U5440.6::5MM PPBUS_G3H 1% 1/20W MF 201 2 S Gain: 0.13067x Vnominal: 20 V, Range: 22 V SMC ADC: 04 (PRODUCTION) EADC1_OTHER5V_HI_ISENSE 2 OTHERISNS PLACE_NEAR=U5410.10:5MM PP3V3_S4SW_SNS 50 27.4K 4 OTHER 3.3V High Side Current Sense (IO3R) 110 R5488 1 DC In Voltage Sense & Enable (VD0R) GND_EADC1_COM Gain: 200x, EDP: 4.31 A Rsense: 0.003 (R5440) or Rsense SHORT Vsense: 12.93 mV, Range: 5 A SMC ADC:8 PBUS_S0_VSENSE G 1% 1/20W MF 201 2 15K GND C 5 2 46 47 48 50 51 53 55 R5419 HS_OTHER5V_IOUT OUT 10 9 109 INA210A 2 IN+ 3 IN+ D D PBUS_S0_VSENSE_IN PLACE_NEAR=R5400.1:70 MM 1 OTHERISNS PLACE_NEAR=U5700.3:5MM 10% 2 6.3V CERM-X5R 0201 U5410 PLACE_NEAR=U5410.2:3:10MM ISNS_HS_OTHER5V_P 1% 1/20W MF 201 2 S XW5480 SM C5411 1 1 3 100K G 3 OTHERISNS BYPASS=U5410.6::5MM V+ OMIT R5482 1 100K PP3V3_S4SW_SNS PPBUS_G3H 2 R5481 6 109 D SMC_SENSOR_PWR_EN OTHER 5V High Side Current Sense (IO5R) 50 PBUSVSENS_EN_L 6 1 GND_SMC_AVSS 110 SOT-963 N-CHANNEL C5409 20% 2 6.3V X5R 0201 PLACE_NEAR=U5400.6:5MM Gain: 200x, EDP: 1.22 A Rsense: 0.01 (R5410) or Rsense SHORT Vsense: 12.2 mV, Range: 1.5 A SMC ADC:7 Q5480 NTUD3169CZ 0.22UF 5% 1/20W MF 2 201 GND 2 PPBUS_G3H 5 IN- CRITICAL Enables PBUS VSense divider when in S0. PLACE_NEAR=U5000.G4:5MM U5400 PLACE_NEAR=U5400.5:10MM ISNS_HS_COMPUTING_N 51 OUT 0.1UF 0.001 109 C5401 1 V+ 52 Gain: 0.167x Vnominal: 12.6 V, Range: 17.97 V SMC ADC: 01 (PRODUCTION) BYPASS=U5400.3::5MM PPBUS_HS_CPU 1 PBUS Voltage Sense & Enable (VP0R) PP3V3_S0_LEFT 110 2 1 54 OF 145 50 OF 121 SIZE D A 7 6 5 4 BYPASS=U5560.6::5MM 1 0.1UF 6 U5560 72 D IN 72 IN INA210A 2 IN+ 3 IN+ UQFN REF 8 200x 4 IN5 IN- 1 NC 1 NC 7 NC NC GND R5569 1 453K R5565 1 OUT 66 48 55 IN CPUCORE_ISNS2_P NO_XNET_CONNECTION=1 0.1% 1/20W 20% 2 6.3V X5R 0201 66 IN CPUCORE_ISNS3_P 1 NO_XNET_CONNECTION=1 PLACE_NEAR=R7230:5MM 66 IN 46 47 48 50 51 53 55 CPUCORE_ISNS1_N 1 NO_XNET_CONNECTION=1 DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C) 1 U5570 71 ISNS_CPUDDR_N IN 71 5 IN- PLACE_NEAR=R7918.3:5MM ISNS_CPUDDR_P IN 4 IN+ INA214 SC70 OUT CRITICAL DDRISNS 100x PLACE_NEAR=R7918.4:5MM 1 REF 1 1 4.53K 2 1% 1/20W MF 201 R5575 2 1 48 OUT C5579 110 PP1V2_S3_CPUDDR 0306-SHORT 2 MF 1/3W 1% 0.005 R5510 1 5 IN- INA210 SC70 200x 4 IN+ ISNS_CPUVDDQ_P OUT CRITICAL LOADISNS 3 PLACE_NEAR=U5510.4:5:10MM PP3V3_S5_T139 53 1 1% 1/20W MF 201 R5515 INA210A UQFN CRITICAL REF 8 4 IN5 IN- 1 NC 1 NC 7 200x NC NC GND SMC_CPUDDR_ISENSE 1 OUT D5530 SC2 A K C5519 110 PP3V3_S4_WLAN 1 453K 1% 1/20W MF 201 R5525 2 ISNS_BT_IOUT REF 8 NC 1 NC 7 R5589 1 1 1/20W 0.1% 1 1 Trip Target on CPU High current: TBD A Hysteresis Circuit: Vref = 0.737 V Vth = 0.616 V -> 2.054 A on CPU High current Vtl = 0.771 V -> 2.571 A on CPU High current Hysteresis Margin = 0.518 A 46 47 48 50 51 53 55 NC NC EADC2_BT_ISENSE 1% 1/20W MF 201 R5585 OUT R5554 294K 53 LOADRC:YES C C5589 1 5% 1/20W MF 2 201 2.2UF 20% 2 6.3V X5R-CERM 0201 50 52 53 NOSTUFF C5553 0.22UF 2 20% 6.3V X5R 0201 C5551 R5553 10% 2 6.3V CERM-X5R 0201 CPUHI_COMP_FB CPUHYS CPUHYS R5556 1% 1/20W MF 2 201 1 12K 5 3 2 1% 1/20W MF 201 CPUHI_COMP_VREF 4 2 1 255K 2 1% 1/20W MF 201 U5551 MAX9119EXK-T SC70-5 CPUHYS CPUHI_COMP_OUT 1 CPUHI_IOUT_R R5555 PP5V_S4_ISNS_D OUT CRITICAL DFN1006H4-3 GND_EADC1_COM 110 55 53 52 51 50 1 1 1/20W 0.1% 120 2 ISNS_WLAN_R_P MF 0201 LOADISNS 72 C5530 IN INA210A ISNS_1V8_SUS_P 2 IN+ 3 IN+ 0.1UF 72 IN S UQFN CRITICAL LOADISNS ISNS_1V8_SUS_N 4 IN5 IN- D 3 10% 2 6.3V CERM-X5R 0201 200x PLACE_NEAR=R8024.4:5MM 10% 2 6.3V CERM-X5R 0201 REF 8 NC 1 NC 7 1 NC NC 3 R5535 ISNS_PP3V3S4_WLAN_IOUT 1/20W 1 1 0.1% 1/20W MF 2 0201 5% 1/20W MF 201 2 LOADISNS LOADISNS 1% 0 PLACE_NEAR=U5700.2:5MM EADC1_PP3V3S4_WLAN_ISENSE OUT C5539 10% 2 6.3V CERM-X5R 0201 DMN32D2LFB4 OUT PART NUMBER 1 2.2UF 117S0008 20% 6.3V 2 X5R-CERM 0201 D 3 DFN1006H4-3 SYM_VER_2 1 G A K CPUHI_IOUT IN S 2 50 Gain: 200x, EDP: 0.7 A Rsense: 0.025 (R8024) or Rsense SHORT Vsense: 17.5 mV, Range: 0.6 A EADC1: CH1 R5599 1 453K 1% 1/20W MF 201 R5595 20K 2 EADC1_P1V8SUS_ISENSE 1 OUT 53 C5599 0.22UF 20% 2 6.3V X5R 0201 5% 1/20W MF 2 201 PLACE_NEAR=U5700.23:5MM LOADRC:YES GND_EADC1_COM 50 51 52 53 SYNC_MASTER=X363_ZIFENGSHEN 53 117S0008 QTY 6 1 SYNC_DATE=04/14/2016 Power Sensors: Load Side DESCRIPTION RES,MTL FLIM,100K,1/16W,0201,SMD,LF RES,MTL FLIM,100K,1/16W,0201,SMD,LF REFERENCE DES C5519,C5529,C5539,C5549,C5589,C5599 C5579 CRITICAL Apple Inc. BOM OPTION LOADRC:NO DDRRC:NO 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT 50 51 52 53 BOM_COST_GROUP=SENSORS 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 B 48 DRAWING NUMBER GND_EADC1_COM 6 SMC_CPUHI_COMP_ALERT_L U5552 0.1UF 5% 1/20W MF 2 0201 PLACE_NEAR=U5700.2:5MM LOADRC:YES 7 C5552 PAGE TITLE MF 201 CPUHYS R5534 17.4K 100K 4.53K 2 1 1 LOADISNS PLACE_NEAR=U5700.23:5MM NOSTUFF PLACE_NEAR=U5590.10:5MM 9 G R5539 1 IAPC_OPA_OUT 145x P1V8SUS_IOUT LOADISNS 4 CRITICAL LOADISNS OUT 10 GND TSOT23-5 C5590 0.1UF U5590 PLACE_NEAR=R8024.3:5MM NOSTUFF R5552 LOADISNS BYPASS=U5590.6::5MM PP3V3_S4SW_SNS 50 51 52 53 LOADISNS BYPASS=U5530.6::5MM LOADISNS R5557 BMON_IOUT_D RB521ZS-30 1.8V Current Sense (I18C) PLACE_NEAR=U5700.1:5MM LOADRC:YES 1 CPUHYS 1 0 D5557 SM-201 53 C5529 LTC2050HVCS5 2 ISNS_WLAN_R_N MF 0201 NOSTUFF 1 NOSTUFF 20% 2 6.3V X5R 0201 Q5530 DMP31D0UFB4 R5532 WWW.AliSaler.Com 4.53K 2 20K 5% 1/20W MF 2 0201 0.22UF 5% 1/20W MF 2 201 5 120 PLACE_NEAR=R5532.1:10MM 8 1 0.1UF CPUHYS EADC1_PP3V3S5_T139_ISENSE 1 ISNS_WLAN_P OUT 10 CPUHYS R5529 20K VOLTAGE=5V R5533 2 4 NO_XNET_CONNECTION=1 BYPASS=U5551.5::5MM 1 GND_SMC_AVSS 46 47 48 50 51 53 55 LOADISNS NOSTUFF 48 PLACE_NEAR=U5000.H1:5MM LOADRC:YES LOADISNS LOADISNS R5530 GND_SMC_AVSS 1 0.22UF NOSTUFF PLACE_NEAR=U5520.10:5MM U5530 0.005 200x 4 IN5 IN- LOADISNS PLACE_NEAR=U5700.1:5MM 2 OMIT PP3V3_S4_BT CRITICAL LOADISNS ISNS_BT_N PLACE_NEAR=U5580.4:5:10MM V+ PP5V_S4 ISNS_WLAN_N ISNS_BT_P UQFN 2 IN+ 3 IN+ C5520 ISNS_PP3V3S0_IOUT OUT 10 LOADISNS ISNS_T139_N 0306-SHORT 1 3 MF 1/3W 1% 1 3 INA210A 1% 1/20W MF 2 201 10% 2 6.3V CERM-X5R 0201 2 A LOADRC:YES PLACE_NEAR=U5000.A1:5MM 2 10% 2 6.3V CERM-X5R 0201 U5580 PLACE_NEAR=U5580.2:3:10MM Gain: 100x Rsense: 0.001 (R5400) 110 PP3V3_S0 20% 2 6.3V X5R 0201 DSF01S30SCAP 110 20% 2 6.3V X5R 0201 LOADISNS BYPASS=U5580.6::5MM C5580 LOADISNS 0.1UF NO_XNET_CONNECTION=1 9 4.53K 2 1 0.1UF U5520 IN+ 3 IN+ PP3V3_S4 PLACE_NEAR=R5533.1:10MM 1 V+ LOADISNS BYPASS=U5520.6::5MM PP3V3_S4SW_SNS 51 50 55 53 WLAN Current Sense (IAPC) Gain: 200x, EDP: 1.67 A 110 0.22UF 84.5K PLACE_NEAR=U5520.4:5:10MM Rsense: 0.01 (R5530) or Rsense SHORT Vsense: 25.05 mV, Range: 1.88 A EADC1: CH4 PP3V3_S4SW_SNS CPUHYS 9 110 53 52 51 50 110 55 1 PLACE_NEAR=U5520.2:3:10MM 3 2 ISNS_T139_P 1% 1/3W MF 0306-SHORT 2 4 0.1% 1/20W MF 0201 0.1% 1/20W MF 0201 PP3V3_S4 6 0.005 715K 1 D C5549 CPU High Side Current (IC0R) Threshold Alert R5519 5% 1/20W MF 2 201 GND PP3V3_S5 R5520 1 CPUVR_ISNS_R_N 48 OUT MF 0201 46 47 48 50 51 53 55 LOADISNS PLACE_NEAR=U5000.H1:5MM 20K V+ OMIT 2.55K 2 1% 1/3W MF 0306-SHORT 2 4 C5510 1 REF 1 6 110 20K R5541 0.005 T139 Current Sense (IF3C) B 1 MF 0201 PLACE_NEAR=U5000.B3:5MM DDRRC:YES NOSTUFF PLACE_NEAR=U5510.6:5MM Gain: 200x, EDP: 0.06 A Rsense: 0.05 (R5520) or Rsense SHORT 52 Vsense: 3 mV, Range: 0.25 A 110 EADC1: CH3 CPUVR_ISNS_N 4.42K 2 1 0.1% 1/20W R5540 1 GND_EADC2_COM ISNS_CPUDDR_IOUT 6 2 109 PP1V2_S3 U5510 PLACE_NEAR=U5510.5:3:10MM 4 ISNS_CPUVDDQ_N R5543 R5580 GND_SMC_AVSS 1 SMC_CPU_ISENSE 5% 1/20W MF 2 201 GND 10% 2 6.3V CERM-X5R 0201 V+ OMIT 4.42K 2 4.53K 2 V- LOADISNS OMIT 110 0.1UF 3 109 0.1% 1/20W MF 2 0201 LOADISNS R5549 1 1% 1/20W MF 201 LOADISNS BYPASS=U5510.3::5MM PP3V3_S4SW_SNS 50 53 MF 0201 Rsense: 0.05 (R5580) or XWTBD Vsense: 3 mV, Range: 0.25 A EADC2: CH05 CPU DDR 1.2V S3 (CPU Only) Current Sense (IMCC) Gain: 200x, EDP: 2 A Rsense: 0.005 (R5510) or Rsense SHORT 52 51 Vsense: 10 mV, Range: 3 A 110 55 SMC ADC: 18 3 LOADISNS PLACE_NEAR=U5000.A1:5MM NOSTUFF PLACE_NEAR=U5540.4:5MM 20% 2 6.3V X5R 0201 NOSTUFF PLACE_NEAR=U5570.6:5MM 715K CPUVR_ISUM_IOUT NO_XNET_CONNECTION=1 R5551 NO_XNET_CONNECTION=1 SC70-5 4 4.42K 2 0.1% 1/20W CPUCORE_ISNS3_N 0.22UF 5% 1/20W MF 2 201 C SMC_DDR1V2_ISENSE 1 R5544 10% 2 6.3V X7R 0201 ISL28133 V+ C5540 0.1UF U5540 1 BT Current Sense (IBTC) Gain: 200x, EDP: 0.06 A R5579 20K GND NO_XNET_CONNECTION=1 PLACE_NEAR=R7230:5MM DDRISNS PLACE_NEAR=U5000.B3:5MM ISNS_DDR_IOUT 6 IN C5570 10% 2 6.3V CERM-X5R 0201 V+ 1 LOADISNS 0.1UF 3 110 CPUCORE_ISNS2_N PLACE_NEAR=R7220:5MM 66 MF 0201 R5548 LOADISNS DDRISNS BYPASS=U5570.3::5MM PP3V3_S4SW_SNS 52 50 51 55 53 4.42K 2 0.1% 1/20W PLACE_NEAR=R7210:5MM IN 0.1% 1/20W MF 0201 CPUVR_ISNS_R_P 1 R5547 LOADISNS 66 CPUVR_ISNS_P MF 0201 0.1% 1/20W LOADISNS NOSTUFF PLACE_NEAR=U5000.B5:5MM 2.55K 2 1 1 LOADISNS CRITICAL R5542 R5550 PLACE_NEAR=R7220:5MM LOADISNS BYPASS=U5540.5::5MM LOADISNS 4.42K 2 1 LOADISNS GND_SMC_AVSS Gain: 100x, EDP: 9.01 A Rsense: 0.003 (R7918) or XWTBD Vsense: 27.03 mV, Range: 10 A SMC ADC: 09 1 PP3V3_S0 110 MF 0201 R5546 C5569 NOSTUFF PLACE_NEAR=U5560.10:5MM 0.1% 1/20W LOADISNS 0.22UF 5% 1/20W MF 2 201 NO_XNET_CONNECTION=1 PLACE_NEAR=R7210:5MM SMC_CPU_IMON_ISENSE 2 1% 1/20W MF 201 51K 9 IN PLACE_NEAR=U5000.B5:5MM NOSTUFF PCH_1V0_IOUT OUT 10 CRITICAL LOADISNS PLACE_NEAR=R8004.3:5MM ISNS_1V0_N 66 NO_XNET_CONNECTION=1 10% 2 6.3V CERM-X5R 0201 V+ PLACE_NEAR=R8004.4:5MM ISNS_1V0_P C5560 5 LOADISNS Gain: 177.71x, EDP: 67 A Rsense: 3x of 0.00075 (R7210, R7220,R7230), Rsum: 0.00025 Vsense: 16.75 mV, Range: 67.52 A SMC ADC: 06 R5545 4.42K 2 1 CPUCORE_ISNS1_P 2 PP3V3_S4SW_SNS 51 50 53 52 55 110 2 CPU Fixed Current Sense (ICAC) PCH 1.0V Current Sense (ISCC) Gain: 200x, EDP: 4.11 A Rsense: 0.003 (R8004) or XWTBD Vsense: 11.33 mV, Range: 5 A SMC ADC: 22 3 6 8 1 55 OF 145 51 OF 121 SIZE D A 8 7 6 5 4 T139 5V Current Sense (IF5C) Gain: 200x, EDP: 0.004 A Rsense: 0.05 (R5630) or Rsense SHORT Vsense: 0.2 mV, Range: 0.25 A EADC1: CH6 55 53 52 51 50 C5630 0.1UF 6 0.005 D IN+ 3 IN+ 1% 1/3W MF 0306-SHORT 2 4 PP5V_S0_T139 UQFN CRITICAL REF 8 LOADISNS ISNS_PP5V_T139_N 4 IN5 IN- 1 NC 1 NC 7 200x PLACE_NEAR=U5630.4:5:10MM 1 453K R5635 1 1 PLACE_NEAR=U5700.4:5MM LOADRC:YES 52 50 GND_EADC1_COM 50 51 52 53 0.1UF CRITICAL REF 8 200x 4 IN5 IN- NC 1 NC 7 1 NC NC C5649 PP3V3_S0 ISNS_LCDPANEL_N 4 IN5 IN- R5680 C5620 REF 8 200x 1 NC 1 NC 7 NC NC R5629 1 453K 2 R5625 51K 9 INA210A 2 IN+ 3 IN+ UQFN OUT 10 CRITICAL TPADISNS REF 4 IN5 IN- 200x PLACE_NEAR=U5650.4:5:10MM NC 1 NC 7 55 53 52 51 50 PP3V3_S4SW_SNS PP3V3_S4 OMIT R5655 R5610 0.005 1% 1/3W MF 0306-SHORT 2 4 A UQFN CRITICAL LOADISNS 4 IN5 IN- ISNS_CAMERA_N PLACE_NEAR=U5610.4:5:10MM 200x GND 9 110 PP3V3_S4_SOC_PMU 2 IN+ 3 IN+ REF 8 NC 1 NC 7 NC NC 55 53 52 51 50 EADC1_TBT_T_ISENSE 2 1% 1/20W MF 201 R5685 1 OUT 53 C5689 0.22UF 20K 20% 5% 1/20W MF 2 201 2 6.3V X5R 0201 TBTRC:YES PLACE_NEAR=U5700.24:5MM GND_EADC1_COM 50 51 52 53 LOADISNS PP3V3_S4SW_SNS BYPASS=U5690.6::5MM 1 R5690 453K EADC2_PP3V3_TPAD_ISENSE 2 1 OUT C5659 0.22UF 1 3 1% 1/3W MF 0306-SHORT 2 4 53 110 ISNS_T151_P 2 IN+ 3 IN+ UQFN CRITICAL LOADISNS ISNS_T151_N 4 IN5 IN- PP3V3_S4_T151 NC 1 NC 7 1 NC NC PLACE_NEAR=U5710.23:5MM TPADRC:YES GND_EADC2_COM 20K NOSTUFF PLACE_NEAR=U5610.10:5MM C5699 0.22UF PLACE_NEAR=U5710.2:5MM LOADRC:YES NOSTUFF PLACE_NEAR=U5690.10:5MM GND_EADC2_COM 50 51 52 53 50 51 52 53 QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION LOADISNS 117S0008 2 RES,MTL FILM,100K,1/16W,0201,SMD,LF C5649,C5689 TBTRC:NO R5619 117S0008 1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5659 TPADRC:NO 1 OUT 53 C5619 0.22UF SYNC_MASTER=X363_ZIFENGSHEN PAGE TITLE SYNC_DATE=04/14/2016 Power Sensors: Extended DRAWING NUMBER LOADRC:YES PLACE_NEAR=U5710.24:5MM GND_EADC2_COM Apple Inc. 50 51 52 53 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SENSORS WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 53 0201 LOADRC:NO EADC2_CAMERA_ISENSE 1 OUT 20% C5619,C5629,C5639,C5699 2 EADC2_T151_ISENSE 2 6.3V X5R RES,MTL FILM,100K,1/16W,0201,SMD,LF 453K 2 5% 1/20W MF 2 201 4 1 453K 1% 1/20W MF 201 R5695 20% 2 6.3V X5R 0201 5% 1/20W MF 2 201 1 117S0008 1% 1/20W MF 201 20K REF 8 B R5699 ISNS_T151_IOUT OUT 10 GND PLACE_NEAR=U5710.24:5MM R5615 200x LOADISNS PLACE_NEAR=U5710.2:5MM 10% 2 6.3V CERM-X5R 0201 U5690 INA210A C5690 0.1UF V+ OMIT C5610 1 110 PP3V3_S4 PART NUMBER ISNS_CAMERA_IOUT OUT 10 NC NC 453K NOSTUFF 20% 6.3V 2 X5R 0201 10% 2 6.3V CERM-X5R 0201 U5610 INA210A PLACE_NEAR=U5610.2:3:10MM 1 3 ISNS_CAMERA_P 1 6 1 1% 1/20W MF 201 0.1UF V+ Gain: 200x, EDP: 0.1638 A Rsense: 0.05 (R5690) or Rsense SHORT Vsense: 819 mV, Range: 0.25 A EADC2: CH4 110 LOADISNS 6 110 50 51 52 53 BYPASS=U5610.6::5MM 1 200x NC 1 NC 7 GND 0.005 NOSTUFF PLACE_NEAR=U5650.10:5MM 9 110 1 T151 Current Sense (IIDC) PLACE_NEAR=U5710.22:5MM Camera Current Sense (ICMC) Gain: 200x. EDP: 0.82 A Rsense: 0.015 (R5610) or XW5610 Vsense: 12.3 mV, Range: 0.83 A EADC2: CH2 R5689 REF 8 C5629 LOADRC:YES 5% 1/20W MF 2 201 GND 4 IN5 IN- 53 R5659 20K NC NC ISNS_TBT_T_N PLACE_NEAR=U5700.24:5MM ISNS_TBT_T_IOUT OUT 10 CRITICAL TBTISNS PLACE_NEAR=U5670.10:5MM TPADISNS PLACE_NEAR=U5710.23:5MM ISNS_PP3V3_TPAD_IOUT 1 UQFN TBTISNS PLACE_NEAR=U5670.4:5:10MM PP3V3_TBT_T_S0 C5650 8 10% 2 6.3V CERM-X5R 0201 20% 6.3V 2 X5R 0201 10% 6.3V 2 CERM-X5R 0201 U5650 0.1UF INA210A 2 IN+ 3 IN+ C C5680 0.22UF 5% 1/20W MF 2 201 0.1UF 6 PP3V3_S4_TPAD OUT TPADISNS BYPASS=U5650.6::5MM PP3V3_S4 ISNS_PP3V3_TPAD_N EADC2_LCDPANEL_ISENSE GND_EADC2_COM V+ 1% 1/3W MF 0306-SHORT 2 4 110 1 PLACE_NEAR=U5620.10:5MM 1 BYPASS=U5670.6::5MM 9 1% 1/20W MF 201 LOADISNS PP3V3_S4SW_SNS TBTISNS U5670 PLACE_NEAR=U5670.2:3:10MM 1 3 ISNS_TBT_T_P 1% 1/3W MF 0306-SHORT 2 4 PLACE_NEAR=U5710.22:5MM ISNS_LCDPANEL_IOUT OUT 10 0.005 LOADISNS 10% 2 6.3V CERM-X5R 0201 UQFN PP3V3_S4SW_SNS PP3V3_S0 OMIT 0.1UF CRITICAL 55 53 52 51 50 V+ BYPASS=U5620.6::5MM LOADISNS PLACE_NEAR=U5650.2:3:10MM ISNS_PP3V3_TPAD_P PLACE_NEAR=U5660.10:5MM 50 51 52 53 LOADISNS 2 IN+ 3 IN+ 1 3 SENSE+ pins of EMC1704 sink 10-20uA current. This deviation has been designed in our Peak Detection circuit. With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV NOSTUFF 1 110 ISNS_LCDPANEL_P 55 53 52 51 50 0.22UF 20% 2 6.3V X5R 0201 PLACE_NEAR=U5700.5:5MM Trackpad 3V Current Sense (IT3C) 110 110 GND_EADC1_COM GND Gain: 200x, EDP: 0.2 A Rsense: 0.05 (R5650) or Rsense SHORT Vsense: 10 mV, Range: 0.25 A EADC2: CH1 In battery discharge scenario negative voltage will be present on IN+/- pins with INA output voltage decreasing from 3.3V with increasing discharge current. C5665 9 IN 1 5% 1/20W MF 2 201 TBTRC:YES PLACE_NEAR=U5640.10:5MM INA210A 5% 1/20W MF 0201 Rsense: 0.025 (R5680) or Rsense SHORT Vsense: 12.5 mV, Range: 0.5 A EADC1: CH2 0.22UF NOSTUFF 6 76 53 OUT 20% 2 6.3V X5R 0201 V+ IN 1 5% 1/20W MF 2 201 1 76 EADC1_TBT_X_ISENSE 2 1% 1/20W MF 201 20K 9 110 453K 1 R5645 U5620 110 GND 15K 2 Thunderbolt TBT RIGHT Current Sense (IURC) Gain: 200x. EDP: 0.5 A R5649 ISNS_TBT_X_IOUT OUT 10 TBTISNS ISNS_TBT_X_N Gain: 200x. EDP: 1 A RSENSE: 0.01 (R8520) or Rsense SHORT Vsense: 5 mV, Range: 1.25 A EADC2: CH0 0.005 NC NC 5% 1/20W MF 0201 R5664 0 1 PLACE_NEAR=U5700.5:5MM LCD Panel Current Sense (ILDC) R5650 NC 1 NC 7 PLACE_NEAR=U5660.10:10MM D R5669 2 ISNS_CPUHIGAIN_OUT_R 6 2 IN+ 3 IN+ PLACE_NEAR=U5640.4:5:10MM OMIT 200x 4 IN5 IN- 54 5% 1/20W MF 0201 TBTISNS 10% 2 6.3V CERM-X5R 0201 UQFN C 110 LOADISNS ISNS_HS_COMPUTING_N 1 0 OUT 2 ISNS_CPUHIGAIN_N ISNS_HS_COMPUTING_N IN 54 C5640 GND B REF 8 1 TBTISNS U5640 PP3V3_TBT_X_S0 110 IN CRITICAL ISNS_CPUHIGAIN_OUT OUT 10 BYPASS=U5640.6::5MM INA210A PLACE_NEAR=U5640.2:3:10MM 1 3 ISNS_TBT_X_P 1% 1/3W MF 0306-SHORT 2 4 2 IN+ 3 IN+ 9 PP3V3_S4SW_SNS 6 0.005 ISNS_HS_COMPUTING_P 2 5% 1/20W MF 0201 R5661 52 50 0 0 1 R5668 1% 1/20W MF 2 201 R5665 CKPLUS_WAIVE=NdifPr_badTerm CKPLUS_WAIVE=NdifPr_badTerm PP3V3_S0_LEFT R5640 IN UQFN PLACE_NEAR=R5400.4:10MM V+ OMIT INA210A PLACE_NEAR=R5400.3:10MM 52 50 1 110 U5660 PLACE_NEAR=U5660.10:10MM 1 OUT R5667 NOSTUFF 16K V+ ISNS_CPUHIGAIN_P ISNS_HS_COMPUTING_P IN PLACE_NEAR=U5660.10:10MM C5639 CKPLUS_WAIVE=NdifPr_badTerm CKPLUS_WAIVE=NdifPr_badTerm 52 50 ISNS_CPUHIGAIN_R_N BYPASS=U5660.6::5MM 53 OUT Rsense: 0.025 (R5640) or Rsense SHORT Vsense: 12.5 mV, Range: 0.5 A EADC1: CH7 55 53 52 51 50 1% 1/20W MF 2 201 10% 2 6.3V CERM-X5R 0201 20% 2 6.3V X5R 0201 NOSTUFF PLACE_NEAR=U5630.10:5MM C5660 2 5% 1/20W MF 0201 R5662 1K 0.1UF 0.22UF 5% 1/20W MF 2 201 GND 1 0 1 PLACE_NEAR=U5660.10:10MM 1 EADC1_PP5V_T139_ISENSE 2 1% 1/20W MF 201 20K NC NC ISNS_CPUHIGAIN_R_P 5% 1/20W MF 201 Thunderbolt TBT LEFT Current Sense (IULC) Gain: 200x. EDP: 0.5 A 110 NOSTUFF R5666 2 R5639 ISNS_PP5V_T139_IOUT OUT 10 9 110 INA210A PP3V3_S0_LEFT LOADISNS PLACE_NEAR=U5700.4:5MM 10% 2 6.3V CERM-X5R 0201 U5630 PLACE_NEAR=U5630.2:3:10MM 2 ISNS_PP5V_T139_P 1 3 110 47 1 6 110 LOADISNS BYPASS=U5630.6::5MM PP3V3_S4SW_SNS PP5V_S0 R5630 1 R5660 V+ OMIT 2 CPU High Side (IC0R) Peak Detection Support 1 110 3 1 56 OF 145 52 OF 121 SIZE D A 6 Current Sense (IHDC) Gain: 200x, EDP: 2.61 A RSENSE: 0.005 (R5750) Vsense: 13.05 mV, Range: 3.0 A SMC ADC: 14 110 55 53 52 51 50 PP3V3_S4SW_SNS LOADISNS BYPASS=U5750.3::5MM 0.1UF 10% 3 PP3V3_SSD_LIM 0306-SHORT 2 MF 1/3W 1% 2 CERM-X5R 0201 R5750 1 MAKE_BASE=TRUE SC70 LOADISNS PLACE_NEAR=U5000.C1:5MM 68 IN 1 LOADISNS SMC_SSDLIM_ISENSE 1% 1/20W MF 201 R5755 20K 1 C5789 OUT LOADRC:YES 68 CPUGT_ISNS2_P IN 1 GND_SMC_AVSS CPUGT_ISNS_R_P 1 110 R5730 1 0.005 IN+ 3 IN+ 1% 1/3W MF 0306-SHORT 2 4 110 PP5V_S0_KBD 4 IN5 IN- PLACE_NEAR=U5730.4:5:10MM NC 1 NC 7 200x 1 1 453K 1 NO_XNET_CONNECTION=1 CPUGT_ISNS_N 0.025 1% 1/3W MF 0306 2 4 CRITICAL PP1V8_S3_MEM CRITICAL GND_EADC2_COM Gain: 200x, EDP: 8 A Rsense: 0.002 (R7570) Vsense: 16 mV, Range: 7.5 A SMC ADC: 17 50 51 52 53 110 55 53 52 51 50 PLACE_NEAR=U5720.4:5:10MM 4 IN5 IN- 0.1UF 67 C5720 200x NC 1 NC 7 NC NC GND 46 47 48 50 51 53 55 LOADISNS NO_XNET_CONNECTION=1 BYPASS=U5770.3::5MM CPUSA_ISNS_N IN 5 IN- PLACE_NEAR=R7370.3:20.5MM CPUSA_ISNS_P IN 4 IN+ CRITICAL LOADISNS 100x 453K 20K PLACE_NEAR=U5000.H2:5MM ISNS_CPUSA_IOUT 1 1 REF 1 1 R5779 4.53K 2 SMC_CPUSA_ISENSE 1% 1/20W MF 201 R5775 20K 1 48 55 OUT OUT 48 C5779 0.22UF 20% 2 6.3V X5R 0201 5% 1/20W MF 2 201 PLACE_NEAR=U5000.H2:5MM NOSTUFF SMC_CPUGT_IMON_ISENSE 2 1% 1/20W MF 201 R5725 2 6.3V X7R 0201 GND NOSTUFF R5729 1 OUT 6 C LOADISNS 10% SC70 PLACE_NEAR=R7370.4:20.5MM C5770 0.1UF INA214 NO_XNET_CONNECTION=1 ISNS_LPDDR_IOUT 1 GND_SMC_AVSS LOADISNS PP3V3_S4SW_SNS 1 BYPASS=U5730.6::5MM REF 8 LOADISNS ISNS_LPDDR_N OUT 10 LOADRC:YES PLACE_NEAR=U5740.4:5MM PLACE_NEAR=U5000.C3:5MM NOSTUFF CPU SA Current Sense (ICSC) LOADRC:YES 3 UQFN 0.22UF C5739 67 LOADRC:YES PLACE_NEAR=U5770.6:5MM GND_SMC_AVSS C5729 46 47 48 50 51 53 55 0.22UF 20% 5% 1/20W MF 2 201 2 6.3V X5R 0201 NOSTUFF NOSTUFF 9 109 INA210A 2 IN+ 3 IN+ C5749 0.1% 1/20W MF 0201 2 6 R5720 PLACE_NEAR=U5720.2:3:10MM ISNS_LPDDR_P 1 3 D 53 PLACE_NEAR=U5710.1:5MM 2 6.3V CERM-X5R 0201 U5720 48 CPUGT_ISNS_R_N 10% V+ 1 OUT 20% 2 6.3V X5R 0201 5% 1/20W MF 2 201 2 0.1% 1/20W MF 0201 U5770 1 R5740 SMC_CPUGT_ISENSE LOADISNS LOADISNS PP1V8_S3 109 1 715K 4.53K 2 1% 1/20W MF 201 20K R5741 1% 1/20W MF 201 V+ PP3V3_S4SW_SNS 1 PLACE_NEAR=U5000.C3:5MM 20% 2 6.3V X5R 0201 NOSTUFF 9 53 52 51 50 110 55 1 V- 0.1% 1/20W MF 2 0201 LPDDR 1.8V Current Sense (IM1C) Gain: 200x, EDP: 0.555 A Rsense: 0.025 (R5720) or Rsense SHORT Vsense: 13.875 mV, Range: 0.6 A SMC ADC: 23 (OPTIONAL) 3 R5749 0.22UF PLACE_NEAR=U5730.10:5MM C R5744 715K 2.94K 2 1 4.42K 2 PLACE_NEAR=R7420.3:5MM NO_XNET_CONNECTION=1 EADC2_KBBLT_ISENSE 2 5% 1/20W MF 2 201 GND 1 LOADISNS 1% 1/20W MF 201 R5735 CPUGT_ISNS2_N IN R5739 20K NC NC 68 PLACE_NEAR=U5710.1:5MM ISNS_KBBLT_IOUT OUT 10 REF 8 LOADISNS ISNS_KBBLT_N LOADISNS 2 CERM-X5R 0201 UQFN SC70-5 4 CPUGT_ISUM_IOUT LOADISNS R5757 6.3V CRITICAL 1 R5743 0.1% 1/20W MF 0201 LOADISNS 10% INA210A ISL28133 1 V+ 1% 1/20W MF 201 4.42K 2 PLACE_NEAR=R7410.3:5MM NO_XNET_CONNECTION=1 0.1UF U5730 PLACE_NEAR=U5730.2:3:10MM 3 2 ISNS_KBBLT_P OMIT IN 1 C5730 6 PP5V_S0 CPUGT_ISNS1_N BYPASS=U5730.6::5MM V+ CPUGT_ISNS_P 10% 2 6.3V X7R 0201 U5740 LOADISNS LOADISNS 1 2.94K 2 C5740 0.1UF CRITICAL 46 47 48 50 51 53 55 68 55 53 52 51 50 1 0.1% 1/20W MF 0201 LOADISNS LOADISNS PP3V3_S0 R5742 R5748 KB backlite Current Sense (IKBC) PP3V3_S4SW_SNS 110 PLACE_NEAR=U5000.C1:5MM PLACE_NEAR=U5750.6:5MM 110 1 BYPASS=U5740.5::5MM LOADISNS 4.42K 2 PLACE_NEAR=R7420.4:5MM NO_XNET_CONNECTION=1 20% 2 6.3V X5R 0201 NOSTUFF Gain: 200x, EDP: 300m A Rsense: 0.035 (R5730) Vsense: 10.5 mV, Range: 0.36 A EADC2: CH3 2 LOADISNS R5746 48 0.22UF 5% 1/20W MF 2 201 2 0.1% 1/20W MF 0201 PLACE_NEAR=R7410.4:5MM NO_XNET_CONNECTION=1 4.53K 2 1 ISNS_SSDNAND_IOUT 6 REF 1 200x GND MAKE_BASE=TRUE PLACE_NEAR=U5750.4:3:10MM PP3V3_SSD_ISNS_R OUT CRITICAL 4 IN+ ISNS_SSDNAND_P 3 3 Gain: 202.93x, EDP: 55 A Rsense: 2x of 0.00075 (R7410, R7420), Rsum: 0.000375 Vsense: 20.625 mV, Range:57.62 A SMC ADC: 5 R5745 4.42K 2 1 CPUGT_ISNS1_P R5789 INA210 5 IN- LOADISNS 6.3V U5750 PLACE_NEAR=U5750.5:5:10MM 4 ISNS_SSDNAND_N 0.005 84 C5750 1 OMIT D 4 CPU GT Current Sense (ICTC) V+ 86 84 78 5 5 SSDLIM 7 2 8 GND_SMC_AVSS 46 47 48 50 51 53 55 PART NUMBER QTY 117S0008 DESCRIPTION 4 REFERENCE DES CRITICAL BOM OPTION LOADRC:NO C5739,C5749,C5779,C5789 RES,MTL FLIM,100K,1/16W,0201,SMD,LF B B EADC1 53 51 PP5V_S4 1 BYPASS=U5700.12::5MM 10 2 5% 1/20W MF 201 BYPASS=U5700.12::5MM 1 C5701 1 0.1UF R5710 C5703 1 C5702 1 0.1UF 4.7UF 10% 2 10V X5R-CERM 0201 LOADISNS EADC2 VOLTAGE=5V LOADISNS PP5V_EADC1_AVDD 20% 10V 2 X5R-CERM 0402 2 10V X5R-CERM 0402 LOADISNS LOADISNS 20% 53 51 PP5V_S4 BYPASS=U5710.12::=5MM 5% 1/20W MF 201 BYPASS=U5710.12::5MM LOADISNS 1 C5711 1 0.1UF 2 6.3V CERM-X5R 0201 C5712 4.7UF 20% 2 10V X5R-CERM 0402 LOADISNS AVDD 51 A 50 52 52 52 51 50 GND_EADC1_COM CRITICAL 2 14 15 52 52 LOADISNS 52 SDA SCL SMBUS_SMC_2_S4_SDA49 SMBUS_SMC_2_S4_SCL49 17 16 VREF REFCOMP 7 8 PP2V5_ADC1_VREF ADC1_REFCOMP 50 1 C5700 2.2UF PAD 1 C5705 0.1UF 2 6.3V CERM-X5R 0201 LOADISNS BYPASS=U5700.8::5MM (Write: 0x10 7 50 53 52 51 50 2 6.3V X5R-CERM 0201 THRM 10% 1 WWW.AliSaler.Com 52 20% PLACE_NEAR=U5700.6:1MM PLACE_NEAR=U5700.25:1MM 8 53 51 GND XW5700 SM AD0 AD1 QFN 6 COM VOLTAGE=0V 20% 2 10V X5R-CERM 0402 LOADISNS LOADISNS 1 C5706 10UF LOADISNS BYPASS=U5700.7::5MM 20% 2 10V X5R-CERM 0402-10 EADC2_LCDPANEL_ISENSE EADC2_PP3V3_TPAD_ISENSE EADC2_CAMERA_ISENSE EADC2_KBBLT_ISENSE EADC2_T151_ISENSE EADC2_BT_ISENSE EADC2_OTHER3V3_HI_ISENSE SMC_TPAD_ISENSE GND_EADC2_COM BYPASS=U5700.8::5MM CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 PLACE_NEAR=U5710.6:1MM PLACE_NEAR=U5710.25:1MM 1 2 AD0 AD1 14 15 SDA SCL 17 16 VREF 7 1 100K 2 SMBUS_SMC_2_S4_SDA SMBUS_SMC_2_S4_SCL 48 OUT REFCOMP THRM 1 C5715 0.1UF 10% 1 C5710 2.2UF C5716 10UF 2 10V X5R-CERM 0402-10 LOADISNS LOADISNS 4 PLACE_NEAR=U5000.H3:5MM 46 47 48 50 51 53 55 Power Sensors: Extended 2 DRAWING NUMBER Apple Inc. LOADISNS (Write: 0x14 051-00647 REVISION R BYPASS=U5710.7::5MM BYPASS=U5710.10::5MM BYPASS=U5710.10::5MM 20% 2 6.3V X5R 0201 SYNC_DATE=04/14/2016 20% 2 6.3V X5R-CERM 0201 20% 2 6.3V CERM-X5R 0201 0.22UF SYNC_MASTER=X363_ZIFENGSHEN 1 ADC2_REFCOMP C5778 49 PP2V5_ADC2_VREF 8 1 49 PAGE TITLE PAD 4.53K 2 SMC_CPUSA_VSENSE GND_SMC_AVSS NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE Read: 0x15) BOM_COST_GROUP=SENSORS 5 CPUSAVSENSE_IN 51 53 110 BOMOPTION=NOSTUFF 5% 1/20W MF 201 LOADISNS PP5V_S4 Read: 0x11) 6 R5778 1 1% 1/20W MF 201 PLACE_NEAR=U5000.H3:5MM R5712 CRITICAL GND 1 XW5778 SM EADC2_AD0 QFN VOLTAGE=0V XW5710 SM (PRODUCTION) 109 8 PPVCCSA_S0_CPU PLACE_NEAR=R7370.2:5 MM LTC2309 6 COM 2 LOADISNS 22 23 24 1 2 3 4 5 SMC ADC: 19 BYPASS=U5710.21::5MM DVDD 9 10 11 18 19 20 51 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 25 52 22 23 24 1 2 3 4 5 9 10 11 18 19 20 51 EADC1_LCDBKLT_ISENSE EADC1_P1V8SUS_ISENSE EADC1_TBT_T_ISENSE EADC1_PP3V3S5_T139_ISENSE EADC1_PP3V3S4_WLAN_ISENSE EADC1_OTHER5V_HI_ISENSE EADC1_PP5V_T139_ISENSE EADC1_TBT_X_ISENSE CPU SA Voltage Sense (VCSC) 4.7UF 10% 2 10V X5R-CERM 0201 U5710 LTC2309 C5714 1 0.1UF U5700 50 BYPASS=U5710.21::5MM C5713 1 BYPASS=U5710.12::5MM DVDD VOLTAGE=5V PP5V_EADC2_AVDD 2 10% BYPASS=U5700.21::5MM 21 10 1 BYPASS=U5700.21::5MM BYPASS=U5700.12::5MM 12 13 110 4.7UF 10% 2 10V X5R-CERM 0201 LOADISNS AVDD C5704 12 13 110 VOLTAGE=5V 25 R5700 21 VOLTAGE=5V LOADISNS 1 57 OF 145 53 OF 121 SIZE D A 7 6 5 3 R5850 Thermal Sensor A: Thunderbolt Die, Airflow Left 110 PP3V3_S0_LEFT 47 1 27 TBTTHMSNS_X_D1_P BI MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 1 MAKE_BASE=TRUE PLACE_NEAR=U5850.2:5MM C5851 1 TBTTHMSNS_X_D1_N 2 D+ PLACE_NEAR=U5850.3:5MM TBTTHMSNS_X_D1_N CRITICAL 1 9 SCL SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA BI 49 BI 49 1% 1/20W MF 2 201 TBTTHRM_ALRT:PU D 3 D- SDA 5 A0 ALERT*/THERM2* 7 TBTTHMSNS_X_ALERT_L OUT 48 10 A1 THERM* 4 TBTTHMSNS_X_THM_L OUT 48 MAKE_BASE=TRUE Note: Use GND pin AC22 on U2800 for N leg. QFN R5852 100K 1% 1/20W MF 2 201 TBTTHRM_THRM:PU TBTTHRM_SNS 1 R5851 100K TBTTHRM_SNS TMP461 TBTTHRM_SNS BI 10% 2 6.3V CERM-X5R 0201 U5850 10% 10V X7R-CERM 2 0201 28 U5850 I2C Address:TMP461 A1->GND A0->GND 0X90/0X91 C5850 V+ 2200PF Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22. 1 0.1UF TBTTHMSNS_X_D1_P Thermal Diode: TBT Die (TTLD) 2 BYPASS=U5850.1::5MM PP3V3_S0_TBTTHMSNS_X_R 2 5% 1/20W MF 201 I2C Write: 0xD8, I2C Read: 0xD9 D 4 1 8 8 6 GND Thermal Diode: Airflow Left Proximity (TaLC) Placement Note: Place U5850 on the TOP side, on the left portion of the board, 1" to the right of USB connector. Thermal Sensor C: Thunderbolt Die, Air Flow Right R5800 I2C Write: 0x98, I2C Read: 0x99 110 PP3V3_S0 47 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 5% 1/20W MF 201 Thermal Diode: TBT Die (TTRD) BI TBTTHMSNS_T_D1_P 1 The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22. PLACE_NEAR=U5800.2:5MM C5801 1 TBTTHMSNS_T_D1_N TBTTHMSNS_T_D1_N 2 D+ PLACE_NEAR=U5800.3:5MM MAKE_BASE=TRUE NC Note: Use GND pin AC22 on UB000 for N leg. 1% 1/20W MF 2 201 TBTTHRM_SNS TBTTHRM_THRM:PU QFN TBTTHRM_SNS 9 SCL 3 D- SDA 5 A0 ALERT*/THERM2* 7 10 A1 THERM* 4 8 R5801 100K TMP461 TBTTHRM_SNS BI 1 U5800 10% 10V X7R-CERM 2 0201 102 CRITICAL V+ 2200PF C C5800 10% 2 6.3V CERM-X5R 0201 TBTTHMSNS_T_D1_P MAKE_BASE=TRUE U5800 I2C Address:TMP461 A1->Floating A0->GND 0X96/0X97 0.1UF 1 Placement Note: 101 BYPASS=U5850.1::5MM PP3V3_S0_TBTTHMSNS_T_R 2 SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA BI 49 54 BI 49 54 1 R5802 100K 1% 1/20W MF 2 201 TBTTHRM_ALRT:PU C TBTTHMSNS_T_ALERT_L OUT TBTTHMSNS_T_THM_L OUT 48 48 6 GND Thermal Diode: Airflow Right Proximity (TaRC) Placement Note: Place U5800 on the TOP side, on the left portion of the board, 1" to the right of USB connector. 54 49 BI 54 49 BI SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL X100 PROXIMITY (TW0P) 110 Thermal Sensor B & CPU High Peak Detection: CPU Proximity, Memory Proximity, Fin Stack Left, Fin Stack Right PP3V3_S0_LEFT AP_TEMP AP_TEMP 1 PLACE_SIDE=BOTTOM I2C Write: 0x98, I2C Read: 0x99 0.1UF 5 V+ PLACE_NEAR=U3730::10MM C5820 1 10K 10% 6.3V 2 CERM-X5R 0201 U5820 5% 1/20W MF 2 201 HPA00330AI B R5870 2 5% 1/20W MF 201 CPUTHMSNS_D1_P 3 PLACE_NEAR=U5870.6:5MM Q5871 C5871 1 10% 10V X7R-CERM 2 0201 CRITICAL 2 PLACE_NEAR=U5870.7:5MM Q5873 1 2200PF BC846BLP DFN1006H4-3 10% 10V X7R-CERM 2 0201 CRITICAL 2 PLACE_NEAR=U5870.9:5MM CPUTHMSNS_D2_N 6 7 C5873 CRITICAL SMBUS_SMC_3_SCL DXP2 10 11 DXP3 DXN3 1 2 VIN+ VIN- ALERT X29THMSNS_A0 3 GND 2 1 B NC WRITE ADDRESS: 0X92 READ ADDRESS: 0X93 R5872 100K 15 CPUTHMSNS_FILTER 5 CPUTHMSNS_ADDR_SEL 13 CPUTHMSNS_ALERT_L SDA SCL 3 4 SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SCL GPIO 12 CPUTHMSNS_THM_L FILTER C A0 ALERT DXN2 14 SCL 4 1% 1/20W MF 2 201 QFN 8 9 CRITICAL ADD0 PLACE U5820 ON BOTTOM NEAR X100 OUT 1 THRM Placement note: R5873 10K PAD 5% 1/20W MF 2 201 1 R5871 100K 1% 1/20W MF 2 201 1 48 BI 49 BI 49 OUT 48 C5874 0.47UF 10% 2 6.3V CERM-X5R 0201 Q5872 2 1 2200PF 1 10% 10V X7R-CERM 2 0201 BC846BLP DFN1006H4-3 BI 1 SOT563 SDA PLACE_NEAR=U5870.10:5MM 3 A 6 AP_TEMP 10% 2 6.3V X7R 0201 CRITICAL DXP1 DXN1 GND CPUTHMSNS_D3_P SMBUS_SMC_3_SDA 0.1UF TMP513AISAR Placement Note: Place U5870 at corner near right Fan, on the TOP side. BI C5870 U5870 Thermal Diode: Fin Stack Right (Th1H) 1 49 V+ CPUTHMSNS_D1_N PLACE_NEAR=U5870.8:5MM C5872 1 Thermal Diode: Fin Stack Left (Th2H) CPUTHMSNS_D2_P 3 BYPASS=U5870.1::5MM MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V Placement Note: Place Q5871, Airflow thermal indicator, above the X100, on the TOP side. 1 2200PF BC846BLP DFN1006H4-3 PP3V3_S0_CPUTHMSNS_R 17 PP3V3_S0 47 16 110 1 49 R5820 PLACE_NEAR=U5870.11:5MM SYNC_MASTER=X363_ZIFENGSHEN CPUTHMSNS_D3_N 52 IN 52 IN ISNS_CPUHIGAIN_P ISNS_CPUHIGAIN_N Thermal Diode: Memory Proximity (TM0P) PAGE TITLE Thermal Sensors Thermal Sensor: CPU Proximity (TC0P) DRAWING NUMBER Placement Note: Place Q5873 under the CPU, on the BOTTOM side. Placement Note: Place Q5872 between two rows of Memory devices, between channel A and B, on the BOTTOM side. SYNC_DATE=04/14/2016 Apple Inc. 051-00647 REVISION R I2C ADDRESS (U5870): 0XB8/0XB9 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=SENSORS WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 58 OF 145 54 OF 121 SIZE D A 8 7 6 5 4 3 2 1 SENSORS: EXTENDER 3 CPU Core Voltage Sense (VCAC) CPU Core IMON Current Sense (ICAM) SMC ADC: 20 (PRODUCTION) 109 8 6 PPVCC_S0_CPU XW5900 SM 1 CPUVSENSE_IN 2 Gain: 1 A / 17.123 mV, Range: 67 A. SMC ADC: 22 R5900 4.53K 2 1 SMC_CPU_VSENSE 1% 1/20W MF 201 PLACE_NEAR=U5000.C4:5MM PLACE_NEAR=R7210.2:5 MM D R5901 1 48 OUT IMON_A_CPUCORE 65 0 1 LOADISNS SMC_CPU_IMON_ISENSE 2 5% 1/20W MF 0201 PLACE_NEAR=U5000.B5:5MM C5900 0.22UF 1 2 20% 2 6.3V X5R 0201 PLACE_NEAR=U5000.C4:5MM GND_SMC_AVSS CPU GT Voltage Sense (VCTC) SMC ADC: 21 (PRODUCTION) PPVCCGT_S0_CPU 109 8 XW5910 SM 1 With R7154 (Ri) set to 365 Ohm, R7210 (Rsen) set to 0.75 mOhm, R7194 set to 100 kOhm, Num Phases (N) is 3, and Io (ICCmax) is 67A, then 1A of Io gives 17.123mV at the Vimon. 0.22UF 20% 6.3V NOSTUFF X5R 0201 PLACE_NEAR=U5000.B5:5MM 110 XW5980 SM (PRODUCTION) PPVCORE_S0_GPU 92 90 1 R5980 GPUCOREVSENSE_IN 2 1 4.53K 2 1% 1/20W MF 201 PLACE_NEAR=RA651.2:5 MM CPUGTVSENSE_IN 1 1 SMC_CPUGT_VSENSE 1% 1/20W MF 201 PLACE_NEAR=R7410.2:5 MM 1 48 OUT IMON_B_CPUGT 65 0 C5910 1 2 20% 2 6.3V X5R 0201 PLACE_NEAR=U5000.C5:5MM GND_SMC_AVSS 20% 0201 PLACE_NEAR=U5000.A3:5MM GND_SMC_AVSS OUT GPU VDDCI Voltage Sense (VG2C) SMC ADC: 11 48 53 C5911 0.22UF 20% 6.3V NOSTUFF X5R 0201 PLACE_NEAR=U5000.A5:5MM GND_SMC_AVSS 46 47 48 50 51 53 55 C5981 2 6.3V X5R SMC_CPUGT_IMON_ISENSE 2 5% 1/20W MF 0201 PLACE_NEAR=U5000.A5:5MM 0.22UF PLACE_NEAR=U5000.C5:5.2MM 1 D 48 OUT 0.22UF Gain: 1 A / 21.701 mV, Range: 64 A. SMC ADC: 23 R5911 LOADISNS 4.53K 2 SMC_GPU_CORE_VSENSE PLACE_NEAR=U5000.A3:5MM 46 47 48 50 51 53 55 CPU GT IMON Current Sense (ICTM) R5910 2 GPU CORE Voltage Sense (VG0C) 48 51 SMC ADC: 8 C5901 GND_SMC_AVSS 46 47 48 50 51 53 55 OUT 46 47 48 50 XW5982 SM (PRODUCTION) 92 PPVDDCI_S0_GPU With R7150 (Ri) set to 432 Ohm, R7410 (Rsen) set to 0.75 mOhm, R7160 set to 100 kOhm, Num Phases (N) is 2, and Io (ICCmax) is 55A, then 1A of Io gives 21.701mV at the Vimon. 51 53 55 1 2 110 GPUVDDCIVSENSE_IN 46 47 48 50 51 53 55 R5982 1 4.53K 2 1% 1/20W MF 201 SMC_GPU_VDDCI_VSENSE 1 48 OUT C5983 0.22UF 20% 2 6.3V X5R 0201 LOADISNS LOADISNS R5921 97 IN GFXIMVP_ISNS2_P 1 R5926 4.42K 2 GFXIMVP_ISNS_R_P 1 0.1% 1/20W MF 0201 LOADISNS LOADISNS CRITICAL 3.65K 2 GFXIMVP_ISNS_P ISL28133 1% 1/20W MF 201 1 R5928 3 715K 1 3.65K 2 1 R5923 97 IN GFXIMVP_ISNS1_N 1 4.42K 2 715K 94 94 SMC_GPU_CORE_ISENSE OUT IN GFXIMVP_ISNS2_N 1 1 5 IN- IN GPUFB_CS_P 4 IN+ GND_SMC_AVSS Gain: 200x, EDP: 4.8 A Rsense: 0.005 (R5970) Vsense: 10 mV, Range: 3 A SMC ADC: 15 46 47 48 50 51 53 55 LOADISNS NO_XNET_CONNECTION=1 110 110 PP1V5R1V35_S0_GPU_IC PLACE_NEAR=U5970.5:5:10MM C5940 3 INA214 SC70 CRITICAL 100x LOADISNS 6 OUT 4.53K 2 1 ISNS_GPUVDDCI_IOUT 1 REF 1 SMC_GPU_VDDCI_ISENSE 1% 1/20W MF 201 R5940 20K 1 2 110 PLACE_NEAR=U5000.D3:5MM LOADRC:YES GND_SMC_AVSS C5941 SC70 CRITICAL LOADISNS 200x 3 OUT 6 ISNS_GPUFBIC_IOUT 1 REF 1 1 4.53K 2 1% 1/20W MF 201 R5971 20K GND R5990 1 46 47 48 50 51 53 55 55 53 52 51 50 PP3V3_S4SW_SNS 3 V+ 0.005 3 PLACE_NEAR=U5950.5:5:10MM ISNS_GPU1V8_N ISNS_GPU1V8_P PLACE_NEAR=U5950.4:3:10MM PP1V8_GPU 5 IN4 IN+ INA210 SC70 CRITICAL LOADISNS 200x GND 6 REF 1 ISNS_GPU1V8_IOUT 10% 2 6.3V CERM-X5R 0201 V+ U5990 ISNS_GPU_HS_N 5 IN- ISNS_GPU_HS_P 4 IN+ INA210 SC70 CRITICAL 3 200x OUT 6 1 4.53K 2 1% 1/20W MF 201 GND_SMC_AVSS R5951 20K 5% 1/20W MF 2 201 NOSTUFF PLACE_NEAR=U5950.6:5MM 46 47 48 50 51 53 55 REF 1 1 1 4.53K 2 1% 1/20W MF 201 R5991 20K SMC_GPU_HS_ISENSE 1 OUT C5992 0.22UF PLACE_NEAR=U5000.H4:5MM PLACE_NEAR=U5990.6:5MM GND_SMC_AVSS 46 47 48 50 51 53 55 SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=05/19/2016 SMC_GPU_1V8_ISENSE Sensor Extended 3 48 PART NUMBER C5951 117S0008 0.22UF 20% 2 6.3V X5R 0201 QTY 5 DESCRIPTION RES,MTL FLIM,100K,1/16W,0201,SMD,LF REFERENCE DES CRITICAL DRAWING NUMBER BOM OPTION Apple Inc. LOADRC:NO C5921,C5941,C5951,C5961,C5971 051-00647 REVISION R PLACE_NEAR=U5000.D4:5MM LOADRC:YES GND_SMC_AVSS 46 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 47 48 50 51 53 55 BOM_COST_GROUP=SENSORS WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 48 20% 2 6.3V X5R 0201 5% 1/20W MF 2 201 GND PPBUS_G3H R5992 PAGE TITLE 1 B PLACE_NEAR=U5000.A1:5MM LOADRC:YES PLACE_NEAR=U5000.H4:5MM ISNS_GPU_HS_IOUT CRITICAL 1 0.22UF 0.1UF R5952 OUT C5971 C5990 LOADISNS PLACE_NEAR=U5000.D4:5MM U5950 1 48 BYPASS=U5990.3::5MM C5950 10% 2 6.3V CERM-X5R 0201 SMC_GPU_FBIC_ISENSE 20% 2 6.3V X5R 0201 5% 1/20W MF 2 201 1 0.002 LOADISNS BYPASS=U5950.3::5MM 55 53 52 51 50 110 0612 2 4 CYN 1W 1% PLACE_NEAR=U5000.A4:5MM LOADRC:YES GND_SMC_AVSS 46 47 48 50 51 53 55 R5972 0.1UF 0306-SHORT 2 4 MF 1/3W 1% 110 PP1V5R1V35_S0_GPU_MEM 20% 2 6.3V X5R 0201 1 OMIT R5950 1 48 109 2 116 OUT 0.22UF 5% 1/20W MF 2 201 GPU 1V8 Current Sense (IG3C) PP3V3_S4SW_SNS A ISNS_GPUFBIC_P 4 IN+ INA210 PLACE_NEAR=U5970.4:3:10MM Gain: 200x, EDP: 4 A Rsense: 0.002 (R5990) or Rsense SHORT Vsense: 8 mV, Range: 7.5 A SMC ADC: 16 (PRODUCTION) PPBUS_HS_GPU 109 R5941 NOSTUFF PLACE_NEAR=U5940.6:5MM Gain: 200x, EDP: 2.3 A Rsense: 0.005 (R5950) Vsense: 7.5 mV, Range: 3 A SMC ADC: 12 PP1V8_S0_GPU 20% 2 6.3V X5R 0201 GPU HIGH SIDE Current Sense (IG0R) LOADISNS PLACE_NEAR=U5000.A4:5MM 10% 2 6.3V X7R 0201 GND 110 0.22UF LOADISNS PLACE_NEAR=U5000.A1:5MM 10% 2 6.3V CERM-X5R 0201 3 0.1UF U5940 4 IN+ 5 IN- C5961 C5970 0.1UF U5970 ISNS_GPUFBIC_N OUT LOADISNS BYPASS=U5970.3::5MM 55 53 52 51 50 2 1 VDDCIS0_CS_P 1 LOADISNS BYPASS=U5940.3::5MM PP3V3_S4SW_SNS V+ IN SMC_GPU_FB_ISENSE NOSTUFF PLACE_NEAR=U5970.6:5MM GPU VDDCI Current Sense (IG2C) 94 5% 1/20W MF 2 201 2 110 5 IN- 20K V+ 0306-SHORT 2 4 MF 1/3W 1% VDDCIS0_CS_N 4.53K 2 1% 1/20W MF 201 R5960 1 OMIT B IN 1 REF 1 GPU FB IC Current SensePP3V3_S4SW_SNS (IG4C) R5970 1 94 LOADISNS 1 C R5961 NOSTUFF PLACE_NEAR=U5960.6:5MM GFXIMVP_ISNS_R_N 55 53 52 51 50 110 100x ISNS_GPUFB_IOUT 20% 2 6.3V X5R 0201 0.005 Gain: 100x, EDP: 9.7 A Rsense: 0.003 (RA368) Vsense: 24 mV, Range: 10 A SMC ADC: 10 CRITICAL 6 OUT 0.22UF 0.1% 1/20W MF 0201 LOADISNS SC70 C5921 LOADISNS 4.42K 2 GPUFB_CS_N LOADISNS PLACE_NEAR=U5000.D3:5MM GND R5924 97 IN INA214 10% 2 6.3V X7R 0201 48 LOADRC:YES NOSTUFF PLACE_NEAR=U5920.4:5MM PLACE_NEAR=U5000.A2:5MM 2 0.1% 1/20W MF 0201 1% 1/20W MF 201 0.1% 1/20W MF 0201 LOADISNS 1 R5930 5% 1/20W MF 2 201 R5929 GFXIMVP_ISNS_N 1% 1/20W MF 201 20K LOADISNS R5927 4.53K 2 1 V- 0.1% 1/20W MF 2 0201 NO_XNET_CONNECTION=1 R5931 SC70-5 4 GFXIMVP_ISUM_IOUT V+ U5960 LOADISNS PLACE_NEAR=U5000.A2:5MM C5960 0.1UF V+ C5920 10% 2 6.3V CERM-X5R 0201 LOADISNS BYPASS=U5960.3::5MM 1 0.1UF U5920 1 PP3V3_S4SW_SNS 3 0.1% 1/20W MF 0201 1 53 52 51 50 110 55 2 IN PP3V3_S4SW_SNS 55 53 52 51 50 5 97 110 Current Sense (IG1C) Gain: 100x, EDP: 10.7 A Rsense: 0.002 (RA300) Vsense: 16 mV, Range: 15 A SMC ADC: 13 BYPASS=U5920.5::5MM LOADISNS 2 C Gain: 122.01x, EDP: 64.2 A Rsense: 2x of 0.00075 (RA651, RA641), Rsum: 0.000375 Vsense: 22.875 mV, Range: 65.57 A SMC ADC: 7 R5920 4.42K 2 1 GFXIMVP_ISNS1_P 46 47 48 50 51 53 55 48 GPU CORE Current Sense (IG0C) 3 GPU SENSORS GPU FB GND_SMC_AVSS 1 59 OF 145 55 OF 121 SIZE D A 8 7 6 FAN CONNECTOR 5 4 3 2 1 KEEP THE 5 PIN CONNECTOR FROM D1 PP3V3_S0 PP3V3_S0 56 110 56 110 D D PP5V_S0 R6000 1 R6050 47K R6005 2 46 5% 1/20W MF 201 R6001 46 IN 115 5% 1/20W MF 201 G 1 DMN32D2LFB4 DFN1006H4-3 SYM_VER_3 D FAN_LT_PWM 3 43 114 115 46 SMC_FAN_1_CTL IN CRITICAL J6000 J6001 FF14A-5C-R11DL-B-3H F-RT-SM F-RT-SM FAN_RT_TACH 43 114 NC 115 1 NC NC Q6050 DMN32D2LFB4 DFN1006H4-3 SYM_VER_3 2 117 BOMOPTION=DBG_FAN FF14A-5C-R11DL-B-3H NC 100K 43 56 110 CRITICAL 2 5% 1/20W MF 201 Q6000 2 47K 1 R6051 2 S SMC_FAN_0_CTL 43 114 OUT 1 100K 5% 1/20W MF 201 FAN_LT_TACH SMC_FAN_1_TACH NC D 47K 3 1 G 1 OUT SMC_FAN_0_TACH 2 S 46 BOMOPTION=DBG_FAN 5% 1/20W MF 201 2 R6055 PP5V_S0 117 1 47K 5% 1/20W MF 201 2 43 56 110 FAN_RT_PWM 43 114 6 1 2 3 4 5 NC 5V DC NC GND NC NC 7 NC 518S0769 115 6 1 2 3 4 5 5V DC GND 7 518S0769 C C CARBON_ISOL R6013 110 PP3V3_S0_LEFT 56 1 5% MF 0 VOLTAGE=3.3V PP3V3_S0_CARBON_R 2 1/20W 0201 C6002 1 1 10UF 0.1UF 20% 6.3V CERM-X5R 2 0402-1 CARBON 10% 2 16V X5R-CERM PP3V3_S0_LEFT 2 5% 1/20W B 100K 1 CARBON_CS MF 201 5 CS LGA CARBON TP6001 A A TP-P5 1 1 TP_CARBON_INT1 TP_CARBON_INT2 9 10 11 15 DEN 8 CARBON_SCL_R CARBON_SDA_R CARBON_SA0 CARBON_DEN 1 BI 49 SMBUS_SMC_3_SDA 2 MF 0201 BI 49 2 5% 1/20W R6012 0 5% MF R6011 100K B 1 MF 201 2 1/20W 0201 CARBON C6001 0.01UF 10% GND 2 25V X5R-CERM 0201 CARBON 13 12 SMBUS_SMC_3_SCL CARBON 1 CAP 14 CARBON_CAP RES RES RES RES 0 1 5% 1/20W TP-P5 TP6002 MF 0201 R6020CARBON_ISOL SCL/SPC 2 SDA/SDI/SDO 3 SDO/SA0 4 7 INT1 6 INT2 2 5% 1/20W VDD_IO AP6DS2AB R6010 0 1 U6000 CARBON 56 R6021CARBON_ISOL 1 16 0201 CARBON VDD 110 C6000 A SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016 PAGE TITLE Fans DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=FAN WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 60 OF 145 56 OF 121 SIZE D A 8 7 6 5 4 3 2 1 SPI ROM Quad-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC. 110 SPI+SWD SAM Connector PP3V3_SUS SAMCONN CRITICAL BYPASS=U6100::3mm 1 C6101 0.1UF 8 U6101 114 57 15 SPI_MLB_CS_L SPIROM_USE_MLB 57 74LVC1G99 SOT833 1 SPI_MLB_CLK 6 CLK OE* 1 57 57 WSON DF40PC-12DP-0.4V-51 M-ST-SM DI(IO0) 5 SPI_MLB_IO0_MOSI 57 114 1 CS* 3 WP*(IO2) 7 HOLD*(IO3) SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L 114 GND IO1 SPI_MLB_IO1_MISO 57 114 IO3 GND 57 114 57 114 57 76 64 48 29 OUT 13 2 1 4 3 6 5 SPI_ALT_IO0_MOSI SPI_ALT_IO1_MISO SPI_ALT_IO2_WP_L SPI_ALT_IO3_HOLD_L 8 7 10 9 SMC_RESET_L 12 11 16 15 THRM_PAD 4 4 DO(IO1) 2 IO2 57 14 PP3V3_G3H 109 OMIT_TABLE PLACE_NEAR=U6100.1:12MM CRITICAL W25Q64FVZPIG 64MBIT IO0 D J6100 20% 2 10V X5R-CERM 0201-1 U6100 10% 16V X5R-CERM 2 0201 SPI_MLBROM_CS_L Y 7 1.0UF CRITICAL VCC 0.1UF C6102 SPI_ALT_CLK SPI_ALT_CS_L SPIROM_USE_MLB SMC_TMS (SWDIO) (SWCLK) SMC_TCK 57 114 57 114 BI 15 57 114 BI 46 47 114 OUT 46 47 114 9 57 2A 3B 5C 6D C6100 10% 2 16V X5R-CERM 0201 VCC 8 D 1 BYPASS=U6101::3mm BYPASS=U6100::3mm NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and Dual-IO modes. Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3. C C SPI Bus Series Termination (Modified per PDG) SPI_ALT_IO3_HOLD_L SPI_ALT_IO2_WP_L SPI_ALT_IO1_MISO SPI_ALT_IO0_MOSI SPI_ALT_CLK SPI_ALT_CS_L PLACE_NEAR=J6100.10:7MM PLACE_NEAR=J6100.8:8MM PLACE_NEAR=J6100.6:7MM PLACE_NEAR=J6100.4:5MM PLACE_NEAR=J6100.3:7MM PLACE_NEAR=J6100.5:6MM SAMCONN 1 R6133 0 5% 1/20W MF 2 0201 SAMCONN 1 R6132 0 5% 1/20W MF 2 0201 SAMCONN 1 R6128 0 5% 1/20W MF 2 0201 SAMCONN 1 R6127 0 5% 1/20W MF 2 0201 1 R6126 0 13 IN 18 13 CPU Master BI SPI_CS0_L 1 SPI_CLK BI 18 13 13 BI SPI_IO<2> PLACE_NEAR=U1100.AM24:50MM BI SPI_IO<3> 1 5% 1/20W MF 201 PLACE_NEAR=U1100.AK24:50MM 2 1 22 2 5% 1/20W MF 201 22 2 R6131 SPI_IO3_R 1 5% 1/20W MF 201 SPI_MLB_CS_L 57 SPI_MLB_CLK 57 SPI_MLB_IO0_MOSI 57 22 5% 1/20W MF 201 PLACE_NEAR=U6100.5:12MM B SPI ROM Slave SPI_MLB_IO1_MISO 57 SPI_MLB_IO2_WP_L 57 SPI_MLB_IO3_HOLD_L 57 R6130 1 R6119 1 2 PLACE_NEAR=U6100.2:12MM SPI_IO2_R 2 22 5% 1/20W MF 201 R6123 1 PLACE_NEAR=U6100.1:12MM R6122 SPI_MOSI SPI_MISO_R 2 PLACE_NEAR=U6100.6:12MM 5% 1/20W MF 201 R6118 22 22 1 22 5% 1/20W MF 201 R6121 R6113 13 57 114 5% 1/20W MF 2 0201 R6112 B 57 114 0 5% 1/20W MF 2 0201 R6111 13 57 114 R6120 22 IN Sam Card ROM Slave 57 114 R6125 R6110 1 2 SPI_CS0_R_L PLACE_NEAR=U1100.AJ24:50MM 5% 1/20W MF 201 22 2 1 SPI_CLK_R PLACE_NEAR=U1100.AJ26:50MM 5% 1/20W MF 201 22 2 1 SPI_MOSI_R PLACE_NEAR=U1100.AM23:50MM 5% (SPI_IO<0>) 1/20W MF 201 22 2 1 SPI_MISO PLACE_NEAR=U1100.AH25:50MM 5% 1/20W (SPI_IO<1>) MF 201 57 114 SAMCONN SAMCONN 1 57 114 2 22 5% 1/20W MF 201 2 PLACE_NEAR=U6100.3:12MM PLACE_NEAR=U6100.7:12MM A SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=11/06/2015 SPI Debug Connector DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 61 OF 145 57 OF 121 SIZE D A 8 7 6 5 4 3 R6280 0 1 R6210 PLACE_NEAR=U6200:5MM 8409_ASP2_SCLK 2 5% 1/20W MF 201 D 2 R6281 0 1 1 8409_ASP2_LRCLK PLACE_NEAR=U6200:10MM AUD_ASP2_SCLK 2 5% 1/20W MF 201 PLACE_NEAR=U6200:5MM 2 33 R6211 1 5% 1/20W MF 201 R6282 0 1 1 C6281 27PF 5% 2 25V C0G 0201 PP1V8_S0 C6203 1 0.1UF 0.22UF 10% 10% 2 10V CERM 402 13 PCH AUDIO 13 2 25V X5R 0201 13 C6201 IN 0.1UF OUT HDA_SDIN0 1 33 PLACE_NEAR=U6200:5MM 2 8409_HDA_SDIN0_R 5% 1/20W MF 201 F3 F2 E4 E3 F4 D2 E1 DMIC1_DATA DMIC1_CLK C2 D1 DMIC2_DATA DMIC2_CLK ASP1_MCLK ASP1_SCLK ASP1_LRCK/FSYNC ASP1_SDIN ASP1_SDOUT B6 C5 D6 B5 C6 SPI_SCLK MOSI GPIO0/MISO1 GPIO1/CS1* GPIO2/CS2* E6 B4 E5 D5 F5 GPIO6/SCL D4 GPIO7/SDA D3 DMIC2_DATA 114 59 IN 59 OUT 59 OUT 61 OUT 61 OUT 61 AUDIO JACK CODEC PLACE_NEAR=U6200:10MM AUD_ASP2_SDOUT 5% 2 25V C0G 0201 2 1 1 8409_ASP1_LRCLK 2 8409_ASP1_SDOUT C6285 1 NOSTUFF 1 DMIC2_CLK 1 33 2 5% 1/20W MF 201 8409_DMIC1_CLK_R 2 8409_DMIC2_DATA PLACE_NEAR=U6200:10MM AUD_ASP1B_SCLK 2 R6220 1 C6286 47PF 5% 2 25V C0G 0201 C6287 47PF 5% 2 25V C0G 0201 PLACE_NEAR=U6200:10MM 33 AUD_ASP1B_SDOUT 2 PLACE_NEAR=U6200:10MM R6225 PLACE_NEAR=U6200:10MM 2 1 33 AUD_ASP1A_LRCLK 2 RIGHT SPEAKER AMPS C AUD_ASP1A_SCLK 5% 1/20W MF 201 R6223 8409_ASP2_SCLK_R 8409_ASP2_LRCLK_R AUD_ASP1B_LRCLK R6222 1 33 2 PLACE_NEAR=U6200:10MM PLACE_NEAR=U6200:10MM 2 5% 1/20W MF 201 NOSTUFF 1 33 33 5% 1/20W MF 201 R6221 PLACE_NEAR=U6200:5MM 1 33 5% 1/20W MF 201 PLACE_NEAR=U6200:5MM R6285 0 R6219 NC AUD_ASP1A_SDOUT OUT 60 OUT 60 OUT 60 LEFT SPEAKER AMPS 5% 1/20W MF 201 8409_ASP2_SDOUT_R NC 8409_ASP1_SCLK_R 8409_ASP1_LRCLK_R R6228 PP1V8_S0 NC 8409_ASP1_SDOUT_R 1 NC NC SPKR_ID0 R6224 47K IN 1 1 R6226 1.5K 1 58 60 61 109 33 2 R6227 5% 1/20W MF 2 201 R6229 1 AUD_I2C_1A_SCL OUT 60 33 2 OUT 59 61 PLACE_NEAR=U6200:5MM AUD_I2C_1B_SCL 5% 1/20W MF 201 61 114 8409_I2C_SCL 8409_I2C_SDA R6230 NC 1 NO_STUFF 1 C6288 1 C6289 5% 2 25V C0G 0201 ESD 2 R6231 100PF 5% 2 25V C0G 0201 33 PLACE_NEAR=U6200:5MM AUD_I2C_1A_SDA BI 60 BI 59 61 B 5% 1/20W MF 201 NO_STUFF 100PF PLACE_NEAR=U6200:5MM PLACE_NEAR=U6200:5MM 5% 1/20W MF 201 1.5K 5% 1/20W MF 2 201 5% 1/20W MF 2 201 GNDD R6207 PLACE_NEAR=U6200:5MM 0 GPIO3/MISO2 F6 GPIO4 F1 GPIO5 A4 8409_DMIC1_DATA PLACE_NEAR=U6200:5MM 1 R6208 6 2 PLACE_NEAR=U6200:5MM 5% 1/20W MF 201 2 5% 1/20W MF 201 58 60 61 109 114 5 OUT AUD_ASP2_SDIN 2 5% 1/20W MF 201 A1 PP1V8_S0 1 33 0 GND_PLL DMIC1_CLK 114 4 8 1 R6206 3 AUD_ASP2_LRCLK 47PF 1 ASP2_MCLK ASP2_SCLK ASP2_LRCK/FSYNC ASP2_SDIN ASP2_SDOUT GNDL DMIC1_DATA 1 2 5% 2 25V C0G 0201 D PLACE_NEAR=U6200:10MM C6283 8409_ASP1_SCLK 5% 2 25V C0G 0201 BCLK SYNC SDO SDI RST* A5 R6205 F-RT-SM 114 47PF PLACE_NEAR=U6200:5MM 47PF B1 B3 A2 C1 A3 C3 FF14A-6C-R11DL-B-3H NC 1 5% 1/20W MF 201 WLCSP J6200 B C6282 NOSTUFF 1 CS8409 3-MIC CONNECTOR APN: 518S0818 7 NOSTUFF 1 33 59 5% 1/20W MF 201 U6200 HDA_RST_L IN 0 2 5% 1/20W MF 201 R6284 5% 1/20W MF 201 HDA_SDOUT IN 0 1 10% 2 16V X5R 603 10% 2 25V X5R 0201 HDA_SYNC IN C6200 1UF HDA_BIT_CLK R6203 13 1 1 VL_DM E2 13 C6204 R6283 U6200.A6:A5:5 MM BYPASS=U6200.C4:C3:5 MM VL_SP C4 1 U6200.E2:C3:5 MM VL_HD B2 U6200.B2:A1:5 MM C 1 OUT 8409_VA_PLL VA_PLL A6 61 60 58 2 R6213 8409_ASP2_SDOUT 2 5% 1/20W MF 201 109 33 5% 1/20W MF 201 PLACE_NEAR=U6200:5MM 1 1 33 2 PLACE_NEAR=U6200:5MM AUD_I2C_1B_SDA 5% 1/20W MF 201 ESD 8409_DMIC2_CLK_R 5% 1/20W MF 201 NC PP1V8_S0 R6290 1 R6291 1 5% 1/20W MF 201 2 5% 1/20W MF 201 2 47K 58 60 61 109 47K AUD_CODEC_INT_L IN 59 AUD_CODEC_RESET_L OUT 59 AUD_SPKRAMP_INT_L IN 60 61 OUT 60 61 AUD_SPKRAMP_RESET_L A SYNC_MASTER=X363_AUDIO SYNC_DATE=01/11/2016 PAGE TITLE HDA Bridge DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=AUDIO WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 62 OF 145 58 OF 121 SIZE D A 8 7 6 5 4 3 2 1 AUDIO JACK CODEC I2C ADDRESS AD1 AD0 GND GND 1.8V 1.8V GND 1.8V GND 1.8V ADDRESS 0x48 <-0x49 0x4A 0x4B L6361 FERR-470-OHM 12 AUD_PWR_EN 1 L83_LDO_EN 2 0201 L6360 59 PP3V3_S0 4 0201 PP1V8_S0_LDO_AUD 59 CRITICAL C6301 1 BYPASS=U6360.A1:B2:3 MM 2.2UF 10% 2 10V X5R-CERM 0402 117 R6360 BYPASS=U6360.A2:B2:3 MM 1 C6361 1.0UF 5% 1/20W MF 2 201 20% 2 10V X5R-CERM 0201-1 XW6300 GND_AUDIO_CODEC 59 CRITICAL 100K 20% 2 10V X5R-CERM 0201-1 59 EN 1 NOSTUFF C6360 1.0UF BYPASS=U6300.B1:C2:5 MM PP1V8_S0_LDO_AUD OUT 1 GND EPAD CRITICAL MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 3 D VOLTAGE=1.8V XDFN-COMBO IN 5 110 NCP160AMX180 2 D U6360 FERR-22-OHM-1A-0.055OHM PP3V3_S0_AUD_F 2 1 SHORT-8L-0.25MM-SM 1 2 L6300 GND_AUDIO_CODEC 59 117 FERR-22-OHM-1A-0.055OHM L83_VCP 2 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 0201 L6301 FERR-22-OHM-1A-0.055OHM 59 PP1V8_S0_LDO_AUD 0201 C6303 62 62 C6321 C6322 R6351 2 62 IN AUD_HS_MIC_N CRITICAL 1 27PF 5% 25V 2 C0G 0201 2.2K VL CRITICAL 1% 1/20W MF 201 1 3300PF R6352 2.2K 62 C6351 VD_FILT VA 10% 10V X7R-CERM 2 0201 1 D5 E5 AUD_HP_PORT_CH_GND PLACE_NEAR=U6300:10mm NOSTUFF 1 10% 16V X5R-X7R 470PF 2 C6320 201 BI R6350 100K 5% 1/20W MF 2 201 NOSTUFF 1 10% 16V X5R-X7R 201 HS_MIC_N 62 (SEE RADAR # 6210118) IN AUD_TIP_SENSE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 1 R6310 0 5% 1/20W MF 2 201 HPSENSB HPOUTB F1 E2 E1 G2 F2 D1 HS4 HS_CLAMP2 HSIN+ HS3 HS_CLAMP1 HSIN- E4 L83_HSBIAS_FILT CRITICAL C6309 4.7UF 1 2 20% 6.3V X5R 402 F3 E3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 F6 WLCSP-SKT F5 G5 F4 G4 G3 AUD_RING_SENSE R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS PLACE_NEAR=U6300:10mm NOSTUFF 5% 25V 2 C0G 0201 AUD_HP_PORT_US_GND HS_MIC_P 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 PLACE_NEAR=U6300:10mm 560PF PLACE_NEAR=U6300:10mm 470PF 2 1 GNDCP CS42L83A VL_SEL C4 DIGLDO_PDN* D4 INT* B7 WAKE* C6 RESET* C5 SPDIF_TX A6 SWIRE_SEL D3 ASP_LRCK/FSYNC B5 SWIRE_SD/ASP_SDIN A5 APN:338S00142 HS4_REF HS3_REF RING_SENSE TIP_SENSE ASP_SDOUT HSBIAS_FILT HSBIAS_FILT_REF SWIRE_CLK/ASP_SCLK AD0 AD1 C3 B2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 BYPASS=U6300.F3:E3:5 MM A1 A2 E7 F7 G7 FILT_P C1 2 BYPASS=U6300.E6:F6:5 MM C BYPASS=U6300.G6:F6:5 MM 2 PP3V3_S0 10% 10V X5R 0402 1 R6302 5% 1/20W MF 2 201 59 110 R6303 1 100K 2 1% 1/20W MF 201 AUD_CODEC_INT_L AUD_CODEC_WAKE_L OUT 58 IN 58 AUD_ASP2_LRCLK IN 58 AUD_ASP2_SDOUT IN 58 AUD_ASP2_SDIN OUT 58 AUD_ASP2_SCLK IN 58 <RDAR://PROBLEM/22033298> AUD_CODEC_RESET_L NC R6304 L83_SDOUT_R 1 0 R6306 PLACE_NEAR=U6300:5mm 2 L83_SDOUT 1 BYPASS=U6300.E7:F7:5 MM BI C6307 IN 1 58 61 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 10% 58 61 10V X5R-CERM 0402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 PLACE_NEAR=U6300:10MM 2 B CRITICAL 2.2UF AUD_I2C_1B_SDA AUD_I2C_1B_SCL L83_FLYP L83_FLYC L83_FLYN 33 5% 1/20W MF 201 5% 1/20W MF 201 NOSTUFF 1 C6380 47PF 5% 2 25V C0G 0201 C6308 2.2UF L83_FILTP 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 CRITICAL C2 D2 G1 1 47K GNDD GNDHS GNDA B6 C7 B3 GNDL SDA SCL FLYP FLYC FLYN 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 A4 B4 L83_HSBIAS_FILT_REF 4.7UF L83_VCP_FILTN E6 G6 U6300 HPSENSA HPOUTA C6306 OMIT_TABLE VCP +VCP_FILT -VCP_FILT GND_VCP 10% 10V X5R 0402 NC AUD_HP_SENSE_R BI 1 1% 1/20W MF 201 2 B VP CRITICAL 62 IN IN AUD_HP_SENSE_L AUD_HP_PORT_R OUT C6352 IN XW6301 SHORT-8L-0.25MM-SM 2 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 10UF D7 R6301 1 4.7UF L83_VCP_FILTP 1 20% 10V 2 X5R-CERM 0402-7 5% 1/20W MF 201 2 AUD_HS_MIC_P C6304 C6305 OMIT_TABLE MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1000 CRITICAL BYPASS=U6300.D7:C7:5 MM 1K 62 L83_VP 2 0201 GND_AUDIO_CODEC NO_XNET_CONNECTION=1 62 1 D6 PP3V3_S0 B1 59 A7 110 2 BYPASS=U6300.D6:F6:5 MM CRITICAL 10% 10V X5R-CERM 0402 FERR-22-OHM-1A-0.055OHM 5% 1/20W MF 201 2 59 1 L6302 1 1K 117 2.2UF 10% 50V 2 X7R 603-1 R6300 C C6302 0.1UF AUD_HP_PORT_L NO_XNET_CONNECTION=1 1 A3 OUT MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 CRITICAL BYPASS=U6300.A3:B3:5 MM 62 L83_VL 2 1 1 C6310 10UF 2 10% 10V X5R-CERM 0402 BYPASS=U6300.G7:F7:5 MM CRITICAL 20% 2 10V X5R 0603 BYPASS=U6300.C1:C2:5 MM GND_AUDIO_CODEC MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 59 117 A SYNC_MASTER=X363_AUDIO SYNC_DATE=01/25/2016 PAGE TITLE AUDIO JACK CODEC DRAWING NUMBER Apple Inc. 051-00647 REVISION R PART NUMBER 138S0719 QTY 2 DESCRIPTION CAP,CER,4.7UF,20%,10V,X5R,0402,MURATA REFERENCE DES CRITICAL BOM OPTION BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE BOM_COST_GROUP=AUDIO II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE CRITICAL C6305,C6306 NOTICE OF PROPRIETARY PROPERTY: 1 63 OF 145 59 OF 121 SIZE D A 8 7 6 5 4 3 2 1 2X MONO SPEAKER AMPLIFIER APN: 353S00604 0dBFS = 9VPK BYPASS=U6400.A2:C2:10 MM BYPASS=U6400.E2:C2:10 MM BYPASS=U6400.A3:B3:5 MM BYPASS=U6400.E3:D3:5 MM VREF_AMP_WL C6400 1 BYPASS=U6400.E4:C4:5 MM 1 1.0UF 1 BI AUD_I2C_1A_SCL AUD_I2C_1A_SDA 58 60 IN IN 58 60 IN SPKRAMP_WL_SCLK 2 5% 1/20W MF 201 PLACE_NEAR=U6400:5MM 58 60 0 1 A4 WLP CRITICAL AUD_ASP1A_LRCLK 1 AUD_ASP1A_SDOUT 0 1 2 SPKRAMP_WL_LRCLK M-RT-SM 5 0806 SPKRAMP_WL_OUT_POS 1 2 114 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 SPKRAMP_WL_OUT_NEG 1 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 114 L6401 SPKRCONN_WL_OUT_NEG 4 LEFT SPEAKER CONNECTOR 6 0806 ADDR0 B5 ADDR1 A5 PP1V8_S0 58 60 61 109 1 I2C ADDRESS = 0x31 C6406 1 220PF C6407 220PF 5% 2 25V C0G-CERM 0402 AGND 5% 1/20W MF 201 1 2 C5 DOUT SPKRAMP_WL_SDIN SPKRCONN_WL_OUT_POS 3 D6 DIN NC 5% 1/20W MF 201 R6405 PLACE_NEAR=U6400:5MM 2 78171-0004 180OHM-3.4A C6 LRCLK R6403 0 D 20% 2 20V POLY SM-1 180OHM-3.4A E6 BCLK R6402 AUD_ASP1A_SCLK 100UF 20% 2 20V POLY SM-1 5% 2 25V C0G-CERM 0402 PGND DGND C1 C2 C3 D3 5% 1/20W MF 201 2 MAX98706 B3 100K C6481 J6410 OUTPSNS E1 D1 OUTP D2 B1 OUTN B2 OUTNSNS A1 E5 RESET* R6401 1 1 L6400 U6400 A6 SCL B6 SDA AUD_SPKRAMP_RESET_L PLACE_NEAR=U6400:5MM C6480 100UF 20% 2 35V X5R-CERM 0603 20% 2 35V X5R-CERM 0603 PVDD B4 IN D5 IRQ* 60 58 1 10UF APN: 518S00521 C4 D4 61 58 AUD_SPKRAMP_INT_L IN 10% 16V 2 X7R-CERM 0402 C6404 1.0UF DVDD 60 58 1 10UF C6405 20% 2 10V X5R-CERM 0201-1 OUT C6403 PP1V8_S0 BYPASS=U6400.A4:B4:5 MM 61 58 1 60 61 109 A2 E2 A3 E3 61 60 58 C6402 0.1UF 10% 2 16V X7R-CERM 0402 VREFC E4 109 1 0.1UF 20% 2 10V X5R-CERM 0201-1 D C6401 PPBUS_G3H C C BYPASS=U6450.A2:C2:10 MM BYPASS=U6450.E2:C2:10 MM BYPASS=U6450.A3:B3:5 MM BYPASS=U6450.E3:D3:5 MM VREF_AMP_TL BYPASS=U6450.E4:C4:5 MM 1 PPBUS_G3H 60 C6450 1 1.0UF 0.1UF 10% 2 16V X7R-CERM 0402 20% 2 10V X5R-CERM 0201-1 1 A4 D5 IRQ* 60 58 BI AUD_I2C_1A_SCL AUD_I2C_1A_SDA A6 SCL B6 SDA U6450 MAX98706 WLP CRITICAL 1 AUD_ASP1A_LRCLK 5% 1/20W MF 201 PLACE_NEAR=U6450:5MM R6455 PLACE_NEAR=U6450:5MM 60 58 60 58 IN IN AUD_ASP1A_SDOUT 1 0 SPKRAMP_TL_SCLK 2 1 2 5% 1/20W MF 201 2 20% 2 35V X5R-CERM 0603 L6450 OUTPSNS E1 D1 OUTP D2 B1 OUTN B2 OUTNSNS A1 180OHM-3.4A SPKRAMP_TL_OUT_POS D6 DIN SPKRAMP_TL_LRCLK NC SPKRAMP_TL_SDIN 2 SPKRAMP_TL_OUT_NEG 1 2 114 L6451 1 SPKRCONN_TL_OUT_NEG C6456 220PF 5% 2 25V C0G-CERM 0402 C5 DOUT AGND SPKRCONN_TL_OUT_POS 114 B I2C ADDRESS = 0x32 C4 D4 5% 1/20W MF 201 0806 1 0806 C6 LRCLK R6453 0 10UF DGND 1 C6457 220PF 5% 25V 2 C0G-CERM 0402 PGND C1 C2 C3 D3 AUD_ASP1A_SCLK C6454 ADDR0 B5 ADDR1 A5 B3 IN 1 180OHM-3.4A B4 60 58 20% 2 35V X5R-CERM 0603 E6 BCLK R6452 0 10UF PVDD E5 RESET* PLACE_NEAR=U6450:5MM 10% 16V 2 X7R-CERM 0402 C6453 1.0UF DVDD IN 0.1UF 1 C6455 20% 2 10V X5R-CERM 0201-1 60 58 C6452 PP1V8_S0 BYPASS=U6450.A4:B4:5 MM B 1 A2 E2 A3 E3 61 60 58 VREFC E4 109 C6451 61 109 A SYNC_MASTER=X363_AUDIO PAGE TITLE SYNC_DATE=01/25/2016 AUDIO Speaker Amps & Conn DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=AUDIO WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 64 OF 145 60 OF 121 SIZE D A 8 7 6 5 4 3 2 1 2X MONO SPEAKER AMPLIFIER APN: 353S00604 0dBFS = 9VPK BYPASS=U6500.E2:C2:10 MM BYPASS=U6500.A2:C2:10 MM BYPASS=U6500.A3:B3:5 MM BYPASS=U6500.E3:D3:5 MM VREF_AMP_TR D C6500 1 BYPASS=U6500.E4:C4:5 MM 1.0UF 1 AUD_SPKRAMP_INT_L 61 59 58 IN 1 5% 1/20W MF 201 PLACE_NEAR=U6500:5MM 61 58 IN AUD_ASP1B_LRCLK IN AUD_ASP1B_SDOUT 0 1 0 1 2 5% 1/20W MF 201 2 SPKRAMP_R_LRCLK A2 E2 A3 E3 A4 C6550 10% 2 16V X7R-CERM 0402 AUD_I2C_1B_SCL AUD_I2C_1B_SDA A4 A6 SCL B6 SDA MAX98706 WLP CRITICAL 61 58 IN PLACE_NEAR=U6550:5MM R6555 IN AUD_ASP1B_SDOUT 1 0 1 2 5% 1/20W MF 201 2 SPKR_ID0 5 6 1 C6506 1 220PF C6507 8 220PF 5% 2 25V C0G-CERM 0402 5% 2 25V C0G-CERM 0402 1 C6552 0.1UF 10% 2 16V X7R-CERM 0402 1 C6553 10UF 20% 2 35V X5R-CERM 0603 1 PPBUS_G3H 60 61 109 C6554 10UF 20% 2 35V X5R-CERM 0603 FL6550 OUTPSNS E1 D1 OUTP D2 B1 OUTN B2 OUTNSNS A1 180OHM-3.4A SPKRAMP_WR_OUT_POS MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 NC SPKRAMP_WR_SDIN C4 D4 5% 1/20W MF 201 114 SPKRCONN_WR_OUT_POS 2 114 SPKRCONN_WR_OUT_NEG B CRITICAL SPKRAMP_WR_OUT_NEG MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 1 FL6551 PP1V8_S0 61 109 1 114 DGND C6556 220PF 5% 2 25V C0G-CERM 0402 I2C ADDRESS = 0X39 C5 DOUT AGND 2 0806 ADDR0 B5 ADDR1 A5 D6 DIN SPKRAMP_WR_LRCLK 0806 1 1 C6557 220PF 5% 2 25V C0G-CERM 0402 PGND C1 C2 C3 D3 61 58 OUT CRITICAL C6 LRCLK R6553 0 58 180OHM-3.4A B3 AUD_ASP1B_LRCLK 5% 1/20W MF 201 PLACE_NEAR=U6550:5MM SPKRAMP_WR_SCLK 2 114 4 114 E6 BCLK R6552 1 61 109 PVDD U6550 B4 AUD_ASP1B_SCLK SPKRCONN_TR_OUT_NEG 1.0UF E5 RESET* IN 114 3 C6555 D5 IRQ* BI 2 FL6501 A2 E2 A3 E3 1 B 61 59 58 PP1V8_S0 C6551 0.1UF DVDD 61 58 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 RIGHT SPEAKER CONNECTOR 2 1 C 1 1.0UF 20% 2 10V X5R-CERM 0201-1 IN 1 PP1V8_S0 BYPASS=U6550.A4:B4:5 MM 61 59 58 SPKRCONN_TR_OUT_POS CRITICAL BYPASS=U6550.E2:C2:10 MM BYPASS=U6550.A2:C2:10 MM BYPASS=U6550.A3:B3:5 MM BYPASS=U6550.E3:D3:5 MM VREFC E4 61 60 58 114 PGND DGND C4 D4 1 7 2 I2C ADDRESS = 0X3A 20% 2 10V X5R-CERM 0201-1 0 1 SPKRAMP_TR_OUT_NEG ADDR0 B5 ADDR1 A5 VREF_AMP_WR BYPASS=U6550.E4:C4:5 MM M-RT-SM 0806 AGND SPKRAMP_R_SDIN 5% 1/20W MF 201 PLACE_NEAR=U6550:5MM SPKRAMP_TR_OUT_POS C5 DOUT NC J6500 78171-6006 0806 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 D6 DIN 109 20% 2 20V POLY SM-1 180OHM-3.4A C6 LRCLK R6503 R6505 PLACE_NEAR=U6500:5MM 61 58 SPKRAMP_R_SCLK 2 100UF 20% 2 20V POLY SM-1 180OHM-3.4A E6 BCLK R6502 AUD_ASP1B_SCLK C6581 C1 C2 C3 D3 61 58 C WLP CRITICAL E5 RESET* 0 100UF D CRITICAL OUTPSNS E1 D1 OUTP D2 B1 OUTN B2 OUTNSNS A1 MAX98706 A6 SCL B6 SDA AUD_SPKRAMP_RESET_L PLACE_NEAR=U6500:5MM 20% 2 35V X5R-CERM 0603 C6580 1 FL6500 U6500 B3 IN 20% 35V 2 X5R-CERM 0603 PVDD B4 60 58 AUD_I2C_1B_SCL AUD_I2C_1B_SDA BI 10UF 1 APN: 518S0672 D5 IRQ* IN 10UF 10% 2 16V X7R-CERM 0402 C6504 1 1.0UF DVDD 61 59 58 C6503 C6505 20% 2 10V X5R-CERM 0201-1 OUT 1 60 61 109 PP1V8_S0 BYPASS=U6500.A4:B4:5 MM 60 58 C6502 0.1UF 10% 2 16V X7R-CERM 0402 VREFC E4 61 60 58 1 0.1UF 20% 2 10V X5R-CERM 0201-1 109 C6501 1 PPBUS_G3H A SYNC_MASTER=X363_AUDIO PAGE TITLE SYNC_DATE=01/25/2016 AUDIO Speaker Amps & Conn DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=AUDIO WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 65 OF 145 61 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D CRITICAL FL6601 120-OHM-25%-1.3A 59 IN AUD_HP_PORT_L 1 2 114 62 AUD_CONN_HP_LEFT 114 62 AUD_CONN_HP_RIGHT 114 62 AUD_CONN_RING2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 0402 CRITICAL FL6600 120-OHM-25%-1.3A 59 IN AUD_HP_PORT_R 1 2 Audio Jack Flex Connector APN: 510S0009 (Matching plug APN: 510S0010) MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 0402 CRITICAL FL6603 120-OHM-25%-1.3A 59 OUT AUD_HP_PORT_US_GND 1 2 MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1000 0402 C J6600 51138-0274 22 CRITICAL F-ST-SM C 21 FL6605 120-OHM-25%-1.3A 59 OUT AUD_HP_PORT_CH_GND 1 2 114 AUD_CONN_SLEEVE 62 MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1000 0402 CRITICAL FL6606 120-OHM-25%-1.3A 59 OUT AUD_HP_SENSE_L 1 2 114 AUD_CONN_HP_SENSE_L 0402 CRITICAL FL6607 NC 120-OHM-25%-1.3A 59 OUT AUD_HP_SENSE_R 1 2 114 AUD_CONN_HP_SENSE_R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AUD_CONN_HP_LEFT 62 114 AUD_CONN_HP_RIGHT 62 114 AUD_CONN_RING2 AUD_CONN_SLEEVE 62 114 62 114 23 0402 24 R6600 59 OUT AUD_TIP_SENSE 1 2K 2 114 AUD_CONN_TIP_SENSE 1% 1/20W MF 201 CRITICAL B B FL6602 120-OHM-25%-1.3A 59 OUT AUD_HS_MIC_P 1 2 114 AUD_CONN_SLEEVE_XW 114 AUD_CONN_RING2_XW 0402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 CRITICAL FL6604 120-OHM-25%-1.3A 59 OUT AUD_HS_MIC_N 1 2 0402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 A SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE AUDIO JACK CONNECTOR DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=AUDIO II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 66 OF 145 62 OF 121 SIZE D A 8 7 6 5 4 3 2 1 J80 Battery Hotbar Flex Pads 998-03902 Flex Pad TO MLB 998-03780. APN:518S0818 OMIT_TABLE CRITICAL J6950 D D PWR-MLB-X363 J6951 HB-SM 10 FF14A-6C-R11DL-B-3H 17 F-RT-SM 7 9 16 NC 1 114 SYS_DETECT_L SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA TP_BMON_IOUT 2 8 3 3 PPVBAT_G3H_CONN 15 64 114 4 BI 49 BI 49 OUT 114 6 14 7 1 1 5 12 4 11 C6960 1 0.1UF 1 RCLAMP3552T SLP1006N3T CRITICAL 1UF 10% 25V 2 X5R 402 10% 25V 2 X5R 603-1 3 C6950 D6950 5% 1/16W MF-LF 2 402 NC 13 6 R6950 10K 8 2 2 1 5 C C BMU POWER FLEX HOTBAR'd TO THE MLB: QTY 1 116 114 64 B PPDCIN_G3H_CHGR MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=8.6V PCBA,FLEX,BMU PWR,X363 0 2 SOT-323 PPDCIN_G3H_CHGR_R 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=8.6V 3 2 R6907 109 PPBUS_G3H 1 5% 1/8W MF-LF 805 CRITICAL D6902 5% 1/16W MF-LF 402 2.2 J6950 BOM OPTION BAT30CWFILM R6920 1 CRITICAL 2 64 DIDT=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 PPVIN_G3H_P3V3G3H MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=8.6V 1 C6905 1 2.2UF PPBUS_G3H_R MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V C6906 1 2.2UF 20% 2 35V X5R-CERM 0402 20% 2 35V X5R-CERM 0402 MAX77596 7 R6921 64 1 0 PM_EN_P3V3_G3H_R TP6910 TP TP-P5 1 10 NC 6 DIDT=TRUE TDFN SUP CRITICAL BST 1 P3V3G3H_VBST LX 3 P3V3G3H_LX R6908 0 1 C6907 0.1UF 10% 2 16V X5R-CERM 0201 5% 1/20W MF 2 0201 EN OUT/FB RESET* BIAS 9 8 P3V3G3H_FB R6923 CRITICAL 1 L6900 1 DIDT=TRUE PP3V3_G3H_REG_R 2 MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V SWITCH_NODE=TRUE R6910 115K 0.1% 1/20W MF 0201 1 C6910 R6911 47K 0.33UF 2 R6912 0.1% 1/20W MF 2 0201 10% 2 16V CERM-X7R 603 1 C6912 10UF 20% 2 6.3V CERM-X5R 0402 5% 1/20W MF 2 201 109 1 C6913 10UF 1 C6914 1 10UF 20% 2 6.3V CERM-X5R 0402 20% 2 6.3V CERM-X5R 0402 CRITICAL CRITICAL C6915 1 10UF C6916 1 10UF 10UF 20% 6.3V 2 CERM-X5R 0402 20% 2 6.3V CERM-X5R 0402 C6917 20% 6.3V 2 CERM-X5R 0402 1 C6919 12PF 5% 2 25V NP0-C0G 0201 2 CRITICAL C6911 5.6PF 2 1 1 10 P3V3G3H_BIAS 1 PP3V3_G3H 2 PIYA25201B-SM 1 XW6900 SM 0 5% 1/10W MF-LF 603 10UH-20%-1.4A-0.399OHM MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 MODE 5 4 5% 1/20W MF 201 2 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 U6903 2 PM_EN_P3V3_G3H B P3V3G3H_VBST_R EPAD FROM USB-C SOURCE REFERENCE DES 11 632-00862 DESCRIPTION AGND PGND PART NUMBER 1 CRITICAL CRITICAL CRITICAL CRITICAL C6919 FOR DESENSE P3V3G3H_FB_RC +/-0.1PF 25V C0G 0201 P3V3G3H_FB_R 1 R6913 1.47K A 1% 1/20W MF 201 2 SYNC_MASTER=J80_MLB PAGE TITLE P3V3G3H_AGND SYNC_DATE=11/06/2015 DC-In & Battery Connectors DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=PLATFORM POWER WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 69 OF 145 63 OF 121 SIZE D A 8 7 6 5 8X B1 CRITICAL CRITICAL 6.8UF C7024 C7025 6.8UF 6.8UF 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM CRITICAL 1 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM CRITICAL 1 C7026 6.8UF 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM CRITICAL 1 C7027 CRITICAL C7028 1 6.8UF 6.8UF C7032 C7033 20% 2 35V X5R-CERM 0402 20% 2 35V X5R-CERM 0402 20% 2 35V X5R-CERM 0402 PLACE_NEAR=Q7030.2:1MM PLACE_NEAR=Q7030.1:3mm 2.2UF 6.8UF 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM C7029 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM 1 2.2UF C7034 2.2UF FROM USB-C SOURCE R7020 0.01 0.5% 0.5W MF 0306 1 TP 1 TP TP-P5 1 TP TP-P5 TBA_GATE_Q4 64 1 TP TP-P5 114 64 TBA_LX1 1 TP TP-P5 114 64 TBA_LX2 1 TP TP-P5 64 48 SMC_CHGR_INT_L 1 C7056 2.2UF 68UF 20% 2 16V POLY-TANT CASE-D2E-SM C7053 1 2.2UF 20% 2 25V X5R 0402-1 20% 2 16V POLY-TANT CASE-D2E-SM C7055 1 C7057 2.2UF 20% 2 25V X5R 0402-1 20% 2 25V X5R 0402-1 1 C7058 2.2UF 1 1 TP TP-P5 C7021 TP7001 1 1 C7022 0.047UF 10% 50V 2 CER-X7R 0402 C7054 1000PF 10% 2 25V X7R 0201 20% 2 25V X5R 0402-1 10% 2 50V CER-X7R 0402 TBA_GATE_Q3 TBA_LX1 1 114 C7030 TBA_BOOT1_RC 1 TP7004 TP7005 Q7040 0 (PBUS) SI7137DP 1% 1W MF 0612-5 PPVBAT_G3H_CHGR_R 1 3 C7061 750K 1 1% 1/20W MF 2 201 2.2UF TBA_CSO_R_N 1 0.01UF 1 10% 25V X5R-CERM 2 0201 1 R7016 255K C7023 1% 1/20W MF 2 201 PPVIN_G3H_P3V3G3H B5 C5 D5 A5 D3 P_IN CSIN CSIP MPM_PBUS AUX_DET ISL9239 WCSP-1 B2 SGATE C2 AGATE E4 MPM_DET 109 PP3V3_G3H 1 R7009 1 20% 10V X5R-CERM 2 0201-1 5% 1/20W MF 201 2 C7080 1.0UF 100K 49 BI 49 IN 48 IN SMBUS_SMC_5_G3_SDA SMBUS_SMC_5_G3_SCL SMC_4FINGERS_RST 114 HPWR_EN_L F5 G5 H5 G2 G3 E5 VR1_3P3 SDA SCL SMC_RST_IN HPWR_EN* COMP G4 CELL A PLACE_NEAR=U7000.A5:2MM 1 C7070 20% 35V X5R-CERM 2 0402 0.12UF 1 10% 10.0V CERM-X5R 2 402 1 E3 NO STUFF 2.2UF 10% 50V 2 CER-X7R 0402 0201 TBA_BGATE 1 C7063 4700PF 10% 2 25V CER-X5R 0201 1 B C7071 GATE_Q1 BOOT1 LX1 GATE_Q2 GATE_Q3 LX2 BOOT2 GATE_Q4 PBUS CSOP CSON BGATE VBAT EN_VR1 SMC_RST* IRQ* CBC_ON MPM_OK AUX_OK AMON BMON H1 F1 G1 E1 D1 B1 C1 A1 A3 A4 B4 B3 C3 F2 H4 H3 H2 F4 NC F3 D4 C4 C7020 0.47UF 2 1 PLACE_NEAR=U7000.A4:1MM 20% 4V CERM-X5R-1 201 PM_EN_P3V3_G3H SMC_RST_L SMC_CHGR_INT_L SMC_CBC_ON SMC_BC_ACOK CHGR_AMON CHGR_BMON OUT 63 1 OUT 48 64 OUT 46 OUT 48 OUT 50 114 OUT 50 114 R7090 100K 2 SMC_RESET_L OUT 29 48 57 76 114 5% 1/20W MF 201 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE PBUS Supply & Battery Charger DRAWING NUMBER E2 AGND PPVIN_G3H_P3V3G3H PGND TBA_COMP C7081 C7062 0.047UF 10% 50V CER-X7R 2 0402 10% 2 25V X5R U7000 1 20% PLACE_NEAR=U7000.C5:1MM 4V CERM-X5R-1 201 63 64 0.047UF C7060 0.1UF 2 10% 25V X7R 0201 63 114 BOMOPTION=OMIT_TABLE 0.47UF 2 1 TBA_CSO_N 1 1 4 1000PF 1% 1/20W MF-LF 2 0201 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 PLACE_NEAR=Q7065.5:2MM G C7064 1.00 PPVBAT_G3H_CONN 5 20% 25V X5R-CERM 2 0603 VDDA A2 NO STUFF R7062 D 10UF 20% 25V 2 X6S-CERM 0402 TBA_AUX_DET C7016 C7077 TO/FROM BATTERY VDDP D2 B C7075 3 S 2 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 TBA_CSO_P TBA_VDDP TBA_VDDA Q7065 SO-8 1% 1/20W MF-LF 0201 2 2 10% 25V 2 X5R-CERM 0201 SYM-VER-2 1 C 1 0.01UF 10% 25V 2 X5R 0201 0.005 2 4 TBA_BOOT2 5% 1/20W MF 201 114 0.1UF 20% 25V 2 X5R 0402-1 CRITICAL 1.00 R7015 2.2UF C7068 1 CRITICAL (BMON) TP7007 1 C7067 1 R7060 1 R7061 4.7 C7069 20% 25V X5R 2 0402-1 TBA_CSO_R_P 1 1 2.2UF 1 5% 1/16W MF-LF 402 2 TBA_BOOT1 2 1206 C7066 TP7006 64 63 1 TBA_LX2 R7040 5% 1/16W MF-LF 2 402 116 F7001 TBA_BOOT2_RC 0 109 12AMP-32V 10% 25V X7R-CERM 2 0402 R7030 PPBUS_G3H 2 1206 0.1UF 10% 2 25V X7R-CERM 0402 1 TBA_GATE_Q4 C7040 0.1UF TP7003 64 PPVBAT_G3H_CHGR_REG MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 CRITICAL DFN TBA_GATE_Q2 TBA_GATE_Q1 TO SYSTEM 12AMP-32V FDMD8800 14 6 5 S2 5 6 14 4 G2 TBA_CSI_N 4 G2 1% 1/20W MF-LF 2 0201 11 G1R 1.00 12 G1 R7022 S1/D2 7 8 9 10 1 2 3 13 1 0.047UF TP7002 F7000 R7075 Apple Inc. 0.12UF 051-00647 REVISION R 10% 2 10.0V CERM-X5R 402 PART NUMBER 152S00199 QTY 1 DESCRIPTION IND,MLD,2.7UH,16A,14.8MO,10.9x10.0x3.00 REFERENCE DES L7030 CRITICAL BOM OPTION CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE BOM_COST_GROUP=PLATFORM POWER I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 D CRITICAL 114 TBA_CSI_R_N TBA_CSI_P TP-P5 TBA_GATE_Q3 C7052 68UF 20% 2 16V POLY-TANT CASE-D2E-SM CRITICAL 1 3 1% 1/20W MF-LF 0201 2 64 CRITICAL 1 IHLP4040CZ-PIMA103T-SM-COMBO 1.00 TBA_GATE_Q2 C7051 68UF 20% 2 16V POLY-TANT CASE-D2E-SM S2 (AMON) R7021 1 64 C7050 68UF 20% 2 35V X5R-CERM 0402 CRITICAL 1 2.7UH-20%-21.5A-0.0135OHM 2 TBA_PHASE2 TBA_PHASE1 1 D1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 TBA_CSI_R_P C 2.2UF CRITICAL 1 L7030 CRITICAL 2 4 64 1 BOMOPTION=OMIT_TABLE PPDCIN_G3H TBA_GATE_Q1 CRITICAL C7035 DFN 50 29 Q7030 114 FDMD8800 116 1 D1 20% 2 35V-0.09OHM POLY-TANT CASE-B1-2-SM CRITICAL 1 1 4X D2 PPDCIN_G3H_CHGR MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 1 13 3 2 1 6.8UF C7043 1 2 12 G1 C7042 1 63 11 G1R 1 114 3 10 9 8 S1/D2 7 CRITICAL D 116 4 1 70 OF 145 64 OF 121 SIZE D A 8 7 6 R7143 FB_GT_R 1 R7142 8 CPU_VCCGTSENSE_P IN 0 1 2 3300PF 2 1 FB_B_CPUGT 3.01K 2 1% 1/20W MF 201 C7144 5% 1/20W MF 201 R7145 R7144 FB_B_GT_R 1K 2 1 1 560 2 CPU_VCCGTSENSE_N 1 1 C7141 1 RTN_B_CPUGT 330PF 2 C7143 FB_A_CPUCORE_RC 10% 25V X7R-CERM 0201 68 65 IN 68 65 IN 2 2 2 R7150 432 CPUGT_ISUMN_R 1 1% 1/20W MF 201 CPUGT_ISEN1 1K 1 10% 10V X7R-CERM 0201 2 3300PF 1 2 GT_ISUMN_R 1% 1/20W MF 201 1 0.01UF 10% 10V X7R-CERM 0201 68 OUT 68 OUT 68 OUT 68 65 65 IN 10% 2 10V X7R-CERM 0201 C7162 R7160 68PF IMON_B_CPUGT 1% 1/20W MF 201 2 55 65 C7160 6800PF 1 2 IN 2 4.64K COMP_B_CPUGT_L 67 IN 67 1 67 2 499 CPUSA_ISUMN_R 67 65 C7182 1K 1 0.01UF 9 10 ISUMP_A ISUMN_A 19 27 PP5V_S4 2 CPUSA_FCCM 35 PWM_C 32 65 CPUSA_ISUMP CPUSA_ISUMN_R 65 COMP_C_CPUSA 29 65 FB_C_CPUSA 30 65 RTN_C_CPUSA 31 65 33 FB_A RTN_A_CPUCORE 65 IMON_A_CPUCORE 55 65 VR_HOT* 46 CPUCORE_PROCHOT_R_L 65 C7190 COMP_C SDA 43 CPUCORE_VIDSOUT_R ALERT* 44 CPUCORE_VIDALERT_R_L SCLK 45 CPUCORE_VIDSCLK_R FB_C RTN_C 40 PROG4_CPUCOREVR PROG5_CPUCOREVR 37 PROG1 PROG2 PROG3 PROG4 PROG5 PSYS IN 65 66 IN 65 66 IN 65 66 150PF 6800PF 1 2 5% 50V CER-C0G 0201 FB_SA_R 2 R7172 IN CPU_VCCSASENSE_P 0 1 2 C7174 2200PF 5% 1/20W MF 201 2 1 COMP_C_CPUSA_L A 2 R7155 2 CORE_ISUMN_R 1 1 C7171 1 1 330PF 10% 16V X7R 0201 2 1% 1/20W MF 201 1% 1/20W MF 201 2 1 2 R7102 0 CPU_PROCHOT_L 2 5% 1/20W MF 201 R7103 1 100 2 1 1 2 R7110 1 C7108 2 10% 10V X7R 201 2 R7175 R7174 C7157 1 2 C7158 1 10% 10V X7R-CERM 0201 2 0.01UF 10% 10V X7R-CERM 0201 2 1K 1 1 560 1% 1/20W MF 201 2 1 2 R7104 10 0 2 2 2 CPU_VIDSOUT 5% 1/20W MF 201 2 10% 25V X7R-CERM 0201 1 110K 65 2 C7172 R7111 1% 1/20W MF 201 R7112 1 71.5K 2 1% 1/20W MF 201 1 R7113 16.9K 2 R7114 1 182K 1% 1/20W MF 201 2 1% 1/20W MF 201 IN C7159 10% 10V X7R-CERM 0201 8 CPU_VIDSCLK IN B 56PF 8 65 COMP_A_CPUCORE 1 1 66 67 110 2.87K 1% 1/20W MF 201 R7107 1% 1/20W MF 201 2 5% 25V NP0-C0G 0201 R7193 C7194 6800PF 1 2 COMP_A_CPUCORE_L 10% 10V X7R-CERM 0201 R7108 65 NTC_B_CPUGT 1 14K 2 NTC_B_CPUGT_R R7194 1% 1/20W MF 201 1% 1/20W MF 201 65 55 IMON_A_CPUCORE 1 1 C7195 150PF 1 100K 2 5% 50V CER-C0G 0201 65 R7115 NTC_A_CPUCORE 1 14K NTC_A_CPUCORE_R 2 1% 1/20W MF 201 SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/10/2015 PAGE TITLE CORE & SA IMVP IC 1 1% 1/20W MF 201 DRAWING NUMBER R7123 Apple Inc. 220KOHM-3% 10% 16V X7R 0201 2 051-00647 REVISION R 0201 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 6 5 4 3 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 7 2 1% 1/20W MF 201 II NOT TO REPRODUCE OR COPY IT 8 2 R7121 65 65 121K 2 65 66 R7120 PROG5_CPUCOREVR 1 IN C7193 65 820PF CPUCORE_ISEN3 8 BI CPU_VIDALERT_L 65 PROG4_CPUCOREVR 65 66 C7149 220KOHM-3% C7173 IN 110 65 FB_C_CPUSA_RC CPUCORE_ISEN2 0.01UF R7124 PROG1_CPUCOREVR 65 PROG2_CPUCOREVR PROG3_CPUCOREVR 65 66 1% 1/20W MF 201 12.1K 4700PF IN C R7109 5% 1/20W MF 201 R7106 1 CPUCORE_ISEN1 100 1% 1/20W MF 201 R7105 1 66 SVID_PU:CORE 1 1 1 IN 10% 2 10V X7R-CERM 0201 73 IN PP1V0_S3 SVID_PU:CORE 1 2 CPUCORE_ISUMN 0.01UF ALL_SYS_PWRGD 5% 1/20W MF 201 65 65 66 6 46 47 OUT 330PF 2 2 2 1% 1/20W MF 201 RTN_C_CPUSA 1K 0.01UF 73 49.9 IN 10% 25V X7R-CERM 201 0201 SM IN 365 10% 10V X7R-CERM 0201 1 CPUCORE_PSYS FB_C_CPUSA XW7170 CPU_VCCSASENSE_N 2.7K 10% 16V X7R 0201 2 C7156 2 1% 1/20W MF 201 C7155 45.3 1% 1/20W MF 201 2.49K 1 10% 10V X7R-CERM 0201 9 8 1 3300PF CPU_VR_EN_R R7191 2 FB_C_SA_R 2 12.1K COMP_C_CPUSA 1 1 10% 10V X7R-CERM 0201 330PF NOSTUFF R7173 8 CPUCORE_ISUMN_R 65 65 1 5% 50V CER-C0G 0201 C7191 C7145 1 220PF 65 CPUVR_PGOOD 48 PROG1_CPUCOREVR PROG2_CPUCOREVR PROG3_CPUCOREVR 36 NTC_A_CPUCORE VR_ENABLE IMON_C 38 15 ISUMP_C ISUMN_C 28 39 NTC_A 65 66 1 1 2 8 9 IN CPUCORE_ISUMP R7154 FB_A_CPUCORE 150PF IMON_C_CPUSA 1 CPU VCC Core 65 C7192 2 10% 16V X7R 0201 1% 1/20W MF 201 1 CPU_VCCSENSE_N 1 330PF 65 17 47 10% 10V X7R-CERM 0201 R7190 1% 1/20W MF 201 2 110 PP5V_S0 100K RTN_A_CPUCORE 1 COMP_A_CPUCORE VR_READY IMON_C_CPUSA OUT 66 16 NTC_B CPUSA_PWM 66 COMP_A FB_B FCCM_C OUT 23 22 14 34 66 CPUCORE_ISEN1 CPUCORE_ISEN2 CPUCORE_ISEN3 IMON_A 3 OUT 21 IMON_B NTC_B_CPUGT 66 ISEN1_A ISEN2_A ISEN3_A 2 COMP_B OUT IN 10% 10V X7R-CERM 2 0201 2 XW7141 10% 10V X6S-CERM 0402 CPUCORE_ISUMP CPUCORE_ISUMN_R 20 IMON_B_CPUGT 65 2 ISEN1_B ISEN2_B CPUCORE_PWM1 CPUCORE_PWM2 CPUCORE_PWM3 26 RTN_A 65 3300PF 1% 1/20W MF 201 8 ISUMP_B ISUMN_B 25 RTN_B 65 1 7 PWM1_A PWM2_A PWM3_A RTN_B_CPUGT 65 SA_ISUMN_R 13 CPUCORE_FCCM 65 65 C7180 2 D 10% 16V X5R-X7R-CERM 0201 C7146 49 B 1 PWM1_B PWM2_B 24 18 IN 1% 1/20W MF 201 R7181 12 FCCM_A 6 65 1 CPUGT_PWM1 CPUGT_PWM2 LLP 65 OUT R7180 CPUSA_ISUMN FCCM_B 5 OUT CPU VCC SA 1 2 11 65 1% 1/20W MF 201 220PF 10% 25V X7R-CERM 201 CPUGT_FCCM FB_B_CPUGT CPUSA_ISUMP C7181 1% 1/20W MF 201 2 C7100 U7100 4 R7161 1 10% 10V X7R-CERM 0201 5% 50V CER-C0G 0201 67 65 1 1UF COMP_B_CPUGT 65 5% 25V C0G 0201 C7161 150PF 2 FB_A_CORE_R 2 8 IN 5% 1/20W MF 201 5% 1/20W MF 201 1 65 65 55 COMP_B_CPUGT 1 1 1 2 CPUGT_ISEN1 CPUGT_ISEN2 IN 68 65 CPU VCC GT + GTx Merged C7152 10% 25V X7R 0402 CPUGT_ISUMP CPUGT_ISUMN_R IN 0.01UF 2 1% 1/20W MF 201 470PF CPU_VCCSENSE_P 1 ISL95828HRTZ 68 65 1 1 C7101 2 10% 10V X7R-CERM 0201 2 C 100K MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V 65 C7150 R7151 CPUGT_ISEN2 0.01UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V 0.22UF 2 C7153 PP5V_COREVR_VCC 42 1 PPVIN_S0_CPUVR_VIN VCC 2 1 CPUGT_ISUMN 1 1K 1 0 2 C7147 R7100 41 1 10 VIN PPBUS_HS_CPU CPUGT_ISUMP C7154 2 65 THRM_PAD IN 2 560 R7146 R7148 10% 16V X7R 0201 220PF 68 10% 25V X7R-CERM 0201 1 FB_CORE_R SM 5% 1/20W MF 201 10% 25V X7R-CERM 201 1 65 109 C7151 C7148 R7149 680PF R7101 IN 2.61K 2 1% 1/20W MF 201 330PF 10% 16V X7R 0201 68 65 1 C7142 1 1 R7147 FB_A_CPUCORE 820PF 2 2 2 65 SM IN 3 FB_B_CPUGT_RC XW7140 9 8 4 65 1% 1/20W MF 201 1% 1/20W MF 201 10% 10V X7R-CERM 0201 D 5 1 71 OF 145 65 OF 121 SIZE D A 8 109 66 7 6 5 1 CRITICAL C7251 1 33UF PP5V_S0 R7216 1 2 5% 1/16W MF-LF 402 66 2 1 2.2UF 20% 25V X6S-CERM 0402 2 PVCC 29 D C7217 PVCCCORE_PH1_AGND CPUCORE_PWM1 IN CPU VCC Phase 1 30 NC 31 NC 66 C7255 1 33UF 20% 2 16V TANT-POLY CASE-B3 PVCCCORE_PH1_AGND 1 C7257 THESE TWO CAPS ARE FOR EMC 1 33UF C7258 1 33UF 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 C7290 1 0.001UF 33UF C7291 0.001UF 10% 2 50V X7R-CERM 0402 10% 2 50V X7R-CERM 0402 20% 2 16V TANT-POLY CASE-B3 R7210 1 CPUCORE_SW1 CPUCORE_BOOT1 7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE PILA63T-SM R7219 1 0 5% 1/16W MF-LF 402 CPUCORE_BP1 2 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V 4 3 CPUCORE_ISNS1_P CPUCORE_ISNS1_N R7218 5% 1/10W MF-LF 603 2 1 NOSTUFF 2 OUT 51 OUT 51 66 1% 1/20W MF 201 NO_XNET_CONNECTION CPUCORE_ISUMN OUT 65 66 R7214 DIDT=TRUE 2 1 2 R7212 C7218 NO_XNET_CONNECTION 10% 50V X7R-CERM 0402 1 1 1K 1% 1/20W MF 201 R7213 200K 2 2 1% 1/20W MF 201 200K 2 NO_XNET_CONNECTION CPUCORE_ISEN1 OUT R7215 XW7210 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 2 CPUCORE_PHASE1 SM 1 200K 2 CPUCORE_ISUMP 2 OUT 51 66 NO_XNET_CONNECTION 65 0.22UF 10% 25V X7R 0402 CPUCORE_ISNS2_N 1 1% 1/20W MF 201 NOSTUFF 1 CPUCORE_ISNS3_N 1 1% 1/20W MF 201 65 66 51 66 NO_XNET_CONNECTION 6X 2.2UF 0402 THESE TWO CAPS ARE FOR EMC C 67 66 65 110 C7271 PP5V_S0 R7226 1 2 5% 1/16W MF-LF 402 2 1 2.2UF 20% 25V X6S-CERM 0402 2 PVCC 29 66 C7227 PVCCCORE_PH2_AGND IN NC NC 30 NC 31 NC 4 32 B 66 66 67 66 65 110 PVCCCORE_PH2_AGND PPBUS_HS_CPU 5 CPUCORE_BOOT2 7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GH 6 R7229 1 0 CPUCORE_BP2 20% 25V X6S-CERM 2 0402 2.2UF 20% 25V X6S-CERM 2 0402 PPVCC_CPU_PH2 1 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V 3 4 CPUCORE_ISNS2_P CPUCORE_ISNS2_N R7228 1 5% 1/10W MF-LF 603 2 2 51 OUT 51 66 1% 1/20W MF 201 1 0.001UF 0.001UF 10% 2 50V X7R-CERM 0402 20% 25V X6S-CERM 2 0402 C7293 C 10% 2 50V X7R-CERM 0402 NO_XNET_CONNECTION CPUCORE_ISUMN OUT 65 66 R7224 DIDT=TRUE 2 1 R7222 C7228 0.001UF 2 10% 25V X7R 0402 XW7220 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 2 CPUCORE_PHASE2 1 C7292 R7221 2.2 NOSTUFF OUT NO_XNET_CONNECTION 10% 50V X7R-CERM 0402 1 1 1K 1% 1/20W MF 201 R7223 200K 2 2 2 1% 1/20W MF 201 CPUCORE_ISEN2 OUT CPUCORE_ISUMP OUT 51 66 NO_XNET_CONNECTION R7225 65 200K 2 2 CPUCORE_ISNS1_N 1 1% 1/20W MF 201 NO_XNET_CONNECTION NOSTUFF 1 200K 0.22UF SM 1 1 2.2UF 20% 25V X6S-CERM 2 0402 CPUCORE_SW2_SNUB MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE C7229 CPUCORE_ISNS3_N 1 1% 1/20W MF 201 65 66 51 66 NO_XNET_CONNECTION B PLACE_NEAR=U7220.32:2MM PP5V_S0 R7236 1 2 5% 1/16W MF-LF 402 2 1 2.2UF 20% 25V X6S-CERM 0402 2 PVCC 29 66 C7237 PVCCCORE_PH3_AGND NC NC 5 CPUCORE_BOOT3 7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 30 NC 31 NC GH 6 4 32 PVCCCORE_PH3_AGND 0 NC NC NC 5% 1/16W MF-LF 402 CPUCORE_BP3 2 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15V 4 3 CPUCORE_ISNS3_P CPUCORE_ISNS3_N R7238 1 5% 1/10W MF-LF 603 2 2 51 OUT 51 66 PART NUMBER R7231 2.2 NOSTUFF OUT 1% 1/20W MF 201 NO_XNET_CONNECTION CPUCORE_ISUMN OUT 1 1 10% 25V X7R 0402 1 3 REFERENCE DES U7210,U7220,U7230 IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5 CRITICAL BOM OPTION CRITICAL R7234 R7232 C7238 0.001UF 2 DESCRIPTION 65 66 DIDT=TRUE 2 QTY 353S00497 NO_XNET_CONNECTION 10% 50V X7R-CERM 0402 1 1 1K 1% 1/20W MF 201 R7233 200K 2 2 2 1% 1/20W MF 201 CPUCORE_ISEN3 OUT CPUCORE_ISUMP OUT 51 66 NO_XNET_CONNECTION SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN 200K 1% 1/20W MF 201 65 66 SYNC_DATE=09/03/2015 PAGE TITLE R7235 65 2 2 CPUCORE_ISNS1_N 1 1% 1/20W MF 201 NO_XNET_CONNECTION NOSTUFF 200K 0.22UF SM 2 PPVCC_CPU_PH3 CPUCORE_SW3_SNUB MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE C7239 XW7230 66 1% 1W MF 0612-1 2.2 R7239 1 16 24 2 PILA63T-SM 1 GL0 27 GL1 33 AGND AGND CPU VCC Phase 3 1 CPUCORE_SW3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE PGND PGND IN CPUCORE_PWM3 R7230 0.00075 L7231 OMIT_TABLE 8 VIN FDMF5808A BOOT 9 VIN PQFN-COMBO-THICKSTNCL PHASE 2 FCCM CRITICAL SW 1 PWM SW CPUCORE_FCCM CRITICAL 12 28 65 IN CRITICAL 20% 25V X6S-CERM 0402 0.2UH-20%-28A-0.0011OHM U7230 66 65 C7236 2.2UF PVCCCORE_PH3_VCC VCC 3 1 1 A 5% 1/16W MF-LF 402 NC 2.2UF C7299 1 1% 1W MF 0612-1 2.2 16 24 NC NC 2 PILA63T-SM 1 GL0 27 GL1 33 AGND AGND CPU VCC Phase 2 1 CPUCORE_SW2 12 28 65 CPUCORE_PWM2 2.2UF C7275 1 0.00075 L7221 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE PGND PGND CPUCORE_FCCM IN C7274 1 R7220 CRITICAL OMIT_TABLE 8 VIN FDMF5808A BOOT 9 VIN PQFN-COMBO-THICKSTNCL PHASE 2 FCCM SW CRITICAL 1 PWM SW 20% 25V X6S-CERM 2 0402 C7273 CRITICAL 20% 25V X6S-CERM 0402 0.2UH-20%-28A-0.0011OHM U7220 66 65 C7226 1 2.2UF 20% 25V X6S-CERM 2 0402 2.2UF PVCCCORE_PH2_VCC VCC 3 1 109 C7272 1 2.2UF 1 109 Vout = 0.55 - 1.5V ICCMAX = 68A F = 750kHz R7211 2.2 0.001UF C7219 PPVCC_S0_CPU CPUCORE_SW1_SNUB MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE NC PPVCC_CPU_PH1 2.2 16 24 NC NC 2 D 1% 1W MF 0612-1 PLACE_NEAR=U7210.32:2MM PPBUS_HS_CPU 1 C7259 0.00075 L7211 5 GH 6 C7256 33UF CRITICAL 12 28 4 32 109 20% 2 16V TANT-POLY CASE-B3 1 1 CRITICAL 20% 25V X6S-CERM 0402 1 GL0 27 GL1 33 AGND AGND NC NC 66 C7254 33UF 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE PGND PGND 65 1 33UF 2 C7216 OMIT_TABLE 8 VIN FDMF5808A BOOT 9 VIN PQFN-COMBO-THICKSTNCL PHASE 2 FCCM CRITICAL SW 1 PWM SW CPUCORE_FCCM IN C7253 CRITICAL 0.2UH-20%-28A-0.0011OHM U7210 66 65 1 CRITICAL 2.2UF PVCCCORE_PH1_VCC VCC 3 1 1 C7252 33UF 20% 2 16V TANT-POLY CASE-B3 CRITICAL CRITICAL 3 7x 33uF B3 CRITICAL PPBUS_HS_CPU CRITICAL 67 66 65 110 4 1 CPUCORE_ISNS2_N CORE IMVP POWER BLOCK 51 66 DRAWING NUMBER NO_XNET_CONNECTION MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE Apple Inc. 051-00647 REVISION R CPUCORE_PHASE3 PLACE_NEAR=U7230.32:2MM NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 72 OF 145 66 OF 121 SIZE D A 8 109 7 6 5 4 3 3X 33UF B3 PPBUS_HS_CPU CRITICAL CRITICAL 110 66 65 2 1 PP5V_S0 C7380 1 20% TANT-POLY CASE-B3 2 16V 33UF R7375 5% 1/16W MF-LF 402 67 1 PVCCCSA_VCIN C7377 1 2 2 11 2.2UF CRITICAL BOMOPTION=OMIT_TABLE 20% 25V X6S-CERM 0402 L7330 1 PVCCCSA_AGND U7370 1 IN CPUSA_PWM 1 12 ZCD_EN* PWM BOOT CPUSA_BOOTSA PHASE 5 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE VSWH 8 GL GL 9 NC PGND PGND CGND NC 3 CRITICAL 7 CPU VCCSA 10 65 IN CPUSA_FCCM VIN 4 14 2 R7379 1 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15V 3 4 5% 1/16W MF-LF 402 2 CPUSA_BPSA 20% TANT-POLY CASE-B3 2 16V CPUSA_ISNS_P CPUSA_ISNS_N C7383 20% TANT-POLY CASE-B3 2 16V 33UF 20% TANT-POLY CASE-B3 C7395 2.2UF 1 20% 25V X6S-CERM 2 0402 C7396 1 2.2UF 20% 25V X6S-CERM 2 0402 D R7372 0 1 2 5% 1/20W MF 201 NOSTUFF OUT 53 OUT 53 CPUSA_ISUMN OUT 65 CPUSA_ISUMP OUT 65 109 Vout = 0.55 - 1.15V ICCMAX = 11.1A F = 750kHz NO_XNET_CONNECTION=1 R7374 1 1K 2 1% 1/20W MF 201 C7378 0.001UF 2 1 33UF PPVCCSA_S0_CPU DIDT=TRUE 1 0 NC NC NO_XNET_CONNECTION=1 10% 50V X7R-CERM 0402 NOSTUFF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE C7379 1 0.22UF XW7370 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SM 2 1 CPUSA_SW_SNUB 13 65 MLP4535 PPVCCSA_CPU_R 2.2 5% 1/10W MF-LF 603 C7382 1% 1/2W MF 0306 R7378 SIC535CD 6 2 IHLP2020BD-SM 1 0.002 0.22UH-20%-22A-0.0037OHM MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE C7381 R7370 CRITICAL CPUVR_SWSA VDRV 20% 25V X6S-CERM 0402 C7376 2.2UF 2 D 2 VCIN 1 1 2X 2.2UF 0402 CRITICAL 33UF 2 16V 1 1 CPUSA_PHASESA PVCCCSA_AGND PLACE_NEAR=U7370.10:2MM 67 10% 25V X7R 0402 2 PART NUMBER 152S00371 QTY 1 DESCRIPTION IND,MLD,0.22UH,20%,22A,3.7MO,5.1x5.2x2.4 REFERENCE DES L7330 CRITICAL BOM OPTION CRITICAL C C B B A SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=11/18/2015 PAGE TITLE SA IMVP IC DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 73 OF 145 67 OF 121 SIZE D A 8 7 109 68 6 5 CRITICAL PPBUS_HS_CPU 1 CRITICAL C7400 1 33UF 110 68 CRITICAL C7401 CRITICAL C7402 1 33UF 20% 2 16V TANT-POLY CASE-B3 PP5V_S0 4 1 33UF 20% 2 16V TANT-POLY CASE-B3 CRITICAL C7403 1 33UF CRITICAL C7404 1 33UF 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 D C7417 1 2.2UF 20% 25V X6S-CERM 0402 68 2 IN CPUGT_FCCM 65 IN CPUGT_PWM1 NC NC 7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 16 24 NC NC CPUGT_BP1 NC MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 1 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V 3 4 NOSTUFF 33UF 20% 2 16V TANT-POLY CASE-B3 OUT 53 OUT 53 68 1% 1/20W MF 201 NO_XNET_CONNECTION CPUGT_ISUMN 65 68 OUT R7414 DIDT=TRUE R7412 1 C7418 1 2 1 1K 10% 50V X7R-CERM 0402 2 D 109 Vout = 0.55 - 1.5V ICCMAX = 55A F = 750kHz R7411 2 1% 1/20W MF 201 NO_XNET_CONNECTION 2 R7413 200K 2 2 200K 1 1% 1/20W MF 201 1% NO_XNET_CONNECTION 1/20W MF 201 NOSTUFF CPUGT_ISEN1 OUT 65 CPUGT_ISUMP OUT 65 68 CPUGT_ISNS2_N 53 68 NO_XNET_CONNECTION 2 4x 2.2uF 0402 PPBUS_HS_CPU 1 2.2UF 20% 25V X6S-CERM 2 0402 R7426 1 PVCCCGT_PH2_VCC 5% 1/16W MF-LF 402 C7427 1 2.2UF 20% 25V X6S-CERM 0402 68 2 68 65 65 IN CPUGT_FCCM IN CPUGT_PWM2 OMIT_TABLE 30 NC 31 NC 4 32 PLACE_NEAR=U7420.32:2MM 2 7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 2 1 GH 6 2 0 NC NC 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 0.00075 1% 1W MF 0612-1 PPVCCGT_CPU_PH2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V 2 1 4 3 CPUGT_ISNS2_P CPUGT_ISNS2_N 1 NOSTUFF OUT 53 68 1% 1/20W MF 201 NO_XNET_CONNECTION CPUGT_ISUMN OUT 65 68 R7424 1 2 2 1 R7422 C7428 10% 50V X7R-CERM 0402 NO_XNET_CONNECTION 1 1 1K 1% 1/20W MF 201 2 2 NOSTUFF 2 R7423 200K 1% 1/20W MF 201 200K 1% 1/20W MF 201 NO_XNET_CONNECTION CPUGT_ISEN2 OUT 65 CPUGT_ISUMP OUT 65 68 1 CPUGT_ISNS1_N 53 68 NO_XNET_CONNECTION 2 CPUGT_PHASE2 1 53 DIDT=TRUE 0.22UF 10% 25V X7R 0402 2 OUT R7421 2.2 0.001UF C7429 C CPUGT_SW2_SNUB CPUGT_BP2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 20% 25V 2 X6S-CERM 0402 2.2 R7429 1 NC 2.2UF 20% 25V X6S-CERM 2 0402 R7428 5% 1/10W MF-LF 603 1 CRITICAL R7420 2 PILA082D-SM 16 24 XW7420 PVCCCGT_PH2_AGND 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE C7423 1 2.2UF 20% 25V X6S-CERM 2 0402 0.22UH-20%-44A-0.0019OHM CPUGT_BOOT2 SM 68 2.2UF L7420 5 GL0 27 GL1 33 AGND AGND NC NC C7422 1 CRITICAL 20% 25V X6S-CERM 0402 CPUGT_SW2 8 VIN FDMF5808A BOOT 9 VIN PQFN-COMBO-THICKSTNCL PHASE 2 FCCM CRITICAL SW 1 PWM SW CPU VCCGT Phase 2 C7426 2.2UF U7420 PVCCCGT_PH2_AGND C7421 PP5V_S0 PGND PGND 2 68 PVCC 29 1 110 VCC 3 PP5V_S0 1 12 28 C 68 C7408 PPVCCGT_S0_CPU CPUGT_ISNS1_P CPUGT_ISNS1_N 1 C7420 110 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 CPUGT_PHASE1 1 33UF 1 CPUGT_SW1_SNUB 1 10% 25V X7R 0402 C7407 2.2 5% 1/10W MF-LF 603 0.22UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE PPVCCGT_CPU_PH1 0.001UF C7419 1 CRITICAL R7418 2 33UF 1% 1W MF 0612-1 2.2 5% 1/16W MF-LF 402 12 28 AGND AGND 4 32 1 0 SM 2 PILA082D-SM R7419 1 XW7410 PLACE_NEAR=U7410.32:2MM 68 PVCCCGT_PH1_AGND 68 CPUGT_BOOT1 GH 6 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE 5 GL0 27 GL1 33 30 NC 31 NC 1 CPUGT_SW1 C7406 R7410 0.22UH-20%-44A-0.0019OHM 20% 25V X6S-CERM 0402 1 0.00075 L7410 2.2UF 1 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 CRITICAL C7416 2 8 VIN FDMF5808A BOOT 9 VIN PQFN-COMBO-THICKSTNCL PHASE 2 FCCM CRITICAL SW 1 PWM SW CPU VCCGT Phase 1 109 OMIT_TABLE U7410 PVCCCGT_PH1_AGND 68 65 1 PGND PGND 5% 1/16W MF-LF 402 PVCC 29 PVCCCGT_PH1_VCC 2 VCC 3 1 C7405 2 7X 33UF B3 CRITICAL 33UF R7416 1 3 B B PART NUMBER 353S00497 QTY 2 DESCRIPTION IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5 REFERENCE DES U7410,U7420 CRITICAL BOM OPTION CRITICAL A SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=09/03/2015 PAGE TITLE GT & GTX IMVP POWER BLOCK DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=CPU & CHIPSET WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 74 OF 145 68 OF 121 SIZE D A 6 5 4 3 5V S0 - V5 109 PPBUS_HS_OTH5V 117 109 PPBUS_HS_OTH3V3 117 110 69 3.3V DSW - V6 PP5V_S4 PP5V_S5 C7600 1 1 C7601 1 2.2UF 33UF 1 C7650 1.0UF 2.2UF 20% 2 25V X6S-CERM 0402 20% 2 25V X6S-CERM 0402 20% 16V 2 TANT-POLY CASE-B3 C7602 1 1 20% 6.3V 2 TANT-POLY CASE-B1S-1 1 C7608 C7605 150UF 2.2UF 20% 2 6.3V TANT-POLY CASE-B1S-1 20% 2 25V X6S-CERM 0402 2 XW7675 SM 1 P5VS4_VFB1_R NO STUFF 1 R7674 1 NO_XNET_CONNECTION=1 1 R7677 200 1% 1/20W MF 2 201 1 5 1 C7674 0.0033UF R7672 4.87K 1 SWITCH_NODE=TRUE 31 VBST1 P5VS4_DRVH 1 DRVH1 69 73 70 OUT 1 1 10% 16V 2 X7R-CERM 0201-1 R7678 41.2K VBST2 26 P3V3S5_VBST DRVH2 24 P5VS4_CSP1 P5VS4_CSN1 7 CSP1 8 CSN1 CSP2 18 CSN2 17 R7675 3.92K BOMOPTION=NOSTUFF R7676 10K 1 PM_EN_PVXS5 DRVL2 27 SW2 25 11 MODE 9 VFB1 10 COMP1 RF 3 VFB2 16 COMP2 15 4 EN1 5 PGOOD1 EN2 21 PGOOD2 20 DIDT=TRUE C7653 2.2UF IN P3V3S5_DRVH R7669 5% 1/20W MF 2 201 73 P3V3S5_SW DIDT=TRUE P3V3S5_DRVL DIDT=TRUE P3V3S5_CSP2 P3V3S5_CSN2 R7695 1 PLACE_NEAR=U7650.28:1MM 1 R76551 200K 69 OUT 1% 1/20W MF 201 2 70 73 BOMOPTION=NOSTUFF R7696 10K 6 7 8 VSW 1 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 1 1 R7694 10 1 5% 1/10W MF-LF 603 2 P3V3S5_SNUBR MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE R7693 1.58K 2 1 1% 1/20W MF 201 NO STUFF 1 1 R7692 3.83K C7694 0.001UF 10% 2 50V X7R-CERM 0402 1% 1/20W MF 2 201 1 P3V3S5_VSW 2 P3V3S5_CSP2_R 10% 10V 2 X7R-CERM 201 (P5VP3V3_VREF2) TGR 10% 6.3V X7R 0201 1% 1/20W MF 201 2 C7699 2700PF 10% 2 10V X7R 201 PIMC063T-SM C7665 1 110 2 XW7690 NO_XNET_CONNECTION=1 C7667 117 1 150UF C7672 150UF 20% 2 6.3V TANT-POLY CASE-B1S-1 20% 2 6.3V TANT-POLY CASE-B1S-1 TG BG 20% 25V X6S-CERM 2 0402 VOUT = 3.3V 8.47A MAX OUTPUT F = 500 KHZ 1UH-20%-17A-0.01OHM NO STUFF 5 P3V3S5_COMP2_R SM 3 1 2.2UF 20% 25V X6S-CERM 2 0402 PP3V3_S5 L7660 C7663 2.2UF 20% 2 16V TANT-POLY CASE-B3 150UF C7693 0.1UF P3V3S5_EN_RCD S5_PWRGD 1 1 C7664 C7680 33UF 20% 2 16V TANT-POLY CASE-B3 VIN 1 4 P3V3S5_RF P3V3S5_VFB2 P3V3S5_COMP2 1 C7662 2 0.1UF 10% 25V X6S-CERM 2 0201 CRITICAL 33UF 20% 2 16V TANT-POLY CASE-B3 Q3D MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1% 1/20W MF 2 201 XW7650 CRITICAL 1 C7661 CRITICAL U7660 CSD58873Q3D C7671 CRITICAL 1 33UF APN: 152S1032 GATE_NODE=TRUE 3.92K 2 P3V3S5_TG MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 1 C7660 20% 2 16V TANT-POLY CASE-B3 P3V3S5_VBST_R 10% 2 10V X5R-CERM 0402 CRITICAL 1 33UF SWITCH_NODE=TRUE DIDT=TRUE 1 1% 1/20W MF 201 2 C7679 4700PF 5% 1/20W MF 201 THRM_PAD 1 P5VS4_COMP1_R C7678 270PF 13 VREG3 QFN EN 12 P5VS4_DRVL 1% 1/20W MF 2 201 DIDT=TRUE VREF2 22 29 VREG5 U7650 GND 1% 1/20W MF 201 R7685 1 2 0 30 DRVL1 P5VS4_EN_RCD P5VS4_PGOOD 1 CRITICAL 32 SW1 DIDT=TRUE 1 10% 10V CERM 2 402 P5VS4_SW DIDT=TRUE GATE_NODE=TRUE 23 P5VS4_VBST P5VS4_VFB1 P5VS4_COMP1 0.1% 1/16W MF 2 0402 B P5VP3V3_SKIPSEL DIDT=TRUE 2 5VS4_VFB1_RR 1 6 SKIPSEL1 19 SKIPSEL2 14 OCSEL DIDT=TRUE GATE_NODE=TRUE 1% 1/20W MF 201 2 NO_XNET_CONNECTION=1 P5VS4_CSP1_R 5% 1/20W MF 2 201 R7673 698 2 1 1 10% 50V CERM 2 402 SM 1 1 10% 6.3V X7R 0201 NO STUFF XW7670 5% 1/20W MF 0201 2 R7665 C7673 0.1UF MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE 2 5% 1/20W MF 201 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 P5VS4_SNUBR XW7671 1 5% 1/20W MF 0201 2 0 SWITCH_NODE=TRUE 5% 1/10W MF-LF 2 603 2 SM BG 0 4 9 20% 25V X6S-CERM 2 0402 TGR VSW PGND 150UF PLACE_NEAR=C7607.1:3MM PLACE_NEAR=L7600.1:3MM PLACE_NEAR=L7600.2:3MM 2.2UF 6 7 8 R7609 10% 2 25V X6S-CERM 0201 3 1 1 1 C7652 0.22UF 33 TG P5VS4_VSW C7607 1 C7609 0.1UF MIN_NECK_WIDTH=0.1200 1 1 1 VIN 2 MIN_LINE_WIDTH=0.2000 C7606 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 0 TPS51980A PIMA042T-SM R7651 P5VS0_VBST_R CRITICAL U7600 CSD58879Q3D L7600 Q3D 2.2UH-20%-4.5A-0.043OHM VOUT = 5V 1.58A MAX OUTPUT F = 500 KHZ R7650 SKIP_5V3V3:AUDIBLE VIN CRITICAL 1 2 PP5V_S4 1 28 69 P5VP3V3_VREF2 SKIP_5V3V3:INAUDIBLE V5SW 110 1 C7651 10UF 20% 2 10V X5R-CERM 0402-1 P5VP3V3_VREG3 P5VS0_TG 117 CRITICAL 110 VOUT = 5V CRITICAL 100MA MAX OUTPUT 10% 25V X6S 2 0402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE D PLACE_NEAR=L7660.1:3MM PLACE_NEAR=C7665.1:3MM 117 1 PLACE_NEAR=L7660.2:3MM D C 2 PGND 7 9 8 20% 2 6.3V TANT-POLY CASE-B1S-1 C7666 1 C7668 1 C7676 1 20% 6.3V 2 TANT-POLY CASE-B1S-1 20% 6.3V 2 TANT-POLY CASE-B1S-1 20% 6.3V 2 TANT-POLY CASE-B1S-1 150UF C7669 150UF 1 2.2UF 20% 25V X6S-CERM 2 0402 2 C7670 150UF NO STUFF C 1 2.2UF 20% 25V X6S-CERM 2 0402 XW7695 SM 1 P3V3S5_VFB2_R XW7691 2 SM 1 NO_XNET_CONNECTION=1 SM R76971 10 1 5% 1/20W MF 201 2 DIDT=TRUE P3V3S5_VFB2_RR C7698 330PF 2 10% 16V X7R 0201 R76981 23.2K (P5VP3V3_VREF2) 0.1% 1/16W MF 0402 2 GND_5V3V3_AGND 1 B MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V R7679 10K 0.1% 1/16W MF 2 0402 R7699 10K 0.1% 1/16W MF 0402 2 R7663 73 PM_SLP_S5_L R7664 0 1 P5VS4_EN_RCD 69 5% 1/20W MF 201 1 100 5% 1/20W MF 201 2 NO STUFF P5VS4_EN_RD 2 1 D7663 SM-201 K A RB521ZS-30 NO STUFF 1 C7654 1.0UF 10% 2 25V X6S 0402 NO STUFF R7643 73 PM_EN_PVXS5 R7644 1 100 5% 1/20W MF 201 2 A 0 1 NO STUFF P3V3S5_EN_RD 2 P3V3S5_EN_RCD 69 5% 1/20W MF 201 D7643 SM-201 K SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN A RB521ZS-30 NO STUFF PAGE TITLE 1 C7644 1.0UF 10% 2 25V X6S 0402 SYNC_DATE=12/09/2015 Power - 5V 3.3V Supply DRAWING NUMBER Apple Inc. NO STUFF 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=PLATFORM POWER WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 76 OF 145 69 OF 121 SIZE D A 8 7 6 5 4 3 2 1 73 70 BANJO - PMIC Control 73 70 1 PP3V3_PMICLDO PP3V3_S5 C7839 1 1% 1/20W MF 201 2 NOSTUFF PPBUS_PMIC E5 VINPP (OD) SYS_PWROK H11 F1 BAT1 G1 BAT2 (OD) PCH_PWROK E11 ALL_SYS_PWRGD G11 R7821 E2 ACIN PMIC_VDCSNS 1 H9 C 73 70 OUT 73 PM_PCH_PWROK OUT 12 70 115 ALL_SYS_PWRGD OUT 46 70 73 OUT 70 73 70 46 20 12 110 SMC_PMIC_INT_L 73 70 73 70 69 OUT 70 46 47 114 EC_ONOFF* K4 73 IN 73 101 IN 89 76 73 70 46 27 20 12 IN 73 72 IN 73 46 43 20 12 IN PCH_PWRBTN* K2 (OD) DPWROK K12 73 70 ACSWON* J2 BAT1SWON* F2 BAT2SWON* G2 (OD) IN 110 EC_RST* J3 GND IN 109 PM_RSMRST_L PMIC_INT* D12 NVDC* (LDO3V = 3S) 5% 1/20W MF 201 2 PM_PCH_SYS_PWROK RSMRST_L_PWRGD J11 G3 VDCSNS PP3V3_PMICLDO 73 70 0 (OD) 70 114 GND IN 89 76 73 70 46 27 20 12 IN PP3V3_PMICLDO70 MAKE_BASE=TRUE PP3V3_SUS 1 CRITICAL PM_SLP_S0_L D9 STANDBY* PP3V3_SUS PP1V8_S3 PP3V3_PMICLDO S5_PWRGD PP3V3_S0_LEFT PP1V8_S0 P5VS4_PGOOD PM_SLP_S3_L E7 K9 K8 E6 F4 E8 J10 F5 VSA VSB VSC VSD VSE VSF VSG VSH (PP) PGA D6 (PP) PGB C5 PGC C6 (PP) PGD H3 (PP) PGE C4 (PP) PGF H4 (PP) PGG F3 (OD) PGH M6 P1V8SUS_PGOOD PM_SLP_S4_L PP3V3_PMICLDO B12 C11 C12 J13 F10 J12 B10 L11 ENA ENB ENC END ENE ENF ENG ENH (OD) LVA L12 (OD) LVB L10 PM_SLP_SUS_L PM_SLP_S3_L IN CPUVR_PGOOD 70 46 20 12 IN PM_SLP_S0_L C8 RESET* 5% 1/20W MF 2 201 PM_RSMRST_L 73 70 NC P3V3SUS_PGOOD P1V8S3_EN TP_PMIC_PGC TP_PMIC_PGD TP_PMIC_PGE TP_PMIC_PGF TP_PMIC_PGG PVCCIO_EN PM_SLP_S0S3_L PM_PCH_PWROK OUT 73 OUT 74 OUT 70 OUT 70 110 PP3V3_S5 70 1 P5VS4_PGOOD 110 70 PP3V3_S0_LEFT 1UF 1 C7831 OMIT_TABLE 1UF 20% 10V X6S-CERM 2 0201 20% 2 10V X6S-CERM 0201 VDDIO0 E1 VDDIO1 M13 20% 10V X6S-CERM 2 0201 C7841 1 20% 2 10V X6S-CERM 0201 70 71 72 B 109 73 70 PP3V0_G3H GND U7800 B13 VBATTBKUP P650839A0B J1 SCLK PMIC_SLAVEADDR L3 SLAVEADDR PMIC_EN3V3SW K3 EN3V3SW 73 P5VS4_PGOOD M5 EN5VSW 73 PP5V_S4 N5 VIN5VSW PPBUS_PMIC M8 VINLDO3 PPBUS_PMIC N6 VIN R7837 1 100K 70 2 5% 1/20W MF 201 70 C7837 PLACE_NEAR=U7800.N6:2MM C7838 1 1.0UF 73 70 A 70 73 A1 NC A13 NC N1 NC N13 NC R7865 PP3V3_PMICLDO VREF1V25 B1 LDO5V N7 PP1V25_PMICVREF PP5V_PMICLDO 2 PPBUS_PMIC 70 VOLTAGE=13.1V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 70 70 71 72 PMIC_SLAVEADDR 1 PLACE_NEAR=U7800.N7:2MM C7836 1 10UF C7835 PLACE_NEAR=U7800.B1:2MM 1 10UF C7834 0.47UF 20% 6.3V 2 CERM-X6S 0402 10% 2 10V X7R 0402 PLACE_NEAR=U7800.N8:2MM 1 1 0 2 PP3V3_PMICLDO 70 73 5% 1/20W MF 201 C7833 NOSTUFF 10UF 20% 2 6.3V CERM-X6S 0402 114 101 89 76 73 70 46 27 20 12 PM_SLP_S3_L 1 R7808 5% 1/20W MF 2 201 70 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 0 5% 1/20W MF 201 70 GND PP5V_PMICLDO 1 R7864 20% 2 6.3V CERM-X6S 0402 70 73 PPBUS_G3H 70 73 100K PP3V3_PMICLDO MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V 70 71 72 PP1V25_PMICVREF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.25V SYNC_MASTER=J80_MLB PAGE TITLE PM_SLP_S0S3_L PM_SLP_S0S3_L MAKE_BASE=TRUE SYNC_DATE=12/08/2015 PMIC-1 & Power Control DRAWING NUMBER 051-00647 73 Apple Inc. 70 REVISION R 71 70 70 PVCCIO_EN PVCCIO_EN MAKE_BASE=TRUE 71 PVCCIO_EN NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=PLATFORM POWER WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 B PVCCIO_EN 71 70 109 PLACE_NEAR=U7800.N7:2MM 10% 25V 2 X6S 0402 5% 1/20W MF 2 201 LDO3V N8 CRITICAL R7807 AGND VOUT3V3SW M7 1 1.0UF 10% 25V 2 X6S 0402 GND TEMP_ALERT* L2 C1 K1 L13 D13 PLACE_NEAR=U7800.M8:2MM PP3V3_S5 F6 F7 F8 G5 G6 G7 G8 H5 H6 H7 H8 J5 J6 J7 J8 K6 K7 IN SMBUS_SMC_5_G3_SCL TRIP* H10 NC0 NC1 NC2 NC3 CRITICAL AGND1 AGND2 AGND3 AGND4 49 (OD) (10 OF 10) PBGA BI 70 1 PBGA J4 VCOMP (7 OF 10) H1 SDA ALL_SYS_PWRGD 73 70 46 70 73 100K U7800 SMBUS_SMC_5_G3_SDA 5% 1/20W MF 2 201 PM_PCH_PWROK 70 12 110 R7805 10K OMIT_TABLE P650839A0B 49 115 GND V3P3A_RTC C13 1UF 5% 1/20W MF 201 VDD5_VPROGOTP D3 C7830 1 1UF PP5V_PMICLDO R7804 5% 1/20W MF 2 201 C7880 1 2 1 10K PP3V0_G3H R7866 0 C L6 ENLVA PLACE_NEAR=U7800.C13:2MM 1 5% 1/20W MF 2 201 S5_PWRGD 73 70 69 1 PP5V_PMICLDO_R R7802 100K 5% 1/20W MF 2 201 73 PP3V3_PMICLDO 1 R7801 100K 12 70 115 73 69 109 73 70 R7810 4.7K OMIT_TABLE PP3V3_PMICLDO CPUVR_PGOOD 110 C7 SHUTDOWN* 73 70 8 (Pull up on Chipset Page) OMIT_TABLE 73 70 5% 1/20W MF 2 201 70 73 73 70 PMIC_SHUTDOWN_L 70 73 CPU_VCCST_PWRGD VCCST_PWRGD E4 101 73 12 D R7861 100K (1 OF 10) 1HZ K11 NC (OD) 1 PBGA DS3_VREN K13 NC (PP) H2 PWRBTNIN GND 73 70 CRITICAL PP3V3_PMICLDO 1M PP3V3_S0_LEFT P650839A0B (8 OF 10) R7820 1 70 U7800 PBGA D11 ACOK 110 GND VDDPG D1 GND P650839A0B 70 PMIC_SHUTDOWN_L 20% 10V 2 X6S-CERM 0201 U7800 SMC_PM_G2_EN C7840 1UF 10% 10V X6S-CERM 2 0402 73 70 73 70 70 PLACE_NEAR=U7800.L8:2MM 1 2.2UF ECVCC L1 D IN 70 110 5% 1/20W MF 2 201 PLACE_NEAR=U7800.D1:2MM CKPLUS_WAIVE=PWRTERM2GND 73 47 46 R7860 100K VDDLV L8 73 70 GND PP3V3_PMICLDO 1 78 OF 145 70 OF 121 SIZE D A 8 7 6 5 1.2V VDDQ - V10 (Banjo#1 VR4) 4 OMIT_TABLE U7800 PP5V_PMICLDO B4 VREGVR4 VBSTVR4 B3 P1V2_VBST 1 MIN_LINE_WIDTH=0.2000 D P1V2S3_ILIM_HS R7900 1 73 11.5K 5 IN D4 E3 DRVHVR4 SWVR4 DRVLVR4 DDRID DDR_VTT_CTRL A2 A3 A5 0 2 P1V2_DRVH_R P1V2_SW P1V2_DRVL_R 1 P1V2_VBST_R 2 1 VIN MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE 73 B5 C2 PGVR4 ENVR4 FBVR4+ FBVR4- (OD) R7901 1 D5 P1V2S3_FB_P P1V2S3_FB_N TG 3 2 2 0 1 1 TGR 4 VSW MIN_LINE_WIDTH=0.2000 7 5% 1/20W MF 201 BG 5 2 2 20% 25V X6S-CERM 0402 R7918 1% 1/3W MF 0306-SHORT 2 1 3 PIMC063T-SM R7917 1 D 0.005 1 P1V2_PHASE PP1V2_S3 2 4 1 PP1V2_S3_REG_R 2.2 5% 1/10W MF-LF 603 CRITICAL C7905 CRITICAL C7908 1 270UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V 2 2 1 270UF 20% 2V TANT CASE-B 20% 2V TANT CASE-B C7906 DIDT=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE 1 270UF C7917 1 0.001UF 10% 50V X7R-CERM 0402 NOSTUFF 1 51 OUT 51 OUT 20% 2V TANT CASE-B ISNS_CPUDDR_P ISNS_CPUDDR_N CRITICAL 2 117 C7913 10UF Vout = 1.2V ICCMAX = 9.01A 20% 2 2 4V X6S 1 C7907 270UF 2 74 109 CRITICAL 0402 CRITICAL P1V2_SW_SNUB P1V2_DRVL 5% 1/20W MF 2 201 0 2 R7904 2 0.47UH-20%-22A-0.0042OHM MIN_NECK_WIDTH=0.1200 NOSTUFF 5% 1/16W MF-LF 402 10 R7903 2 2.2UF L7900 DIDT=TRUE 6 8 1 A4 100K 5% 1/20W MF 201 C3 PGNDVR4 IN PVCCIO_EN PM_SLP_S4_L 20% 25V X6S-CERM 0402 C7903 2.2UF OMIT PGND OUT 2 1 1 R7906 70 20% 16V TANT-POLY CASE-B3 C7902 CRITICAL 5% 1/20W MF 201 MIN_LINE_WIDTH=0.2000 2 Check R7901 1 1 33UF R7905 20% 16V X6S-CERM 0201 DIDT=TRUE 1 Q3D MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 CRITICAL 9 1% 1/20W MF 201 IN GND PM_MEMVTT_EN DIDT=TRUE CRITICAL ILIMVR4 20% 16V TANT-POLY CASE-B3 CSD58873Q3D P1V2_DRVH 0.1UF 5% 1/20W MF 201 MIN_NECK_WIDTH=0.1200 D2 C7904 R7902 CRITICAL C7901 1 33UF U7900 PBGA 72 70 CRITICAL C7900 CRITICAL (5 OF 10) 2 PPBUS_HS_CPU 109 P650839A0B 3 C7909 C7914 270UF 20% 2V TANT CASE-B 2 1 10UF 20% 2V TANT CASE-B F = 600kHz 20% 4V X6S 2 0402 CRITICAL 2 XW7904 SM P1V2S3_FB_R_P 1 2 P1V2S3_FB_R_N 1 2 XW7903 SM C C 0.6V VTT - V13 (Banjo#1 LDO1) PP1V2_S3 CRITICAL C7935 OMIT_TABLE CRITICAL C7930 1 10UF 1 CRITICAL P650839A0B 10UF 20% 4V X6S 2 0402 PP0V6_S0_DDRVTT U7800 1 PBGA 20% 4V X6S 2 0402 (9 OF 10) A6 B6 XW7931 SM 1 2 VINLDO1_0 VINLDO1_1 VOUTLDO1_0 VOUTLDO1_1 A8 XW7930 B8 SM CRITICAL PMIC_VINLDO1S F9 CRITICAL C7931 1 15UF 2 109 CRITICAL C7932 1 15UF C7933 1 C7934 1 15UF 20% 2 2V X6S 0402 20% 2 2V X6S 0402 109 117 CRITICAL C7936 1 15UF 15UF 20% 2 2V X6S 0402 20% 2 2V X6S 0402 CRITICAL CRITICAL C7937 15UF 20% 20% 2 2V X6S 0402 2 2V X6S 0402 1 117 Vout = 0.6V ICCMAX = 0.572A VINLDO1S PGNDLDO1_0 PGNDLDO1_1 A7 B7 R7930 D8 FBLDO1 PVTT_FB 1 10 PVTT_FB_R 2 5% 1/20W MF 201 B B 0.95V VCCIO - V6 (Banjo#1 VR3) 109 71 PPBUS_HS_CPU CRITICAL CRITICAL C7968 1 C7960 PVCCIO_VBST_R OMIT_TABLE MIN_LINE_WIDTH=0.2000 1 U7800 PPBUS_HS_CPU 1 2 1 P650839A0B PBGA (4 OF 10) PMIC_VINVR3 G9 VINVR3 VBSTVR3 B11 2 PVCCIO_VBST 1 PVCCIO_ILIM_LS 2 VIN A12 A11 A9 PVCCIO_DRVH PVCCIO_SW PVCCIO_DRVL_R 3 OUT 70 IN PVCCIO_PGOOD PVCCIO_EN B9 E9 2 PGVR3 ENVR3 FBVR3+ FBVR3- C10 D7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 GATE_NODE=TRUE MIN_NECK_WIDTH=0.1200 DIDT=TRUE PVCCIO_FB_P PVCCIO_FB_N 5% 1/20W MF 201 A10 A 0 1 0 2 2 2 2.2UF 20% 25V X6S-CERM 0402 4 TGR VSW R7963 10 5% 1/20W MF 201 MIN_LINE_WIDTH=0.2000 1 PVCCIO_PHASE 2 5 BG 2 PPVCCIO_S0_CPU 109 117 PIMC063T-SM NOSTUFF C7964 R79691 10UF 2.2 5% 1/10W MF-LF 603 1 20% 4V X6S 2 0402 CRITICAL 2 PVCCIO_SW_SNUB DIDT=TRUE PVCCIO_DRVL 2 7 1UH-20%-17A-0.01OHM MIN_NECK_WIDTH=0.1200 8 5% 1/16W MF-LF 402 1 L7960 DIDT=TRUE 6 R7962 1 20% 25V X6S-CERM 0402 C7962 1 TG R7965 73 1 2.2UF CRITICAL 1 7.5K 1% 1/20W MF 201 DRVHVR3 SWVR3 DRVLVR3 C7961 Q3D 20% 16V X6S-CERM 0201 DIDT=TRUE PGNDVR3 R7961 C9 ILIMVR3HS ILIMVR3LS 2 1 CSD58873Q3D C7963 0.1UF MIN_NECK_WIDTH=0.1200 D10 20% 16V TANT-POLY CASE-B3 1 U7960 5% 1/20W MF 201 MIN_LINE_WIDTH=0.2000 CRITICAL 20% 16V TANT-POLY CASE-B3 PGND 71 DIDT=TRUE 33UF 9 109 XW7964 SM CRITICAL MIN_NECK_WIDTH=0.1200 R7964 33UF C7969 1 10% 50V X7R-CERM 0402 2 C7955 1 1 10UF 20% 4V X6S 2 0402 1 C7966 220UF 3 2 20% 2V ELEC SM-COMBO 1 C7967 220UF 3 2 C7970 Vout = 0.95V ICCMAX = 5.50A F = 500kHz 220UF 20% 2V ELEC SM-COMBO 3 2 20% 2V ELEC SM-COMBO CRITICAL 0.001UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE NOSTUFF 2 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N IN 8 IN 8 9 PMIC-1 1.2V 0.6V VCCIO DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART BOM_COST_GROUP=PLATFORM POWER WWW.AliSaler.Com 8 7 6 5 4 3 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 79 OF 145 71 OF 121 SIZE D A 8 7 6 5 1V - V11 (Banjo#1 VR1) 4 3 ROOM=BANJO C8001 1 2.2UF OMIT_TABLE PP5V_PMICLDO C8016 D 1 PBGA 1UF (2 OF 10) 20% 10V X6S-CERM 2 0201 M10 VREGVR1 VBSTVR1 2 0.1UF L9 DRVHVR1 SWVR1 DRVLVR1 ILIMVR1 N12 N11 N9 20% 0201 3 TG M12 PGVR1 ENVR1 FBVR1+ FBVR1- MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE 4 TGR VSW J9 5 1 1 R8003 10 R8002 MIN_LINE_WIDTH=0.2000 7 5% 1/20W MF 201 2 PP1V_PCH_REG_R 1% 1/2W MF 0306 2 4 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.0V PIMC063T-SM R80091 2.2 5% 1/10W MF-LF 603 PP1V0_SUS 0.003 1 P1VS4_PHASE 51 OUT 51 OUT 1 3 CRITICAL C8004 ISNS_1V0_P ISNS_1V0_N 110 117 CRITICAL C8005 1 10UF 1 1 10UF 20% 4V X6S 2 0402 2 P1VS4_SW_SNUB 5% 1/20W MF 2 201 0 2 BG D R8004 1UH-20%-17A-0.01OHM MIN_NECK_WIDTH=0.1200 8 P1VS4_FB_P P1VS4_FB_N N10 2 K10 CRITICAL L8000 DIDT=TRUE PGND M9 20% 16V TANT-POLY CASE-B3 C8006 1 220UF 20% 4V X6S 2 0402 3 C8007 1 220UF 20% 2 2V ELEC SM-COMBO 3 C8010 220UF 20% 2 2V ELEC SM-COMBO 3 20% 2 2V ELEC SM-COMBO 9 IN P1VSUS_PGOOD P3V3SUS_PGOOD PGNDVR1 73 OUT 2 CRITICAL NOSTUFF 73 2 33UF 20% 16V TANT-POLY CASE-B3 CRITICAL 1 8.45K 2 C8008 1 6 P1VS4_DRVH P1VS4_SW P1VS4_DRVL 33UF 20% 25V X6S-CERM 0402 2 C8002 CRITICAL VIN 2 16V X6S-CERM DIDT=TRUE 2.2UF 1 Q3D C8003 MIN_NECK_WIDTH=0.1200 P1VS4_ILIM_HS 1% 1/20W MF 201 P1VS4_VBST MIN_LINE_WIDTH=0.2000 CRITICAL R8000 M11 1 5% 1/20W MF 201 1 CSD58889Q3D DIDT=TRUE 0 P650839A0B 1 U8000 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 R8001 20% 25V X6S-CERM 0402 CRITICAL P1VS4_VBST_R U7800 1 1 PPBUS_G3H 109 C8000 72 71 70 2 DIDT=TRUE C8009 1 10% 50V X7R-CERM 0402 2 0.001UF NOSTUFF Vout = 1.0V ICCMAX = 4.11A F = 500kHz XW8003 SM P1VS4_FB_R_P P1VS4_FB_R_N 1 2 1 2 XW8004 SM 1.8V - V8 (Banjo#1 VR2) C C Stuff with 107S00058/107S00103 at Proto OMIT_TABLE U7800 F13 20% 25V X6S-CERM 0402 1 2.2UF 20% 25V X6S-CERM 0402 2 C8021 150UF 2 2 20% 6.3V TANT-POLY CASE-B1S-1 1 H13 1 P1V8SUS_SW 20% 2 10V X6S-CERM 0201 73 70 P1V8SUS_PGOOD PM_SLP_SUS_L OUT 73 IN E12 DIDT=TRUE R8029 SWITCH_NODE=TRUE NOSTUFF F11 PGVR2 ENVR2 FBVR2+ FBVR2- E10 P1V8SUS_FB_P P1V8SUS_FB_N 1 R8020 1 100 5% 1/20W MF 201 2 1 2 R8021 10 1 3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V 2.2 5% 1/10W MF-LF 603 G10 PP1V8_SUS_REG_R PIFE25201B-SM MIN_NECK_WIDTH=0.1200 C8025 1UF 2 MIN_LINE_WIDTH=0.2000 VREGVR2 PGNDVR2_0 2.2UF 1 E13 G13 C8020 1 PP5V_PMICLDO PGNDVR2_1 C8024 H12 CRITICAL G12 72 71 70 SWVR2_0 SWVR2_1 VINVR2_0 VINVR2_1 1% 1/3W MF 0306-SHORT 0.47UH-20%-4.0A-28MOHM (3 OF 10) F12 0.005 L8020 PBGA PP3V3_S5 R8024 APN: 152S1682 P650839A0B 110 OMIT CRITICAL 51 OUT 51 OUT 2 4 PP1V8_SUS CRITICAL 1 C8022 109 1 100UF ISNS_1V8_SUS_P ISNS_1V8_SUS_N 2 DIDT=TRUE 20% 6.3V TANT-POLY CASE-A3-LLP 117 CRITICAL C8023 CRITICAL 1 1 C8026 20UF 100UF 2 CRITICAL 20% 2 2.5V X6S-CERM 0402-1 20% 6.3V TANT-POLY CASE-A3-LLP C8027 20UF 20% 2.5V 2 X6S-CERM 0402-1 P1V8S3_SW_SNUB C8029 1 10% 50V X7R-CERM 0402 2 0.001UF NOSTUFF 5% 1/20W MF 2 201 XW8021 SM R8025 P1V8SUS_FB_R_P 1 C8028 0.01UF 1 100 2 P1V8SUS_FB_RC 1 Vout = 1.8V ICCMAX = 0.7A F = 2MHz 2 5% 1/20W MF 201 10% 10V 2 X7R 0201-1 B B P1V8SUS_FB_R_N 1 2 XW8020 SM R8050 109 PPBUS_G3H 1 0 2 5% 1/20W MF 201 OMIT_TABLE U7800 P650839A0B PBGA (6 OF 10) PPVIN_SUS_VR5_R VOLTAGE=13.1V L7 VINVR5 VBSTVR5 M3 NC CRITICAL K5 ILIMVR5HS L5 ILIMVR5LS M4 PGVR5 M2 ENVR5 FBVR5+ G4 FBVR5- L4 SYNC_MASTER=X363_ZIFENGSHEN N3 A PGNDVR5 NC DRVHVR5 M1 NC SWVR5 N2 NC DRVLVR5 N4 NC SYNC_DATE=04/14/2016 PAGE TITLE PMIC-1 1V 1.8V VCCPCH DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART BOM_COST_GROUP=PLATFORM POWER WWW.AliSaler.Com 8 7 6 5 4 3 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 80 OF 145 72 OF 121 SIZE D A 8 7 6 5 4 3 2 1 KEEP THESE RAILS ON WHEN USING XDP 110 D MAKE_BASE=TRUE XDP:YES R8110 0 1 2 5% 1/20W MF 201 C8192 PM_EN_PVXS5 PM_EN_PVXS5 PM_EN_PVXS5 PM_SLP_SUS_L MAKE_BASE=TRUE PP3V3_PMICLDO 70 OUT 69 OUT 69 MAKE_BASE=TRUE 110 OUT 72 OUT 74 PP5V_S4 P5VS4_PGOOD 70 69 PM_SLP_SUS_L PM_SLP_SUS_L PP3V3_PMICLDO 73 70 70 IN CPUVR_PGOOD 1 10% 10V 2 X5R-CERM 0201 SM PP8100 PP MAKE_BASE=TRUE PP5V_S4 70 P5VS4_PGOOD P5VS4_PGOOD 71 IN PVCCIO_PGOOD 1 46 20 12 PM_SLP_S5_L MAKE_BASE=TRUE PP8101 PP 73 18 XDP_PRESENT_L IN P2MM 70 72 OUT 70 IN P1VSUS_PGOOD 1 SM 73 70 46 43 20 12 (INV) PM_SLP_S4_L IN SOT886 3 OUT 74 OUT 74 OUT 69 73 70 GND MAKE_BASE=TRUE P3V3SUS_PGOOD MAKE_BASE=TRUE GND IN P1V8SUS_PGOOD 1 1 SM 5% 1/20W MF 2 201 2 71 110 P3V3SUS_PGOOD PP3V3_SUS 73 18 XDP:YES C8194 72 1 0.1UF 10% 10V X5R-CERM 2 0201 XDP:YES U8194 74AUP1T97GM 5 1 S3 Enables MAKE_BASE=TRUE OUT 71 73 70 70 46 ALL_SYS_PWRGD MAKE_BASE=TRUE ALL_SYS_PWRGD IN XDP_PRESENT_L IN PM_SLP_S0S3_L (INV) SOT886 6 4 XDP:NO 1 C S0 Enables 114 101 89 76 70 46 27 20 12 PM_SLP_S3_L MAKE_BASE=TRUE PM_SLP_S3_L PM_SLP_S3_L PM_SLP_S3_L 70 69 73 OUT 74 OUT 74 115 46 18 12 S5_PWRGD PM_RSMRST_L MAKE_BASE=TRUE S5_PWRGD 46 PM_RSMRST_L 70 MAKE_BASE=TRUE R8194 100K R8195 0 73 XDP:YES 65 1 (S3# AND S0# OR XDP) P1VS0SW_EN_RC 3 2 73 70 46 43 20 12 73 18 PM_SLP_S4_L R8192 100K 5% 1/20W MF 201 PP8106 PP 0 D 74 OUT XDP:YES 1 R8193 70 PM_SLP_S4_L P1V0S3_EN 4 PP8102 PP (S4# OR XDP) 74AUP1T97GM 6 XDP:NO 72 70 PM_SLP_S5_L PM_SLP_S5_L PM_SLP_S5_L U8192 SM P2MM S4 Enables XDP:YES P2MM SUS Enables 70 12 0.1UF P2MM MAKE_BASE=TRUE 1 5 1 SMC_PM_G2_EN 70 47 46 PP3V3_SUS 2 S5 Enables 73 18 5% 1/20W MF 2 201 2 5% 1/20W MF 201 C J80G specific GND 73 70 S0i Enables MAKE_BASE=TRUE 114 73 P1VS0SW_EN_RC MAKE_BASE=TRUE P1VS0SW_EN_RC OUT 74 73 70 73 70 IN PM_SLP_S0S3_L MAKE_BASE=TRUE PM_SLP_S0S3_L OUT 73 46 12 CPUVR_PGOOD MAKE_BASE=TRUE CPUVR_PGOOD CPUVR_PGOOD PM_PCH_SYS_PWROK PM_PCH_SYS_PWROK MAKE_BASE=TRUE 70 65 74 110 20 14 12 PP3V3_S0 R8199 1 10K 109 PP1V8_S0 PP1V8_S0 OUT 1% 1/20W MF 201 70 B 114 73 46 12 B 2 PM_PCH_SYS_PWROK R8163 73 PM_SLP_S3_L 0 1 R8164 1 100 5% 1/20W MF 201 2 NO STUFF P5VS0_EN_RD 2 OUT 74 5% 1/20W MF 201 D8163 SM-201 K A RB521ZS-30 NO STUFF A P5VS0_EN 1 C8154 1.0UF 10% 2 25V X6S 0402 NO STUFF SYNC_MASTER=J80_SILUCHEN_MLB_BAFFIN PAGE TITLE SYNC_DATE=12/08/2015 PMIC-1 Aliases & TPs DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=PLATFORM POWER WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 81 OF 145 73 OF 121 SIZE D A 8 7 6 5 3.3V SUS Switch SLG5AP1569V PP3V3_S5 STDFN 2 1 PM_SLP_SUS_L IN 3 VOUT PP3V3_SUS 110 GND D 1UF U8200 U8212 10% 10V 2 X5R 402-1 EDP: 416mA Part 1.0UF 20% 6.3V X5R 0201-1 1 SLG5AP1569V 73 Load Switch Type 2 R(on) @ 3.6V 34 mOhm Typ 46 mOhm Max Current 1A Max PM_SLP_S5_L IN VDD SOT23-5-COMBO 1 VIN VOUT 5 3 EN PP1V8_S4 EDP: 0.020 A NC1 4 NC GND 1 U8295 109 C8295 1 20% 6.3V X5R 0201-1 2 1.0UF 1 LP5907MFX-1.8V 4 C8200 1 1 PP3V3_S5 C8211 ON 2 3.3V S0 Switch LEFT SLG5AP1445V C8212 1UF 74 10% 2 10V X5R 402-1 2 73 110 CRITICAL VIN 3 1.8V S4 LDO U8200 110 4 74 73 IN P3V3S0_CAP 7 PM_SLP_S3_L 2 CAP TDFN8 CRITICAL ON C82961 D 3 S 5 PP3V3_S5 PP3V3_S0_LEFT EDP: 2.031A 91 110 GND 8 4700PF 10% 10V 2 X7R 201 3.3V S4 Switch U8203 TPS22969DNY P3V3S4_EN_R 0.1UF C8203 1 PP3V3_S5 1.0UF Part TPS22969 Type Load Switch R(on) @ 3.6V 4.4 MOHM TYP 6.6 MOHM MAX Current 3.3V S0 Switch C C8205 110 U8205 S3_STATE:YES C8214 1 1 C8215 70 1 IN 0 SLG5AP1453V P1V8S3_RAMP 7 P1V8S3_EN 2 TDFN CAP ON D 3 S 5 74 73 IN PM_SLP_S3_L 2 TDFN8 CRITICAL CAP ON C82061 D 3 S 5 PP3V3_S5 PP3V3_S0 EDP: 2.031A 91 110 5V S0 Switch PP5V_S4 1 U8205 Part SLG5AP1445V Type Load Switch R(on) @ 3.6V 7.8 MOHM TYP 8.5 MOHM MAX Current 4A MAX K C8207 B P5VS0_FET_RAMP 7 CAP P5VS0_EN 2 ON TDFN CRITICAL 4700PF D 3 S 5 C8218 1 PP1V8_S3 EDP: 0.550 A EDP: 1.6mA C8219 117 73 1 IN PM_SLP_S3_L 7 CAP 2 ON TDFN 5.3A Max D 3 S 5 PP1V0_S3 3 PP1V8_SUS 109 S 5 PP1V8_S0 109 110 EDP: 0.240 A 1 Part SLG5AP1453V C8286 0.1UF P1V0S0SW_RAMP 1 Type Load Switch R(on) 7.8 mOhm Typ 9.6 mOhm Max R(on) @ 5.3A 7.8 mOhm Typ 9.6 mOhm Max 5% 2 25V C0G 0201 Current 5.3A Max VIN 1 SMC_SENSOR_PWR_EN ON PP3V3_SUS C8287 73 IN P1VS0SW_EN_RC 100PF PP1V2_S3 C8221 BOMOPTION=VCCPLLOC:S0G R8210 VOUT 3 PP3V3_S4SW_SNS_FET_R VOLTAGE=3.3V MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1200 C8210 1 20% 6.3V X5R 0201-1 2 4 GND 0 1 2 PP3V3_S4SW_SNS 110 5% 1/16W MF-LF 402 C8222 Type Load Switch R(on) @ 3.6V 34 mOhm Typ 46 mOhm Max Current 1A Max IN 7 CAP 2 ON STDFN D 3 WWW.AliSaler.Com Current 2.5A Max 1 VDD S 5 SLG5AP1453V P1V2S0SW_RAMP CAP PM_SLP_S0S3_L 2 ON TDFN GND 8 D 3 S 5 5 110 U8285 Part SLG5AP1635V Type Load Switch R(on) @ 25C 20 mOhm Typ 28 mOhm Max Current 2.5A Max Ton Total R8220 5% 1/16W MF-LF 2 402 110 PP1V0_S0SW EDP: 0.04 A 109 0 U8220 7 BOMOPTION=VCCPLLOC:S0G 39us max @ 1V PP1V0_S3 39us max @ 1V BOMOPTION=VCCPLLOC:S3 PP1V2_S0SW EDP: 0.260 A 109 SYNC_MASTER=J80_SAKKOC_MLB_BAFFIN SYNC_DATE=12/11/2015 PAGE TITLE BOMOPTION=VCCPLLOC:S0G Power FETs U8220 6 20 mOhm Typ 28 mOhm Max GND Part SLG5AP1453V Type Load Switch R(on) @ 5.3A 7.8 mOhm Typ 9.6 mOhm Max Current 5.3A Max DRAWING NUMBER Apple Inc. 4 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=PLATFORM POWER 7 R(on) @ 25C U8285 1 10% 10V 2 X5R 402-1 10% 10V 2 X7R 201 U8210 SLGAP1569V 73 1 1UF 4700PF 1.0UF Part 1 Load Switch SLG5AP1635V 1.2V S0 SW Switch STDFN Type B 5.3A CRITICAL SLG5AP1635V VDD 10% 2 16V X5R-CERM 0201 Load Switch 2 Part PP3V3_S5 EDP: 0.140 A Type SLG5AP1569V 110 U8283 U8218 110 C 5% 1/20W MF 201 2 GND SLG5AP1453V PP3V3_S5 8 ON 5% 2 25V C0G 0201 D GND 8 10% 10V 2 X7R 201 U8210 A Current 2 STDFN U8218 4700PF 3.3V Sensor Switch IN 7.8 mOhm Typ 9.6 mOhm Max CAP 100PF Part Current 48 R(on) @ 5.3A 7 S3_STATE:NO 0 SLG5AP1635V 1.0V S0 SW Switch U8209 110 Load Switch R8282 1 SLG5AP1453V P1V8S0_RAMP 110 Type P1V0S3_EN IN 110 VDD 10% 10V 2 X5R 402-1 PP5V_S0 SLG5AP1453V 73 C8284 PP1V0_SUS U8283 109 P1V0S3_RAMP S3_STATE:YES VDD 10% 2 16V X5R-CERM 0201 1 1UF GND 8 10% 10V 2 X7R 201 0.1UF PMEG3010EB/S500 Part C8283 Ton Total C8208 SLG5AP1453V 1 4A MAX S3_STATE:YES 1 A PP3V3_S5 10% 2 16V X5R-CERM 0201 U8209 IN Current PP3V3_S5 1.8V S0 Switch 0.1UF VDD 110 1 110 1 73 7.8 MOHM TYP 8.5 MOHM MAX 117 S3_STATE:YES 74 110 10% 10V 2 X7R 201 110 71 109 U8215 GND 8 4700PF PP1V2_S3 D8216 SOD523 GND 8 10% 10V 2 X7R 201 A PMEG3010EB/S500 5% 1/20W MF 201 2 U8215 4700PF 2 R8281 1 S3_STATE:YES VDD 10% 10V 2 X5R 402-1 S3_STATE:YES K S3_STATE:NO SLG5AP1445V 7 R(on) @ 3.6V 1.0V S3 Switch D8215 SOD523 6A MAX 1 20% 6.3V X5R 0201-1 VDD 109 PP3V3_S5 1UF 1.0UF 1 PP1V8_SUS 74 110 20% 6.3V X5R 0201-1 2 1.8V S3 Switch U8203 GND EPAD NOSTUFF P3V3S0_CAP Load Switch 3 VBIAS 1 10% 16V X5R-CERM 2 0201 74 Type 117 1 C8209 SLG5AP1445V 8 5% 1/20W MF 201 110 Part 1 2 PP3V3_S4 EDP: 3.55A U8295 8 0 PM_SLP_S5_L 1 9 IN VOUT 6 VIN CRITICAL 4 ON R8209 73 DFN8 1 2 PP3V3_S5 74 5 110 D 74 110 1 82 OF 145 74 OF 121 SIZE D A 8 7 6 5 4 3 2 1 Page Notes Power aliases required by this page: - =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT) - =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT) PPVOUT_S0_LCDBKLT PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:5MM CRITICAL 1 CRITICAL POWER GOING TO LCD BACKLIGHT 3AMP-32V 75 FDC638APZ_SBMS001 0.025 F8400 1 Q8400 R8400 CRITICAL 2 1 3 PPVIN_S0SW_LCDBKLT_FET VOLTAGE=12.6V 1% 1W MF 0612-1 2 4 75 1 PLACE_NEAR=Q8401.5:3MM 1 NOSTUFF R8401 1 80.6K 10% 16V X7R-1 0201 1% 1/16W MF-LF 2 402 3 2 ISNS_LCDBKLT_N 10% 50V CERM 402 1 R8402 110 1 PP5V_S0 75 2 63.4K R8444 1% 1/16W MF-LF 2 402 1 1 0 C8410 1 10% 25V X6S-CERM 0603 2 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 2 402 75 C8440 1 1 GND_BKLT_SGND 2 10% 100V X5R 1206 D PLACE_NEAR=D8410.K:5MM R8442 BKLT_EN_R 2 NO STUFF 5% 1/20W MF 0201 1 C8442 VOLTAGE=59V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.3000 LP8548B1SQ_-03 11 9 10 SD VSENSE_N VSENSE_P 19 SENSE_OUT 17 12 EN PWM_KEYB 15 16 SCL SDA SW SW FB GD 5% 25V NPO-C0G 0201 2 1 21 4 2 C8468 2.2UF 10% 100V X5R 1206 PLACE_NEAR=D8410.K:5MM 2.2UF 10% 100V X5R 1206 2 10% 100V X5R 1206 2 376S0678 1 C8470 2.2UF 2 1 10% 100V X5R 1206 R8431 CRITICAL CRITICAL 1 C8471 1 2.2UF 2 10% 100V X5R 1206 2.2UF 2 10% 100V X5R 1206 C8472 CRITICAL 1 2.2UF 10% 100V X5R 1206 2 C8473 2.2UF 2 10% 100V X5R 1206 R8431: 28.7K 1% 1/16W MF-LF 2 402 28.7K FOR J80 DISPLAY. PWRPK-1212-8 R8433 1 1 2 3 R8432 1 150K PLACE_NEAR=U8400.1:5MM 1% 1/16W MF-LF 2 402 C NOSTUFF C8430 100PF 2 5% 100V C0G-CERM 0603 LCDBKLT_SW VOUT = 52V TYP, 59V MAX ISET_KEYB 20 NC FS = 625KHZ TYP (+/- 7%) KEYB1 13 KEYB2 14 NC NC SW2 6 FB2 8 NC NC (IPU) C8469 PLACE_NEAR=D8410.K:5MM LCDBKLT_FB LCDBKLT_FET_DRV (IPU) 1 PLACE_NEAR=D8410.K:7MM CRITICAL SI7812DN 5% 1/16W MF-LF 2 402 SWITCH_NODE=TRUE QFN IOUT = 0.135A TYP, 0.15A MAX MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V GATE_NODE=TRUE DIDT=TRUE CRITICAL BKLT_PWM_KEYB 1 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V MAKE_BASE=TRUE 4 LCDBKLT_FET_DRV_R DIDT=TRUE 10% 100V X5R 1206 C8467 PLACE_NEAR=D8410.K:6MM 1 Q8401 75 2.2UF 1 SM 10 GND_SW GND_SW GND_SW2 GNDD GNDA GND_BKLT_SGND 75 1 33PF 2 PLACE_NEAR=L8410.1:5MM Ben IC - V3 C8466 CRITICAL CRITICAL XW8410 CRITICAL THRM PAD 24 23 7 3 22 1 10% 25V X5R 402 PLACE_NEAR=L8410.1:5MM 10% 10V X5R 402-1 MIN_LINE_WIDTH=0.1200 MIN_NECK_WIDTH=0.6000 PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW 0 PLACE_NEAR=L8410.1:5MM U8400 BKLT_SENSE_OUT 2 PLACE_NEAR=U8400.18:5MM 1M BKLT_SD 10% 25V X6S-CERM 0603 C8465 1 2 0.1UF 4.7UF CRITICAL PLACE_NEAR=D8410.K:4MM C8412 5 R8440 5% 1/20W MF 201 2 1 C8441 1UF 2 C8411 SANDWICH C8210 C8410 AND C8211 C8411 VDDD 5 C 10% 10V X5R 402-1 2 PMEG10020ELR-DFLS2100 152S00253 PLACEMENT_NOTE: PP5V_S0_BKLT_A PP5V_S0_BKLT_D 1UF PLACE_NEAR=U8400.5:5MM 75 1 2 R8445 0 75 75 2 25 1 EDP_BKLT_EN 2.2UF 10% 100V X5R 1206 2 C8464 PLACE_NEAR=D8410.K:5MM CRITICAL 1 2.2UF SOD123-COMBO A K PIME062D-SM CRITICAL 4.7UF IN C8463 PLACE_NEAR=D8410.K:5MM CRITICAL 1 D8410 15UH-20%-1.9A-0.24OHM 0.001UF LCDBKLT_EN_L 89 2 CRITICAL 1 2.2UF 10% 100V X5R 1206 PLACE_NEAR=D8410.K:8MM CRITICAL L8410 C8401 VDDA 18 OUT C8462 1 2.2UF 10% 100V X5R 1206 PLACE_NEAR=D8410.K:6MM PLACE_NEAR=L8410.2:3MM CRITICAL CRITICAL 50 2 CRITICAL 1 C8400 ISNS_LCDBKLT_P C8461 2.2UF 10% 100V X5R 1206 371S00077 2 VOLTAGE=12.6V 2 OUT 4 CRITICAL 1 PPVIN_S0SW_LCDBKLT MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V MAKE_BASE=TRUE 6 5 PPVIN_S0SW_LCDBKLT_R 1000PF 50 75 SSOT6-HF 107S00034 0603 2 LCDBKLT_TB_XWR 740S0159 PPBUS_G3H CRITICAL PPVIN_SW_LCDBKLT_SW D C8460 2.2UF SENSOR ON PAGE 54 USES R8400 TO MEASURE THE PLACE_NEAR=D8410.K:6MM CRITICAL 1 116 PLACE_NEAR=D8410.K:7MM PLACE_NEAR=D8410.K:6MM 109 75 76 114 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V MAKE_BASE=TRUE R8447 10K 5% 1/20W MF 201 2 B B XW8400 SM 1 2 GND_BKLT_SGND 110 75 75 MIN_LINE_WIDTH=0.1500 MIN_NECK_WIDTH=0.2000 VOLTAGE=0V PP5V_S0 1 R8452 1.8K 5% 1/20W MF 2 201 1 R8453 1.8K 5% 1/20W MF 2 201 PLACE_NEAR=U8400.15:10MM R8450 111 IN I2C_BKLT_SCL 1 R8451 111 BI I2C_BKLT_SDA 1 0 2 0 5% 1/20W MF 0201 2 BKLT_SCL BKLT_SDA 5% 1/20W MF 0201 I2C ID DEDICATED.ONLY CONNECTS TO JERRY PLACE_NEAR=U8400.16:10MM PBUS LINE WIDTHS A PP5V_S0_BKLT_A MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V LCD BKLT LINE WIDTHS PPVIN_S0SW_LCDBKLT_FET 75 75 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V PPVIN_S0SW_LCDBKLT_R PP5V_S0_BKLT_D MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V 75 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V 75 LCDBKLT_FET_DRV_R MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V GATE_NODE=TRUE 75 DIDT=TRUE PPVIN_SW_LCDBKLT_SW MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V SWITCH_NODE=TRUE PPVOUT_S0_LCDBKLT MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=59V PPVIN_S0SW_LCDBKLT_FET 75 SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/03/2015 PAGE TITLE LCD Backlight Driver DIDT=TRUE 75 76 114 116 DRAWING NUMBER Apple Inc. 75 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 051-00647 REVISION R PPVIN_S0SW_LCDBKLT 75 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12.6V 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 84 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART BOM_COST_GROUP=DISPLAY WWW.AliSaler.Com 8 7 6 5 4 3 SHEET 75 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 LCD PANEL INTERFACE (eDP) + Camera (MIPI) PP5V_S0 CRITICAL 1 110 VDD U8500 D SLG5AP1443V LCD_PWR_SLEW R8515 1 150K 7 PANEL_P5V_EN 2 CAP 2 ON 5% 1/20W MF 201 1 2 D 3 S 5 VOLTAGE=5V PP5V_S0SW_LCD 76 114 8 GND R8517 330 TDFN PANEL_P5V_EN_D 5% 201 1/20W MF D8517 SC2 1 A 10% 2 10V X5R-CERM 0201 1 C8515 1 0.1UF K DSF01S30SCAP C8511 0.1UF C8509 10% 2 10V X5R-CERM 0201 2200PF 10% 2 10V X7R-CERM 0201 1 C8512 PP3V3_S5 110 PPVOUT_S0_LCDBKLT 10UF 20% 2 10V X5R-CERM 0402-7 CRITICAL 1 D Stuff with 107S0276/107S0020 at Proto U8501 LCD_PWR_SLEW_3V3 R8516 200K PANEL_P3V3_EN 2 2 1% 1/20W MF 201 1 1 330 2 1 PANEL_P3V3_EN_D K 5% 201 1/20W MF S 5 NO_XNET_CONNECTION=1 1% 1/3W MF 0306-SHORT VOLTAGE=3.3V PP3V3_S0SW_LCD_R C8513 1 3 1.0UF 10% 2 10V X7R-CERM 0201 A C8510 1 2200PF 10% 2 6.3V CERM-X5R 0201 D8518 SC2 D 2 20% 6.3V X5R 0201-1 52 ISNS_LCDPANEL_P 52 ISNS_LCDPANEL_N 47 46 PANEL_FET_EN_DLY 116 1 BUF_SMC_RESET_L DFR_DISP_PWR_EN DFR_DISP_SMC_RST_L VDD 89 76 114 101 89 73 70 46 27 20 12 114 U8510 BYPASS 76 64 57 48 29 IN EDP_PANEL_PWR_EN 2 EDP_PANEL_PWR_EN U8510PANEL_FET_EN_DLY 3 IN PM_SLP_S3_L 4 PM_SLP_S3_L 8 IN SMC_RESET_L 9 X604_DISP_PWR_EN 6 X604_DISP_SMC_RST_L PANEL_FET_EN_DLY NC0 NC1 76 1 2 5% 1/20W MF 0201 NO_STUFF OUT 46 48 76 OUT 42 OUT 42 76 114 76 76 BUF_EDP_PANEL_PWR_EN 76 76 114 76 76 10 76 5 11 76 NC_U8510_5 NC_U8510_11 7 BUF_EDP_PANEL_PWR_EN 114 76 GND R8591 0 76 75 76 PANEL_PWR_EN_CONN STQFN 12 SMC_RESET_INPUT_L SMC_RESET_OUTPUT_L R8590 2 114 SLG4AP4998 NO_STUFF 5% 1/20W MF 0201 NO_STUFF J8500 PPVOUT_S0_LCDBKLT 38 BI 38 BI IN SMC_RESET_L 1 5% MF 0 2 1/20W 0201 38 BUF_SMC_RESET_L OUT EDP_INT_ML_N<0> EDP_INT_ML_P<0> EDP_INT_ML_N<1> EDP_INT_ML_P<1> EDP_INT_ML_N<2> EDP_INT_ML_P<2> EDP_INT_ML_N<3> EDP_INT_ML_P<3> MIPI_CLK_CONN_N MIPI_CLK_CONN_P IN IN SIGNAL 114 114 114 114 111 111 111 PP3V3_S0 NO_XNET_CONNECTION=1 NO_STUFF 1 76 EDP_INT_ML_P<0> EDP_INT_ML_P<0> 76 IN EDP_INT_ML_N<0> EDP_INT_ML_N<0> 76 5% 1/20W MF 2 201 MAKE_BASE=TRUE MAKE_BASE=TRUE IN EDP_INT_ML_P<1> EDP_INT_ML_P<1> 76 EDP_INT_ML_N<1> 76 MAKE_BASE=TRUE 114 111 IN EDP_INT_ML_N<1> 114 111 IN EDP_INT_ML_P<2> EDP_INT_ML_P<2> 76 114 111 IN EDP_INT_ML_N<2> EDP_INT_ML_N<2> 76 114 111 IN EDP_INT_ML_P<3> EDP_INT_ML_P<3> 76 114 111 IN EDP_INT_ML_N<3> EDP_INT_ML_N<3> 76 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE R8505 114 114 76 89 89 OUT DP_INT_HPD 1 5% MF 0 2 1/20W 0201 DP_INT_HPD_R 76 114 76 EDP_AUXCH_C_N 114 76 EDP_AUXCH_C_P LCD_FSS R8504 1 R85011 5% 1/20W MF 201 2 5% 1/20W MF 201 2 100K NO_XNET_CONNECTION=1 NO_STUFF 100K 1 R8502 MAKE_BASE=TRUE 113 111 BI EDP_AUXCH_C_P EDP_AUXCH_C_P 76 114 113 111 BI EDP_AUXCH_C_N EDP_AUXCH_C_N 76 114 1M 5% 1/20W MF 2 201 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 BUF_EDP_PANEL_PWR_EN DP_INT_HPD_R LCD_FSS LCD_IRQ_L 45 76 76 89 114 OUT 15 114 OUT 48 114 IN 20 114 I2C_BKLT_SDA I2C_BKLT_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL BI IN BI IN I2C_ALS_SDA I2C_ALS_SCL I2C_CAM_SCL I2C_CAM_SDA 46 GND 76 114 BKLT_PWM_TCON2MLB BKLT_PWM_MLB2TCON PWR PP5V_S0SW_LCD IN R8503 1M 76 114 C 4 47 110 PP3V3_S0SW_LCD 44 3 46 48 76 B A PWR 1 MIPI_DATA_CONN_N MIPI_DATA_CONN_P 76 114 38 EDP_AUXCH_C_N EDP_AUXCH_C_P R8592 76 64 57 48 29 114 43 PP3V3_G3H CRITICAL 1 NO_XNET_CONNECTION=1 F-ST-SM 109 EDP_PANEL_PWR_EN 76 114 20759-042E-02 C 89 76 PP3V3_S0SW_LCD MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V DSF01S30SCAP 76 0 2 4 1 10% 100V 2 X7R-CERM 0603 0.005 3 GND C8516 0.47UF R8518 ON 8 1 CAP TDFN 116 1000PF R8520 SLG5AP1443V 7 C8500 OMIT VDD 75 76 114 BI 111 114 114 49 114 49 114 42 114 IN 42 114 IN 37 38 114 BI PP5V_S0_ALSCAM_F 111 37 38 114 38 114 B 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN PAGE TITLE SYNC_DATE=12/03/2015 eDP Display Connector DRAWING NUMBER Apple Inc. LCD Panel HPD, FSS & AUX strapping 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=DISPLAY WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 85 OF 145 76 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D PLACE AC COUPLING CAPS NEAR U8605 IN LINEAR PATTERN, SAME SIDE GND_VOID=TRUE C8650 113 87 IN PCIE_SSD_R2D_LB_P<0> GND_VOID=TRUE C8651 113 87 IN PCIE_SSD_R2D_LB_N<0> GND_VOID=TRUE C8652 14 IN PCIE_SSD_R2D_C_P<1> GND_VOID=TRUE C8653 113 14 IN PCIE_SSD_R2D_C_N<1> GND_VOID=TRUE C8654 14 IN PCIE_SSD_R2D_C_P<2> GND_VOID=TRUE C8655 113 C 14 14 IN IN PCIE_SSD_R2D_C_N<2> GND_VOID=TRUE PCIE_SSD_R2D_C_P<3> C8656 0201 GND_VOID=TRUE 113 14 IN PCIE_SSD_R2D_C_N<3> C8657 0201 0.22UF GND_VOID=TRUE 1 2 20% 6.3V X6S-CERM 0201 0.22UF GND_VOID=TRUE 1 2 20% 6.3V OMIT_TABLE X6S-CERM 2 20% 6.3V X6S-CERM 2 20% 6.3V X6S-CERM 2 20% 6.3V X6S-CERM 2 20% 6.3V X6S-CERM 2 20% 6.3V 113 113 PCIE_SSD_R2D_P<1> PCIE_SSD_R2D_N<1> V2 RXDP1 U2 RXDN1 113 PCIE_SSD_R2D_P<2> PCIE_SSD_R2D_N<2> AB2 RXDP2 AA2 RXDN2 TXDP2 AC1 TXDN2 AB1 PCIE_SSD_R2D_P<3> PCIE_SSD_R2D_N<3> AD4 RXDP3 AD3 RXDN3 TXDP3 AE5 TXDN3 AE4 0201 113 X6S-CERM 2 20% 6.3V X6S-CERM PLACE_NEAR=U8605.AD10:3MM R86021 240 2 87 PCIE_CLK100M_SSD_LB_P IN 1 R8600 49.9 1 240 2 1 R8601 MF-LF 113 87 PLACE_NEAR=U8605.AE9:3MM PLACE_NEAR=U8605.M1:3MM 2 77 PLACE_NEAR=U8605.N1:3MM 2 77 83 82 77 P18 T18 V13 V15 SSD_FVREF0 PCIE_CLK100M_SSD_LB_N 240 2 1/20W 1% MF 201 84 78 77 84 81 80 84 81 80 115 B 87 IN 84 IN 114 80 IN 114 80 IN 114 80 OUT 114 80 IN GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8_SPICLK GP9_SPICS GP10_SPIDI_DO GP11_SPIDO_DI GP12 GP13 GP14 GP15 GP16_DAT GP17_CLK GP18_URX GP19_UTX GP20 GP21 GP22 GP23 VREF_NAND D5 FSOURCE0 E3 FSOURCE1 PLACE_NEAR=U8605.J18:3MM R86041 CLKREQ H3 AD14 VREF_CA A16 VREF_DQ SSD_VREF_CA SSD_VREF_DQ J18 SZQ G11 SCKEIN SSD_SZQ PP1V2_SSD_DRAM_L12 D9 H6 I2C_CLK I2C_DAT SSD_RESET_LB_L D6 PERST SSD_RESET_B_L L2 RESET* SSD_JTAG_TCK SSD_JTAG_TDI SSD_JTAG_TDO SSD_JTAG_TMS D4 E4 C2 G1 TCK TDI TDO TMS SSD_I2C_CLK SSD_I2C_DAT PWRCON0 PWRCON1 PWRCON2 PWRCON3 PWRCON4 C9 C6 A6 B8 B9 D8 D3 G7 G8 C5 B7 B10 H4 F2 D7 C7 G2 J2 G4 G3 F8 B5 C3 D2 J4 K2 L3 K3 K1 VDDPLL_01 P6 PLL_REF_RETURN_01 R4 84 78 PP1V2_SSD_DRAM 114 1 1 R8630 4.7K 1 C8630 0.1UF 10% 2 16V CER 0201 1 R8631 4.7K 1% 1/20W MF 2 201 1 R8632 SSD_VREF_DQ 1 C8631 0.1UF 10% 16V 2 CER 0201 1 R8633 4.7K 1% 1/20W MF 2 201 VDDPLL_23 U6 PLL_REF_RETURN_23 AA4 R8620 4.7K 1% 1/20W MF 2 201 1% 1/20W MF 2 201 77 REXT P4 PP1V8_SSD_FMC 4.7K 1% 1/20W MF 2 201 SSD_VREF_CA 84 83 82 81 80 78 15 TSEN_TEST_OUT G17 SSD_FVREF0 77 1 C8620 0.1UF 10% 2 16V CER 0201 1 113 113 113 113 113 113 113 PCIE_SSD_D2R_C_P<0> PCIE_SSD_D2R_C_N<0> 0201 6.3V X6S-CERM 20% 6.3V X6S-CERM C8641 2 0201 20% 6.3V X6S-CERM 20% 6.3V X6S-CERM 20% 6.3V X6S-CERM 20% SSD_CLKIN SSD_CLKOUT 6.3V 77 113 20% OUT 6.3V X6S-CERM PCIE_SSD_D2R_LB_N<0> OUT 87 113 PCIE_SSD_D2R_P<1> OUT 14 113 PCIE_SSD_D2R_N<1> OUT 14 113 PCIE_SSD_D2R_P<2> OUT 14 113 PCIE_SSD_D2R_N<2> OUT 14 113 PCIE_SSD_D2R_P<3> OUT 14 113 PCIE_SSD_D2R_N<3> OUT 14 113 0.22UF 1 C8644 2 0201 0.22UF 1 C8645 2 0201 0.22UF 1 C8646 2 0201 GND_VOID=TRUE 77 113 SSD_CLKREQ_LB_L X6S-CERM C8643 2 0201 GND_VOID=TRUE 87 113 0.22UF 1 GND_VOID=TRUE PCIE_SSD_D2R_C_P<3> PCIE_SSD_D2R_C_N<3> C8642 2 0201 GND_VOID=TRUE PCIE_SSD_D2R_C_P<2> PCIE_SSD_D2R_C_N<2> OUT 0.22UF 1 GND_VOID=TRUE PCIE_SSD_D2R_C_P<1> PCIE_SSD_D2R_C_N<1> PCIE_SSD_D2R_LB_P<0> 0.22UF 1 GND_VOID=TRUE NC CLKOSCI B3 CLKOSCO A3 G14 SVREF1 F10 SVREF3 SSD_SVREF1 77 1% 1/16W 402 IN BOOTSEL C10 AD10 ZQ0 AE9 ZQ1 1/20W 1% MF 201 113 TXDP1 W1 TXDN1 V1 CRITICAL F1 SUSCLK SSD_ZQ0 SSD_ZQ1 R8603 1/16W 1% MF-LF 402 49.9 SYM 3 OF 5 J3 TESTMOD NC 1/20W 1% MF 201 113 BGA M1 REFCLKP N1 REFCLKN 0.22UF GND_VOID=TRUE 1 TXDP0 T1 TXDN0 R1 PCIE_SSD_R2D_P<0> PCIE_SSD_R2D_N<0> 0201 0.22UF GND_VOID=TRUE 1 20% R2 RXDP0 P2 RXDN0 0201 0.22UF GND_VOID=TRUE 1 X6S-CERM C8640 2 KG10000C2E-A200TAB 0201 0.22UF GND_VOID=TRUE 1 6.3V 1 GND_VOID=TRUE U8605 0.22UF GND_VOID=TRUE 1 20% 0201 0.22UF GND_VOID=TRUE 1 GND_VOID=TRUE 0.22UF 1 C8647 2 0201 0.22UF 87 115 SSD_GP0 SSD_GP1 80 R8660 80 113 NC NC NC NC NC NC C SSD_CLKIN 77 1M 1 SSD_CLKOUT 2 1% 1/20W MF 201 1 77 113 R8661 240 Y8660 2.00X1.60-SM SSD_GP8 SSD_GP9 SSD_GP10 NC 80 NC 114 80 80 25MHZ-30PPM-6PF-120OHM PLACE_NEAR=Y8660.1:1MM 80 1 10PF 80 SSD_GP12 SSD_PGOOD_L 1 C8660 5% 2 50V C0G 0201 80 SSD_PGOOD_L MAKE_BASE=TRUE SSD_BOOT_LB_L MAKE_BASE=TRUE SSD_DEBUG_I2C_DAT MAKE_BASE=TRUE SSD_DEBUG_I2C_CLK MAKE_BASE=TRUE SMC_OOB1_R2D_L IN SMC_OOB1_D2R_L OUT SSD_GP20 80 1 SSD_GP21 80 SSD_GP22 100K 80 1% SSD_GP23 80 1/20W SSD_BOOT_LB_L SSD_DEBUG_I2C_DAT SSD_DEBUG_I2C_CLK IN 84 114 IN 87 114 3 2 NC PLACE_NEAR=U8605.B3:4MM 1% 1/20W MF 201 2PLACE_NEAR=Y8660.3:1MM 4 PLACE_NEAR=U8605.A3:4MM NC SSD_CLKOUT_R 1 NC NC 113 PLACE_NEAR=Y8660.3:1MM C8661 10PF 5% 2 50V C0G 0201 115 86 114 BI OUT 86 114 48 80 114 48 80 114 B R8640 SSD_PWRCON0 SSD_PWRCON1 SSD_PWRCON2 SSD_PWRCON3 MF 2 201 OUT 84 OUT 84 OUT 84 OUT 84 84 80 78 R8680 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1200 1 C8680 1 0.22UF R86701 C8681 1UF 10% 16V 2 CERM 402 10% 2 6.3V X7R 0402 1 PP1V8_SSD_PLL23 PPVSS_SSD_PLL23 1UF 10% 2 6.3V X7R 0402 1K 1 C8683 0.22UF NC 10% 16V 2 CERM 402 77 82 83 1 C8684 1UF 10% 2 6.3V X7R 0402 2 1% 1/16W MF-LF 402 C8682 PLACE_NEAR=U8605.R4:3MM 2 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2500 1/16W 1% MF-LF 402 MIN_NECK_WIDTH=0.1200 PLACE_NEAR=U8605.U6:5MM PREXT_SSD 10 1 PLACE_NEAR=U8605.P6:5MM NC PP1V8_SSD_PLL01 PPVSS_SSD_PLL01 PP1V8_SSD_DRAM R8681 1 1 C8685 1UF 10 2 1% 1/16W MF-LF 402 10% 2 6.3V X7R 0402 PLL RETURN CONNECTS TO GND ON PACKAGE R8621 4.7K 1% 1/20W MF 2 201 84 78 77 PP1V2_SSD_DRAM_L12 1 A R8610 4.7K 1% 1/20W MF 2 201 SYNC_MASTER=X363_JSAMUELS PAGE TITLE POLARIS_CONTROLLER DRAWING NUMBER SSD_SVREF1 1 C8610 0.1UF 10% 2 16V CER 0201 1 SYNC_DATE=04/01/2016 051-00647 77 Apple Inc. R8611 4.7K REVISION R 1% 1/20W MF 2 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 86 OF 145 77 OF 121 SIZE D A 8 7 6 5 4 3 2 1 PP1V1_SSD_PCIE 84 78 L8700 FERR-30-OHM-2.2A-0.035-OHM 78 1 PP1V1_SSD_LVDS 2 0402 VOLTAGE=1.1V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 1 C8700 0.1UF 10% 2 6.3V X7R 0402 D C8701 1 1UF 10% 2 16V CER 0201 D OMIT_TABLE U8605 PP1V8_SSD_DRAM 84 80 78 77 PP1V2_SSD_DRAM 84 78 77 PP3V3_SSD_LIM 86 84 53 1 C8796 1 12PF C8797 C8795 3.0PF 5% 2 25V NP0-C0G 0201 1 0.22UF +/-0.1PF 2 25V NP0-C0G 0201 20% 6.3V 2 X5R 0201 B4 B23 AD8 AD21 A4 A8 A15 A23 C1 J1 AE8 AE14 AE18 AE21 E2 E1 C 114 84 PP1V0_SSD_CORE C8746 1 1 12PF 1 3.0PF 5% 2 25V NP0-C0G 0201 84 78 C8745 C8744 1 1UF +/-0.1PF 2 25V NP0-C0G 0201 C8743 1 1UF 10% 2 6.3V X7R 0402 C8742 10% 6.3V 2 X7R 0402 10% 2 16V CER 0201 C8758 1 12PF C8757 1 3.0PF C8756 1UF 10% 2 6.3V X7R 0402 +/-0.1PF 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 1 C8755 1UF 10% 2 6.3V X7R 0402 L8760 FERR-30-OHM-2.2A-0.035-OHM C8740 0.1UF 10% 2 16V CER 0201 1 PP1V0_SSD_CORE_L12 1 C8754 1UF 10% 2 6.3V X7R 0402 1 C8753 0.1UF 10% 2 16V CER 0201 NOSTUFF 1 C8752 0.1UF 10% 2 16V CER 0201 2 1 C8761 1UF 1 C8751 0.1UF 10% 2 16V CER 0201 1 C8750 0.1UF 10% 2 16V CER 0201 C8774 1 12PF C8773 3.0PF 5% 2 25V NP0-C0G 0201 C8772 1 1UF C8771 0.22UF 10% 2 16V CERM 402 10% 2 6.3V X7R 0402 +/-0.1PF 2 25V NP0-C0G 0201 1 1 VDD10_SRAM VDD18_PLL0 VDD18_PLL1 VDD18_PLL2 VDD18_PLL3 10% 2 16V CER 0201 1 PP1V8_SSD_OSC VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 C877B 1 12PF C877A 1 3.0PF 1UF +/-0.1PF 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 C8779 10% 2 6.3V X7R 0402 114 PP1V8_SSD_DRAM 1 C8778 1UF 10% 2 6.3V X7R 0402 84 83 82 81 80 78 77 15 1 C8777 1UF 10% 6.3V 2 X7R 0402 1 C8776 1 0.1UF 1 C8716 1 1UF C8791 1UF 10% 6.3V 2 X7R 0402 1 C8790 0.1UF 10% 2 16V CER 0201 10% 2 6.3V X7R 0402 C 84 78 PP1V8_SSD_OSC M6 M7 K6 K7 PP1V8_SSD_DRAM_L12 1 78 PP1V8_SSD_PLL0 PP1V8_SSD_PLL1 PP1V8_SSD_PLL2 PP1V8_SSD_PLL3 C870C 1 12PF 78 +/-0.1PF 25V 2 NP0-C0G 0201 78 FERR-30-OHM-2.2A-0.035-OHM 1 C8721 1UF 10% 6.3V 2 X7R 0402 1 C8720 0.1UF 10% 2 16V CER 0201 77 78 84 L8725 FERR-30-OHM-2.2A-0.035-OHM PP1V1_SSD_PCIE 1 C8702 0.1UF 10% 2 16V CER 0201 1 C8703 0.1UF 10% 2 16V CER 0201 1 C8704 1UF 10% 2 6.3V X7R 0402 1 C8705 78 78 84 1 PP1V8_SSD_PLL1 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 1UF 1 C8726 1UF 1 C8725 0.1UF 10% 2 16V CER 0201 10% 6.3V 2 X7R 0402 10% 2 6.3V X7R 0402 2 0402 NC NC B L8730 PP1V2_SSD_DRAM FERR-30-OHM-2.2A-0.035-OHM 77 78 84 78 1 PP1V8_SSD_PLL2 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 2 0402 1 C8731 1UF 1 C8730 0.1UF 10% 2 16V CER 0201 10% 6.3V 2 X7R 0402 L8735 FERR-30-OHM-2.2A-0.035-OHM 78 1 PP1V8_SSD_PLL3 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 2 0402 1 C8736 1UF 1 C8735 0.1UF 10% 2 16V CER 0201 10% 2 16V CER 0201 84 83 82 PP1V8_SSD_FMC PP3V3_SSD_NAND SYNC_MASTER=X363_JSAMUELS C8784 1UF 10% 6.3V 2 X7R 0402 2 0402 15 77 78 80 81 82 83 84 114 PP1V2_SSD_DRAM 1 PP1V8_SSD_PLL0 78 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 78 PP1V8_SSD_FMC L8720 3.0PF 5% 25V 2 NP0-C0G 0201 78 C870D 0.1UF 10% 2 16V CER 0201 1 1UF C8715 C8775 1 1 2 0402 10% 6.3V 2 X7R 0402 1 84 80 78 77 0.1UF 15 77 78 80 81 82 83 84 114 PP1V2_SSD_DRAM A C8711 1 1UF 10% 2 6.3V X7R 0402 78 A5 A7 A9 A11 A14 A17 A19 A22 C25 D1 D25 H1 H25 VDDQ C8710 L8715 VDDIO_SENSE_01 T4 VDDIO_SENSE_23 AB4 VDD12_DDR 1 FERR-30-OHM-2.2A-0.035-OHM VDDIO_23_0 U8 VDDIO_23_1 V8 VDD12_CKE 2 0402 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 P8 R8 VDDIO_01 1 PP1V8_SSD_LVDS 78 PP1V8_SSD_FMC AE10 AE13 AE15 AE19 VDDCA F11 FERR-30-OHM-2.2A-0.035-OHM 78 84 PP1V8_SSD_LVDS VDD18_TS G16 VDD10_LOG PP1V2_SSD_DRAM 10% 16V 2 CER 0201 T7 VDD18_OSC F4 84 78 77 0.1UF PP1V8_SSD_DRAM_L12 F17 F20 J20 K18 L18 N18 N20 R18 U18 V10 V12 V14 V16 V18 Y12 Y18 Y20 VDD10_ALV VDD11_LVDS L8710 77 78 80 84 78 VDD33_UART R7 C8770 PP1V8_SSD_DRAM F6 G6 VDD18_NAND VDD33_ALV33 PP1V1_SSD_LVDS PP1V2_SSD_DRAM_L12 CRITICAL VDD2 78 G9 G13 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 VDD18_ALV18 VDD18_LVDS VDD10_PLL PP1V2_SSD_DRAM_L12 1 H17 K9 K11 K13 K15 K17 M11 M15 M17 P11 P15 P17 T11 T13 T15 T17 K4 L4 M4 VDD18_GPIO K8 0.1UF 84 78 77 U10 VDD1 PP1V0_SSD_PLL C8760 10% 2 16V CER 0201 10% 2 6.3V X7R 0402 B 1 VOLTAGE=1.0V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 0402 84 78 77 1 PP1V0_SSD_CORE_L12 1 84 78 77 C8741 0.1UF 10% 2 16V CER 0201 NOSTUFF 84 78 1 0.1UF M9 N10 P9 R10 T9 BGA SYM 4 OF 5 PP1V8_SSD_DRAM 84 80 78 77 KG10000C2E-A200TAB 10% 6.3V 2 X7R 0402 1 C8783 1UF 10% 6.3V 2 X7R 0402 1 C8782 1UF 10% 2 6.3V X7R 0402 1 C8781 0.22UF 10% 2 16V CERM 402 1 C870A 12PF C8780 5% 2 25V NP0-C0G 0201 0.1UF 10% 2 16V CER 0201 1 SYNC_DATE=05/18/2016 PAGE TITLE C870B POLARIS POWER 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=SSD WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 87 OF 145 78 OF 121 SIZE D A 8 7 6 5 4 3 2 1 OMIT_TABLE U8605 KG10000C2E-A200TAB A1 A2 A10 A24 A25 B1 B2 B6 B12 B14 B21 B24 B25 C4 C8 C14 C16 C18 C20 D10 D12 D15 D23 E25 F7 F9 F14 G10 G15 G19 G22 G24 H2 J6 J7 J8 J10 J12 J14 J16 K19 K23 K25 L6 L7 L8 L10 L12 L14 L16 M3 M8 M18 N16 N23 N25 R12 R14 R16 R19 R24 U12 U14 U16 U23 V9 V11 V19 V25 W10 W14 W17 Y23 AA25 AB16 AB20 AB23 AC9 AC13 AD11 AD17 AD22 AD24 AD25 AE24 AE25 D C B A BGA SYM 5 OF 5 CRITICAL VSSIO VSSI L1 M2 N2 N3 N4 N6 N7 N8 P1 P3 R3 R6 T2 T3 T6 T8 U1 U3 U4 U7 V3 V4 V6 W2 W3 W4 W8 Y1 Y2 Y3 Y4 AA1 AA3 AB3 AB5 AC2 AC3 AC4 AC5 AD1 AD2 AD5 AD6 AE1 AE2 AE3 AE6 AE7 VSS18_OSC F3 VSS_LVDS P7 V7 D C B SYNC_MASTER=X363_JSAMUELS SYNC_DATE=04/01/2016 PAGE TITLE PAGE_TITLE=POLARIS GND DRAWING NUMBER Apple Inc. 051-00647 REVISION R 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 88 OF 145 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 79 OF 121 IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 1 SIZE D A 8 7 6 5 4 3 2 1 SSD RELATED BOM Groups TABLE_BOMGROUP_HEAD D BOM GROUP BOM OPTIONS SSD_CONFIG:256GB SSD_GPIO9,NAND_TYPE:256GB,SSD_CTRL_TYPE:4GBIT SSD_CONFIG:512GB SSD_GPIO8,NAND_TYPE:512GB,SSD_CTRL_TYPE:4GBIT SSD_CONFIG:1TB NAND_TYPE:1TB,SSD_CTRL_TYPE:8GBIT SSD_CONFIG:2TB SSD_GPIO10,NAND_TYPE:2TB,SSD_CTRL_TYPE:8GBIT TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM R8926 77 SSD_GP0 1 0 D 2 SATA/NVME_L SELECT 5% 1/20W MF 201 NOSTUFF 77 SSD_GP1 NAND Parts PART NUMBER 1 DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 335S00149 4 NAND,1Z,64GBM,TOGG DDR2,64G,SS,BGA 168 U9100,U9110,U9200,U9210 CRITICAL NAND_TYPE:256GB 335S00204 4 NAND,V3,128GBM,TOGG DDR2,256G,SSBGA 168 U9100,U9110,U9200,U9210 CRITICAL NAND_TYPE:512GB 335S00205 4 NAND,V3,256GBM,TOGG DDR2,256G,SS,BGA 168 U9100,U9110,U9200,U9210 CRITICAL NAND_TYPE:1TB 335S00219 4 NAND,V3,512GBM,TOGG DDR2,256G,SS,BGA 168 U9100,U9110,U9200,U9210 CRITICAL NAND_TYPE:2TB SSD Controller Parts R8927 0 QTY 2 PART NUMBER ROM CODE DEBUG 5% 1/20W MF 201 QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 339S00154 1 POP,POLARIS+4GBIT,SSD CTRL,A2,BGA516 U8605 CRITICAL SSD_CTRL_TYPE:4GBIT 339S00155 1 POP,POLARIS+8GBIT,SSD CTRL,A2,BGA516 U8605 CRITICAL SSD_CTRL_TYPE:8GBIT J8900 BOMOPTION=SSD_DEBUG 14-5843-12-022-829+ M-ST-SM C 84 78 77 114 PP1V8_SSD_DRAM 114 77 OUT 114 77 OUT 114 77 OUT 114 77 IN SSD_JTAG_TMS SSD_JTAG_TCK SSD_JTAG_TDI SSD_JTAG_TDO 103 86 IN SSD_DEBUG_I2C_CLK_CONN 1 2 3 4 5 6 GND TMS TCK TDI TDO MCTP_CLK VDD GP15 GP12 URX UTX MCTP_DAT 12 11 10 9 8 7 PP1V8_SSD_FMC 15 77 78 81 82 83 84 114 SSD_BOOT_LB_L SSD_GP12 SMC_OOB1_R2D_L SMC_OOB1_D2R_L OUT OUT SSD_DEBUG_I2C_DAT_CONN 77 114 C 77 OUT 48 77 114 OUT 48 77 114 86 103 BI 114 GND 1 R8975 0 5% 1/20W MF 2 201 NOSTUFF 13 14 15 16 R8940 84 81 77 SSD_I2C_CLK 4.7K 1 2 1% 1/20W MF 201 NOSTUFF 77 SSD_GP22 R8964 1 0 R8941 2 84 81 77 5% 1/20W MF 201 NOSTUFF 77 SSD_GP23 0 4.7K 1 2 1% 1/20W MF 201 FORM FACTOR ID: TURNKIT=11 R8967 1 SSD_I2C_DAT Internal pullup on GP22,GP23 2 SSD CONFIGURATIONS 5% 1/20W MF 201 SSD_GPIO10 R8928 77 SSD_GP10 1 0 5% 1/20W MF 201 B NAND APN CAPACITY CONTROLLER APN R8980/GPIO8 R8981/GPIO9 R8928/GPIO10 2 128 GB - - STUFF-0 STUFF-0 STUFF-0 NOSTUFF-1 STUFF-0 NOSTUFF-1 B SSD_GPIO8 77 SSD_PGOOD_L NOSTUFF R8980 R8929 1 0 2 77 PMIC PGOOD SSD_GP8 1 0 77 SSD_GP20 R8981 R8920 1 0 77 2 5% 1/20W MF 201 NOSTUFF 77 SSD_GP21 SSD_GP9 1 0 512 GB 335S00204 339S00154 (A2 4GB DRAM) STUFF-0 NOSTUFF-1 NOSTUFF-1 1 TB 335S00205 339S00155 (A2 8GB DRAM) NOSTUFF-1 NOSTUFF-1 NOSTUFF-1 2 TB 335S00219 339S00155 (A2 8GB DRAM) NOSTUFF-1 STUFF-0 2 5% 1/20W MF 201 DEBUG 339S00154 (A2 4GB DRAM) SSD DENSITY SSD_GPIO9 NOSTUFF 335S00149 2 5% 1/20W MF 201 5% 1/20W MF 201 256 GB NOSTUFF-1 R8960 1 0 2 5% 1/20W MF 201 A SYNC_MASTER=X363_JSAMUELS SYNC_DATE=04/01/2016 PAGE TITLE Connector DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=SSD WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 1 89 OF 145 80 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D 84 83 82 81 80 78 77 15 114 PP1V8_SSD_FMC 1 84 83 82 81 80 78 77 15 PP1V8_SSD_FMC 1 C9000 C9010 0.1UF 0.1UF 10% 2 16V CER 0201 10% 2 16V CER 0201 PLACE NEAR NAND U9100 on BOTTOM side 8 8 PLACE NEAR CONTROLLER on TOP side VCC VCC U9010 U9000 CAT34TS00 CAT34TS00 C 1 A0 2 A1 3 A2 ADDR: B'0011 000(R/W) 84 81 80 77 84 81 80 77 BI IN SSD_I2C_DAT SSD_I2C_CLK TDFN CRITICAL 5 SDA ADDR: B'0011 001(R/W) EVENT* 7 84 81 80 77 BI NC 84 81 80 77 6 SCL IN SSD_I2C_DAT 5 SDA SSD_I2C_CLK 6 SCL CRITICAL EVENT* VSS EPAD 84 83 82 81 80 78 77 15 7 NC EPAD 9 4 114 C TDFN 4 VSS 1 A0 2 A1 3 A2 9 114 PP1V8_SSD_FMC 1 C9030 0.1UF 10% 2 16V CER 0201 8 PLACE NEAR NAND U9200 on BOTTOM side B B VCC U9030 CAT34TS00 84 81 80 77 BI SSD_I2C_DAT 5 SDA 84 81 80 77 IN SSD_I2C_CLK 6 SCL TDFN CRITICAL EVENT* 4 VSS 7 NC EPAD 9 1 A0 2 A1 3 A2 ADDR: B'0011 011(R/W) A SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE PAGE_TITLE=TEMP SENSORS DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 90 OF 145 81 OF 121 SIZE D A 8 7 6 5 4 114 84 83 82 81 80 78 77 15 3 C9160 1 3.0PF 84 83 82 81 80 78 77 15 PP1V8_SSD_FMC 84 83 82 78 1 C9157 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 12PF 5% 2 25V NP0-C0G 0201 1 C9101 0.1UF 10% 16V 2 CER 0201 1 C9102 1 0.1UF 3.0PF 10% 16V 2 CER 0201 +/-0.1PF 2 25V NP0-C0G 0201 +/-0.1PF 25V 2 NP0-C0G 0201 1 C9150 12PF 5% 2 25V NP0-C0G 0201 1 C9100 4.7UF 84 83 82 20% 2 10V X5R-CERM 0402 1 C9152 VCC BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 113 C 85 85 BI BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI C9111 0.1UF 10% 16V 2 CER 0201 10% 16V 2 CER 0201 C9153 PP12V_SSD_VPP 12PF 1 5% 2 25V NP0-C0G 0201 12PF 5% 2 25V NP0-C0G 0201 P10 N11 M10 L9 P5 N4 M5 L6 SSD_NAND_FA_DQ0 SSD_NAND_FA_DQ1 SSD_NAND_FA_DQ2 SSD_NAND_FA_DQ3 SSD_NAND_FA_DQ4 SSD_NAND_FA_DQ5 SSD_NAND_FA_DQ6 SSD_NAND_FA_DQ7 C5 D4 E5 F6 C10 D11 E10 F9 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B A NC NC A1 A11 A12 A13 A14 A2 A3 A4 B1 B13 B14 B2 C1 C14 D1 D14 G13 G2 G4 G9 H10 H13 H2 H4 J11 J13 J2 J5 K11 K13 K2 K6 N1 N14 P1 P14 R1 R13 R14 R2 T1 T11 T12 T13 T14 T2 T3 T4 CE0_0* CE1_0* CE2_0* CE3_0* OMIT_TABLE U9100 NAND-MLC-V3-CS-2TB-HDP K9UUGY8S7M-1CK0TP1 BGA CRITICAL DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 DQ6_1 DQ7_1 113 +/-0.1PF 2 25V NP0-C0G 0201 VPP VCCQ DQ0_0 DQ1_0 DQ2_0 DQ3_0 DQ4_0 DQ5_0 DQ6_0 DQ7_0 VCC C9158 3.0PF K3 J3 K5 K4 CLE0 ALE0 WE0* K10 K9 J9 RE_0 RE_0* N6 P6 SSD_NAND_FC_CE_B0_L SSD_NAND_FC_CE_B1_L SSD_NAND_FC_CE_B2_L SSD_NAND_FC_CE_B3_L SSD_NAND_FC_CLE SSD_NAND_FC_ALE SSD_NAND_FC_WE_L N9 P9 WP0* J10 R/B0_0* R/B1_0* G3 H3 CE0_1* CE1_1* CE2_1* CE3_1* G12 H12 G10 G11 SSD_NAND_FA_RE_P SSD_NAND_FA_RE_N 114 R/B0_1* R/B1_1* VREF F11 L4 RESET0* RESET1* J6 H9 IN 85 85 85 85 IN 85 IN 85 BI 85 113 BI 85 113 SSD_NAND_FA_DQS_P SSD_NAND_FA_DQS_N 4.7K RFU BI 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 2 1% 1/20W MF NOSTUFF 201 PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 BI BI 85 113 85 113 R9101 SSD_NAND_FA_RDY 1 4.7K 2 1% 1/20W MF 201 NC F12 F3 F4 L11 L12 L3 85 113 PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 1 SSD_NAND_FA_CE_B0_L SSD_NAND_FA_CE_B1_L SSD_NAND_FA_CE_B2_L SSD_NAND_FA_CE_B3_L D9 C9 K12 J12 85 SSD_NAND_FC_RDY RE_1 RE_1* H5 IN NOSTUFF SSD_FVREF0 SSD_NAND_FC_RESET_L SSD_NAND_FA_RESET_L 1 IN 85 IN 85 NC NC NC NC NC NC C9103 0.1UF 10% 2 16V CER 0201 BI 113 R9100 SSD_NAND_FA_CLE SSD_NAND_FA_ALE SSD_NAND_FA_WE_L WP1* 85 IN SSD_NAND_FC_DQS_P SSD_NAND_FC_DQS_N G5 G6 H6 D6 C6 IN IN SSD_NAND_FC_RE_P SSD_NAND_FC_RE_N CLE1 ALE1 WE1* DQS1 DQS1* 85 IN 114 DQS0 DQS0* IN 85 77 82 83 C9155 SSD_NAND_FB_DQ0 SSD_NAND_FB_DQ1 SSD_NAND_FB_DQ2 SSD_NAND_FB_DQ3 SSD_NAND_FB_DQ4 SSD_NAND_FB_DQ5 SSD_NAND_FB_DQ6 SSD_NAND_FB_DQ7 P10 N11 M10 L9 P5 N4 M5 L6 DQ0_0 DQ1_0 DQ2_0 DQ3_0 DQ4_0 DQ5_0 DQ6_0 DQ7_0 SSD_NAND_FD_DQ0 SSD_NAND_FD_DQ1 SSD_NAND_FD_DQ2 SSD_NAND_FD_DQ3 SSD_NAND_FD_DQ4 SSD_NAND_FD_DQ5 SSD_NAND_FD_DQ6 SSD_NAND_FD_DQ7 C5 D4 E5 F6 C10 D11 E10 F9 DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 DQ6_1 DQ7_1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC A1 A11 A12 A13 A14 A2 A3 A4 B1 B13 B14 B2 C1 C14 D1 D14 G13 G2 G4 G9 H10 H13 H2 H4 J11 J13 J2 J5 K11 K13 K2 K6 N1 N14 P1 P14 R1 R13 R14 R2 T1 T11 T12 T13 T14 T2 T3 T4 VCCQ U9110 NAND-MLC-V3-CS-2TB-HDP K9UUGY8S7M-1CK0TP1 BGA CRITICAL C9161 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 D VPP CE0_0* CE1_0* CE2_0* CE3_0* OMIT_TABLE 1 K3 J3 K5 K4 SSD_NAND_FB_CE_B0_L SSD_NAND_FB_CE_B1_L SSD_NAND_FB_CE_B2_L SSD_NAND_FB_CE_B3_L CLE0 ALE0 WE0* K10 SSD_NAND_FB_CLE K9 SSD_NAND_FB_ALE J9 SSD_NAND_FB_WE_L RE_0 RE_0* N6 P6 DQS0 DQS0* N9 P9 WP0* J10 R/B0_0* R/B1_0* G3 H3 CE0_1* CE1_1* CE2_1* CE3_1* G12 H12 G10 G11 SSD_NAND_FD_CE_B0_L SSD_NAND_FD_CE_B1_L SSD_NAND_FD_CE_B2_L SSD_NAND_FD_CE_B3_L CLE1 ALE1 WE1* G5 G6 H6 SSD_NAND_FD_CLE SSD_NAND_FD_ALE SSD_NAND_FD_WE_L RE_1 RE_1* D9 C9 SSD_NAND_FD_RE_P SSD_NAND_FD_RE_N DQS1 DQS1* D6 C6 WP1* H5 SSD_NAND_FB_RE_P SSD_NAND_FB_RE_N 114 SSD_NAND_FB_DQS_P SSD_NAND_FB_DQS_N IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 BI 85 113 BI 85 113 R9110 SSD_NAND_FB_RDY K12 J12 VREF F11 L4 RESET0* RESET1* J6 H9 SSD_NAND_FD_DQS_P SSD_NAND_FD_DQS_N 4.7K 1 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 114 R/B0_1* R/B1_1* RFU 2 1% 1/20W MF 201 NOSTUFF C PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 BI 85 113 BI 85 113 R9111 SSD_NAND_FD_RDY 1 4.7K 2 1% NOSTUFF 1/20W MF 201 NC F12 F3 F4 L11 L12 L3 PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 SSD_FVREF0 SSD_NAND_FB_RESET_L SSD_NAND_FD_RESET_L 1 IN 85 IN 85 77 82 83 C9112 0.1UF 10% 2 16V CER 0201 B NC NC NC NC NC NC NU VSS B10 B3 B5 C11 C12 C3 C4 D13 D2 D5 E11 E12 E13 E2 E3 E9 F5 H11 J4 L10 M12 M13 M2 M3 M4 M6 N10 N13 N2 P11 P12 P3 P4 R10 R12 R5 85 SSD_NAND_FC_DQ0 SSD_NAND_FC_DQ1 SSD_NAND_FC_DQ2 SSD_NAND_FC_DQ3 SSD_NAND_FC_DQ4 SSD_NAND_FC_DQ5 SSD_NAND_FC_DQ6 SSD_NAND_FC_DQ7 1 B12 R3 B11 B4 C13 C2 D10 D12 D3 E4 E6 F10 L5 M11 M9 N12 N3 N5 P13 P2 R11 R4 B6 B9 F13 F2 L13 L2 R6 R9 5% 2 25V NP0-C0G 0201 113 0.1UF 84 83 82 PP12V_SSD_VPP 12PF BI 1 B12 R3 C9156 3.0PF 85 1 C9110 PP3V3_SSD_NAND 1 113 C9159 5% 2 25V NP0-C0G 0201 1 B11 B4 C13 C2 D10 D12 D3 E4 E6 F10 L5 M11 M9 N12 N3 N5 P13 P2 R11 R4 84 83 82 78 C9151 12PF +/-0.1PF 2 25V NP0-C0G 0201 PP3V3_SSD_NAND C9154 B6 B9 F13 F2 L13 L2 R6 R9 D 1 1 PP1V8_SSD_FMC 1 114 2 SYNC_MASTER=X363_JSAMUELS SYNC_DATE=08/09/2016 PAGE TITLE NU NAND 1/2 DRAWING NUMBER VSS B10 B3 B5 C11 C12 C3 C4 D13 D2 D5 E11 E12 E13 E2 E3 E9 F5 H11 J4 L10 M12 M13 M2 M3 M4 M6 N10 N13 N2 P11 P12 P3 P4 R10 R12 R5 Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 91 OF 145 82 OF 121 SIZE D A 7 6 5 4 114 3 C9260 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 1 C9254 12PF 5% 2 25V NP0-C0G 0201 1 C9210 0.1UF 10% 16V 2 CER 0201 1 C9211 0.1UF 10% 16V 2 CER 0201 PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 84 83 82 3.0PF D +/-0.1PF 2 25V NP0-C0G 0201 C9251 12PF 5% 25V 2 NP0-C0G 0201 1 C9201 0.1UF 10% 16V 2 CER 0201 1 C9202 84 83 82 78 10% 2 16V CER 0201 1 +/-0.1PF 2 25V NP0-C0G 0201 84 83 82 3.0PF 1 C9250 20% 2 10V X5R-CERM 0402 5% 2 25V NP0-C0G 0201 1 12PF 5% 25V 2 NP0-C0G 0201 VCC 85 BI 113 85 BI 113 85 BI 113 85 BI 113 BI 113 85 BI 113 85 BI 113 C 85 113 113 85 85 BI BI 85 BI 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI P10 N11 M10 L9 P5 N4 M5 L6 SSD_NAND_FE_DQ0 SSD_NAND_FE_DQ1 SSD_NAND_FE_DQ2 SSD_NAND_FE_DQ3 SSD_NAND_FE_DQ4 SSD_NAND_FE_DQ5 SSD_NAND_FE_DQ6 SSD_NAND_FE_DQ7 C5 D4 E5 F6 C10 D11 E10 F9 SSD_NAND_FG_DQ0 SSD_NAND_FG_DQ1 SSD_NAND_FG_DQ2 SSD_NAND_FG_DQ3 SSD_NAND_FG_DQ4 SSD_NAND_FG_DQ5 SSD_NAND_FG_DQ6 SSD_NAND_FG_DQ7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B A NC NC A1 A11 A12 A13 A14 A2 A3 A4 B1 B13 B14 B2 C1 C14 D1 D14 G13 G2 G4 G9 H10 H13 H2 H4 J11 J13 J2 J5 K11 K13 K2 K6 N1 N14 P1 P14 R1 R13 R14 R2 T1 T11 T12 T13 T14 T2 T3 T4 DQ0_0 DQ1_0 DQ2_0 DQ3_0 DQ4_0 DQ5_0 DQ6_0 DQ7_0 CE0_0* CE1_0* CE2_0* CE3_0* OMIT_TABLE U9200 NAND-MLC-V3-CS-2TB-HDP K9UUGY8S7M-1CK0TP1 CLE0 ALE0 WE0* BGA CRITICAL DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 DQ6_1 DQ7_1 1 VCC C9258 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 VPP VCCQ 5% 25V 2 NP0-C0G 0201 5% 2 25V NP0-C0G 0201 K3 J3 K5 K4 K10 K9 J9 RE_0 RE_0* N6 P6 DQS0 DQS0* N9 P9 SSD_NAND_FE_CE_B0_L SSD_NAND_FE_CE_B1_L SSD_NAND_FE_CE_B2_L SSD_NAND_FE_CE_B3_L SSD_NAND_FE_CLE SSD_NAND_FE_ALE SSD_NAND_FE_WE_L 114 WP0* J10 R/B0_0* R/B1_0* G3 H3 CE0_1* CE1_1* CE2_1* CE3_1* CLE1 ALE1 WE1* G12 H12 G10 G11 G5 G6 H6 85 IN 85 IN 85 IN 85 IN 85 85 IN 85 IN 85 BI 85 113 BI 85 113 SSD_NAND_FG_CE_B0_L SSD_NAND_FG_CE_B1_L SSD_NAND_FG_CE_B2_L SSD_NAND_FG_CE_B3_L SSD_NAND_FG_CLE SSD_NAND_FG_ALE SSD_NAND_FG_WE_L SSD_NAND_FG_RE_P SSD_NAND_FG_RE_N DQS1 DQS1* D6 C6 SSD_NAND_FG_DQS_P SSD_NAND_FG_DQS_N 4.7K 1 RESET0* RESET1* RFU 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI 113 85 BI IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 2 1% NOSTUFF 1/20W MF 201 BI 85 113 BI 85 113 81 80 78 77 15 114 84 83 82 PP1V8_SSD_FMC H5 R9201 K12 J12 SSD_NAND_FG_RDY 1 F11 L4 J6 H9 F12 F3 F4 L11 L12 L3 4.7K 2 1% 1/20W NOSTUFF MF 201 NC VREF 113 PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 SSD_NAND_FE_RDY D9 C9 R/B0_1* R/B1_1* IN 85 R9200 RE_1 RE_1* WP1* 85 IN SSD_NAND_FE_RE_P SSD_NAND_FE_RE_N SSD_NAND_FE_DQS_P SSD_NAND_FE_DQS_N IN 113 SSD_FVREF0 SSD_NAND_FE_RESET_L SSD_NAND_FG_RESET_L 1 IN 85 IN 85 C9203 0.1UF 10% 2 16V CER 0201 NC NC NC NC NC NC 77 82 83 BI SSD_NAND_FF_DQ0 SSD_NAND_FF_DQ1 SSD_NAND_FF_DQ2 SSD_NAND_FF_DQ3 SSD_NAND_FF_DQ4 SSD_NAND_FF_DQ5 SSD_NAND_FF_DQ6 SSD_NAND_FF_DQ7 P10 N11 M10 L9 P5 N4 M5 L6 DQ0_0 DQ1_0 DQ2_0 DQ3_0 DQ4_0 DQ5_0 DQ6_0 DQ7_0 SSD_NAND_FH_DQ0 SSD_NAND_FH_DQ1 SSD_NAND_FH_DQ2 SSD_NAND_FH_DQ3 SSD_NAND_FH_DQ4 SSD_NAND_FH_DQ5 SSD_NAND_FH_DQ6 SSD_NAND_FH_DQ7 C5 D4 E5 F6 C10 D11 E10 F9 DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 DQ6_1 DQ7_1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC A1 A11 A12 A13 A14 A2 A3 A4 B1 B13 B14 B2 C1 C14 D1 D14 G13 G2 G4 G9 H10 H13 H2 H4 J11 J13 J2 J5 K11 K13 K2 K6 N1 N14 P1 P14 R1 R13 R14 R2 T1 T11 T12 T13 T14 T2 T3 T4 1 D C9261 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 VPP VCCQ K3 J3 K5 K4 SSD_NAND_FF_CE_B0_L SSD_NAND_FF_CE_B1_L SSD_NAND_FF_CE_B2_L SSD_NAND_FF_CE_B3_L CLE0 ALE0 WE0* K10 K9 J9 SSD_NAND_FF_CLE SSD_NAND_FF_ALE SSD_NAND_FF_WE_L RE_0 RE_0* N6 P6 SSD_NAND_FF_RE_P SSD_NAND_FF_RE_N DQS0 DQS0* N9 P9 SSD_NAND_FF_DQS_P SSD_NAND_FF_DQS_N WP0* J10 R/B0_0* R/B1_0* G3 H3 CE0_1* CE1_1* CE2_1* CE3_1* G12 H12 G10 G11 SSD_NAND_FH_CE_B0_L SSD_NAND_FH_CE_B1_L SSD_NAND_FH_CE_B2_L SSD_NAND_FH_CE_B3_L CLE1 ALE1 WE1* G5 G6 H6 SSD_NAND_FH_CLE SSD_NAND_FH_ALE SSD_NAND_FH_WE_L RE_1 RE_1* D9 C9 SSD_NAND_FH_RE_P SSD_NAND_FH_RE_N CE0_0* CE1_0* CE2_0* CE3_0* OMIT_TABLE U9210 NAND-MLC-V3-CS-2TB-HDP K9UUGY8S7M-1CK0TP1 BGA CRITICAL IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 114 84 83 82 81 80 78 77 15 85 113 BI BI DQS1 DQS1* D6 C6 WP1* H5 85 113 SSD_NAND_FF_RDY K12 J12 VREF F11 L4 RESET0* RESET1* J6 H9 4.7K 1 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN 85 IN SSD_NAND_FH_DQS_P SSD_NAND_FH_DQS_N R/B0_1* R/B1_1* C 2 1% 1/20W MF 201 NOSTUFF 85 84 83 82 81 80 78 77 15 BI 85 113 BI 85 113 PP1V8_SSD_FMC R9211 SSD_NAND_FH_RDY 1 4.7K 2 1% 1/20W MF 201 NC RFU PP1V8_SSD_FMC R9210 114 NOSTUFF SSD_FVREF0 SSD_NAND_FF_RESET_L SSD_NAND_FH_RESET_L F12 F3 F4 L11 L12 L3 1 IN 85 IN 85 77 82 83 C9212 B 0.1UF 10% 2 16V CER 0201 NC NC NC NC NC NC NU VSS B10 B3 B5 C11 C12 C3 C4 D13 D2 D5 E11 E12 E13 E2 E3 E9 F5 H11 J4 L10 M12 M13 M2 M3 M4 M6 N10 N13 N2 P11 P12 P3 P4 R10 R12 R5 113 C9252 C9255 12PF 12PF 4.7UF 12PF 1 C9253 C9200 B6 B9 F13 F2 L13 L2 R6 R9 +/-0.1PF 2 25V NP0-C0G 0201 1 1 PP12V_SSD_VPP B11 B4 C13 C2 D10 D12 D3 E4 E6 F10 L5 M11 M9 N12 N3 N5 P13 P2 R11 R4 C9256 C9259 3.0PF PP3V3_SSD_NAND 1 PP3V3_SSD_NAND 0.1UF B12 R3 84 83 82 78 1 PP12V_SSD_VPP B11 B4 C13 C2 D10 D12 D3 E4 E6 F10 L5 M11 M9 N12 N3 N5 P13 P2 R11 R4 C9257 B6 B9 F13 F2 L13 L2 R6 R9 1 1 PP1V8_SSD_FMC 84 83 82 81 80 78 77 15 1 114 2 B12 R3 8 SYNC_MASTER=X363_JSAMUELS SYNC_DATE=08/09/2016 PAGE TITLE NAND 2/2 DRAWING NUMBER NU Apple Inc. 051-00647 REVISION R B10 B3 B5 C11 C12 C3 C4 D13 D2 D5 E11 E12 E13 E2 E3 E9 F5 H11 J4 L10 M12 M13 M2 M3 M4 M6 N10 N13 N2 P11 P12 P3 P4 R10 R12 R5 VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 92 OF 145 83 OF 121 SIZE D A 8 7 6 5 4 3 2 1 CRITICAL U9390 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V PP3V3_SSD_NAND 78 TPS22965 TPS22965 CT 6 PP3V3_SSD_ISNS_R 20% 2 10V X5R-CERM 0603-1 1 22UF 10% 2 16V CER 0201 C9302 CRITICAL MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE 20% 2 10V X5R-CERM 0603-1 0.1UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V L9330 0.47UH-20%-4.0A-28MOHM 1 P1V8_SSD_FMC_SW 2 PP1V8_SSD_FMC C9330 22UF 20% 2 10V X5R-CERM 0603-1 1 C9331 84 78 77 PP1V2_SSD_DRAM C9311 22UF 20% 2 10V X5R-CERM 0603-1 20% 2 10V X5R-CERM 0603-1 1 C9313 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE P1V1_SSD_PCIE_SW 22UF 20% 2 10V X5R-CERM 0603-1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V L9340 1UH-20%-1.1A-0.1OHM 1 2 PP1V1_SSD_PCIE C9340 84 77 20% 2 6.3V X5R-CERM 0201 C9318 1 0.1UF 1 31 17 14 16 15 SSD_PGOOD_L OUT OUT C9322 0.1UF 10% 2 16V CER 0201 77 81 80 77 81 80 77 IN IN BI QFN SW1 VOUT1 SW2 VOUT2 SW3 VOUT3 SW4 VOUT4 SW5 VOUT5 SSD_PWRCON0 SSD_I2C_CLK SSD_I2C_DAT PVIN6 PGND6 PVIN6O SW6 VOUT6 PG RSTO PMRST SCL SDA 26 23 25 24 22 1 2 VOUT 3 ON CT 6 NC 4 VBIAS 1 0.1UF C9393 C 1UF GND EPAD 20% 2 4V CERM-X6S 0201 10% 2 16V CER 0201 77 78 80 84 C9350 22UF 20% 2 10V X5R-CERM 0603-1 TPS22966 POWER PINS USE SINGLE PAD ON PCB U9395 TPS22966 114 53 78 84 86 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE CRITICAL MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.0V L9360 0.47UH-20%-4.0A-28MOHM P1V0_SSD_CORE_SW 1 2 PP1V0_SSD_CORE 84 77 IN 86 84 78 53 78 84 114 C9360 22UF 20% 2 10V X5R-CERM 0603-1 1 PP1V0_SSD_CORE R9390 1 C9307 0.1UF C9361 R9391 1 10% 2 16V CER 0201 22UF 20% 2 10V X5R-CERM 0603-1 1K 2 SSD_PWRCON1_R0 5% 1/20W MF 201 PP3V3_SSD_LIM 1 1 84 78 SSD_PWRCON1 PIFE25201B-SM P12V_SSD_VPP_SW 1 35 OTP_W 36 OTP_R PP1V8_SSD_DRAM C9306 78 0805 LDO 34 SSD_PMIC_LDO 37 EPAD MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V L9350 P1V8_SSD_DRAM_SW 29 27 3 1 6 8 12 9 20 18 PP3V3_SSD_LIM 32 AVIN 33 AGND SSD_RESET_B_L 1 B R9320 1% 1/20W MF 2 201 1% 1/20W MF 2 201 77 20% 2 6.3V X5R-CERM 0201 100K 4.7K 77 C9320 PVIN1 PGND1 PVIN2 PGND2 PVIN3 PGND3 PVIN4 PGND4 PGND4 PVIN5 PGND5 1 1UH-20%-1.1A-0.1OHM S2FPS04X01-1030 30 28 4 2 5 7 13 10 11 21 19 10% 2 16V CER 0201 2.2UF R9321 CRITICAL MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE U9310 MIN_LINE_WIDTH=0.2000 XW9300 MIN_NECK_WIDTH=0.1200 SM VOLTAGE=3.3V 1 2 PP3V3_SSD_PMIC_AVIN ADDED XW ON AVIN 114 C9319 0.1UF 10% 2 16V CER 0201 PP1V8_SSD_DRAM 1 1 0.1UF 10% 2 16V CER 0201 1 VIN 8 7 1 C9317 PP3V3_SSD_LIM PP3V3_SSD_LIM SON 1K NC 2 SSD_PWRCON1_R1 5% 1/20W MF 201 NC 1 VIN1 3 ON1 12 CT1 DPU 4 VBIAS 6 VIN2 5 ON2 10 CT2 1UF 10% 2 6.3V X7R 0402 L9370 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V PP1V2_SSD_DRAM 0.47UH-20%-4.0A-28MOHM 1 P1V2_SSD_DRAM_SW 2 1 C9395 1UF 20% 2 4V CERM-X6S 0201 B U9397 77 78 84 R9392 1 1 C9370 1 22UF C9371 20% 2 10V X5R-CERM 0603-1 R9393 1 MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.4000 SWITCH_NODE=TRUE DIDT=TRUE L9380 2.2UH-20%-1A-0.263OHM D9380 SOD1608 2 SSD_PWRCON1_R2 1K 5% 1/20W MF 201 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=12V NC 2 SSD_PWRCON1_R3 NC 1 VIN1 3 ON1 12 CT1 DPU VOUT1 13 CRITICAL 4 VBIAS 6 VIN2 5 ON2 10 CT2 VOUT2 8 GND CRITICAL 1K 5% 1/20W MF 201 22UF 20% 2 10V X5R-CERM 0603-1 SSD PMIC Alternate Parts 78 TPS22966 PIFE25201B-SM MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.4000 SWITCH_NODE=TRUE DIDT=TRUE PP1V0_SSD_CORE_L12 CRITICAL MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE NC MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.0V VOUT2 8 C9321 NC VOUT1 13 CRITICAL 11 1 SSD_PWRCON1 IN 86 84 78 53 CRITICAL 80 77 78 84 PP1V8_SSD_DRAM 84 80 78 77 2.2UF 20% 2 6.3V X5R-CERM 0201 86 84 78 53 1 2 GND 2.2UF MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.8V PP1V8_SSD_DRAM_L12 TPS22965 20% 2 10V X5R-CERM 0603-1 C9315 20% 2 4V CERM-X6S 0201 GND EPAD PAD 1 1UF U9393 22UF C9314 C9391 CRITICAL 78 0805 1 77 78 NC 1 THRM 20% 2 10V X5R-CERM 0603-1 C9312 1 22UF CT 6 10% 2 16V CER 0201 CRITICAL 5 1 8 7 VOUT C9305 0.1UF 22UF D MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V PP1V2_SSD_DRAM_L12 4 VBIAS PP3V3_SSD_LIM PP3V3_SSD_LIM C VIN 3 ON SSD_PWRCON2 IN 1 1 SON 1 2 86 84 78 53 C9310 5% 2 50V C0G 0402 TPS22965 22UF 77 1 33PF U9391 20% 2 10V X5R-CERM 0603-1 C9390 CRITICAL 15 77 78 80 81 82 83 114 PIFE25201B-SM 1 84 53 78 86 C9304 NOSTUFF GND EPAD PAD 20% 2 10V X5R-CERM 0603-1 22UF 10% 2 50V X7R-CERM 0402 10% 2 16V CER 0201 C9301 1 0.001UF GND EPAD 0.1UF 22UF C9303 1 82 83 SSD_P3V3_NAND_CT 1 9 C9300 CT 6 4 VBIAS 1 5 D C9308 1 3 ON SSD_PWRCON3 IN SSD_3V3_SS 4 VBIAS 1 77 53 9 3 ON SSD_PWR_LB_EN IN 8 7 15 87 VOUT THRM 115 VIN VOUT 5 SON 1 2 VIN 8 7 9 PP3V3_S5_POLARIS 5 87 SON 1 2 PP3V3_SSD_LIM 86 84 78 53 9 115 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V U9300 ALTERNATE FOR PART NUMBER BOM OPTION REF DES 1 COMMENTS: 152S00309 1 ALL 152S00310 C9381 2.2UF TABLE_ALT_ITEM 152S1721 P12V_SSD_VPP_SW_L A K PP12V_SSD_VPP 82 83 0806 TABLE_ALT_ITEM 152S00457 2 15 PART NUMBER 11 TABLE_ALT_HEAD PMEG4010EPKS500 CRITICAL 20% 2 6.3V X5R-CERM 0201 ALL C9380 4.7UF 10% 2 25V X5R-CER 0805 PLACE_NEAR=L9380.1:3MM A 1 NOSTUFF 1 C9382 4.7UF 10% 2 35V X5R-CERM 0603-1 SYNC_MASTER=X363_JSAMUELS SYNC_DATE=08/09/2016 PAGE TITLE PAGE_TITLE=POLARIS PMIC DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 93 OF 145 84 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D OMIT_TABLE OMIT_TABLE U8605 U8605 KG10000C2E-A200TAB KG10000C2E-A200TAB BGA BGA SYM 2 OF 5 SYM 1 OF 5 82 113 OUT 82 OUT 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 82 OUT 82 OUT 82 OUT 82 OUT C 82 OUT 82 OUT 82 OUT 82 OUT 85 82 OUT 82 OUT 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 113 82 BI 82 OUT 82 OUT 82 OUT 82 OUT B 82 OUT 82 OUT 82 OUT 82 OUT 85 SSD_NAND_FA_ALE SSD_NAND_FA_CLE SSD_NAND_FA_DQS_N SSD_NAND_FA_DQS_P SSD_NAND_FA_DQ0 SSD_NAND_FA_DQ1 SSD_NAND_FA_DQ2 SSD_NAND_FA_DQ3 SSD_NAND_FA_DQ4 SSD_NAND_FA_DQ5 SSD_NAND_FA_DQ6 SSD_NAND_FA_DQ7 SSD_NAND_FA_CE_B0_L SSD_NAND_FA_CE_B1_L SSD_NAND_FA_CE_B2_L SSD_NAND_FA_CE_B3_L NC NC NC NC SSD_NAND_FA_RE_N SSD_NAND_FA_RE_P SSD_NAND_FA_WE_L SSD_NAND_FA_RESET_L SSD_NAND_FA_ZQ SSD_NAND_FB_ALE SSD_NAND_FB_CLE SSD_NAND_FB_DQS_N SSD_NAND_FB_DQS_P SSD_NAND_FB_DQ0 SSD_NAND_FB_DQ1 SSD_NAND_FB_DQ2 SSD_NAND_FB_DQ3 SSD_NAND_FB_DQ4 SSD_NAND_FB_DQ5 SSD_NAND_FB_DQ6 SSD_NAND_FB_DQ7 SSD_NAND_FB_CE_B0_L SSD_NAND_FB_CE_B1_L SSD_NAND_FB_CE_B2_L SSD_NAND_FB_CE_B3_L NC NC NC NC SSD_NAND_FB_RE_N SSD_NAND_FB_RE_P SSD_NAND_FB_WE_L SSD_NAND_FB_RESET_L B16 C17 A13 A12 B11 B13 C13 C12 D14 D11 D13 C11 A18 F12 B17 F13 B19 C15 B15 G12 F15 F16 D16 B18 D17 F0ALE F0CLE F0DQS* F0DQS F0DQ0 F0DQ1 F0DQ2 F0DQ3 F0DQ4 F0DQ5 F0DQ6 F0DQ7 F0CEB0 F0CEB1 F0CEB2 F0CEB3 F0CEB4 F0CEB5 F0CEB6 F0CEB7 F0RE* F0RE F0WE* F0NDRST* F0ZQ D22 C22 A20 A21 D20 D18 C19 D21 D19 B20 B22 C21 H18 G18 C23 E23 E24 J19 G20 D24 F18 F19 H19 C24 F1ALE F1CLE F1DQS* F1DQS F1DQ0 F1DQ1 F1DQ2 F1DQ3 F1DQ4 F1DQ5 F1DQ6 F1DQ7 F1CEB0 F1CEB1 F1CEB2 F1CEB3 F1CEB4 F1CEB5 F1CEB6 F1CEB7 F1RE* F1RE F1WE* F1NDRST* CRITICAL 0 1 2 3 F2ALE F2CLE F2DQS* F2DQS F2DQ0 F2DQ1 F2DQ2 F2DQ3 F2DQ4 F2DQ5 F2DQ6 F2DQ7 F2CEB0 F2CEB1 F2CEB2 F2CEB3 F2CEB4 F2CEB5 F2CEB6 F2CEB7 F2RE* F2RE F2WE* F2NDRST* K22 J22 F25 G25 F23 E22 F22 H22 H20 F24 H24 G23 J24 H23 M19 L19 L22 J25 K24 N19 K20 L20 M20 J23 SSD_NAND_FC_ALE SSD_NAND_FC_CLE SSD_NAND_FC_DQS_N SSD_NAND_FC_DQS_P SSD_NAND_FC_DQ0 SSD_NAND_FC_DQ1 SSD_NAND_FC_DQ2 SSD_NAND_FC_DQ3 SSD_NAND_FC_DQ4 SSD_NAND_FC_DQ5 SSD_NAND_FC_DQ6 SSD_NAND_FC_DQ7 SSD_NAND_FC_CE_B0_L SSD_NAND_FC_CE_B1_L SSD_NAND_FC_CE_B2_L SSD_NAND_FC_CE_B3_L F3ALE F3CLE F3DQS* F3DQS F3DQ0 F3DQ1 F3DQ2 F3DQ3 F3DQ4 F3DQ5 F3DQ6 F3DQ7 F3CEB0 F3CEB1 F3CEB2 F3CEB3 F3CEB4 F3CEB5 F3CEB6 F3CEB7 F3RE* F3RE F3WE* F3NDRST* P23 T19 M25 L25 L23 P19 L24 M22 M23 N22 N24 M24 T25 R22 P24 T22 R23 P25 U19 R25 R20 P20 P22 T20 SSD_NAND_FD_ALE SSD_NAND_FD_CLE SSD_NAND_FD_DQS_N SSD_NAND_FD_DQS_P SSD_NAND_FD_DQ0 SSD_NAND_FD_DQ1 SSD_NAND_FD_DQ2 SSD_NAND_FD_DQ3 SSD_NAND_FD_DQ4 SSD_NAND_FD_DQ5 SSD_NAND_FD_DQ6 SSD_NAND_FD_DQ7 SSD_NAND_FD_CE_B0_L SSD_NAND_FD_CE_B1_L SSD_NAND_FD_CE_B2_L SSD_NAND_FD_CE_B3_L NC NC NC NC SSD_NAND_FC_RE_N SSD_NAND_FC_RE_P SSD_NAND_FC_WE_L SSD_NAND_FC_RESET_L NC NC NC NC SSD_NAND_FD_RE_N SSD_NAND_FD_RE_P SSD_NAND_FD_WE_L SSD_NAND_FD_RESET_L OUT 82 OUT 82 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 BI 82 113 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 82 OUT 83 OUT 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 113 83 BI 83 BI 113 OUT 83 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT SSD_NAND_FE_ALE SSD_NAND_FE_CLE SSD_NAND_FE_DQS_N SSD_NAND_FE_DQS_P SSD_NAND_FE_DQ0 SSD_NAND_FE_DQ1 SSD_NAND_FE_DQ2 SSD_NAND_FE_DQ3 SSD_NAND_FE_DQ4 SSD_NAND_FE_DQ5 SSD_NAND_FE_DQ6 SSD_NAND_FE_DQ7 SSD_NAND_FE_CE_B0_L SSD_NAND_FE_CE_B1_L SSD_NAND_FE_CE_B2_L SSD_NAND_FE_CE_B3_L NC NC NC NC SSD_NAND_FE_RE_N SSD_NAND_FE_RE_P SSD_NAND_FE_WE_L SSD_NAND_FE_RESET_L SSD_NAND_FF_ALE SSD_NAND_FF_CLE SSD_NAND_FF_DQS_N SSD_NAND_FF_DQS_P SSD_NAND_FF_DQ0 SSD_NAND_FF_DQ1 SSD_NAND_FF_DQ2 SSD_NAND_FF_DQ3 SSD_NAND_FF_DQ4 SSD_NAND_FF_DQ5 SSD_NAND_FF_DQ6 SSD_NAND_FF_DQ7 SSD_NAND_FF_CE_B0_L SSD_NAND_FF_CE_B1_L SSD_NAND_FF_CE_B2_L SSD_NAND_FF_CE_B3_L NC NC NC NC SSD_NAND_FF_RE_N SSD_NAND_FF_RE_P SSD_NAND_FF_WE_L SSD_NAND_FF_RESET_L W23 Y24 W25 Y25 V24 U24 T23 U25 T24 V23 U22 V22 W22 Y22 Y19 W19 AA23 AA24 AA22 W18 V20 W20 W24 U20 F4ALE F4CLE F4DQS* F4DQS F4DQ0 F4DQ1 F4DQ2 F4DQ3 F4DQ4 F4DQ5 F4DQ6 F4DQ7 F4CEB0 F4CEB1 F4CEB2 F4CEB3 F4CEB4 F4CEB5 F4CEB6 F4CEB7 F4RE* F4RE F4WE* F4NDRST* V17 AB18 AE22 AE23 AB25 AC24 AB24 AC25 AC23 AB22 AC22 AD23 AC20 AC21 AD20 AB21 W15 W16 AD19 AE20 Y16 Y17 AB19 AC19 F5ALE F5CLE F5DQS* F5DQS F5DQ0 F5DQ1 F5DQ2 F5DQ3 F5DQ4 F5DQ5 F5DQ6 F5DQ7 F5CEB0 F5CEB1 F5CEB2 F5CEB3 F5CEB4 F5CEB5 F5CEB6 F5CEB7 F5RE* F5RE F5WE* F5NDRST* CRITICAL 4 5 6 7 F6ALE F6CLE F6DQS* F6DQS F6DQ0 F6DQ1 F6DQ2 F6DQ3 F6DQ4 F6DQ5 F6DQ6 F6DQ7 F6CEB0 F6CEB1 F6CEB2 F6CEB3 F6CEB4 F6CEB5 F6CEB6 F6CEB7 F6RE* F6RE F6WE* F6NDRST* W13 Y15 AE16 AE17 AC18 AB17 AD18 AC17 AC16 AB15 AC15 AD16 AD15 AC14 W12 AD13 W11 AB11 AC12 AB12 Y14 Y13 AB13 AB14 SSD_NAND_FG_ALE SSD_NAND_FG_CLE SSD_NAND_FG_DQS_N SSD_NAND_FG_DQS_P SSD_NAND_FG_DQ0 SSD_NAND_FG_DQ1 SSD_NAND_FG_DQ2 SSD_NAND_FG_DQ3 SSD_NAND_FG_DQ4 SSD_NAND_FG_DQ5 SSD_NAND_FG_DQ6 SSD_NAND_FG_DQ7 SSD_NAND_FG_CE_B0_L SSD_NAND_FG_CE_B1_L SSD_NAND_FG_CE_B2_L SSD_NAND_FG_CE_B3_L F7ALE F7CLE F7DQS* F7DQS F7DQ0 F7DQ1 F7DQ2 F7DQ3 F7DQ4 F7DQ5 F7DQ6 F7DQ7 F7CEB0 F7CEB1 F7CEB2 F7CEB3 F7CEB4 F7CEB5 F7CEB6 F7CEB7 F7RE* F7RE F7WE* F7NDRST* W9 AC7 AE12 AE11 AD12 AC11 AB10 AC10 AB9 AD9 AB8 AC8 AB7 Y7 W7 AB6 Y6 W6 Y8 AC6 Y10 Y11 Y9 AD7 SSD_NAND_FH_ALE SSD_NAND_FH_CLE SSD_NAND_FH_DQS_N SSD_NAND_FH_DQS_P SSD_NAND_FH_DQ0 SSD_NAND_FH_DQ1 SSD_NAND_FH_DQ2 SSD_NAND_FH_DQ3 SSD_NAND_FH_DQ4 SSD_NAND_FH_DQ5 SSD_NAND_FH_DQ6 SSD_NAND_FH_DQ7 SSD_NAND_FH_CE_B0_L SSD_NAND_FH_CE_B1_L SSD_NAND_FH_CE_B2_L SSD_NAND_FH_CE_B3_L NC NC NC NC SSD_NAND_FG_RE_N SSD_NAND_FG_RE_P SSD_NAND_FG_WE_L SSD_NAND_FG_RESET_L NC NC NC NC SSD_NAND_FH_RE_N SSD_NAND_FH_RE_P SSD_NAND_FH_WE_L SSD_NAND_FH_RESET_L OUT 83 OUT 83 BI 83 113 BI 83 113 BI 83 113 BI 83 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 OUT 83 OUT 83 OUT 83 OUT 83 C OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 BI 83 113 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 B SSD_NAND_FA_ZQ 1 R9400 240 1% 1/20W MF 2 201 A SYNC_MASTER=X363_JSAMUELS SYNC_DATE=04/01/2016 PAGE TITLE SSD NAND VR DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 94 OF 145 85 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D 84 78 53 PP3V3_SSD_LIM PLACE_NEAR=U9500:2mm 1 C9500 1 0.1UF 1K 10% 2 6.3V CERM-X5R 0201 9 C 5% 1/20W MF 2 201 VCC 114 77 OUT 114 77 BI SSD_DEBUG_I2C_CLK SSD_DEBUG_I2C_DAT From Polaris CRITICAL 1 Y+ 2 Y- M+ 5 M- 4 U9500 PI3USB102EZLE TQFN 15 SSD_DEBUGI2C_SEL_PCH 10 SEL GND 1 R9551 1K 5% 1/20W MF 201 2 From Debug Connector / ACE TA SPEED = 3.2Mbps SEL = LOW SSD_DEBUG_I2C_CLK_CONN 80 103 114 IN SSD_DEBUG_I2C_DAT_CONN 80 103 114 BI I2C_SSD_SCL I2C_SSD_SDA From PCH SPEED = 1Mbps SEL = HIGH 8 SSD_DEBUG_MUX_OE 1 IN BI C 15 15 R9504 3 1K 5% 1/20W MF 2 201 NO_XNET_CONNECTION=1 NOSTUFF NO_XNET_CONNECTION=1 D+ 7 D- 6 OE* R9550 R9503 0 1 2 5% 1/20W MF 201 NOSTUFF NO_XNET_CONNECTION=1 R9502 1 0 2 5% 1/20W MF 201 B B A SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/15/2016 PAGE TITLE SSD SUPPORT DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=SSD II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 95 OF 145 86 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D LIFEBOAT J9600 PCH Side 110 20759-042E-02 F-ST-SM 43 PP3V3_S5 1 115 115 115 114 114 114 15 14 20 14 115 113 113 20 14 14 14 C 113 113 113 14 12 12 IN IN IN OUT OUT OUT IN IN IN IN SSD_BOOT_L SSD_PWR_EN SSD_RESET_L SSD_CLKREQ_L PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0> PCIE_SSD_R2D_C_P<0> PCIE_SSD_R2D_C_N<0> PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE PWR SIGNAL 44 SSD Side PP3V3_S5_POLARIS VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18GND_VOID=TRUE 19 20GND_VOID=TRUE 21 22 23 24GND_VOID=TRUE 25 26GND_VOID=TRUE 27 28 29 30GND_VOID=TRUE 31 32GND_VOID=TRUE 33 34 35 36 37 38 39 40 41 42 SSD_BOOT_LB_L SSD_PWR_LB_EN 84 115 NC OUT 77 114 OUT 84 115 115 NC SSD_RESET_LB_L SSD_CLKREQ_LB_L OUT 77 115 IN 77 115 PCIE_SSD_D2R_LB_P<0> PCIE_SSD_D2R_LB_N<0> IN 77 113 IN 77 113 PCIE_SSD_R2D_LB_P<0> PCIE_SSD_R2D_LB_N<0> OUT 77 113 OUT 77 113 PCIE_CLK100M_SSD_LB_P PCIE_CLK100M_SSD_LB_N OUT 77 113 OUT 77 113 C NC Detect Pin PWR 45 47 46 GND 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 B B A SYNC_MASTER=X363_BBABADI SYNC_DATE=01/20/2016 PAGE TITLE Lifeboat DRAWING NUMBER Apple Inc. 051-00647 REVISION R BOM_COST_GROUP=SSD NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 96 OF 145 87 OF 121 SIZE D A 8 7 6 5 4 3 2 1 D D C C B B A SYNC_MASTER=Constraints SYNC_DATE=05/18/2016 PAGE TITLE Constraints DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 97 OF 145 88 OF 121 SIZE D A 6 5 4 3 DPMUX_UC_MD2_R Q9890 OUT 91 89 OUT 98 89 111 89 46 12 OUT BI 46 12 BI 46 12 BI 46 12 BI 46 12 IN 89 20 20 114 76 IN 89 111 89 OUT 111 89 IN D4 A5 B4 A1 C2 B2 C1 C3 TP_DPMUX_UC_P40 TP_DPMUX_UC_P41 TP_DPMUX_UC_P42 LCD_FSS LCD_MUX_SEL TP_DPMUX_UC_P45 TP_DPMUX_UC_P46 TP_DPMUX_UC_P47 IN C A9 P30/LAD0 D9 P31/LAD1 C8 P32/LAD2 B7 P33/LAD3 A8 P34/LFRAM* D8 P35/LRESET* D7 P36/LCLK was 33MHz now 24MHz!!! D6 P37/SERIRQ LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L DPMUX_LRESET_L LPC_CLK24M_DPMUX_UC TP_DPMUX_UC_P37 G2 F3 E4 DPMUX_UC_TX DPMUX_UC_RX TP_DPMUX_UC_P52 N10 M11 L10 N11 N12 M13 N13 L12 P40/TMI0/TCMCYI0 P41/TMO0/TCMCKI0/TCMMCI0 P42/TCMCYI1 P43/TMI1/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWMU4B P47/PWMU5B P80/PME* P81/GA20 P82/CLKRUN* P83/LPCPD* P84/IRQ3*/TXD1 P85/IRQ4*/RXD1 P86/IRQ5*/SCK1 A7 B6 C7 D5 A6 B5 C6 P90/IRQ2* P91/IRQ1* P92/IRQ0* P93/IRQ12* P94/IRQ13* P95/IRQ14* P96/EXCL P97/SDA0/IRQ15* J4 G3 H2 G1 H4 G4 F4 F1 89 R9801 PP3V3_S4 110 NC NC NC NC NC NC NC NC S 2 DPMUX_UC_MD1 89 1 PP3V3_S0 98 89 49 1 0 2 89 5% 1/16W MF-LF 402 C9800 OUT 111 IN 111 1 0.1UF 20% 10V X7R-CERM 0402 20% 10V X7R-CERM 0402 2 PP3V3_S3_DPMUX_UC_R MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V PP3V3_S0_DPMUX_UC_R MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V C9801 1 0.1UF TP_DPMUX_UC_P80 TP_DPMUX_UC_P81 TP_DPMUX_UC_P82 TP_DPMUX_UC_P83 DPMUX_UC_TX DPMUX_UC_RX TP_LCD_IRQ 2 5% 1/16W MF-LF 402 R9800 110 0 C9802 C9803 1 0.1UF 2 20% 10V X7R-CERM 0402 89 89 99 IN 27 29 89 20 IN 27 29 IN 101 IN 101 IN 48 89 IN 89 99 DPMUX_LRESET_L 0 1 2 5% 1/16W MF-LF 402 D3 113 113 89 89 A3 A2 DPMUX_UC_XTAL DPMUX_UC_EXTAL RES* XTAL EXTAL 49 OUT 20 89 48 46 OUT SMC_GFX_OVERTEMP OUT NC NC NC TP_FB_CLAMP_TOGGLE_REQ_L B 99 89 OUT 99 89 OUT 99 89 OUT 99 89 OUT 99 OUT 89 46 OUT 99 89 89 76 OUT 89 75 OUT 89 89 20 89 15 OUT OUT 89 15 OUT 89 15 OUT 89 15 OUT 89 15 B8 C9 B9 A10 C10 B10 C11 A11 TP_DPA_EG_HPD DP_X_SNK0_HPD_EG DP_X_SNK1_HPD_EG DP_T_SNK0_HPD_EG DP_T_SNK1_HPD_EG GPU_GFX_PWR_LEVEL_L SMC_GFX_SELF_THROTTLE DP_INT_EG_HPD OUT OUT EDP_PANEL_PWR_EN EDP_BKLT_EN TP_DPMUX_UC_PC2 TP_DPMUX_UC_PC3 LCD_MUX_EN TP_LCD_MUX_REQ BKLT_PWM_MLB2TCON TP_DPMUX_UC_PC7 G11 G13 F12 H13 G10 G12 H11 J13 TP_DPA_IG_HPD DP_X_SNK0_HPD_IG DP_X_SNK1_HPD_IG DP_T_SNK0_HPD_IG DP_T_SNK1_HPD_IG TP_DPMUX_UC_PD5 TP_DPMUX_UC_PD6 DP_INT_IG_HPD M10 N9 K10 L8 M9 N8 K9 L7 PE0/EXEXCL PE1/ETCK PE2/ETDI PE3/ETDO PE4/ETMS PE5/ETRST* K1 J3 K2 J1 K4 H3 DPMUX_UC_CLK32K DPMUX_UC_TCK DPMUX_UC_TDI DPMUX_UC_TDO DPMUX_UC_TMS DPMUX_UC_TRST_L PF0/IRQ8*/PWMU0A PF1/IRQ9*/PWMU1A PF2/IRQ10*/TMOY PF3/IRQ11*/TMOX PF4/PWMU2A/EXDSR PF5/PWMU3A/EXDTR PF6/PWMU4A/EXCTS PF7/PWMU5A/EXRTS K5 N5 M6 L5 M5 N4 L4 M4 EG_LCD_PWR_EN EG_BKLT_EN PM_ALL_GPU_PGOOD P5_S0GPU_PGOOD GPUVCORE_PGOOD PVDDCI_PGOOD P1V8GPU_PGOOD P3V3_S0GPU_PGOOD PG0/EXIRQ8*/TMIX/SDAA PG1/EXIRQ9*/TMIY/SCLA PG2/EXIRQ10*/SDAB PG3/EXIRQ11*/SCLB PG4/EXIRQ12*/SDAC PG5/EXIRQ13*/SCLC PG6/EXIRQ14*/SDAD PG7/EXIRQ15*/SCLD M8 N7 K8 K7 K6 N6 M7 L6 R4F2113NLG TLP-145V SYM 2 OF 3 OMIT_TABLE PB0/LSMI* PB1/LSCI PB2/RI*/PWMU0B PB3/DCD*/PWMU1B PB4/DSR*/FSIDO PB5/DTR*/FSIDI PB6/CTS*/FSICK PB7/RTS*/FSISS PC0/TIOCA0/WUE8* PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10* PC3/TIOCD0/TCLKB/WUE11* PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15* 89 89 111 89 111 89 89 PP3V3_S0_DPMUX_UC_R DPMUX_UC_TX DPMUX_UC_RX DPMUX_UC_RESET_L 1 IN 99 IN 99 IN 91 IN 91 IN 91 IN 91 IN 91 IN 91 2 3 4 10K 5% 1/20W MF 201 2 5 89 DPMUX_UC_MD1 5% 1/20W MF 201 DPMUX_XTAL:YES DPMUX_UC_MDCKN 6 89 113 DPMUX_DEBUG R9891 1 BI OUT IN 10K 5% 1/20W MF 201 2 DPMUX_XTAL:NO 113 5 IN 113 5 IN 113 5 IN 113 5 IN 113 5 BI 113 5 BI 113 99 IN 113 99 IN 113 99 IN 113 99 IN 113 99 IN 113 99 IN 113 99 IN 113 99 IN 113 99 BI 113 99 BI DP_INT_IG_ML_P<2> DP_INT_IG_ML_N<2> B6 A6 DIN1_2+ DIN1_2- DP_INT_IG_ML_P<3> DP_INT_IG_ML_N<3> A8 A9 DIN1_3+ DIN1_3- DP_INT_IG_AUX_P DP_INT_IG_AUX_N H9 J9 DAUX1+ DAUX1- U9850 CRITICAL J2 HPD_1 DIN2_0+ DIN2_0- DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1> D8 D9 DIN2_1+ DIN2_1- DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2> E8 E9 DIN2_2+ DIN2_2- DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3> F8 F9 DIN2_3+ DIN2_3- DP_INT_EG_AUX_P DP_INT_EG_AUX_N H6 J6 DAUX2+ DAUX2- 89 NC VSS VSS VSS VSS VSS D2 L3 F10 C5 B11 D TFBGA DDC_CLK1 DDC_DAT1 B8 B9 DOUT_0+ B2 DOUT_0- B1 EDP_INT_ML_P<0> EDP_INT_ML_N<0> OUT 111 OUT 111 DOUT_1+ D2 DOUT_1- D1 EDP_INT_ML_P<1> EDP_INT_ML_N<1> OUT 111 OUT 111 DOUT_2+ E2 DOUT_2- E1 EDP_INT_ML_P<2> EDP_INT_ML_N<2> OUT 111 OUT 111 DOUT_3+ F2 DOUT_3- F1 EDP_INT_ML_P<3> EDP_INT_ML_N<3> OUT 111 OUT 111 AUX+ H2 AUX- H1 IN 110 98 89 49 1 2 89 DPMUX_UC_MD1 R9812 10K 1 2 89 DPMUX_UC_MD2 R9813 10K 1 2 89 DPMUX_UC_CLK32K R9814 89 DPMUX_UC_TCK R9815 10K 1 2 89 DPMUX_UC_TDI R9816 10K 1 2 89 DPMUX_UC_TDO R9817 10K 1 2 DPMUX_UC_TMS R9818 10K 1 2 H5 J5 DDC_CLK2 DDC_DAT2 H3 HPD_2 LCD_MUX_SEL A1 GPU_SEL 89 LCD_MUX_EN B7 XSD* 98 89 EG_CLKREQ_SEL_L R9819 89 48 SMC_GFX_PWR_LEVEL_L R9842 LCD_MUX_EN R9855 R9856 5% 5% 5% 5% 10K 1 5% 89 5% 5% 100K 1 HPDIN J1 1 LCD_MUX_SEL 1 100K 91 89 EG_RAIL1_EN R9821 10K 1 2 91 89 EG_RAIL2_EN R9822 10K 1 2 IN 15 IN 15 R9840 DPMUX_UC_RESET_L 10K 1 100K 0 MF 1/20W 201 MF 1/20W 201 MF 1/20W 201 201 MF 1/20W MF 1/20W 201 MF 1/20W 201 MF 1/20W 91 89 EG_RAIL3_EN R9823 10K 1 2 91 89 EG_RAIL4_EN R9824 10K 1 2 91 89 EG_RAIL5_EN R9825 10K 1 2 89 76 EDP_PANEL_PWR_EN R9826 10K 1 2 89 75 EDP_BKLT_EN R9827 10K 1 2 89 20 BKLT_PWM_MLB2TCON R9828 10K 1 2 89 DPMUX_UC_NMI R9829 10K 1 2 89 DPMUX_UC_MD1 R9830 10K 1 89 DPMUX_UC_MD2 R9831 10K 2 1 2 89 DPMUX_UC_PECI R9832 89 DPMUX_UC_PEVREF 89 PP3V3_S0 PP3V3_S5 1 1 1/20W MF 1 2 MF 74LVC1G07GF SOT891 PM_SLP_S3_L 2 A 1 NC NC 5 NC MF 201 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% NOSTUFF 1/20W MF 201 5% NOSTUFF 1/20W MF 201 2 1/20W MF 201 1 2 5% NOSTUFF 5% 1/20W MF 201 10K 1 2 5% 1/20W MF 201 R9833 10K 1 2 5% 1/20W MF 201 EG_RESET_L R9835 100K 1 2 5% 1/20W MF 201 DP_X_SNK0_HPD_IG R9836 100K 1 2 5% 1/20W MF 201 99 89 DP_X_SNK0_HPD_EG R9837 100K 1 2 5% 1/20W MF 201 89 15 DP_X_SNK1_HPD_IG R9838 100K 1 2 5% 1/20W MF 201 99 89 DP_X_SNK1_HPD_EG R9839 100K 1 2 5% 1/20W MF 201 89 15 DP_INT_IG_HPD R9845 100K 1 2 5% 1/20W MF 201 99 89 DP_INT_EG_HPD R9846 100K 1 2 5% 1/20W MF 201 99 89 GPU_GFX_OVERTEMP R9847 100K 1 2 5% 1/20W MF 201 99 89 GFX_SELF_THROTTLE R9848 100K 1 2 5% 1/20W MF 201 SMC_GFX_OVERTEMP R9849 100K 1 2 5% 1/20W MF 201 SMC_GFX_SELF_THROTTLE R9852 100K 1 2 5% 1/20W MF 201 89 LCD_MUX_SEL 100K 1 2 LCD_MUX_EN 100K 201 1 2 5% 1/20W NOSTUFF 5% 1/20W MF 89 R9853 R9854 MF 201 89 15 1/20W MF GMUX_SLP_S3_BUF_L 1/20W MF 201 89 201 R9870 NOSTUFF 1 MF 111 49 89 98 110 GMUX_SLP_S3_BUF_L Y 4 1/20W 201 5% 1/20W MF 2 201 U9870 5% 201 4.7K VCC 201 201 NOSTUFF 5% C GMUX_SLP_S3_BUF_L 89 MAKE_BASE=TRUE 89 48 46 R9871 89 46 470K 5% 1/20W MF 2 201 B SYNC_MASTER=dpmux SYNC_DATE=08/22/2015 PAGE TITLE eDP Mux DPMUX_XTAL:YES 4 C9891 R9893 1 0 2 5% 1/20W MF 201 DPMUX_UC_XTAL 89 113 DPMUX_UC_EXTAL 89 113 89 15 99 89 89 15 12PF 99 89 5% 2 50V C0G-CERM 0201 WWW.AliSaler.Com 6 111 NOSTUFF MF 201 MF 2 1/20W 201 MF 1/20W 5% 1/20W NOSTUFF 5% 1/20W 5% R9841 1/20W 201 1 5% DP_T_SNK0_HPD_IG R9872 DP_T_SNK0_HPD_EG R9873 DP_T_SNK1_HPD_IG DP_T_SNK1_HPD_EG R9874 R9875 100K 100K 100K 100K 1 1 1 1 DRAWING NUMBER 2 051-00647 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH 5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE Apple Inc. 2 2 2 REVISION R 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=GRAPHICS 7 BI 2 II NOT TO REPRODUCE OR COPY IT 8 111 DDC_AUX_SEL C2 10K 2 76 114 89 DBG_XTAL 5% 2 50V C0G-CERM 0201 BI 1% 1/20W MF 201 R9820 2 5% 10K 1 MF 89 76 73 70 46 27 20 12 1 12PF DPMUX_HPD_PD DPMUX_UC_RESET_L 2 5% 100K 1/20W 2 5% 49 20 89 PP3V3_S0 5% 89 89 Y9800 1.60X1.20MM-SM C9890 EDP_AUXCH_C_P EDP_AUXCH_C_N R9862 89 DBG_XTAL 2 20% 10V X7R-CERM 0402 CBTL06142EEE H8 J8 DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0> NC NC NC 10K 89 24.000MHZ-30PPM-9.5PF-60OHM 1 3 113 DPMUX_UC_EXTAL_R DPMUX_UC_XTAL_R 1 IN DIN1_1+ DIN1_1- 2 DBG_XTAL 8 89 R9811 R9892 R9890 DPMUX_UC_NMI DPMUX_UC_TRST_L GND 0 NMI E3 89 DPMUX_XTAL:YES 1 89 2 49 10% 6.3V 2 X7R 0201 1 5 B5 A5 OMIT_TABLE 1 0.1UF 7 DPMUX_UC_MD1 DPMUX_UC_MD2 10K 89 C9870 49 89 98 110 113 DP_INT_IG_ML_P<1> DP_INT_IG_ML_N<1> 89 MD1 D1 MD2 H1 R9810 3 PP3V3_S0 2 DPMUX_UC_MDCKN DPMUX_UC_NMI 89 J9800 M-RT-SM 10% 6.3V X6S-CERM 0402 89 89 NC 1909782 1 0.47UF MDCKN C4 DPMUX UC PULL-UPS 110 101 IN 89 89 EDP_IG_PANEL_PWR_EN EDP_IG_BKLT_EN DPMUX_UC_PECI DPMUX_UC_PEVREF 114 C9805 NC E5 2 0.1UF DPMUX UC PULL-DOWNS DPMUX_LRESET_L TP_DPMUX_UC_PG6 DP_INT_HPD E2 F2 A4 B3 PH0/IRQ6* PH1/EXIRQ7* PECI PEVREF PD0/AN8 PD1/AN9 PD2/AN10 PD3/AN11 PD4/SSO PD5/SSI PD6/SSCK PD7/SCS NC NC NC 5 89 NC_I2C_DPMUX_A_SDA NC_I2C_DPMUX_A_SCL DPMUX UC DEBUG HEADER A 2 6 BI U9800 2 SYM 3 OF 3 R9850 1 PA0/KIN8*/SDA1 PA1/KIN9*/SCL1 PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD PA4/KIN12*/PS2BC PA5/KIN13*/PS2BD PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD 113 DIN1_0+ DIN1_0- NC R4F2113NLG DPMUX_XTAL:NO N3 N1 M3 M2 N2 L1 K3 L2 IN B4 A4 20% U9800 5% 1/20W MF 201 I2C_DPMUX_UC_SDA I2C_DPMUX_UC_SCL DPMUX_UC_IRQ 5 DP_INT_IG_ML_P<0> DP_INT_IG_ML_N<0> 2 10V X7R-CERM TLP-145V 20% 10V X7R-CERM 0402 C9851 0.1UF 0402 20% 10V X7R-CERM 0402 10K 49 113 DPMUX_UC_RESET_L R9802 IN IN C9804 NOSTUFF GPU_GFX_OVERTEMP DP_X_SNK0_HPD DP_X_SNK1_HPD DP_T_SNK0_HPD DP_T_SNK1_HPD SMC_GFX_PWR_LEVEL_L GFX_SELF_THROTTLE TP_DPMUX_UC_P97 5 0.1UF 1 0.1UF 2 113 NC NC DPMUX_UC_VCL P50/FTXD P51/FRXD P52/SCL0 CONNECT I2C TO LCD BKLT IC 1 1 B3 C8 G8 H4 H7 G2 91 89 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 P20 P21 P22 P23 P24 P25 P26 P27 1 G C9850 2 VBAT J2 OUT OMIT_TABLE DP 2:1 ANALOG MUX SYM_VER_2 AVREF L11 91 89 SYM 1 OF 3 1 DFN1006H4-3 TP_DPMUX_UC_P60 TP_DPMUX_UC_P61 TP_DPMUX_UC_P62 GMUX_SLP_S3_BUF_L TP_DPMUX_UC_P64 TP_DPMUX_UC_P65 TP_DPMUX_UC_P66 TP_DPMUX_UC_P67 AVSS OUT D13 E11 D12 F11 E13 E12 F13 E10 TLP-145V L13 K12 K11 J12 K13 J10 J11 H12 89 L9 91 89 EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN EG_RAIL5_EN EG_CLKREQ_SEL_L EG_RESET_L TP_FB_CLAMP R4F2113NLG P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4* P65/KIN5* P66/KIN6* P67/IRQ7*/KIN7* VCL E1 OUT P10/WUE0* P11/WUE1* P12/WUE2* P13/WUE3* P14/WUE4* P15/WUE5* P16/WUE6* P17/WUE7* VCC B1 VCC M1 VCC H10 91 89 B12 A13 A12 B13 D11 C13 C12 D10 AVCC M12 D TP_DPMUX_UC_P10 TP_DPMUX_UC_P11 TP_DPMUX_UC_P12 TP_DPMUX_UC_P13 TP_DPMUX_UC_P14 TP_DPMUX_UC_P15 TP_DPMUX_UC_P16 TP_DPMUX_UC_P17 DPMUX_UC_MD2 2 5% 1/20W MF 201 D 3 DMN32D2LFB4 U9800 0 1 PP3V3_S0 110 R9894 1 2 VDD A2 VDD J4 7 GND GND GND GND GND GND 8 1 98 OF 145 89 OF 121 SIZE D A 8 7 6 VOLTAGE=5V L9900 120OHM-25%-1.8A-0.06DCR 1 PP5V_S0_GPUFET 91 PCC:YES 1 R9900 MIN_NECK_WIDTH=0.1200 PP5V_S0_GPU_OPAMP 0402 PCC:YES PLACE_NEAR=U9900.6:2.54MM 1 C9900 1 10UF 2 X6S 0201 PPVCORE_S0_GPU 2 X6S-CERM 0201 2 1 VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 OUT 2 PP3V3_VREF_PCC C9905 1 3 1UF 90 PCC:YES GND C9904 0.1UF 10% 2 6.3V X6S 0201 2 X6S-CERM 0201 D PLACE_NEAR=U9900.6:2.54MM 6 PCC:YES V+ U9900 LMP8640 4 IN- GPU_VCORE_LOAD PCC:YES R9901 SOT23-6 50X 5 NC 1 VOUT LBW_AMP_OUT_R 1 0 LBW_AMP_OUT 2 5% 1/20W MF 0201 1 TP-P6 TP9900 A PCC:YES 1 PLACE_NEAR=U9903.5:2.54MM C9915 PP5V_S0_GPU_OPAMP 0.01UF 2 XW9900 PPVCORE_S0_GPU PCC:YES 1 SC4437 SOT23-3 20% V- 92 90 55 1 IN PP5V_VREF_PCC 2 X6S 0201 TP_U9900_5 110 2 5% 1/20W MF 201 3 IN+ SHORT-0201 1 2 2.2 MIN_NECK_WIDTH=0.1200 6.3V XW9901 92 90 55 1 U9901 MIN_LINE_WIDTH=0.2000 6.3V XW9901 should be the lower voltage placement should be at the GPU power pin furthest from the VR 110 3 VOLTAGE=5V 10% PLACE_NEAR=U9900.6:2.54MM PLACE_NEAR=U9900.6:2.54MM SHORT-0201 1 2 PP5V_S0_GPU_OPAMP 0.1UF 6.3V 2 CERM-X6S 0402 90 C9903 1 20% 6.3V 6.3V C9902 1UF 20% 90 PCC:YES PCC:YES C9901 10% D PCC:YES MIN_LINE_WIDTH=0.2000 2 0.1UF PLACE_NEAR=L9900.1:2.54MM 4 PCC:YES PCC:YES 100 5 10% 2 10V X5R 201 GPU_VCORE_SOURCE PCC:YES 1 C9911 1 C9912 1 20% 1% 1/16W MF-LF 2 402 6.3V 6.3V 2 X6S 0201 R9912 130 1UF 10% C PCC:YES BOMOPTION=NOSTUFF 0.1UF XW9900 should be the higher voltage placement should be immediately after the last of the output bulk caps PP3V3_S0_GPU 90 2 X6S-CERM 0201 90 94 97 99 110 PCC:YES 1 R9913 130 1% 1/16W MF-LF 2 402 C PCC:YES 90 PP3V3_VREF_PCC PLACE_NEAR=U9903.3:2.54MM 1 C9910 VCC+ 10PF PCC:YES 1 These pullups remain stuffed even when the PCC circuit is unstuffed 99 97 94 90 110 0 5% 1/20W MF 2 201 PP3V3_S0_GPU 2.0K 5% 1/20W MF 201 2 R9916 2.0K 5% 1/20W MF 201 2 1 1 R9902 10K PCC:YES 5% 1/20W MF 2 201 PCC_POT_WP 0.1UF 10% 2 6.3V X6S 0201 1 C9907 PLACE_NEAR=U9903.1:2.54MM 4.7UF 5% 2 25V C0G 0201 1 PCC:YES LMV331 SC70 4 PCC_COMP_OUT WP* MSOP RH 7 2 BOMOPTION=NOSTUFF 1 SCL RL 6 PCC_POT_RL 99 I2C_GPU_PCC_SDA 3 SDA RW 5 PCC_POT_REF R9906 A 5% 1/20W MF 2 201 1 PCC:YES R9904 0 5% 1/20W MF 2 201 B 2 5% 1/16W MF-LF 402 PCC_POT_LEVEL_D K NSR05F20NXT5G 2 Q9900 PCC_COMP_OUT_BASE 2N3906 1 SOT23-HF 1 3 TP-P6 130 1 1M 5% 1/20W MF 201 2 TP9902 GPU_VCORE_PCC 2 OUT 99 BOMOPTION=NOSTUFF 1 This pulldown remains stuffed even when the PCC circuit is unstuffed PCC:YES C9913 10PF 1 A 2 R9914 33.2K 1% 1/20W MF 2 201 1 C9914 220PF 10% 2 25V X7R-CERM 201 5% 25V C0G 0201 PCC:YES R9905 1 R9909 BOMOPTION=NOSTUFF PCC:YES 4 GND 2 BOMOPTION=NOSTUFF D9900 DSN2 10K PCC_POT_RH I2C_GPU_PCC_SCL 2 1% 1/16W MF-LF 402 C9909 99 130 1% 1/16W MF-LF 402 PCC:YES GND 1 U9910 1 1 PCC:YES R9911 10% 2 6.3V X6S 0201 CAT5140ZI-50-G 2 R9910 20% 2 6.3V CER-X5R 0402 0.1UF VCC 8 R9915 1 C9906 1 PCC:YES U9903 PCC:YES PCC:YES 1 R9903 PCC:YES 5 3 PCC:YES R9908 PCC_POT_LEVEL_R 1 PCC:YES 1 C9908 1 0.01UF R9907 0 2 PCC_POT_LEVEL 1 5% 1/20W MF 0201 TP-P6 A TP9901 10K 10% 10V 2 X5R-CERM 0201 5% 1/20W MF 2 201 B BOMOPTION=NOSTUFF A SYNC_MASTER=X363_SEAN SYNC_DATE=01/27/2016 PAGE TITLE GPU PCC DRAWING NUMBER Apple Inc. 051-00647 REVISION R BOM_COST_GROUP=GRAPHICS NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED WWW.AliSaler.Com 8 7 6 5 4 3 2 10.0.0 1 99 OF 145 90 OF 121 SIZE D A 7 IN PEG_GPU_R2D_C_P<3> IN PEG_GPU_R2D_C_N<3> IN PEG_GPU_R2D_C_P<4> IN PEG_GPU_R2D_C_N<4> 1 1 0.22UF 1 1 20% 0.22UF 1 20% 0.22UF 1 X6S-CERM UA000 0201 X6S-CERM X6S-CERM PEG_GPU_R2D_P<0> 113 PEG_GPU_R2D_N<0> 0201 113 PEG_GPU_R2D_P<1> 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 113 PEG_GPU_R2D_N<1> 113 PEG_GPU_R2D_P<2> 113 PEG_GPU_R2D_N<2> 1 2 20% GND_VOID=TRUE 113 PEG_GPU_R2D_P<3> 6.3V X6S-CERM 0201 113 PEG_GPU_R2D_N<3> 0.22UF 1 GND_VOID=TRUE 6.3V X6S-CERM 113 PEG_GPU_R2D_N<4> PEG_GPU_R2D_C_N<6> GND_VOID=TRUE 0.22UF CA059 1 GND_VOID=TRUE PEG_GPU_R2D_C_P<7> 1 GND_VOID=TRUE 1 X6S-CERM 0201 113 PEG_GPU_R2D_N<5> 20% 6.3V 6.3V PP1V8_S0_GPU 99 1 111 PLACE_NEAR=UA000.AY13:5MM IN EG_PEG_CLK100M_P IN EG_PEG_CLK100M_N 0 RA010 1 2 0201 MF 1/20W 5% BOMOPTION=SPEED 0 RA011 1 1/20W 0 RA013 1 1/20W 1/20W 100 P3V3GPU_EN OUT 100 OUT 100 PCIE_RX5+ PCIE_RX5- 113 PCIE_TX5+ PCIE_RX6+ PCIE_RX6PCIE_RX7+ PCIE_RX7- AV33 AU33 PCIE_REFCLK+ PCIE_REFCLK- AY13 TEST_PG 2 5% 97 P1V35FB_EN P1V35FB_EN OUT 94 2 0201 MF 5% MAKE_BASE=TRUE RA019 2 100K 1 201 RA018 2 100K 1 201 RA017 2 100K 1 201 RA016 2 100K 1 201 RA015 100K 2 180K 1 201 DBGLED_GPU_D DBGLED QA000 DMN5L06VK-7 D 3 IN GPUVCORE_PGOOD 94 IN GPUFB_PGOOD 1 PEG_GPU_D2R_C_N<3> PEG_GPU_D2R_C_P<4> 0.22UF 1 OUT 111 113 PEG_GPU_D2R_P<4> OUT 111 113 PEG_GPU_D2R_N<4> OUT 111 113 PEG_GPU_D2R_P<5> OUT 111 113 PEG_GPU_D2R_N<5> OUT 111 113 PEG_GPU_D2R_P<6> OUT 111 113 PEG_GPU_D2R_N<6> OUT 111 113 PEG_GPU_D2R_P<7> OUT 111 113 PEG_GPU_D2R_N<7> OUT 111 113 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 6.3V X6S-CERM 0201 2 20% GND_VOID=TRUE PEG_GPU_D2R_N<3> 0201 2 20% GND_VOID=TRUE 113 X6S-CERM PEG_GPU_D2R_C_N<4> PEG_GPU_D2R_C_P<5> 0.22UF 1 2 20% GND_VOID=TRUE PEG_GPU_D2R_C_N<5> CA072 0.22UF 1 2 20% GND_VOID=TRUE PEG_GPU_D2R_C_P<6> PEG_GPU_D2R_C_N<6> CA073 0.22UF 1 2 20% GND_VOID=TRUE PEG_GPU_D2R_C_P<7> CA074 PEG_GPU_D2R_C_N<7> 0.22UF 1 2 20% 110 74 PP3V3_S0 110 74 PP3V3_S0_LEFT D 6 S 1 NC RA0221 VER 3 DBGLED_GPU 5 G A DBGLED DA000 GRN-90MCD-5MA-2.85V 0402 S 4 K PLACE_SIDE=BOTTOM SILK_PART=S0_ON P5_S0GPU_PGOOD OUT 89 P3V3_S0GPU_PGOOD OUT 89 P1V8GPU_PGOOD OUT 89 PVDDCI_PGOOD OUT 89 GPUVCORE_PGOOD OUT 89 GPUFB_PGOOD OUT 91 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE Tieing off Ridge GPIOs Both SNK0 and SNK1 shown as always available 91 GPUFB_PGOOD 1 IN 27 101 BI IN 101 OUT 15 OUT 15 SYNC_MASTER=X363_SEAN PM_ALL_GPU_PGOOD 2 MAKE_BASE=TRUE PM_ALL_GPU_PGOOD OUT 89 OUT 97 SYNC_DATE=01/27/2016 PAGE TITLE BAFFIN PCI-E DRAWING NUMBER Apple Inc. PCC:YES 051-00647 REVISION R 1 201 330K 2 RA023 5% 1/20W MF 0201 27 BI PCH pins mirror TBT_X hookup RA020 0 B TBT_X_HDMI_DDC_DATA TBT_X_HDMI_DDC_CLK TBT_T_HDMI_DDC_DATA TBT_T_HDMI_DDC_CLK TBT_X_DPMUX_SEL TBT_T_DPMUX_SEL 20K MAKE_BASE=TRUE A 0.22UF 111 6.3V NC 2 G SOT563 MAKE_BASE=TRUE 97 CA070 PEG_GPU_D2R_C_P<3> VER 3 5% 1/20W MF 201 2 P3V3_S0GPU_PGOOD PVDDCI_PGOOD PEG_GPU_D2R_C_N<2> OUT 0201 2 20% PEG_GPU_D2R_P<3> X6S-CERM D C SPARE MAKE_BASE=TRUE IN AE37 AE38 113 PCIE_TX7- 113 PCIE_TX7+ 1 GND_VOID=TRUE DBGLED P5_S0GPU_PGOOD 97 AG37 AG38 113 PCIE_TX6- 113 PCIE_TX6+ 0.22UF PCC:NO PCC:YES P1V8GPU_PGOOD CA069 PEG_GPU_D2R_C_P<2> 113 6.3V 2 20% 111 1/20W MF 5% 0201 DMN5L06VK-7 PP3V3_S0_GPU PP5V_S0_GPUFET 100 IN AJ37 AJ38 113 PCIE_TX5- 1 OUT GPU_RESET_R_L QA000 OUT 2 90 OUT GPUVCORE_EN 1 201 100 P3V3GPU_EN 2 GPUVCORE_EN 0201 MF MAKE_BASE=TRUE RA021 110 PCIE_RX4+ PCIE_RX4- 0.22UF GND_VOID=TRUE PEG_GPU_D2R_N<2> SOT563 0 RA014 1 1/20W B 5% AL37 AL38 113 PCIE_TX4- 113 PCIE_TX4+ DBGLED RA099 EG_RAIL5_EN 89 RA002 P1V8GPU_EN 0 1 2 TP_PVDDCI_GPU_EN 0201 MF 0 RA012 1 EG_RESET_L IN MAKE_BASE=TRUE 2 EG_RAIL4_EN 89 99 100K EG_RAIL3_EN 89 111 2 0201 MF 5% CA068 PEG_GPU_D2R_C_N<1> 113 RA001 1 201 EG_RAIL2_EN 89 AN37 113 PCIE_TX3+ AN38 113 PCIE_TX3- PEG_GPU_D2R_C_P<1> 111 0201 2 20% OUT X6S-CERM AV41 PERST* PLACE_NEAR=UA000.AY13:5MM 1% 1/20W MF 201 2 EG_RAIL1_EN PCIE_RX3+ PCIE_RX3- 1 GND_VOID=TRUE 1K 89 AM41 AM40 AH41 AH40 GPU_TEST_PG 1 AR37 113 PCIE_TX2+ AR38 113 PCIE_TX2- 0201 2 1% 1/20W MF 201 PCIE_RX2+ PCIE_RX2- 0.22UF GND_VOID=TRUE PEG_GPU_D2R_P<2> 6.3V RA035 110 0201 X6S-CERM 111 1K AP41 AP40 CA075 PEG_GPU_D2R_C_N<0> 113 2 C X6S-CERM 113 PEG_GPU_R2D_N<7> BOMOPTION=BAFFIN RA000 AU38 113 PCIE_TX1+ AU39 113 PCIE_TX1- AJ41 AJ40 113 PEG_GPU_R2D_N<6> 2 GND_VOID=TRUE PCIE_RX1+ PCIE_RX1- PEG_GPU_D2R_C_P<0> 111 100K IN 6.3V 113 PEG_GPU_R2D_P<7> 0.22UF CA061 PEG_GPU_R2D_C_N<7> AR41 AR40 AK41 AK40 113 PEG_GPU_R2D_P<5> 2 20% AV35 113 PCIE_TX0+ AU35 113 PCIE_TX0- OUT 0201 2 20% PEG_GPU_D2R_N<1> X6S-CERM 1 201 IN 0201 113 PEG_GPU_R2D_P<6> 0.22UF CA060 X6S-CERM 2 20% PCIE_RX0+ PCIE_RX0- CA076 6.3V 1 113 2 111 IN 20% 0.22UF 111 6.3V 2 20% OUT 100K 113 111 PEG_GPU_R2D_C_P<6> 1 PEG_GPU_D2R_P<1> 0201 1 201 113 111 IN 2 0.22UF 113 X6S-CERM 2 20% 111 6.3V 100K 113 111 1 1 OUT 0201 1 201 113 0.22UF CA048 AT41 AT40 AL41 AL40 113 PEG_GPU_R2D_P<4> 0201 0.22UF PEG_GPU_D2R_N<0> X6S-CERM 2 20% GND_VOID=TRUE CA071 2 20% CA067 SYM 1 OF 7 0201 113 6.3V 1 GND_VOID=TRUE BGA 6.3V 2 20% 0.22UF CA047 6.3V 0.22UF 113 6.3V 2 20% GND_VOID=TRUE CA066 2 GND_VOID=TRUE PEG_GPU_R2D_C_N<5> BOMOPTION=OMIT_TABLE 2 GND_VOID=TRUE IN CA065 2 20% 0.22UF CA039 0201 1 GND_VOID=TRUE 100-CK4803-ES 1 GND_VOID=TRUE PEG_GPU_R2D_C_P<5> X6S-CERM CA064 2 GND_VOID=TRUE IN 6.3V 20% 0.22UF CA029 0201 0.22UF 111 0201 2 20% GND_VOID=TRUE 2 GND_VOID=TRUE CA028 X6S-CERM 20% GND_VOID=TRUE CA027 6.3V CA063 2 20% 0.22UF CA026 0201 1 GND_VOID=TRUE 2 GND_VOID=TRUE CA025 X6S-CERM 0.22UF OUT X6S-CERM 1 RA034 111 PEG_GPU_R2D_C_N<2> 6.3V CA062 PEG_GPU_D2R_P<0> 6.3V RA033 113 111 IN 0201 20% 0.22UF CA024 X6S-CERM 2 20% 2 113 111 PEG_GPU_R2D_C_P<2> 6.3V 1 GND_VOID=TRUE 100K 113 111 IN 1 GND_VOID=TRUE CA023 20% 0.22UF 1 201 113 111 PEG_GPU_R2D_C_N<1> 0.22UF 0201 2 GND_VOID=TRUE CA022 X6S-CERM 2 113 111 IN 1 6.3V 100K 113 111 PEG_GPU_R2D_C_P<1> 0.22UF 20% 1 201 113 IN GND_VOID=TRUE CA021 CA077 2 RA032 D 111 PEG_GPU_R2D_C_N<0> 1 2 RA031 113 111 IN 0.22UF CA020 2 113 111 PEG_GPU_R2D_C_P<0> 3 100K 113 111 IN 4 1 201 113 111 5 RA030 113 6 2 8 BOM_COST_GROUP=GRAPHICS NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 100 OF 145 SHEET IV ALL RIGHTS RESERVED 8 10.0.0 1 91 OF 121 SIZE D A 8 7 6 5 4 3 2 1 LA100 0.24UH-20%-10A-0.012OHM 92 1 PP1V8_S0_GPU_LC_IC 2 PP1V8_S0_GPU 110 1210 1 CA100 0.1UF 1 CA101 1 0.1UF CA10A 4.7UF 20% 2 6.3V X6S 0402 1 CA102 1UF 10% 2 6.3V X6S 0201 10% 2 6.3V X6S 0201 D 1 20% 2 6.3V X6S-CERM 0201 CA10B 4.7UF 20% 2 6.3V X6S 0402 1 20% 4V 2 X6S-CERM 0402-2 CA103 1UF 110 20% 2 6.3V X6S-CERM 0201 CA10C 10UF 1 BOMOPTION=OMIT_TABLE 1 92 PP1V5R1V35_S0_GPU_IC CA10D 10UF 20% 4V 2 X6S-CERM 0402-2 110 1 92 110 92 10% 2 6.3V X6S 0201 110 92 RA101 1K 1% 1/20W MF 2 201 BOMOPTION=SPEED CA104 0.1UF AC32 AG32 AG35 AJ34 AJ32 W32 AL34 PPVDDCI_S0_GPU 92 1 PP3V3_S0_GPU AC10 AG10 K11 K13 K19 K23 K27 K31 L10 N10 W10 C VDD_33 BA12 AUX_ZVSS C3 92 90 55 110 97 92 OUT PVCORE_GPU_FB_SNS_P AR13 FB_VDDC 94 92 OUT PVDDCI_GPU_FB_SNS_P AV13 FB_VDDCI AU13 FB_VSS SM XWA100 1 2 SHORT-14L-0.1MM-SM 1 2 SHORT-14L-0.1MM-SM 1 2 92 55 PPVDDCI_S0_GPU 1 10 GPU_FB_SNS_COMMON_NEG NO_XNET_CONNECTION=1 GPU_PCIE_ZVSS XWA102 NO_XNET_CONNECTION=1 1 P1V5R1V35_GPU_FB_SNS_P 1% 1/20W MF 2 201 92 94 NO_XNET_CONNECTION=1 RA102 200 BOMOPTION=BAFFIN AU41 1 PCIE_ZVSS RA100 VDDC 150 1% 1/20W MF 2 201 10 1 92 97 NO_XNET_CONNECTION=1 1% 1/20W MF 201 2 PVCORE_GPU_FB_SNS_P 2 PVDDCI_GPU_FB_SNS_P 92 94 NO_XNET_CONNECTION=1 1% 1/20W MF 201 RA113 10 1 2 GPU_FB_SNS_COMMON_NEG 92 NO_XNET_CONNECTION=1 1% 1/20W MF 201 B VDDC PP1V5R1V35_S0_GPU_IC 92 110 1 CA105 0.1UF 10% 2 6.3V X6S 0201 1 1 0.1UF 10% 2 6.3V X6S 0201 CA112 1 20UF CA117 2.2UF 20% 2 4V X6S-CERM 0201 CA107 0.1UF 10% 2 6.3V X6S 0201 CA113 10UF 20% 2 2.5V X6S-CERM 0402-1 1 CA106 1 20% 2 4V X6S-CERM 0402-2 1 CA118 2.2UF 20% 2 4V X6S-CERM 0201 1 CA119 2.2UF 20% 2 4V X6S-CERM 0201 1 CA108 0.1UF 10% 2 6.3V X6S 0201 1 1 CA109 0.1UF CA114 1000PF CA120 2.2UF 20% 4V 2 X6S-CERM 0201 12PF CA115 1000PF 5% 2 25V CERM 0402 1 CA110 5% 2 25V NP0-C0G 0201 10% 6.3V 2 X6S 0201 1 1 5% 2 25V CERM 0402 1 CA121 12PF 5% 2 25V NP0-C0G 0201 1 1 CA111 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 1 1 AA13 AA15 AA21 AA23 AA29 AA31 AC13 AC15 AC21 AC23 AC29 AC31 AE13 AE15 AE21 AE23 AE29 AE31 AG13 AG15 AG21 AG23 AG29 AG31 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 PPVCORE_S0_GPU 55 90 92 110 110 CA199 3.1PF +/-0.05PF 2 25V C0G-CERM 0201 CA116 1000PF 5% 2 25V CERM 0402 VDDCI 92 90 55 PPVCORE_S0_GPU 1 CA125 3 1 AA11 AE11 L13 L17 L21 L25 L29 N11 U11 3 CA129 1 20UF CA136 1 1 1 1 2.2UF 1 CA147 1 CA132 1 CA138 1 1 2.2UF 1 1 CA150 1 CA134 1 CA140 1 1 2.2UF 1 1 CA152 1 CA177 1 CA142 CA143 1 2.2UF 20% 2 4V X6S-CERM 0201 CA153 CA178 220UF 20% 2 2V ELEC SM-COMBO 3 3 1 20% 2 2V ELEC SM-COMBO CA144 2.2UF 20% 2 4V X6S-CERM 0201 1 CA145 2.2UF 20% 2 4V X6S-CERM 0201 CA154 1 12PF +/-0.1PF 2 25V NP0-C0G 0201 20% 2 2V ELEC SM-COMBO 220UF 20% 2 4V X6S-CERM 0201 3.0PF 5% 2 25V NP0-C0G 0201 CA135 2.2UF 20% 2 4V X6S-CERM 0201 CA151 3 20% 2 2.5V X6S-CERM 0402-1 CA141 D CA176 220UF 20UF 20% 2.5V 2 X6S-CERM 0402-1 12PF 20% 2 4V X6S-CERM 0201 1 20% 2 2V ELEC SM-COMBO 20UF 20% 2 4V X6S-CERM 0201 2.2UF 20% 2 4V X6S-CERM 0201 CA133 2.2UF 20% 2 4V X6S-CERM 0201 CA148 3 20% 2 2.5V X6S-CERM 0402-1 CA139 CA128 220UF 20UF 20% 2.5V 2 X6S-CERM 0402-1 2.2UF 20% 2 4V X6S-CERM 0201 1 20% 2 2V ELEC SM-COMBO 20UF 20% 2 4V X6S-CERM 0201 2.2UF 20% 2 4V X6S-CERM 0201 CA131 2.2UF 20% 2 4V X6S-CERM 0201 CA146 3 20% 2 2.5V X6S-CERM 0402-1 CA137 CA127 220UF 20UF 2.2UF 20% 2 4V X6S-CERM 0201 92 CA130 20% 2 2.5V X6S-CERM 0402-1 2.2UF 1 1 20% 2 2V ELEC SM-COMBO 20UF 20% 2 2.5V X6S-CERM 0402-1 1 CA126 220UF 20% 2 2V ELEC SM-COMBO AJ27 AJ29 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 N13 N15 N21 N23 N29 N31 R13 R15 R21 R23 R29 R31 U13 U15 U21 U23 U29 U31 W13 W15 W21 W23 W29 W31 AJ31 AL31 1 220UF 110 RA111 RA112 110 92 FB_VMEMIO XWA101 PVDDCI_GPU_FB_SNS_N 2 1% 1/20W MF 201 PPVCORE_S0_GPU VDD_18 P1V5R1V35_GPU_FB_SNS_P RA110 1 VDD_08 AM31 NO_XNET_CONNECTION=1 PP1V5R1V35_S0_GPU_MEM VDDC 94 92 OUT 94 OUT 110 VMEMIO PP3V3_S0_GPU PVCORE_GPU_FB_SNS_N 10 BGA SYM 5 OF 7 AM15 AP15 AR15 P1V5R1V35_GPU_FB_SNS_N 97 94 OUT 100-CK4803-ES PP1V8_S0_GPU_LC_IC VOLTAGE=1.8V GPU_AUX_ZVSS 94 OUT UA000 C 3.0PF 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 PPVDDCI_S0_GPU 1 CA11A 1UF 20% 2 6.3V X6S-CERM 0201 1 CA11B 1UF 20% 2 6.3V X6S-CERM 0201 CA11C 1 1 4.7UF CA11D 4.7UF 20% 2 6.3V X6S 0402 20% 2 6.3V X6S 0402 1 CA11E 10UF 20% 4V 2 X6S-CERM 0402-2 1 CA11F 10UF 20% 2 4V X6S-CERM 0402-2 PPVDDCI_S0_GPU 110 92 55 CA155 1 1 1UF CA156 1UF 20% 2 6.3V X6S-CERM 0201 20% 2 6.3V X6S-CERM 0201 1 CA157 1UF 20% 2 6.3V X6S-CERM 0201 1 CA158 12PF 5% 2 25V NP0-C0G 0201 1 CA159 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 B CA160 1 1 0.1UF 0.1UF 10% 2 6.3V X6S 0201 PPVDDCI_S0_GPU CA161 10% 2 6.3V X6S 0201 1 CA162 0.1UF 10% 2 6.3V X6S 0201 1 CA163 1UF 20% 2 6.3V X6S-CERM 0201 1 CA164 1UF 20% 2 6.3V X6S-CERM 0201 1 CA165 1UF 20% 2 6.3V X6S-CERM 0201 1 CA166 12PF 5% 2 25V NP0-C0G 0201 1 CA167 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 55 92 110 1 CA168 1 220UF 3 CA169 1 220UF 20% 2 2V ELEC SM-COMBO 3 1 5% 2 25V NP0-C0G 0201 20% 2 2V ELEC SM-COMBO CA172 1000PF 5% 2 25V CERM 0402 A 1 220UF 3 CA149 12PF CA170 CA173 10UF 20% 2 10V X6S-CERM 0603 1 220UF 20% 2 2V ELEC SM-COMBO 3 CRITICAL 1 CA171 CA175 220UF 20% 2 2V ELEC SM-COMBO 3 20% 2 2V ELEC SM-COMBO CRITICAL 1 CA174 10UF 20% 2 10V X6S-CERM 0603 SYNC_MASTER=X363_SEAN PAGE TITLE CRITICAL 1 CA122 CRITICAL 1 10UF CA123 10UF 20% 2 10V X6S-CERM 0603 20% 10V 2 X6S-CERM 0603 CRITICAL 1 SYNC_DATE=02/01/2016 Baffin CORE/FB POWER CA124 DRAWING NUMBER 10UF Apple Inc. 20% 2 10V X6S-CERM 0603 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=GRAPHICS II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 101 OF 145 SHEET IV ALL RIGHTS RESERVED 8 10.0.0 1 92 OF 121 SIZE D A 8 7 6 5 4 3 D 95 113 95 BI 113 95 BI 113 95 113 95 95 BI 113 95 BI 113 113 95 BI 113 95 BI 113 95 BI 113 95 BI 113 95 BI 113 95 BI 113 95 BI 113 95 113 95 BI 113 95 BI 113 95 BI 113 95 BI 95 113 95 BI 113 95 BI 113 95 BI 113 95 BI 95 95 95 113 95 BI 95 113 95 BI 113 95 BI 113 95 BI 113 95 BI FB_A0_DQ<15> FB_A0_DQ<16> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<19> FB_A0_DQ<20> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<23> FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<26> FB_A0_DQ<27> FB_A0_DQ<28> FB_A0_DQ<29> FB_A0_DQ<30> FB_A0_DQ<31> FB_A1_DQ<1> FB_A1_DQ<2> FB_A1_DQ<3> FB_A1_DQ<4> FB_A1_DQ<5> FB_A1_DQ<6> FB_A1_DQ<7> FB_A1_DQ<8> FB_A1_DQ<9> FB_A1_DQ<10> BI 95 95 113 95 BI 113 95 BI 113 95 BI FB_A1_DQ<11> BI FB_A1_DQ<12> BI 113 95 113 95 113 95 BI 113 95 BI 113 95 BI FB_A1_DQ<13> FB_A1_DQ<14> FB_A1_DQ<15> FB_A1_DQ<16> BI FB_A1_DQ<17> BI 113 95 113 95 113 95 BI 113 95 BI 113 95 BI FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<20> FB_A1_DQ<21> BI FB_A1_DQ<22> BI FB_A1_DQ<23> FB_A1_DQ<24> FB_A1_DQ<25> FB_A1_DQ<26> BI FB_A1_DQ<27> BI 113 95 BI 113 95 BI 113 95 BI 113 95 BI B27 A27 B26 A26 A24 B23 A23 B22 B20 A20 B19 A19 B17 A16 B16 A15 B15 A14 B14 B13 A11 B11 A10 B10 B8 A7 B7 A6 A4 B4 A3 B3 FB_A1_DQ<0> BI 113 95 FB_A0_DQ<14> BI 113 95 FB_A0_DQ<13> BI 113 113 FB_A0_DQ<12> BI BI 113 FB_A0_DQ<11> BI 95 95 FB_A0_DQ<10> BI 95 95 FB_A0_DQ<9> BI 113 113 FB_A0_DQ<8> BI 113 113 FB_A0_DQ<7> BI 113 95 FB_A0_DQ<6> BI BI 113 FB_A0_DQ<5> BI 95 113 FB_A0_DQ<4> BI 113 113 B 95 FB_A0_DQ<3> BI 95 95 FB_A0_DQ<2> BI 113 113 FB_A0_DQ<1> BI 113 L34 L37 L38 J35 G37 E38 E35 D35 H41 H40 G41 G40 E40 D41 D40 C41 C40 B39 A39 B38 B36 A36 B35 A35 B33 B32 A32 B31 A30 B29 B28 A28 FB_A0_DQ<0> BI 113 113 C 95 FB_A1_DQ<28> FB_A1_DQ<29> FB_A1_DQ<30> FB_A1_DQ<31> 93 DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 UA000 100-CK4803-ES BGA SYM 3 OF 7 MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 G25 H25 E27 D27 D29 H27 H23 E23 MAA1_0 MAA1_1 MAA1_2 MAA1_3 MAA1_4 MAA1_5 MAA1_6 MAA1_7 E15 H15 G13 D13 H11 H13 H17 G17 FB_A0_A<0> FB_A0_A<2> FB_A0_A<3> FB_A0_A<4> FB_A0_A<5> FB_A0_A<6> FB_A0_A<7> FB_A1_A<0> FB_A1_A<1> FB_A1_A<2> FB_A1_A<3> FB_A1_A<4> FB_A1_A<5> FB_A1_A<6> FB_A1_A<7> FB_A0_WCLK_N<0> FB_A0_WCLK_P<1> WCKA1_0 A22 WCKA1_0* B21 FB_A1_WCLK_N<0> WCKA1_1 A8 WCKA1_1* B9 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31 B24 A18 B12 B6 DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3 J38 F40 A38 B30 FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3> FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3> FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A1_DBI_L<2> FB_A1_DBI_L<3> K15 MEM_CALRA FB_A_CALR 1 RA202 120 DRAM_RSTA L32 1% 1/20W MF 2 201 NOSTUFF OUT 96 113 96 OUT 113 96 BI 113 96 95 113 BI OUT 113 96 BI OUT 95 113 OUT 95 113 OUT 95 113 OUT 95 113 OUT 95 113 FB_A1_CKE_L FB_A0_WE_L FB_A1_WE_L FB_A1_A<8> FB_A_RESET_PIN_L 1 1 RA290 5.1K 110 93 1% 1/20W MF 2 201 PP1V5R1V35_S0_GPU_IC 96 BI 113 96 BI 113 96 BI 113 96 BI 96 BI 113 96 BI 113 96 BI 113 96 BI 95 113 OUT 95 113 113 96 BI OUT 95 113 113 96 BI 113 96 BI 113 96 BI 113 96 BI 95 113 95 113 OUT 95 113 113 96 BI OUT 95 113 113 96 BI OUT 95 113 113 96 OUT 95 113 113 96 OUT 95 113 OUT 95 113 113 96 113 96 96 OUT 113 96 BI 113 96 BI 95 113 96 BI 113 96 BI 113 96 BI 113 96 BI 113 96 BI 95 113 95 113 BI 95 113 113 96 BI 95 113 113 96 95 113 95 113 95 113 96 96 113 96 BI 113 96 BI 113 96 BI 95 113 95 113 96 96 113 96 BI 113 96 BI 113 96 BI 95 113 96 96 113 96 BI 113 96 BI 113 96 BI 96 BI 113 96 BI 113 96 BI 113 96 BI 95 113 113 96 BI OUT 95 113 113 96 BI OUT 95 113 95 113 OUT 95 113 FB_B0_DQ<19> FB_B0_DQ<20> FB_B0_DQ<21> FB_B0_DQ<22> FB_B0_DQ<23> FB_B0_DQ<24> FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27> FB_B0_DQ<28> FB_B0_DQ<29> FB_B0_DQ<30> FB_B0_DQ<31> FB_B1_DQ<1> FB_B1_DQ<2> FB_B1_DQ<3> FB_B1_DQ<4> FB_B1_DQ<5> FB_B1_DQ<6> FB_B1_DQ<7> FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11> FB_B1_DQ<12> FB_B1_DQ<13> FB_B1_DQ<14> FB_B1_DQ<15> FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<18> FB_B1_DQ<19> FB_B1_DQ<20> FB_B1_DQ<21> FB_B1_DQ<22> FB_B1_DQ<23> FB_B1_DQ<24> FB_B1_DQ<25> FB_B1_DQ<26> FB_B1_DQ<27> FB_B1_DQ<28> FB_B1_DQ<29> FB_B1_DQ<30> FB_B1_DQ<31> 1 99 PP3V3_S0_GPU 2 NOSTUFF 10K 1 RA204 40.2 1% 1/20W MF 201 2NOSTUFF A 1 RA206 100 1% 1/20W MF 2 201 NOSTUFF SYM 4 OF 7 R5 R8 N7 N4 L8 N8 U8 U7 MAB1_0 MAB1_1 MAB1_2 MAB1_3 MAB1_4 MAB1_5 MAB1_6 MAB1_7 AE7 AE8 AG5 AG4 AJ4 AG8 AC8 AC5 RA201 1 2 FB_A_RESET_L OUT 95 1 10K FB_B0_A<2> FB_B0_A<3> FB_B0_A<4> FB_B0_A<5> FB_B0_A<6> FB_B0_A<7> FB_B1_A<0> FB_B1_A<1> FB_B1_A<2> FB_B1_A<3> FB_B1_A<4> FB_B1_A<5> FB_B1_A<6> FB_B1_A<7> FB_B0_WCLK_P<0> FB_B0_WCLK_N<0> FB_B0_WCLK_P<1> FB_B0_WCLK_N<1> FB_B1_WCLK_P<0> FB_B1_WCLK_N<0> WCKB1_1 AN4 WCKB1_1* AN5 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31 EDCB0_0 EDCB0_1 EDCB0_2 EDCB0_3 F2 M2 V1 AD2 EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3 AL1 AU2 BA6 AV7 DDBIB0_0 DDBIB0_1 DDBIB0_2 DDBIB0_3 E2 M1 V2 AE2 DDBIB1_0 DDBIB1_1 DDBIB1_2 DDBIB1_3 AK2 AV1 AY6 AV9 FB_B1_WCLK_P<1> FB_B1_WCLK_N<1> FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3> FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3> OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 FB_B0_DBI_L<2> FB_B0_DBI_L<3> FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3> FB_B0_ABI_L FB_B1_ABI_L FB_B0_CLK_P FB_B0_CLK_N CLKB1 AL5 CLKB1* AL4 FB_B1_CLK_P FB_B1_CLK_N RASB0* W4 RASB1* AA4 FB_B0_RAS_L FB_B1_RAS_L CASB0* U4 CASB1* AC4 FB_B0_CAS_L FB_B1_CAS_L CSB0_0* G5 FB_B0_CS_L CSB1_0* AL8 FB_B1_CS_L CKEB0 W5 CKEB1 AA7 FB_B0_CKE_L FB_B1_CKE_L WEB0* L4 WEB1* AJ7 FB_B0_WE_L FB_B1_WE_L MAB0_8 R4 MAB0_9 L5 NC FB_B0_A<8> MAB1_8 AE4 MAB1_9 AJ8 NC DRAM_RSTB AM11 96 113 FB_B0_DBI_L<1> CLKB0 G4 CLKB0* J4 RA203 OUT FB_B0_DBI_L<0> ADBIB0 W8 ADBIB1 AA8 FB_B1_A<8> RA296 FB_B_RESET_PIN_L 1 10 BI 96 113 BI 96 113 BI 96 113 BI 96 113 BI 96 113 BI 96 113 BI 96 113 BI 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 113 OUT 96 OUT 96 113 OUT 96 113 1 PLACE_NEAR=UA000.R10:2.54MM 1 1 RA295 93 B 49.9 2 FB_B_RESET_L OUT CA295 10% 25V 2 X7R 0201 PP1V5R1V35_S0_GPU_IC RA205 40.2 1% 1/20W MF 201 2NOSTUFF PLACE_NEAR=UA000.U10:2.54MM note: to be unstuffed after initial baffin bringup SYNC_MASTER=J80_SEAN FB_B_MVREFD 93 PLACE_NEAR=UA000.U10:2.54MM PAGE TITLE 93 PLACE_NEAR=UA000.U10:2.54MM CA200 1 1UF RA207 100 20% 2 6.3V X6S-CERM 0201 NOSTUFF 1% 1/20W MF 2 201 NOSTUFF 1 SYNC_DATE=04/29/2015 Baffin FRAME BUFFER I/F DRAWING NUMBER CA201 Apple Inc. 1UF 20% 2 6.3V X6S-CERM 0201 NOSTUFF 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE BOM_COST_GROUP=GRAPHICS II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 6 5 4 3 2 102 OF 145 SHEET IV ALL RIGHTS RESERVED 7 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 8 96 120PF 1% 1/20W MF 2 201 10% 2 25V X7R 0201 C 1% 1/20W MF 201 5.1K 120PF D RA297 FB_B_RESET_R_L 2 1% 1/20W MF 201 1% 1/20W MF 2 201 NOSTUFF CA290 FB_B0_A<1> WCKB1_0 AP1 WCKB1_0* AP2 120 5% 1/20W MF 201 2 FB_B0_A<0> WCKB0_1 AB1 WCKB0_1* AA2 R10 MEM_CALRB FB_B_CALR note: to be unstuffed after initial baffin bringup 1 MAB0_0 MAB0_1 MAB0_2 MAB0_3 MAB0_4 MAB0_5 MAB0_6 MAB0_7 WCKB0_0 H1 WCKB0_0* J2 AE40 TESTEN GPU_TEST_EN PLACE_NEAR=UA000.K17:2.54MM 1 BGA 1 FB_A_MVREFD PLACE_NEAR=UA000.K17:2.54MM 100-CK4803-ES 5% 1/20W MF 201 110 PLACE_NEAR=UA000.K17:2.54MM UA000 U10 MVREFDB FB_B_MVREFD 95 113 49.9 AH1 AH2 AJ2 AK1 AL2 AM1 AM2 AN2 AR1 AR2 AT1 AT2 AV2 AW1 AW2 AY3 BA3 AY4 BA4 AY5 BA7 AY7 AY8 BA8 AR4 AR5 AU4 AU7 AN8 AV11 AU11 AP11 FB_B1_DQ<0> DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 RA200 1% 1/20W MF 201 1 FB_B0_DQ<18> 93 RA293 FB_A_RESET_R_L FB_B0_DQ<17> BI OUT OUT FB_B0_DQ<16> BI 113 95 113 FB_B0_DQ<15> BI 113 95 113 FB_B0_DQ<14> BI 113 95 113 FB_B0_DQ<13> BI 113 95 113 FB_B0_DQ<12> BI 113 95 113 FB_B0_DQ<11> BI 113 95 113 FB_B0_DQ<10> BI 113 95 113 FB_B0_DQ<9> BI 113 95 113 FB_B0_DQ<8> BI 113 BI FB_B0_DQ<7> BI 95 113 95 113 FB_B0_DQ<6> BI 95 113 BI FB_B0_DQ<5> BI OUT 1% 1/20W MF 201 PLACE_NEAR=UA000.K15:2.54MM 113 113 OUT 2 BI 95 113 RA291 10 96 OUT 110 FB_A0_A<8> 113 BI OUT FB_A0_CKE_L BI 96 OUT FB_A1_CS_L 96 113 OUT FB_A0_CS_L 113 95 113 OUT FB_A1_CAS_L BI OUT OUT FB_A0_CAS_L 96 95 113 FB_B0_DQ<4> BI 113 95 113 FB_B0_DQ<3> BI 95 113 OUT FB_B0_DQ<2> BI 95 113 95 113 FB_B0_DQ<1> BI OUT OUT FB_A1_RAS_L MAA1_8 D15 MAA1_9 E11 NC 96 113 OUT FB_A0_RAS_L MAA0_8 D25 MAA0_9 H29 NC 113 95 113 OUT FB_A1_CLK_N WEA0* G29 WEA1* D11 95 113 OUT FB_A1_CLK_P CKEA0 G21 CKEA1 E19 OUT OUT FB_A0_CLK_N CSA1_0* E7 BI OUT FB_A0_CLK_P CSA0_0* H31 96 OUT FB_A1_ABI_L CASA0* D23 CASA1* D17 113 BI FB_A0_ABI_L RASA0* D21 RASA1* D19 95 113 BI FB_A1_DBI_L<1> CLKA1 D7 CLKA1* D9 OUT BI FB_A1_DBI_L<0> CLKA0 E31 CLKA0* D31 BI BI FB_A0_DBI_L<3> ADBIA0 H21 ADBIA1 H19 OUT 96 OUT FB_A0_EDC<0> B25 B18 A12 B5 96 113 C2 C1 D2 D1 F1 G2 G1 H2 K2 K1 L2 L1 N2 P2 P1 R2 R1 T2 T1 U2 W1 W2 Y1 Y2 AB2 AC1 AC2 AD1 AF1 AF2 AG1 AG2 FB_B0_DQ<0> BI 113 OUT FB_A1_WCLK_N<1> G38 F41 B37 A31 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3 DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3 FB_A1_WCLK_P<1> 96 95 113 OUT FB_A1_WCLK_P<0> 113 95 113 OUT FB_A0_WCLK_N<1> 95 113 OUT OUT FB_A0_WCLK_P<0> WCKA0_1 A34 WCKA0_1* B34 EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 OUT FB_A0_A<1> WCKA0_0 D33 WCKA0_0* E33 K17 MVREFDA FB_A_MVREFD 1 BOMOPTION=OMIT_TABLE BOMOPTION=OMIT_TABLE 113 2 1 93 OF 121 SIZE D A 8 7 6 5 4 109 110 PP3V3_S0_GPU 99 97 90 110 PP5V_S0 3 RA330 RA310 BOMOPTION=BAFFIN 1 RA331 10K 5% 1/20W MF 2 201 D MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V 1 CA310 2.2UF BOMOPTION=SPEED RA301 92 IN 1 P1V5R1V35_GPU_FB_SNS_P VCC 10% 2 16V X6S-CERM 0603 91 IN 1.62K 2 1% 1/20W MF 201 1 RA305 1 191K 92 IN 1 P1V5R1V35_GPU_FB_SNS_N 5% 2 50V C0G 0201 1.62K 2 91 NOSTUFF RA309 CA305 NOSTUFF C CA303 1 10PF 5% C0G 2 0201 50V RA3031 4.64K 0.1% 1/20W MF 0201 2 NOSTUFF RA3041 4.64K CA304 0.1% 1/20W MF 0201 2 1 0 1 2 5% 1/20W MF 0201 12 VO CRITICAL MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0850 SWITCH_NODE=TRUE DIDT=TRUE LGATE 1 14 4 GPUFB_SET0 SET0 GPUFB_SET1 9 SET1 6 VID0 2 16V TANT-POLY CASE-B3 20% 2 25V X6S-CERM 0402 QA300 2.2UF 5% 25V 2 CERM 0402 GPU FB SUPPLY VOUT = 1.5V / 1.35V 10.7A MAX OUTPUT F = 500 KHZ 5% 1/16W 1 MF-LF 402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE RA300 0.002 LA300 0.68UH-20%-14A 1 8 2 6 PP1V5R1V35_GPU_REG_R 1 3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V PILE063T-COMBO 55 OUT 55 OUT 1% 1/2W MF 0306 2 4 CA330 1 GPUFB_CS_P XWA301 CA332 1 CA333 1 20% 2V 2 ELEC SM-COMBO 20% 2V 2 ELEC SM-COMBO 220UF XWA302 2 GPUFB_GPU_OCSET_R RA315 3 20% 2V 2 ELEC SM-COMBO 3 3 2200PF 2 1 VID1 10% 16V CERM 0201 2 1% 1/20W MF 201 2 3 220UF CA319 RA316 4.53K 1 220UF GPUFB_GPU_VO_R 1% 1/20W MF 201 2 XWA300 SM CA335 1 1 1 4.53K 1 5% 25V CERM 2 0402 3 2 SM PGND 1 1000PF 20% 2V 2 ELEC SM-COMBO 3 110 116 CA334 220UF 20% 2V 2 ELEC SM-COMBO GPUFB_CS_N 5 CA331 1 220UF 1 GND D PP1V5R1V35_S0_GPU_MEM SM FBVDD_ALTVO GPUFB_AGND CA326 1000PF 20% 2 25V X6S-CERM 0402 CRITICAL SIZ710DT CRITICAL VID1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 CRITICAL RA307 0.1% 1/20W MF 2 0201 5% C0G 2 0201 50V 20% CA325 1 2.2UF 2 16V TANT-POLY CASE-B3 16.9K 10PF 1 7 POWERPAK-6X3.7 3 4 8 5 2 RTN FSEL 20% CA324 CA323 33UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE PGOOD GPUFB_FSEL 33UF 2 16V TANT-POLY CASE-B3 GPUFB_DRVH 1 1 GPUFB_DRVL 11 OCSET 13 94 GPUFB_LL PHASE 16 SREF 2 RA312 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE UGATE 17 CA322 376S0959 GPUFB_DRVH_R BOOT 18 CRITICAL 1 GPUFB_SET_R 1 1 GPUFB_VO 5% 1/20W MF 201 2 RA308 0.01UF 10% 2 10V X7R-CERM 0201 7 0 95.3K 1 GPUFB_SREF GPUFB_RTN_DIV RA306 0.1% 1/20W MF 2 0201 10 FB GPUFB_PGOOD OUT 1% 1/20W MF 201 1 GPUFB_SENSE_DIV GPUFB_OCSET 22PF 0.1% 1/20W MF 2 0201 RA302 CA306 UTQFN 15 EN 10% 16V 2 X7R-CERM 0402 MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0850 DIDT=TRUE ISL95870AH CA321 20% 2 16V TANT-POLY CASE-B3 0.1UF CRITICAL 1 33UF GPUFB_VBST UA300 P1V35FB_EN CA320 20% CA311 1 5% 1/16W MF-LF 402 2 PVCC CRITICAL 1 33UF 0 PP5V_S0GPU_P1V35_GPU 94 1 RA3111 20 FBVDD_ALTVO CA318 20% 2 10V X6S-CERM 0603 5% 1/16W MF-LF 402 2 CRITICAL MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0850 DIDT=TRUE 10UF 2.2 19 5% 1/20W MF 2 201 1 2 10K 1 1 PPBUS_HS_GPU GPUFB_BOOT_RC 1 2 VID0 FBVDD C 0 0 1.5V 1 0 1.35V PLACE_NEAR=UA300.3:1mm GPU VDDCI SUPPLY VOUT = 0.8V-0.9V REG_BOOT_GPU_VDDCI_RC PVDDCI_GPU_FB_SNS_P 1 NOSTUFF NO_XNET_CONNECTION=1 1 CA380 0.1UF 92 IN 10% 2 16V X5R-CERM 0201 PVDDCI_GPU_FB_SNS_N RA393 97 92 IN PVCORE_GPU_FB_SNS_N 1 NO_XNET_CONNECTION=1 97 OUT 0 1 0 5% 1/20W MF 2 0201 5% 1/20W MF 0201 CA381 10% 2 10V X7R-CERM 0201 REG_GPU_VDDCI_VSEN B 1% 1/20W MF 2 201 REG_GPU_VDDCI_FB NOSTUFF 97 1 97 RA383 30 1% 1/20W MF 2 201 1 100PF 5% 2 25V C0G 0201 97 OUT IN IN CRITICAL 1 RA366 MIN_NECK_WIDTH=0.2000 IN IN 1 1 5% 1/16W MF-LF 402 2 REG_UGATE_GPU_VDDCI 3 TG DIDT=TRUE 6 7 8 GATE_NODE=TRUE MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000 4 TGR VSW MIN_LINE_WIDTH=0.6000 5 BG 1 CA354 EMC PLACE_NEAR=QA350.1:4mm 1 2.2UF CA355 2.2UF 20% 2 25V X6S-CERM 0402 20% 2 25V X6S-CERM 0402 Note: Regulator requires a minimum load to prevent noise in the audio frequencies 0.002 0.2UH-20%-28A-0.0011OHM 1 2 VRVDDCI_R VR_PHASE_GPU_VDDCI PILA63T-SM NOSTUFF 2 4 1% 1/2W MF 0306 1 3 CA366 1 PPVDDCI_S0_GPU RA369 200 5% 1/16W MF-LF 2 402 REG_SNUBBER_GPU_VDDCI NOSTUFF RA367 5% 1/10W MF-LF 2 603 CA383 10% 2 10V X7R-CERM 0201 REG_GPU_VDDCI_COMP RA385 RA391 97 OUT REG_GPU_VDDCI_ISUMP 1 CA390 97 OUT REG_GPU_VDDCI_ISUMN 1 3.09K 2 1% 1/20W MF 201 REG_GPU_VDDCI_FCCM REG_GPU_VDDCI_IMON 1 2 REG_GPU_VDDCI_VSUMP 1% 1/20W MF 201 1 10% 10V CERM 2 201 1K CA391 0.1UF 10% 2 16V X5R-CERM 0201 2 1 XWA354 SM 2 RA392 REG_GPU_VDDCI_VSUMN_R XWA353 SM 1 1.00 2 1 VDDCIS0_CS_P OUT 55 VDDCIS0_CS_N OUT 55 REG_GPU_VDDCI_VSUMN 1% 1/20W MF-LF 0201 SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/08/2015 PAGE TITLE Baffin 1V05 GPU / 1V35 FB Power Supply DRAWING NUMBER 97 OUT REG_GPU_VDDCI_ISEN1 Apple Inc. 051-00647 REVISION R 1 RA386 10K 1% 1/20W MF 2 201 1 RA387 365K 1% 1/20W MF 2 201 1 CA384 1000PF 10% 2 16V X7R-1 0201 1 RA389 121K 1% 1/20W MF 2 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 6 5 4 3 2 103 OF 145 SHEET IV ALL RIGHTS RESERVED 7 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=GRAPHICS 8 B 110 2.2 RA390 OUT CA353 5% 2 25V CERM 0402 2 25V NP0-C0G 0201 10% 2 50V X7R-CERM 0402 5600PF 97 1 1000PF +/-0.1PF 25V RA368 LA350 1 1% 1/20W MF 2 201 OUT 2 16V TANT-POLY CASE-B3 3.0PF 0.001UF 41.2K 97 2 16V TANT-POLY CASE-B3 CA352 EMC PLACE_NEAR=QA350.1:4mm 3300PF 1 A 2 16V TANT-POLY CASE-B3 20% 5% 2 NP0-C0G 0201 1 12PF CRITICAL 1 REG_PHASE_GPU_VDDCI REG_LGATE_GPU_VDDCI REG_GPU_VDDCI_FB_R 1 20% CRITICAL CA351 CA358 33UF CRITICAL GATE_NODE=TRUE DIDT=TRUE 1% 1/20W MF 2 201 33UF 20% 2 16V TANT-POLY CASE-B3 CA357 1 CSD58873Q3D MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000 RA384 33UF 20% QA350 CA356 CRITICAL CRITICAL 1 Q3D RA365 GATE_NODE=TRUE SWITCH_NODE=TRUE 97 CA350 CRITICAL 1 VIN 1 REG_UGATE_GPU_VDDCI_R DIDT=TRUE CRITICAL 1 33UF APN376S1005 CRITICAL DIDT=TRUE DIDT=TRUE NOSTUFF 9.09K CA382 PPBUS_HS_GPU REG_BOOT_GPU_VDDCI MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 97 1 109 5% 1/16W MF-LF 2 402 MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000 REG_GPU_VDDCI_VSEN_C RA382 F = 450 KHZ 2.2 3300PF 499 OUT 1 1 1 97 10% 2 16V X7R-CERM 0402 RA380 2 CA365 0.1UF NO_XNET_CONNECTION=1 ?9.7A? MAX OUTPUT PGND IN 9 92 1 94 OF 121 SIZE D A 8 7 6 5 4 3 2 1 UA450 UA400 32MX32-1.25GHZ-MFL 32MX32-1.25GHZ-MFL BGA BGA H5GQ1H24AFR-T2C H5GQ1H24AFR-T2C 113 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 95 113 113 93 IN 93 IN 113 93 IN 96 95 PP1V5R1V35_S0_GPU_MEM 110 CK TERMINATION - A0 PLACE_NEAR=UA400.J11:8.4MM D RA401 60.4 FB_A0_CLK_P 1 95 93 113 2 1 1% 1/20W MF 201 PLACE_NEAR=UA400.J12:8.4MM RA402 60.4 FB_A0_CLK_N 2 1% 1/20W MF 201 H11 FB_A0_A<2> K10 FB_A0_A<5> K11 FB_A0_A<4> FB_A0_A<3> H10 FB_A0_A<7> K4 H5 FB_A0_A<1> H4 FB_A0_A<0> K5 FB_A0_A<6> J3 FB_A0_CKE_L 1% 1/20W MF 201 113 95 93 IN 113 95 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 IN J12 FB_A0_CLK_P J11 FB_A0_CLK_N G12 FB_A0_CS_L L12 FB_A0_WE_L L3 FB_A0_CAS_L G3 FB_A0_RAS_L J13 1 2 RA403 120 1% 1/20W MF 201 1% 1/20W MF 201 2 95 93 1 113 2 113 PLACE_NEAR=UA450.J11:8.4MM 1 C PLACE_NEAR=UA450.J12:8.4MM RA451 60.4 J10 FB_A0_SEN 93 93 IN IN BI 113 93 BI 113 93 BI 113 93 BI PP1V5R1V35_S0_GPU_MEM CK TERMINATION - A1 FB_A1_CLK_P J1 FB_A0_MF 1 RA404 120 2 RA452 60.4 1 1% 1/20W MF 201 (1 OF 2) A8/A7 A9/A1 A10/A0 A11/A6 CKE* OMIT_TABLE FB_A0_ZQ RA400 120 BA0/A2 BA1/A5 BA2/A4 BA3/A3 FB_A1_CLK_N 2 113 93 IN 113 93 IN J2 FB_A_RESET_L J4 FB_A0_ABI_L C2 FB_A0_EDC<0> C13 FB_A0_EDC<1> R13 FB_A0_EDC<2> R2 FB_A0_EDC<3> D4 FB_A0_WCLK_P<0> D5 FB_A0_WCLK_N<0> CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET* ABI* EDC0 EDC1 EDC2 EDC3 WCK01 WCK01* 113 93 95 1% 1/20W MF 201 113 113 93 93 IN IN P4 FB_A0_WCLK_P<1> P5 FB_A0_WCLK_N<1> WCK23 WCK23* DBI0* DBI1* DBI2* DBI3* D2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A4 D13 FB_A0_DBI_L<1> P13 FB_A0_DBI_L<2> P2 FB_A0_DBI_L<3> FB_A0_DQ<0> A2 FB_A0_DQ<1> B4 FB_A0_DQ<2> B2 FB_A0_DQ<3> E4 FB_A0_DQ<4> E2 FB_A0_DQ<5> F4 FB_A0_DQ<6> F2 FB_A0_DQ<7> A11 FB_A0_DQ<8> A13 FB_A0_DQ<9> B11 FB_A0_DQ<10> B13 FB_A0_DQ<11> E11 FB_A0_DQ<12> E13 FB_A0_DQ<13> F11 FB_A0_DQ<14> F13 FB_A0_DQ<15> U11 FB_A0_DQ<16> U13 FB_A0_DQ<17> T11 FB_A0_DQ<18> T13 FB_A0_DQ<19> N11 FB_A0_DQ<20> N13 FB_A0_DQ<21> M11 FB_A0_DQ<22> M13 FB_A0_DQ<23> U4 FB_A0_DQ<24> U2 FB_A0_DQ<25> T4 FB_A0_DQ<26> T2 FB_A0_DQ<27> N4 FB_A0_DQ<28> N2 FB_A0_DQ<29> M4 FB_A0_DQ<30> M2 UA400 FB_A0_DQ<31> NC U5 C5 PP1V5R1V35_S0_GPU_MEM 1 2 1 CA400 4.7UF 20% 6.3V X6S 0402 2 CA401 4.7UF 20% 6.3V X6S 0402 1 2 CA402 4.7UF 20% 6.3V X6S 0402 1 (2 OF 2) D10 CA496 G1 G5 2 CA403 4.7UF 20% 6.3V X6S 0402 2 CA404 4.7UF 20% 6.3V X6S 0402 2 CA405 4.7UF 20% 6.3V X6S 0402 CA497 1 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 G4 G11 H1 G14 H14 VDD VSS MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 2 K1 96 95 RA430 549 B 2 1 2 CA406 1UF 20% 4V CERM-X6S 0201 2 1 CA410 1UF 20% 4V CERM-X6S 0201 2 CA407 1UF 20% 4V CERM-X6S 0201 CA411 1UF 20% 4V CERM-X6S 0201 2 1 2 1 CA408 1UF 20% 4V CERM-X6S 0201 2 1 CA412 1UF 20% 4V CERM-X6S 0201 2 CA409 1UF 20% 4V CERM-X6S 0201 CA413 1UF 20% 4V CERM-X6S 0201 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 93 113 93 IN 113 93 IN 113 113 113 113 113 RA450 120 1% 1/20W MF 201 93 93 RA454 120 1% 1/20W MF 201 2 1 93 RA453 120 1% 1/20W MF 201 2 95 93 1 113 2 93 113 93 113 93 113 113 113 93 113 IN IN IN IN IN IN IN IN IN IN 1 113 BI 93 113 113 93 113 93 113 113 BI 93 95 93 113 93 113 93 95 93 113 BI 93 IN FB_A1_A<5> K10 FB_A1_A<4> K11 FB_A1_A<3> H10 FB_A1_A<7> K4 FB_A1_A<1> H5 FB_A1_A<0> H4 FB_A1_A<6> K5 FB_A1_CKE_L J3 93 93 93 93 93 93 IN IN BI BI BI BI IN IN IN IN FB_A1_CLK_P J12 FB_A1_CLK_N J11 FB_A1_CS_L G12 FB_A1_WE_L L12 FB_A1_CAS_L L3 FB_A1_RAS_L G3 FB_A1_ZQ J13 FB_A1_MF J1 FB_A1_SEN J10 J2 FB_A_RESET_L J4 FB_A1_ABI_L FB_A1_EDC<0> C2 FB_A1_EDC<1> C13 FB_A1_EDC<2> R13 FB_A1_EDC<3> R2 FB_A1_WCLK_P<0> D4 FB_A1_WCLK_N<0> D5 FB_A1_WCLK_P<1> P4 FB_A1_WCLK_N<1> P5 2 1 CA414 1UF 20% 4V CERM-X6S 0201 2 CA415 1UF 20% 4V CERM-X6S 0201 1 2 CA416 0.1UF 10% 6.3V X6S 0201 1 2 CA417 0.1UF 10% 6.3V X6S 0201 L11 93 113 L14 P11 P10 R5 T5 2 A 1 CA418 0.1UF 10% 6.3V X6S 0201 2 CA419 0.1UF 10% 6.3V X6S 0201 1 2 CA420 0.1UF 10% 6.3V X6S 0201 1 2 CA421 0.1UF PLACE_NEAR=UA400.J14:8.4MM PLACE_NEAR=UA400.J14:8.4MM 1 T10 2 OMIT_TABLE CA431 820PF 10% 25V X7R-CERM 0201 2 2 RA431 1.33K 1 1% 1/20W MF 201 PLACE_NEAR=UA400.J14:8.4MM 10% 6.3V X6S 0201 1% 1/20W MF 201 2 1 CA422 0.1UF 10% 6.3V X6S 0201 2 CA423 0.1UF 10% 6.3V X6S 0201 1 2 CA424 0.1UF 10% 6.3V X6S 0201 1 2 CA425 0.1UF 10% 6.3V X6S 0201 A1 D3 A3 D12 A12 D14 A14 E5 C1 E10 C3 F1 C4 F3 C11 F12 C12 F14 C14 G2 E1 G13 E3 VDDQ 1 IN 95 96 1 PLACE CLOSE TO U9000 2 E14 K3 F5 K12 F10 VSSQ H2 H13 110 20% 6.3V X6S 0402 1 2 CA451 4.7UF 20% 6.3V X6S 0402 1 2 CA452 4.7UF 20% 6.3V X6S 0402 K13 M12 M5 M14 M10 N5 N1 N10 N3 1 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 P3 N14 P12 R1 1 RA432 549 FB_A0_VREFD 2 95 CA453 4.7UF 20% 6.3V X6S 0402 1 2 CA454 4.7UF 20% 6.3V X6S 0402 1 2 CA455 4.7UF 20% 6.3V X6S 0402 CA456 1UF 20% 4V CERM-X6S 0201 CA460 1UF 20% 4V CERM-X6S 0201 1 2 1 2 CA457 1UF 20% 4V CERM-X6S 0201 CA461 1UF 20% 4V CERM-X6S 0201 1 2 1 2 1 CA458 1UF 20% 4V CERM-X6S 0201 2 1 CA462 1UF 20% 4V CERM-X6S 0201 2 CA459 1UF 20% 4V CERM-X6S 0201 CA463 1UF 20% 4V CERM-X6S 0201 CA464 1UF 20% 4V CERM-X6S 0201 1 2 CA465 1UF 20% 4V CERM-X6S 0201 1 2 CA466 0.1UF 10% 6.3V X6S 0201 1 2 CA467 0.1UF 10% 6.3V X6S 0201 1% 1/20W MF 201 D10 G1 G5 G4 G10 G11 H1 VDD VSS FB_A1_DQ<3> E4 FB_A1_DQ<4> E2 FB_A1_DQ<5> F4 FB_A1_DQ<6> F2 FB_A1_DQ<7> A11 FB_A1_DQ<8> A13 FB_A1_DQ<9> B11 FB_A1_DQ<10> B13 FB_A1_DQ<11> E11 FB_A1_DQ<12> E13 FB_A1_DQ<13> F11 FB_A1_DQ<14> F13 FB_A1_DQ<15> U11 FB_A1_DQ<16> U13 FB_A1_DQ<17> T11 FB_A1_DQ<18> T13 FB_A1_DQ<19> N11 FB_A1_DQ<20> N13 FB_A1_DQ<21> M11 FB_A1_DQ<22> M13 FB_A1_DQ<23> U4 FB_A1_DQ<24> U2 FB_A1_DQ<25> T4 FB_A1_DQ<26> T2 FB_A1_DQ<27> N4 FB_A1_DQ<28> N2 FB_A1_DQ<29> M4 FB_A1_DQ<30> M2 FB_A1_DQ<31> BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 D C NC J5 FB_A1_A<8> 93 113 IN NC K1 L4 K14 L11 L5 L14 L10 P11 P10 R5 T5 1 PLACE_NEAR=UA400.U10:8.4MM PLACE_NEAR=UA400.A10:13.5MM 2 PLACE_NEAR=UA400.U10:8.4MM CA468 0.1UF 10% 6.3V X6S 0201 1 2 CA469 0.1UF 10% 6.3V X6S 0201 1 2 CA470 0.1UF 10% 6.3V X6S 0201 1 2 CA471 0.1UF 10% 6.3V X6S 0201 PLACE_NEAR=UA400.U10:12.4MM 1 1 2 NOSTUFF CA432 820PF 10% 25V X7R-CERM 0201 1 2 NOSTUFF CA433 820PF 10% 25V X7R-CERM 0201 2 96 95 PP1V5R1V35_S0_GPU_MEM RA480 549 1% 1/20W MF 201 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 PLACE_NEAR=UA450.J14:8.4MM FB_A1_VREFC 95 PLACE_NEAR=UA450.J14:8.4MM PLACE_NEAR=UA450.J14:8.4MM NOSTUFF RA433 1.33K 1 1% 1/20W MF 201 2 1 T10 2 NOSTUFF RA435 931 1% 1/20W MF 201 1 FB_SW_LEG IN 95 96 2 CA472 0.1UF 10% 6.3V X6S 0201 1 2 CA473 0.1UF 10% 6.3V X6S 0201 1 2 CA474 0.1UF 10% 6.3V X6S 0201 1 2 CA475 0.1UF 10% 6.3V X6S 0201 CA481 820PF 10% 25V X7R-CERM 0201 RA481 1.33K 1 1% 1/20W MF 201 2 2 B3 PLACE_NEAR=UA450.J14:8.4MM RA484 931 1% 1/20W MF 201 FB_SW_LEG B12 D1 A1 D3 A3 D12 A12 D14 A14 U12 A10 VREFD 7 E5 C1 E10 C3 F1 C4 F3 C11 F12 C12 F14 C14 1 549 E3 VDDQ FB_A1_VREFD 1% 1/20W MF 201 E14 K3 F5 K12 F10 VSSQ H13 M1 K2 NOSTUFF PLACE_NEAR=UA450.U10:8.4MM PLACE_NEAR=UA450.U10:8.4MM PLACE_NEAR=UA450.U10:8.4MM PLACE_NEAR=UA450.U10:8.4MM H2 L13 2 95 E12 H12 NOSTUFF 1 PLACE_NEAR=UA450.U10:12.4MM 1 10% 25V X7R-CERM 0201 K13 M12 M5 M14 M10 N5 N1 N10 N3 P1 N12 P3 N14 SYNC_MASTER=J80_SEAN P12 R1 PAGE TITLE P14 R3 T1 R4 T3 R11 T12 R12 T14 R14 2 NOSTUFF CA482 820PF M3 95 FB_A1_VREFC J14 95 FB_A1_VREFD A10 U10 2 1 CA483 820PF 10% 25V X7R-CERM 0201 NOSTUFF RA483 1.33K 2 1 1% 1/20W MF 201 2 NOSTUFF RA485 931 1% 1/20W MF 201 FB_SW_LEG SYNC_DATE=04/29/2015 GDDR5 Frame Buffer A DRAWING NUMBER Apple Inc. 051-00647 REVISION R U1 NOTICE OF PROPRIETARY PROPERTY: BRANCH VREFC U3 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE U12 VREFD U14 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 104 OF 145 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 5 95 96 RA482 E1 G13 H3 96 95 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 U14 6 IN B PP1V5R1V35_S0_GPU_MEM 110 R14 U3 95 96 PLACE CLOSE TO U9050 R12 VREFC IN B14 BOM_COST_GROUP=GRAPHICS WWW.AliSaler.Com B2 R11 U10 8 FB_A1_DQ<2> 1 U1 FB_A0_VREFD FB_A1_DQ<1> B4 R4 T14 95 FB_A1_DQ<0> A2 110 H14 L1 L2 R3 T12 J14 A4 1 NOSTUFF PLACE_NEAR=UA400.U10:8.4MM N12 T3 FB_A0_VREFC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 93 113 B10 D11 G14 96 95 K2 T1 95 FB_A1_DBI_L<3> BI B5 (2 OF 2) PP1V5R1V35_S0_GPU_MEM E12 H12 P14 WCK23 WCK23* P2 B1 B14 P1 1 WCK01 WCK01* FB_A1_DBI_L<2> OMIT_TABLE 2 M3 EDC0 EDC1 EDC2 EDC3 FB_A1_DBI_L<1> P13 U5 R10 FB_SW_LEG B12 D1 CA450 4.7UF RA434 931 B3 M1 ABI* FB_A1_DBI_L<0> D13 NC C5 PP1V5R1V35_S0_GPU_MEM 1 1 L13 1 CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET* D2 2 95 L10 L2 A8/A7 A9/A1 A10/A0 A11/A6 CKE* DBI0* DBI1* DBI2* DBI3* BGA PLACE_NEAR=UA400.J14:8.4MM L5 H3 (1 OF 2) A5 G2 1 BA0/A2 BA1/A5 BA2/A4 BA3/A3 OMIT_TABLE 113 2 2 1 BI 1% 1/20W MF 201 K14 B1 1 93 113 96 95 PP1V5R1V35_S0_GPU_MEM 110 G10 R10 1 BI 113 H11 H5GQ1H24AFR-T2C FB_A0_VREFC 1 93 113 1 L4 1 BI IN NC 110 1 L1 1 93 113 93 FB_A1_A<2> B10 D11 5% 2 25V NP0-C0G 0201 BI 113 IN C10 NOSTUFF 12PF 93 113 IN B5 C10 BI 93 32MX32-1.25GHZ-MFL FB_A0_A<8> H5GQ1H24AFR-T2C 96 95 110 93 113 NC J5 BGA BI UA450 A5 32MX32-1.25GHZ-MFL 113 FB_A0_DBI_L<0> 1 95 OF 121 SIZE D A 8 7 6 5 4 3 2 1 UA550 UA500 32MX32-1.25GHZ-MFL 32MX32-1.25GHZ-MFL BGA BGA H5GQ1H24AFR-T2C H5GQ1H24AFR-T2C 113 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 96 113 113 93 IN 93 IN 113 93 IN H11 FB_B0_A<2> K10 FB_B0_A<5> K11 FB_B0_A<4> FB_B0_A<3> H10 FB_B0_A<7> K4 PP1V5R1V35_S0_GPU_MEM CK TERMINATION - B0 D RA501 60.4 FB_B0_CLK_P 1 96 93 113 2 1 1% 1/20W MF 201 PLACE_NEAR=UA500.J12:8.4MM RA502 60.4 FB_B0_CLK_N 2 1% 1/20W MF 201 PLACE_NEAR=UA500.J11:8.4MM 113 96 93 IN 113 96 93 IN 113 93 IN 113 93 IN 113 93 IN 113 93 IN H5 FB_B0_A<1> H4 FB_B0_A<0> K5 FB_B0_A<6> J3 FB_B0_CKE_L J12 FB_B0_CLK_P J11 FB_B0_CLK_N G12 FB_B0_CS_L L12 FB_B0_WE_L L3 FB_B0_CAS_L G3 FB_B0_RAS_L J13 FB_B0_ZQ RA500 120 1% 1/20W MF 201 J1 FB_B0_MF 1 J10 FB_B0_SEN RA504 120 2 1% 1/20W MF 201 1 RA503 120 1% 1/20W MF 201 2 96 93 1 113 2 113 93 93 IN IN BI 113 93 BI 113 93 BI 113 93 BI J2 FB_B_RESET_L J4 FB_B0_ABI_L C2 FB_B0_EDC<0> C13 FB_B0_EDC<1> R13 FB_B0_EDC<2> R2 FB_B0_EDC<3> BA0/A2 BA1/A5 BA2/A4 BA3/A3 (1 OF 2) A8/A7 A9/A1 A10/A0 A11/A6 CKE* OMIT_TABLE CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET* ABI* EDC0 EDC1 EDC2 EDC3 PP1V5R1V35_S0_GPU_MEM CK TERMINATION - B1 FB_B1_CLK_P 1 C PLACE_NEAR=UA550.J12:8.4MM RA551 60.4 2 RA552 60.4 1 1% 1/20W MF 201 1% 1/20W MF 201 FB_B1_CLK_N 2 113 93 IN 113 93 IN D4 FB_B0_WCLK_P<0> D5 FB_B0_WCLK_N<0> WCK01 WCK01* 113 93 96 113 93 IN PLACE_NEAR=UA550.J11:8.4MM 113 93 IN P4 FB_B0_WCLK_P<1> P5 FB_B0_WCLK_N<1> WCK23 WCK23* DBI0* DBI1* DBI2* DBI3* D2 P2 FB_B0_DBI_L<3> DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A4 FB_B0_DQ<0> UA500 D13 NC FB_B0_DQ<1> B4 FB_B0_DQ<2> B2 FB_B0_DQ<3> E4 FB_B0_DQ<4> E2 FB_B0_DQ<5> F4 FB_B0_DQ<6> F2 FB_B0_DQ<7> A11 A13 1 2 1 CA500 4.7UF 20% 6.3V X6S 0402 2 CA501 4.7UF 20% 6.3V X6S 0402 1 2 CA502 4.7UF 20% 6.3V X6S 0402 1 CA498 12PF 5% 2 25V NP0-C0G 0201 B13 2 1 CA503 4.7UF 20% 6.3V X6S 0402 2 CA504 4.7UF 20% 6.3V X6S 0402 1 2 CA505 4.7UF 20% 6.3V X6S 0402 1 CA499 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 E11 (2 OF 2) E13 D11 D10 F11 B 2 1 2 CA506 1UF 20% 4V CERM-X6S 0201 2 1 CA510 1UF 20% 4V CERM-X6S 0201 2 CA507 1UF 20% 4V CERM-X6S 0201 CA511 1UF 20% 4V CERM-X6S 0201 2 1 2 1 CA508 1UF 20% 4V CERM-X6S 0201 2 1 CA512 1UF 20% 4V CERM-X6S 0201 2 CA509 1UF 20% 4V CERM-X6S 0201 CA513 1UF 20% 4V CERM-X6S 0201 G1 G5 G4 G10 G11 H1 G14 VDD VSS 110 K1 L4 K14 L11 L5 96 F13 L14 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 U11 CA514 1UF 2 20% 4V CERM-X6S 0201 2 CA515 1UF 20% 4V CERM-X6S 0201 1 2 CA516 0.1UF 10% 6.3V X6S 0201 1 2 CA517 0.1UF 10% 6.3V X6S 0201 FB_B0_DQ<16> U13 FB_B0_DQ<17> T11 FB_B0_DQ<18> T13 FB_B0_DQ<19> N11 FB_B0_DQ<20> N13 FB_B0_DQ<21> M11 FB_B0_DQ<22> M13 FB_B0_DQ<23> U4 FB_B0_DQ<24> U2 FB_B0_DQ<25> T4 FB_B0_DQ<26> T2 FB_B0_DQ<27> N4 FB_B0_DQ<28> N2 FB_B0_DQ<29> M4 FB_B0_DQ<30> M2 FB_B0_DQ<31> 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 113 93 93 93 113 93 IN 113 93 IN 113 113 113 93 93 93 93 113 96 93 96 93 113 93 93 113 113 RA550 120 1% 1/20W MF 201 RA554 120 2 1% 1/20W MF 201 1 RA553 120 1% 1/20W MF 201 2 1 113 2 93 93 113 93 113 113 113 93 113 93 113 113 BI 93 96 93 113 93 113 IN IN IN IN IN IN IN IN IN IN 1 113 BI IN FB_B1_A<2> H11 FB_B1_A<5> K10 FB_B1_A<4> K11 FB_B1_A<3> H10 FB_B1_A<7> K4 FB_B1_A<1> H5 FB_B1_A<0> H4 FB_B1_A<6> K5 FB_B1_CKE_L J3 P11 P10 R5 T5 93 93 93 93 93 93 IN IN BI BI BI BI IN IN IN IN NC FB_B1_CLK_P J12 FB_B1_CLK_N J11 FB_B1_CS_L G12 FB_B1_WE_L L12 FB_B1_CAS_L L3 FB_B1_RAS_L G3 FB_B1_ZQ J13 FB_B1_MF J1 FB_B1_SEN J10 J2 FB_B_RESET_L J4 FB_B1_ABI_L FB_B1_EDC<0> C2 FB_B1_EDC<1> C13 FB_B1_EDC<2> R13 FB_B1_EDC<3> R2 FB_B1_WCLK_P<0> D4 FB_B1_WCLK_N<0> D5 FB_B1_WCLK_P<1> P4 FB_B1_WCLK_N<1> P5 FB_B0_A<8> IN 93 113 2 10% 6.3V X6S 0201 2 10% 6.3V X6S 0201 1 2 CA520 0.1UF 10% 6.3V X6S 0201 1 2 CA521 0.1UF 10% 6.3V X6S 0201 1 2 1 CA522 0.1UF 10% 6.3V X6S 0201 2 CA523 0.1UF 10% 6.3V X6S 0201 1 2 CA524 0.1UF 10% 6.3V X6S 0201 1 2 CA525 0.1UF 10% 6.3V X6S 0201 EDC0 EDC1 EDC2 EDC3 WCK01 WCK01* WCK23 WCK23* 96 95 RA530 549 2 1 PLACE_NEAR=UA500.J14:8.4MM 2 PLACE_NEAR=UA500.J14:8.4MM 1 CA531 820PF 10% 25V X7R-CERM 0201 2 RA531 1.33K 1 1% 1/20W MF 201 2 B12 A1 D3 A3 D12 A12 D14 A14 E5 C1 E10 C3 1% 1/20W MF 201 F1 C4 C14 G2 E1 G13 20% 6.3V X6S 0402 1 2 CA551 4.7UF 20% 6.3V X6S 0402 1 2 CA552 4.7UF FB_B1_DQ<1> B4 FB_B1_DQ<2> B2 FB_B1_DQ<3> E4 FB_B1_DQ<4> E2 FB_B1_DQ<5> F4 FB_B1_DQ<6> F2 FB_B1_DQ<7> A11 FB_B1_DQ<8> A13 FB_B1_DQ<9> B11 FB_B1_DQ<10> B13 FB_B1_DQ<11> E11 FB_B1_DQ<12> E13 FB_B1_DQ<13> F11 FB_B1_DQ<14> F13 FB_B1_DQ<15> U11 FB_B1_DQ<16> U13 FB_B1_DQ<17> T11 FB_B1_DQ<18> T13 FB_B1_DQ<19> N11 FB_B1_DQ<20> N13 FB_B1_DQ<21> M11 FB_B1_DQ<22> M13 FB_B1_DQ<23> U4 FB_B1_DQ<24> U2 FB_B1_DQ<25> T4 FB_B1_DQ<26> T2 FB_B1_DQ<27> N4 FB_B1_DQ<28> N2 FB_B1_DQ<29> M4 FB_B1_DQ<30> M2 FB_B1_DQ<31> 20% 6.3V X6S 0402 110 IN 95 96 2 96 95 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 1 E12 H12 E14 K3 F5 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 BI 93 113 FB_B1_A<8> 2 96 CA553 4.7UF 20% 6.3V X6S 0402 1 2 CA554 4.7UF 20% 6.3V X6S 0402 1 2 CA555 4.7UF 20% 6.3V X6S 0402 CA556 1UF 20% 4V CERM-X6S 0201 1 2 CA557 1UF 20% 4V CERM-X6S 0201 1 2 1 CA558 1UF 20% 4V CERM-X6S 0201 2 CA559 1UF 20% 4V CERM-X6S 0201 CA560 1UF 20% 4V CERM-X6S 0201 1 2 CA561 1UF 20% 4V CERM-X6S 0201 1 2 1 CA562 1UF 20% 4V CERM-X6S 0201 2 CA563 1UF 20% 4V CERM-X6S 0201 NOSTUFF RA532 549 1 1% 1/20W MF 201 2 CA564 1UF 20% 4V CERM-X6S 0201 1 2 CA565 1UF 20% 4V CERM-X6S 0201 1 2 CA566 0.1UF 10% 6.3V X6S 0201 1 2 CA567 0.1UF 10% 6.3V X6S 0201 PLACE_NEAR=UA500.U10:8.4MM H2 H13 M1 PLACE_NEAR=UA500.U10:8.4MM PLACE_NEAR=UA500.U10:8.4MM D11 D10 G1 G5 G4 G10 G11 H1 G14 H14 VDD VSS L1 K1 L4 K14 L11 L5 L14 L10 P11 P10 R5 T5 R10 T10 NC 96 95 PP1V5R1V35_S0_GPU_MEM 110 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 RA580 549 1% 1/20W MF 201 2 PLACE_NEAR=UA550.J14:8.4MM 96 PLACE_NEAR=UA550.J14:8.4MM PLACE_NEAR=UA550.J14:8.4MM PLACE_NEAR=UA550.J14:8.4MM 1 1 2 CA581 820PF 10% 25V X7R-CERM 0201 RA581 1.33K 2 1 1% 1/20W MF 201 RA584 931 1% 1/20W MF 201 B3 FB_SW_LEG NOSTUFF 1 K13 M12 M5 M14 M10 N5 N1 N10 N3 P1 N12 2 CA532 820PF 10% 25V X7R-CERM 0201 NOSTUFF 1 2 1 CA533 820PF 10% 25V X7R-CERM 0201 2 NOSTUFF RA533 1.33K 1 1% 1/20W MF 201 2 1 NOSTUFF RA535 931 2 1% 1/20W MF 201 P3 N14 P12 R1 P14 CA568 0.1UF 10% 6.3V X6S 0201 1 2 CA569 0.1UF 10% 6.3V X6S 0201 1 2 CA570 0.1UF 10% 6.3V X6S 0201 1 2 CA571 0.1UF 10% 6.3V X6S 0201 IN B12 B D1 A1 D3 A3 D12 A12 D14 A14 E5 C1 E10 C3 F1 C4 F3 C11 F12 C12 F14 C14 G2 E1 G13 E3 PLACE CLOSE TO U9050 PP1V5R1V35_S0_GPU_MEM H3 VDDQ 110 96 95 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 1 FB_B1_VREFD E12 H12 E14 K3 F5 K12 F10 2 96 NOSTUFF RA582 549 1% 1/20W MF 201 PLACE_NEAR=UA550.U10:8.4MM PLACE_NEAR=UA550.U10:8.4MM VSSQ H2 H13 NOSTUFF PLACE_NEAR=UA550.A10:8.4MM 1 M1 K2 M3 K13 2 NOSTUFF 1 CA582 820PF 10% 25V X7R-CERM 0201 M12 M5 M14 M10 N5 N1 N10 N3 P1 N12 P3 N14 SYNC_MASTER=J80_SEAN P12 R1 PAGE TITLE P14 R3 T1 R4 T3 R11 T12 R12 T14 R14 2 1 CA583 820PF 10% 25V X7R-CERM 0201 2 NOSTUFF RA583 1.33K NOSTUFF PLACE_NEAR=UA550.U10:8.4MM 1 1% 1/20W MF 201 2 RA585 931 1% 1/20W MF 201 FB_SW_LEG IN 95 96 1 2 R3 CA572 0.1UF 10% 6.3V X6S 0201 1 2 CA573 0.1UF 10% 6.3V X6S 0201 1 2 CA574 0.1UF 10% 6.3V X6S 0201 1 2 CA575 0.1UF 10% 6.3V X6S 0201 IN SYNC_DATE=04/29/2015 GDDR5 Frame Buffer B DRAWING NUMBER Apple Inc. R11 R12 051-00647 REVISION R R14 A10 U3 U12 VREFD 96 FB_B1_VREFC J14 96 FB_B1_VREFD A10 U10 VREFC U1 NOTICE OF PROPRIETARY PROPERTY: BRANCH U3 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE U12 VREFD U14 U14 7 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 105 OF 145 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=GRAPHICS 95 96 PLACE_NEAR=UA550.U10:8.4MM R4 VREFC 95 96 B14 L13 PLACE_NEAR=UA500.U10:8.4MM PLACE_NEAR=UA500.A10:8.4MM K2 M3 C 93 113 IN F10 VSSQ D NC J5 2 1 FB_B0_VREFD U10 WWW.AliSaler.Com FB_B1_DQ<0> A2 93 113 B10 U1 8 A4 1 PLACE CLOSE TO U9000 E3 VDDQ T14 FB_B0_VREFD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BI B5 (2 OF 2) C12 T12 96 FB_B1_DBI_L<3> U5 C11 F14 J14 P2 B1 1 PP1V5R1V35_S0_GPU_MEM T3 FB_B0_VREFC FB_B1_DBI_L<2> OMIT_TABLE B14 D1 CA550 4.7UF RA534 931 FB_SW_LEG T1 96 FB_B1_DBI_L<1> P13 NC C5 PP1V5R1V35_S0_GPU_MEM 1% 1/20W MF 201 B3 H3 FB_B1_DBI_L<0> D13 H5GQ1H24AFR-T2C FB_SW_LEG A ABI* D2 BGA NC PLACE_NEAR=UA500.J14:8.4MM 2 L13 CA519 0.1UF CK CK* CS* WE* CAS* RAS* ZQ MF (MF=0) SEN RESET* DBI0* DBI1* DBI2* DBI3* A5 L2 1 A8/A7 A9/A1 A10/A0 A11/A6 CKE* 32MX32-1.25GHZ-MFL 96 T10 L2 CA518 0.1UF (1 OF 2) UA550 PLACE_NEAR=UA500.J14:8.4MM FB_B0_VREFC 1 K12 1 BA0/A2 BA1/A5 BA2/A4 BA3/A3 OMIT_TABLE 113 93 113 IN 113 113 BI IN FB_B1_VREFC L10 F12 1 FB_B0_DQ<15> BI 1 1 H14 L1 F3 1 FB_B0_DQ<14> 95 PP1V5R1V35_S0_GPU_MEM B1 1 FB_B0_DQ<13> 93 113 B10 OMIT_TABLE 1 FB_B0_DQ<12> BI C10 R10 1 FB_B0_DQ<11> 110 2 1 FB_B0_DQ<10> B5 C10 NOSTUFF FB_B0_DQ<9> B11 U5 C5 FB_B0_DQ<8> J5 BGA PP1V5R1V35_S0_GPU_MEM FB_B0_DBI_L<2> A2 H5GQ1H24AFR-T2C 96 95 110 FB_B0_DBI_L<1> P13 A5 32MX32-1.25GHZ-MFL 113 FB_B0_DBI_L<0> 1 96 OF 121 SIZE D A 8 7 PART NUMBER QTY 376S00174 6 DESCRIPTION 2 REFERENCE DES CRITICAL 4 3 CA600 1 33UF RA601 110 PP5V_S0 97 0 1 RA602 2 1 1 5% 1/20W MF 0201 D PP1V8_S0_GPU 97 109 97 CA609 33UF CA610 1 5% 1/20W MF 201 CA637 1 1.0UF CA690 12PF 10% 5% 25V 2 NP0-C0G 0201 25V X6S 2 0402 1 CA691 1 3.0PF CA692 12PF 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 CA604 CA605 1 33UF 20% 2 16V TANT-POLY CASE-B3 1 1 33UF CA606 1 CA607 12PF 33UF 20% 2 16V TANT-POLY CASE-B3 20% 2 16V TANT-POLY CASE-B3 CA612 1 2.2UF 5% 2 NP0-C0G 0201 20% 2 16V TANT-POLY CASE-B3 CA694 12PF PP5V_S0_GFXIMVP_VDDP CA638 5% 2 25V NP0-C0G 0201 1 1.0UF 1 CA695 1 3.0PF CA696 12PF +/-0.1PF 2 25V NP0-C0G 0201 5% 25V 2 NP0-C0G 0201 20% 25V X6S-CERM 2 0402 25V X6S-CERM 2 0402 X6S-CERM 2 0402 GPU CORE SUPPLY 1 64.2A MAX OUTPUT LA640 CA697 3.0PF 1 OMIT_TABLE PPVIN_S0_GFXIMVP_VIN 2 5% 1/20W MF 0201 1 CA639 0.22UF 10% 25V 2 X7R 0402 RA660 VDD 29 1 IRF3575 PQFN VDDIO 7 PPBUS_HS_GPU VOLTAGE=12.6V 1 1 127K 25 1000PF 1% 1/20W MF 201 2 VDDIO = 1.14V - 1.95V CA660 Line Width & DIDT on all DIDT nets 5% 2 25V C0G 0201 REG_GPU_VDDCI_COMP 43 IN 94 IN 94 IN 94 IN 110 CA661 10% 2 16V CER-X7R 0201 1 CA663 5% 2 25V C0G 0201 1 CA664 2.0PF 1 100 97 91 IN PM_ALL_GPU_PGOOD ENABLE Vil<1V,Vih>1.6V Ileak<35uA PWROKVthres=750mV, 1uA-leak 97 97 GPUVCORE_SVC GPUVCORE_SVD GPUVCORE_SVT_R GPUVCORE_COMP GPUVCORE_SENSE_P 4 6 8 22 CKPLUS_WAIVE=PDIFPR_BADTERM 19 21 20 16 17 GFXIMVP_ISUMP NOSTUFF 806 SVC {Vih>0.7*VDDIO SVD{Vil<0.3*VDDIO SVT50R Vol<0.4V@4mA |Ioh|<1uA COMP VSEN RTN CA666 1 BOOT1 UGATE1 PHASE1 LGATE1 24 25 26 27 DIDT=TRUE GATE_NODE=TRUE SWITCH_NODE=TRUE GATE_NODE=TRUE FB FB2 ISUMP ISUMN 5% 2 25V C0G 0201 10% 10V CERM 2 201 91 OUT 94 OUT 94 OUT 94 OUT 94 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE NO_XNET_CONNECTION=1 RA640 GFXIMVP_BOOT1 GFXIMVP_UGATE1 GFXIMVP_Q1S1 GFXIMVP_LGATE1 OUT PP5V_S0 GFXIMVP_ISEN2 GFXIMVP_ISEN1 0 5% 1/16W MF-LF 2 402 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 94 IN RA650 97 110 97 97 VIN CA667 0.1UF 2 X6S 0201 1 CRITICAL CA650 25 10% 2 16V CERM 402 GATEH 6 7 26 SW 5 32 GATEL NC NC NC NC NC NC NC Q1S 4 16 28 31 IN 1 IN GPUVCORE_SVD_R 5% 1/20W MF 201 A GPUVCORE_PGOOD 47K OUT GPUVCORE_SVT 1 10K 2 1 RA688 1 2 47K 10K 1 1 2 22 GPUVCORE_SVD 2 1 97 5% 1/20W MF 201 5% 1/20W MF 201 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 PILA63T-SM 97 GPUVCORE_SVT_R 100K VOLTAGE=1.1V MF 1% 201 RA653 1 1% 1/20W MF 201 2 1% 1/20W MF 201 2 GFXIMVP_ISEN1 IN 1 PVCORE_GPU_FB_SNS_P GPUVCORE_VR_HOT_L IN PVCORE_GPU_FB_SNS_N 1 0 5% 1/20W MF 0201 97 99 2 0 WWW.AliSaler.Com RA654 1K 1.00 1% 1/20W MF-LF 2 0201 GFXIMVP_ISUMN GFXIMVP_ISUMP GPUVCORE_SENSE_P 2 5% 1/20W MF 0201 97 97 X6S-CERM 0201 1 1/20W MF 201 1 GFXIMVP_ISNS2_N 2 55 97 1% GPUVCORE_SENSE_N CA668 1 2.0PF 25V NP0-C0G-CERM 2 0201 NOSTUFF NO_XNET_CONNECTION=1 97 10K 20% +/-0.1PF GPUVCORE_NTC 97 RA655 2 6.3V 1 SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN 97 SYNC_DATE=12/08/2015 PAGE TITLE GFX IMVP VCore Regulator [106] CA669 0.01UF DRAWING NUMBER 10% Apple Inc. 2 25V X5R-CERM 0201 1/20W 051-00647 REVISION R NO_XNET_CONNECTION=1 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE II NOT TO REPRODUCE OR COPY IT 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 106 OF 145 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE ISL6277A datasheet (December 19,2012) 7 1 1 1 RA667 92 55 97 CA651 97 BOM_COST_GROUP=GRAPHICS 8 1 RA652 1 10K 2 4 GFXIMVP_ISNS1_N GFXIMVP_ISNS1_P 1 94 92 2 1 3 1% 1W MF 0612-1 0.22UF 90 94 99 110 2 MF 0.00075 PPVCORE_S0_GFX_PH1 2 97 5% 1/20W MF 201 RA690 GPUVCORE_SVD LA650 1 1% 1/20W 201 2 NOSTUFF RA651 CRITICAL RA681 RA683 97 RA687 5% 1/20W MF 201 10K 22 PP3V3_S0_GPU 91 97 5% 1/20W MF 201 RA686 1 GPUVCORE_SVC 376S1136 97 RA668 2 CRITICAL NO_XNET_CONNECTION RA685 1 NOSTUFF GPUVCORE_SVC 5% 1/20W MF 201 2 B 55 2 RA682 RA684 1 22 5% 1/20W MF 201 97 110 98 NOSTUFF NC RA680 98 47K 1 2 3 24 27 29 30 SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE NO_XNET_CONNECTION=1 PP1V8_S0_GPU OMIT_TABLE PQFN 0.22UF GPUVCORE_SVC_R C 55 97 97 109 GFXIMVP_PHASE1 98 GFXIMVP_ISNS1_N 2 IRF3575 GFXIMVP_BOOT1_R GFXIMVP_ISUMN_R 6.3V 10K 1% 1/20W MF 201 0.2UH-20%-28A-0.0011OHM 10% RA645 QA650 RA666 1 1 PPBUS_HS_GPU 1 91 97 REG_GPU_VDDCI_FCCM 1% 1/20W MF 201 2 X6S-CERM 0201 SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 5% 1/16W MF-LF 2 402 5% 1/20W MF 2 201 NO_XNET_CONNECTION=1 97 1 20% PGND 1 97 0.22UF 1 GFXIMVP_PHASE2 0 10 2 97 CA641 NC 1 RA665 GFXIMVP_ISUMN 1% 1/20W MF-LF 2 0201 GFXIMVP_ISUMN GFXIMVP_ISUMP 376S1136 NOSTUFF 634 1.00 GFXIMVP_ISEN2 97 GFXIMVP_BOOT2_R 1 RA644 1K PGND GFXIMVP_ISUMP_C 1 1 2 3 24 27 29 30 11 GFXIMVP_BOOT2 GFXIMVP_UGATE2 GFXIMVP_Q1S2 GFXIMVP_LGATE2 GPUVCORE_PGOOD PGOOD 23 1% 1/20W MF 201 2 55 97 6.3V NO_XNET_CONNECTION=1 5600PF NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 DIDT=TRUE GATE_NODE=TRUE SWITCH_NODE=TRUE GATE_NODE=TRUE 13 ISEN3 14 ISEN2 15 ISEN1 1000PF NOSTUFF 34 33 32 31 FCCM_NB 41 CA665 1 1% 1/20W MF 201 2 10% 2 16V CER-X7R 0201 10 18 GPUVCORE_SENSE_N RA664 1 CA662 220PF B 9 GPUVCORE_FB GPUVCORE_FB2 GPUVCORE_FB_R 1 GPUVCORE_EN OUT NCMIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 BOOT2 UGATE2 PHASE2 LGATE2 1% 1/20W MF 201 2 10K 10% 2 CERM 402 REG_BOOT_GPU_VDDCI REG_UGATE_GPU_VDDCI_R REG_PHASE_GPU_VDDCI REG_LGATE_GPU_VDDCI PWM_Y 28 IN NOSTUFF 1% 1/20W MF 2 201 NTC_NB NTC 27-33uA 91 NOSTUFF NO_XNET_CONNECTION=1 RA663 ISEN1_NB ISEN2_NB VR_HOT* 11Rdwn,1uA-leak 2 NP0-C0G-CERM 0201 97 2 12 BOOTX UGATEX PHASEX LGATEX GATEL 16V PVDDCI_PGOOD 36 37 38 39 CA640 5 32 Q1S 0.22UF 94 IN NC PGOOD_NB 42 ISUMP_NB ISUMN_NB 5 97 97 NC FB_NB GPUVCORE_VR_HOT_L 25V NO_XNET_CONNECTION=1 GPUVCORE_NTC 48 1 REG_GPU_VDDCI_IMON PWM2_NB 40 OUT +/-0.1PF NO_XNET_CONNECTION=1 46 REG_GPU_VDDCI_ISEN1 PP5V_S0 99 97 RA662 1% 1/20W MF 2 201 47 97 10PF GPUVCORE_COMP_C 10K REG_GPU_VDDCI_ISUMP REG_GPU_VDDCI_ISUMN NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 220PF 1 44 1 49 1 97 REG_GPU_VDDCI_FB QFN CRITICAL PAD 94 COMP_NB IMON 11 IMON_NB 3 SW 4 16 28 31 IN ISL6277AHRZ VSEN_NB 6 7 26 NC NC NC NC NC NC NC RA643 1 110 18 20 21 22 23 45 THRM C 94 IN REG_GPU_VDDCI_VSEN GATEH 1 RA642 1 NO_XNET_CONNECTION CRITICAL UA600 94 1 PPVCORE_S0_GPU 2 4 GFXIMVP_ISNS2_N GFXIMVP_ISNS2_P QA640 TP_GPUVCORE_IMON 1% 1W MF 0612-1 1 3 VOLTAGE=1.1V 55 VDDP 30 97 PPVCORE_S0_GFX_PH2 PILA63T-SM VIN VIN 35 109 2 0.00075 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 0.2UH-20%-28A-0.0011OHM +/-0.1PF 2 25V NP0-C0G 0201 F = 450 KHZ RA641 CRITICAL 25V X6S 2 0402 0 D VOUT = 0.75-1.00V +/-0.1PF 2 25V NP0-C0G 0201 10% RA603 3.0PF 1 3.0PF 18 20 21 22 23 1 CA608 +/-0.1PF 2 25V NP0-C0G 0201 25V CRITICAL VOLTAGE=5V CRITICAL 1 2.2UF 20% 25V X6S-CERM 2 0402 CA693 CA611 1 20% 25V 1 CA603 1 33UF 20% 2 16V TANT-POLY CASE-B3 2.2UF 20% PPBUS_HS_GPU 109 CA602 1 33UF 20% 2 16V TANT-POLY CASE-B3 2.2UF PP5V_S0_GFXIMVP_VDD CA601 1 PPBUS_HS_GPU VOLTAGE=5V 2 1 CRITICAL 1 20% 2 16V TANT-POLY CASE-B3 110 2 BOM OPTION CRITICAL QA640,QA650 MOSFET,CTRL+SYNC,25V,4.1/1.4MO,QFN32,6x6 5 1 97 OF 121 SIZE D A 7 6 5 former site of the SPEED MLPS STRAPS 110 PCIe Gen3 enabled, Half-Swing, TX De-emp enabled VBIOS disabled, Boot from EFI VGA enabled All power audio-capable display output 256MB FB Aperture Size PS_0: 01001 82nF 8.45k 2k PS_1: 10001 10nF 8.45k 2k PS_2: 10000 10nF NC 4.75k PS_3: 00000 680nF NC 4.75k 110 4 RA770 NOSTUFF 1 RA771 5.1K NOSTUFF D RA77A 1 RA77B GPU_ROM_CONFIG<0> 99 GPU_AUD_PORT_CONN<2> GPU_AUD_PORT_CONN<1> GPU_AUD_PORT_CONN<0> 99 GPU_BIF_GEN3_EN_A 99 GPU_TX_HALF_SWING 99 GPU_TX_DEEMPH_EN 99 99 99 98 GPU_ROM_SO (strap BIF_CLK_PM_EN) 99 98 GPU_ROM_CS_L_R (strap BIOS_ROM_EN) 99 GPU_VGA_DIS 99 GPU_AUD<1> 99 GPU_AUD<0> 99 99 99 99 99 RA772 1 RA773 RA77C RA774 1 RA77D 1 1 5.1K GPU_BRD_CFG<2> GPU_BRD_CFG<1> GPU_BRD_CFG<0> GPU_SMBUS_ADDR<1> GPU_SMBUS_ADDR<0> NOSTUFF 1 RA786 5.1K C 1 RA787 5.1K 1% 1/20W MF 201 2 RA780 NOSTUFF RA788 RA789 5.1K 1% 1/20W MF 201 2 1 RA78A 5.1K 110 99 1/20W 99 RA7511 GPU_GPIO_SVD_R 1/20W MF 5% 22 201 RA757 GPU_GPIO_SVD 2 5% MF 1 201 2 1% 1/20W MF 201 2 1 RA791 5.1K 1 RA792 5.1K 1% 1/20W MF 201 2 1% 1/20W MF 201 2 1 5.1K 1% 1/20W MF 201 2 1% 1/20W MF 201 2 GPUVCORE_SVC_R OUT 89 49 PP3V3_S0 0 RA758 2 NOSTUFF 1 RA78B GPUVCORE_SVD_R OUT 1 1 0.1UF 97 RA700 47K 10% 6.3V 2 CERM-X5R 0201 1 5% 1/20W MF 2 201 RA793 1 1 RA78C UA702 EG_CLKREQ_SEL_L 89 111 5.1K 1 5.1K 1% 1/20W MF 201 2 1% 1/20W MF 201 2 110 RA795 1 5.1K RA703 6 1 SC70 SEL 0 GPUVCORE_SVT MAKE_BASE=TRUE B1 VCC GND 4 GPUVCORE_SVT IN 97 1 98 99 GPU_ROM_SI_R 1 GPU_ROM_SI 2 5% 1% 1/20W 1/20W MF MF 0201 201 2 1/20W GPU_ROM:YES CA721 0201 GPU_ROM:YES RA726 VCC 201 GPU_ROM:YES A 99 GPU_ROM_SCLK_R 1 5% 1/20W MF 1 S* RA725 GPU_ROM:YES 1 2 GPU_ROM_CS_L 1/20W MF GPU_ROM_SO_R 1 M25P10A 2 GPU_ROM_SO 1 RA78E 1 GPU_ROM_SI_R 5.1K (strap reserved) 98 99 GPU_RESERVED 1% 1/20W MF 201 2 1 RA797 1 RA798 5.1K 1 RA799 5.1K 1% 1/20W MF 201 2 1/20W MF OMIT_TABLE 1 1% 1/20W MF 201 2 GPUCLK:OSC OMIT_TABLE RA741 1 5% 1/20W MF 0201 2 5% 1/20W MF 201 2 10K 1 0 2 GPU_XTAL_OR_CLK_IN 1 CA740 18PF GPUCLK:XTAL 5% 2 25V C0G 0201 1 5% 1/20W MF 2 201 YA740 27MHZ-30PPM-18PF-60OHM RA742 GPUCLK:XTAL 1 RA744 0 B0 RA730 THRM VSS 4 5% 1/20W MF 0201 2 113 GPU_XTAL_PU_OR_CAP 1 5% 2 25V C0G 0201 DESCRIPTION GPU XTAL 27 MHZ OR GPU OSC 100 MHZ REFERENCE DES CRITICAL 1/20W MF 0201 BOM OPTION 197S0499 1 XTAL,27.000MHZ,30PPM,12PF,2.5x2.0MM YA740 CRITICAL GPUCLK:XTAL RA732 10K NOSTUFF 1 5% 1/16W MF-LF 402 2 RA733 10K NOSTUFF 197S00056 1 OSC,MEMS,100MHZ,+/-20PPM,1.8V,2520 YA740 CRITICAL GPUCLK:OSC 1 5% 1/16W MF-LF 402 2 RA734 1 117S0201 1 RES,0 OHM,5%,0201 RA743 CRITICAL GPUCLK:XTAL 10K 5% 1/16W MF-LF 402 2 117S0080 1 RES,33 OHM,5%,0201 RA743 CRITICAL GPUCLK:OSC 155S0387 1 FERRITE BEAD, 470OHM,0.1A,1.5MOHM DCR,060 RA740 CRITICAL GPUCLK:OSC 117S0201 1 RES,0 OHM,5%,0201 RA742 CRITICAL GPUCLK:XTAL 99 132S0444 1 CAP,CER,X5R,0.1UF,10%,6.3V,0201 RA742 CRITICAL GPUCLK:OSC 99 GPU_JTAG_TMS 99 GPU_JTAG_TDO 99 GPU_JTAG_TCK 99 SYNC_MASTER=X363_SEAN PAGE TITLE SYNC_DATE=01/28/2016 Baffin GPIOs,CLK & Straps DRAWING NUMBER 1 Apple Inc. 5% 1/16W MF-LF 402 2 9 051-00647 REVISION R 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=GRAPHICS WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 107 OF 145 SHEET IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 99 113 CA741 18PF 5% 1/20W 0201 GPU_XTAL_OUT 1 5% 1/20W MF 0201 GPUCLK:XTAL 1 NOSTUFF QTY 0 2 10K PAD B 2.50X2.00MM-SM OMIT_TABLE 99 RA745 1M OMIT_TABLE GPU_CLKREQ_L 99 113 5% 1/20W MF 0201 GPUCLK:XTAL RA740 1 0 2 3 0 RA743 GPU_XTAL_XTAL_OR_CLK NOSTUFF 0 C 99 5.1K 1% 1/20W MF 201 2 GPU_XTAL_PWR_OR_GND GPU_JTAG_TRST_L 201 RA722 5% NOSTUFF 1 1% 1/20W MF 201 2 EG_CLKREQ_PU GPU_JTAG_TDI 98 99 5% UFDFPN8 1 201 Q2 7 HOLD* NO STUFF 5% UA701 33 3 W* GPU_ROM_WP_L 33 GPU_ROM_CS_L_R 6C GPU_ROM_SCLK 2 201 98 99 5D RA724 33 5% 1/16W MF-LF 402 2 X6S MF 1 10K 10% 8 NOSTUFF RA731 6.3V 2 2 1% 1/20W MF 201 2 PP3V3_S0_GPU NOSTUFF 0.1UF 1 5% 5.1K 1% 1/20W MF 201 2 OMIT_TABLE 5% 1/20W MF 2 201 GPU JTAG 110 33 D 1 SEL = 0 : PCH CLKREQ CONNECTED TO GPU SEL = 1 : PCH CLKREQ TIED TO PULLUP GPU ROM 5.1K RA79B PP1V8_S0_GPU 0 EG_CLKREQ_OUT_L BOMOPTION=NOSTUFF RA720 NOSTUFF 1 5.1K 5.1K 1% 1/20W MF 201 2 PART NUMBER 0 RA784 2 5 MF RA721 1 110 1 2 RA723 RA78D 5.1K 1% 1/20W MF 201 2 RA704 GPU_ROM:YES 1 RA796 VER 1 1 1% 1/20W MF 201 2 1% 1/20W MF 201 2 PI5A3157BC6E A GPU_ROM:YES 1 5.1K 5.1K 1% 1/20W MF 201 2 47K 5% 1/20W MF 2 201 CRITICAL 5% 1/20W MF 0201 2 PP3V3_S0_GPU RA783 5.1K 1% 1/20W MF 201 2 RA794 RA701 1 RA702 47K BOMOPTION=BAFFIN 97 5% 1/20W MF 0201 B 110 NOSTUFF 1 PCIe Gen3 enabled, FULL-Swing, TX De-emp enabled VBIOS disabled, Boot from EFI VGA enabled, CLKREQ_L enabled All power audio-capable display output Audio for DP or HDMI dongle 256MB FB Aperture Size SMBUS address 41 113 BOMOPTION=SPEED 99 RA79A 1% 1/20W MF 201 2 1% 1/20W MF 201 2 5.1K 1% 1/20W MF 201 2 PP3V3_S0_GPU CA700 5% 1/20W MF 0201 1 1 5.1K 5.1K 1% 1/20W MF 201 2 5.1K GPU CLKREQ GATING GPU_GPIO_SVC RA782 NOSTUFF 3 RA790 1% 1/20W MF 201 2 2 RA778 1% 1/20W MF 201 2 NOSTUFF 1 1 5.1K 1% 1/20W MF 201 2 5.1K 1% 1/20W MF 201 2 RA777 NOSTUFF 1 1 5.1K GPU_GPIO_SVC_R 1 5.1K RA781 5.1K NOSTUFF NOSTUFF RA78F 0 RA776 1% 1/20W MF 201 2 1% 1/20W MF 201 2 NOSTUFF 1 1 5.1K 1% 1/20W MF 201 2 Former site of the GPU SVI2 VOLTAGE TRANSLATION SPEED ONLY 22 NOSTUFF 0 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 RA785 RA7501 1 NOSTUFF 1 1 5.1K 1% 1/20W MF 201 2 RA775 1% 1/20W MF 201 2 RA77F 5.1K 1% 1/20W MF 201 2 NOSTUFF 5.1K 1% 1/20W MF 201 2 5.1K 1% 1/20W MF 201 2 1 5.1K 1% 1/20W MF 201 2 NOSTUFF 1 NOSTUFF 5.1K 5.1K 1% 1/20W MF 201 2 99 1 1% 1/20W MF 201 2 5.1K GPU_ROM_CONFIG<1> NOSTUFF 5.1K 1% 1/20W MF 201 2 99 1 BAFFIN STRAPS NOSTUFF GPU_ROM_CONFIG<2> 2 NOTICE THE ANNOYING MIX OF 3.3V AND 1.8V PULL-UPS PP3V3_S0_GPU PP1V8_S0_GPU 99 3 4 8 1 98 OF 121 SIZE D A 8 7 6 5 4 3 2 1 BOMOPTION=OMIT_TABLE 99 PP1V8_S0_GPU PPVDDCI_S0_GPU 91 99 110 99 RA800 RA801 5% 1/20W MF 2 201 1.69K 1 1% 1/20W MF 2 201 BOMOPTION=SPEED RA821 99 10K GPU_BP_0 PP1V8_S0_GPU 99 5% 1/20W MF 2 201 99 BOMOPTION=BAFFIN 1 98 98 91 99 110 98 RA802 98 10K 98 5% 1/20W MF 2 201 1 98 98 GPU_BP_1 TPA802 TPA803 TPA804 TPA805 TPA807 TPA808 TPA809 TPA810 99 RA803 150 1% 1/20W MF 2 201 BOMOPTION=SPEED 110 97 94 90 A A A A A A A A TP-P6 TP-P6 TP-P6 TP-P6 TP-P6 TP-P6 TP-P6 BOMOPTION=SPEED 1 1 2 G VER 5 6D SMBUS_SMC_1_S0_SCL RA805 4.7K 1 1 RA806 4.7K 98 RA820 98 10K 5% 1/20W MF 2 201 5% 1/20W MF 2 201 S 1 98 49 IO 3D SMBUS_SMC_1_S0_SDA MF 201 AU17 GPIO_SVC AV17 GPIO_SVD AR17 GPIO_SVT I2C_GPU_PCC_SCL I2C_GPU_PCC_SDA 90 5 G VER 5 S 4 OUT 98 W40 AA40 AA35 AW40 AW41 AA34 U35 GPU_TX_HALF_SWING GFX_VDDCI_ALTV_ZERO GPU_BIF_GEN3_EN_A GPU_SMB_DAT RA812 GPU_GFX_PWR_LEVEL_L 0 110 2 0201 MF GPU_GFX_PWR_LEVEL_R_L 1 5% 1/20W 97 89 PP3V3_S0_GPU 99 93 IN 98 98 GPU_ROM_SI_R 98 GPU_ROM_SCLK_R 98 GPU_ROM_CONFIG<0> 98 GPU_ROM_CONFIG<1> 98 GPU_ROM_CONFIG<2> 98 89 89 GPU_GFX_OVERTEMP DFN1010 4 B Y UA801 NC 3 2 0201 MF 6 74LVC1G08FW5 RA813 GFX_SELF_THROTTLE 0 A GPUVCORE_VR_HOT_L GPU_ROM_SO IN OUT (strap BIFCLK_PM_EN) 5% 1/20W 89 IN 2 DP_X_SNK0_HPD_EG GPU_RESERVED GFX_VDDCI_ALTV_ONE DP_X_SNK1_HPD_EG GPU_GFX_OVERTEMP_R 1 EG_RESET_L 91 111 5 98 GPU_TX_DEEMPH_EN 99 GPU_VRAM_STRAP 98 GPU_ROM_CS_L_R GPU_FDO NC BOMOPTION=SPEED 1 98 RA807 90 10K B IN 5% 1/20W MF 2 201 PP3V3_S0_GPU 5% 1/20W MF 2 201 GPU_JTAG_TDI 98 GPU_JTAG_TCK 98 GPU_JTAG_TMS 98 GPU_JTAG_TDO IN 93 99 110 IN AP25 AM25 AM27 W41 Y40 Y41 AU21 AA41 U34 R37 AV25 R38 AB40 AB41 AP27 U38 W37 W38 GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15 GPIO_16_8P_DETECT GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20 GPIO_21 GPIO_22_ROMCS* GPIO_28_FDO GPIO_29 GPIO_30 AF40 AD40 AE41 AD41 AF41 JTAG_TRST* JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO BA38 NC AV29 NC AU31 NC AV31 NC AU25 AV23 AM29 NC DP_T_SNK0_HPD_EG DP_T_SNK1_HPD_EG GPIO_0 GPIO_1 GPIO_2 SMBCLK SMBDAT GPIO_5_REG_HOT_AC_BATT GPIO_6_TACH librarian reordered pins to follow tx 99 RA823 10K 5% 1/20W MF 2 201 113 98 113 98 100 IN 100 LA800 PP1V8_S0_GPU NC VOLTAGE=1.8V GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG DP_INT_EG_ML_P<2> OUT 89 113 DP_INT_EG_ML_N<2> OUT 89 113 TX4P_DPA1+ AY35 TX4M_DPA1- BA35 DP_INT_EG_ML_P<1> OUT 89 113 DP_INT_EG_ML_N<1> OUT 89 113 TX5P_DPA0+ AY36 TX5M_DPA0- BA36 DP_INT_EG_ML_P<0> OUT 89 113 DP_INT_EG_ML_N<0> OUT 89 113 GPU_PLLCHARZ_H GPU_PLLCHARZ_L NOSTUFF 1 1 10% 10% 2 6.3V X6S 0201 6.3V DP_X_SNK0_ML_C_P<3> OUT 27 113 DP_X_SNK0_ML_C_N<3> OUT 27 113 TX0P_DPB2+ AY30 TX0M_DPB2- BA30 DP_X_SNK0_ML_C_P<2> OUT 27 113 DP_X_SNK0_ML_C_N<2> OUT 27 113 TX1P_DPB1+ AY31 TX1M_DPB1- BA31 DP_X_SNK0_ML_C_P<1> OUT 27 113 DP_X_SNK0_ML_C_N<1> OUT 27 113 TX2P_DPB0+ AY32 TX2M_DPB0- BA32 DP_X_SNK0_ML_C_P<0> OUT 27 113 DP_X_SNK0_ML_C_N<0> OUT 27 113 TXCCP_DPC3+ AY24 TXCCM_DPC3- BA24 DP_X_SNK1_ML_C_P<3> OUT 27 113 DP_X_SNK1_ML_C_N<3> OUT 27 113 TX3P_DPC2+ AY25 TX3M_DPC2- BA25 DP_X_SNK1_ML_C_P<2> OUT 27 113 DP_X_SNK1_ML_C_N<2> OUT 27 113 TX4P_DPC1+ AY26 TX4M_DPC1- BA26 DP_X_SNK1_ML_C_P<1> OUT 27 113 DP_X_SNK1_ML_C_N<1> OUT 27 113 TX5P_DPC0+ AY27 TX5M_DPC0- BA27 DP_X_SNK1_ML_C_P<0> OUT 27 113 DP_X_SNK1_ML_C_N<0> OUT 27 113 TXCDP_DPD3+ AY19 TXCDM_DPD3- BA19 DP_T_SNK0_ML_C_P<3> OUT 101 113 DP_T_SNK0_ML_C_N<3> OUT 101 113 TX2P_DPD0+ AY22 TX2M_DPD0- BA22 DP_T_SNK0_ML_C_P<0> OUT 101 113 DP_T_SNK0_ML_C_N<0> OUT 101 113 TX1P_DPD1+ AY21 TX1M_DPD1- BA21 DP_T_SNK0_ML_C_P<1> OUT 101 113 DP_T_SNK0_ML_C_N<1> OUT 101 113 TX0P_DPD2+ AY20 TX0M_DPD2- BA20 DP_T_SNK0_ML_C_P<2> OUT 101 113 DP_T_SNK0_ML_C_N<2> OUT 101 113 TXCEP_DPE3+ AY14 TXCEM_DPE3- BA14 DP_T_SNK1_ML_C_P<3> OUT 101 113 DP_T_SNK1_ML_C_N<3> OUT 101 113 TX0P_DPE2+ AY15 TX0M_DPE2- BA15 DP_T_SNK1_ML_C_P<2> OUT 101 113 DP_T_SNK1_ML_C_N<2> OUT 101 113 TX1P_DPE1+ AY16 TX1M_DPE1- BA16 DP_T_SNK1_ML_C_P<1> OUT 101 113 DP_T_SNK1_ML_C_N<1> OUT 101 113 TX2P_DPE0+ AY18 TX2M_DPE0- BA18 DP_T_SNK1_ML_C_P<0> OUT 101 113 DP_T_SNK1_ML_C_N<0> OUT 101 113 GPU_AUD<1> 98 GPU_AUD<0> 98 EG_LCD_PWR_EN NC NC 1 OUT 2 X6S 0201 PLACE_NEAR=LA800.1:2.54MM CA850 0.1UF PLACE_NEAR=UA000.AM13:2.54MM 10% 0.1UF GPU_PLLCHARZ_RC_H 1 CA851 10UF 6.3V 2 X6S 0201 NOSTUFF 1 RA880 51.1 1% 1/20W MF 2 201 NOSTUFF 1 RA881 51.1 1% 1/20W MF 2 201 C 89 RA810 1 1 RA811 BOMOPTION=BAFFIN 0 5% 1/20W MF 201 RA815 10K 5% 1/20W MF 2 0201 1K 5% 1/20W MF 2 201 PP1V8_S0_GPU 2 91 99 110 BOMOPTION=BAFFIN B GPU_CLKREQ_L 98 DP_INT_EG_AUX_P IO 89 113 DP_INT_EG_AUX_N IO 89 113 DDC2CLK AV19NC DDC2DATA AU19NC AUX2+ AP19 AUX2- AM19 DP_X_SNK0_AUXCH_C_P IO 27 113 DP_X_SNK0_AUXCH_C_N IO 27 113 DDCAUX3+ AM21 DDCAUX3- AP21 DP_X_SNK1_AUXCH_C_P IO 27 113 DP_X_SNK1_AUXCH_C_N IO 27 113 DDCAUX4+ AR23 DDCAUX4- AP23 DP_T_SNK0_AUXCH_C_P IO 101 113 DP_T_SNK0_AUXCH_C_N IO 101 113 DDCAUX5+ AU27 DDCAUX5- AV27 DP_T_SNK1_AUXCH_C_P IO 101 113 IO 101 113 DP_T_SNK1_AUXCH_C_N DDCVGACLK AN34NC DDCVGADATA AP31NC N38 TS_A SYNC_MASTER=X363_SEAN 2 CERM-X6S 0402 WWW.AliSaler.Com 7 SYNC_DATE=01/27/2016 PAGE TITLE Baffin DP/GPIO DRAWING NUMBER RSVD K41 NC RSVD R34 NC Apple Inc. 1 CA852 1 20% 10% 2 6.3V X6S 0201 1UF 6.3V 2 X6S-CERM 0201 CA853 0.1UF 051-00647 REVISION 6 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE BOM_COST_GROUP=GRAPHICS II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 4 3 2 108 OF 145 SHEET IV ALL RIGHTS RESERVED 5 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE PLACE_NEAR=UA000.AM13:2.54MM PLACE_NEAR=UA000.AM13:2.54MM PLACE_NEAR=UA000.AM13:2.54MM 8 D GPU_PLLCHARZ_RC_L R 20% 6.3V 99 CA881 0402 1 99 NOSTUFF CA880 0.1UF TXCBP_DPB3+ AY28 TXCBM_DPB3- BA28 AUX1+ AY11 AUX1- BA11 AM13 TSVDD PP1V8_GPU_TSVDD TX3P_DPA2+ AY34 TX3M_DPA2- BA34 DDC1CLK AY10NC DDC1DATA BA10NC MIN_NECK_WIDTH=0.2000 2 89 113 CLKREQ* AV40 MIN_LINE_WIDTH=0.4000 120OHM-25%-1.8A-0.06DCR 1 OUT OUT GENLK_CLK AR29NC GENLK_VSYNC AP29NC N35 DPLUS N34 DMINUS GPUTHMSNS_D1_P GPUTHMSNS_D1_N 89 113 GPU_DIECRACKMON TEST6 B2 BA13 GPU_TEST_PG_BACON TEST_PG_BACO BOMOPTION=VRAM:GRP1 A OUT DP_INT_EG_ML_N<3> TEMPIN0 J8 TEMPINRETURN J7 BA39 XTALIN AY39 XTALOUT GPU_XTAL_OR_CLK_IN GPU_XTAL_OUT DP_INT_EG_ML_P<3> DIGON AC40 AV21 HPD1 DP_INT_EG_HPD TXCAP_DPA3+ AY33 TXCAM_DPA3- BA33 HSYNC W34 VSYNC W35 BOMOPTION=VRAM:GRP2 GPU_VRAM_STRAP 110 GPU_VCORE_PCC 98 89 pins to follow tx RA822 10K 1 (MLPS enabled for SPEED) GPU_JTAG_TRST_L IN (strap BIOS_ROM_EN) GPU_VGA_DIS 98 89 89 1 (strap reserved) GFX_SELF_THROTTLE_R 1 librarian reordered AC35 SCL AC34 SDA GPU_SMB_CLK 89 BGA SYM 2 OF 7 DBGDATA_0 DBGDATA_1 DBGDATA_2 DBGDATA_3 DBGDATA_4 DBGDATA_5 DBGDATA_6 DBGDATA_7 DBGDATA_8 DBGDATA_9 DBGDATA_10 DBGDATA_11 DBGDATA_12 DBGDATA_13 DBGDATA_14 DBGDATA_15 AG34 SWAPLOCKA NC AE34 SWAPLOCKB NC 90 SOT563 100-CK4803-ES AY38 ANALOGIO GPU_ANALOGIO 1/20W 5% 1/20W MF 2 201 QA800 DMN5L06VK-7 C 150 RA804 2 GPU_GPIO_SVC_R GPU_GPIO_SVD_R GPUVCORE_SVT 98 SOT563 L40 L41 M40 M41 N40 N41 P40 P41 R40 R41 T40 T41 U40 U41 V40 V41 UA000 AU40 WAKE* NC QA800 IN 1 1 1 1 1 1 1 1 TP-P6 1% DMN5L06VK-7 49 AA38 BP_0 AA37 BP_1 PP3V3_S0_GPU PP3V3_S0_GPU 110 GPU_BP_0 GPU_BP_1 GPU_AUD_PORT_CONN<0> GPU_AUD_PORT_CONN<1> GPU_AUD_PORT_CONN<2> GPU_BRD_CFG<0> GPU_BRD_CFG<1> GPU_BRD_CFG<2> GPU_SMBUS_ADDR<0> GPU_SMBUS_ADDR<1> GPU_DBG_8 GPU_DBG_9 GPU_DBG_10 GPU_DBG_11 GPU_MPLS_PS_0 GPU_MPLS_PS_1 GPU_MPLS_PS_2 GPU_MPLS_PS_3 98 BOMOPTION=BAFFIN D TP_EG_BKLT_PWM AC37 BL_ENABLE AC38 BL_PWM_DIM EG_BKLT_EN 1 10K AU15 PLLCHARZ_H AV15 PLLCHARZ_L 110 89 OUT 1 GPU_PLLCHARZ_H GPU_PLLCHARZ_L 1 99 OF 121 SIZE D A 8 7 6 5 4 3 2 1 PPBUS_HS_GPU 109 12PF CRITICAL 1 CRITICAL CA901 1 3.0PF 25V 25V 2 NP0-C0G 0201 1 20% 20% 2 25V X6S-CERM 0402 2 16V POLY-TANT CASED12-SM 2 NP0-C0G 0201 CA903 CRITICAL 1 2.2UF 33UF +/-0.1PF 5% CRITICAL CA902 2.2UF 20% 2 25V X6S-CERM P1V8GPU_PGOOD 0402 TPS62130B MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 D 2 IN 5% 1/20W MF 201 P1V8GPU_EN RA900 10 10 AVIN 8 DEF 13 7 QFN CRITICAL VOS EN FSW 1.5UH-20%-2.61A-0.068OHM REG_PHASE_1V8GPU 1 PP1V8_GPU 2 1 REG_VOS_P1V8GPU REG_FB_P1V8GPU SYM 7 OF 7 VSS A VSS PX_EN 100-CK4803-ES BGA SYM 6 OF 7 VSS VSS PAD THRM CA907 47UF 20% 2 6.3V POLY-TANT 0805 CRITICAL 1 CA908 47UF 20% 2 6.3V POLY-TANT 0805 CRITICAL CRITICAL 1 CA909 47UF 20% 2 6.3V POLY-TANT 0805 1 CA910 47UF 20% 2 6.3V POLY-TANT 0805 CRITICAL 1 CA911 47UF 20% POLY-TANT 0805 20% 2 6.3V POLY-TANT 0805 2 6.3V 17 RA902 105K 0.1% 1/16W MF 2 0402 CA906 4700PF 10% 2 10V X7R 201 <Ra> 1 RA903 82.5K 1% 1/16W MF-LF 2 402 XWA900 SM <Rb> AGND_P1V8GPU MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0850 1 2 XWA901 SM P1V8GPU_FSW 1 2 C Vout = 0.8V * ( Ra + Rb ) / Rb PART NUMBER QTY 353S00897 DESCRIPTION 1 REFERENCE DES CRITICAL BOM OPTION CRITICAL UA900 IC,TPS62130B-S,3A BUCK CNVTRT,QFN16,3X3M GPU THERMAL RA960 110 PP3V3_S0 47 1 GPUTHMSNS_D1_P GPUTHMSNS_D1_P 99 OUT MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 1 2200PF V+ 10% 10V X7R-CERM 2 0201 MAKE_BASE=TRUE GPUTHMSNS_D2_P 3 SOT23-8 2 49 B Placement Note: Place UA960 Bottom side, under the VRAM shield can, but not within 2mm of any IC 10% CRITICAL 10V X7R-CERM 2 0201 GPUTHMSNS_D2_N 49 5 1 2200PF BC846BLP SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SCL 7 SDA 6 GND CA962 1 GPUTHRM_SNS THERMAL SENSOR: VRAM PROXIMITY UA960 TMP442A 3 DXP2 4 DXN2 NO_XNET_CONNECTION=1 QA960 DFN1006H4-3 1 DXP1 2 DXN1 PLACE_NEAR=UA960.3:5MM GPUTHMSNS_D1_N CRITICAL 8 TBTTHRM_SNS GPUTHMSNS_D1_N CA960 0.1UF NO_XNET_CONNECTION=1 PLACE_NEAR=UA960.2:5MM THERMAL DIODE: GPU DIE IN 1 10% 2 6.3V CERM-X5R 0201 CA961 99 BYPASS=UA960.1::5MM PP3V3_S0_GPUTHMSNS_R 2 5% 1/20W MF 201 TBTTHRM_SNS I2C Write: 0x98, I2C Read: 0x99 THERMAL DIODE: GPU PROXIMITY 3.3V S0 GPU Switch 110 110 10% VDD X5R 2 402-1 UA950 10V 1 91 IN CA953 P3V3GPU_RAMP CAP P3V3GPU_EN 2 ON TDFN PCC:YES 10% VDD X5R 2 402-1 UA951 10V D 3 PP3V3_S0 110 S 5 PP3V3_S0_GPU 110 EDP: 0.100 A CA952 1 91 SLG5AP1453V P5VGPU_RAMP 7 CAP P3V3GPU_EN 2 ON PCC:YES GND 10% 1 1UF SLG5AP1453V 7 4700PF PP5V_S0 PCC:YES 1 1UF CA950 5V S0 GPU Switch PP3V3_S5 CA951 AC41 NC IN 4700PF TDFN D 3 S 5 VOLTAGE=5V GND 10% 10V X7R 2 201 PP5V_S0_GPUFET 90 91 EDP: 0.100 A MIN_NECK_WIDTH=0.1000 SYNC_MASTER=X363_SEAN SYNC_DATE=01/27/2016 PAGE TITLE Baffin VSS & MISC MIN_LINE_WIDTH=0.1000 UA950 Part SLG5AP1453V DRAWING NUMBER Part Apple Inc. SLG5AP1453V 051-00647 REVISION R Type Load Switch Type Load Switch R(on) @ 5.3A 7.8 mOhm Typ 9.6 mOhm Max R(on) @ 5.3A 7.8 mOhm Typ 9.6 mOhm Max Current 5.3A Max Current 5.3A Max UA951 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=GRAPHICS II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 7 6 5 4 3 2 10.0.0 dvt-fab10 109 OF 145 SHEET 100 OF 121 IV ALL RIGHTS RESERVED WWW.AliSaler.Com CA912 Placement Note: Place QA960 TOP side, under the GPU 10V X7R 2 201 8 CRITICAL 1 47UF D 1 BGA UA000 1 8 100-CK4803-ES AJ1 AJ10 AJ11 AJ3 AJ35 AJ39 AJ5 AL10 AL11 AL3 AL32 AL35 AL39 AL7 AM17 AM23 AN1 AN3 AN35 AN39 AN40 AN41 AN7 AP13 AP17 AR11 AR19 AR21 AR25 AR27 AR3 AR31 AR35 AR39 AR7 AU1 AU23 AU29 AU3 AU9 AW11 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27 116 REG_SSTR_P1V8GPU SS/TR 9 1 B UA000 A13 A17 A2 A21 A25 A29 A33 A37 A40 A5 A9 AA1 AA10 AA17 AA19 AA25 AA27 AA3 AA32 AA39 AA5 AC11 AC17 AC19 AC25 AC27 AC3 AC39 AC7 AE1 AE10 AE17 AE19 AE25 AE27 AE3 AE32 AE35 AE39 AE5 AG11 AG17 AG19 AG25 AG27 AG3 AG39 AG40 AG41 AG7 G31 G35 G39 G7 J1 J3 J34 J37 J39 J40 J41 J5 K21 K25 K29 K40 L11 L15 L19 L23 L27 L3 L31 L35 L39 L7 N1 N17 N19 N25 N27 N3 N32 N37 N39 N5 R11 R17 R19 R25 R27 R3 R32 R35 R39 R7 U1 U17 U19 U25 U27 U3 U32 U37 U39 U5 W11 W17 W19 W25 W27 W3 W39 W7 1 5% 1/20W MF 2 201 1 8 C AW29 AW3 AW31 AW33 AW35 AW37 AW39 AW5 AW7 AW9 AY1 AY12 AY17 AY2 AY23 AY29 AY37 AY40 AY41 AY9 B1 B40 B41 BA17 BA2 BA23 BA29 BA37 BA40 BA5 BA9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C5 C7 C9 E1 E13 E17 E21 E25 E29 E3 E39 E4 E41 E9 G11 G15 G19 G23 G27 G3 10% 2 25V X6S 0402 BOMOPTION=OMIT_TABLE 15 16 BOMOPTION=OMIT_TABLE AGND 0.1UF 6 PGND PGND CA905 CRITICAL RA901 10 PG 4 1 110 PIFE32251B-SM 14 FB 5 91 LA900 DIDT=TRUE SW 1 SW 2 SW 3 OUT 1.818 V 2.3 A 1250 kHz CRITICAL MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 UA900 PPVIN_S0GPU_1V8_RC 1 OMIT_TABLE TPS62130 VOLTAGE=1.8V 91 Output voltage: Max peak current: Switching freq: CA904 PVIN 12 CA900 PVIN 11 CRITICAL 1 1 SIZE D A 7 6 PP3V3_UPC_TA_LDO 10% 2 6.3V CERM 402 5% 1/20W MF 201 2 113 103 IN 113 103 IN PCIE_TBT_T_R2D_P<0> PCIE_TBT_T_R2D_N<0> UB090 8MBIT-3.0V CLK 103 TBT_T_SPI_CS_L 1 CS* 101 TBT_T_ROM_WP_L 3 WP*(IO2) 7 HOLD*(IO3) TBT_T_ROM_HOLD_L DI(IO0) 5 DO(IO1) 2 USON TBT_T_SPI_MOSI TBT_T_SPI_MISO 103 OMIT_TABLE CRITICAL 103 113 103 113 113 113 113 C 113 113 113 113 113 99 99 99 99 99 99 99 99 99 IN 0.1UF CB021 1 CB022 DP_T_SNK0_ML_C_P<1> 1 0.1UF CB023 DP_T_SNK0_ML_C_N<1> IN 1 0.1UF IN DP_T_SNK0_ML_C_P<2> IN DP_T_SNK0_ML_C_N<2> CB024 1 0.1UF CB025 1 0.1UF IN DP_T_SNK0_ML_C_P<3> IN DP_T_SNK0_ML_C_N<3> BI 1 0.1UF IN BI CB020 DP_T_SNK0_ML_C_N<0> IN CB026 1 CB027 1 0.1UF 0.1UF CB028 DP_T_SNK0_AUXCH_C_P 1 0.1UF CB029 DP_T_SNK0_AUXCH_C_N 1 0.1UF 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_T_SNK0_ML_P<0> 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_T_SNK0_ML_P<1> 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 0201 DP_T_SNK0_ML_N<0> 0201 0201 DP_T_SNK0_ML_N<1> 0201 DP_T_SNK0_ML_P<2> 0201 DP_T_SNK0_ML_N<2> 0201 DP_T_SNK0_ML_P<3> 0201 DP_T_SNK0_ML_N<3> 0201 DP_T_SNK0_AUXCH_P 0201 DP_T_SNK0_AUXCH_N 0201 101 113 103 IN 113 103 IN 113 103 IN 113 103 101 12 IN 12 IN 20 OUT 101 101 101 101 101 101 101 101 113 GND_VOID=TRUE 113 GND_VOID=TRUE 113 GND_VOID=TRUE 113 113 113 B 113 113 113 113 113 113 99 99 99 99 99 99 99 99 99 IN DP_T_SNK1_ML_C_N<0> IN DP_T_SNK1_ML_C_P<1> IN DP_T_SNK1_ML_C_N<1> IN IN DP_T_SNK1_ML_C_N<2> IN DP_T_SNK1_ML_C_P<3> 0.1UF CB031 1 CB032 1 0.1UF CB033 1 CB034 1 CB035 1 CB036 1 0.1UF 0.1UF DP_T_SNK1_ML_C_N<3> IN BI 1 0.1UF DP_T_SNK1_ML_C_P<2> BI CB030 0.1UF IN 0.1UF CB037 1 0.1UF DP_T_SNK1_AUXCH_C_P DP_T_SNK1_AUXCH_C_N GND_VOID=TRUE GND_VOID=TRUE 89 113 CB038 1 0.1UF CB039 1 0.1UF A 1 1 1 100K 1M 1M 1 1M 1 1M 2 2 5% 5% 2 5% 2 5% 2 5% 2 5% RB062 1/20W MF RB072 1/20W MF 201 201 RB060 1/20W MF 201 RB061 1/20W MF 201 101 DP_TB_HPD TBT_TA_LSRX 101 RB0301 GND_VOID=TRUE 100K 113 5% 1/20W MF 201 2 GND_VOID=TRUE 113 101 105 RB071 TBT_TB_LSRX 101 105 MF 201 PCIE_TBT_T_D2R_C_P<0> PCIE_TBT_T_D2R_C_N<0> OUT 103 113 OUT 103 113 PCIE_REFCLK_100_IN_P PCIE_REFCLK_100_IN_N PCIE_CLKREQ* FCBGA PCIE_RX1_P PCIE_RX1_N PCIE_TX1_P PCIE_TX1_N P23 P22 PCIE_TBT_T_D2R_C_P<1> PCIE_TBT_T_D2R_C_N<1> OUT 103 113 OUT 103 OMIT_TABLE 113 PCIE_TX2_P PCIE_TX2_N K23 K22 PCIE_TBT_T_D2R_C_P<2> PCIE_TBT_T_D2R_C_N<2> OUT 103 113 OUT 103 113 PCIE_TX3_P PCIE_TX3_N F23 F22 PCIE_TBT_T_D2R_C_P<3> PCIE_TBT_T_D2R_C_N<3> OUT 103 113 OUT 103 113 D 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 0201 DP_T_SNK1_ML_N<0> 0201 101 113 OUT 101 113 DP_T_SNK1_ML_N<2> 101 113 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_T_SNK1_ML_P<3> 101 113 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM DP_T_SNK1_AUXCH_P 0201 0201 DP_T_SNK1_ML_N<3> 0201 0201 DP_T_SNK1_AUXCH_N 0201 113 101 113 101 113 101 113 101 113 101 113 101 101 101 5% 1/20W MF 201 2 113 101 113 101 113 101 113 101 101 113 101 113 101 113 101 DPSNK0_ML0_P DPSNK0_ML0_N DP_T_SNK0_ML_P<1> DP_T_SNK0_ML_N<1> AB9 AC9 DPSNK0_ML1_P DPSNK0_ML1_N DP_T_SNK0_ML_P<2> DP_T_SNK0_ML_N<2> AB11 AC11 DPSNK0_ML2_P DPSNK0_ML2_N DP_T_SNK0_ML_P<3> DP_T_SNK0_ML_N<3> AB13 AC13 DPSNK0_ML3_P DPSNK0_ML3_N DP_T_SNK0_AUXCH_P DP_T_SNK0_AUXCH_N Y11 W11 DP_T_SNK0_HPD AA2 113 101 113 113 14K GND_VOID=TRUE DP_T_SNK1_ML_P<1> DP_T_SNK1_ML_N<1> AB17 AC17 DPSNK1_ML1_P DPSNK1_ML1_N DP_T_SNK1_ML_P<2> DP_T_SNK1_ML_N<2> AB19 AC19 DPSNK1_ML2_P DPSNK1_ML2_N DP_T_SNK1_ML_P<3> DP_T_SNK1_ML_N<3> AB21 AC21 DPSNK1_ML3_P DPSNK1_ML3_N GND_VOID=TRUE BI Y18 PLACE_NEAR=UB000.Y18:4MM 29 27 IN 103 29 15 IN 29 27 IN 103 29 27 OUT 2 4.75K 1/20W 0.5% 0201 RB055 PLACE_NEAR=UB000.H6:2MM GND_VOID=TRUE GND_VOID=TRUE 113 113 104 104 BI BI DP_TA_AUXCH_P 0201 DP_TA_AUXCH_N 0201 2 16V 10% X5R-CERM 1 2 16V 10% X5R-CERM 1 CB010 104 PLACE_NEAR=UB000.H19:2MM Y4 V4 T4 W4 TDI TMS TCK TDO TBT_T_RBIAS TBT_T_RSENSE H6 J6 RBIAS RSENSE RB054 105 103 OUT 103 DPSRC_ML2_P DPSRC_ML2_N L2 L1 NC_DP_T_SRC_ML_P<2> NC_DP_T_SRC_ML_N<2> OUT 103 OUT 103 DPSRC_ML3_P DPSRC_ML3_N J2 J1 NC_DP_T_SRC_ML_P<3> NC_DP_T_SRC_ML_N<3> OUT 103 OUT 103 DPSRC_AUX_P DPSRC_AUX_N W19 Y19 NC_DP_T_SRC_AUX_P NC_DP_T_SRC_AUX_N OUT 103 OUT 103 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6 TEST_PWR_GOOD MISC G1 DP_T_SRC_HPD DP_T_SRC_RBIAS U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1 I2C_TBT_T_SDA I2C_TBT_T_SCL TBT_T_ROM_WP_L 101 TBT_T_TMU_CLK_OUT SMC_PME_S4_DARK_L TBT_T_CIO_PLUG_EVENT_L TBT_T_HDMI_DDC_DATA TBT_T_HDMI_DDC_CLK TBT_T_TMU_CLK_IN I2C_TBT_TA_INT_L I2C_TBT_TB_INT_L TBT_T_USB_PWR_EN TBT_T_FORCE_PWR PM_BATLOW_L PM_SLP_S3_L TBT_T_CIO_PWR_EN TBT_T_TEST_EN AB5 TBT_T_TEST_PWR_GOOD F4 USBC_T_RESET_L XTAL_25_IN XTAL_25_OUT D22 D23 TBT_T_XTAL25M_IN TBT_T_XTAL25M_OUT EE_DI EE_DO EE_CS* EE_CLK AB3 AC4 AC3 AB4 UPC_T_SPI_MOSI UPC_T_SPI_MISO UPC_T_SPI_CS_L UPC_T_SPI_CLK PB_TX1_P PB_TX1_N A9 B9 USBC_TA_R2D_C_P<1> USBC_TA_R2D_C_N<1> A19 B19 PA_TX0_P PA_TX0_N PB_TX0_P PB_TX0_N USBC_TA_D2R_P<1> USBC_TA_D2R_N<1> B21 A21 PA_RX0_P PA_RX0_N PB_RX0_P PB_RX0_N DP_TA_AUXCH_C_P 113 DP_TA_AUXCH_C_N Y15 W15 PA_DPSRC_AUX_P PA_DPSRC_AUX_N USB_UPC_TA_P USB_UPC_TA_N E20 D20 PA_USB2_D_P PA_USB2_D_N 113 106 OUT 113 106 OUT 113 106 OUT 113 106 IN 113 106 IN 103 BI 103 BI 104 101 OUT 104 101 IN 104 101 IN TBT_TA_LSTX TBT_TA_LSRX DP_TA_HPD TBTTHMSNS_T_D1_P PB_USB2_D_P PB_USB2_D_N L15 N15 FUSE_VQPS_64 FUSE_VQPS_128 DEBUG BI 91 IN 29 IN 103 IN 12 20 27 46 70 73 76 89 114 IN 103 104 C 103 103 107 IN 103 113 OUT 103 113 29 103 29 103 29 103 29 103 101 107 RB037 103 5% 1/20W MF 2 201 103 105 PU at PCH not used 1 PU at PCH RB029 100 5% 1/20W MF 2 201 RB027 100K 105 1 IN RB025 5% 1/20W MF 2 201 100 5% 1/20W MF 2 201 B To SPI Flash OUT 106 113 OUT 106 113 A13 B13 USBC_TB_D2R_P<1> USBC_TB_D2R_N<1> IN 106 113 IN 106 113 Y16 W16 DP_TB_AUXCH_C_P DP_TB_AUXCH_C_N E19 D19 USB_UPC_TB_P USB_UPC_TB_N GND_VOID=TRUE CB0121 2 DP_TB_AUXCH_P 10% 16V 0201 X5R-CERM CB0131 2 DP_TB_AUXCH_N 10% 16V 0201 X5R-CERM 0.1UF BI 103 BI 103 0.1UF OUT 101 105 IN 101 105 IN 101 105 BI 105 113 BI 105 113 GND_VOID=TRUE PLACE_NEAR=UB000.F19:2MM D6 W13 W18 104 1 USBC_TB_R2D_C_P<1> USBC_TB_R2D_C_N<1> MONDC_DPSNK_0 MONDC_DPSNK_1 RB035 2.2K 5% 1/20W MF 2 201 IN A11 B11 E18 1 IN 113 USB2_ATEST 2.2K 103 OUT ATEST_P ATEST_N RB036 IN 113 A23 B23 1 91 OUT 106 TBT_TB_USB2_RBIAS TEST_EDM 103 106 F19 AC1 OUT OUT PB_USB2_RBIAS PCIE_ATEST OUT C23 C22 MONDC_CIO_0 MONDC_CIO_1 MONDC_DPSRC 1 NC NC NC RB053 499 1% 1/20W MF 2 201 LAST_MODIFIED=Wed Aug 24 09:58:00 2016 DRAWING SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE USB-C HIGH SPEED 1 DRAWING NUMBER Apple Inc. 051-00647 REVISION AB2 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=TBT WWW.AliSaler.Com 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 110 OF 145 SHEET 101 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 8 107 2.2K PP3V3_S5_TBT_T_SW 103 27 29 103 101 5% 1/20W MF 2 201 5% 1/20W MF 2 201 14K OUT USBC_TB_R2D_C_P<2> USBC_TB_R2D_C_N<2> PA_USB2_RBIAS 2.2K 1 BI 113 H19 RB034 BI IN TBT_TB_LSTX TBT_TB_LSRX DP_TB_HPD 1 MF 201 2 1% 113 B4 B5 G2 V18 1 106 PB_LSTX PB_LSRX PB_DPSRC_HPD MONDC_SVR 1/20W 106 PA_LSTX PA_LSRX PA_DPSRC_HPD THERMDA THERMDA PLACE_NEAR= UB000.N6:2MM IN A5 A4 M4 AC23 AB23 NC 113 PB_DPSRC_AUX_P 113 PB_DPSRC_AUX_N PP3V3_S5_TBT_T_SW RB052 N6 E1 3.01K 2 1% 1/20W MF 201 103 PA_TX1_P PA_TX1_N OUT USE NEAREST GND BALL (AC22) FOR THERM_D_N 499 OUT A17 B17 106 OUT NC_DP_T_SRC_ML_P<1> NC_DP_T_SRC_ML_N<1> USBC_TA_R2D_C_P<2> USBC_TA_R2D_C_N<2> 113 54 N2 N1 USBC_TB_D2R_P<2> USBC_TB_D2R_N<2> IN 113 1 DPSRC_ML1_P DPSRC_ML1_N B7 A7 IN CB011 103 PB_RX1_P PB_RX1_N 106 0.1UF OUT PA_RX1_P PA_RX1_N 113 0.1UF 103 A15 B15 106 113 JTAG_TBT_TDI JTAG_TBT_T_TMS JTAG_TBT_TCK JTAG_ISP_TDO 1 OUT TEST_EN DPSNK_RBIAS TBT_T_PCIE_BIAS RB051 20 NC_DP_T_SRC_ML_P<0> NC_DP_T_SRC_ML_N<0> DPSRC_RBIAS DPSNK1_DDC_CLK DPSNK1_DDC_DATA N16 IN DPSRC_ML0_P DPSRC_ML0_N DPSRC_HPD DPSNK1_HPD TBT_T_PCI_RESET_L USBC_TA_D2R_P<2> USBC_TA_D2R_N<2> 113 PLACE_NEAR=UB000.J6:2MM 113 DPSNK1_AUX_P DPSNK1_AUX_N L4 R2 R1 RESET* GND_VOID=TRUE 1 Y8 N4 DP_T_SNK_RBIAS 1% 201 MF 1/20W GND_VOID=TRUE Y6 PCIE_RBIAS DPSNK0_DDC_CLK DPSNK0_DDC_DATA DPSNK1_ML0_P DPSNK1_ML0_N Y12 W12 PERST* DPSNK0_HPD AB15 AC15 DP_T_SNK1_DDC_CLK DP_T_SNK1_DDC_DATA IN DPSNK0_AUX_P DPSNK0_AUX_N DP_T_SNK1_ML_P<0> DP_T_SNK1_ML_N<0> RB050 TF Y5 R4 DP_T_SNK1_AUXCH_P DP_T_SNK1_AUXCH_N 1 GND_VOID=TRUE 101 101 113 103 GND_VOID=TRUE 101 AB7 AC7 DP_T_SNK1_HPD GND_VOID=TRUE GND_VOID=TRUE 101 DP_T_SNK0_ML_P<0> DP_T_SNK0_ML_N<0> DP_T_SNK0_DDC_CLK DP_T_SNK0_DDC_DATA 1 2 DP_T_SNK1_ML_P<2> 0201 101 103 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 0201 113 113 DP_T_SNK1_ML_P<1> DP_T_SNK1_ML_N<1> 101 BI GND_VOID=TRUE 2 10% 16V X5R-CERM 2 10% 16V X5R-CERM 0201 113 113 GND_VOID=TRUE 101 101 103 100K DP_T_SNK1_ML_P<0> 113 PLACE_NEAR=UB000.N16:5MM R 101 1/20W V19 T19 AC5 101 IN GND_VOID=TRUE 104 TBT_TB_LSTX MF 201 PCIE_CLK100M_TBT_T_P PCIE_CLK100M_TBT_T_N TBT_T_CLKREQ_L 104 RB070 1/20W PCIE_RX3_P PCIE_RX3_N 113 103 113 1% 1/20W MF 201 2 101 V23 V22 CRITICAL TBT_TA_USB2_RBIAS DP_TA_HPD TBT_TA_LSTX H23 H22 OUT GND_VOID=TRUE 100K PCIE_TBT_T_R2D_P<3> PCIE_TBT_T_R2D_N<3> 113 113 1 PCIE_RX2_P PCIE_RX2_N 113 SNK1 AC Coupling 99 M23 M22 113 RB031 113 PCIE_TBT_T_R2D_P<2> PCIE_TBT_T_R2D_N<2> IN GND_VOID=TRUE 89 DP_T_SNK1_ML_C_P<0> T23 T22 IN SNK0 AC Coupling DP_T_SNK0_ML_C_P<0> PCIE_TBT_T_R2D_P<1> PCIE_TBT_T_R2D_N<1> IN 10K PU ON CLOCKS PAGE 99 TBT-AR-4C-CNTRL PCIE_TX0_P PCIE_TX0_N 9 4 113 103 GND EPAD 113 UB000 SOURCE PORT 0 103 PCIE_RX0_P PCIE_RX0_N LC GPIO D W25Q80DVUXIE 6 1 SYM 1 OF 2 VCC TBT_T_SPI_CLK Y23 Y22 POC GPIO 5% 1/20W MF 2 201 PORT B 5% 1/20W MF 2 201 1UF 3.3K TBT PORTS 3.3K 3.3K 2 CB090 SINK PORT 0 RB090 5% 1/20W MF 201 2 RB092 SINK PORT 1 3.3K RB093 3 103 1 1 4 PORT A 1 1 8 RB091 1 5 PCIE GEN3 8 1 SIZE D A 6 SOURCED BY INTERNAL SWITCH 1 CB130 1.0UF 20% 2 6.3V X5R 0201-1 1 CB131 1 1.0UF CB132 1 1.0UF 20% 2 6.3V X5R 0201-1 CB133 1 1.0UF 20% 2 6.3V X5R 0201-1 CB134 1 1.0UF 20% 2 6.3V X5R 0201-1 PP0V9_TBT_T_DP CB135 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V CB136 1 1.0UF 20% 2 6.3V X5R 0201-1 5 1.0UF 20% 2 6.3V X5R 0201-1 20% 2 6.3V X5R 0201-1 SOURCED BY INTERNAL SWITCH PP0V9_TBT_T_PCIE D 1 CB164 1.0UF 20% 2 6.3V X5R 0201-1 1 CB165 1.0UF 20% 2 6.3V X5R 0201-1 1 CB166 1 1.0UF CB167 1.0UF 20% 2 6.3V X5R 0201-1 20% 2 6.3V X5R 0201-1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V SOURCED BY INTERNAL SWITCH 1 CB184 1.0UF 20% 2 6.3V X5R 0201-1 1 CB185 1.0UF 1.0UF 20% 6.3V 2 X5R 0201-1 CB146 1 1.0UF 20% 6.3V 2 X5R 0201-1 PP0V9_TBT_T_CIO PP3V3_TBT_T_ANA_PCIE PP3V3_TBT_T_ANA_USB2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 1 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V SOURCED BY INTERNAL SWITCH MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V CB145 PP0V9_TBT_T_USB SOURCED BY INTERNAL SWITCH 20% 2 6.3V X5R 0201-1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V CB147 1.0UF 1 20% 6.3V 2 X5R 0201-1 CB120 1.0UF 20% 2 6.3V X5R 0201-1 1 CB121 1.0UF 20% 2 6.3V X5R 0201-1 SOURCED BY INTERNAL SWITCH C B A WWW.AliSaler.Com 8 7 6 L8 L11 L12 M8 T11 T12 L6 M6 V11 V12 V13 VCC0P9_DP VCC0P9_DP TBT-AR-4C-CNTRL VCC0P9_DP VCC0P9_DP SYM 2 OF 2 FCBGA VCC0P9_DP OMIT_TABLE VCC0P9_DP CRITICAL VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK UB000 M13 M15 M16 L19 N19 L18 M18 N18 VCC0P9_PCIE VCC0P9_PCIE VCC0P9_PCIE VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 R15 R16 VCC0P9_USB VCC0P9_USB R8 R9 R11 R12 VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO L16 J16 A6 A8 A10 A12 A14 A16 A18 A20 A22 B6 B8 B10 B12 B14 B16 B18 B20 B22 D8 D9 D11 D12 D13 D15 D16 D18 E8 E9 E11 E15 E16 E22 E23 F9 F20 F16 G22 G23 H1 H2 H12 H13 H15 H16 H20 J5 J19 J20 J18 J22 J23 K1 K2 L5 L20 L22 L23 M1 M2 M5 M19 M20 N5 N20 N22 N23 P1 P2 R5 R18 R19 R20 R22 4 VCC3P3_LC R6 VCC3P3_SX F8 VCC3P3_S0 R13 VCC3P3A VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR VCC0P9_SVR VCC0P9_SVR VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_SENSE VCC 7 VCC3P3_ANA_PCIE VCC3P3_ANA_USB2 VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA 5 2 1 PP3V3_TBT_T_LC PP3V3_S5_TBT_T_SW PP3V3_TBT_T_F 1 A2 A3 B3 L9 M9 E12 E13 F11 F12 F13 F15 J9 SVR_VSS SVR_VSS SVR_VSS A1 B1 B2 F18 H18 J11 H11 R23 T1 T2 T5 T20 U23 U22 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 M11 1 VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 H9 SVR_IND SVR_IND SVR_IND VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 107 C1 C2 D1 VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR_SENSE GND 8 CB191 CB190 CB194 1.0UF 1.0UF 47UF 20% 6.3V 2 X5R 0201-1 20% 2 6.3V X5R 0201-1 CB195 1 CB181 20% 2 6.3V X5R 0201-1 20% 6.3V CER-X5R 2 0603 PP3V3_TBT_T_S0 1 CB175 CB176 1 10UF 1 10UF 1 10UF 20% 20% 6.3V 2 6.3V 2 CERM-X5R CERM-X5R 0402-4 0402-4 BYPASS=UB000.A2:A1:3MM 116 CB177 10% 2 16V X5R-CERM 0201 1.0UF CRITICAL 47UF 20% 6.3V CER-X5R 2 0603 1 LB190 1.0UH-20%-2.1A-0.128OHM 1 CB180 0.1UF FROM USB-C PORT CONTROLLER (UPC) 2 0603 1 1 SOURCED BY INTERNAL SWITCH MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 103 110 116 D CB178 10UF 20% 6.3V 2 CERM-X5R 0402-4 20% 6.3V 2 CERM-X5R 0402-4 PP0V9_TBT_T_SVR MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V 1 LB150 VR0V9_IND_TBT_T 1 1 1 CB111 1.0UF 20% 2 6.3V X5R 0201-1 20% 2 6.3V X5R 0201-1 5% 2 25V NP0-C0G 0201 2 CB110 1.0UF 12PF 0.68UH-20%-6.1A-0.020OHM DIDT=TRUE SWITCH_NODE=TRUE CB117 1 CB112 1.0UF 20% 2 6.3V X5R 0201-1 1 CB113 1.0UF 20% 2 6.3V X5R 0201-1 CB114 1 1.0UF 20% 2 6.3V X5R 0201-1 1 CB115 1.0UF 20% 2 6.3V X5R 0201-1 1 CB116 1.0UF 20% 2 6.3V X5R 0201-1 1210 1 CB150 47UF PP0V9_TBT_T_LVR 20% 2 6.3V CER-X5R 0603 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V 1 CB151 47UF 20% 2 6.3V CER-X5R 0603 1 CB152 INTERNAL SWITCHING VR OUTPUT 47UF 20% 6.3V 2 CER-X5R 0603 SOURCED BY INTERNAL SWITCH CB192 CB193 1 1.0UF 1 1.0UF 20% 6.3V 2 X5R 0201-1 20% 6.3V 2 X5R 0201-1 CB154 10UF 1 CB155 1 10UF 20% 6.3V 2 CERM-X5R 0402-4 C 20% 6.3V 2 CERM-X5R 0402-4 2x 10uF outside BGA area ISOLATE GND OF SVR_IND CAPS AND GND OF VCC3P3_SVR CAPS FROM SYSTEM GND IN LAYOUT (SEE INTEL LAYOUT GUIDELINES) Add XW or alias on support page XW P0V9_TBT_T_SVR_AGND 103 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=0V XWB100 SM 1 2 TBTTHMSNS_T_D1_N OUT B 54 PLACE_NEAR=UB000.AC22:2MM NO_XNET_CONNECTION=1 SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015 PAGE TITLE USB-C HIGH SPEED 2 DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=TBT 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 111 OF 145 SHEET 102 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 1 SIZE D A 8 7 6 5 4 USBC 5V EN PD TMU CLKs 108 TBT_X_TMU_CLK_IN 101 RB225 5% 1/20W TBT_T_TMU_CLK_OUT MAKE_BASE=TRUE TBT_T_TMU_CLK_OUT 15 1 201 MF TBT_X_TMU_CLK_IN RB226 100K 2 PLACE_NEAR=UB000.V2:5mm 1 TP_UPC_TA_SWD_DATA 104 27 2 1/20W 201 DP_T_SRC_HPD 105 101 TP_UPC_TB_SWD_CLK 101 NC_DP_T_SRC_AUX_P NC_DP_T_SRC_AUX_N ACE Debug Support 103 104 114 101 NONE NONE NONE 402 2 MAKE_BASE=TRUE 101 TP_UPC_TA_DBG_UART_RX TP_UPC_TB_DBG_UART_TX OMIT 104 114 105 114 NOSTUFF NONE NONE NONE 402 2 6AMP-32V-0.0095OHM 1 2 PP20V_USBC_TA_VBUS_F TP_UPC_TB_DBG_UART_RX 104 105 USBC_TB_CC1 104 USBC_TA_CC2 USBC_TA_CC2 RB268 DP_T_SNK0_DDC_DATA MAKE_BASE=TRUE 5% 1/20W 1 201 MF RB269 DP_T_SNK1_DDC_CLK MAKE_BASE=TRUE 5% 1/20W 1 201 MF RB270 DP_T_SNK1_DDC_DATA MAKE_BASE=TRUE 5% 1/20W 1 201 MF 100K 100K 1 CB211 0.1UF 740S0135 10% 2 35V CER-X5R 0201 6AMP-32V-0.0095OHM 1 2 PP20V_USBC_TB_VBUS_F 1 CB212 0.1UF 10% 2 35V CER-X5R 0201 1 CB213 0.1UF 10% 2 35V CER-X5R 0201 1 2 2 105 104 UPC_TA_DBG4 105 UPC_TB_DBG3 105 UPC_TB_DBG4 104 UPC_TA_DBG1 5% 1/20W MF RB261 5% 1/20W MF 1 201 MF 1 201 MF 1 201 RB262 5% 1/20W RB263 5% 1/20W RB264 5% UPC_TA_DBG2 1/20W 104 UPC_TA_HPD_RX 105 UPC_TB_HPD_RX MF RB265 5% 1/20W MF RB233 5% 1/20W 1/20W 1 201 1 201 100K 2 100K 2 100K 2 I2C_UPC_T_SDA2 105 I2C_UPC_T_SDA2 103 I2C_UPC_T_SDA2 MF MF 1 201 104 I2C_UPC_T_SCL2 105 I2C_UPC_T_SCL2 103 I2C_UPC_T_SCL2 106 RB207 TBT_T_XTAL25M_OUT NOSTUFF RB206 101 OUT 5% 1/20W MF 201 1 201 MF 4 1M to/from Ridge 113 1 5% 1/20W 2 2 YB200 25MHZ-25PPM-20PF-50OHM TBT_T_XTAL25M_IN 1 1 5% 25V C0G 0201 I2C_TBT_T_SCL I2C_TBT_T_SDA I2C_TBT_TB_INT_L 1 RB290 AR/ACE SPI BUS SERIES R'S 101 B ROM RB280 RB281 RB282 RB283 RB284 RB285 RB286 RB287 TBT_T_SPI_CLK 101 TBT_T_SPI_CS_L 101 TBT_T_SPI_MOSI 101 TBT_T_SPI_MISO 113 113 113 111 111 111 PCIE_TBT_T_R2D_C_P<0> IN 0201 X5R 6.3V GND_VOID=TRUE PCIE_TBT_T_R2D_C_N<0> IN 0201 X5R 6.3V GND_VOID=TRUE PCIE_TBT_T_R2D_C_P<1> IN 0201 X5R 6.3V GND_VOID=TRUE PCIE_TBT_T_R2D_C_N<1> IN 0201 X5R 6.3V GND_VOID=TRUE A 113 113 113 113 111 111 111 111 IN PCIE_TBT_T_R2D_C_P<2> IN PCIE_TBT_T_R2D_C_N<2> 0201 X5R 6.3V GND_VOID=TRUE 0201 X5R 6.3V GND_VOID=TRUE PCIE_TBT_T_R2D_C_P<3> IN 0201 X5R 6.3V GND_VOID=TRUE PCIE_TBT_T_R2D_C_N<3> IN 0201 X5R 6.3V 2 5% 1 15 1 15 1 15 1 15 1 15 1 1 1 15 15 15 2 5% 2 5% 2 5% 2 TBT_T_SPI_CLK_DBG 1/20W MF MF 1 100K 2 103 I2C_TBT_TB_INT_L I2C_UPC_T_SCL2 I2C_UPC_T_SDA2 SMC_USBC_INT_L TBT_T_SPI_CLK_DBG UPC_TA_UART_TX 101 103 103 2 103 46 29 100K 2 100K 2 105 104 MF IN 5% MF 104 201 IN 201 104 201 IN 104 UPC_TA_SPI_MISO 104 MF 5% 1/20W MF 201 OUT 5% 1/20W MF 201 IN 5% 1/20W UPC_T_SPI_CS_L MF 201 IN 29 101 UPC_T_SPI_MOSI 201 IN 29 101 201 OUT 2 2 2 5% 2 5% UPC_T_SPI_CLK 1/20W MF MF 2 20% 1 2 20% 1 2 20% 1 2 20% CB241 PCIE_TBT_T_R2D_N<0> 0.22UF CB242 PCIE_TBT_T_R2D_P<1> 0.22UF 1 CB243 PCIE_TBT_T_R2D_N<1> 0.22UF 1 2 20% 1 2 20% PCIE_TBT_T_R2D_P<0> 0.22UF 2 20% 2 20% CB240 CB244 PCIE_TBT_T_R2D_P<2> 0.22UF CB245 PCIE_TBT_T_R2D_N<2> 0.22UF 1 CB246 PCIE_TBT_T_R2D_P<3> 0.22UF 1 CB247 0.22UF PCIE_TBT_T_R2D_N<3> OUT OUT OUT OUT OUT OUT OUT OUT 101 101 101 101 101 101 113 101 101 USB2_UPC_TB_P 2 WWW.AliSaler.Com 7 1 2 3 4 5 6 7 8 9 10 11 12 15 16 I2C_TBT_TA_INT_L I2C_TBT_T_SDA I2C_TBT_T_SCL TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN UPC_TA_UART_RX 1/20W 0201 RB255 0 1 1/20W 0201 101 5% MF 1 105 NOSTUFF 101 105 104 104 29 101 116 101 101 101 PP3V3_UPC_TA_LDO 1 113 113 113 113 113 113 113 113 101 113 101 113 101 113 101 113 101 113 101 101 113 101 113 IN 104 5% MF USB_UPC_PCH_TB_N 14 USB_UPC_PCH_TA_P RB257 0 USB2_UPC_TA_N 1 5% MF PP20V_USBC_TA_VBUS 105 103 PP20V_USBC_TB_VBUS 105 PP3V3_UPC_TB_LDO 104 PP5V_S4_T_USBC 105 PP5V_S4_T_USBC 108 PP5V_S4_T_USBC IN IN IN 0201 X5R 0201 X5R 1 6.3V 2 20% PCIE_TBT_T_D2R_C_P<1> 0201 X5R PCIE_TBT_T_D2R_C_N<1> 0201 X5R PCIE_TBT_T_D2R_C_P<2> IN PCIE_TBT_T_D2R_C_N<2> IN 1 6.3V 2 20% PCIE_TBT_T_D2R_C_N<0> IN IN 6.3V 0201 0201 X5R X5R 6.3V X5R X5R 1 1 6.3V 6.3V 2 20% CB253 0.22UF 2 20% 6.3V CB252 0.22UF 6.3V 2 20% CB251 0.22UF 1 PCIE_TBT_T_D2R_C_N<3> 0201 0.22UF 2 20% PCIE_TBT_T_D2R_C_P<3> 0201 2 20% CB250 CB254 0.22UF CB255 0.22UF 1 CB256 0.22UF 1 CB257 0.22UF PCIE_TBT_T_D2R_P<0> OUT 111 MAKE_BASE=TRUE PP20V_USBC_TA_VBUS 106 MAKE_BASE=TRUE PP20V_USBC_TB_VBUS 106 MAKE_BASE=TRUE MAKE_BASE=TRUE TBT_T_USB_PWR_EN PCIE_TBT_T_D2R_N<0> MAKE_BASE=TRUE PP3V3_TBT_T_S0 PM_BATLOW_L UPC_T_5V_EN 105 UPC_T_5V_EN SMC_PME_S4_DARK_L UPC_T_5V_EN IN SMC_USBC_INT_L OUT 111 6 SMC_USBC_INT_L MAKE_BASE=TRUE SSD_DEBUG_I2C_CLK_CONN 105 SSD_DEBUG_I2C_DAT_CONN SSD_DEBUG_I2C_DAT_CONN 1 1 OUT 111 NC_UPC_TB_I2C_ADDR GND ALIASES 113 105 OUT 111 111 OUT 111 113 GND_VOID=TRUE PCIE_TBT_T_D2R_N<2> 113 GND_VOID=TRUE PCIE_TBT_T_D2R_P<3> OUT 111 113 GND_VOID=TRUE PCIE_TBT_T_D2R_N<3> OUT 111 5 1/20W 0201 MAKE_BASE=TRUE JTAG_TBT_T_TMS 15 29 101 MAKE_BASE=TRUE PP3V3_S4 29 110 114 MAKE_BASE=TRUE TP_USBC_TB_RESET_L IN 14 TP_USBC_TB_RESET_L MAKE_BASE=TRUE TBT_POC_RESET TBT_POC_RESET OUT 14 15 29 MAKE_BASE=TRUE GND 105 GND GND 104 105 GND 29 GND 29 GND 105 GND 105 GND 105 GND 105 GND 104 GND 105 GND 104 OUT 104 XDP_PCH_OBSDATA_C3 113 GND_VOID=TRUE PCIE_TBT_T_D2R_P<2> PP3V3_S4 105 GND_VOID=TRUE PCIE_TBT_T_D2R_N<1> 105 14 1/20W 0201 2 JTAG_TBT_T_TMS PP3V3_S4 80 86 114 101 XDP_PCH_OBSDATA_C2 2 RB259 0 UPC_TB_FAULT_L 104 BI TBT_T_CIO_PLUG_EVENT_L 5% MF IN 80 86 114 MAKE_BASE=TRUE RB258 0 UPC_TA_FAULT_L IN OUT MAKE_BASE=TRUE TBT_T_CIO_PLUG_EVENT_L 104 29 46 103 OUT B SSD_DEBUG_I2C_CLK_CONN 113 GND_VOID=TRUE PCIE_TBT_T_D2R_P<1> IN 15 29 MAKE_BASE=TRUE 105 15 108 MAKE_BASE=TRUE 105 29 103 JTAG_ISP_TDO SMC_USBC_INT_L MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V 29 46 47 48 MAKE_BASE=TRUE JTAG_ISP_TDO 29 27 12 29 46 MAKE_BASE=TRUE IN 105 NO TEST 105 12 103 MAKE_BASE=TRUE 104 MAKE_BASE=TRUE PP5V_S4_T_USBC GND_VOID=TRUE 12 103 MAKE_BASE=TRUE 104 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V 113 14 1/20W 0201 104 PP3V3_UPC_TB_LDO PP3V3_TBT_T_S0 C TBT_T_CIO_PWR_EN 5% MF 1 105 14 USB_UPC_PCH_TA_N 2 SMC_PME_S4_DARK_L 105 2 20% 104 1/20W 0201 SMC_PME_S4_DARK_L 31 30 29 D2R PCIE_TBT_T_D2R_C_P<0> 12 103 14 2 PM_BATLOW_L 101 103 102 103 12 103 USB_UPC_PCH_TB_P RB256 0 USB2_UPC_TA_P TBT_T_USB_PWR_EN 101 29 27 MAKE_BASE=TRUE PP3V3_UPC_TA_LDO PP3V3_UPC_TA_LDO 104 110 101 1/20W 0201 TBT_T_CIO_PWR_EN 101 NOSTUFF POWER ALIASES 105 AR 103 NOSTUFF 105 105 2 5% MF USB2_UPC_TA_N 105 29 101 103 101 1/20W 0201 RB253 0 MAKE_BASE=TRUE 101 02 1 USB2_UPC_TB_N 104 NOSTUFF USB_UPC_TA_N 2 5% MF Ace 101 SIGNAL ALIASES RB252 USB2_UPC_TB_N 113 105 104 103 31 30 105 104 103 31 30 SYNC_MASTER=J80_AGOTETI_MLB_BAFFIN 4 SYNC_DATE=12/07/2015 PAGE TITLE USB-C Support DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 112 OF 145 SHEET 103 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=TBT 8 14 USB2_UPC_TB_P USB_UPC_TA_P 2 5% MF 116 UPC_T_SPI_MISO 1/20W 1/20W 0201 RB354 0 104 UPC_TA_SPI_MOSI 1/20W 13 MAKE_BASE=TRUE USB_UPC_TB_N 2 104 104 UPC_TA_SPI_CS_L 1/20W JB200 103 201 UPC_TA_SPI_CLK 1/20W 1/20W 0201 RB251 0 104 GND_VOID=TRUE GND_VOID=TRUE 111 100 Ridge PCIE Caps R2D 113 1 49 M-ST-SM 2 105 USB_UPC_TB_P 2 5% MF 101 49 D USB2_UPC_TA_P RB250 0 U3200 (Write: 0x7E Read: 0x7F) 2 SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SCL 2 201 MAKE_BASE=TRUE Sec ACE 20PF MF 505070-1220 104 1 CB203 2.00X1.60-SM 1/20W 5% 33 Place on bottom NO_XNET_CONNECTION=1 I2C_TBT_T_SCL I2C_TBT_T_SDA I2C_TBT_TA_INT_L 49 PLACE_NEAR=U5000:5mm MAKE_BASE=TRUE U3100 (Write: 0x70 Read: 0x71) I2C_TBT_T_SCL I2C_TBT_T_SDA I2C_TBT_TA_INT_L I2C_TBT_TB_INT_L MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 49 ACE DEBUG CONN XWB200 SM P0V9_TBT_T_SVR_AGND Pri ACE Alpine Ridge U2800 (MASTER) 5% 25V C0G 0201 CRITICAL 2 IN 20PF TBT_T_XTAL25M_OUT_R 2 3 101 0113 1 113 1 TBT SMBUS_SMC_4_G3H_SDA SMBUS_SMC_4_G3H_SDA 2 201 MAKE_BASE=TRUE RIDGE 0.9V SVR XW 10% 2 35V CER-X5R 0201 TBT to ACE CB202 MF RB242 1 106 105 25MHz xtal 1/20W USBC_DBG 100K 100K 5% 33 MAKE_BASE=TRUE 103 1 201 RB234 5% 1 201 104 RB241 1 105 0.1UF C RB260 UPC_TA_DBG3 2 CB214 102 104 USBC_TB_CC2 2 29 30 31 104 105 106 MAKE_BASE=TRUE 104 PPDCIN_G3H 105 ACE PDs 100K 100K 106 MAKE_BASE=TRUE USBC_TB_CC2 1 201 MF 1/20W 104 MAKE_BASE=TRUE 104 114 FB201 PP20V_USBC_TB_VBUS USBC_TB_CC1 ACE FET DCIN Bypass Caps CRITICAL 103 5% DP_T_SNK1_DDC_DATA PLACE_NEAR=QB400:5MM 105 105 RB288 1 FB200 0603 MAKE_BASE=TRUE DP_T_SNK1_DDC_CLK NOSTUFF 0603 PP20V_USBC_TA_VBUS DP_T_SNK0_DDC_CLK DP_T_SNK0_DDC_DATA RB289 1 CRITICAL 104 101 TP_UPC_TA_DBG_UART_TX OMIT USBC_TA_CC1 105 PLACE_NEAR=U5000:5mm MAKE_BASE=TRUE USBC_TA_CC1 RB267 DP_T_SNK0_DDC_CLK 2 PLACE_NEAR=QB300:5MM FUSES FOR UPC MF 1 I2C SERIES R'S 104 Ridge PDs 101 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NC_DP_T_SRC_ML_P<3..0> NC_DP_T_SRC_ML_N<3..0> NC_DP_T_SRC_AUX_P NC_DP_T_SRC_AUX_N 101 1M 1 IF DP SRC NOT USED 101 TPB201 1 TP TPB202 TP-P5 1 TP TPB203 TP-P5 1 TP TPB204 TP-P5 TP_UPC_TB_SWD_DATA 5% 1/20W MF 201 NC_DP_T_SRC_ML_P<3..0> NC_DP_T_SRC_ML_N<3..0> 1/20W 2 TP-P5 RB240 101 5% 1 201 100K 1 TP TP_UPC_TA_SWD_CLK 104 105 DP SRC OPTIONS RB232 UPC_T_5V_EN 103 2 ACE A/B RPD STRAPPING MAKE_BASE=TRUE 5% MF D 3 1 SIZE D A 8 7 6 5 4 3 2 1 PRIMARY ACE USB-C PORT CONTROLLER (UPC) QB300 FDPC4044 D D FUSE 103 PPDCIN_G3H PP20V_USBC_TA_VBUS CB301 TP_QB300_DRAIN UPC_TA_GATE2 10% 2 35V X5R 0402 109 PP5V_S4_T_USBC 5% 2 1/20W 1/20W 104 I2C_UPC_TA_DBG_CTL_SDA 104 MF RB308 5% I2C_UPC_TA_DBG_CTL_SCL MF 201 201 TESTPOINTS MUST BE PRESENT FOR GPIO0, GPIO1 (EVEN IN PRODUCTION) USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR 107 OUT 105 103 103 114 103 114 101 105 103 101 BI 101 OUT USE GPIO3 FOR POWER_GATE_EN ON BANSURI DESIGNS BI 103 105 103 103 OUT 31 30 29 OUT 103 OUT 103 IN 0 1 1M 2 5% RB305 1/20W MF UPC_TA_UART_RX 103 104 RB303 1 104 15K 104 0.1% 1/20W TF-LF 0201 2 105 201 NEED 0.1% TO SMC B REAR PORT: CONNECT UPC SPI TO ROM FRONT PORT: GROUND UPC SPI 103 BI 103 BI 103 OUT 103 BI 103 BI 103 OUT 103 OUT 103 OUT 103 IN 103 OUT 103 103 105 LB300 105 90-OHM-0.1A EXCX4CE SYM_VER-1 BI USB2_UPC_TA_P 1 USB2_UPC_TA_N 103 4 PLACE_NEAR=UB300.L5:5mm 2 PP3V3_S4 1 RB310 100K NO_XNET_CONNECTION=1 113 101 BI 113 101 BI 5% 1/20W MF 2 201 OUT 101 IN 101 OUT I2C_UPC_TA_DBG_CTL_SCL I2C_UPC_TA_DBG_CTL_SDA A5 I2C_SDA2 B5 I2C_SCL2 B6 I2C_IRQ2* UPC_TA_SPI_CLK UPC_TA_SPI_MOSI UPC_TA_SPI_MISO UPC_TA_SPI_CS_L A3 B4 A4 B3 TP_UPC_TA_SWD_DATA TP_UPC_TA_SWD_CLK F4 SWD_DATA G4 SWD_CLK UPC_TA_UART_RX UPC_TA_UART_TX F2 UART_RX E2 UART_TX TBT_TA_LSTX TBT_TA_LSRX L4 LSX_R2P K4 LSX_P2R BI 103 BI 103 BI 103 BI UPC_TA_DBG1 UPC_TA_DBG2 UPC_TA_DBG3 UPC_TA_DBG4 L2 K2 L3 K3 LDO_1V8A K1 LDO_1V8D A2 LDO_3V3 G1 VOUT_3V3 H2 VDDIO B1 H11 J10 J11 K11 VBUS VBUS VBUS VBUS LDO_BMC E1 1 CB309 0.47UF 10% 2 6.3V CERM-X5R 0201 HV_GATE1 B9 HV_GATE2 A9 C_CC1 L9 C_CC2 L10 USBC_TA_CC1 USBC_TA_CC2 RPD_G1 K9 RPD_G2 K10 USBC_TA_CC1 USBC_TA_CC2 BI 103 BI 103 1 10% 16V 2 CER-X7R 0201 USBC_TA_USB_TOP_P USBC_TA_USB_TOP_N BI 106 BI 106 C_USB_BP K7 C_USB_BN L7 USBC_TA_USB_BOT_P USBC_TA_USB_BOT_N BI 106 BI 106 BI 106 115 BI 106 115 NC L11 USBC_TA_SBU1 USBC_TA_SBU2 CB314 220PF C_USB_TP K6 C_USB_TN L6 C_SBU1 K8 C_SBU2 L8 L5 USB_RP_P K5 USB_RP_N J1 AUX_P J2 AUX_N C UPC_TA_SS SENSEP B10 SENSEN A10 SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ DP_TA_AUXCH_P DP_TA_AUXCH_N 10% 2 6.3V CERM-X5R 0201 20% 2 4V X5R-CERM 0201 20% 2 6.3V CERM-X5R 0402-1 CB306 0.47UF 2.2UF 10UF 20% 2 6.3V X5R 0201-1 SS H7 E4 DEBUG_CTL1 D5 DEBUG_CTL2 I2C_UPC_T_SDA2 I2C_UPC_T_SCL2 SMC_USBC_INT_L 1.0UF CB308 1 BGA F1 I2C_ADDR G2 R_OSC D1 I2C_SDA1 D2 I2C_SCL1 C1 I2C_IRQ1* 1 CB304 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V CRITICAL OMIT_TABLE UB300 F10 BUSPOWERZ USB_UPC_TA_F_P USB_UPC_TA_F_N 103 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V CD3215A GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 I2C_TBT_T_SDA I2C_TBT_T_SCL I2C_TBT_TA_INT_L CB305 1 1 BI 103 106 BI 103 106 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 CB313 220PF 10% 2 16V CER-X7R 0201 B GROUND NC or GND to dissipate heat DEBUG1 DEBUG2 DEBUG3 DEBUG4 SYNC_MASTER=J80_MLB PAGE TITLE 1 NO_XNET_CONNECTION=1 103 103 3 PLACE_NEAR=UB300.K5:5mm PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO A 104 VOUT_3V3 FOR RIDGE, OR FLOAT IF UNUSED GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 103 BI B2 C2 D10 G11 C10 E10 G10 D7 H6 PRIMARY ONLY PRIMARY ONLY 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V A1 D6 E5 E6 E7 F5 G5 H4 H5 G8 H8 L1 B8 D8 E8 F6 F7 F8 G6 G7 103 TP_UPC_TA_DBG_UART_TX TP_UPC_TA_DBG_UART_RX TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN DP_TA_HPD UPC_TA_HPD_RX UPC_T_5V_EN SMC_PME_S4_DARK_L UPC_TA_FAULT_L UPC_TA_I2C_ADDR UPC_TA_R_OSC CRITICAL 5% 1/20W MF 201 2 E11 MRESET F11 RESET* GND GND I2C_ADDR PRIMARY ONLY RB302 1 TBT_POC_RESET USBC_T_RESET_L_R HV FET/SENSE RB309 IN TYPE-C 1M 1 2 103 DIGITAL CORE I/O AND CONTROL 1M 1 105 107 PORT MUX 103 VIN_3V3 H1 PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES PP_CABLE H10 20% 2 6.3V CERM-X5R 0402-1 A6 A7 A8 B7 CB300 10UF GND P3V3_TBT_T_SX_EN_R PP1V1_UPC_TA_LDO_BMC 1 C 103 PP1V8_UPC_TA_LDOD PP_HV PP_HV PP_HV PP_HV 103 PP3V3_UPC_TA_LDO PP1V8_UPC_TA_LDOA GND 31 30 29 CAP FOR PP_5V0 ON VR PAGE PP3V3_G3H A11 B11 C11 D11 103 105 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V PP3V3_UPC_TA_LDO PP_5V0 PP_5V0 PP_5V0 PP_5V0 105 29 30 31 103 MAX 100uF TOTAL ON RAIL UPC_TA_GATE1 1UF 103 S1 NC MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=20V 1 8 1 G1 G2 4 3 2 S2 PP20V_USBC_TA_VBUS_F 103 Add on support page 5 PWR-CLIP-33 RB311 SYNC_DATE=11/06/2015 USB-C PORT CONTROLLER A DRAWING NUMBER 100K 5% 1/20W MF 2 201 GND Apple Inc. 103 051-00647 REVISION R PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION 10.0.0 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 113 OF 145 II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 104 OF 121 IV ALL RIGHTS RESERVED 2 1 SIZE D A 8 7 6 5 4 3 2 1 SECONDARY ACE USB-C PORT CONTROLLER (UPC) QB400 FDPC4044 PWR-CLIP-33 FUSE 103 Add on support page 103 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=20V 1 PPDCIN_G3H CB401 1 1M 2 RB409 5% 2 1/20W RB408 5% 1/20W I2C_UPC_TB_DBG_CTL_SCL MF 103 105 201 103 CRITICAL RB403 1 105 15K 1 1M 2 RB405 5% 1/20W 105 0.1% 1/20W TF-LF 0201 2 MF 201 UPC_TA_UART_TX 103 104 NEED 0.1% 105 GND B IN I2C_UPC_TB_DBG_CTL_SCL I2C_UPC_TB_DBG_CTL_SDA E4 DEBUG_CTL1 D5 DEBUG_CTL2 103 BI OUT 103 BI 103 BI 103 REAR PORT: CONNECT UPC SPI TO ROM FRONT PORT: GROUND UPC SPI OUT 103 OUT 103 OUT 103 IN 103 OUT 103 103 105 LB400 90-OHM-0.1A 104 104 103 103 OUT 101 IN 101 OUT EXCX4CE SYM_VER-1 USB2_UPC_TB_P BI USB2_UPC_TB_N 2 103 3 PLACE_NEAR=UB400.K5:5mm PP3V3_S4 PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO NO_XNET_CONNECTION=1 113 101 BI 113 101 BI A 1 RB410 100K 5% 1/20W MF 2 201 103 BI 103 BI 103 BI 103 BI TP_UPC_TB_SWD_DATA TP_UPC_TB_SWD_CLK F4 SWD_DATA G4 SWD_CLK UPC_TA_UART_TX UPC_TA_UART_RX F2 UART_RX E2 UART_TX L4 LSX_R2P K4 LSX_P2R USB_UPC_TB_F_P USB_UPC_TB_F_N L5 USB_RP_P K5 USB_RP_N DP_TB_AUXCH_P DP_TB_AUXCH_N J1 AUX_P J2 AUX_N SSD_DEBUG_I2C_CLK_CONN SSD_DEBUG_I2C_DAT_CONN UPC_TB_DBG3 UPC_TB_DBG4 L2 K2 L3 K3 LDO_BMC E1 LDO_1V8A K1 LDO_1V8D A2 LDO_3V3 G1 VOUT_3V3 H2 VDDIO B1 VIN_3V3 H1 SENSEP B10 SENSEN A10 1 CB409 0.47UF 10% 2 6.3V CERM-X5R 0201 HV_GATE1 B9 HV_GATE2 A9 C_CC1 L9 C_CC2 L10 USBC_TB_CC1 USBC_TB_CC2 RPD_G1 K9 RPD_G2 K10 USBC_TB_CC1 USBC_TB_CC2 BI 103 BI 103 C_USB_TP K6 C_USB_TN L6 USBC_TB_USB_TOP_P USBC_TB_USB_TOP_N BI 106 BI 106 C_USB_BP K7 C_USB_BN L7 USBC_TB_USB_BOT_P USBC_TB_USB_BOT_N BI 106 BI 106 BI 106 115 BI 106 115 C_SBU1 K8 C_SBU2 L8 SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ TBT_TB_LSTX TBT_TB_LSRX UPC_TB_SS NC L11 USBC_TB_SBU1 USBC_TB_SBU2 1 CB414 220PF 10% 2 16V CER-X7R 0201 1 103 106 BI 103 106 CB413 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 220PF 10% 2 16V CER-X7R 0201 B GROUND NC or GND to dissipate heat DEBUG1 DEBUG2 DEBUG3 DEBUG4 RB411 1 SYNC_MASTER=J80_MLB 100K NO_XNET_CONNECTION=1 BI GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 103 BI 4 PLACE_NEAR=UB400.L5:5mm A3 B4 A4 B3 20% 2 4V X5R-CERM 0201 20% 2 6.3V CERM-X5R 0402-1 C SS H7 A5 I2C_SDA2 B5 I2C_SCL2 B6 I2C_IRQ2* GND GND GND GND 2.2UF 10UF 20% 2 6.3V X5R 0201-1 CB404 10% 2 6.3V CERM-X5R 0201 BGA D1 I2C_SDA1 D2 I2C_SCL1 C1 I2C_IRQ1* I2C_UPC_T_SDA2 I2C_UPC_T_SCL2 SMC_USBC_INT_L CB408 0.47UF A1 D6 E5 E6 E7 F5 G5 H4 H5 G8 H8 L1 B8 D8 E8 F6 F7 F8 G6 G7 103 1 I2C_TBT_T_SDA I2C_TBT_T_SCL I2C_TBT_TB_INT_L 1 1.0UF 1 CB406 CD3215A F10 BUSPOWERZ F1 I2C_ADDR G2 R_OSC BI UB400 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 NC_UPC_TB_I2C_ADDR UPC_TB_R_OSC 103 103 TO SMC B2 C2 D10 G11 C10 E10 G10 D7 H6 103 105 201 I2C_UPC_TB_DBG_CTL_SDA MF 114 CB405 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V 1 CRITICAL OMIT_TABLE HV FET/SENSE 103 1M OUT E11 MRESET F11 RESET* TYPE-C 1 103 TBT_POC_RESET TP_USBC_TB_RESET_L TP_UPC_TB_DBG_UART_TX TP_UPC_TB_DBG_UART_RX 103 114 TBT_T_CIO_PWR_EN 104 103 101 BI TBT_T_USB_PWR_EN 104 103 101 BI DP_TB_HPD 101 OUT UPC_TB_HPD_RX 103 UPC_T_5V_EN 103 OUT SMC_PME_S4_DARK_L 104 103 31 30 29 OUT UPC_TB_FAULT_L 103 OUT PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES GND IN DIGITAL CORE I/O AND CONTROL TESTPOINTS MUST BE PRESENT FOR GPIO0, GPIO1 (EVEN IN PRODUCTION) 103 PP_5V0 PP_5V0 PP_5V0 PP_5V0 20% 2 6.3V CERM-X5R 0402-1 H11 J10 J11 K11 10UF VBUS VBUS VBUS VBUS CB400 1 VOUT_3V3 FOR RIDGE, OR FLOAT IF UNUSED MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V PORT MUX 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V PP1V1_UPC_TB_LDO_BMC PP_CABLE H10 CAP FOR PP_5V0 ON VR PAGE 104 103 PP1V8_UPC_TB_LDOD PP5V_S4_T_USBC 103 C PP3V3_UPC_TB_LDO GND A6 A7 A8 B7 31 30 29 PP_HV PP_HV PP_HV PP_HV 103 104 P3V3_TBT_T_SX_EN_R 107 PP1V8_UPC_TB_LDOA A11 B11 C11 D11 104 PP3V3_G3H 29 30 31 103 MAX 100uF TOTAL ON RAIL UPC_TB_GATE1 TP_QB400_DRAIN UPC_TB_GATE2 10% 2 35V X5R 0402 109 S1 NC 1UF 103 8 PP20V_USBC_TB_VBUS_F PP20V_USBC_TB_VBUS PP3V3_UPC_TB_LDO 1 G1 G2 4 3 2 S2 D 5 D PAGE TITLE 5% 1/20W MF 201 2 GND SYNC_DATE=11/06/2015 USB-C PORT CONTROLLER B DRAWING NUMBER 051-00647 103 Apple Inc. PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 114 OF 145 SHEET 105 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 1 SIZE D A 6 VOLTAGE=20V DB502 10% 2 25V X5R-CERM 0201 1 0.01UF A CB551 CB552 1 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 0.01UF 10% 2 25V X5R-CERM 0201 DB525 CRITICAL CB506 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 CB507 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 CRITICAL CB503 1 0.01UF CB512 0.01UF 10% 2 25V X5R-CERM 0201 10% 2 25V X5R-CERM 0201 BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM 1 CB502 CRITICAL 1 CB508 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 CRITICAL CB509 1 0.01UF CB505 0.01UF 10% 2 25V X5R-CERM 0201 10% 2 25V X5R-CERM 0201 BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM 61 63 65 67 69 71 73 75 77 79 81 83 85 GND GND_VOID=TRUE CB593 0.22UF 6.3V X5R-CERM 0201 1 1 GND_VOID=TRUE CB570 USBC_TA_R2D_P<1> 114 GND_VOID=TRUE GND_VOID=TRUE 60 62 64 66 68 70 72 74 76 78 80 82 84 86 2 1 2 2 1 1 GND_VOID=TRUE GND_VOID=TRUE PP20V_USBC_TA_VBUS_CONN PART NUMBER 138S0683 QTY 2 2 1 1 106 114 115 TBT_R2D1 101 IN 113 BI 105 BI 105 USB2 TOP OUT 101 113 OUT 101 113 105 BI TBT_D2R1 115 SBU1 1 2 10% CB571 1 2 10% 0.22UF 6.3V USBC_TA_SBU2 X5R-CERM 0201 GND_VOID=TRUE 0.22UF 6.3V X5R-CERM 0201 USBC_TA_R2D_C_P<1> USBC_TA_R2D_C_N<1> USBC_TA_USB_TOP_P USBC_TA_USB_TOP_N GND_VOID=TRUE GND_VOID=TRUE 2 2 1 1 104 BI 115 IN 101 113 IN 101 113 SBU2 TBT_R2D0 BI 104 BI 104 USB2 BOT OUT 101 113 OUT 101 113 103 BI 104 TBT_D2R0 CC1 2 B 1 116 DESCRIPTION 2 113 C USBC_TA_D2R_P<1> USBC_TA_D2R_N<1> USBC_TA_CC1 OUT CC2 1 GND_VOID=TRUE GND_VOID=TRUE TP_JB500_P56 USBC_TB_R2D_C_P<2> USBC_TB_USB_TOP_P USBC_TB_USB_TOP_N USBC_TB_D2R_N<2> USBC_TB_D2R_P<2> USBC_TB_SBU1 101 IN 105 2 GND_VOID=TRUE GND_VOID=TRUE USBC_TA_R2D_N<1> 5.5V-6.2PF 2 0201-THICKSTNCL 2 DZB553 1 0201 GND_VOID=TRUE ESD8011 1 10% USBC_TB_R2D_C_N<2> X5R-CERM X3DFN2-THICKSTNCL 2 2 6.3V DB557 2 1 0.22UF 103 BI GND_VOID=TRUE GND_VOID=TRUE ESD8011 X3DFN2-THICKSTNCL ESD8011 DB558 X3DFN2-THICKSTNCL ESD8011 10% 5.5V-6.2PF 10% 25V 2 X5R-CERM 0201 CB501 PWR 2 0201-THICKSTNCL 0.01UF CRITICAL 1 59 GND_VOID=TRUE GND_VOID=TRUE 1 ESD8011 CB500 BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM CB592 GND_VOID=TRUE DB522 BYPASS=JB500.59::2MM 1 DB556 5.5V-6.2PF DZB552 0201-THICKSTNCL ESD8011 DB550 ESD8011 X3DFN2-THICKSTNCL DB551 ESD8011 X3DFN2-THICKSTNCL GND_VOID=TRUE GND_VOID=TRUE PLACE VBUS CAP NEAR EACH VBUS PIN PP20V_USBC_TA_VBUS_CONN 0201 X3DFN2-THICKSTNCL A 1 10% GND_VOID=TRUE ESD8011 DB501 1 GND_VOID=TRUE GND_VOID=TRUE D 2 25V X5R-CERM DZB502 A 10% 25V 2 X5R 402 2 BYPASS=JB500.58::2MM BYPASS=JB500.58::2MM BYPASS=JB500.58::2MM DB529 NSR20F40NX_G ESDA25P35-1U1M 1UF 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=20V 1 1610 1 1 CRITICAL K OMIT_TABLE CB504 1 1 2 1 X3DFN2-THICKSTNCL DB500 DSN2 K 2 1 2 0201 CB559 GND_VOID=TRUE GND_VOID=TRUE ESD8011 SM 2 GND_VOID=TRUE GND_VOID=TRUE 1 DB504 B XWB500 PP20V_USBC_TA_VBUS CRITICAL 1 X3DFN2-THICKSTNCL 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=20V 103 2 0201 GND_VOID=TRUE GND_VOID=TRUE ESD8011 2 DB526 X3DFN2-THICKSTNCL ESD8011 5.5V-6.2PF 1 DB527 2 0201-THICKSTNCL DZB501 GND_VOID=TRUE GND_VOID=TRUE X5R-CERM GND_VOID=TRUE GND_VOID=TRUE ESD8011 6.3V USBC_TA_R2D_N<2> 2 X3DFN2-THICKSTNCL 10% 0.22UF 2 DB520 2 0201 X3DFN2-THICKSTNCL 1 X5R-CERM 2 ESD8011 CB572 6.3V GND_VOID=TRUE USBC_TA_R2D_P<2> DB555 10% 0.22UF GND_VOID=TRUE GND_VOID=TRUE ESD8011 2 GND_VOID=TRUE USBC_TA_R2D_C_N<2> USBC_TA_D2R_P<2> USBC_TA_D2R_N<2> USBC_TA_CC2 OUT DB552 X3DFN2-THICKSTNCL CB573 GND_VOID=TRUE 1 GND_VOID=TRUE GND_VOID=TRUE X3DFN2-THICKSTNCL BI GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 10% 2 25V X5R-CERM 0.01UF 10% 2 25V X5R-CERM 0201 USBC_TB_R2D_P<2> 5.5V-6.2PF 103 GND_VOID=TRUE GND_VOID=TRUE 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 SIGNAL 58 0201-THICKSTNCL 104 1 PWR DB521 OUT 113 101 113 101 57 DZB551 IN 1 0.01UF USBC_TB_R2D_N<2> F-ST-SM 5.5V-6.2PF CC2 101 1 CB558 BYPASS=JB500.58::2MM 20759-056E-02 2 0.01UF 10% 2 25V X5R-CERM 0201 USBC_TB_CC2 0201-THICKSTNCL TBT_D2R1 113 1 2 CB555 114 DZB500 TBT_R2D1 1 2 ESD8011 101 1 2 OUT CB562 CRITICAL 1 JB500 X3DFN2-THICKSTNCL IN USBC_TA_R2D_C_P<2> 1 2 DB528 BI 1 2 ESD8011 BI 104 2 TP_JB500_P2 GND_VOID=TRUE GND_VOID=TRUE X3DFN2-THICKSTNCL 113 104 USBC_TA_USB_BOT_N USBC_TA_USB_BOT_P USBC_TA_SBU1 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE 2 USBC_TB_R2D_P<1> 0201 DB512 SBU1 BI X5R-CERM 5.5V-6.2PF C 115 104 6.3V 0201-THICKSTNCL USB2 BOT ESD8011 DB554 GND_VOID=TRUE 0.22UF DZB503 BI 10% X3DFN2-THICKSTNCL BI 105 USB2 BOT 2 CB557 CRITICAL 1 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 10% 2 25V X5R-CERM 0201 BYPASS=JB500.58::2MM CB553 BYPASS=JB500.58::2MM 0.01UF 10% 2 25V X5R-CERM 0201 USBC_TB_R2D_N<1> 0201 ESD8011 BI 105 OUT 1 DB553 105 X5R-CERM DB524 115 6.3V X3DFN2-THICKSTNCL 101 113 101 OUT 113 CB590 USBC_TB_R2D_C_P<1> USBC_TB_D2R_N<1> USBC_TB_D2R_P<1> USBC_TB_SBU2 USBC_TB_USB_BOT_N USBC_TB_USB_BOT_P 0.22UF GND_VOID=TRUE 5.5V-6.2PF IN GND_VOID=TRUE 0201-THICKSTNCL SBU2 101 10% ESD8011 TBT_D2R0 113 2 ESD8011 TBT_R2D0 1 X3DFN2-THICKSTNCL CB591 USBC_TB_R2D_C_N<1> IN GND_VOID=TRUE X3DFN2-THICKSTNCL GND_VOID=TRUE DZB550 101 BI X3DFN2-THICKSTNCL 113 103 ESD8011 105 DB549 CC1 CB556 0.01UF USBC_TB_CC1 CRITICAL 1 0.01UF 10% 2 25V X5R-CERM 0201 CRITICAL 1 1 0.01UF BYPASS=JB500.58::2MM D CRITICAL X3DFN2-THICKSTNCL 10% 25V 2 X5R 402 A 1 ESDA25P35-1U1M 1UF CB550 1610 BYPASS=JB500.58::2MM CRITICAL DB559 1 CRITICAL X3DFN2-THICKSTNCL NSR20F40NX_G CB554 BYPASS=JB500.58::2MM CRITICAL X3DFN2-THICKSTNCL DB570 DSN2 BYPASS=JB500.58::2MM K OMIT_TABLE K 1 PLACE VBUS CAP NEAR EACH VBUS PIN PP20V_USBC_TB_VBUS_CONN 1 ESD8011 CRITICAL 2 ESD8011 SM 2 3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 XWB550 PP20V_USBC_TB_VBUS 103 4 DB560 VOLTAGE=20V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 5 DB523 7 X3DFN2-THICKSTNCL 8 CAP,CER,X5R,1UF,10%,25V,0402 REFERENCE DES CRITICAL BOM OPTION CRITICAL CB504, CB554 NOSTUFF LAST CHANGE: Wed Apr 1 22:57:37 2015 A SYNC_MASTER=X362_MLB SYNC_DATE=03/30/2016 PAGE TITLE USB-C CONNECTOR A DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 115 OF 145 SHEET 106 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 1 SIZE D A 8 7 6 5 4 3 2 1 D D TBT T "POC" Power-up Reset NOSTUFF MAKE_BASE=TRUE P3V3_TBT_T_SX_EN_R 1 RB600 402 0 2 MF-LF 5% 1/16W CRITICAL UB600 SLG5AP1449V RB601 0 P3V3_TBT_T_SX_EN 2 5% 1/20W MF 201 1 RB605 100K STDFN 1 ON D 2 S 3 PP3V3_S5 110 116 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V C PP3V3_S5_TBT_T_SW GND PP3V3_S5_TBT_T_SW 102 PP3V3_S5_TBT_T_SW 101 5% 1/20W MF 2 201 UB601 1 RB602 100K 1% 1/20W MF 2 201 104 IN CRITICAL VCC UB601 TPS3895ADRY USON MAKE_BASE=TRUE USBC_T_RESET_L_R 1 6 IN 1 USBC_T_RESET_L_R 1 ENABLE TBTTPOCRST_SNS 3 SENSE SENSE_OUT 4 CT 5 GND RB603 24.9K Output Push-pull Delay 440us +/- 20us Vth 2.508V nominal USBC_T_RESET_L OUT 101 TBTTPOCRST_CT CB600 2 IN 105 P3V3_TBT_T_SX_EN_R P3V3_TBT_T_SX_EN_R 4 C 104 1 100PF 5% 25V 2 C0G 0201 1% 1/20W MF 2 201 NOSTUFF RB604 1 0 2 5% 1/20W MF 201 B B DESIGN: j130/dev_mlb_u LAST CHANGE: Wed Apr 1 22:57:37 2015 A SYNC_MASTER=X362_MLB SYNC_DATE=03/29/2016 PAGE TITLE USB-C CONNECTOR B DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE BOM_COST_GROUP=USB-C WWW.AliSaler.Com 8 7 6 5 4 3 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART . 116 OF 145 SHEET 107 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 1 SIZE D A 8 116 108 103 7 6 PP5V_S4_T_USBC 5 110 34 4 PP5V_S4 116 109 34 3 1 XWB702 SM 2 1 27.4K 1 RB731 2 0.1% 1/20W MF 2 0201 NO_XNET_CONNECTION=1 VCC 2.2UF 27.4K 0.1% 1/20W MF 0201 2 CB722 10% 10V X6S-CERM 0402 103 IN NO_XNET_CONNECTION=1 1 RB717 191K 1 CB717 22PF 0.1% 1/20W MF 2 0201 5% 2 50V C0G 0201 P5VUSBCT_SENSE_DIV 10 FB P5VUSBCT_SREF 7 NC RB718 RTN 13 FSEL P5VUSBCT_SET0 8 SET0 P5VUSBCT_SET1 9 SET1 6 VID0 NOSTUFF 95.3K 0.1% 1/20W MF 2 0201 RB713 5 1 BOOT 18 UGATE 17 PGOOD 4 P5VUSBCT_RTN_DIV 10% 16V X7R-CERM 0402 P5VUSBCT_SET_R D FDPC1012S LLP P5VUSBCT_DRVH_R MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE P5VUSBCT_LL MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUE DIDT=TRUE RB739 2 0 5% 1/20W MF 0201 CRITICAL V+ 8 V+ 9 1 RB730 CRITICAL MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE 2 3 4 1.5UH-20%-12.5A-0.017OHM HSG 1 2 PIMB062D-SM SW 1 1 CB726 10PF 5% 2 50V C0G 0201 1 RB704 10K 0.1% 1/20W MF 2 0201-1 1 RB702 10K 0.1% 1/20W MF 2 0201-1 11K P5VUSBCT_R 2 4 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 NO_XNET_CONNECTION=1 1% 1/2W MF 0306 P5VUSBCT_DRVL CB705 LSG 7 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE 116 1 CB706 1 1 2.2UF CB709 150UF 20% 25V X5R-CERM 2 0402-1 20% 2 6.3V TANT-POLY CASE-B1S-1 1 CB708 150UF 20% 2 6.3V TANT-POLY CASE-B1S-1 1 CB707 150UF 20% 2 6.3V TANT-POLY CASE-B1S-1 P5VUSBCT_N RB721 2.74K 2 108 P5VUSBCT_P VID1 GND 103 1 3 20% 25V X5R-CERM 2 0402-1 NO_XNET_CONNECTION=1 CB770 2200PF 2 1 10% 25V CER-X7R 0201 2 Vout = 5.23V Freq = 500 kHz Max OCP = 13.9A Nom OCP = 11.6A Min OCP = 9.37A 1 1% 1/20W MF 201 2 PGND 1% 1/20W MF 201 1 PP5V_S4_T_USBC 0.002 LB700 P5VUSBCT_DRVH 1 RB700 C 20% 2 25V X5R-CERM 0402-1 CRITICAL 0 5% 1/20W MF 201 2.2UF 20% 2 25V X5R-CERM 0402-1 20% 16V 2 TANT-POLY CASE-B3 CB701 2.2UF 3 1 14 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE LGATE 1 11 OCSET 2.2UF 33UF CB716 P5VUSBCT_VBST PHASE 16 SREF P5VUSBCT_OCSET 1 2 CRITICAL 12 VO 0.1UF 10% 16V X5R-CERM 0201 UTQFN P5VUSBCT_VO P5VUSBCT_FSEL CB723 PVCC ISL95870AH 15 EN 1 0.1UF 2.2 5% 1/20W MF 201 2 CB700 QB701 UB700 UPC_T_5V_EN 20% 10V X5R-CERM 0402-1 1 20% 16V 2 TANT-POLY CASE-B3 20% 16V 2 TANT-POLY CASE-B3 1 GND GND GND 1 10UF VOLTAGE=5V P5VUSBCT_SENSE_DIV_R CB721 RB709 1 33UF CB702 1 5 6 10 RB703 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 P5VUSBCT_RTN_DIV_R 1 20 D PP5V_USBCT_VCC SM 1 2 CB703 CRITICAL 1 2 XWB701 2 1 33UF MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE 19 2 CRITICAL CB704 P5VUSBCT_BOOT_RC 2.2 5% 1/20W MF 201 1 PPBUS_G3H CRITICAL RB701 2 1 RB772 C 2.74K 1% 1/20W MF 2 201 CB715 10PF 5% 2 50V C0G 0201 XWB700 SM P5VUSBCT_AGND MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 1 2 PLACE_NEAR=UB700.2:1mm B B A SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN SYNC_DATE=12/04/2015 PAGE TITLE TBT 5V REGULATOR DRAWING NUMBER Apple Inc. 051-00647 REVISION R BOM_COST_GROUP=USB-C NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 117 OF 145 SHEET 108 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 7 6 5 PBUS Rails 116 PPBUS_G3H 64 PPBUS_G3H MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V MAKE_BASE=TRUE PPVCC_S0_CPU 114 66 PPBUS_HS_CPU PPVCC_S0_CPU PPVCC_S0_CPU PPVCCSA_S0_CPU 50 67 PP0V6_S0_DDRVTT PP0V6_S0_DDRVTT 6 8 55 10 72 34 108 8 53 11 116 60 61 PPVCCGT_S0_CPU PPVCCGT_S0_CPU 72 109 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V MAKE_BASE=TRUE 117 PPVCCGT_S0_CPU PPVCCGT_S0_CPU 8 55 109 PP0V6_S3_MEM_VREFDQ_A 21 PP0V6_S3_MEM_VREFCA_A 21 PP0V6_S3_MEM_VREFDQ_B 21 PP0V6_S3_MEM_VREFCA_A 11 116 CPU VCCIO Rails 97 117 71 PPVCCIO_S0_CPU PPVCCIO_S0_CPU MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.95V MAKE_BASE=TRUE 117 PPVCCIO_S0_CPU 94 PP1V8_SUS 72 5 8 PP1V8_SUS PP1V8_SUS 100 74 74 PP1V8_SUS 15 16 17 69 117 PP1V8_S4 PP1V8_S4 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S4 PP1V8_S4 69 117 PP1V8_S3 74 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V MAKE_BASE=TRUE 38 42 20 PP1V8_S3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S3 PP1V8_S3 43 PP1V8_S3_MEM 117 74 71 PP1V2_S3 53 70 PP1V8_S3_MEM MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE B PP1V8_S3_MEM 1V2 Rails 22 23 24 25 116 PP1V2_S3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V MAKE_BASE=TRUE PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 3V3 G3H Rails 114 74 PP1V8_S0 22 23 24 25 116 71 117 21 PP1V8_S0 61 114 MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S0 PP1V8_S0 22 23 24 25 22 23 24 25 116 16 17 58 60 61 51 74 57 46 47 76 PP1V8_S0 48 37 38 42 64 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 43 48 49 48 51 PP1V2_S3_CPUDDR PP1V2_S3_CPUDDR MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V MAKE_BASE=TRUE 47 20 PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H A PP1V8_SUS MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE 94 PPBUS_S4_HS_TPAD PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H 24 25 VOLTAGE=0.6V C MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V MAKE_BASE=TRUE PP3V3_G3H PP0V6_S3_MEM_VREFCA_A MAKE_BASE=TRUE 97 PPBUS_HS_OTH3V3 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE 24 25 VOLTAGE=0.6V 1V8 Rails 10 B PP3V3_G3H PP0V6_S3_MEM_VREFDQ_B MAKE_BASE=TRUE 65 53 63 22 23 VOLTAGE=0.6V 71 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V MAKE_BASE=TRUE PPBUS_S4_HS_TPAD PP0V6_S3_MEM_VREFCA_A MAKE_BASE=TRUE 71 PPBUS_HS_OTH5V PPBUS_S4_HS_TPAD 22 23 VOLTAGE=0.6V 68 PPBUS_HS_GPU PPBUS_HS_OTH3V3 PP0V6_S3_MEM_VREFDQ_A MAKE_BASE=TRUE 67 74 50 21 66 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=13.1V MAKE_BASE=TRUE PPBUS_HS_OTH3V3 26 116 55 PPBUS_HS_OTH5V 50 26 116 D PPVCCSA_S0_CPU PPVCCSA_S0_CPU 63 PPBUS_HS_GPU PPBUS_HS_GPU PPBUS_HS_GPU 117 PP0V6_S0_DDRVTT MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.6V MAKE_BASE=TRUE PPVCCSA_S0_CPU 70 PPBUS_HS_CPU PPBUS_HS_OTH5V 71 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15V MAKE_BASE=TRUE 50 PPBUS_HS_GPU 50 1 75 PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU C 117 50 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=13.1V MAKE_BASE=TRUE PPBUS_HS_GPU PP0V6_S0_DDRVTT 114 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V MAKE_BASE=TRUE 50 PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU 55 2 0V6 Rails PPVCC_S0_CPU 50 68 50 3 IMVP Rails PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H D 4 PP1V2_S3_CPUDDR 8 PP1V2_S3_CPUDDR 10 116 73 19 37 42 37 49 30 31 29 SYNC_MASTER=J80_MLB SYNC_DATE=08/16/2015 PAGE TITLE RTC Rails 70 PP3V0_G3H PP3V3_G3H PP3V3_G3H Power Aliases - 1 104 105 DRAWING NUMBER Apple Inc. PP3V0_G3H MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.0V MAKE_BASE=TRUE PP3V0_G3H PP3V0_G3H 051-00647 REVISION R 74 PP1V2_S0SW PP1V2_S0SW MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V MAKE_BASE=TRUE 12 16 17 PP1V2_S0SW 70 8 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 120 OF 145 SHEET 109 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 7 6 1V0 Rails 117 PP1V0_SUS 72 PP1V0_SUS 69 PP1V0_SUS PP1V0_SUS 16 17 69 PP5V_S5 PP5V_S5 PP5V_S4 PP3V3_S5 PP3V3_S5 17 17 34 108 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP1V0_S3 PP1V0_S3 PP1V0_S3 PP1V0_S3 PP1V0_S3 PP1V0_S3 38 115 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V MAKE_BASE=TRUE 6 8 11 52 65 66 67 117 75 PP5V_S0 PP5V_S0 PP3V3_SUS 76 68 PP5V_S0 PP1V0_S0SW PP3V3_S5_T139 94 6 8 11 18 PP5V_S0 PP5V_S0 97 100 PP3V3_S5_T139 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S5_T139 42 117 52 PP3V3_S4_SOC_PMU PP3V3_S4_SOC_PMU MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE 53 PP3V3_S4_SOC_PMU PP3V3_S4_SOC_PMU 52 PP5V_S0_T139 PP5V_S0_KBD PP5V_S0_KBD MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V MAKE_BASE=TRUE PP5V_S0_KBD 38 42 74 PP3V3_S4 PP5V_S0_T139 97 PPVCORE_S0_GPU PPVCORE_S0_GPU 116 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V MAKE_BASE=TRUE 94 PP1V5R1V35_S0_GPU_MEM 100 PP1V8_GPU 43 PP1V8_GPU 55 PP1V5R1V35_S0_GPU_MEM MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V MAKE_BASE=TRUE 52 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S0_GPU MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V MAKE_BASE=TRUE PP1V5R1V35_S0_GPU_MEM PP1V5R1V35_S0_GPU_MEM PP1V8_S0_GPU PP1V5R1V35_S0_GPU_IC A 89 74 33 116 107 116 114 57 16 17 16 17 12 15 16 17 49 49 49 52 51 51 20 54 47 76 47 59 12 13 15 52 16 17 100 49 89 98 89 100 43 PP3V3_S0_LEFT PP3V3_S0_LEFT PP3V3_S0_LEFT PP3V3_S0_LEFT PP3V3_S0_LEFT 13 16 17 16 17 15 16 17 70 56 74 70 43 114 52 PP3V3_TBT_X_S0 PP3V3_TBT_X_S0 52 PP3V3_TBT_T_S0 PP3V3_TBT_T_S0 PP1V5R1V35_S0_GPU_IC MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V MAKE_BASE=TRUE PP1V5R1V35_S0_GPU_IC 52 50 52 38 42 42 37 70 54 28 29 116 51 51 52 43 49 12 52 102 92 PP1V8_S0_GPU PP1V8_S0_GPU PP1V8_S0_GPU 99 55 92 51 PP3V3_S4_BT 99 116 47 48 52 89 PP3V3_S4_T151 MAKE_BASE=TRUE PP3V3_S4_BT MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500 VOLTAGE=3.3V MAKE_BASE=TRUE 98 51 PP3V3_S0_GPU 95 96 PP3V3_S0_GPU MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S0_GPU 55 PP3V3_S4_WLAN PP3V3_S4_WLAN 36 PP3V3_S4_TPAD 114 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1800 VOLTAGE=3.3V MAKE_BASE=TRUE 93 99 92 PP3V3_S0_GPU PP3V3_S0_GPU PP3V3_S0_GPU PP3V3_S0_GPU 93 92 35 97 92 100 45 98 PP3V3_S4_TPAD 91 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S4_TPAD 98 43 98 SYNC_MASTER=X363_SAKKOC 99 PP3V3_S0_GPU PP3V3_S0_GPU PP3V3_S0_GPU PP3V3_S4SW_SNS 98 PP3V3_S4SW_SNS PP3V3_S4SW_SNS PP3V3_S4SW_SNS 90 94 97 99 98 SYNC_DATE=01/14/2016 PAGE TITLE Power Aliases - 2 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE DRAWING NUMBER 50 Apple Inc. 50 51 52 53 55 051-00647 REVISION R Digital Ground GND MIN_NECK_WIDTH=0.1000 MIN_LINE_WIDTH=0.1270 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 6 5 4 3 2 121 OF 145 SHEET 110 OF 121 IV ALL RIGHTS RESERVED 7 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT WWW.AliSaler.Com 103 35 PP3V3_S4_T151 74 8 C 54 PP3V3_S0_LEFT PP3V3_S0_LEFT PP3V3_S0_LEFT PP3V3_S0_LEFT PP3V3_S0_LEFT 18 73 114 D 49 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE 12 14 16 17 29 103 12 14 20 73 PP3V3_S0_LEFT PP3V3_S0_LEFT 91 74 54 91 99 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S0_GPU PP1V8_S0_GPU 92 PP3V3_S4_T151 55 52 55 100 56 B PP1V8_GPU PPVDDCI_S0_GPU PPVDDCI_S0_GPU PPVDDCI_S0_GPU PPVDDCI_S0_GPU 116 87 PP3V3_S4 55 90 92 116 PPVDDCI_S0_GPU 51 53 42 PPVCORE_S0_GPU 94 76 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 PP3V3_S4 114 GPU Rails B 74 PP3V3_S4 114 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V MAKE_BASE=TRUE 74 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE 40 41 PP5V_S0_T139 74 PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS T208 Rails 51 74 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE PP1V0_S0SW C 19 PP3V3_SUS 47 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1V MAKE_BASE=TRUE 72 53 74 74 74 43 56 117 65 8 11 20 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 17 74 117 PP3V3_S5 73 12 117 70 PP3V3_S5 74 16 17 74 PP3V3_S5 65 114 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 74 PP3V3_S5 74 PP3V3_S0 74 PP3V3_S5 18 20 1 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE 12 16 17 PP3V3_S5 51 53 PP3V3_S0 91 74 PP3V3_S5 PP3V3_S5 PP3V3_S5 43 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 16 2 115 MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S5 PP5V_S4 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1V MAKE_BASE=TRUE PP1V0_S0SW 69 MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V MAKE_BASE=TRUE 16 PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_S3 117 PP5V_S4 16 3 3V3 Rails MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V MAKE_BASE=TRUE 16 PP1V0_SUS 74 117 16 17 PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_SUS PP1V0_SUS 74 4 5V Rails MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1V MAKE_BASE=TRUE D 5 1 SIZE D A 8 7 6 5 4 3 SIGNAL ALIAS NC ALIASES 2 111 111 111 111 111 D 111 MAKE_BASE=TRUE 12 NC_CLKOUT_PCIE_1_N NC_CLKOUT_PCIE_1_N 12 NC_CLKOUT_PCIE_1_P NC_CLKOUT_PCIE_1_P 12 NC_CLKOUT_PCIE_2_N NC_CLKOUT_PCIE_2_N 12 111 12 NC_CLKOUT_PCIE_2_P NC_CLKOUT_PCIE_2_P 12 111 12 NC_CLKOUT_PCIE_6_N NC_CLKOUT_PCIE_6_N 12 111 12 NC_CLKOUT_PCIE_6_P NC_CLKOUT_PCIE_6_P 12 111 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 12 NC_CLKOUT_PCIE_8_N NC_CLKOUT_PCIE_8_N 12 111 111 12 NC_CLKOUT_PCIE_8_P NC_CLKOUT_PCIE_8_P 12 111 12 NC_CLKOUT_PCIE_9_N NC_CLKOUT_PCIE_9_N 111 MAKE_BASE=TRUE MAKE_BASE=TRUE IN PEG_GPU_D2R_P<7..0> =PEG_D2R_P<7..0> OUT 5 113 29 IN PEG_GPU_D2R_N<7..0> =PEG_D2R_N<7..0> OUT 5 113 29 IN PEG_GPU_R2D_C_P<7..0> =PEG_R2D_C_P<7..0> IN 5 113 29 OUT PEG_GPU_R2D_C_N<7..0> =PEG_R2D_C_N<7..0> IN 5 113 29 OUT MAKE_BASE=TRUE NC_TP_PCH_GPP_G1 113 91 IN NC_TP_PCH_GPP_G2 NC_TP_PCH_GPP_G2 113 91 15 OUT NC_TP_PCH_GPP_G3 113 91 15 NC_TP_PCH_GPP_G3 OUT 15 NC_TP_PCH_GPP_G4 NC_TP_PCH_GPP_G4 15 NC_TP_PCH_GPP_G5 NC_TP_PCH_GPP_G5 113 103 IN 15 NC_TP_PCH_GPP_G6 NC_TP_PCH_GPP_G6 113 103 IN 15 NC_TP_PCH_GPP_G7 NC_TP_PCH_GPP_G7 113 103 OUT 15 NC_TP_PCH_GPP_G8 NC_TP_PCH_GPP_G8 113 103 OUT MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_TBT_X_D2R_P<3..0> =PEG_D2R_P<11..8> OUT 5 PCIE_TBT_X_D2R_N<3..0> =PEG_D2R_N<11..8> OUT 5 PCIE_TBT_X_R2D_C_P<3..0> =PEG_R2D_C_P<11..8> IN 5 PCIE_TBT_X_R2D_C_N<3..0> =PEG_R2D_C_N<11..8> IN 5 PCIE_TBT_T_D2R_P<3..0> =PEG_D2R_P<15..12> OUT 5 PCIE_TBT_T_D2R_N<3..0> =PEG_D2R_N<15..12> OUT 5 PCIE_TBT_T_R2D_C_P<3..0> =PEG_R2D_C_P<15..12> IN 5 PCIE_TBT_T_R2D_C_N<3..0> =PEG_R2D_C_N<15..12> IN 5 MAKE_BASE=TRUE NC_TP_PCH_GPP_G1 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE GPU ALIAS MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 111 91 15 12 111 MAKE_BASE=TRUE 113 1 Thunderbolt Signals Through PEG GPU PEG Lanes MAKE_BASE=TRUE 12 111 MAKE_BASE=TRUE 2 12 EG_CLKREQ_OUT_L EG_CLKREQ_OUT_L 98 12 EG_PEG_CLK100M_N EG_PEG_CLK100M_N 91 12 EG_PEG_CLK100M_P EG_PEG_CLK100M_P 91 EG_RESET_L 91 99 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE D MAKE_BASE=TRUE EG_RESET_L 12 111 MAKE_BASE=TRUE 89 111 12 NC_CLKOUT_PCIE_9_P NC_CLKOUT_PCIE_9_P 12 111 111 12 NC_CLKOUT_PCIE_10_N NC_CLKOUT_PCIE_10_N 12 111 111 12 NC_CLKOUT_PCIE_10_P NC_CLKOUT_PCIE_10_P 12 111 111 12 NC_CLKOUT_PCIE_11_N NC_CLKOUT_PCIE_11_N 12 111 111 12 NC_CLKOUT_PCIE_11_P NC_CLKOUT_PCIE_11_P 12 111 111 12 NC_CLKOUT_PCIE_12_N NC_CLKOUT_PCIE_12_N 12 111 111 12 NC_CLKOUT_PCIE_12_P NC_CLKOUT_PCIE_12_P 12 111 111 12 NC_CLKOUT_PCIE_14_N NC_CLKOUT_PCIE_14_N 12 111 111 12 NC_CLKOUT_PCIE_14_P NC_CLKOUT_PCIE_14_P 12 111 111 12 NC_CLKOUT_PCIE_15_N NC_CLKOUT_PCIE_15_N 12 111 111 12 NC_CLKOUT_PCIE_15_P NC_CLKOUT_PCIE_15_P 12 111 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE C CPU Display Aliases MAKE_BASE=TRUE 14 NC_PCH_GPP_F15 14 NC_PCH_GPP_F16 14 NC_PCH_GPP_F17 14 NC_PCH_GPP_F18 NC_PCH_GPP_F15 MAKE_BASE=TRUE C NC_PCH_GPP_F16 MAKE_BASE=TRUE NC_PCH_GPP_F17 MAKE_BASE=TRUE NC_PCH_GPP_F18 eDP conn 114 76 114 76 113 76 113 76 DPMUX EDP_INT_ML_P<3..0> EDP_INT_ML_P<3..0> 89 EDP_INT_ML_N<3..0> EDP_INT_ML_N<3..0> 89 EDP_AUXCH_C_P EDP_AUXCH_C_P 89 EDP_AUXCH_C_N EDP_AUXCH_C_N 89 NC_DDI1_ML_C_P<3..0> NC_DDI1_ML_C_P<3..0> 5 NC_DDI1_ML_C_N<3..0> NC_DDI1_ML_C_N<3..0> 5 NC_DDI1_AUXCH_C_P NC_DDI1_AUXCH_C_P 5 NC_DDI1_AUXCH_C_N NC_DDI1_AUXCH_C_N 5 NC_DDI2_ML_C_P<3..0> NC_DDI2_ML_C_P<3..0> 5 NC_DDI2_ML_C_N<3..0> NC_DDI2_ML_C_N<3..0> 5 NC_DDI2_AUXCH_C_P NC_DDI2_AUXCH_C_P 5 NC_DDI2_AUXCH_C_N NC_DDI2_AUXCH_C_N 5 NC_DDI3_ML_P<3..0> NC_DDI3_ML_P<3..0> 5 NC_DDI3_ML_N<3..0> NC_DDI3_ML_N<3..0> 5 NC_DDI3_AUXCH_P NC_DDI3_AUXCH_P 5 NC_DDI3_AUXCH_N NC_DDI3_AUXCH_N 5 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE B NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE 89 DPMUX_UC_RX DPMUX_UC_TX 15 NC_EDP_IG_BKLT_PWM 89 DPMUX_UC_RX DPMUX_UC_TX MAKE_BASE=TRUE MAKE_BASE=TRUE B 89 89 NC_EDP_IG_BKLT_PWM MAKE_BASE=TRUE EPD PANEL A MAKE_BASE 75 75 I2C_BKLT_SCL I2C_BKLT_SDA SYNC_MASTER=X363_SAKKOC TRUE I2C_BKLT_SCL 76 114 TRUE I2C_BKLT_SDA 76 114 SYNC_DATE=01/13/2016 PAGE TITLE 12 NC_PCH_SLP_WLAN_L MAKE_BASE=TRUE Signal Aliases NC_PCH_SLP_WLAN_L DRAWING NUMBER 13 13 NC_SPI_CS1_L NC_SPI_CS2_L MAKE_BASE=TRUE MAKE_BASE=TRUE NC_SPI_CS1_L NC_SPI_CS2_L Apple Inc. 051-00647 REVISION R UNUSED SIGNALS NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 122 OF 145 SHEET 111 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 7 6 5 4 3 2 1 Memory Bit/Byte Swizzle LPDDR3 COMMAND/ADDRESS D C B MAKE_BASE TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 A MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> 22 22 22 22 22 22 22 22 23 23 23 23 23 23 23 23 MAKE_BASE TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 TRUE 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 113 7 BDW-H LPDDR3 NET BIT SWIZZLE MAKE_BASE=TRUE MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63> MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 22 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 23 113 7 BDW-H LPDDR3 NET BIT SWIZZLE MAKE_BASE=TRUE MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> WWW.AliSaler.Com 4 D 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 C 24 24 24 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 B 25 25 25 25 25 25 25 25 25 25 24 24 24 24 24 SYNC_MASTER=J80_MLB 25 PAGE TITLE 25 25 SYNC_DATE=11/06/2015 Memory Bit/Byte Swizzle DRAWING NUMBER 051-00647 25 Apple Inc. 25 25 REVISION R 25 25 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE 3 2 10.0.0 dvt-fab10 123 OF 145 SHEET 112 OF 121 IV ALL RIGHTS RESERVED 5 24 24 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 6 24 24 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 7 24 24 II NOT TO REPRODUCE OR COPY IT 8 24 1 SIZE D A 8 7 6 5 4 3 XTAL High Speed NO_TEST DMI 13 5 DMI_S2N_P<3..0> DMI_S2N_N<3..0> DMI_N2S_P<3..0> DMI_N2S_N<3..0> IN 13 5 IN 13 5 IN 13 5 IN NO_TEST=1 D 99 27 IN 99 27 IN 27 27 IN 99 27 IN 99 27 IN 27 27 IN IN 101 99 IN 101 99 IN 101 IN 101 101 101 99 IN IN 99 IN 101 IN 101 IN 99 27 99 27 IN IN 101 99 IN 101 99 IN 27 IN 27 101 C IN IN IN 101 IN 99 27 IN 99 27 IN 101 101 99 99 IN IN 27 IN 27 IN 101 IN 101 IN 12 6 NO_TEST=1 NO_TEST=1 NO_TEST=1 DP - CPU/ACE DP_X_SNK0_ML_C_N<3..0> DP_X_SNK0_ML_C_P<3..0> DP_X_SNK0_ML_N<3..0> DP_X_SNK0_ML_P<3..0> DP_X_SNK1_ML_C_N<3..0> DP_X_SNK1_ML_C_P<3..0> DP_X_SNK1_ML_N<3..0> DP_X_SNK1_ML_P<3..0> DP_T_SNK0_ML_C_N<3..0> DP_T_SNK0_ML_C_P<3..0> DP_T_SNK0_ML_N<3..0> DP_T_SNK0_ML_P<3..0> DP_T_SNK1_ML_C_N<3..0> DP_T_SNK1_ML_C_P<3..0> DP_T_SNK1_ML_N<3..0> DP_T_SNK1_ML_P<3..0> DP_X_SNK0_AUXCH_C_P DP_X_SNK0_AUXCH_C_N DP_T_SNK0_AUXCH_C_P DP_T_SNK0_AUXCH_C_N DP_X_SNK0_AUXCH_P DP_X_SNK0_AUXCH_N DP_T_SNK0_AUXCH_P DP_T_SNK0_AUXCH_N DP_X_SNK1_AUXCH_C_P DP_X_SNK1_AUXCH_C_N DP_T_SNK1_AUXCH_C_P DP_T_SNK1_AUXCH_C_N DP_X_SNK1_AUXCH_P DP_X_SNK1_AUXCH_N DP_T_SNK1_AUXCH_P DP_T_SNK1_AUXCH_N 111 91 IN NO_TEST=1 111 91 IN NO_TEST=1 111 NO_TEST=1 111 91 IN NO_TEST=1 111 29 IN NO_TEST=1 111 29 IN NO_TEST=1 111 29 IN NO_TEST=1 111 IN NO_TEST=1 111 103 IN NO_TEST=1 111 103 IN NO_TEST=1 103 101 IN NO_TEST=1 103 101 IN NO_TEST=1 29 27 IN NO_TEST=1 29 27 IN NO_TEST=1 29 27 IN NO_TEST=1 29 27 IN NO_TEST=1 103 NO_TEST=1 103 101 IN NO_TEST=1 111 103 IN NO_TEST=1 111 103 IN NO_TEST=1 91 IN NO_TEST=1 91 IN NO_TEST=1 91 IN NO_TEST=1 91 IN 111 76 IN IN NO_TEST=1 NO_TEST=1 38 14 IN 38 14 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 95 93 IN NO_TEST=1 95 93 IN NO_TEST=1 95 93 113 113 B IN 35 14 IN 35 IN 35 IN 35 14 IN 35 14 IN 87 77 14 IN 87 77 14 IN 113 113 113 77 77 IN 77 IN 87 77 14 IN 14 IN 14 IN 77 113 IN 87 77 14 IN 87 77 IN 87 77 IN 14 IN 87 77 IN 14 IN 87 77 IN 32 27 IN 32 27 IN 32 27 IN 32 27 IN 30 27 IN 32 27 A IN IN 32 27 IN 32 27 IN 31 27 IN 32 27 IN 31 27 30 27 IN IN 27 IN 27 IN 27 IN 27 IN PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_R2D_P PCIE_AP_R2D_N NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N NO_TEST=1 NO_TEST=1 PCH/SSD PCIE_SSD_D2R_N<3..0> PCIE_SSD_D2R_P<3..0> PCIE_SSD_R2D_N<3..0> PCIE_SSD_R2D_N<3..0> PCIE_SSD_D2R_C_N<3..0> PCIE_SSD_R2D_C_N<3..0> PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_C_P<3..0> PCIE_SSD_R2D_C_N<3..0> PCIE_SSD_D2R_LB_P<0> PCIE_SSD_R2D_LB_N<0> PCIE_SSD_D2R_P<3> PCIE_SSD_D2R_LB_N<0> PCIE_SSD_D2R_N<3> PCIE_SSD_R2D_LB_P<0> 96 93 IN 96 93 IN 96 93 96 93 IN IN IN 96 93 IN 96 93 IN 96 93 96 93 IN IN 96 93 IN 96 93 IN 96 93 IN 96 93 95 93 IN IN 95 93 IN 95 93 IN NO_TEST=1 95 93 IN NO_TEST=1 95 93 NO_TEST=1 95 93 NO_TEST=1 95 93 NO_TEST=1 95 93 NO_TEST=1 95 93 NO_TEST=1 95 93 NO_TEST=1 95 93 NO_TEST=1 95 93 IN NO_TEST=1 95 93 IN 95 93 IN NO_TEST=1 NO_TEST=1 IN IN IN IN IN IN IN IN 95 93 IN 95 93 IN 95 93 IN 95 93 IN 95 93 USBC_XB_D2R_P<2..1> USBC_XA_D2R_P<2..1> USBC_XB_R2D_C_P<2..1> DP_XA_AUXCH_P USBC_XA_D2R_N<2..1> USBC_XB_R2D_C_N<2..1> USBC_XA_R2D_C_P<2..1> DP_XB_AUXCH_P USBC_XA_R2D_C_N<2..1> DP_XB_AUXCH_N DP_XA_AUXCH_N DP_XA_AUXCH_C_N DP_XA_AUXCH_C_P DP_XB_AUXCH_C_P DP_XB_AUXCH_C_N IN IN 95 93 USB-C X USBC_XB_D2R_N<2..1> IN 95 93 96 93 EDP_AUXCH_C_N EDP_AUXCH_C_P IN PEG_GPU_D2R_N<7..0> PEG_GPU_D2R_P<7..0> PEG_GPU_R2D_C_N<7..0> PEG_GPU_R2D_C_P<7..0> NO_TEST=1 PCIE_TBT_X_D2R_P<3..0> PCIE_TBT_X_D2R_N<3..0> PCIE_TBT_X_R2D_C_P<3..0> PCIE_TBT_X_R2D_C_N<3..0> PCIE_TBT_T_D2R_P<3..0> PCIE_TBT_T_D2R_N<3..0> PCIE_TBT_T_D2R_C_P<3..0> PCIE_TBT_T_D2R_C_N<3..0> PCIE_TBT_X_D2R_C_P<3..0> PCIE_TBT_X_D2R_C_N<3..0> PCIE_TBT_X_R2D_P<3..0> PCIE_TBT_X_R2D_N<3..0> PCIE_TBT_T_R2D_P<3..0> PCIE_TBT_T_R2D_N<3..0> PCIE_TBT_T_R2D_C_P<3..0> PCIE_TBT_T_R2D_C_N<3..0> PEG_GPU_D2R_C_N<7..0> PEG_GPU_D2R_C_P<7..0> PEG_GPU_R2D_N<7..0> PEG_GPU_R2D_P<7..0> NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 IN 95 93 IN NO_TEST=1 95 93 IN NO_TEST=1 95 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN NO_TEST=1 96 93 IN 96 93 IN IN IN 12 6 IN 12 6 IN 12 6 IN 12 6 IN 12 6 IN IN 87 12 IN 87 77 IN 87 77 IN 115 18 12 IN 115 18 12 IN 35 12 IN 35 12 IN NO_TEST=1 NO_TEST=1 IN 87 12 NO_TEST=1 NO_TEST=1 IN CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_LB_N PCIE_CLK100M_SSD_LB_P NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 89 5 IN 89 5 IN 89 5 IN 89 5 IN 99 89 IN 99 89 IN 99 89 IN 99 89 IN NO_TEST=1 NO_TEST=1 89 IN NO_TEST=1 89 IN 89 IN 89 IN FB_A0_CKE_L FB_A1_CKE_L FB_A0_WE_L FB_A1_WE_L FB_B1_CS_L FB_B0_CKE_L FB_B1_CKE_L FB_B0_WE_L FB_B0_WE_L FB_B0_CLK_P FB_B1_CLK_N FB_B1_CLK_P FB_B0_RAS_L FB_B1_RAS_L FB_B0_CAS_L FB_B1_CAS_L FB_B0_CS_L FB_A0_DQ<31..0> FB_A1_DQ<31..0> FB_A0_A<8..0> FB_A1_A<8..0> FB_A0_WCLK_N<1..0> FB_A0_WCLK_P<1..0> FB_A1_WCLK_N<1..0> FB_A1_WCLK_P<1..0> FB_A0_EDC<3..0> FB_A1_EDC<3..0> FB_A0_DBI_L<3..0> FB_A1_DBI_L<3..0> FB_A0_ABI_L FB_A1_ABI_L FB_A0_CLK_N FB_A0_CLK_P FB_A1_CLK_N FB_A1_CLK_P FB_A0_RAS_L FB_A1_RAS_L FB_A0_CAS_L FB_A1_CAS_L FB_A0_CS_L FB_B0_CLK_N FB_B0_DQ<31..0> FB_B1_DQ<31..0> FB_B0_A<8..0> FB_B1_A<8..0> FB_B0_WCLK_N<1..0> FB_B0_WCLK_P<1..0> FB_B1_WCLK_N<1..0> FB_B1_WCLK_P<1..0> FB_B0_EDC<3..0> FB_B1_EDC<3..0> FB_B0_DBI_L<3..0> FB_B1_DBI_L<3..0> FB_B0_ABI_L FB_B1_ABI_L 19 IN 19 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 29 27 IN 29 IN 29 27 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 101 IN 103 IN 38 IN 101 IN NO_TEST=1 38 IN NO_TEST=1 38 IN 77 IN 77 IN NO_TEST=1 77 IN NO_TEST=1 99 98 IN NO_TEST=1 103 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N DP_INT_IG_ML_N<3..0> DP_INT_IG_ML_P<3..0> DP_INT_IG_AUX_N DP_INT_IG_AUX_P DP_INT_EG_ML_N<3..0> DP_INT_EG_ML_P<3..0> DP_INT_EG_AUX_N DP_INT_EG_AUX_P 103 NO_TEST=1 NO_TEST=1 99 98 IN 98 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 DPMUX_UC_XTAL DPMUX_UC_EXTAL DPMUX_UC_EXTAL_R DPMUX_UC_XTAL_R NO_TEST=1 NO_TEST=1 NO_TEST=1 26 22 7 IN 26 23 22 7 IN 26 23 22 7 IN 112 7 IN 112 7 IN 112 7 IN 112 7 IN 112 112 7 7 IN IN NO_TEST=1 26 23 7 IN NO_TEST=1 26 24 7 IN NO_TEST=1 26 25 7 IN 26 25 24 7 IN NO_TEST=1 NO_TEST=1 26 25 24 7 NO_TEST=1 NO_TEST=1 NO_TEST=1 36 IN NO_TEST=1 IN IN NO_TEST=1 36 IN NO_TEST=1 36 IN NO_TEST=1 36 IN 36 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 36 IN NO_TEST=1 36 35 IN NO_TEST=1 36 IN 36 35 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 36 IN NO_TEST=1 36 35 IN NO_TEST=1 36 IN 36 35 IN NO_TEST=1 NO_TEST=1 36 NO_TEST=1 NO_TEST=1 36 35 NO_TEST=1 IN IN 36 IN 36 35 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 82 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 MEM_A_CLK_P<1..0> MEM_A_CLK_N<1..0> MEM_A_DQ<63..0> MEM_B_DQ<63..0> MEM_A_DQS_P<7..0> MEM_A_DQS_N<7..0> MEM_B_DQS_P<7..0> MEM_B_DQS_N<7..0> MEM_A_CAB<9..0> MEM_B_CAA<9..0> MEM_B_CAB<9..0> NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 MEM_B_CLK_P<1..0> MEM_B_CLK_N<1..0> NO_TEST=1 NO_TEST=1 WIFI NO_TEST=1 36 TBT_X_XTAL25M_OUT TBT_X_XTAL25M_OUT_R TBT_X_XTAL25M_IN TBT_T_XTAL25M_OUT TBT_T_XTAL25M_OUT_R SOC_XTAL_24M_O TBT_T_XTAL25M_IN SOC_XTAL_24M_I SOC_XTAL_24M_O_R SSD_CLKIN SSD_CLKOUT SSD_CLKOUT_R GPU_XTAL_OUT GPU_XTAL_OR_CLK_IN GPU_XTAL_XTAL_OR_CLK MEMMEM_A_CAA<9..0> NO_TEST=1 USB_CAMERA_DFR_N USB_CAMERA_DFR_P BAFFIN FRAME BUFFER FB_A1_CS_L IN NC_PCH_CLK24M_XTALOUT SYSCLK_CLK24M_X2 SYSCLK_CLK24M_X2_R SYSCLK_CLK24M_X1 1 NO_TEST=1 DP MUX CRYSTAL NO_TEST=1 19 GPU_XTAL_PU_OR_CAP NO_TEST=1 NO_TEST=1 MUX NO_TEST=1 PCH/DFR NO_TEST=1 PCH/AR 35 14 101 NO_TEST=1 CPU/EDP 76 IN 29 95 93 111 91 IN CPU/PCH CLK PEG 2 50_0_ANT 50_1_ANT 50_2_ANT 50_0_COM 50_1_COM NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 50_2_COM 50_A_0_DIPLEXER 50_A_0_MATCH 50_G_0_DIPLEXER 50_G_0_MATCH 50_A_1_DIPLEXER 50_A_1_MATCH 50_G_1_DIPLEXER 50_G_1_MATCH 50_A_2_DIPLEXER 50_A_2_MATCH 50_G_2_DIPLEXER 50_G_2_MATCH NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 106 101 IN 106 101 IN NO_TEST=1 106 101 IN NO_TEST=1 106 101 IN 104 101 IN 104 101 IN NO_TEST=1 101 IN NO_TEST=1 101 IN 106 101 IN 106 101 IN NO_TEST=1 106 101 IN NO_TEST=1 106 101 IN 105 101 IN 105 101 IN NO_TEST=1 101 IN NO_TEST=1 101 IN 85 83 IN 85 83 IN 85 83 IN NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 85 83 85 83 IN IN 85 83 IN 85 83 IN USBC_TA_D2R_P<2..1> USBC_TA_D2R_N<2..1> USBC_TA_R2D_C_P<2..1> USBC_TA_R2D_C_N<2..1> DP_TA_AUXCH_P DP_TA_AUXCH_N DP_TA_AUXCH_C_P DP_TA_AUXCH_C_N USBC_TB_D2R_P<2..1> USBC_TB_D2R_N<2..1> USBC_TB_R2D_C_P<2..1> USBC_TB_R2D_C_N<2..1> DP_TB_AUXCH_P DP_TB_AUXCH_N DP_TB_AUXCH_C_P DP_TB_AUXCH_C_N SSD_NAND_FH_DQ4 SSD_NAND_FH_DQ0 SSD_NAND_FH_DQS_P SSD_NAND_FH_DQ5 SSD_NAND_FH_DQ6 SSD_NAND_FH_DQ7 SSD_NAND_FH_DQS_N IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN 85 83 IN NO_TEST=1 NO_TEST=1 USB-C T NO_TEST=1 85 83 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 SSD_NAND_FA_DQ0 SSD_NAND_FA_DQ1 SSD_NAND_FA_DQ2 SSD_NAND_FA_DQ3 SSD_NAND_FA_DQ4 SSD_NAND_FA_DQ5 SSD_NAND_FA_DQ6 SSD_NAND_FA_DQ7 SSD_NAND_FA_DQS_N SSD_NAND_FA_DQS_P SSD_NAND_FB_DQ0 SSD_NAND_FB_DQ1 SSD_NAND_FB_DQ2 SSD_NAND_FB_DQ3 SSD_NAND_FB_DQ4 SSD_NAND_FB_DQ5 SSD_NAND_FB_DQ6 SSD_NAND_FB_DQ7 SSD_NAND_FB_DQS_N SSD_NAND_FB_DQS_P SSD_NAND_FC_DQ0 SSD_NAND_FC_DQ1 SSD_NAND_FC_DQ2 SSD_NAND_FC_DQ3 SSD_NAND_FC_DQ4 SSD_NAND_FC_DQ5 SSD_NAND_FC_DQ6 SSD_NAND_FC_DQ7 SSD_NAND_FC_DQS_N SSD_NAND_FC_DQS_P SSD_NAND_FD_DQ0 SSD_NAND_FD_DQ1 NAND NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 SSD_NAND_FE_DQS_N SSD_NAND_FE_DQS_P NO_TEST=1 SSD_NAND_FF_DQ0 SSD_NAND_FF_DQ1 SSD_NAND_FF_DQ2 SSD_NAND_FF_DQ3 SSD_NAND_FF_DQ4 SSD_NAND_FF_DQ5 SSD_NAND_FF_DQ6 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 SSD_NAND_FH_DQ3 NO_TEST=1 SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/14/2016 PAGE TITLE ICT & FCT 1 DRAWING NUMBER Apple Inc. NO_TEST=1 051-00647 REVISION R NO_TEST=1 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 5 4 3 2 124 OF 145 SHEET 113 OF 121 IV ALL RIGHTS RESERVED 6 10.0.0 dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 7 B NO_TEST=1 SSD_NAND_FF_DQ7 SSD_NAND_FF_DQS_N SSD_NAND_FF_DQS_P SSD_NAND_FG_DQ0 SSD_NAND_FG_DQ2 SSD_NAND_FG_DQ3 SSD_NAND_FG_DQ4 SSD_NAND_FG_DQ5 SSD_NAND_FG_DQ6 SSD_NAND_FG_DQ7 SSD_NAND_FG_DQS_N SSD_NAND_FG_DQS_P SSD_NAND_FH_DQ1 SSD_NAND_FH_DQ2 NO_TEST=1 NO_TEST=1 C NO_TEST=1 SSD_NAND_FD_DQ2 SSD_NAND_FD_DQ3 SSD_NAND_FD_DQ4 SSD_NAND_FD_DQ5 SSD_NAND_FD_DQ6 SSD_NAND_FD_DQ7 SSD_NAND_FD_DQS_N SSD_NAND_FD_DQS_P SSD_NAND_FE_DQ0 SSD_NAND_FE_DQ1 SSD_NAND_FE_DQ2 SSD_NAND_FE_DQ3 SSD_NAND_FE_DQ4 SSD_NAND_FE_DQ5 SSD_NAND_FE_DQ6 SSD_NAND_FE_DQ7 NO_TEST=1 NO_TEST=1 D NO_TEST=1 II NOT TO REPRODUCE OR COPY IT 8 NO_TEST=1 1 SIZE D A 8 7 6 MESA CONNECTOR 45 IN 45 IN 45 IN 45 IN 45 37 IN 45 37 IN D 45 IN 45 IN 45 IN 45 IN 45 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 109 57 IN 57 IN 57 IN 57 IN 76 64 57 48 29 114 57 IN 57 IN 57 15 IN IN 57 47 46 IN 57 47 46 IN 61 IN 61 IN 61 IN 61 IN 60 IN 60 IN 60 IN 60 IN 61 58 IN IN 110 IN 109 IN 114 114 43 114 43 IN 103 29 IN 114 43 IN 43 IN 115 56 43 IN 115 56 43 IN 110 114 IN 114 43 IN 114 43 IN 114 43 IN 48 43 IN 114 43 IN FUNC_TEST=TRUE 42 38 IN 42 37 IN 42 IN 42 38 37 42 38 37 114 IN 42 37 IN 42 38 114 IN 42 37 110 B IN FUNC_TEST=TRUE IN IN 42 38 IN 42 IN 42 42 38 IN IN 42 38 IN 42 38 IN FUNC_TEST=TRUE FUNC_TEST=TRUE 114 FUNC_TEST=TRUE 114 FUNC_TEST=TRUE FUNC_TEST=TRUE 114 FUNC_TEST=TRUE SPKRCONN_TR_OUT_POS SPKRCONN_TR_OUT_NEG SPKRCONN_WR_OUT_POS SPKRCONN_WR_OUT_NEG SPKRCONN_TL_OUT_POS SPKRCONN_TL_OUT_NEG SPKRCONN_WL_OUT_POS SPKRCONN_WL_OUT_NEG SPKR_ID0 GND FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE IN 43 IN 43 IN IN 49 46 IN 110 IN 43 IN 43 IN 43 IN 43 13 IN 43 IN 43 13 IN 43 IN 43 13 IN 43 IN 48 46 IN 48 47 46 IN FUNC_TEST=TRUE FUNC_TEST=TRUE 43 49 46 FUNC_TEST=TRUE 48 47 43 42 IN 114 43 IN FUNC_TEST=TRUE 114 43 IN FUNC_TEST= 114 43 IN 46 43 IN FUNC_TEST=TRUE DFR_TOUCH_GPIO2 DFR_TOUCH_SPI_CS_L FUNC_TEST=TRUE 43 IN 114 42 38 IN FUNC_TEST=TRUE DFR_TOUCH_SPI_MOSI_R DFR_TOUCH_ROM_I2C_SCL DFR_TOUCH_ROM_I2C_SDA DFR_TOUCH_RESET_L 42 38 IN 42 38 IN 42 IN 42 IN 42 38 IN 42 38 IN 42 38 IN 42 38 IN 42 37 42 38 37 A 42 38 37 IN IN IN FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 62 IN 62 IN 62 IN 62 IN 62 IN 62 IN 62 IN 62 IN AUD_CONN_HP_LEFT AUD_CONN_HP_RIGHT AUD_CONN_RING2 AUD_CONN_SLEEVE AUD_CONN_HP_SENSE_L AUD_CONN_HP_SENSE_R AUD_CONN_TIP_SENSE AUD_CONN_SLEEVE_XW AUD_CONN_RING2_XW GND FUNC_TEST=TRUE FUNC_TEST=TRUE 116 76 75 FUNC_TEST=TRUE 76 FUNC_TEST=TRUE 76 76 FUNC_TEST=TRUE IN IN IN IN 76 IN 111 76 IN FUNC_TEST=TRUE 111 76 IN DFR_TOUCH_PANEL_DETECT DFR_DISP_VSYNC FUNC_TEST=TRUE 111 DFR_TOUCH_SPI_MISO_R DFR_TOUCH_SPI_CLK_R FUNC_TEST=TRUE DFR_TOUCH_INT_L DFR_CLKIN_RESET_L FUNC_TEST=TRUE DFR_TOUCH_ROM_WC FUNC_TEST=TRUE X2 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE X3 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 76 IN 111 76 111 76 IN 111 76 IN 111 76 IN 38 IN IN 38 IN 76 IN 76 38 IN 76 42 IN 76 42 IN 76 38 37 IN 76 38 37 IN FUNC_TEST=TRUE X4 111 76 IN 111 76 IN 49 46 IN 49 46 IN 76 48 IN 76 20 IN 89 76 IN 76 15 IN 76 IN 89 76 IN FUNC_TEST=TRUE X2 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE X6 1 80 77 FUNC_TEST=TRUE FUNC_TEST=TRUE 80 77 FUNC_TEST=TRUE 80 77 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 64 63 IN FUNC_TEST=TRUE 49 46 IN FUNC_TEST=TRUE 49 46 IN FUNC_TEST=TRUE 63 IN 64 50 X5 114 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE IN IN 48 43 IN 64 IN 64 IN 64 IN 64 IN FUNC_TEST=TRUE 116 64 IN 64 63 IN FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE X5 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE X3 76 49 IN 76 49 IN 38 IN 38 IN PPVOUT_S0_LCDBKLT PP3V3_S0SW_LCD EDP_AUXCH_C_N EDP_AUXCH_C_P EDP_INT_ML_N<0> EDP_INT_ML_P<0> EDP_INT_ML_N<1> EDP_INT_ML_P<1> EDP_INT_ML_N<2> EDP_INT_ML_P<2> EDP_INT_ML_N<3> EDP_INT_ML_P<3> MIPIC_CLK_N MIPIC_CLK_P PP5V_S0SW_LCD PP5V_S0_ALSCAM_F I2C_ALS_SDA I2C_ALS_SCL I2C_CAM_SCL I2C_CAM_SDA I2C_BKLT_SDA I2C_BKLT_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL BKLT_PWM_TCON2MLB BKLT_PWM_MLB2TCON LCD_FSS LCD_IRQ_L PPDCIN_G3H 1 TP-P6 A TP-P6 1 A TP-P6 1 PPDCIN_G3H PPDCIN_G3H A 64 HPWR_EN_L 110 PP3V3_S0 109 A TRUE GND FUNC_TEST=TRUE FUNC_TEST=TRUE 1 TP-P6 A 1 TP-P6 A 1 TP-P6 A 1 TP-P6 A TP-P6 PP3V3_G3H USB_C 115 32 IN FUNC_TEST=TRUE 87 77 IN 80 77 IN FUNC_TEST=TRUE 103 86 80 IN FUNC_TEST=TRUE 103 86 80 IN FUNC_TEST=TRUE 80 77 48 IN FUNC_TEST=TRUE 80 77 48 IN FUNC_TEST=TRUE 83 82 81 80 78 77 15 84 IN SMC_ONOFF_L 46 45 48 47 FUNC_TEST=TRUE 1 76 48 29 64 57 114 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 14 FUNC_TEST=TRUE 84 78 1 USB3_TEST_D2R_P 1 TP-P6 A 1 TP-P6 A TP-P6 1 A 1 TP-P6 FUNC_TEST=TRUE FUNC_TEST=TRUE 1 109 PPBUS_G3H 1 TP-P6 14 USB3_TEST_R2D_N 14 USB3_TEST_R2D_P 1 TP-P6 A 1 TP-P6 A 1 TP-P6 USB_TEST_P 14 USB_TEST_N 46 12 73 87 14 115 FUNC_TEST=TRUE 46 29 47 87 115 73 20 46 89 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE GND AP_RESET_L 14 20 14 115 87 FUNC_TEST=TRUE FUNC_TEST=TRUE A PPVCC_S0_CPU FUNC_TEST=TRUE FUNC_TEST=TRUE A 109 20 15 36 35 FUNC_TEST=TRUE FUNC_TEST=TRUE PP1V0_SSD_CORE TP-P6 TP-P6 46 29 47 FUNC_TEST=TRUE USB3_TEST_D2R_N FUNC_TEST=TRUE SSD_BOOT_LB_L SSD_BOOT_LB_L SSD_DEBUG_I2C_CLK_CONN SSD_DEBUG_I2C_DAT_CONN SMC_OOB1_R2D_L SMC_OOB1_D2R_L PP1V8_SSD_FMC A A 14 FUNC_TEST=TRUE X5 X5 X5 X4 X5 X5 A TP-P6 1 TP-P6 A 1 TP-P6 SMC_RESET_L FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 1 FUNC_TEST=TRUE SSD DEBUG CONNECTOR 115 TPAC500 TPAC501 TPAC502 TPAC503 TPAC504 TPAC505 TPAC506 TPAC507 TPAC529 TPAC512 TPAC536 TPAC518 15 101 70 12 27 76 48 20 12 35 A A A 1 TP-P6 A 1 TP-P6 A 1 TP-P6 SSD_RESET_L A 1 TP-P6 A 1 TP-P6 A PM_PCH_SYS_PWROK SSD_PWR_EN 1 TP-P6 A 1 TP-P6 SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L A 1 TP-P6 A 1 TP-P6 A 1 TP-P6 SSD_BOOT_L PM_SLP_S3_L SMC_DEV_SUPPLY_R_L A 1 TP-P6 A TP-P6 PLT_RST_L C TPAC517 TPAC538 TPAC539 TPAC527 TPAC510 TPAC511 TPAC595 TPAC596 TPAC598 TPAC597 TPAC599 TPAC525 TPAC526 TPAC537 TPAC530 TPAC531 TPAC532 TPAC533 TPAC534 TPAC508 TPAC509 TPAC513 TPAC514 TPAC515 TPAC516 FUNC_TEST=TRUE MIC FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 109 58 IN 58 IN 58 IN 58 IN 61 IN FUNC_TEST=TRUE FUNC_TEST=TRUE DMIC1_CLK DMIC1_DATA DMIC2_CLK DMIC2_DATA PP1V8_S0 GND FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE BUF_EDP_PANEL_PWR_EN DP_INT_HPD GND SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA MIPIC_DATA_P MIPIC_DATA_N USB-C PROBE BLOCK TESTING FUNC_TEST=TRUE FUNC_TEST=TRUE X3 FUNC_TEST=TRUE FUNC_TEST=TRUE 32 IN 32 IN 106 IN 106 IN TP_J3300_P2 TP_J3300_P56 TP_JB500_P2 TP_JB500_P56 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 1 1 1 1 TP-P6 TP-P6 TP-P6 TP-P6 A A A A TPAC580 TPAC581 TPAC582 TPAC583 FUNC_TEST=TRUE FUNC_TEST=TRUE ADDITIONAL TPs 110 IN PP3V3_S5 FUNC_TEST=TRUE IN PP3V3_SUS FUNC_TEST=TRUE 110 SYNC_MASTER=J80_BBABADI_MLB_BAFFIN SYNC_DATE=12/10/2015 PAGE TITLE 1 TP-P6 A 1 TP-P6 A ICT & FCT 2 TPAC584 TPAC585 DRAWING NUMBER Apple Inc. 051-00647 REVISION NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 5 4 3 2 125 OF 145 SHEET 114 OF 121 IV ALL RIGHTS RESERVED 6 10.0.0 dvt-fab10 II NOT TO REPRODUCE OR COPY IT 7 B FUNC_TEST=TRUE R 8 D (row,col)=(5,5) Diameter=0.6mm Pitch=1mm Middle - Top Layer TP3001 TP3002 TP3003 TP3004 PP20V_USBC_XA_VBUS_CONN GND A 1 TP-P6 A 1 TP-P6 A TP-P6 1 A TP-P6 1 FUNC_TEST=TRUE X2 X5 X5 A 1 FUNC_TEST=TRUE TP_UPC_XA_SWD_DATA -------------------------> TP_UPC_XA_SWD_CLK -------------------------> TP_UPC_XB_SWD_DATA -------------------------> TP_UPC_XB_SWD_CLK -------------------------> TP_UPC_TA_DBG_UART_TX 104 103 IN TP_UPC_TA_DBG_UART_RX 104 103 IN TP_UPC_TB_DBG_UART_TX 105 103 IN TP_UPC_TB_DBG_UART_RX 105 103 IN UPC_XA_DBG_UART_TX 30 29 IN UPC_XA_DBG_UART_RX 30 29 IN TP_UPC_XB_DBG_UART_TX 31 29 IN TP_UPC_XB_DBG_UART_RX 31 29 IN PP20V_USBC_TB_VBUS_CONN 116 115 106 IN PP20V_USBC_TA_VBUS_CONN 116 115 106 IN GND PP20V_USBC_XB_VBUS_CONN 116 115 32 TP-P6 A PPDCIN_G3H FUNC_TEST=TRUE 114 FUNC_TEST=TRUE FUNC_TEST=TRUE 1 FUNC_TEST=TRUE GND PPVBAT_G3H_CHGR_REG PPDCIN_G3H_CHGR FUNC_TEST=TRUE X2 SSD_DEBUG_I2C_DAT SSD_PGOOD_L FUNC_TEST=TRUE FUNC_TEST=TRUE X4 SSD_DEBUG_I2C_CLK 116 50 29 114 64 116 50 29 114 64 116 50 29 114 64 116 50 29 114 64 FUNC_TEST=TRUE SYS_DETECT_L GND SMC_LSOC_RST_L TBA_COMP TBA_VDDA TBA_LX1 TBA_LX2 FUNC_TEST=TRUE FUNC_TEST=TRUE 86 77 1 TP-P6 A 1 TP-P6 A 1 TP-P6 (row,col)=(2,6) Diameter=0.6mm Pitch=1mm Left Side - Top Layer FUNC_TEST=TRUE TP_BMON_IOUT CHGR_AMON CHGR_BMON IN 64 50 X4 SSD_JTAG_TDO TP-P6 X7 PPVBAT_G3H_CONN SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA A 80 77 86 77 X2 BATTERY TUBA FUNC_TEST=TRUE FUNC_TEST=TRUE SSD_JTAG_TCK SSD_JTAG_TDI FUNC_TEST=TRUE TPAC528 TPAC519 TPAC520 TPAC521 TPAC522 TPAC523 TPAC524 TPAC535 A 1 TP-P6 A 1 TP-P6 A 1 TP-P6 SSD_JTAG_TMS FUNC_TEST=TRUE 84 77 FUNC_TEST=TRUE 1 Wifi & SSD fixture Test Points (row,col)=(4,2) Diameter=0.6mm Pitch=1mm Right Side - Top Layer FUNC_TEST=TRUE KBD_I2C_SCL KBD_I2C_SDA KBD_INT_L SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL PP3V3_S4_TPAD PP5V_S4_TPAD_CONN ACT_GND PPVIN_S4_TPAD_FUSE TPAD_SPI_CLK TPAD_SPI_IF_EN_CONN TPAD_SPI_MISO TPAD_SPI_CS_L_CONN TPAD_SPI_MOSI TPAD_SPI_INT_L_CONN SMC_ACTUATOR_DISABLE_L SMC_PME_S4_WAKE_L SMC_LID KBD_BLC_GSLAT KBD_BLC_GSSCK KBD_BLC_GSSOUT SMC_VIBE_L KBD_BLC_GSSIN GND 2 eDP 111 DFR_DISP_VSYNC DFR_DISP_TE DFR_DISP_INT DFR_DISP_RESET_L PP3V3_S0SW_DFR MIPID_CLK_P MIPID_CLK_N MIPID_DATA_P MIPID_DATA_N PP1V8_S0SW_DFR DFRDRV_I2C_SCL DFRDRV_I2C_SDA GND FUNC_TEST=TRUE 116 FUNC_TEST=TRUE DFR Disp Conn 114 FUNC_TEST=TRUE IN IN DFR_TOUCH_LID GND FUNC_TEST=TRUE X2 TPAD CONNECTOR FUNC_TEST=TRUE FUNC_TEST=TRUE PP1V8_S0SW_DFR PP5V_S0_T139 FUNC_TEST=TRUE FUNC_TEST=TRUE 62 FUNC_TEST=TRUE DFR Touch Conn IN FUNC_TEST=TRUE FUNC_TEST=TRUE X2 X2 63 114 42 GND_FAN PP5V_S0_FAN_CONN FAN_LT_TACH FAN_LT_PWM PP5V_S0_KBD PP3V3_G3H KBD_BLC_GSSOUT KBD_BLC_GSLAT PP3V3_S4 KBD_BLC_GSSIN KBD_BLC_XBLANK FAN_RT_TACH FAN_RT_PWM KBD_I2C_SDA KBD_INT_L KBD_I2C_SCL SMC_LSOC_RST_L KBD_BLC_GSSCK GND 3 AUDIO JACK FUNC_TEST=TRUE AUDIO AMP C IN FUNC_TEST=TRUE PP3V3_G3H SPI_ALT_IO0_MOSI SPI_ALT_IO1_MISO SPI_ALT_IO2_WP_L SPI_ALT_IO3_HOLD_L SMC_RESET_L SPI_ALT_CLK SPI_ALT_CS_L SPIROM_USE_MLB SMC_TMS SMC_TCK GND IN IN 56 43 FUNC_TEST=TRUE FUNC_TEST=TRUE 43 115 FUNC_TEST=TRUE FUNC_TEST=TRUE IN 56 43 FUNC_TEST=TRUE PP1V8_MESA_CONN MESA_SPI_MOSI_CONN MENU_KEY_L MESA_SPI_CLK_CONN PP16V0_MESA_CONN GND 43 115 FUNC_TEST=TRUE SPI ROM 114 4 KBD CONNECTOR PP3V0_MESA_CONN MESA_SPI_MISO_CONN MESA_SNSR_INT_CONN MESA_BOOST_EN_CONN MESA_I2C_SDA MESA_I2C_SCL IN 5 1 SIZE D A 8 7 6 5 4 3 2 1 OTHER TEST POINTS / NC CPU NC with No Testpoint Property 13 13 13 D 113 18 12 113 18 12 13 NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP NC_HDA_SDIN1 1 NC_SPI_SMC_MOSI I1 1 NC_SPI_SMC_MISO I2 1 NC_SPI_SMC_CS_L I4 1 NC_SPI_SMC_CLK I3 1 TRUE 1 TRUE 1 TRUE 1 TRUE 1 TRUE 1 TRUE NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP NC_HDA_SDIN1 TRUE I26 TRUE I27 TRUE I28 TRUE I29 TRUE I30 TRUE 48 48 I53 TRUE I57 TRUE I56 TRUE I55 TRUE I54 TRUE I58 TRUE I62 TRUE I61 TRUE I60 TRUE I59 TRUE I63 TRUE I64 TRUE I65 TRUE I66 TRUE TP0502 CPU_DC_BR2_BR1 ----------------------------> TP0503 CPU_DC_C1_B2 -------------------------------> TP0504 CPU_DC_C38_B38 -----------------------------> TP0505 CPU_DC_BR1_BR2 -----------------------------> TP0610 CPU_DC_BR38_BT36 ---------------------------> TP0900 CPU_DC_BT36_BR38 ---------------------------> TP0901 PCH D (Refer to PCH pages) XDP_PCH_OBSDATA_A1 -------------------------> TP1884 XDP_PCH_OBSDATA_A2 -------------------------> TP1870 XDP_PCH_OBSDATA_A3 -------------------------> TP1871 XDP_PCH_OBSDATA_B0 -------------------------> TP1872 XDP_PCH_OBSDATA_B1 -------------------------> TP1885 XDP_PCH_OBSDATA_B2 -------------------------> TP1886 XDP_PCH_OBSDATA_B3 -------------------------> TP1887 XDP_PCH_OBSDATA_D0 -------------------------> TP1877 43 56 114 XDP_PCH_OBSDATA_D1 -------------------------> TP1878 43 56 114 XDP_PCH_OBSDATA_D2 -------------------------> TP1879 38 110 XDP_PCH_OBSDATA_D3 -------------------------> TP1880 43 56 114 XDP_PCH_OBSFN_C0 -------------------------> TP1882 43 56 114 XDP_BPM_L<0> -------------------------> TP1800 38 110 XDP_BPM_L<1> -------------------------> TP1801 XDP_BPM_L<2> -------------------------> TP1802 XDP_BPM_L<3> -------------------------> TP1803 NC_USB_EXTA_OC_L -------------------------> TP1873 NC_USB_EXTB_OC_L -------------------------> TP1874 NC_USB_EXTC_OC_L -------------------------> TP1875 NC_USB_EXTD_OC_L -------------------------> TP1876 20 FAN_LT_PWM FAN_LT_TACH PP5V_S0 FAN_RT_PWM FAN_RT_TACH PP5V_S0 XDP_CPU_TCK XDP_PCH_TCK XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TRST_L XDP_CPU_TMS XDP_PCH_TMS XDP_PCH_TDI XDP_PCH_TDO XDP_CPU_PREQ_L XDP_CPU_PRDY_L PM_RSMRST_L PM_PCH_PWROK PM_SYSRST_L CPU_CFG<3> ----------------------------> TP1883 115 115 XDP Test-Points TRUE CPU_DC_B38_C38 XDP_PCH_OBSDATA_A0 -------------------------> C I52 TP0501 48 FAN Test Points I25 CPU_DC_B2_C1 -------------------------------> 48 NC_PCH_CLK32K_RTCX2 I7 (Refer to CPU pages) C 6 18 13 18 6 18 TPs on BOTTOM to check USB-C Instalation 6 18 6 13 18 6 18 I75 13 18 I76 13 18 I77 13 18 I78 6 13 18 I79 6 13 18 I80 12 18 46 73 I81 12 70 I82 I83 12 18 46 6 18 I86 I85 I84 B USBC_XA_SBU1 USBC_XB_SBU1 USBC_XA_SBU2 USBC_XB_SBU2 USBC_TA_SBU1 USBC_TB_SBU1 USBC_TA_SBU2 USBC_TB_SBU2 PP20V_USBC_XA_VBUS_CONN PP20V_USBC_XB_VBUS_CONN PP20V_USBC_TA_VBUS_CONN PP20V_USBC_TB_VBUS_CONN FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 30 32 31 32 30 32 31 32 104 106 105 106 104 106 105 106 32 114 116 32 114 116 106 114 116 106 114 116 B TPs to check LifeBoat Instalation I88 I87 I90 I89 I91 I92 I93 I95 I94 I96 PP3V3_S5_POLARIS PP3V3_S5 SSD_PWR_EN SSD_PWR_LB_EN SSD_BOOT_L SSD_BOOT_LB_L SSD_RESET_L SSD_RESET_LB_L SSD_CLKREQ_L SSD_CLKREQ_LB_L FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 84 87 110 14 87 114 84 87 15 87 114 77 87 114 14 20 87 114 77 87 20 87 77 87 A SYNC_MASTER=X363_BBABADI SYNC_DATE=01/26/2016 PAGE TITLE NC & No Test DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 126 OF 145 SHEET 115 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 109 10 7 6 5 PP1V2_S3_CPUDDR 1 109 CC704 1 12PF D 25 24 23 22 CC700 1 3.0PF 12PF PP1V2_S3 109 CC701 CC706 1 3.0PF CC716 1 CRITICAL CC720 1 12PF 25 24 23 22 1 CC709 1 12PF CC710 1 12PF 5% 2 25V NP0-C0G 0201 CC711 12PF 1 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 CC712 1 CC713 1 12PF 131S00041 CC714 DESCRIPTION 6 REFERENCE DES CAP,CER,12PF,5%,100V,C0G,0402 CRITICAL BOM OPTION CRITICAL CC784,CC785,CC786,CC787,CC788 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 QTY 1 5% 2 25V NP0-C0G 0201 PP0V6_S0_DDRVTT 26 CC715 1 CC718 12PF D 1 CC719 3.0PF 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 CC721 CC722 1 12PF CC723 12PF CRITICAL CC724 1 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 CRITICAL 1 CRITICAL CC725 1 12PF 5% 2 25V NP0-C0G 0201 CC726 12PF CC727 CRITICAL CC728 1 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 CRITICAL CRITICAL 1 12PF CRITICAL CC730 1 1 12PF 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 CRITICAL CC729 1 5% 2 25V NP0-C0G 0201 CC731 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 PP1V8_S3_MEM CRITICAL 1 CRITICAL CC732 1 12PF C 110 CC750 1 12PF 110 102 1 CC735 12PF +/-0.1PF 2 25V NP0-C0G 0201 CC738 CC751 3.0PF CC736 CC768 110 3.0PF CC769 1 3.0PF +/-0.1PF 25V NP0-C0G 2 0201 0201 107 C 115 CC740 1 114 PP20V_USBC_XB_VBUS_CONN 32 1 115 12PF 1 5% 2 25V NP0-C0G 0201 5% 25V 2 NP0-C0G 0201 114 106 115 CC742 1 3.0PF +/-0.1PF 25V 2 NP0-C0G 0201 PP3V3_S5 1 1 3.0PF +/-0.1PF 25V NP0-C0G 2 0201 CC754 CC741 1 3.0PF 12PF +/-0.1PF 25V NP0-C0G 2 0201 5% 2 25V NP0-C0G 5% 25V 2 NP0-C0G 0201 PP3V3_TBT_T_S0 1 12PF 12PF +/-0.1PF 25V NP0-C0G 2 0201 CC737 PP0V9_TBT_X_SVR 1 CC767 CRITICAL 1 12PF 28 CC739 1 CRITICAL 1 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 PP3V3_TBT_X_S0 29 28 +/-0.1PF 2 25V NP0-C0G 0201 103 CRITICAL CC734 3.0PF 3.0PF 5% 2 25V NP0-C0G 0201 PP0V9_TBT_T_SVR 1 5% 2 25V NP0-C0G 0201 PP3V3_S5 1 CRITICAL CC733 12PF 5% 2 25V NP0-C0G 0201 102 CRITICAL CRITICAL 1 12PF 5% 2 25V NP0-C0G 0201 33 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 CC708 12PF +/-0.1PF 2 25V NP0-C0G 0201 12PF 3.0PF CRITICAL 110 1 PART NUMBER 1 3.0PF 2 PP1V2_S3 1 109 CC717 3 PPVCCGT_S0_CPU 11 CC703 1 +/-0.1PF 2 25V NP0-C0G 0201 109 5% 2 25V NP0-C0G 0201 25 24 23 22 CC702 3.0PF 5% 2 25V NP0-C0G 0201 PP0V6_S0_DDRVTT 26 12PF 109 1 CC707 12PF 5% 2 25V NP0-C0G 0201 CRITICAL 1 1 12PF +/-0.1PF 2 25V NP0-C0G 0201 +/-0.1PF 25V 2 NP0-C0G 0201 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 109 1 CC705 4 CC743 12PF +/-0.1PF 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 CC744 1 1 12PF CC745 5% 2 25V NP0-C0G 0201 1 12PF +/-0.1PF 2 25V NP0-C0G 0201 5% 25V 2 NP0-C0G 0201 5% 2 25V NP0-C0G 0201 1 3.0PF CC758 1 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 115 CC759 1 3.0PF 1 CC756 1 12PF 12PF CC757 1 12PF 5% 25V 2 NP0-C0G 0201 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 CC760 114 106 34 29 1 CC763 1 CC761 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 1 12PF CC753 12PF 5% 2 25V NP0-C0G 0201 1 PP5V_S4_X_USBC 116 CRITICAL CC748 5% 2 25V NP0-C0G 0201 PP20V_USBC_TA_VBUS_CONN 12PF 5% 2 25V NP0-C0G 0201 CC747 3.0PF PP20V_USBC_TB_VBUS_CONN CC755 PP20V_USBC_XA_VBUS_CONN 32 CC746 1 12PF 114 108 103 CC762 12PF 1 CC765 5% 2 25V NP0-C0G 0201 34 PPBUS_G3H CRITICAL 1 CC752 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 116 109 108 34 PPBUS_G3H CRITICAL CRITICAL 1 CC749 12PF 3.0PF CRITICAL 12PF 5% 2 25V NP0-C0G 0201 108 CRITICAL PP5V_S4_T_USBC 1 109 CC766 1 CC764 12PF 3.0PF 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 B B 110 100 PP1V8_GPU 2.4G DESENSE 114 1 CC770 12PF 5% 2 25V NP0-C0G 0201 110 94 1 CC7715G 64 50 29 PPDCIN_G3H CRITICAL DESENSE 3.0PF 1 CRITICAL CC772 12PF +/-0.1PF 2 25V NP0-C0G 0201 CC773 1 3.0PF 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL CC774 1 12PF 5% 25V 2 NP0-C0G 0201 CC779 12PF 5% 2 25V NP0-C0G 0201 NO_STUFF 1 CC780 12PF 5% 2 25V NP0-C0G 0201 NO_STUFF 1 CC781 12PF 5% 2 25V NP0-C0G 0201 NO_STUFF 1 CC782 12PF 5% 2 25V NP0-C0G 0201 NO_STUFF 1 CC783 114 64 63 PPDCIN_G3H_CHGR 12PF 114 1 5% 2 25V NP0-C0G 0201 76 75 55 CC775 3.0PF CRITICAL CC776 1 12PF +/-0.1PF 2 25V NP0-C0G 0201 CC777 12PF 5% 2 25V NP0-C0G 0201 5% 25V 2 NP0-C0G 0201 CRITICAL 1 CC778 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 PPVOUT_S0_LCDBKLT NOSTUFF CC784 1 12PF PP1V8_S0_GPU 109 64 2 12PF 2% 100V CERM 0402 2 CC787 1 12PF 2 2% 100V CERM 0402 12PF 2 OMIT_TABLE 1 CC788 CC70A 12PF 2% 100V CERM 0402 2 5% 100V CERM 0402 OMIT_TABLE SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/15/2016 PAGE TITLE 1 CC790 12PF 5% 2 25V NP0-C0G 0201 2% 100V CERM 0402 1 12PF OMIT_TABLE CRITICAL CC789 NOSTUFF CC786 1 PPBUS_G3H NO_STUFF 1 CC785 12PF 2% 2 100V CERM 0402 OMIT_TABLE 110 CRITICAL 1 PP1V5R1V35_S0_GPU_MEM 1 A CRITICAL 1 5% 2 25V NP0-C0G 0201 CRITICAL 1 CC791 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL 1 CC792 12PF 5% 2 25V NP0-C0G 0201 CRITICAL 1 CC793 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL 1 CC794 12PF 5% 2 25V NP0-C0G 0201 CRITICAL 1 CC795 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL 1 CC796 12PF 5% 2 25V NP0-C0G 0201 CRITICAL 1 CC797 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL 1 CC798 12PF 5% 2 25V NP0-C0G 0201 Desense Caps CRITICAL 1 DRAWING NUMBER CC799 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=WIRELESS WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 127 OF 145 SHEET 116 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 1 SIZE D A 8 110 7 PP5V_S0 56 43 PP0V6_SLEEP1_BUCK0 41 39 1 CC800 1 12PF D PPBUS_HS_CPU CRITICAL CC805 12PF 3.0PF 5% 2 25V NP0-C0G 0201 109 69 CC806 1 +/-0.1PF 2 25V NP0-C0G 0201 PPBUS_HS_OTH5V 1 1 12PF 69 71 CRITICAL 1 CC812 CC814 12PF 74 71 109 CRITICAL 1 3.0PF 5% 2 25V NP0-C0G 0201 CC804 5% 2 25V NP0-C0G 0201 CC809 1 D CRITICAL CC810 1 12PF +/-0.1PF 2 25V NP0-C0G 0201 CC811 3.0PF 5% 25V 2 NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 1 PP1V2_S3 109 CRITICAL 1 1 12PF PP0V6_S0_DDRVTT 71 CRITICAL CC816 1 12PF 5G DESENSE CC818 2.4G DESENSE PPVCCIO_S0_CPU CRITICAL CC819 1 3.0PF 2.4G DESENSE C CRITICAL 1 CC830 1 12PF 69 74 PP5V_S0 1 +/-0.1PF 2 25V NP0-C0G 0201 PP5V_S4 NOSTUFF +/-0.1PF 2 25V NP0-C0G 0201 50 PPBUS_HS_OTH3V3 CRITICAL 1 72 PP1V8_SUS 110 CRITICAL 1 CC820 12PF 72 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 2.4G DESENSE 5G DESENSE CC824 12PF 5% 2 25V NP0-C0G 0201 2.4G DESENSE CRITICAL 1 CC825 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 1 CC838 12PF 5% 2 25V NP0-C0G 0201 5G DESENSE C CC834 +/-0.1PF 2 25V NP0-C0G 0201 110 69 PP3V3_S5 NOSTUFF 1 CC836 5% 2 25V NP0-C0G 0201 CRITICAL 1 CC826 12PF CC837 12PF 110 1 3.0PF 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 PP1V0_SUS CC821 5% 2 25V NP0-C0G 0201 3.0PF 5% 2 25V NP0-C0G 0201 CRITICAL CC823 CRITICAL 1 12PF CRITICAL 1 CC833 NOSTUFF 1 CC835 5% 2 25V NP0-C0G 0201 109 CRITICAL 1 CRITICAL 12PF B CC832 3.0PF 109 1 CRITICAL NOSTUFF CRITICAL CC831 3.0PF 5% 2 25V NP0-C0G 0201 NOSTUFF 110 110 CRITICAL CC822 5% 2 25V NP0-C0G 0201 5G DESENSE NOSTUFF CRITICAL 12PF +/-0.1PF 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 2.4G DESENSE 71 CRITICAL 1 12PF 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 109 CRITICAL CC817 1 3.0PF 5% 25V 2 NP0-C0G 0201 PP3V3_S4 1 5% 25V 2 NP0-C0G 0201 PP1V2_S3 74 2 PPBUS_HS_OTH3V3 CRITICAL 110 3 12PF CRITICAL CC808 12PF +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL CC813 12PF CC815 CC803 +/-0.1PF 2 25V NP0-C0G 0201 3.0PF 5% 2 25V NP0-C0G 0201 109 4 NOSTUFF 1 3.0PF CRITICAL CC807 5% 2 25V NP0-C0G 0201 109 CC802 5% 25V 2 NP0-C0G 0201 CRITICAL 1 NOSTUFF 1 12PF +/-0.1PF 2 25V NP0-C0G 0201 CRITICAL 1 CC801 1 5 GND_AUDIO_CODEC 59 3.0PF 5% 2 25V NP0-C0G 0201 109 6 PP5V_S0 110 CRITICAL 1 CC827 3.0PF +/-0.1PF 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 +/-0.1PF 2 25V NP0-C0G 0201 5G DESENSE 2.4G DESENSE 5G DESENSE 1 B PP3V3_S5 CC828 1 12PF CC829 12PF 5% 2 25V NP0-C0G 0201 5% 2 25V NP0-C0G 0201 A SYNC_MASTER=DESENSE SYNC_DATE=05/18/2016 PAGE TITLE Desense Caps DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT BOM_COST_GROUP=WIRELESS WWW.AliSaler.Com 8 7 6 5 4 3 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 128 OF 145 SHEET 117 OF 121 IV ALL RIGHTS RESERVED 2 10.0.0 1 SIZE D A 8 7 6 5 4 3 2 1 D D C C B B A SYNC_MASTER=X363_ZIFENGSHEN PAGE TITLE SYNC_DATE=06/02/2016 Project Specific Constraints DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 130 OF 145 SHEET 118 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 7 6 5 BOM Variants 44 ULA Configs 4 3 2 1 36 PROA Configs TABLE_BOMGROUP_HEAD D C B BOM NUMBER BOM NAME BOM OPTIONS 639-02212 MLB,2.6G,MC-16,ULA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02120 MLB,2.6G,MC-16,ULA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02591 MLB,2.6G,MC-16,ULA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-02214 MLB,2.6G,MC-16,ULA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-02587 MLB,2.6G,SM-16,ULA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02116 MLB,2.6G,SM-16,ULA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02589 MLB,2.6G,SM-16,ULA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-02586 MLB,2.6G,SM-16,ULA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01615 MLB,2.7G,MC-16,ULA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02592 MLB,2.7G,MC-16,ULA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01614 MLB,2.7G,MC-16,ULA-MC,SSD-512,X36G3 BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01603 MLB,2.7G,SM-16,ULA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02594 MLB,2.7G,SM-16,ULA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01602 MLB,2.7G,SM-16,ULA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01639 MLB,2.9G,MC-16,ULA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-01637 MLB,2.9G,MC-16,ULA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02596 MLB,2.9G,MC-16,ULA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01638 MLB,2.9G,MC-16,ULA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01627 MLB,2.9G,SM-16,ULA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-01625 MLB,2.9G,SM-16,ULA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02598 MLB,2.9G,SM-16,ULA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01626 MLB,2.9G,SM-16,ULA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_MC_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-02154 MLB,2.6G,MC-16,ULA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02119 MLB,2.6G,MC-16,ULA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02590 MLB,2.6G,MC-16,ULA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-02213 MLB,2.6G,MC-16,ULA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-02211 MLB,2.6G,SM-16,ULA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02115 MLB,2.6G,SM-16,ULA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02588 MLB,2.6G,SM-16,ULA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-02585 MLB,2.6G,SM-16,ULA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01612 MLB,2.7G,MC-16,ULA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02593 MLB,2.7G,MC-16,ULA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01611 MLB,2.7G,MC-16,ULA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01600 MLB,2.7G,SM-16,ULA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-02595 MLB,2.7G,SM-16,ULA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01599 MLB,2.7G,SM-16,ULA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB 639-01636 MLB,2.9G,MC-16,ULA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-01634 MLB,2.9G,MC-16,ULA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02597 MLB,2.9G,MC-16,ULA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01635 MLB,2.9G,MC-16,ULA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM BOM NUMBER BOM NAME BOM OPTIONS 639-02655 MLB,2.7G,MC-16,PROA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02656 MLB,2.7G,MC-16,PROA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02654 MLB,2.7G,MC-16,PROA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02664 MLB,2.7G,SM-16,PROA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02665 MLB,2.7G,SM-16,PROA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02663 MLB,2.7G,SM-16,PROA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02673 MLB,2.9G,MC-16,PROA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02674 MLB,2.9G,MC-16,PROA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02672 MLB,2.9G,MC-16,PROA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02682 MLB,2.9G,SM-16,PROA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02683 MLB,2.9G,SM-16,PROA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02681 MLB,2.9G,SM-16,PROA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02652 MLB,2.7G,MC-16,PROA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02653 MLB,2.7G,MC-16,PROA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02651 MLB,2.7G,MC-16,PROA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02661 MLB,2.7G,SM-16,PROA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02662 MLB,2.7G,SM-16,PROA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02660 MLB,2.7G,SM-16,PROA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02670 MLB,2.9G,MC-16,PROA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02671 MLB,2.9G,MC-16,PROA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02669 MLB,2.9G,MC-16,PROA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02679 MLB,2.9G,SM-16,PROA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02680 MLB,2.9G,SM-16,PROA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02678 MLB,2.9G,SM-16,PROA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02649 MLB,2.7G,MC-16,PROA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02650 MLB,2.7G,MC-16,PROA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02648 MLB,2.7G,MC-16,PROA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02658 MLB,2.7G,SM-16,PROA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02659 MLB,2.7G,SM-16,PROA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02657 MLB,2.7G,SM-16,PROA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.7,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02667 MLB,2.9G,MC-16,PROA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02668 MLB,2.9G,MC-16,PROA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02666 MLB,2.9G,MC-16,PROA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB 639-02676 MLB,2.9G,SM-16,PROA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:1TB 639-02677 MLB,2.9G,SM-16,PROA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:2TB 639-02675 MLB,2.9G,SM-16,PROA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_PROA,SSD_CONFIG:512GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM B TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-01624 MLB,2.9G,SM-16,ULA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:1TB 639-01622 MLB,2.9G,SM-16,ULA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:256GB 639-02599 MLB,2.9G,SM-16,ULA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:2TB 639-01623 MLB,2.9G,SM-16,ULA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,BAFFIN_ULA,SSD_CONFIG:512GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM A SYNC_MASTER=J80_MLB PAGE TITLE BOM Variants, Power/Socket Configs 639 BOM Configuration DRAWING NUMBER Apple Inc. TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME SYNC_DATE=07/23/2015 BOM OPTIONS 051-00647 REVISION R TABLE_BOMGROUP_ITEM 639-01966 PCBA,MLB,NONE,SM-16,FB4-SM,S256,X363 BASE_BOM,DEVEL_BOM,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,SSD_CONFIG:256GB 639-01967 PCBA,MLB,SKT,VDDC,SM-16,FB4-SM,S256,X363 BASE_BOM,DEVEL_BOM,STARDUST:VDDC,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,SSD_CONFIG:256GB 639-01968 639-01969 PCBA,MLB,SKT,MVDD,SM-16,FB4-SM,S256,X363 PCBA,MLB,SKT,CPU,SM-16,FB4-SM,S256,X363 NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM BASE_BOM,DEVEL_BOM,STARDUST:VDDCI_MVDD,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,SSD_CONFIG:256GB I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT TABLE_BOMGROUP_ITEM BASE_BOM,DEVEL_BOM,CPU_SKL:SOCKET,RAM_16G_SAMSUNG_2133,4GB_SM_BAFFIN,SSD_CONFIG:256GB III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 141 OF 145 SHEET 119 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 7 6 5 4 3 2 1 BOM Variants 48 LEA Configs TABLE_BOMGROUP_HEAD D C B BOM NUMBER BOM NAME BOM OPTIONS 639-02621 MLB,2.6G,MC-16,LEA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02618 MLB,2.6G,MC-16,LEA-HY,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02622 MLB,2.6G,MC-16,LEA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02620 MLB,2.6G,MC-16,LEA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-02608 MLB,2.6G,SM-16,LEA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02602 MLB,2.6G,SM-16,LEA-HY,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02611 MLB,2.6G,SM-16,LEA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02605 MLB,2.6G,SM-16,LEA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02645 MLB,2.9G,MC-16,LEA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02643 MLB,2.9G,MC-16,LEA-HY,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02646 MLB,2.9G,MC-16,LEA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02644 MLB,2.9G,MC-16,LEA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02633 MLB,2.9G,SM-16,LEA-HY,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02631 MLB,2.9G,SM-16,LEA-HY,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02634 MLB,2.9G,SM-16,LEA-HY,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02632 MLB,2.9G,SM-16,LEA-HY,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_HY_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02647 MLB,2.6G,MC-16,LEA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02616 MLB,2.6G,MC-16,LEA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02619 MLB,2.6G,MC-16,LEA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02617 MLB,2.6G,MC-16,LEA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02607 MLB,2.6G,SM-16,LEA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02601 MLB,2.6G,SM-16,LEA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02610 MLB,2.6G,SM-16,LEA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02604 MLB,2.6G,SM-16,LEA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02641 MLB,2.9G,MC-16,LEA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02639 MLB,2.9G,MC-16,LEA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02642 MLB,2.9G,MC-16,LEA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02640 MLB,2.9G,MC-16,LEA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02629 MLB,2.9G,SM-16,LEA-MC,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02627 MLB,2.9G,SM-16,LEA-MC,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02630 MLB,2.9G,SM-16,LEA-MC,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02628 MLB,2.9G,SM-16,LEA-MC,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_MC_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02614 MLB,2.6G,MC-16,LEA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02612 MLB,2.6G,MC-16,LEA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02615 MLB,2.6G,MC-16,LEA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02613 MLB,2.6G,MC-16,LEA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02606 MLB,2.6G,SM-16,LEA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02600 MLB,2.6G,SM-16,LEA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02609 MLB,2.6G,SM-16,LEA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM B TABLE_BOMGROUP_ITEM 639-02603 MLB,2.6G,SM-16,LEA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.6,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02637 MLB,2.9G,MC-16,LEA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02635 MLB,2.9G,MC-16,LEA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02638 MLB,2.9G,MC-16,LEA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02636 MLB,2.9G,MC-16,LEA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_MICRON_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB 639-02625 MLB,2.9G,SM-16,LEA-SM,SSD-1TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:1TB 639-02623 MLB,2.9G,SM-16,LEA-SM,SSD-256,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:256GB 639-02626 MLB,2.9G,SM-16,LEA-SM,SSD-2TB,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:2TB 639-02624 MLB,2.9G,SM-16,LEA-SM,SSD-512,X363G BASE_BOM,DEVEL_BOM,CPU_SKL:2.9,RAM_16G_SAMSUNG_2133,2GB_SM_BAFFIN,BAFFIN_LEA,SSD_CONFIG:512GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM A SYNC_MASTER=J80_MLB PAGE TITLE SYNC_DATE=07/23/2015 639 BOM Configuration 2 DRAWING NUMBER Apple Inc. 051-00647 REVISION R NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 142 OF 145 SHEET 120 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A 8 7 6 5 4 3 2 1 Alternate Parts TABLE_ALT_HEAD TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 311S0271 197S00046 BOM OPTION REF DES COMMENTS: 311S00008 ALL NXP w/ Diodes 197S00036 ALL Epson w/ TXC TABLE_ALT_ITEM 740S0144 740S0118 TABLE_ALT_ITEM ALL PART NUMBER ALTERNATE FOR PART NUMBER <rdar://problem/23117904> for IG <rdar://problem/24316367> for EG 311S00013 <rdar://problem/23117749> for IG <rdar://problem/23543146> for EG 311S00118 BOM OPTION REF DES COMMENTS: 311S0508 ALL Part will be stuffed in production 311S0489 ALL (Stale; delete later after page sync) TABLE_ALT_ITEM <rdar://problem/24316400> TABLE_ALT_ITEM 740S00003 740S0135 TABLE_ALT_ITEM ALL TABLE_ALT_ITEM <rdar://problem/27623384> TABLE_ALT_ITEM 376S1089 376S1128 TABLE_ALT_ITEM ALL 197S00047 197S00036 ALL TABLE_ALT_ITEM Kyocera w/ TXC 311S00072 311S0657 ALL <rdar://problem/23595055> TABLE_ALT_ITEM 376S1080 376S0820 TABLE_ALT_ITEM ALL 197S00048 197S00036 ALL TABLE_ALT_ITEM Murata w/ TXC 311S00090 311S00028 ALL <rdar://problem/23602138> D TABLE_ALT_ITEM D 376S00086 376S0761 TABLE_ALT_ITEM ALL 197S00053 197S00050 ALL <rdar://problem/23117849> for IG <rdar://problem/23543858> for EG Kyocera w/ TXC TABLE_ALT_ITEM 353S00750 353S00877 ALL 353S00878 353S00599 ALL <rdar://problem/23545068> TABLE_ALT_ITEM 376S00074 376S0855 ALL 376S00014 376S0761 ALL TABLE_ALT_ITEM 197S00054 197S00050 ALL TABLE_ALT_ITEM NDK w/ TXC <rdar://problem/23545040> TABLE_ALT_ITEM TABLE_ALT_ITEM 197S00055 197S00050 ALL TABLE_ALT_ITEM Murata w/ TXC 311S00105 311S0233 ALL <rdar://problem/24316381> TABLE_ALT_ITEM 372S0186 372S0185 TABLE_ALT_ITEM ALL 311S0596 311S0593 ALL <rdar://problem/23118093> for IG <rdar://problem/23544024> for EG NXP w/ Diodes TABLE_ALT_ITEM 353S00880 353S3452 ALL <rdar://problem/23545099> TABLE_ALT_ITEM 371S0713 371S0558 TABLE_ALT_ITEM ALL 107S0276 107S00020 ALL Cyntec w/ TFT TABLE_ALT_ITEM 311S00060 311S0273 TABLE_ALT_ITEM ALL 107S00021 107S0284 ALL TFT w/ Yageo <rdar://problem/23117951> for IG <rdar://problem/23542980> for EG <rdar://problem/23129685> for IG <rdar://problem/23519943> for EG TABLE_ALT_ITEM 311S00007 311S0426 ALL <rdar://problem/23597412> TABLE_ALT_ITEM 128S0445 128S0392 ALL <rdar://problem/23566873> TABLE_ALT_ITEM 311S00004 311S0370 TABLE_ALT_ITEM ALL 132S00012 132S0401 ALL <rdar://problem/23118402> for IG <rdar://problem/23527525> for EG Taiyo w/ Murata&TDK TABLE_ALT_ITEM 152S00415 ALL 152S00140 <rdar://problem/23766197> TABLE_ALT_ITEM 155S0914 155S0897 TABLE_ALT_ITEM ALL 152S00343 152S1682 ALL <rdar://problem/23541694> for IG <rdar://problem/23541871> for EG NXP w/ Diodes TABLE_ALT_ITEM 128S0436 ALL 128S0392 <rdar://problem/23566873> TABLE_ALT_ITEM 155S0694 155S0387 TABLE_ALT_ITEM ALL 107S00087 107S00029 ALL TFT w/ Yageo <rdar://problem/23121290> for IG <rdar://problem/23520039> for EG 343S00135 343S00136 ALL T208 <rdar://problem/23363718> for IG <rdar://problem/23526361> for EG 343S00137 343S00136 ALL T208 343S00138 343S00136 ALL T208 138S00105 138S00037 ALL TABLE_ALT_ITEM TABLE_ALT_ITEM 155S0660 155S0513 ALL 155S00154 155S0398 ALL TABLE_ALT_ITEM 128S00057 128S00018 ALL NEC w/ Vishay 128S00058 128S00018 ALL NEC w/ Rohm 128S0364 128S0264 ALL Kemet w/ Panasonic TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 155S00007 155S0667 ALL 138S0863 138S0853 ALL TABLE_ALT_ITEM <rdar://problem/23366105> for IG <rdar://problem/23527232> for EG TABLE_ALT_ITEM <rdar://problem/23640133> TABLE_ALT_ITEM TABLE_ALT_ITEM 138S0641 138S0700 ALL <rdar://problem/23118759> for IG <rdar://problem/23528188> for EG Murata w/ SS&Taiyo TABLE_ALT_ITEM 152S00434 152S1829 ALL <rdar://problem/23825631> TABLE_ALT_ITEM 138S0775 138S0860 <rdar://problem/23155097> for IG <rdar://problem/23564467> for EG ALL TABLE_ALT_ITEM 138S0739 138S0706 ALL <rdar://problem/23118915> for IG <rdar://problem/23528364 for EG NEC w/ Vishay TABLE_ALT_ITEM 353S3527 353S3528 ALL <rdar://problem/24492801> TABLE_ALT_ITEM 138S0703 138S0648 <rdar://problem/23118804> for IG <rdar://problem/> for EG ALL TABLE_ALT_ITEM 138S0945 138S0706 ALL TABLE_ALT_ITEM NEC w/ Rohm 353S3526 353S3528 ALL <rdar://problem/24492801> TABLE_ALT_ITEM 132S00064 132S0409 TABLE_ALT_ITEM ALL 152S00358 152S00208 ALL <rdar://problem/23119390> for IG <rdar://problem/23542069> for EG Murata w/ Chillisin TABLE_ALT_ITEM 353S00135 353S00034 ALL <rdar://problem/24534121> TABLE_ALT_ITEM 128S0325 128S0397 TABLE_ALT_ITEM ALL 152S00389 152S00241 OFF <rdar://problem/23342644> for IG <rdar://problem/> for EG Cyntec w/ Vishay TABLE_ALT_ITEM 353S2220 353S00034 ALL <rdar://problem/24534121> TABLE_ALT_ITEM 128S00029 C 128S00007 TABLE_ALT_ITEM ALL 152S00390 152S00265 OFF <rdar://problem/23342719> for IG <rdar://problem/> for EG Cyntec w/ Vishay TABLE_ALT_ITEM 353S00769 353S4398 ALL <rdar://problem/24534714> C TABLE_ALT_ITEM 128S00026 128S00011 ALL 128S00070 128S00007 ALL TABLE_ALT_ITEM 152S00400 152S1872 ALL Murata w/ Cyntec 152S1872 152S00361 ALL Murata w/ Cyntec TABLE_ALT_ITEM 353S00879 353S00754 ALL 104S00012 155S0398 ALL <rdar://problem/23545080> TABLE_ALT_ITEM TABLE_ALT_ITEM <rdar://problem/25329164> <rdar://problem/23132240> for IG <rdar://problem/23542412> for EG TABLE_ALT_ITEM <rdar://problem/25180014> TABLE_ALT_ITEM 128S00009 128S00007 TABLE_ALT_ITEM ALL 155S00034 155S0706 ALL <rdar://problem/23118020> for IG <rdar://problem/23543018> for EG Taiyo w/ Murata TABLE_ALT_ITEM 353S4342 353S00854 ALL <rdar://problem/23621422> TABLE_ALT_ITEM 107S0249 107S0251 ALL 107S00071 107S00053 ALL TABLE_ALT_ITEM 152S00543 152S00484 ALL <rdar://problem/24780681> TABLE_ALT_ITEM TABLE_ALT_ITEM 371S00082 371S00046 ALL <rdar://problem/23341512> for IG <rdar://problem/23545301> for EG On-Semi w/ Diodes TABLE_ALT_ITEM 371S00089 371S00085 ALL <rdar://problem/24806090> TABLE_ALT_ITEM 107S00070 107S0085 TABLE_ALT_ITEM ALL 376S00146 376S1061 ALL <rdar://problem/23341674> for IG <rdar://problem/23545469> for EG NXP w/ Diodes TABLE_ALT_ITEM 107S00111 107S00110 ALL <rdar://problem/24968171> TABLE_ALT_ITEM 107S00033 107S00034 BLC ALL TABLE_ALT_ITEM 353S00711 353S2073 ALL <rdar://problem/23605939> for IG <rdar://problem/23605957> for EG On Semi w/ TI TABLE_ALT_ITEM 335S00213 335S0888 ALL <rdar://problem/24985900> TABLE_ALT_ITEM 107S00015 107S00011 ALL 376S1106 376S0678 ALL TABLE_ALT_ITEM TABLE_ALT_ITEM Fairchild alt to Vishay BLC 311S0437 311S00112 ALL <rdar://problem/24747570> TABLE_ALT_ITEM 740S00019 740S00007 ALL <rdar://problem/23137505> for IG <rdar://problem/23545479> for EG Bourns w/ Polytronics TABLE_ALT_ITEM 377S0178 377S00031 ALL <rdar://problem/25118595> TABLE_ALT_ITEM 138S0738 138S1101 ALL TABLE_ALT_ITEM Samsung alt to Murata 155S00189 155S0342 ALL <rdar://problem/23117986> for IG <rdar://problem/23543015> for EG Murata w/ Taiyo TABLE_ALT_ITEM 371S00091 371S00083 ALL <rdar://problem/24827333> TABLE_ALT_ITEM 138S0846 138S0811 ALL TABLE_ALT_ITEM Samsung alt to Murata 132S0438 132S0428 ALL <rdar://problem/23118548> for IG <rdar://problem/23527609> for EG Murata w/ Taiyo&TDK TABLE_ALT_ITEM 197S00069 197S00068 ALL <rdar://problem/24473517> TABLE_ALT_ITEM 376S1053 376S0604 ALL TABLE_ALT_ITEM Diodes alt to Fairchild 138S0714 138S0713 ALL <rdar://problem/23118842> for IG <rdar://problem/23528300> for EG Murata w/ Samsung TABLE_ALT_ITEM 138S0698 138S00113 ALL <rdar://problem/23528153> TABLE_ALT_ITEM 152S00359 152S00253 ALL TABLE_ALT_ITEM Chillisin alt to Cyntec 138S0715 138S0732 ALL <rdar://problem/23118873> for IG <rdar://problem/23528349> for EG Murata w/ Samsung TABLE_ALT_ITEM 152S00461 152S00112 ALL <rdar://problem/24417973> TABLE_ALT_ITEM 740S00027 740S0159 ALL TABLE_ALT_ITEM Bourns alt to Little Fuse 107S00086 107S00056 ALL <rdar://problem/23121312> for IG <rdar://problem/23520074> for EG TFT w/ Cyntec TABLE_ALT_ITEM 371S00074 371S0602 ALL <rdar://problem/25919460> TABLE_ALT_ITEM 371S0704 371S00077 ALL TABLE_ALT_ITEM NXP alt to Diodes 138S0875 138S0678 ALL Taiyo w/ Mur&SS <rdar://problem/23129763> for IG <rdar://problem/23528106> for EG 197S00082 197S00081 ALL <rdar://problem/23129934> for IG <rdar://problem/23528216> for EG 353S00991 353S00920 ALL <rdar://problem/23132624> for IG <rdar://problem/23543045> for EG 131S00134 131S00041 ALL TABLE_ALT_ITEM TABLE_ALT_ITEM 138S00032 138S0831 ALL 138S00049 138S0831 ALL TABLE_ALT_ITEM 138S0786 138S0705 ALL Murata w/ Samsung 155S0382 155S0659 ALL Murata w/ TDK TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM <rdar://problem/24316117> TABLE_ALT_ITEM B 152S2052 152S1954 ALL B <rdar://problem/23135833> for IG <rdar://problem/23542478> for EG Taiyo w/ Cyntec TABLE_ALT_ITEM 220uF 2.0V D-case, 128S00044 DQ 152S2015 152S1958 ALL Taiyo w/ Cyntec T208 128S00055 128S00002 ALL Kemet w/ Panasonic <rdar://problem/23137154> for IG <rdar://problem/23542579> for EG TABLE_ALT_ITEM 998-04070 998-04071 OFF TABLE_ALT_ITEM Hynix alt to SS <rdar://problem/23148659> for IG <rdar://problem/23526236> for EG TABLE_ALT_ITEM 128S00010 128S00011 TABLE_ALT_ITEM ALL 138S0748 138S0751 ALL Murata w/ SS 138S00102 138S0773 ALL Murata w/ Taiyo 138S0789 138S0941 ALL Murata w/ SS <rdar://problem/23155052> for IG <rdar://problem/23528417> for EG TABLE_ALT_ITEM 128S00031 128S00011 TABLE_ALT_ITEM ALL <rdar://problem/23155089> for IG <rdar://problem/23529046> for EG TABLE_ALT_ITEM 138S00084 138S00060 <rdar://problem/23118634> for IG <rdar://problem/23527737> for EG ALL TABLE_ALT_ITEM <rdar://problem/23155132> for IG <rdar://problem/23529142> for EG TABLE_ALT_ITEM 155S00155 155S0441 TABLE_ALT_ITEM OFF (Stale; delete later after page sync) 107S00101 107S00005 ALL Cyntec w/ Yageo 107S00102 107S00017 ALL Cyntec w/ Yageo 107S00100 107S00057 ALL Cyntec w/ TFT 107S00103 107S00058 ALL Cyntec w/ Yageo 107S00104 107S00061 ALL Cyntec w/ Yageo <rdar://problem/23193801> for IG <rdar://problem/23519872> for EG TABLE_ALT_ITEM 155S00190 155S0897 TABLE_ALT_ITEM ALL <rdar://problem/23194019> for IG <rdar://problem/23519914> for EG TABLE_ALT_ITEM 353S00107 353S3239 TABLE_ALT_ITEM ALL <rdar://problem/23224358> for IG <rdar://problem/23520119> for EG TABLE_ALT_ITEM 353S00525 353S4471 TABLE_ALT_ITEM ALL <rdar://problem/23228523> for IG <rdar://problem/23520163> for EG TABLE_ALT_ITEM 376S1193 376S00037 TABLE_ALT_ITEM OFF <rdar://problem/23229217> for IG <rdar://problem/23520193> for EG TABLE_ALT_ITEM 740S00028 740S0118 TABLE_ALT_ITEM ALL 107S00105 107S00062 ALL Cyntec w/ Yageo 152S00403 152S00322 ALL Murata w/ Chillisin <rdar://problem/23230371> for IG <rdar://problem/23520241> for EG TABLE_ALT_ITEM 152S00369 152S00268 ALL <rdar://problem/23405116> for IG <rdar://problem/23542193> for EG Cyntec w/ NEC TABLE_ALT_ITEM <rdar://problem/23341061> for IG <rdar://problem/23542282> for EG TABLE_ALT_ITEM 128S0296 128S0487 ALL NEC w/ pana <rdar://problem/23422212> for IG <rdar://problem/23527282> for EG 353S00852 353S4262 ALL <rdar://problem/23446936> for IG <rdar://problem/23542939> for EG 138S00104 138S0978 ALL TABLE_ALT_ITEM <rdar://problem/23341158> for IG <rdar://problem/23542282> for EG TI w/ OnSemi TABLE_ALT_ITEM 128S00012 128S0487 ALL NEC w/ Rohm 155S00188 155S0275 ALL Murata w/ Taiyo TABLE_ALT_ITEM TABLE_ALT_ITEM <rdar://problem/23583487> TABLE_ALT_ITEM 155S00018 155S0664 ALL <rdar://problem/23447549> for IG <rdar://problem/23543068> for EG Murata w/ Taiyo TABLE_ALT_ITEM 128S00069 128S00067 ALL 150uF 6.3V B12 Rohm for Panasonic <rdar://problem/23527054> TABLE_ALT_ITEM A 152S00388 152S00182 TABLE_ALT_ITEM ALL <rdar://problem/23542023> 138S0759 138S0762 ALL <rdar://problem/23582324> TABLE_ALT_ITEM 107S0240 107S0255 ALL 128S00062 128S00067 ALL TABLE_ALT_ITEM <rdar://problem/23520324> 377S0077 377S0183 SYNC_MASTER=J80_MLB ALL <rdar://problem/23640745> PAGE TITLE TABLE_ALT_ITEM 150uF 6.3V B12 NEC for Panasonic TABLE_ALT_ITEM 152S00363 152S00048 ALL <rdar://problem/23541533> SYNC_DATE=12/13/2015 Alternates BOM Table TABLE_ALT_ITEM 138S0660 138S0684 DRAWING NUMBER TABLE_ALT_ITEM ALL <rdar://problem/24316249> 138S00111 138S00036 ALL <rdar://problem/23546425> Apple Inc. TABLE_ALT_ITEM 155S00204 155S0731 TABLE_ALT_ITEM ALL <rdar://problem/24310837> 138S00097 138S0750 ALL <rdar://problem/23581953> 051-00647 REVISION R TABLE_ALT_ITEM 155S00203 155S0894 ALL 116S00006 116S0175 ALL <rdar://problem/24285018> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE dvt-fab10 TABLE_ALT_ITEM <rdar://problem/23524119> TABLE_ALT_ITEM 311S00104 311S00091 ALL <rdar://problem/23640575> I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART WWW.AliSaler.Com 7 6 5 4 3 2 145 OF 145 SHEET 121 OF 121 IV ALL RIGHTS RESERVED 8 10.0.0 1 SIZE D A