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Power-Efficient RF and mm-Wave VCOs/PLL

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Analog and Mixed-Signal Circuits in Nanoscale CMOS

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

Almost every electronic system demands a clock signal with high spectral purity. Wireless or wireline systems typically rely on two approaches to enhance the data rate: (1) employing a denser modulation scheme and (2) increasing the operating frequency to secure a large bandwidth. Both approaches impose stringent requirements on the phase noise or jitter of the clock signal. Also, the clock generator needs to be power-efficient in order to improve the battery life of a mobile terminal or save energy dissipation in the data center. This chapter elaborates VCO (voltage-controlled oscillator) and PLL (phase-locked loop) designs, two critical components of a clock generator. The first and third designs demonstrate how the harmonic shaping techniques help to improve the phase noise of the RF and mm-wave VCOs. The second presents an inductive mode-switching technique that can increase the frequency tuning range of the mm-wave VCO without compromising the phase noise. The fourth work is a 25.5–29.9 GHz subsampling (SS) PLL utilizing a master-slave isolated subsampling phase detector to simultaneously obtain low jitter and low reference spur. We verified all four designs with silicon results in 65 nm CMOS (complementary metal-oxide semiconductor).

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Author information

Authors and Affiliations

  1. State-Key Laboratory of Analog and Mixed-Signal VLSI/IME and FST-ECE, University of Macau, Macao SAR, China

    Hao Guo, Zunsong Yang, Chee Cheow Lim, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak & Rui P. Martins

  2. School of Engineering, Asia Pacific University of Technology and Innovation, Kuala Lumpur, Malaysia

    Chee Cheow Lim

  3. Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia

    Harikrishnan Ramiah

  4. On leave from Instituto Superior Técnico, Universidade de Lisboa, Lisboa, Portugal

    Rui P. Martins

Authors
  1. Hao Guo
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  2. Zunsong Yang
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  3. Chee Cheow Lim
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  4. Harikrishnan Ramiah
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  5. Yatao Peng
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  6. Yong Chen
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  7. Jun Yin
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  8. Pui-In Mak
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  9. Rui P. Martins
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Corresponding author

Correspondence to Jun Yin .

Editor information

Editors and Affiliations

  1. University of Macau, Macao, China

    Rui Paulo da Silva Martins

  2. University of Macau, Macao, China

    Pui-In Mak

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Guo, H. et al. (2023). Power-Efficient RF and mm-Wave VCOs/PLL. In: Paulo da Silva Martins, R., Mak, PI. (eds) Analog and Mixed-Signal Circuits in Nanoscale CMOS. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-031-22231-3_2

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  • DOI: https://doi.org/10.1007/978-3-031-22231-3_2

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-22230-6

  • Online ISBN: 978-3-031-22231-3

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