Abstract
Continual neural signals recording is very important in the design of an effective brain machine interface and also to interpret human neurophysiology. Advancements in technology made the electronics to be capable of recording signals from large number of neurons on a single device. The demand for data from large number of neurons is continuously increasing from day to day. It is required for near approximate estimation of a challenging tool for the design engineers to produce an efficient Neural Recording Front End (NRFE). For small implant size, area occupied per channel must be low. Dynamic range in NRFE varies with respect to time due to change in the distance between electrode and neuron or background noise which requires adaptability. In this work, techniques for reduction of power consumption per channel and reduction in area consumption per channel in a NRFE are studied, via new circuits and architectures, and compared for proper choice of sub-blocks.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Chen, K., Yang, Z., Hoang, L., Weiland, J., Humayun, M., Liu, W.: An integrated 256-channel epi-retinal prosthesis. Solid-State Circ. 45(9), 1946–1956 (2010)
He, J., Ma, C., Herman, R.: Engineering neural interfaces for rehabilitation of lower limb function in spinal cord injured. Proc. IEEE 96(7), 1152–1166 (2008)
Amar, A., Levy, M., Liu, C., Apuzzo, M.: Vagus nerve stimulation. Proc. IEEE 96(7), 1142–1151 (2008)
Harrison, R., Kier, R., Chestek, C., Gilja, V., Nuyujukian, P., Ryu, S., Greger, B., Solzbacher, F., Shenoy, K.: Wireless neural recording with single low-power integrated circuit. Neural Syst. Rehabil. Eng. IEEE Trans. 17(4), 322–329 (2009)
Chaturvedi, V., Amrutur, B.: An area-efficient noise-adaptive neural amplifier in 130 nm CMOS technology. Emerg. Sel. Top. Circ. Syst. PP(99), 1–10 (2011)
Tong, X., Wang, J.: A 1Â V 10 bit 25kS/s VCO-based ADC for implantable neural recording. In: IEEE Conference (2017)
Yeon, P., Bakir, M.S., Ghovanloo, M.: Towards a 1.1Â mm2 free-floating wireless implantable neural recording SoC. In: IEEE Conference (2018)
Shui, B., Keller, M., Kuhl, M., Manoli, Y.: A 70.8Â dB 0.0045Â mm2 low-power continuous-time incremental delta-sigma modulator for multi-site neural recording interfaces. In: IEEE Conference (2018)
Park, S.-Y., Cho, J., Lee, K., Yoon, E.: Dynamic power reduction in scalable neural recording interface using spatiotemporal correlation and temporal sparsity of neural signals. IEEE J. Solid State Circ. (2018)
Kim, C., Joshi, S., Courellis, H., Wang, J., Miller, C., Cauwenberghs, G.: Sub-μVrms-noise sub-μW/channel ADC-direct neural recording with 200-mV/ms transient recovery through predictive digital autoranging. IEEE J. Solid-State Circ. (2018)
Tong, X., Wang, R.: A 0.6Â V 10 bit 120kS/s SAR ADC for implantable multichannel neural recording. In: IEEE Conference (2017)
Rehman, S.U., Kamboh, A.M., Yang, Y.: A 79 μW 0.24 mm2 8-channel neural signal recording front-end integrated circuit. In: IEEE Conference (2017)
Tang, T., Goh, W.L., Yao, L., Cheong, J.H., Gao, Y.: An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit. In: IEEE Conference (2017)
Luany, S., Liuy, Y., Williams, I., Constandinou, T.G.: An event-driven SoC for neural recording. In: IEEE Conference (2016)
Ando, H., Yoshida, T., Matsushita, K., Hirata, M., Suzuki, T.: Wireless multichannel neural recording ith a 128Â Mbps UWB transmitter for an implantable brain-machine interfaces. IEEE Trans. (2015)
Bahr, A., Saleh, L.A., Hinsch, R., Schroeder, D., Isbrandt, D., Krautschneider, W.H.: Small area, low power neural recording integrated circuit in 130Â nm CMOS technology for small ammalians. In: 2016 IEEE (2016)
Liu, X., Zhang, M., Xiong, T., Richardson, A.G., Lucas, T.H., Chin, P.S., Etienne-Cummings, R., Tran, T.D., Van der Spiegel, J.: A fully integrated wireless compressed sensing neural signal acquisition system for chronic recording and brain machine interface. IEEE Trans. 10(4), 874–883 (2016)
Hsu, W.-Y., Cao, C., Schmid, A.: A time-based, digitally intensive circuit and system architecture for wireless neural recording with high dynamic range. In: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16–19 Oct. 2016, Abu Dhabi, UAE (2016)
Mendrela, A.E., Cho, J., Fredenburg, J.A., Nagaraj, V., Netoff, T.I., Flynn, M.P., Yoon, E.: A bidirectional neural interface circuit with active stimulation artifact cancellation and cross-channel common-mode noise suppression. IEEE J. Solid-State Circ. (2015)
Liu, X., Zhu, H., Zhang, M., Richardson, A.G., Lucas, T.H., Van der Spiegel, J.: Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit. 2015 IEEE, pp. 2996–2999 (2015)
Tao, Y., Lian, Y.: A 0.8Â V, 1MS/s, 10-bit SAR ADC for multi-channel neural recording. IEEE Trans. IEEE (2014)
Widge, A.S., Dougherty, D.D., Eskandar, E.N.: An implantable 64-channel neural interface with reconfigurable recording and stimulation. In: 2015 EU, pp. 7837–7840 (2015)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Brundavani, P., Vishnu Vardhan, D. (2020). Review of Low Power Techniques for Neural Recording Applications. In: Gunjan, V., Zurada, J., Raman, B., Gangadharan, G. (eds) Modern Approaches in Machine Learning and Cognitive Science: A Walkthrough. Studies in Computational Intelligence, vol 885 . Springer, Cham. https://doi.org/10.1007/978-3-030-38445-6_14
Download citation
DOI: https://doi.org/10.1007/978-3-030-38445-6_14
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-38444-9
Online ISBN: 978-3-030-38445-6
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)