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Design of energy efficient VCO for PLL application

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Abstract

This manuscript proposes a design approach of current starved stack voltage control oscillator (VCO) with DTMOS transistor technique for phase-locked loop (PLL) application with efficient switching energy and high frequency. The PLL is the critical component and plays a vital role in many communication systems such as satellite communication, GPS system, clock data recovery, and frequency synthesizer. An oscillator's oscillating frequency is controlled by the control voltage, known as the voltage control oscillator. Among all the oscillators, the current starved oscillator is the most popular oscillator due to the balancing nature between a wide tuning range and low area. In this manuscript, the stack delay with DTMOS transistor techniques is used in current starved VCO, which reduces delay and enhances the frequency. The cadence virtuoso EDA tool with 45 nm technology is used to design all the circuits. There is an improvement in the frequency and in the switching energy by 34.57% and 18.60%, respectively.

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The authors declare that the data supporting the findings obtained during this research work is available within the paper.

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Authors and Affiliations

  1. Electronics and Communication Engineering, MMMUT, Gorakhpur, India

    Balwant Singh, Saurabh Kumar & R. K. Chauhan

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  1. Balwant Singh
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  2. Saurabh Kumar
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  3. R. K. Chauhan
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Contributions

All authors contributed to the study, conception, and design. Balwant Singh, Saurabh Kumar, and R.K.Chauhan did material preparation, data collection, and analysis. Balwant Singh wrote the first draft of the manuscript and all authors commented on previous versions. All authors read and approved the final manuscript.

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Correspondence to Saurabh Kumar.

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Singh, B., Kumar, S. & Chauhan, R.K. Design of energy efficient VCO for PLL application. Analog Integr Circ Sig Process 114, 31–40 (2023). https://doi.org/10.1007/s10470-022-02122-y

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