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Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy

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Abstract

This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration for capacitor mismatch is single-channel least mean square (LMS) algorithm. The capacitor recombination algorithm can initially calibrate the capacitor array mismatch and provide an environment conducive to convergence for LMS algorithm. After running the capacitor recombination algorithm, the convergence speed of LMS algorithm can be improved. The results of 100 times of Monte Carlo simulation show that LMS algorithm can converge within 1500 cycles, the ADC signal-to-noise and distortion ratio is improved from 71.63 to 97.47 dB, the spurious-free dynamic range is improved from 84.98 to 125.28 dB, the effective number of bits is improved from 12.85 to 15.90 bits, the differential nonlinearity is reduced from 2.09 to 0.90 LSBs, and the integer nonlinear is reduced from 7.14 to 0.68 LSBs.

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References

  1. A. Bannon, C.P. Hurrell, D. Hummerston, C. Lyden, An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range, in: 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1–2. IEEE (2014)

  2. K.L. Chan, N. Rakuljic, I. Galton, Segmented dynamic element matching for high-resolution digital-to-analog conversion. IEEE Trans. Circuits Syst. I Regul. Pap. 55(11), 3383–3392 (2008)

    Article  MathSciNet  Google Scholar 

  3. K.-H. Chang, C.-C. Hsieh, A 12b 10MS/s 18.9 fJ/conversion-step sub-radix-2 SAR ADC, in: 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1–4. IEEE (2016)

  4. B. Chen, M. Maddox, M.C.W. Coln, Y. Lu, L.D. Fernando, Precision passive-charge-sharing SAR ADC: analysis, design, and measurement results. IEEE J. Solid-State Circuits 53(5), 1481–1492 (2018)

    Article  Google Scholar 

  5. Y.-H. Chung, C.-H. Tien, Q.-F. Zeng, A 16-Bit calibration-free SAR ADC with binary-window and capacitor-swapping DAC switching schemes. IEEE Trans. Circuits Syst. I Regul. Pap. (2021)

  6. X. Ding, K. Hofmann, L. Zhang, D. Yi, Y. Ma, Redundant double conversion based digital background calibration of SAR ADC with convergence acceleration and assistance, in: 2018 25th International Conference ”Mixed Design of Integrated Circuits and System” (MIXDES), pp. 192–197. IEEE (2018)

  7. H. Fan, Y. Wang, X. Wu, A realizable digital bubble sorting SAR ADC calibration technology, in: 2021 International Conference on IC Design and Technology (ICICDT), pp. 1–4. IEEE (2021)

  8. Y.-S. Hu, J.-H. Lin, D.-G. Lin, K.-Y. Lin, H.-S. Chen, An 89.55dB-SFDR 179.6dB-FoMs 12-bit l-MS/s SAR-assisted SAR ADC with weight-split compensation calibration, in: 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 253–256 (2018)

  9. W.-H. Huang, S.-H. Wu, Z.-X. Chen, Y.-S. Shu, An amplifier-less calibration-free SAR ADC achieving 100dB SNDR for multi-channel ECG acquisition with 667mV pp linear input range, in: 2019 Symposium on VLSI Circuits, pp. C70–C71. IEEE (2019)

  10. C.P. Hurrell, C. Lyden, D. Laing, D. Hummerston, M. Vickery, An 18b 12.5 MHz ADC with 93dB SNR, in: 2010 IEEE International Solid-State Circuits Conference-(ISSCC), pp. 378–379. IEEE (2010)

  11. S. Konno, Y. Miyahara, K. Sobue, K. Hamashita, A 16b 1.62 MS/s calibration-free SAR ADC with 86.6 dB SNDR utilizing DAC mismatch cancellation based on symmetry, in: 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 1–2. IEEE (2020)

  12. Z. Lan, L. Dong, X. Jing, L. Geng, A 12-bit 100MS/s SAR ADC with digital error correction and high-speed LMS-based background calibration, in: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5. IEEE (2021)

  13. H. Li, M. Maddox, M.C.W. Coin, W. Buckley, D. Hummerston, N. Naeem, A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3 ppm INL, in: 2018 IEEE International Solid-State Circuits Conference-(ISSCC), pp. 242–244. IEEE (2018)

  14. W. Liu, P. Huang, Y. Chiu, A 12b 22.5/45MS/s 3.0 mW 0.059 mm\(^{2}\) CMOS SAR ADC achieving over 90dB SFDR, in: 2010 IEEE International Solid-State Circuits Conference-(ISSCC), pp. 380–381. IEEE (2010)

  15. M. Maddox, B. Chen, M. Coln, R. Kapusta, J. Shen, L. Fernando, A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS, in: 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 153–156. IEEE (2016)

  16. J. McNeill, M.C.W. Coln, B.J. Larivee, “Split ADC’’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE J. Solid-State Circuits 40(12), 2437–2445 (2005)

    Article  Google Scholar 

  17. J.A. McNeill, R. Majidi, J. Gong, “Split ADC’’ background linearization of VCO-based ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 62(1), 49–58 (2014)

    Article  Google Scholar 

  18. J. Shen, A. Shikata, L.D. Fernando, N. Guthrie, B. Chen, M. Maddox, N. Mascarenhas, R. Kapusta, M.C.W. Coln, A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS. IEEE J. Solid-State Circuits 53(4), 1149–1160 (2018)

    Article  Google Scholar 

  19. Y.-S. Shu, L.-T. Kuo, T.-Y. Lo, An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS. IEEE J. Solid-state Circuits 51(12), 2928–2940 (2016)

    Article  Google Scholar 

  20. Y. Wang, L. Zhang, F. Mei, Y. Chen, J. Wu, Digital calibration of capacitor mismatch and gain error in pipelined SAR ADCs, in: 2021 IEEE 14th International Conference on ASIC (ASICON), pp. 1–4. IEEE (2021)

  21. L. Wei, G. Shangshang, W. Xiao, S. Shiguang, Background LMS calibration algorithm realization for SAR-ADC, in: 2021 6th International Conference on Integrated Circuits and Microsystems (ICICM), pp. 142–146. IEEE (2021)

  22. B. Xu, Y. Chiu, Background calibration of time-interleaved ADC using direct derivative information, in: 2013 IEEE International symposium on Circuits and Systems (ISCAS), pp. 2456–2459. IEEE (2013)

  23. F. Ye, J. Ren, A 12-bit SAR ADC using pseudo-dynamic weighting C-DAC for capacitor error calibration, in: 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 746–749 (2020)

  24. Y. Zhou, B. Xu, Y. Chiu, A 12-b 1-GS/s 31.5-mW time-interleaved SAR ADC with analog HPF-assisted skew calibration and randomly sampling reference ADC. IEEE J. Solid-State Circuits 54(8), 2207–2218 (2019)

    Article  Google Scholar 

Download references

Funding

The work of Hua Fan was supported by Sichuan Science and Technology Program under Grant 2022YFG0164 and supported by Medico-Engineering Cooperation Funds from University of Electronic Science and Technology of China under Grant ZYGX2021YGLH203, and supported by general project of Chongqing Natural Science Foundation under Grant 2022NSCQ-MSX5348. The work of Quanyuan Feng was supported by the Important Project of the National Natural Science Foundation of China under Grant 62090012.

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Fan, H., Wang, Y., Wei, Q. et al. Capacitor Recombination Algorithm Combined with LMS Algorithm in 16-Bit SAR ADC with Redundancy. Circuits Syst Signal Process 42, 3181–3199 (2023). https://doi.org/10.1007/s00034-022-02266-2

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