This repo contains detailed documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
- Introduction
- Block Diagram of PLL
- Reference Books for Literature review and architecture design
- Setting up Linux Environment
- Installations
- Running eSim and Ngspice
- Prelayout
- Layout Design
- Acknowlegment
- References
The phase locked loop is a circuit which takes the external low frequency clock signal generated with the help of crystal oscillator and gives the High frequency clock signal as the output in this case it is 8 times input clock frequency. This high frequency clock generated can be given to different circuits on chip. The clock signal generated by PLL is stable in terms of clock frequency and clock phase.
- Design of Analog CMOS Integrated Circuits Behzad Razavi
- Design of CMOS Phase Locked Loops Behzad Razavi
Download the latest version of Virtual Box from the following link:
https://www.virtualbox.org/
After installation it will look somewhat like this:
Download the Ubuntu Disk Image:
https://ubuntu.com/download/desktop
Create a new machine:
Follow the steps hereafter.
After complete installation the Ubuntu window looks like this:
Open terminal and run:
sudo apt-get install git
Then do:
git clone https://github.com/parasgidd/avsdpll_3v3.git
Install eSim and follow steps from here: https://esim.fossee.in/downloads
Run following Commands in the terminal: git clone git://opencircuitdesign.com/magic
cd magic
sudo ./configure
sudo make
sudo make install
cd /avsdpll_3v3/prelayout$
ngspice inv.cir
Run the following command to open Magic:
magic -T SCN6M_SUBM.10.tech
I would like to thank Mr.Kunal Ghosh and Mr. Paras Gidd for explaining the the detail designing procedure of PLL circuit. This tutoril helped me to understand the the analog design flow right from circuit simulation to post layout simulation.