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SN74LVC1G57: Using SN74LVC1G57 for deadtime circuit

Jose Sandoval
Prodigy 20 points
Part Number: SN74LVC1G57
Other Parts Discussed in Thread: STRIKE

I am using the SN74LVC1G57 configured as 2-input AND gate as part of a deadtime circuit. See the attached image for reference. Vcc is 5V. Two identical deadtime circuits are used: one for the HI side switch and another one for the LOW side switch.

Input A for the AND gate is always ON for purposes of this discusion. The depicted source is a square wave at 400 kHz. Deadtime is created by slowing only the rising edge through the RC constant. The falling edge is not affected due to diode. I was expecting deadtime ~105 ns since that's the amount of time it takes AND gate input B to reach ~2.4V which I approximated to be the positive-going input threshold voltage (Vt+). However, I am measuring a deadtime of 70 ns. Is my understanding of Vt+ incorrect? What's the Vt+ for Vcc = 5V? What could be causing the deadtime to be 70 ns instead of 105 ns?

  • 0
    TI__Guru* 96591 points

    I'd expect the typical positive threshold to be around 2.75V, just based on the datasheet values:

    Given that, I'd expect your circuit to provide about 128ns of delay to the input signal (probably closer to 131ns, given the delay of the device, but that's going to factor out since you're using 2).

    I would recommend to put an oscilloscope on the input and output to see what's going on.

    There could be damage to the input, causing additional leakage that is throwing off your charge time calculation. Have you tried swapping to a new IC? The most common cause of extra leakage is an ESD strike, which can leave the device mostly operational besides the added leakage.

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    I will get the input and output waveforms and get back to you. The IC is a new part. 

  • 0 in reply to Jose Sandoval
    TI__Guru* 96591 points
    Jose Sandoval said:
    The IC is a new part. 

    Does that mean you've replaced the device in an ESD safe environment? Or that the original IC was new?

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    I meant that the original IC was new. I've captured waveforms. The delay between the pwm source and the AND gate output is about ~100 ns on the rising edge which would indicate that the device is switching ON at around 2.3V. Does this value make sense?

    I am measuring the delay between 2.5V level of both signals. I also tried probing at AND gate input B but that introduces another delay due to probe capacitance making the delay b/w PWM source and AND gate output ~117 ns. See plots below for your reference.

    On the falling edge I measure a delay of ~11.5 ns between the pwm source and the AND gate output. I was expecting something close to 7 ns (i.e 2ns due to RC and  5ns due to propagation delay of device). Does the 11.5 ns sound reasonable? What are the Vt- thresholds for Vcc =5V?

    The effective deadtime I observe at the output of the AND gates is close to 85 ns.

    My ultimate goal is to make sure that I have consistency across parts and boards. 

  • +1 in reply to Jose Sandoval
    TI__Guru* 96591 points

    Your rising and falling edges are pretty slow relative to your timebase, which is going to throw off your calculations. The typical RC charge time assumes a perfect step function.

    I don't see any problem with the operation shown or the circuit. Your expectations for accuracy are what need to be adjusted. You aren't going to get a perfect-to-the-nanosecond delay with this type of circuit.

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    Thanks for the feedback.