ADC31JB68: Ramp pattern?, JESD204B Link unstable.

Hi,

How is your JESD IP configured? Do the settings match that of the ADC registers in accordance with the datasheet? Are you using a 250 MHz FPGA ref clock (5 Gbps / 20)?

The documentation that we have for the TSW14J10EVM does not include the ZC106 dev kit (only ZC706), but would assume that you have made any necessary modifications in the firmware.

Are you able to verify the SYSREF frequency?

Best Regards,

Dan

Hi,

We are going to use ZU7EV(MPSoC with video CODEC).

So, I need to do it with ZCU106 board.

As you can check in the LMK04828 settings.

CLK, 500MHz input is connected to LMK04828's CLKin1 and ADC31JB68's CLKIN.

500MHz/2 = 250MHz for FPGA refclk(DCLKout8), and glbclk(DCLKout10).

500MHz/32 = 15.625MHz for SYSREF(SDCLKout3, SDCLKout11).

And, in below ILA capture, jesd204_bolck_IBUF_OUT is sysref.

ILA capture clock is 250MHz, glbclk.

sysref is 16 clock period of 250MHz capture clock.

So it's 15.625MHz. 

When JESD204 link succeed, rx_sync is like above, steady 1.

When JESD204 link fails, rx_sync is like below. Pattern is changing like below.

When JESD204 link is connected, if I caputre 50MHz CW tone, the wave form is like below. There are periodic discontinuities. The period is about 128 samples.

Below is JESD204 IP settins.

Hi Seung Oh,

I am facing a similar situation. In my setup my clocks are as follows

ADC DEV Clock - 500 MHz

ADC SYSREF Clock - 15.625 MHz

FPGA CORE Clock - 125 MHz

FPGA REF Clock - 500 MHz ( cpll_refclk)

FPGA SYSREF Clock - 15.625 MHz

When you say glbclk what do you mean? on the JESDB Block there are two clocks REF_CLK and CORE_CLK. Are you setting both clocks to 125MHz?

Also are you capturing all the samples inside the FPGA i.e with a 50MHz input signal and 500 MHz sampling frequency you should capture 10 samples/cycle?

Really appreciate your help.

Thanks and Rgds,

Stephen

I see that you have the following clocks

FPGA CORE Clock - 125 MHz

FPGA REF Clock - 250 MHz ( cpll_refclk)

FPGA SYSREF Clock - 15.625 MHz

Now the only questions is are you capturing all the samples?

Thanks,

Stephen

Hi,

I found your post now.

As you can see HSMC Pro software.

Evaluation board just capture ~64KB of data, when it receive capture command.

The product, that we are developing, will capture all date in NVMe drive.

Regards,