1. xerox 560 computer system - The UK Mirror Service

Xerox 560 ComputerReference Manual90 30 76A

'xerox Corporation/701 South Aviation BoulevardlEI Segundo, California 90245_213679-4511XEROXXerox 560 ComputerReierence iVianuaiFIRST EDITION90 30 76AJanuary 1974Price: $7.25© 1974, Xerox CorporationPrinted in U.S.A.

4. INPUT/OUTPUT OPERA TIO NS 142 AGURESExternal DIO Interface 142 1. A Xerox 560 Computer System 9Multiplexor Input/Output Processor (MIOP)Devi ce Controllers 142 2. The Basic Processor 10Rotating Memory Processor (RMP) 143Input/Output Processor (lOP) Fundamentals __ 143 3. Information Boundaries 13Command List 143Operational IOCD 143 4. Main Memory 15Control IOCD 146I/o Operation Phases 148 5. Addressing Logic 18Preparation Phase 148Initiation Phase 148 6. Index Displacement Alignment (Real andFetching Phase 148 Virtual Addressing Modes) 21Execution Phase 149Termination Phase 151 7. Generation of Actual Addresses Indirect,Virtual Addressing 225. OPERATIONAL CONTROL 152 8. Index Displacement Alignment (Real-Extended Addressing) 23Externa I Control Subsystem 152Central ized System Control 152 9. Generation of Effective Virtual AddressControl Console Devices 152 (Indirect Real-Extended Addressing) 24Control Commands 153Operator Control Commands 153 10. Operational States of an Interrupt Level 31Diagnosti c Control Commands 156Maintenance Control Commands 158 1l. Interrupt Priority Chain 34System Control Panel 161Operating Procedures and Information ___ 16412. Typical 28-Word Portion of Memory Stackfor PSS and P LS 1026. SYSTEM CONFIGURATION CONTROL 167 13. Formats of I/o Instructions 128Configuration Control Panel (CCP) 167 14. Bootstrap Loader 155APPENDIXES15.System Control Panel 16216. Chassis Physical Configuration 168A. REFERENC E TABLES 17317. Sample Rows of CCP Switches 168Standard Symbols and Codes 173Standard Character Sets 173Control Codes 173Special Code Properties 173Standard 8-Bit Computer Codes (EBCDIC)___ 174Standard 7-Bit Communication CodesTABLES(ANSCII) 174Standard Symbol-Code Correspondences 175 l. Basic Processor Operating Modes andHexadecimal Arithmetic 179 Address i ng Cases 25Addition Table 179Multiplication Table 179 2. Interrupt Locations 33Table of Powers of SixteenlO 180Table of Powers of Ten16 180 3. Summary of Trap Locations 37Hexadecimal-Decimal Integer ConversionTable 181 4. TCC Setting for Instruction ExceptionHexadecimal-Decimal Fraction Conversion Trap X'4D' 44Table 187Table of Powers of Two 191 5. Registers Changed at Time of a Trap Due toMathematica I Constants 191 an Operand Access 45B. GLOSSARY OF SYMBOLIC TERMS 192 6. ANALYZE Table for Operation Codes 57C. FAULT STATUS REGISTERS 195 7. Floating-Point Number Representation 76iv

8. Condition Code Settings for Floating-Point 19. Status Response Bits for AIO Instruction 135Instructions 7920. I/o Address (AIO Response) 1359. Status Word 0 1192l. Event Messages 15310. Status Word 1 11922. Diagnostic Control (P-Mode) Commands ___ 15711. Read Direct Mode 9 Status Word 12323. Bit Assignments and Description, Processor12. Chassis Type Assignments 124 Control Word, Register Q30 (X'1 E') ___ 16513. Description of I/o Instructions 128 24. Bit Assignments, Address CompareRegister Q31 (X'1F') 16614. I/o Status Information (Register R) 13025. Functi ons of Processor Cluster Confi gurat ion15. Device Status Byte (Register R or Ru1) Control Panel Row 169(SIO, no, and HIO only) 13126. Functions of Memory Unit Configuration16. Operational Status Byte (Register Ru1) 132 Control Panel Row 17017. Status Response Bits for I/o Instructions 133 C-l. Fault Status Registers 19518. lOP Status Byte 134 C-2. Memory Unit Status Register 196v

1. XEROX 560 COMPUTER SYSTEMINTRODUCTIONThe Xerox 560 general-purpose, digital, computer systemaccommodates a variety of scientific, business, real-time,and ti me-shar i ng app I i cat ions. A system inc I udes systemcontrol, basic processor, I/O processor, and main memory(up to 256K words) with two ports. Each major systemelement performs asynchronously with respect to otherelements.The basic system can be readi Iy expanded. Memory accesspaths can be increased from the basic two ports to a maximumof six ports. Input/output capability can be increasedby adding more input/output processors (lOPs), device controllers,and peripheral devices.The basic processor (BP) has an extensi ve i nstructi on setthat includes floating-point, byte-string, and decimalinstruct ions.The multiaccess memory units, with interleaving, afford ahigh level of system performance. Main memory can beexpanded in 16K word increments to a maximum of 256Kwords. Address interleaving may be performed betweenmemory units of like size. The number of ports to eachmemory unit can be expanded to allow independent accessto memory by up to six II processor clusters" (i. e. ,functional groups).Processor clusters are the grouping of two or more functions(such as a basic processor, an I/O processor, and interfaces)on a common bus. Clustering permits processors toshare common faci I iti es, e. g., buses and memory interfaces.Therefore, the hardware is I ess redundant, henceless complex, resulting in more reliability at a lower cost.There are multiple combinations of functional groups fromwhich to select.Existing Sigma 5-9 programs may be run on the system. Theupward compatibility of the comprehensive, modular software(assemblers, compi lers, mathematical and uti lity routines,and application packages) eliminates reprogramming.Features have been incorporated in this design to enhanceoverall system reliability, maintainability, and availability.Centralized switches for system repartitioning may permitfaulty units, or an entire subsystem, to be isolated for diagnosisor repair while the primary system continues operation.Parity checking is performed on each byte of informationfor most system interfaces and internal control signals. Mostfai led instructions are automatically retried, and uninterruptedprocessing continues. The only apparent effect maybe an entry in the error log. In the event an error is irrecoverabl e, there are error storage reg i sters that return completedata on the fault and the status of the system atthat point.GENERAL CHARACTERISTICSThe following system features and characteristics permitefficient operation in general-purpose, multiprocessor,time-sharing, real-time, and multiuse environments:• Word-oriented memory (32-bit word plus parity bitper byte) that can be addressed and altered as byte(8-bit), halfword (2-byte), word (4-byte), and doubleword(8-byte) quantities.•Memory expandable to 256K words (K = 1024) in modularunits of 16K words each.•••Immediate operand instructions for greater storageefficiency and increased speed.•Hardware memory mapping, which virtually eliminatesmemory fragmentation and provides dynamic programrelocation.•Memory write protection within memory units to preventinadvertent destruction of critical areas of memory fromany processor cluster.••Indirect addressing with or without postindexing.Displacement index registers, automatically selfadjustingfor all data sizes.•Four blocks of 16 general-purpose registers for addressing,indexing, and accumulating.permit rapid context switching.Multiple registersAA ____... ______ ___ J.. __ L~ __ L __ _ ~ ~_L ___ ___ .-.I ! __ r ______ L~___n .... II.v., ............"'= !-'.V."'.... IIVII 'VI ;'1;"""" ,",II,", II11V111,UIIUIIsecuri ty and protecti on.Watchdog timer to assure nonstop operation.Real-time priority interrupt system with automatic identificationand priority assignment, fast response time,and 14 internal and up to 48 external levels that canbe individually armed, enabled, and triggered byprogram control.• Instructions with long execution times can be interrupted.• Automatic traps for error or fault conditions, withmasking capability and maximum recoverability, underprogram control.• Power fail-safe for automatic shutdown and resumptionof processing in event of power fai lure.• Multiple interval timers with a choice of resolutionsfor independent ti me bases.• Privileged instruction logic for program integrity inmultiuse environments.Xerox 560 Computer System

• Extensive instruction set that includes:• Byte, halfword, word, and doubleword operations.• Use of all memory-referencing instructions forregister-to-register operations, with or withoutindirect addressing and postindexing, and withinnormal instruction format.• Multiple register operations.• Fixed-point integer arithmetic operations in halfword,word, and doubleword modes.• Immediate operand instructions.• Floating-point hardware operations in short andlong formats with significance, zero, and normalizationcontrol and checking, all under full programcontrol.• Full complement of logical operations (AND, OR,exclusive OR).• Comparison operations, including compare betweenlimits (with I imits in memory or in registers).• Call instructions that permit up to 64 dynamicallyvariable, user-defined instructions, and allow aprogram access to operating system functions withoutoperating system intervention.• Decimal hardware operations, including arithmetic,edit, and pack/unpack.• Byte-string instructions.• Push-down stack operations (hardware implemented)of single or multiple words, with automaticI imit checking, for dynamic space allocation,subroutine communication, and recursiveroutine capabi lity.• Automatic conversion operations, including binary/BCD and any other weighted-number systems.• Analyze instruction that facilitates effectiveaddress computation.• Interpret instruction that increases speed of interpretiveprograms.• Shift operations (left and right) of word or doubleword,including logical, circular, arithmetic,searching shift, and floating-point modes.• Built-in reliability and maintainability features thatinclude:• Extensive error logging. When a fault is detected,system status and fault information are availablefor program retrieval and logging for subsequentanalysis.• Full parity checking on all data and addressescommunicated in either direction on buses betweenmemory units and processors, providing fault detectionand location capability to permit theoperating system or diagnostic program to quicklydetermine a faulty unit.• Address stop feature that permits operator or maintenancepersonnel to:Stop on any instruction address.Stop on any memory reference address.Stop when any word in a selected page ofmemory is referenced.• Traps that provide for detection of a variety offault conditions, designed to enable a high degreeof system recoverab iii ty .• Partitioning features that enable system reconfigurationvia a centralized Configuration ControlPanel. Units may be partitioned from the systemby selectively disabling them from buses (assumingother system facilities can handle the additionalload). Thus, faulty units, processors, devices, oran alternate system can be isolated from the operationalsystem to enable diagnosis or repair whi Iethe primary system continues operation.• Independently operating I/O system with the followingfeatures:• Direct input/output (READ DIRECT, WRITE DIRECTinstructions) for transfer of 32-bit words betweenthe specified general register and an external device;a 16-bit address is transferred for selectionand control purposes; and each transfer is underdirect program control.• Up to five independent I/O processor clusters (restrictedonly by the maximum number of 6 ports).• Multiplexor I/O processors (MIOPs) (up to 3 perI/O cluster), each providing for simultaneous operationof up to 16 devices per processor.• Data chaining for gather-read and scatter-writeoperati ons.• Command chaining for multiple record operations.• Write lock protect feature within memory unitfor positive protection from all processors storinginto memory.• Comprehensive modular software that is program compatiblewith Sigma 5-9 computers:•Expands in capabi I i ty and speed as system grows.•Operating system: Control Program-Five (CP-V).2 General Characteristics

Many operations are performed in floating-point formatand on strings of characters. Other typical characteristicsinclude decimal arithmetic operations, binary to decimalnumber conversion (for printing or display), and high systemi nput/ output transfer rates.General-purpose features are described in the followingparagraphs.Floating-Point Hardware. Both short (32-bit) and long(64-bit) formats are available in the floating-point instructions.Under program control, the user may selectoptional zero checking, normalization, floating-pointrounding and significance checking. Significance checkingpermits use of short floating-point format for high processingspeed and storage economy and of long floatingpointformat when loss of significance is detected.Decimal Arithmetic Hardware. Decimal arithmetic instructionsoperate on up to 31 digits plus sign. This instructionset includes pack/unpack instructions for converting to/fromthe packed format of two digits per byte, and a generalizededit instruction for zero suppression, check protection, andformatting, with punctuation to display or print it.Indirect Addressing. Indirect addressing faci litates tablelinkages and permits keeping data sections of a programseparate from procedure sections for ease of maintenance.Displacement Indexing. Indexing by means of a IIfloating lidisplacement permits accessing a desired unit of data withoutconsidering its size. The index registers automaticallyalign themselves appropriately; thus, the same index registermay be used on arrays with different data sizes. Forexample, in a matrix multiplication of any array of fullword, single-precision, fixed-point numbers, the resultsmay be stored in a second array as double-precision numbers,using the same index quantity for both arrays. If anindex register contains the value of k, then the user alwaysaccesses the kth element, whether it is a byte, halfword,word, or doubleword. Incrementing by various quantitiesaccording ro daro size is nor required; instead, incrementingis always by units in a continuous array table regardlessof the size of data element used.Instruction Set. More than 100 major instructions permitshort, highly optimized programs to be written. These arerapidly assembled and minimize both program space andexecution time.Translate Instruction. The Translate instruction permitsrapid translation between any two 8-bit codes; thus, datafrom a variety of input sources can be handled and reconvertedeasi iy for output.Conversion Instructions. Two generalized conversion instructionsprovide for bidirectional conversions betweeninternal binary and any other weighted number system,including BCD.Call Instructions. These four instructions permit handlingup to 64 user-defined subroutines, as if they were built-inmachine instructions. Call instructions also gain access tospecified operating system services without requiring itsi nterventi on.Interpret Instruction. The Interpret instruction simplifiesand speeds interpretive operations such as compilation, thusreducing space and time requirements for compilers andother interpretive systems.Four-Bit Condition Code. Checking results is simplified byautomatically providing information on almost every instructionexecution, including indicators for overflow, underflow,zero, minus, and plus, as appropriate, withoutrequiring an extra instruction execution.Direct Input/Output (DIO). Direct input/output faci litatesin-line program control of asynchronous or specialpurposedevices. This feature permits information to betransmitted directly to or from general-purpose registers.Multi lexor Input/Out ut Processor (MIOP). Once initialized,I 0 processors operate independently of the basicprocessor, freeing it to provide faster response to systemneeds. An MIOP requires minimal interaction with thebasic processor. I/O command doublewords permit bothcommand chaining and data chaining without interveningbasic processor control. I/o equipment speeds range fromslow rates involving human interaction (teletypewriter, forexample) to transfer rates of rotating memory devices ofover 750,000 bytes per second. Peripheral controllers attachedto an MIOP may be operated simultaneously.Rotating Memory Processor (RMP). An RMP supports up to15 disk drives, one at a time, permitting large capacity,high transfer rate files. Dual access (between 2 RMPs) optionis available.TIME -SHARING FEATURESTi me-shari ng is the abi Ii ty of a system to share its tota Iresources among many users at the same time. Each usermay be performing a different task, requiring a differentshare of the available resources. Some users may be onlinein an interactive, IIconversational limode with thebasic processor while other users may be entering work tobe processed that requires only final output.Time-sharing features are described in the followingparagraphs.Rapid Context Saving. When changing from one user toanother, the operating environment can be switched quicklyand easily. Stack-manipulating instructions permit storingin a push-down stack of 1 to 16 general-purpose registers bya single instruction. Stack status is updated automaticallyand information in the stack can be retrieved when needed4 Time-Sharing Features

(also, by a single instruction). The current program statuswords, which contain the entire description of the currentuser's environment and mode of operation, may be storedanywhere in memory, and new program status words may beloaded, all with a single instruction.Multiple Register Blocks. The availability of four blocksof 16 general-purpose registers improves response time byreducing the need to store and load register blocks. Adistinct block may be assigned for different functions asneeded; the program status words automatically select theapplicable register block.User Protection. The slave mode feature restricts each userto his own set of instructions while reserving to the operatingsystem certain "privileged" (master mode) instructionsthat could destroy another user's program if used incorrectly.Also, a memory access - protection feature preventsa user from accessi ng any storage areas other thanthose assigned to him. It permits him to access certain areasfor reading only, such as those containing publ ic subroutines,while preventing him from reading, writing, or accessinginstructions in areas set aside for other users.Storage Management. Main memory is expandable to 256K(K = 1024) words. To make efficient use of available memory,the memory map hardware permits storing a user's programin fragments as sma II as a page of 512 words, whereverspace is avai lable; yet all fragments appear as a single,contiguously addressable block of storage at execution time.The memory map also automatically handles dynamic programrelocation so that the program appears to be stored inn dnnrlrlrt"l v.i0}' 0t ~X~ClJt!0!",! t!!'!'!e, e'!e!"! th0~gh it !'!'!cy cctuallybe stored in a different set of locations each time itis brought into memory. The memory map provides theabi I ity to locate any 128K-word virtual program in the basicprocessor's logical addressing space. Thus, the system canalways address a virtual memory of 128K words regardlessof physical memory size.Input/Output Capability. Time-sharing input/output requirementsare handled by the same general-purpose input/output capabi I i ti es descri bed under II Genera I-PurposeFeatures".Nonstop Operation. A "watchdog" timer assures that thesystem continues to operate even in case of halts or delaysdue to fai lure of special I/O devices. Multiple real-timeclocks with varying resolutions permit independent timebases for flexible allocation of time slices to each user.Reliability, Maintainability, Availability. Since timesharingsystems have many on-line users needing immediatesystem response, "downtime" defeats time sharing's primarypurpose. Pool i ng of resources a long wi th fl exi bl e reconfigurationcontrol ensures a high level of continuous availability.Configuration controls are provided to switch theload from one unit to another in the event of a failure withno loss of functional capability, only capacity. In addition,a nonworking subset of the total system may belogically isolated (partitioned) so that maintenance mayproceed on the subset while the remainder of the systemconti nues to operate.To minimize the effect of transient errors, automatic retryof fa i led instructions is performed.REAL-TIME FEATURESReal-time applications are characterized by a need for:(1) hardware that provides quick response to an externalenvironment; (2) speed that is sufficient to keep up withthe real-time process itself; (3) input/output flexibility tohandle a wide variety of data types at different speeds;and (4) reliabi lity features to minimize irreplaceable losttime.Multilevel, Priority Interrupt System. The real-timeoriented system provi des rapi d response to external interruptlevels. Each interrupt is automatically identified and respondedto according to its priority. For further flexibi lity,each level can be individually disarmed (to discontinue inputacceptance) and disabled (to defer responses). Use ofthe disarm/disable feature makes programmed dynamic reassignmentof priorities quick and easy, even while a realtime process is in progress.Programs involving interrupts from specially designed equipmentoften require checkout before the equipment is actuallyavai lable. To permit simulating this special equipment, anyexternal interrupt level can be "triggered" by the basicprocessor through execution of a single instruction. Thiscapability is also useful in establishing a modified hierarchyof responses. For example, in responding to a high-priorityinterrupt, after the urgent processing is completed, it maybe desirable to assign a lower priority to the remaining portionso that the interrupt routine is free to respond to othercritical stimul i. The interrupt routine can accomplish thisby triggering a lower-priority level, which processes theremaining data only after other interrupts have been handled.READ DIRECT and WRITE DIRECT instructions (described inChapter 3) allow the program to completely interrogate,preserve, and a I ter the conditi on of the interrupt system atany time and to restore that system at a later time.Nonstop Operation. When connected to special devices(on a ready/resume basis), the basic processor may be excessivelydelayed if the specific device does not respondquickly. As in the time-sharing environment, the built-inwatchdog timer assures that the basic processor cannot bedelayed for an excessive length of time.Real-Time Clocks. Many real-time functions must be timedto occur at specific instants. Other timing information isalsoneeded - for example, elapsed time since a given event, orthe current time of day. The computer system can containup to four real-time clocks with varying degrees of resolution to meet these needs. These clocks a I so a II ow easy handlingof separate time bases and relative time priorities.Real-Time Features 5

Rapid Context Switching. When responding to a new set ofinterrupt-initiated circumstances, a computer system mustpreserve the current operating environment, for continuancelater, whi Ie setting up the new environment. This changingof environments must be done quickly, with a minimum ofII overhead ll time costs. Anyone of the four blocks ofgeneral-purpose arithmetic registers can, if desired, be assignedto a specific environment. All relevant informationabout the current environment (instruction address, currentgeneral register block, memory-protection key, etc.) iskept in the program status words. A single instructionstores the current program status words anywhere in memoryand loads new ones from memory to establish a new environment,which includes information identifying a newblock of general-purpose registers. Thus, the system'soperating environment can be preserved and changed completelythrough the execution of a single instruction.Priority Interrupt System. In a multiuse environment, manyelements operate simulatneously and asynchronously. Thus,an efficient priority interrupt system is essential. It allowsthe computer system to respond quickly, and in proper order,to the many demands made on it, with attendant improvementsin resource efficiency.Quick Response. The many features that combine to producea quick-response system (multiple register blocks,rapid context saving, multiple push-pull operations) benefitall users because more of the system's resources are readi Iyavai lable at any instant.Memory Protection. The memory protection features protecteach user from every other user and guarantee the integrityof programs essential to critical real-time applications.Memory Protection. Both foreground (real-time) and backgroundcan run concurrently in the system because a foregroundprogram is protected against destruction by an uncheckedbackground program. Under operating systemcontrol, the memory access-protection feature preventsaccessing memory for specified combinations of reading,writing, and instruction acquisition.Variable Precision Arithmetic. Much of the data encounteredin real-time systems are 16 bits or less. To processthis data efficiently, both halfword and fullword arithmeticoperations are provided. For extended precision, doublewordarithmetic operations are also included.Direct Input/Output. For handling asynchronous I/O, a32-bitword can be transferred direct!y between any genera!purpose register and external devices.Reliability, Maintainability, Availability. The capabilitiesdescribed in the section, II Time-Sharing Features llapply equally to the real-time environment.Input/Output. Because of the wide range of capacities andspeeds, the I/O system simultaneously satisfies the needs ofmany different application areas economically, both interms of equipment and programming.Instruction Set. The comprehensive instruction set providesthe computational and data-handling capabilities requiredfor widely differing application areasi therefore, each user'sprogram length and running time is minimized, and thethroughput is maximized.MULTIPROCESSOR FEATURESSystem design readily permits expansion to shared memoryin a multiprocessor system. The system can contain a combinationof functional clusters, each of which in turn maycontain multiple processors. The total number of clustersis restricted to the maximum port limitation of six. All processorsina system may share common memory.The following paragraphs describe the major multiprocessorfeatures of the system,MULTIUSE FEATURESAs implemented in this system, IImultiuse ll combines two ormore application areas. The real-time application is themost difficult general computing task because of its severerequirements. Similarly, another difficult multiuse task isa time-sharing application that includes one or more realtimeprocesses. Because the system is designed on a realtimebase, it is qualified for a mixture of applications in amultiuse environment. Many hardware features that provevaluable for Certain application areas are equally USeful inothers, although in different ways. This multiple capabilitymakes the system particularly effective in multiuseapplications.The major multiuse features are described in the following paragraphs.MULTIPROCESSOR INTERLOCKIn a multiprocessor system, the basic processors often needexclusive control of a system resource. This resource maybe a region of memory, a particular peripheral device, or,in some cases, a specific software process. There isa specialinstruction to provide this required multiprocessor interlock.This special instruction, LOAD AND SET, unconditionallysets a 11111 bit inthe sign position of the referenced memorylocation during the restore cycle of the memory operation.If this bit had been previously set by another processor, theinterlock is said to be IIset" and the testing program proceedsto another task. On the other hand, if the sign bitof the tested location is a zero, the resource is allocatedto the testing processor, and simultaneously the interlockis set for any other processor.6 Multiuse Features/Multiprocessor Features

MULTIPORT MEMORY SYSTEMThe system has growth capabi Ii ty of up to 6 ports permemory unit. A memory unit may contain 16K or32K words.This architecture allows flexibility in growth patternsand provides high memory bandwidth, essential to multiprocessor systems.MANUAL PARTITIONING CAPABILITYManual partitioning capabi lity is afforded for all systemunits. Thus, besides the primary advantage of increasedthroughput, a secondary advantage of a multiprocessorsystem is the "fail-soft" abi I ity. Given a duplicate unit,any unit can be partitioned by selectively disabling it fromthe system buses. Depending on the type of fai ling unit,the system wi II be operable, with some degree of degradedperformance. An alternate processor bus with dual systemcapabilities can be provided.MULTIPROCESSOR CONTROL FUNCTIONA multiprocessor control function is provided on all multiprocessorsystems. This function provides these basic features:1. Control of the External Direct Input/Output bus (ExternalDIO), used for controlling system maintenanceand special purpose units such as analog to digitalconverters.2. Central control of system partitioning.3. Centralized interrupt system, providing capability forthe operating system to use interrupts to schedule tasksindependently of the number of basic processors presentin a system.4. Processor to processor communication via processorbuses.SHARED INPUT/OUTPUTIn a multiprocessor system, any basic processor may directI/o actions to any I/O processor. Specifically, any basicprocessor can issue an SIO, no, TDV, or HIO instructionto begin, test, or stop any I/O process. However,the "end-action ll sequence of the I/O process is directedto one of the basic processors in the system by the SystemControl Processor. This feature (accomplished by settinga pair of configuration control switches) allows dedicatingI/o end-action tasks to a single processor and avoids conflictresolution problems.Multiprocessor Features 7

2. SYSTEM ORGANIZATIONThe elements of this computer system include a basicprocessor (BP), input/output processors (lOPs), memory, I/odevice controllers, and devices (see Figure 1). The processorsand interfaces clustered into functional groups, interconnectedvia buses and controlled from a ConfigurationControl Panel and a System Control Processor. Elementswithin a processor cluster share an access path for intraclustercommunications. Thus, the total computer system canbe viewed functionally as a group of program-controlledprocessor clusters communicating with each other and acommon memory. Each processor cluster operates asynchronouslyand semi-independently, automatically overlappingthe operation of elements within as well as theoperation of other processor clusters for greater speed (whencircumstances permit).PROCESSOR CLUSTERSProcessors (basic processor and MIOP, for example) aregrouped functionally along with a Memory Interface (MI)and a Processor Interface (PI) into a processor cluster. Elementswithin a processor cluster share an access path (thecluster bus) to the Memory Interface, which connects to thememory system via a memory bus. The Memory Interfaceresolves contention problems and controls use of the clusterbus by the elements in the cluster.A processor communicates with processors in other processorclusters through the Processor Interface, which connects directlyto a processor bus. Via the processor bus, any processorcan communicate with or control any other processoranywhere in the system configuration.Note: Although two processor buses are provided, a ProcessorInterface can be connected to one or theother of the processor buses, but not to both at thesame time.Within a basic processor-MIOP processor cluster, the basicprocessor primari Iy performs overa II contro I and data reductiontasks whereas the MIOP performs the task associatedwith the exchange of digital information between mainmemory and selected peripheral devices. The MIOP communicateswith device controllers via the I/o bus, whichconnects to the Controller Interface (CI).3. Internal and external interrupt processing.4. External and certain internal direct I/o (DIO) control.It provides these major interfaces with other parts of thesystem:1. System console interface.2. System contro I bus interface.3. Processor bus interface.4. Interna I and externa I interrupt interfaces.5. External and certain interna I DIO interfaces.6. System clock interface.In addition to these major interfaces it provides paths forother signals including system reset, 1.024 MHz clock,power on/power off trap requests, and external real-timeclocks.Figure 1 shows the interconnection of a System Control Processorto processor clusters via a processor bus as well as interconnectionto the system console, external Direct Input/Output (DIO), and external interrupts.BASIC PROCESSORThis section describes the organization and operation of thebasic processor in terms of instruction and data formats, informationprocessing, and program control. The basic processorcomprises a fast memory and an arithmetic and controlunit as functionally shown in Figure 2.Note: Functionally associated with the basic processor bUTphysically located elsewhere are a memory map,memory access protection codes, and memory writeprotection codes. Memory control storage for thememory map and access codes is located in the MemoryInterface, and the memory control storage forthe write protection codes (write locks) is locatedin the memory. These functions are described in"Memory System", later in this chapter.SYSTEM CONTROL PROCESSORThe System Control Processor performs these primary functionsin the overall system:1 • System control.2. External Control Subsystem.GENERAL REGISTERSA fast (integrated circuit) memory consisting of ninety-six32-bit registers is used within the basic processor. A groupof 24 registers is referred to as a register block; thus, abasic processor contains four register blocks. A 2-bit controlfield (called a register block pointer) in the programstatus words (PSWs) selects the register block currently8 System Organization

MemoryUnHMemoryUnitMemoryUnitSystemControlConsoleSystemControlProcessor~~ss;- - - - ---, rCluster (Basic) 1 II I III IMemoryIInterfaceIIIIIProcessor IBus # 1 III IIProcessor I IIInterfaceI IIr--- ____ I ~ I I ~.--1---,SystemControlProcessorIIIL_[_Jr- --,1 System I Control ILC~o~JExternal InterruptsRemote Terminal Console InputsDIO BusBasicProcessorMIOProcessoq BUS 1fT T"2I I ~·uIIIIIIIII~~-;:- - - - -,C luster (I/O)MemoryInterfaceProcessorInterfaceRMPMIOPDeviceControllero~Communications.-------1 InterfaceDeviceControllerDeviceControllerLineAdapterComm.LinesLineAdapterComm.LinesDual Access OptionFigure 1. A Xerox 560 Computer System90 30 76A-l (1/74)Basic Processor 9

FAST MEMORYARITHMETIC AND CONTROL UNITGENERAL REGISTER BLOCK (TYPICAL)0~1 ______________ ~1............::::::::::::::.:.:.:::. ~:~:~:~:~:~:~:~:~:~:~:) .. ~:.'~.:~:.~ .. :~..:~.:~: .. ~: .. ::.~.:~:. ...............I··············· ..-:.:-:.:..-:.:-......... ........................ .:.:.:-.........,~~~~~~~~~~~:~~;:~:;:; ~:~:~:~:~:;~~;~~~~~~~~r~~~~~:;:~:;:::::::::::::: ·t~:~r~~~~~~:-:·:·:·:·:·:·:·:·:·: .-:::::::::::::::::::::::.:.. :::::.:.:.:.:.:.:.:.:-:.:.:.:.:. ::::::::::::::::::::::::::. :::::::::::::::12 I {:rrr::r ::::::)~.:.................:. ::::)):::::::nc:::::::::::::::::::::::::::.:::::: ::::::rt~:l3(:: ::.:.:.::::::::: ..:.:.:::..... .:.:.:.:.:.:.:.. >f>~{:: ::::::::::: :.:.:.:-::::::: :::::;:::: ::: .. .. :': .. ..':.::.':':.. :~.:: ..'::::..... '.:: .. ::I Jf;~;~;;;; Itf}~}::::: ...............:.:.:.:.:..,:.::..-...-......::::::;::::::::: .. 1 ~4 1::I:::::~::::::I::::::::::::::r::r:::::j:: :::::::;:::;::::::f::t::::::::::::::; :::::::::::::::::::::::::::::::::::15 1::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::1 .::::):r::::::=::::::::::::::::·: ,::::::::::::::I:I:t::tl8~1 ______________ ~IndexRegistersINSTRUCTION REGISTERo Indirect Access FlagoIII 1111 I Operation Code Field1 7DID General Register Designator8 11ITIJ Index Register Designator12 14Reference Address Field111111111 11111111 III15 31 Memory.......--.... 1PROGRAM STATUS WORDSI/O Processors IIIIRead/Write Direct1 •InterruptsMopping• •.Access Protection.9 1 .....________......1O~1 ______________ ~11 I"--________________ ~12 ~I ________________ ~13 ~I ________ ~14 ~I _________.....15----------------------171 ~ __________......16 Jl18 I~ ________________ __19 IL... ________....20 1 .....________......21 1 ....._________31-digitDecimalAccumulatorReservedOJ]] Condition Codeo 3ITO Floating-point Mode Control5 7o Master/Slave Mode Control8D Memory Map Control9[JJ Arithmetic Trap Masks1011Instruction,..,...'T"'"T""'T'"T..,....,~'T"'"T""'I""T"'T'"'T..,....I""""I AddressId I I I I I I I I I I I " I I I or15 31 ExtendedDisplacement[ill Write Key32 35[ill Interrupt Inhibits37 39OJ Register Block Pointer5859o Register AI tered60o Mode Altered Control61L---..I :: --=---=----=------,1 ~I _--------'Figure 2. The Basic Processor10 Basic Processor

MASTER MODEThe master/slave control bit (bit 8 of the PSWs) must containa zero for the basic processor to operate in mastermode. In th is mode the basic processor can perform a II ofits control functions and can modify any part of the system.The restrictions upon the basic processor1s operations in thismode are those imposed by the write locks on certain protectedparts of memory. It is assumed that there is a residentoperating system (operating in the master mode) thatcontrols and supports the operation of other programs (whichmay be in the master, master-protected, or slave mode).high-order bits contain zeros. The memory map always maps17-bit virtual addresses into 20-bit real addresses (seeIIMemory Address Control II, later in this chapter for a discussionof how the map is used).UNMAPPED MODEWhen the basic processor is operating in the unmapped mode,there is a direct one-to-one relationship between the effectivevirtual address of each instruction and the actual addressused to access main memory. (See II Rea I Addressing ll ,later in this chapter.)MASTER-PROTECTED MODEThe master-protected mode of operation provides additionalprotection for programs that operate in the master mode. Themaster-protected mode occurs when the basic processor isoperating in the master mode with the memory map in effectand the mode altered control bit (bit 61 of the PSWs) is on.In this mode the memory protection violation trap occurs(location X I 40 I , with CC4 = 1), as it does in all mappedslave programs, if a program makes a reference to a virtualpage to which access is prohibited by the current setting ofthe access protecti on codes.INFORMATION FORMATNomenclature associated with digital information within thecomputer system is based on functional and/or physical attributes.A "word" may be either a 32-bit instruction wordor a 32-bit data word.The bit positions of a word are numbered from 0 through 31as follows:SLAVE MODEThe slave mode of operation is the problem-solving modeof the basic processor. In this mode, access protectioncodes apply to the slave mode program if mapping is in effect,and all IIprivileged II operations are prohibited. Privilegedoperations are those relating to input/output and tochanges in the fundamental control state of the basic processor.All privileged operations are performed in themaster or master-protected mode by a group of privilegedinstructions. Any attempt by a program to execute a privilegedinstruction whi Ie the basic processor is in the slavemode results in a trap. The master/slave mode control bit(bit 8 of the PSWs) can be changed when the basic processoris in the master or master-protected mode. Nevertheless,a s!aVe mode program can gain direct access to certai!1 executiveprogram operations by means of CALL instructions.-The operations avai lable through CALL instructions are establishedby the resident operating system.A word can be divided into two 16-bit parts (halfwords) inwh ich the bit positions are numbered from 0 through 15 asfollows:A word can also be divided into four 8-bit parts (bytes) inwhich the bit positions are numbered 0 through 7 as follows:Two words can be combined to form a 64-bit element (adoubleword) in which the bit positions are numbered 0through 63 as follows:MAPPED MODEAlthough the memory map is located in the Memory Interface(MI), it functions as part of the basic processor. Thebasic processor communicates with memory through the MI.Mapping is effective for all the words of real memory, andis invoked when bit 9 (MM) of the PSWs contains a one.Memory mapping generates real page addresse:s from vir-tualaddresses. The memory map can be loaded with either11-bit real page addresses or 8-bit real page addresses bymeansofthe MOVE MEMORY CONTROL (MMC) privilegedinstruction (see Chapter 3, "Control Instructions "). Elevenbitreal page addresses are always provided for in the map,thus if 8-bit real page addresses are generated, the threeI : Least Signif~cant word: In " " "I~ ~ '" '" ~ " " ,,1« " " ,,:« " '" "I" ,; ,. ,,' ~ " " "1M,, " "In fixed-point binary arithmetic each element of informationrepresents nurneiical data as a signed integer (bit 0 representsthe sign, remaining bits represent the magnitude, andthe binary point is assumed to be just to the right of theleast significant or righi-most bit). Negative va lues arerepresented in two1s complement form. Other formats requiredfor floating-point and decimal instructions are describedin Chapter 3.12 Basic Processor

INFORMATION BOUNDARIESBasic processor instructions assume that bytes, halfwords,and doublewords are located in main memory according tothe following boundary conventions:1. A byte is located in bit positions 0 through 7, 8through 15, 16 through 23, and 24 through 31 of aword.2. A halfword is located in bit positions 0 through 15 and16 through 31 of a word.3. A doubleword is located such that bit positions 0 through31 are contained within an even-numbered word, andbit positions 32 through 63 are contained within thenext consecutive word (which is odd-numbered).Figure 3 illustrates these boundaries.DoublewordDoublewordWord (even address)Word (odd address)Word (even address)Word (odd address)Halfword 0 Halfword 1 Halfword 0 Halfword 1Halfword 0 Halfword 1 Halfword 0 Halfword 1Byte O! Byte 1 Byte 2!Byte 3 Byte 0 !Byte 1 Byte 2!Byte 3 Byte O! Byte 1 Byte 2!Byte 3 Byte 0 !Byte 1 Byte 2!Byte 3Figure 3. Information BoundariesINSTRUCTION REGISTERBitsDescriptionThe instruction register contains the instruction the basicprocessor is currently executing. The format and fields ofthe two general types of instructions (memory reference andimmediate operand) are described below. Specific formatsfor each instruction are given in Chapter 3.MEMORY REFERENCE INSTRUCTIONSInstructions that make reference to an operand in main memorymay have the following format:12-14 index register. If X contains zero, indexing will(cont.) not be performed; hence register 0 cannot be usedas an index register. (See "Address ModificationExample: Indexing (Real and Virtual Addressing) ",later in this chapter for a description of theindexing process.)15-31 Reference address. Th i s 17 -b i t fi e I d norma II y containsthe reference address of the instruction operand.The reference address is translated into aneffective virtual address in accordance with theaddressing type (real, real extended, or virtual)and the address modification required (direct!indirect or indexing). (See "Memory ReferenceAddresses" later in this chapter.)Bitso1-7DescriptionIndirect addressing. One level of indirect addressingis performed only if this bit position containsa one.Operation code. This 7-bit field contains the codethat designates the operation to be performed. Seethe inside front and back covers for complete listingsof operation codes.IMMEDIATE OPERAND INSTRUCTIONSImmediate operand type instructions are particularly efficientbecause the required operand is contained within theinstruction word. Hence, memory reference, indirect addressing,and indexing are not required.8-11 R field. For most instructions this 4-bit field designatesone of the first 16 general registers of thecurrent register block as an operand source, resultdestination, or both.12-14 X field. This 3-bit field designates one of generalregisters 1-7 of the current register block as anBitsoDescriptionBit position 0 must be coded with a zero. If itcontains a one, the instruction is interpreted as beingnonexistent. (See "Trap System ", later in thischapter. )Bas i c Processor 13

Bits1-7DescriptionOperation code. This 7-bit field contains the codethat designates the operation to be performed.When the basic processor encounters any immediateoperand operation, it interprets bits 12-31 ofthe instruction word as an operand. These are theimmediate operand operation codes:possible clock and power sources. Memory units may containtwo, four, or six ports, which have a fixed priorityorder for the resolution of contention problems.The following sections describe the organization and operationof the memory system. Also described are the variousmodes and types of addressing, including indexing.OperationCodeInstructionNameMnemonicMEMORY UNIT8-1112-31X'02 1X '21 1X '22 1X'23 1Load Conditionsand Floating ControlImmediateAdd ImmediateCompare ImmediateLoad ImmediateMultiply ImmediateLCFIR field. This 4-bit field designates one of thefirst 16 general registers in the current generalregister block. The register may contain anotheroperand and/or be designated as the register inwhich the results of the operation are to bestored or a ccumu la ted.Operand. This 20-bit field contains the immediateoperand. Negative numbers are representedin two1s complement form. For arithmetic operationsbit 12 (the sign bit) is extended by duplicationto the left through bit position 0 to form a32-bit operand.AICILIMIMain memory is divided physically and logically into oneto eight module assemblies called memory units. Becausethe memory unit is a logical component that contains all thefunctions available in the entire memory, the minimum memoryis one memory unit. The minimum storage capacity permemory unit is 16K words; the maximum is 32K words. Amemory location stores a word of 36 bits; the first 32 bits areinformation and the last 4 are byte parity bits (the latterbeing unavai lable to the program). Each memory unit comprisesa specific storage capacity, drive and sense circuits,a set of operational registers (address, data, and status), aset of write lock control registers for 32K words of memory,and a timing and control unit.CORE MEMORY MODULESCore memory modules (CMMs) provide a storage facility ofstandard modules (see Figure 4).MEMORY DRIVERThe memory driver in each memory unit performs all memoryoperations except storage (provided for by the CMMs) andthe few operations performed by the ports. The major functionsof the memory driver are:The byte-string instructions (described in Chapter 3) aresimi lar to immediate-operand instructions in that they cannotbe modified by indexing. Nevertheless, the operandfield of byte-string instructions contains either a byteaddress displacement or a byte address that is a virtual addresssubject to modification by the memory map. If abyte-string instruction has a one in bit position zero, thebasic processor treats it as a nonexistent instruction (see"Trap System ", later in this chapter).MAIN MEMORYThe memory system comprises memory units, memory interfaces(MIs), and memory buses. Figure 4 illustrates the relationshipsamong these components.The primary technology for main memory is magnetic core.The maximum physical storage is 256Kwords. Memory unitscan be interleaved on a two-way interleave basis. Eachmemory unit is provided with a set of starting addressswitches on the Configuration Control Panel (see Chapter 6)together with a two-position switch that selects one of two1 • Store address word.2. Store data-in and data-out words during memorycycles.3. Store write locks in special memory (other than CMMs).4. Perform parity generation and checking on address andmemory bus data words, and on core memory modulewords.5. Generate and store status words.6. Control and time all transfers of address words, datawords, status words, write locks, and write key amongthe ports, CMM, and the storage registers.7. Control and time a!! data, parity, and. control signalsissued to the memory bus.8. Accept one of two or more simultaneous memory requestson the basis of port positional priority and otherpriority status information such as "high priority" and"memory reserved ".14 Main Memory

(Maximumof eight)Core Core Core CoreMemory Memory Memory MemoryModules Modules Modules Modules(CMM) (CMM) (CMM) (CMM)MemoryUnitMemoryMemoryMemoryMemoryMemoryMemoryMemoryUnitUnitUnitDriverDriverDriverDriver(MD) (MD) (MD) (MD)P P P P P P P P P P P P P P P P P P P P P P P P1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6Memory Bus 1I - -- --,I,L....--1Memory Bus 2I ------I IMemoryI 1MemoryT ntArfn C-A I Interface- I .---I--IIBasicfI--- RMPProcessor IIcoProcessor2 I Cluster...

PORTS AND MEMORY BUSESA memory unit may contain two, four, or six ports, whichhave a fixed priority order for the resolution of access contention.Each port allows the memory unit to communicatevia a memory bus with a different external system (i.e., aprocessor cluster), which communicates with the memorybus via the Memory Interface (MI) (see Figure 4). Portsare numbered from 1 (top priority) to 6 (lowest priority).The selection logic is biased to select port 1 (the fast port)whenever the memory is quiescent. Thus performance isimproved for the Memory Interface (MI) connected to thatport, and hence to the processors connected to that MI.A memory reserve function insures proper execution of instructionsthat require guaranteed re-access to a memorylocation before a second processor can access it.Each port is equipped with an inhibit function that canbe activated from the Configuration Control Panel (seeChapter 6).Other major functions performed by the ports are:1. Address recognition.2. Address interleaving.The memory system is built up by interconnection of identicallynumbered ports of all memory units. Each interconnectingcable is called a memory bus, which is dedicatedto a single processor cluster (see Figure 4).PORT PRIORITYThe multi port structure a I lows two simultaneous requests formemory to be processed immediately if the requests arereceived on different ports for different memory units, andneither memory unit is busy. If a requested memory unitis busy or receives simultaneous requests, the memory portlogic selects the highest priority request first.Normally, all ports in a memory unit operate on the fixedpriority basis (the fast port has the highest priority and thehighest-numbered normal port the lowest). Thus, if a singlememory unit simultaneously receives requests on port 2 andport 4, port 2 has first access to the memory unit.Each port also has associated with it a high-priority linewhich, upon receiving a high-priority request, raises theportIs priority above that of all other ports except for anyhigher priority port, which also has a high-priority requeston its line.MEMORY INTERLEAVINGMemory interleaving is a hardware feature that distributessequential addresses into two independently operating memoryunits. Interleaving increases the probabil ity that a processor(i. e., basic processor, RMP, or MIOP) can gainaccess to a given memory location without encounteringinterference from another processor that is making sequentiaI requests.Two memory units of the same size can be two-way interleaved.Both memory units transform an incoming address,as follows:Size of EachMemory Unit32K16KAddress BitsInterchanged16 and 3117 and 31As a result of the address transformation, even incoming addressesare assigned to one memory unit and odd incomingaddresses to the other. Note that the incoming address (untransformed)is stored in the status register of the accessedunit in each cycle and is available as are other types of dynamicstatus information. (Interleaved memory units havetwo status registers, one in each of the units.)MEMORY UNIT STARTING ADDRESSEach memory unit is individually identified by starting addressswitches located on the Configuration Control Panel(see Chapter 6). These switches define the range of addressesthe memory unit responds to when servicing memoryrequests. All addresses, including the starting address, fora given memory unit are the same for all ports in that unit;that is, the address of a given word remains the same regardlessof the port used to access the word. The startingaddress of a memory uni t must be on a boundary equa I to amultiple of the size of the memory unit when two memoryunits (of the same size) are interleaved. The starting addressof one memory unit must be a multiple of the size ofthe two memory units together; the second memory unit musthave a starting address higher than that of its companion byits own size. Another way to say this is that the startingaddress for the combined units must be on a boundary equalto a multiple of the total size of the interleaved assembly.MAINTAINABILITY AND PERFORMANCEMemory maintainability is enhanced by the followingfeatures:1. Error detection. Each memory unit senses and remembersparity errors in the CMM data as well as parityerrors in the address word or the memory bus data, portselection errors, CMM selection error, and undefinedoperations. This status information is available to diagnosticprograms to facilitate error localization inspace and time of occurrence. The memor,' unit sensesand reports, but does not remember (for diagnostic purposes)a write lock violation.2. Modularity. For ease of replacement, the logic and storagecircuitry is packaged on modules that are removablefrom backpanelswithoutrequiring cable disconnectiol1s.16 Main Memory

3. Diagnostic logic. Each memory driver module carrieslogic used exclusively for localizing faulty elementsin that module. The benefit derived from this diagnosticlogic depends on such external factors as the accessibilityto a module tester.Memory system performance depends on these factors:1. Access time of memory unit.2. Cycle time of memory unit.3. Type of cycle requested.4. Number of memory units.5. Interleaving.6 • Type of port (fast or norma I) selected.7. Self or mutual interference between memory requests.All these factors characterize not only memory performancebut a Iso system performance.Port access time and cycle time are essential memory speedcharacteristics pertaining to CMM operations.1. Port access time. This is the time interval measuredbetween the clock pulse that transmits an address wordfrom the Memory Interface (MI) to an idle memory unitand the clock pulse that translates a memory word fromthe same memory unit to the MI.2. Cycle time. Cycle time depends on the operation beingperformed and on the sequence of operation. Cycletime determines the maximum rate at which a memoryunit can accept requests.VIRTUAL AND REAL MEMORYVirtual memory is the address space available to an individualprogram. The maximum size of virtual memory is128K words, broken into as many as 256 pages of 512 wordseach distributed throughout the available pages of realmemory.Real memory corresponds to the physical memory, and its sizeis equal to the total number of words contained within allmemory units in the system. The size of real memory rangesfrom a minimum of 16K words to a maximum of 256K words.Note: Real memory address space is 1 mi Ilion words.MEMORY REFERENCE ADDRESSMemory locations 0 through 15 are not normally accessibleto the programmer because their memory addresses are reservedas register designators for "register-te-register" operations.Nevertheless an instruction treats any of thefirst 16 registers of the current register block as if it werea location in main memory. Furthermore, the register blockcan hold an instruction (or a series of as many as 16 instructions)for execution just as though the instruction (or instructions)were in main memory.The following terms are used in the various types of addressingdescribed in subsequent sections. See also Figure 5,which illustrates the control and data flow during addressgeneration.1. Instruction Address. This is the address of the nextinstruction to be executed. For real, real-extended,and virtual addressing the 17-bit instruction address iscontained within bits 15-31 of the program status words(PSWs) •2. Reference Address. Th is is the 17 -b i t or 20-b it addressassociated with any instruction (except that in a trapor interrupt location that has a 0 in bit position 10).For real, real extended, direct, and virtual addressing,the reference address is the address contained withinbits 15-31 of the instruction itself.The reference address may be modified by using indirectaddressing, indexing, and memory mapping. A referenceaddress becomes an effective virtual address afterthe indirect addressing and/or postindexing (if required)is performed.3. 20-Bit Trap or Interrupt Reference Address. If bit position10 of any instruction in a trap or interrupt locationcontains a 0, bits 12-31 of that instruction are used asa 20-b it reference address. Th is 20-b i t reference addresscan be modified only by using indirect addressing.This 20-bit reference address cannot be indexedor mapped. (See "Interrupt and Trap Entry Addressing",later in this chapter.)4. Direct Reference Address. If neither indirect addressingnor indexing is called for by the instruction (i. e.,if bit 0 and the X field contain zero), the referenceaddress of the instruction (as defined above) becomesthe effective virtual address. Direct addressing maybe used during real, virtual, or real extended addressingmodes, including trap and interrupt operations. Directaddressing during virtual addressing does not precludememory mapping.5. Indirect Reference Address. The 7-bit operation codefield of the instruction word format provides for as manyas 128 instruction operation codes, nearly all of whichcan use indirect addressing (except immediate-operandand byte-string instructions). If the instruction callsfor indirect addressing (bit position 0 contains a 1), thereference address (as defined above) is used to access aword location that contains the direct reference addressin bit positions 15-31, or bit positions 12-31 for certainreal extended addressing operations. The indirect addressingoperation is limited to one level, regardless ofthe contents of the word location pointed to by the referenceaddress field of the instruction. Indirect addressingoccurs before indexing; that is, the 17-bitMain Memory 17

Fetch contents of register.yesAdd 16-19 bit index to17-bit reference address;17-19 bit arithmetic.Add 20-22 bit index to17-bit direct referenceaddress or 20-bit indirectreference address; 20-22bit arithmetic.Fetch contents of 20-bitreal address. If writeoperation, trap on writeprotectviolation.Map to 20-bit real address.Trap on accessprotect violation if inslave or master-protectedmodes.Figure 5. Addressing Logic18 Main Memory

eference address field of the instruction is used toobtain a word, and the 17 or 20 low-order bits of theword thus obtained effectively replace the initial referenceaddress field; then indexing is carried out accordingto the operation code of the instruction. SeeFigures 7 and 9, later in this chapter.6. Index Reference Address. If indexing is called for inthe instruction (a value other than zero in bits 12-14of the instruction), the direct or indirect reference addressis modified by addition of the displacement valuein the general register (index) called for by the instruction(after scaling the displacement according to theinstruction type). This final reference address value(after indirect addressing, indexing, or both) is definedas the effective virtual address of the instruction. Indexingafter indirect addressing is ,ca lied postindexing.See also Figures 7 and 9, later in this chapter.7. Displacements. Displacements are the 16- to 22-bitvalues used in index registers and by byte-string instructionsto generate effective addresses of the appropriatesize (byte, halfword, word, or doubleword).8. Register Address. If any instruction provides a virtualaddress that is a memory reference (i .e., a direct,indirect, or indexed reference address) in the range 0through 15, the basic processor does not attempt to readfrom or write into main memory locations 0 through 15.Instead, the four low-order bits of the reference addressare used as a general register address and the generaI reg ister correspond i ng to th is address is used as theoperand location or result destination. Thus, the instructioncan use any of the first 16 registers in the currenTregisTer biocK as Tne source or an operand, thelocation of a direct address, or the destination of a result.Such usage is called a "register-to-register"operation.9. Actual Address. This is the address value actually usedby the basic processor to access main memory via thememory address register (see Figure 5). If the effectivevirtual address is in the range 0 through 15 (X10 throughX'F '), one of the first 16 general registers in the currentregister block is being addressed. If the basic processoris operating in the virtual addressing mode, alladdresses grea ter than 15 (X 1 F I) are transformed (usua IIyinto addresses in a different memory page) by the memorymap into actual addresses. Contrarily, if the basicprocessor is operating in either real or real extendedmode, no transformation via the memory map takes place.10. Effective Address. The effective address is defined asthe final virtual address computed for an instruction.Note, however, that some instructions do not use theeffective address as a location reference; instead, theeffective address is used to control the operation ofthe instruction (as in a shift instruction), to designatethe address of an input/output device (as in an input/output instruction), or to designate a specific elementof the system (as in a READ DIRECT or WRITE DIRECTinstruction) •11. Effective Location. An effective location is definedas the actual location (in main memory or in the currentregister block) that is to receive the result of a memoryreferencinginstruction, and is referenced by means ofan effective address. Because an effective addressmay be either an actual address or a virtual address,when applicable, this definition of an effective locationassumes the transformation of a virtual address intoan actual address.12. Effective Operand. An effective operand is definedas the contents of an actual location (in main memoryor in the current register block) that is to be used asan operand by a memory-referencing instruction, andis referred to by means of an effective address. Thisalso presupposes the transformation of a virtual addressinto an actual address.TYPES OF ADDRESSINGExcept for the special type of addressing performed by someinterrupt and trap instructi ons, all addressing within thecomputer system is real, real extended, or virtual.REAL ADDRESSINGIn real addressing, a one-to-one relationship prevails betweenthe effective virtual address of each instructionand the actual address used to access main memory. Realaddressing has these characteristics:1. Each reference address is a 17-bit word address.2. The reference address may be direct or indirect, withor without postindexing.3. Displacements associated with indexing are automaticallyaligned, as required, using the full 32-bit contentsof the index register. The final result is truncated tothe left of the high-order bit of the original 17-bit referenceaddress, and the effective real address is a16-bit doubleword address, 17-bit word address, 18-bithalfword address, or a 19-bit byte address.4. If indirect addressing is invoked, the 17-bit referenceaddress in the instruction word is used to access the indirectaddress word in memory. The low-order 17 bitsof this word then replace the reference address of theinstruction word in the calculations described in (3),above.5. Memory mapping and memory access protection arenever invoked.6. Memory write protection is automatically invoked.7. Leading zeros are automatically appended to the effectiveaddress to generate an actual word address as requiredby the main memory.Main Memory 19

8. Real addressing is allowed in master mode and in slavemode, and is specified when bit positions 9 and 61 ofthe PSWs both contain zero.VIRTUAL ADDRESSINGVirtual addressing uses the memory map to determine theactual address to be associated with a particular referenceaddress of each instruction. Virtual addressing differs fromreal addressing in that there is normally no exact relationshipbetween the effective virtual address and the actualaddress. These are the characteristics of virtual addressing:1. Each reference address is a 17-bit address.2. The reference address may be direct or indirect, withor without postindexing.3. Displacements associated with indexing are automaticallyaligned, as required, using the full 32-bitcontents of the index register. The final result istruncated to the left of the high-order bit of theoriginal 17-bit reference address, and the effectivevirtual address is a 16-bit doubleword address, 17-bitword address, 18-bit halfword address, or a 19-bit byteaddress.ADDRESS MODIFICA nON EXAMPLE: INDEXING(REAL AND VIRTUAL ADDRESSING)Figure 6 shows how the indexing operation takes place duringreal and virtual addressing operations. The instructionis brought from memory and loaded into a 34-bit instructionregister that initially contains zeros in the two low-orderbit positions (32 and 33). The displacement value from theindex register is then aligned with the instruction register(as an integer) according to the address type of the instruction;that is, if it is a byte operation, the low-order bit ofthe displacement is aligned with the least significant bit ofthe 34-bit instruction register (bit position 34). The displacementis then shifted one bit to the left of this positionfor a halfword operation, two bits to the left for a wordoperation, and three bits to the left for a doubleword operation.An addition process then takes place to develop a19-bit address, referred to as the effective address of theinstruction. High-order bits of the 32-bit displacement areignored in the development of this effective address (i .e.,the 15 high-order bits are ignored for word operations, the25 high-order bits are ignored for shift operations, and the16 high-order bits are ignored for doubleword operations).The displacement value, however, can cause the effectiveaddress to be less than the initial reference address (withinthe instruction) if the displacement value contains a sufficientnumber of high-order 12's (i .e., if the displacementvalue is a negative integer in two's complement form).4. Virtua I memory access protection is always invoked.If the access protection code is invalid, the instructionaborts and traps to location X'40'. (See "Trap System",later in this chapter.)5. Memory mapping translates the 8 most significant bitsof the effective virtual address (the page portion) intoan l1-bit page address. This page address is concatenatedwith the 9 least significant bits of the referenceaddress. The resultant 20-bit word address is the actualaddress used to access memory. This feature permitsanyone user at any given time to have a virtual memoryof as many as 128K words (256 pages) locatedthroughout real (actual) memory comprising as manyas 256K words (512 pages). Although virtual memorymay be physically fragmented, it is logically contiguous.Note that Sigma 6/7 programs may run on this computersystem without requiring change to the mapping structure.The memory map is loaded with 8-bit page addresses(the 3 high-order bits of the ll-bit real pageaddress are reset to zeros). The most significant 8 bitsof the effective virtual add.-ess are then translated intothe designated 8-bit page address.The effective virtual address of an instruction is always a19-bit byte address value. This value, however, is automaticallyadjusted to the information boundary conventions.Thus, for halfword operations the low-order bit of the effectivehalfword address is zero; for word operations the twolow-order bits of the effective word address are zeros; andfor doubleword operations the three low-order bits of theeffective doubleword address are zeros.In a byte operation with no indexing, the effective byteis the first byte (byte 0 in bit positions 0-7) of a word location;in a halfword operation with no indexing, the effectivehalfword is the first halfword (halfword 0 in bitpositions 0-15) of a word location. A doubleword operationalways involves a word at an even numbered addressand the word at the next sequential (which is odd numbered)word address. Thus, if an odd numbered word locationis specified for a doubleword operation, the low-order bit ofthe effective address field (bit position 31) is automaticallyforced to zero. This means that in a doubleword operationan odd numbered word (reference) address designates thesame doubleword as the next lower even numbered wordaddress.6. The memory writp.-protedion fp.otlJre is invokp.rl for thE?actual address in real memory.7. Virtual addressing may be used in all modes (master,master-protected, and slave) and is specified whenbit 9 of the PSWs contains a one.In the real addressing mode, the 19-bit effective virtualaddress is concatenated with 3 leading zeros to form a22-bit actual address. In the virtual addressing mode,the 8 most significant bits of the 19-bit virtual addressare mapped (using the memory map) into the ll-bit actualpage address, thus forming a 22-bit actual address.20 Main Memory

Instruction in memory:Instruction in instruction register:Byte operation indexing 01 ignment:I IIIIHalfword operation indexing 01 ignment:Word operation indexing 01 ignment:Shift operation indexing alignment:Doubleword operation indexing 01 ignment:Effect i ve vi rtua I address:Figure 5. Index Displacement AI ignment (Real and Virtual Addressing Modes)ADDRESS MODIFICA nON EXAMPLE: INDIRECT,INDEXED HALFWORD (VIRTUAL ADDRESSING)Figure 7 illustrates the address modification and mappingprocess for an indirectly addressed t indexed, halfword operation.As shown, reference address 1 is the content ofthe reference address field in the instruction stored in memory.The instruction is brought into the instruction register,and if the value of the reference address field is greaterthan 15, the memory map converts the 19-bit effective virtualaddress into a 22-bit actual address. The 17 low-orderbits of the main memory location pointed to by the actualaddress, labeled reference address 2, then replaces referenceaddress 1 in the instruction register. The index registerdesignated by the X field of the instruction is subsequentlyaligned for incrementing at the halfword-address level. Thefinal effective virtual address is formed by the address generator,and if the value of the reference address is greaterthan 15, the effective virtual address is transformed throughthe memory map into an actual address. The resultant 22-bitactual (main memory) address, which automatically containsa low-order 0, is then used to access the halfword to beused as the operand for the instruction.Note that for the real addressing mode, the modificationsrequired for indirect, indexed halfword operation are thesame with one exception: reference address 1 and the finaleffective address are concatenated with three leading zeros(as opposed, to being transformed by the memory map).REAL-EXTENDED ADDRESSINGReal-extended addressing is similar to real addressing in thata direct relationship exists between the effective virtual addressof each instruction and the actual address. The functionof real-extended addressing is to foci litate operationsin a memory system larger than 128K words.Note: Instructions and indirect addresses that involvereal-extended address calculations must themselvesreside in the first 128K words of memory (or in thegeneral registers), although they in turn may ultimatelyaccess operands in locations beyond the first128K words of memory.Main Memory 21

Instruction in memory:Instruction in instruction registers:The 8 high-order bits of the reference address arereplaced with ll-bit page address Z from memory map:Actual address of memory location that containsthe direct address:17-bit direct address in memory:Indi rect addressing replaces reference addresswith direct address:,-------~·------~'r~------~~~----~22-bit actual addressIIIIIIHalfword operation indexing alignment:Effective virtual address:I II I1119-bit virtual1halfword address Il, I... l, I ... I ... I ... I, I, , , , , " , , , £"I" " """ "r\." I I I I I I I I I I VI15116 17 18 19120 2122 2312425 26 27128 29 30 31 1 3233,...The 8 high-order bits of the effective address arereplaced with ll-bit page address N from memory map:\.o 1 2 3 4 5... I1 IFinal memory address, which is the actual address ofhalfword location containing the effective halfword:Figure 7. Generation of Actual Addresses Indirect, Virtual Addressing22 Main Memory

Real-extended addressing is specified when PSWs bitlocation 9 contains zero and PSWs bit location 61 containsone. In real-extended addressing, the 17-bit referenceaddress in the instruction word is expanded to a 20-bit referenceaddress by the appendage of 3 bit positions to theleft of the reference address (see Figure 8). If indexing orindirect addressing are not specified in the instruction,these 3 bit positions contain zeros. Otherwise, addresscalculations are performed in this manner: If indexing isspecified (X field in the instruction contains a value otherthan zero), the contents of the specified index register areproperly al igned with respect to the 17-bit reference addressaccording to the general alignment rules. Arithmeticon the aligned quantities then takes place using the full32-bit contents of the index register. The fina I resul t istruncated 3 bits to the left of the original 17-bit referenceaddress, these 3 bits having been acquired from the indexregister plus any carry resulting from the addition of the17-bit reference address with the index register contents.appropriate alignment of the 32-bit contents of the indexregister is then made and the addition operation performed.The result is truncated to the left of the 20-bit operand obtainedfrom the indirect address word.In real-extended addressing, 20-bit address calculationsactually encompass 22-, 21-, 20-, and 19-bitcalculations,respectively, for byte, halfword, word, and doublewordalignments (see Figures 8 and 9).The stack pointer doubleword for push-down instructionscontains a 20-bit word address for the top of stack addressfield, as shown in the following format:If the instruction specifies indirect addressing (bit position 0contains one), the 17-bit reference address is used to accessan indirect word in memory. The low-order 20 bits ofthe indirect word then replace the 17-bit reference addressfrom the instruction. If indexing is also specified, theInstruction in memory:T~.~~"",,..":~~ .. ~,......I 1-. .. ,......I....I~,..~~'&"11_1111-11_.1 _0./1...., ..... .." _ ..... ""'I....,~...,generator:' ___ 1 ___ -_IIIIUCACUnot indexedByte operation indexing alignment:Halfword operation indexing alignment:Word operat!on indexing al ignment:Shift operation indexing alignment:Doubleword operation indexing alignment:20-bit effective address:I IFigure 8. Index Displacement Alignment (Real-Extended Addressing)Main Memory 23

Instruction in memory:Instruction in instruction register:Indi rect reference addresses:IIIr]-o -]]-1-]2-]-3-]4"']:....::-6-:-]:-]-:I-:-2-f ]-:-2-:3-1-::-4-~-5-:-2-:-1:-8-~9-:o--':,lo 0Contents of indirect reference address:Address used if bit 0 = 1:Displacement aligned for halfword indexing:Final effective address:Figure 9. Generation of Effective Virtual Address (Indirect Real-Extended Addressing)These are the register formats for byte-string instructions:Register Rul:Byte-string instruction:20-bit signed disp acement,sign extended before useRegister R:During real-extended addressing memory write protectionis invoked.Table 1 summarizes the addressing characteristics.24 Main Memory

Table 1. Basic Processor Operating Modes and Addressing CasesPSW BITMS MM MA Mode and Addressing Characteristics0 0 0 Master mode, unmapped, 17-bit calculations, real addressing (128K words, maximum).1 0 0 Slave mode, unmapped, 17-bit calculations, real addressing (128K words, maximum).0 0 1 Master mode, unmapped, 20-bit calculations, real-extended addressing, 17-bit instruction referenceaddress (instructions and indirect words in first 128K words only), indexed and indirect addresses are20 bits.1 0 1 Slave mode, unmapped, 20-bit calculations, real-extended addressing, 17-bit instruction referenceaddress (instructions and indirect words in first 128K words only), indexed and indirect addresses are20 bits.0 1 0 Master mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum), map to1M words, real (Sigma 6/7 map to first 128K words by virtue of loading map with three high-orderzeros for all pages).1 1 - Slave mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum), map to1M words, real (Sigma 6/7 map to first 128K words by virtue of loading map with three high-orderzeros for a II pages).0 1 1 Master-protected mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum),map to 1 M words, rea I (access protection invoked).INTERRUPT AND TRAP ENTRY ADDRESSINGAn instruction residing in an interrupt location (see "CentralizedInterrupt System" later in this chapter! and executedasthe directresultof an interruptsequence is definedas an interrupt instruction. Both conditions must be truesimultaneously. Thus an instruction in an interrupt locationis not an interrupt instruction if it is executed as the resultof a program branch to the interrupt location under normalprogram control. The only va I id interrupt instructions areXPSD, PSS, MTW, MTH, and MTB.Similarly, a trap instruction (see "Trap System", later inthis chapter) is defined as an instruction in a trap locationexecuted as a direct result of a trap condition. The onlyvalid trap instructions are XPSD and PSS.XPSD Address Calculations. Address calculations associatedwith XPSD instructions deviate from the standardforms. Two basic formats are used in XPSD instructions,depending on whether subjective or objective addressingis being used.Bit 10 of the XPSD instruction is the addressing type (AT)designator. In the circumstances described below, it designateswhether the reference address in the XPSD instructionis to be considered unconditionally as a 20-bit realaddress or whether the current mode of addressing calculationsis to be appl ied to it.Format 1:Format 2:Format 1 is used in these circumstances:1. Bit position 10 (AT) of the XPSD contains zero. In thisforma t the reference address is a 20-b it actua I address(i .e., no mapping). Note that this is true regardlessof whether the instruction is in a trap, interrupt, ornormal location and independent of the mode (mapped,unmapped, real-extended) of the current PSWs. If indirectaddressing is specified, the indirect word containsa 20-bit address with exactly the same properties.2. Bit position 10 (AT) oftheXPSD contains one, theinstructionis in a trap or interrupt location, the instructionis being executed as the result of a trap or interrupt,and the current mode of the PSWs is not rea I-extended.In this format, the reference address is a 20-bit actualMa i n Memory 25

11-bit page address in the accessed element of the memorymap array replaces the 8 high-order bits of the virtual addressto produce the actual address of the main memory locationto be used by the instruction (20-bit word addressthat is automatically adjusted as required for doubleword,halfword, or byte operation). See Figure 7.Note: If the 11-bit page address in the accessed elementof the memory map is all zeros, and an actual addressis produced that corresponds to a word addressin the range 0 through 15, when the ll-bit pageaddress is combined with the 9 low-order bits of thevirtual address, the corresponding general registerin the current register block is not accessed. Inthis one particular instance a word address in therange 0 through 15 corresponds to an actual mainmemory location rather than a general register.REAL MEMORY WRITE LOCKSAdditional memory protection, independent of the accessprotection, is provided by a write lock and key technique.A 4-bit write protect lock (WL) is provided for each 512-word page of actual memory. Thus, for the maximum 1Mwordreal memory there would be 2048 4-bit write locks.Write locks are assigned to pages of actual addresses asfollows:Actual addressesX'6oo '-X'7FF'Actual addressesX'400'-X'5FF'Actual addressesX'200'-X'3FF'Actual addressesO-X'l FF'(memory page 0)ActualaddressesX'1FEoo'X'l FFFF'(memorypage 255)ActualaddressesX'1FCOO'X' 1FDFF'2. A key value of 0000 is a "skeleton II key that will openany lock; thus write access to any memory page is permittedindependent of its lock value.3. A lock value other than 0000 for a memory page permitswrite access to that page only if the key value(other than 0000) is identical to.the lock value.Thus a program can write into a given memory page if thelock value is 0000, if the key value is 0000, or if the keyvalue matches the lock value.Note: The memory access protection feature operates duringvirtualaddressingmodes and on virtual addresses,whereas the memory write protection feature alwaysoperates on actua I memory addresses. Thus, if thememory access protection feature is invoked (thatis, if the basic processor is operating in the slavemode or the master-protected inode and is usi ng thememory map), the access protection codes are examinedwhen the virtual address is converted intoan actual address. Then the lock and key are examinedto determine whether the program (master,master-protected, or slave mode) is allowed to alterthe contents of the main memory location correspondingto the final actual address. If an instruction attemptsto write into a write-protected memory page,the basic processor aborts the instruction, and trapsto location X 140 1 , the "nonallowed operation" trap(see "Trap System ", later in this chapter). If anI/O procedure attempts to write into a writeprotectedmemory page, the write lock violation bitin the lOP sta tus byte is set, and can be tested bythe AIO, TIO, and TDV instructions.PROGRAM STATUS WORDSThe critical control conditions of the basic processor are definedwithin 64 bits of information collectively referred toas the program status words (PSWs). The current PSWs maybe considered as one 64-bit internal basic processor register,although they actually exist as a collection of separate registersand flip-flops (see Figure 2 appearing earlier in thischapter). When stored in memory, the PSWs have the followingformat:The write protect locks can be changed only by executingthe privileged instruction MOVE TO MEMORY CONTROL(see Chapter 3, "Control Instructions").The write key (a 4-bit field in the PSWs for any operatingprogram, or in the command doubleword for I/o operations)works in conjunction with the write lock to determinewhether any program (slave, master-protected, or mastermode) can write into a specific page of main memory iocations.The write key and lock control access for writingaccording to these rules:They may be optionally followed by an additional two wordswith the following format:1. A lock value of 0000 means that the correspondingmemory page is unlocked; write access to that page ispermitted independent of the key value.28 Main Memory

DesignationFunctionDesignationFunctionCC Condition code. This generalized 4-bitcode indicates the nature of the results of aninstruction. The significance of the conditioncode bits depends upon the particular instructionjust executed. After an instruction isexecuted, the BRANCH ON CONDITIONSSET (BCS) and BRANCH ON CONDITIONSRESET (BCR) instructions can be used singlyor in combination to test for a particular conditioncode setting. (These instructions aredescribed in Chapter 3, "Execute/BranchInstructions") •FRFSFZIn some operations onlya portion of the conditioncode is involved; thus, the term CC 1refers to the first bit of the condition code,CC2 to the second bit, and CC3 and CC4,respectively, to the third and fourth bits. Anyprogram can change the current value of thecondition code by executing either the LOADCONDITIONS AND FLOATING CONTROLIMMEDIATE (LCFI) or the LOAD CONDITIONS AND FLOATING CONTROL (LCF)instruction. Any program can store the currentcondition code by executing the STORECONDITIONS AND FLOATING CONTROL(STCF) instruction. These instructions aredescribed in Chapter 3, ;;Load/~toreInstructions" .Floating round mode control (see FN below).Floating significance mode control (see FNbelow).Floating zero mode control (see FN below).MS Master/slave mode control. The basic processoris in the master mode when this bit andthe mode altered bit (bit 61) both containzero; it is in the slave mode when this bitcontains one. (See MS for a description ofmaster-protected mode.) A master mode ormaster-protected mode program can changethis mode control bit by executing theLOAD PROGRAM STATUS WORDS (LPSD),EXCHANGE PROGRAM STATUS WORDS(XPSD), PUSH STATUS (PSS), or PULL STATUS(PLS) instruction. These privi leged instructionsare described in Chapter 3, "ControlInstructions" •MM Memory map control. The memory map is ineffect when this bit position contains a one.A master mode or master-protected mode programcan change the· memory map control byexecuting an LPSD, XPSD, PSS, or PLSinstruction.DM Decimal mask. The decimal arithmetic trap(see "Trap System", later in this chapter) ispermitted to occur when this bit position containsa one. The conditions that cause adecimal arithmetic trap are described in Chapter3, II Decimal Instructions". The decimaltrap mask can be changed by a master modeor master-protected mode program executingthe LPSD, XPSD, PSS, or PLS instruction.AMArithmetic mask. The fixed-point arithmeticoverflow trap is permitted to occur when thisbit contains one. The instructions that cancause fixed-point overflow are described inthe section "Trap System", later in this chapter.The arithmetic trap mask can be changedby a master mode or master-protected modeprogram executing an LPSD, XPSD, PSS, orPLS instruction.FNFloating normalize mode control. The fourfloating-point mode control bits (FR, FS, FZ,and FN) control the operation of the basicprocessor with respect to invoking the roundoffmode of floating-point calculations,checking floating-point significance, generatingzero results, and normalizing theresults of floating-point additions and subtractions,respectively. (The floating-pointmode controls are described in Chapter 3,"Floating-Point Instructions".) Any programcan change the state of the current floatingpointmode controls by executing either theLCFI or the LCF instruction. Any program canstore the current state of the current floatingpointmode controls by executing the STCFinstruction.IAWKCIIIInstruction address. This 17-bit field containsthe virtual address of the next instruction tobe executed.Write key. This field contains the 4-bit keyused in conjunction with a write lock in thememory write protection feature. A mastermode or master-protected mode program canchange the value of the write key by executingan LPSD, XPSD, PSS, or PLS instruction.Counter interrupt group inhibit (see EI, below).Input/output interrupt group inhibit (see EI,below).Main Memory 29

DesignationFunctionEI External interrupt group inhibit. The threeinterrupt group inhibit bits (CI, II, and EI)determine whether certain interrupts are allowedto occur. The function of these groupinterrupt inhibits are described in "Centralized Interrupt System ", later in th is chapter.A master mode or master-protected mode programcan change the group interrupt inhibitsby executing an LPSD, XPSD, PSS, PLS, orWRITE DIRECT (WD) instruction. These privilegedinstructions are described in Chapter3, "Control Instructions ".When all the conditions for acknowledging the interrupthave been achieved, the basic processor stops executingthe current program and executes the instruction in the correspondinginterrupt location. After the basic processor hassuccessfully accessed the interrupt instruction, it advancesthe interrupt level to the active state. The basic processormay actually execute many program instructions betweenthe time that the interrupt-requesting condition is sensedand the time that the actual interrupt acknowledgment occurs.After the interrupt is completely processed, the basicprocessor returns to the interrupted program and resumes itsexecution.RPRegister pointer. This 2-bit field selects oneof the 4 possible blocks of general-purposeregisters as the current register block. Amaster or master-protected mode program canchange the register pointer by executingLPSD, XPSD, PSS, PLS, or the LOAD REGISTER POINTER (LRP) instruction. LRP isdescribed in Chapter 3, under "ControlInstructions" •STATES OF AN INTERRUPT LEVELAn interrupt level is mechanized by means of three flipflops.Two flip-flops are used to define four mutually exclusivestates; disarmed, armed, waiting, and active. Thethird flip-flop provides the disabled/enabled function andis independent of the defined state. The various states andthe conditions of interrupt levels are described in the followingparagraphs. Figure 10 conceptually illustrates theoperational state changes of a typica I interrupt level.RA Register altered bit. When a trap occurs,this bit is set to one when any general registeror location in memory has been alteredin the execution or partial execution of theinstruction that caused the trap.MAMode altered. This bit is used to invoke boththe master-protected mode of operation andthe real-extended addressing mode). Table 1detai Is the function of the setting of this bitin conjunction with the setting of the MS(bit 8)and MM (bit 9) fields. The bits are setby an LPSD, XPSD, PSS, or PLS instruction.MP Memory protection violation address. If theX PSD instruction is being executed in a traproutine as a result of a memory protectionviolation and the SP bit in the XPSD is a one,the effective virtual address causing theviolation is stored in the fourth word. Thisstorage may be invoked so that memory protectionviolations can be recorded.DISARMEDWhen an interrupt level is in the disarmed state, no signalis admitted to that interrupt level; that is, the level neitheraccepts nor remembers an interrupt event, nor is any programinterrupt caused by it at any time.Although an interrupt level can change from any state tothe disarmed state, only a special form of the WRITE DIRECTinstruction (WD) can cause a disarmed level to change toanother state. The WD instruction is described in Chapter3, "Control Instructions ".ARMEDWhen an interrupt level is in the armed state, it can acceptand remember an interrupt signal. The receipt of such a signaladvances the interrupt level to the waiting state whereit remains until it is allowed to advance to the active state.A special form of the WD instruction can cause an armedlevel to be advanced directly to the active state.CENTRALIZED INTERRUPTSThe system includes a single, centralized interrupt feature.A II int.orrllntc; nr"" t""rrninnt.orl in thQ ,,,darn r .... ntrnl Pr ...._........_.. _....__._ ._......._. __ ......__,_._00. __.... _..._cessor. The System Control Processor is described earl ierand also in Chapters 5 and 6.When a condition that wil I result in an interrupt is sensed,a signal is sent to the corresponding interrupt level. Ifthat level is "armed", it advances to the waiting state.A level can change from any state to the armed state.WAITINGFor an interrupt level to be in the waiting state, that levelmust have been previously armed and received an interruptsignal. The signal may have been generated externally,internally, or have resulted from a WD operation. Anysignals received by an interrupt level already in the waitingstate are ignored.30 Centralized Interrupts

InterruptStateDisarmedArmed[$Waiting[$FF Configuration~i"III'LevelEnableSource ofChange SignalBasic ProcessorBasic Processoror External Signal~II--- Bas i c ProcessorInterrupt TimingActive~IGroup Inhibit offNo higher-priority level active,or waiting and enabledFigure 10. Operational States of an Interrupt LevelWhen an interrupt level is in the waiting state, the followingconditions must all exist simultaneously before the leveladvances to the active state:1. The level must be enabled (i .e., its enable/disablefl ip-flop must be set to one).2. The group inhibit (CI, II, or El, if applicable) must bezero.3. No higher-priority interrupt level is in the activestate, or is in the waiting state, enabled, and notinhibited.4. The basic processor must be at an interruptible pointin the execution of a program.Note that one or more interrupt levels of higher priority canalso be in the waiting state if they are disabled, inhibited,or both disabled and inhibited.Generally, if the enable/disable flip-flop is off (level isdisabled), the interrupt level can undergo all state changesexcept that of moving from the waiting to the active state(see exception case, below). Furthermore, if the interruptlevel is disabled, it is completely removed from the chainthat determines the priority of access to the basic processor.Thus a disabled interrupt level in the waiting state does notprevent an enabled, waiting interrupt level of lower priorityfrom moving to the active state.Note this exception to the foregoing description: Althoughgenerally no interrupt level can move from the waiting stateto the active state unless it is enabled, a specia I form of theWD instruction can move a waiting level to the active statewhether or not the level is enabled.ACTIVEAfter the basic processor has successfully accessed the interruptinstruction, then the interrupting level advances tothe active state. When all the conditions for acknowledgmenthave been achieved, the interrupt level causes theCentral ized Interrupts 31

~ ___basic processor to execute the contents of the assignedinterrupt location as the next instruction. (Interrupt locationsare defined in II Physical Organization ll , later in thischapter.) The instruction address portion of the program status~ords (PSWs) remains unchanged unti I the instruction inthe interrupt location is executed.The instruction in the interrupt location must be one of thefollowing: XPSD, PSS, MTS, MTH, or MTW. If the executionof any other instruction in an interrupt location is attemptedas the result of an interrupt level advancing to theconditions for acknowledgment, an instruction exceptiontrap occurs.The use of the privileged instruction XPSD or PSS in an interruptlocation permits an interrupt-servicing routine tosave the entire current machine environment. If workingregisters are needed by the routine and additional registerblocks are avai lable, the contents of the current registerblock can be saved automatically with no time loss. Thisis accomplished by changing the value of the register pointer(using the LOAD REGISTER POINTER instruction), whichresults in the assignment of a new block of 24 registers tothe routine. The instruction LOAD REGISTER POINTER(LRP) is described in Chapter 3, IIControl Instructions ll •An interrupt level remains in the active state until it iscleared (removed from the active state and returned to thedisarmed or armed state) by the execution of the LPSD, PlS,or WD instruction. An interrupt-servicing routine can itselfbe interrupted (whenever a higher priority interrupt levelmeets all the conditions for becoming active) and then continued(after the higher priority interrupt is cleared). However,an interrupt-servicing routine cannot be interruptedby an interrupt of the same or lower priority as long as thehigher priority interrupt level remains in the active state.Any signals received by an interrupt level in the activestate are ignored. Norma lIy, the interrupt-servicing routineclears its interrupt level and transfers program controlback to the point of interrupt by means of an LPSD instructionwith the same effective address as the XPSD instructionin the interrupt location.transmission is delayed until the new inhibit states of thebasic processor are known; these states are transmitted tothe interrupt system so the latter can record the new basicprocessor status.DIALOGUE DURING AN INTERRUPT-EXITING SEQUENCEWhen the basic processor exits an interrupt-servicing routine,it must notify the interrupt system to move the interruptlevel associated with that routine from the active state toeither the armed or disarmed state. To do this it must gainaccess to the processor bus and the interrupt system, eitherof which maybe busy at the time access is requested. Whencommunication with the interrupt system is established, thebasic processor transmits information for setting the levelstate to armed or disarmed, and new inhibit states it has assumedas a result of the exit operation.PHYSICAL ORGANIZATIONUp to 62 interrupt levels are available, each with a uniquelocation (see Table 2) assigned in the System Control Processor,and with a unique priority. The basic processor canselectively arm, enable, or arm and enable any interruptlevel. The basic processor can also IItriggerll any interruptlevel (supply a signal at the same physical point where thesigna I from the externa I source wou Id enter the interruptlevel). The triggering of an interrupt permits testing specialsystems programs before the special systems equipmentis available. The basic processor also permits an interruptservicingroutine to defer a portion of the processing associatedwith an interrupt level by processing the urgentportion of an interrupt-servicing routine, triggering a lowerpriority level (for a routine that handles the less urgentpart), then clearing the high-priority interrupt level so thatother interrupts can occur before the deferred interrupt re-~_ :~ _____~~_..J~I"'V"~" ,~ 1"" v\.. ........ u.DIALOGUE BETWEEN THE BASIC PROCESSOR ANDTHE INTERRUPT SYSTEM DURING AN INTERUPTENTERING SEQUENCEWhen an interrupt level is ready to be moved to the activestate, a dialogue takes place between the interrupt systemand the basic processor. This dialogue takes place over theprocessor bus and involves the Processor Interface (PI) associatedwith the processor cluster of which the basic processoris a member. When the processor bus becomes avai lableand the basic processor is ut un interruptible point, the interruptsystem transmits the interrupt address to the basicprocessor. It initiates its interrupt actions (i.e., executesthe instruction in the interrupt location and services theinterrupt at the appropriate time to avoid race conditions,and communicates with the interrupt system with an indicationto move the level to the active state. This latterINTERRUPT GROUPSInterrupt levels are organized in standard group configurationsthat are connected in a predetermined and fixed prioritychain (see Table 2 and Figure 11). The priority of eachlevel within a group is fixed; the first level has the highestpriority and the last level has the lowest.INTERNAL INTERRUPTSStandard internal interrupts are provided with the systemand include all group D levels (interna I override t counterequaIs-zero, and I/O).32 Centra I ized Interrupts

AddressTable 2. Interrupt LocationsDIO AddressPSWsRegisterGroup Dec Hex Function Inhibit Group BitInternalOverride(optional)82 52 Counter 1 count pulse 1683 53 Counter 2 count pulse 1784 54 Counter 3 count pulse 1885 55 Counter 4 count pulse none 0 1986 56 Processor fault 2087 57 Memory Fault 21112 70 16113 71 17114 72 18115 73 19116 74 20External 117 75 External group 3 EI 3 21Override 118 76 (first 12 levels) 22119 77 23120 78 24121 79 25122 7A 26123 7B 2788 58 Counter 1 zero 22Counter- 89 59 Counter 2 zero CI 0 23Equals-Zero 90 5A Counter 3 zero 2491 5B Counter 4 zero 25I/O92 5C Input/Output 2693 50 Control panel 2794 5E Reserved II 0 2895 5F Reserved 29ExternalGroup 2(optional)96 60 16Externa I group 2 EI 2(first 12 levels)107 6B 27ExternalGroup 4(optional)128 80 16External group 4 EI 4(first 12 levels)139 8B .27ExternalGroup 5(optional)144 90 16I Externa I group 5 EI 5(fi rst 12 leve Is)155 9B 27Centralized Interrupts 33

1st Priority 2nd Priority 3rd PriorityInternal External Counter-Override Override Equals-ZeroInterrupts Interrupts Interrupts4th Priority 5th Priority 6th PriorityExternalExternalI/o Interrupts Group 2 Group 4InterruptsInterrupts7th PriorityExternalGroup 5InterruptsFigure 11. Interrupt Priority ChainInternal Override Group (Locations X'52 1 through X'571).The six interrupt levels of thi!> group always have the highestpriority in the system. The four count-pulse interrupt levelsare triggered by pulses from clock sources. Counter 4 hasa constant frequency of 500 Hz. Counters 1, 2, and 3 canbe individua IIy set to any of four manually switchable frequencies- the commercial line frequency, 500 Hz, 2000 Hz,or a user-supplied external signal - that may be differentfor each counter. Each of the count pulse interrupt locationsmust contain one of the modify and test instructions(MTB, MTH, or MTW), an XPSD, or a PSS instruction.H/'-_._ l.'- ____ J!C! __ l.! __ f_C .. L _ _ CC __ L! .• _ L .. L_ L_IC ... __ J __VYIII::I1 1111:: IIIUUIII~UIIUIi \UI 1111:: 1::111::~IIVI:: Uyll::, IIUIIVVUIU, UIword) causes a zero result, the appropriate counter-equalszerointerrupt level (see "Counter-Equals-Zero Group") istriggered.Note: Count pulse interrupt level 4 is a subjective timecounter with the following special attribute: Whenthe instruction in location X '55 1 is executed as theresult of an interrupt, it must be an MTB, MTH, orMTW; otherwise, an instruction exception trap(X '40') will occur.The internal override group also contains a processor faultand a memory fault interrupt level. Both locations norma IIycontain an XPSD or a PSS instruction. The processor faultinterrupt level is triggered by a signal when certain faultconditions are detected. A POLR instruction must be usedto reset the fault. The memory fault interrupt level istriggered by a signal that the memory generates when itdetects certain fault conditions. An LMS instruction mustbe used to reset the fault. (See "Trap System" later inthis chapter for further information on processor and memoryfaults.)Counter-Equals-Zero Group (Locations X 158 1 through X '5B ').Each interrupt I eve lin the counter-equa Is-zero group is associatedwith a corresponding count-pulse interrupt level inthe internal override group. When the execution of a mod-!c.. __ J L __ L ! __.L_•• _L! __ :_ .. L ___•. _ ..__•. 1 __ !_j.___.._j. 1 ___.. : __Ily UIIU IC;)I III;)IIU~IIUII III IIIC ~UUIII-I"UI;)C IIIICIIUI"I IU~UIIUIIcauses a zero result in the effective byte, halfword, or wordlocation, the corresponding counter-equals-zero interruptlevel is triggered. The counter-equals-zero interrupt locationsnormally contain an XPSD or a PSS instruction andthey can be i nh ib i ted or permitted as a group. If bit 37(CI) of the current PSW contains a zero, the counter-equalszerointerrupt levels are allowed to interrupt the programbeing executed. If the CI bit contains a one, the counterequals-zerointerrupt levels are inhibited from being allowedto interrupt the program. These interrupt levels wait untilthe C I bit is reset to zero and then interrupt the program accordingto priority.Input/Output Group (Locations X '5C through X '5F'). Thisinterrupt group comprises the input/output (I/O) interruptlevel, the control panel interrupt level, and two levels reservedfor future use. The I/O interrupt level accepts interruptsigna Is from the I/o system. The I/O interrupt location34 Centralized Interrupts

is assumed to contain an XPSD or a PSS instruction thattransfers program control to a routine for servicing all I/ointerrupts. The I/o routine should contain an ACK NOWLEDGE I/o INTERRUPT (AIO) instruction that identifies thesource and reason for the interrupt. (The AIO instruction isdiscussed in Chapter 3 "Input/Output Instrudions".)The control panel interrupt level is activated from the operator1sconsole. This location normally contains an X PSDor a PSS instruction. The operator can thus trigger this interruptlevel to initiate a specific routine.The interrupt levels in the I/o group can be inhibited orpermitted by means of bit position 38 (II) of the PSWs.If II is reset to zero, interrupt signals affecting the I/ogroup interrupt levels are allowed to interrupt the programbeing executed. If the II bit is set to one, interruptsignals in this group are inhibited from interrupting theprogram.EXTERNAL INTERRUPTSA system can contain 4 optional groups of external interruptlevels. The external override group, group 3, containsthe first 12 external interrupt levels. External groups 2,4, and 5 each contain 12 external interrupt levels. (SeeTable 2 and Figure 11.) External levels may be triggeredby external sources or via WD instructions, while internallevels may be triggered by internal sources or via WDinstructions.All external interrupt levels normally contain XPSD or PSSinstructions and can be inhibited or permitted by means ofthe setting of bit position 39 (EI) of the program status words.If EI contains a zero, external interrupts are allowed to interrupta program; if EI contains a one, all external interruptsare inhibited from interrupting the program.NUMBER OF INTERRUPT GROUPSThe 14 internal interrupt levels are standard in every systemand all external levels are optional. The addition of theexternal groups (12 levels per group) raises the number ofinterrupt levels to a maximum of 62.CONTROL OF THE INTERRUPT SYSTEMThe system has two points of interrupt control. One pointof interrupt control is achieved by means of the interruptinhibit bits (CI, II, and EI) in the program status words (PSWs).The basic processor is inhibited from interrupting a programif the interrupt inhibit bit for a corresponding class of interruptlevels is set to one, that is, no interrupt level in theinhibited group can advance from the waiting state to theactive state, and the entire group is disabled (removed fromthe interrupt recognition priority chain) • Consequently, awaiting, enabled, interrupt level in an inhibited group doesnot prevent a lower priority, waiting, enabled interruptlevel in an uninhibited group from interrupting the program.However, if an interrupt group is inhibited while a level inthat group is in the active state, no lower priority interruptlevel can advance to the active state.Note also this special case: When the processor detectedfault (PDF) flag is set to 1 (see "Processor Detected Faults Jl ,later in this chapter), the processor fault, memory fault, andcount pulse interrupts are automatica lIy inhibited.The second point of interrupt control is at the individual interruptlevel. The basic processor can interact with anyinterrupt level by means of special modes of the RD and WDinstructions (described in Chapter 3, JlControl Instructions Jl ).For this purpose, the interrupt levels are organized into thefollowing DIO address groups (see last two columns inTable 2):1. The 14 levels of internal interrupts (internal overridegroup, counter-equals-zero group, and I/o group) aredesignated as group code 0 in bits 28-31 of the effectiveaddress of the RD or WD instruction.2. The 12 levels of each group of external interrupts aredesignated as group codes 2, 3, 4, and 5. That is,external group 2 is designated group code 2, externalgroup 3 is designated group code 3, etc.3. There is no group code 1.The addressing of an individual interrupt level within itsDIO group of 12 or 14 is accomplished by an assigned selectionbit within the low-order 16-bit positions of the R registerdesignated in the RD or WD instruction (see lastcolumn in Table 2).The WD instruction can individually arm, disarm, enable,disable, or trigger (move to the active state) any interruptlevel. The RD instruction can determine which interruptlevels within a selected DIO group are in the armed orwaiting state, waiting or active state, or are enabled.TIME OF INTERRUPT OCCURRENCESThe basic processor permits an interrupt to occur during thefollowing time intervals (related to the execution cycle ofan instruction) provided the SCP basic processor (BP) statusindicators are either in the RUN or WAIT condition:1. Between instructions an interrupt is permitted betweenthe completion of any instruction and the initiation ofthe next instruction.2. Between instruction initiations an interrupt is also permittedto occur during the execution of the followingmultiple-operand instructions:MOVE BYTE STRING (MBS)COMPARE BYTE STRING (CBS)TRANSLATE BYTE STRING (TBS)Centralized Interrupts 35

TRANSLA TE AND TEST BYTE STRING (TTBS)EDIT BYTE STRING (EBS)DECIMAL MULTIPLY (OM)DECIMAL DIVIDE (DO)MOVE TO MEMORY CONTROL (MMC)The control and immediate results of these instructions residein registers and memory; thus, the instruction can beinterrupted between the completion of one iteration (operandexecution cycle) and that time (during the next iteration)when a memory location or register is modified. If aninterrupt occurs during this time, the current iteration isaborted and the instruction address portion of the programstatus words (PSWs) remains pointing to the interrupted instruction.After the interrupt-servicing routine is completed,the instruction continues from the point at which itwas interrupted and does not begin anew.SINGLE-INSTRUCTION INTERRUPTSA single-instruction interrupt occurs in this situation: aninterrupt level is activated, the current program is interrupted,the single instruction in the interrupt location isexecuted, the interrupt level is automatically cleared andarmed, and the interrupted program continues without beingdisturbed or delayed (except for the time required to executethe single instruction).If any of the following instructions is executed in any interruptlocation, then the corresponding interrupt is automaticallyasingle-instruction interrupt:MODIFY AND TEST BYTE (MTB)MODIFY AND TEST HALFWORD (MTH)MODIFY AND TEST WORD (MTW)A modify and test instruction modifies the effective byte,halfword, or word (as described in Chapter 3, "Fixed-PointArithmetic Instructions") but the current condition code remainsunchanged (even if overflow occurs). The effectiveaddress of a modify and test instruction in an interrupt location(except counter 4) is always treated as an actual address,regardless of whether the memory map is currentlybeing used. Counter 4 uses the mapped location if mappingis currentiy invoked (as specified in the PSWs). I he executionof a modify and test instruction in an interruptlocation, including mapped and unmapped counter 4, is independentof the virtual memory access-protection codeand the real memory write lock; thus, a memory protectionviolation trap cannot occur as the result of overflow causedby executing MTH or MTW in an interrupt location.The execution of a modify and test instruction in an interruptlocation automatically clears and arms the corresponding interruptlevel, allowing the interrupted program to continue.When a modify and test instruction is executed in a countpulseinterrupt location, all of the above conditions applyas well as the following: If the resultant value in the effectivelocation is zero, the corresponding counter-equalszerointerrupt is triggered.TRAP SYSTEMA trap is similar to an interrupt in that when a trap conditionoccurs, program execution automatically branches to apredesignated location. A trap differs from an interrupt inthat a trap location must contain an XPSD or PSS instruction.The time of trap occurrence can vary: The instructionin the trap location can be executed immediately (i .e.,the current instruction in the program being executed isaborted), or when the current instruction has been partiallyexecuted (i.e., in the case of a long byte-string operation),or upon completion of the current instruction. The trap instructionis not held in abeyance by higher priority traps,whereas interrupts possibly may not be processed before anentire sequence of instructions is executed.TRAP ENTRY SEQUENCEA trap entry sequence begins when the basic processor detectsthe trap condition and ends when the new program statuswords (PSWs) have successfully replaced the old PSWs.Detection of any condition (function) listed in Table 3,which summarizes the trap system, results in a trap to aunique location in memory. When a trap condition occurs,the basic processor sets the trap state. The operation thebasic processor is currently performing mayor may not becarried to compietion, depending on the type of trap andthe operation being performed. In any event, the programinstruction is terminated with a trap sequence (branch to theappropriate trap location). During this sequence the programcounter is not advanced; instead, the X PSD instructionin the trap location is executed. If any interrupt level isready to move to the active state at the same time an X PSDtrap instruction is in process, the interrupt acknowledgmentwill not occur until the XPSD trap instruction is completed.Should a trap location not contain an XPSD or PSS instruction,a second trap sequence is immediately invoked (see"Instruction Exception Trap" later in this chapter).TRAP ADDRESSINGTrap addressing is described under "Interrupt and Trap EntryAddressing",36 Trap System

Table 3. Summary of Trap LocationsLocationsPSWsDec. Hex. Function Mask Bit Time of Occurrence Trap Condi ti on Code64 40 Nonallowed operation65 41 Reservedl. Nonexistent None At instruction decode. Set TCC1 tinstruction2. Nonexistent mem- None Prior to memory access. Set TCC2ory address3. Privi leged instruc- None At instruction decode. Set TCC3tion in slave mode4. Memory protection None Prior to memory access. Set TCC4violation5. Write lock violation None Prior to memory access. Set TCC3, TCC466 42 Push-down stack limit TW, TS At the time of stack limit detection. Nonereached (in stack (The aborted pushdown instructionpointer) does not change memory, registers,or the condition code.)67 43 Fixed-point arithmetic AM For all instructions except DWand NoneoverflowDH, trap occurs after completion ofinstruction. For DW and DH, instructionis aborted with memory, register,CC1, CC3, and CC4 unchanged.68 44 Floating-point arithme- At detection.tic fault1. Characteristic NoneNone{(The floating-point instruction isoverflowaborted without changing any reg-2. Divide by zero None isters. The condition code is set to None3. Significance check FS, FZ, FI\indicate the reason for the trap.)None69 45 Decimal arithmetic fault DM At detection. (The aborted decima I Noneinstruction does not change memory,registers, CC3, or CC4.)70 46 Watchdog timer runout None At runout. (The PDF tt flag will be Set TCC2 if basic proset.)cessor usi ng processorbus;71 47 Programmed trap None Interruptible point reached upon Nonecompletion of WD.set TCC3 if basic processorus i ng memorybus; andset TCC4 if basic processorusing DIO bus.tSee "Trap Condition Code ll ,later in this chapter.tt See II Processor Detected Fau I ts ", la ter in th i s cha pter .T rap System 37

Table 3. Summary of Trap Locations (cont.)LocationsPSWsDec. Hex. Function Mask Bit Time of Occurrence Trap Condition Code72 48 CALLl None At instruction decode. Equal to R field ofCALL instruction.73 49 CALL2 None At instruction decode. Equal to R field ofCALL instruction.74 4A CALL3 None At instruction decode. Equal to R field ofCALL instruction.75 4B CALL4 None At instruction decode. Equal to R field ofCALL instruction.76 4C Hardware error trap None At time of basic processor detec- TCC1, 2, 3 = 0tion (the PDFt flag wi II be set).TCC4 = 0 if parityerror on genera I registeror internal controlregister.TCC4 = 1 if otherhardware errors.77 4D Instruction exception None (The PDF t flag will be set.) Set TCC3 if MMC contrapfiguration illegal;set TCC = X·C· if trapor interrupt sequencewith illegal instruction;set TCC = X·F· if trapor interrupt sequenceand processor detectedfault;set TCC4 if invalidregister designation(odd register on AD,SD, FAL, FSL, FML,FDL, TBS, TTBS, EBS,and register 0 on EBS).78 4E Reserved79 4F Reserved80 50 Power on Interruptible point.81 51 Power off Interruptible point.tSee IIProcessor Detected Faults ll ,later in this chapter.38 Trap System

TRAP MASKSThe programmer may mask the four trap conditions describedbelow in the program status words (PSWs) or the stack pointerdoubleword, as appropriate; other traps cannot be masked.1. The push-down stack I imit trap is masked within thestack pointer doubleword for each individual stack.2. The fixed-point overflow trap is masked in bit position11 (AM) of the PSWs. If this bit position containsa zero, the trap is allowed to occur; if bit 11 containsa zero, the trap is not allowed to occur. AM can bemasked by operator intervention, or by execution ofthe XPSD, PSS, PLS, or LPSD privileged instructions.3. The floating-point significance check trap is maskedby a combination of the floating significance (FS),floating zero (FZ), and floating normalize (FN) modecontrol bits in the PSWs (see IIFloating-Point ArithmeticFault Trapll, later in this chapter). FS, FZ, andFN can be set or cleared by the execution of any ofthe following instructions:LOAD CONDITIONS AND FLOATING CONTROL (LCF)LOAD CONDITIONS AND FLOATING CONTROL IMMEDIATE (LCFI)EXCHANGE PROGRAM STATUS WORDS (XPSD)LOAD PROGRAM STATUS WORDS (LPSD)PUSH STATUS (PSS)PULL STATUS (PLS)4. The decimal arithmetic fault trap is masked by bit position10 (DM) of the PSWs. If DM contains a one,the trap is allowed; if DM contains a zero, the trap isnot allowed. DM can be masked by execution ofthe X PSD, PSS, PLS, or LPSD privi leged instruction.with the condition code bits (CC1-CC4) of the new PSWswhen loading CC1-CC4. See also IIInstruction ExceptionTrapll later in this chapter for more information on the trapcondition code.NONALLOWED OPERATION TRAPThe attempt to perform a nonallowed operation alwayscauses the basic processor to abort the instruction being executedwhen the nonallowed operation is detected and toimmediately execute the XPSD or PSS instruction in trap locationX 1 40 1 • A nonallowed operation cannot be masked.NONEXISTENT INSTRUCTIONAny instruction that is not standard is defined as nonexistent.This includes immediate operand instructions thatspecify indirect addressing (a one in bit 0 of the instruction).If a nonexistent instruction is detected, the basic processortraps to location X 140 1 when the nonexistent instruction isdecoded. No general registers or memory locations arechanged; the PSWs point to the instruction trapped. Withrespect to the condition code and instruction address fieldsof the program status words, the operation of the XPSD orPSS in location X 140 1 is as follows:1. Store the current PSWs. The condition codes stored arethose that existed at the end of the last instructionprior to the nonexistent instruction.2. Store the 16 general registers of the current registerblock if instruction in trap location is a PSS.3. Load the new PSWs.4. Modify the new PSWs.TRAP CONDITION CODEFor the push-down stack limit trap, fixed-point overflowtrap, floating-point fault trap, and decimal fault trap, thenormal condition code register (CC 1-CC4) is loaded withmore detai led information about the trap condition justbefore the trap occurs. These condition codes are saved aspart of the old program status words when the XPSD or PSSinstruction is executed in response to the trap.For the nona I lowed operation trap, watchdog timer runouttrap, hardware error trap, instruction exception trap, andCALL trap, a special register (trap condition codes TCC1-TCC4) is loaded just before the trap occurs. When theX PSD or PSS instruction is executed in response to the trap,this register is added to the new program address if bit 9(MM) contains a one; TCC 1-TCC4 are also logically OReda. Set CCl to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the X PSD or PSS instructioncontains a one, the program counter is incremented by eight. If AI contains a zero, theprogram counter remains unchanged from the valueloaded from memory.NONEXISTENT MEMORY ADDRESSAny attempt to access a nonexistent memory address causesa trap to location X l 40 1 at the time of the request for memoryservice. A nonexistent memory address condition isdetected when an actual address is presented to the memoryT rap System 39

system. If the basic processor is in the map mode, theprogram address wi II already have been modified by thememory map to generate an actual (but nonexistent) address.(See Table 5 for possible changes to registers andmemory locations later in this chapter.) The operation ofthe X PSD or PSS in location X 140 1 is as follows:1. Store the current PSWs.2. Store general registers if PSS.3. Load the new PSWs.without changing protected memory and traps to locationX'40 I • Refer to Table 5 for possible changes to registersand memory locations. (The virtual page address that causedthe violation is in the fourth PSW word.) The operation ofthe XPSD or PSS in trap location X'40 1 is as follows:1 • Store the current PSWs.2. Store general registers if PSS.3. Load the new PSWs.4. Modify the new PSWs.a. Set CC2 to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the XPSD or PSS instructioncontains a one, the program counter is incrementedby four. If AI contains a zero, the programcounter remains unchanged from the value loadedfrom memory.4. Modify the new PSWs.a. Set CC4 to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the XPSD or PSS containsa one, the program counter is incremented by one.If AI contains a zero, the program counter remainsunchanged from the va lue loaded from memory.PRIVILEGED INSTRUCTION IN SLAVE MODEAn attempt to execute a privi leged instruction while thebasic processor is in the slave mode causes a trap to locationX'40 ' before the privi leged operation is performed.No general registers or memory locations are changed, andthe PSWs point to the instruction trapped. The operationof the XPSD or PSS in trap location X'40 ' is as follows:1 • Store the current PSWs.2. Store general registers if PSS.3. Load the new PS'vVs.a. Set CC3 to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the XPSD or PSS containsa one, the program counter is implemented by two.If AI contains a zero, the program counter remainsunchanged from the values loaded from memory.MEMORY PROTECTION VIOLA nONA memory protection violation occurs because of a memorymap access control bit violation (by a program executedin slave mode or master-protected mode using the memorymap). When memory protection violation occurs, thebasic processor aborts execution of the current instructionWRITE LOCK VIOLATIONA memory write lock violation occurs when an instruction(program in master, master-protected, or slave mode) triesto alter the contents of a write-protected memory page. Ifa write lock violation occurs, the basic processor aborts executionof the current instruction without changing protectedmemory and traps to location X 140 1 • (Refer to Table 5 forpossible changes to registers and memory locations.) (Thevirtual page address that caused the violation is the fourthPSW word.) The operation of the XPSD or PSS in trap locationX'40' is as follows:1 . Store the current PSWs.2. Store genera I reg is ters if PSS.3. Load the new PSWs.4. Modify the new PSWs.a. Set CC3 and CC4 to ones. The other conditioncode bits remain unchanged from the values loadedfrom memory.b. If bit position 9 (AI) of the X PSD or PSS containsa one, the program counter is incremented bythree. If AI contains a zero, the program counterremains unchanged from the value loaded frommemory.40 Trap System

PUSH-DOWN STACK LIMIT TRAPPush-down stack overflow or underflow can occur duringexecution of any of the following instructions:OperationInstruction Mnemonic CodePush Word PSW X'09 1Pull Word PLW XIOS IPush Multiple PSM X'OB 'Pull Multiple PLM X'OA 'Modify Stack Pointer MSP X' 13 1During the execution of any stack-manipulating instruction(see Chapter 3, II Push-down Instructi ons "), the stack iseither pushed (words added to stack) or pulled (words removedfrom stack). In either case, the space (5) and words(W) fields of the stack pointer doubleword are tested priorto moving any words. If execution of the instruction wouldcause the space (5) field to become less than 0 or greaterthan 2 15 _1, the instruction is aborted with memory andregisters unchanged. If TS (bit 32) of the stack pointerdoubleword is set to 0, the basic processor traps to locationX'421. If TS is set to 1, the trap is inhibited and the basicprocessor processes the next instruction. If execution ofthe instruction would cause the words (W) field to becomeless than 0 or greater than 215_1, the instruction is abortedwith memory and registers unchanged. If TW (bit 4S) ofthe stack pointer doubleword is set to 0, the basic processortraps to location X'421. If the TW is set to 1, the trap isinhibited and the basic processor processes the next instruction.If trapping is inhibited, CC 1 or CC3 is set to 1 toindicate the reason for aborting the instruction. The stackpointer doubleword, memory, and registers are modifiedonly if the instruction is successfully executed.If a push-down instruction traps, the execution of X PSD orPSS in trap location X'42 1 is as follows:1. Store the current PSWs. The condition codes that arestored are those that existed prior to execution of theaborted push-down instruction.2. Store general registers if PSS.3. Load the new PSWs. The condition code and instructionaddress portions of the PSWs remain at the va lueloaded from memory.FIXED-POINT OVERFLOW TRAPOverflow can occur for any of the following instructions:OperationInstruction Mnemonic CodeLoad Complement Word LCW X'3A 'Load Comp lement Doub I eword LCD X' 1A'Add Ha Ifword AH X'50'Subtract Halfword SH X'5S'Divide Halfword DH X'56 1Add Immediate AI X'20'Add Word AW X'30'Subtract Word SW X l 3S 1Divide Word DW X'36 1Add Doubleword AD XllOlSubtract Doub leword SD X' 1S 1Modify and Test Halfword MTH X'53 1Modify and Test Word MTW X'33 1Add Word to Memory AWM X I 66 1Except for the instructions DIVIDE HALFWORD (DH) andDIVIDE WORD (DW), instruction execution is allowed toproceed to completion. CC2 is set to 1 and CC3 and CC4represent the actual result (0, -, or +) after overflow.If the fixed-point arithmetic trap mask (bit 11 of PSWs) isa 1, the basic processor traps to location X 143 1 instead ofexecuting the next instruction in sequence.For DWand DH, the instruction execution is aborted withoutchanging any register, and CC2 is set to 1; CC 1, CC3,and CC4 remain unchanged from their values at the end ofthe instruction immediately prior to the DW or DH. If thefixed-point arithmetic trap mask is a 1, the basic processortraps to location X I 43 1 instead of executing the next instructionin sequence.The execution of XPSD or PSS in trap location X I 43 1 is asfollows:1. Store the current PSWs. (Store general registers if PSS.)If the instruction trapped was any instruction other thanDW or DH, the stored condition code is interpreted asfollows:CCltCC2 CC3 CC4 Meaning_tt 0 0 Result after overflow is zero.ooResult after overflow isnegative.Result after overflow ispositive.InstructionMnemonicOperationCodetCC1 remains unchanged for instructions LCW, LAW, LCD,and LAD.Load Absolute WordLoad Absolute DoublewordLAWLADX'3B 'X'1B 'tt A hyphen indicates that the condition code bits are not affectedby the condition given under the "Meaning II heading.Trap System 41

2.CC1 toCC2 CC3 CC4 MeaningNo carry out of bit 0 of theadder (add and subtract instructionsonly).Carry out of bit 0 of theadder (add and subtract instructionsonly).If the instructi on trapped was a DW or DH, the storedcondition code is interpreted as follows:CC1ttCC2 CC3 CC4 MeaningOverflowLoad the new PSWs. The condition code and instructionaddress portions of the PSWs remain at the valueloaded from memory.If none of the above conditions occurred but characteristicunderflow occurs with floating zero modebit (FZ) = 1, the stored condition code is interpretedas follows:CClCC2 CC3 CC4 MeaningooCharacteristic underflow,negative result.Characteristic underflow,positive result.If none of the above conditions occurred but an additionor subtraction results in either a zero result (withFS = 1 and FN = 0), or a postnormal ization shift ofmore than two hexadecimal places (with FS = 1 andFN = 0), the stored condition code is interpreted asfollows:CC1CC2 CC3 CC4 MeaningFLOATING-POINT ARITHMETIC FAULT TRAPFloating-point fault detection is performed after the operationcalled for by the instruction code is performed, butbefore any results are loaded into the general registers.Thus, a floating-point operation that causes an arithmeticfault is not carried to completion in that the original contentsof the genera I reg isters are unchanged.Instead, the basic processor traps to location X'44 1 with thecurrent condition code indicating the reason for the trap.A characteristic overflow or an attempt to divide by zeroalways results in a trap condition. A significance check ora characteristic underflow results in a trap condition onlyif the floating-point mode controls (FS, FZ, and FN) in thecurrent program status words are set to the appropriate state.If a floating-point instruction traps, the execution of XPSDor PSS in trap location X'44 1is as follows:1. Store the current PSWs. (Store general registers ifP~~.) If division is attempted with a zero divisor orif characteristic overflow occurs, the stored conditioncode is interpreted as follows:CCloooCC2 CC3 CC4 MeaningooooZero divisor.Characteristic overflow,nega t i ve resu I t.Characteristic overflow,positive result.tCCl remains unchanged for instructions LCW, LAW, LCD,and LAD.ttA hyphen indicates that the condition code bits are not affectedby the condition given under the "Meaning ll heading.0 0 0 Zero result of addition orsubtraction.0 0 More than two postnormalizingshifts, negative result.0 0 More than two postnormalizingshifts, positive result.2. Load the new PSWs. The condition code aild instructionaddress portions of the PSWs remain at the valuesloaded from memory.DECIMAL ARITHMETIC FAULT TRAPWhen either of two decimal fault conditions occurs (seeChapter 3, IIDecimal Instructions ll ), the normal sequencingof instruction is halted, CCl and CC2 are set according tothe reason for the fault condition, and CC3, CC4, memory,and the decimal acclJrnulator remain unchanged by the instruction.If the decimal arithmetic trap mask (bit position10 of PSW1) is a 0, the instruction execution sequencecontinues with the next instruction in sequence at the timeof fault detection; however, if the decimal arithmetic trapmask contains a 1, the basic processortrapstolocationX'45 1at the time of fault detection. The following are the faultconditions for decimal instructions:Instruction Name Mnemonic FaultDec i rna I Load DL I II ega I dig i tDecimal Store DS Illegal digitDecimal Add DA Overflow, i lIega IdigitDecimal Subtract DS Overflow, illegaldigitDecimal Multiply DM Illegal digit42 Trap System

Instruction Name Mnemonic FaultDecimal Divide DD Overflow, i lIega IdigitDecimal Compare DC Illegal digitDecimal Shift DSA Illegal digitArithmeticPack Decimal Digits PACK Illegal digitUnpack Decimal Digits UNPK Illegal digitEdit Byte String EBS Illegal digitThe execution of XPSD or PSS in trap location X'45 1 is asfollows:1 • Store the current PSWs. (Store genera I registers ifPSS.) The stored condition code is interpreted asfollows:CC 1 CC2 CC3 CC4 MeaningooAll digits legal and overflow.Illegal digit detected.2. Load the new PSWs. The condition code and instructionaddress portions of the PSWs remain at the valuesloaded from memory.CALL INSTRUCTION TRAPThe four CALL instructions (CAll, CAL2, CAL3, and CAL4)cause the basic processor to trap to location X'48 1 (forCAll), X'49 1 (for CAL2), X'4A' (for CAL3), or X'4B ' (forCAL4). Execution of the XPSD or PSS instruction in thetrap location is as follows:1. Store the current PSWs. The stored condition code bitsare those that existed prior to the CA LL instruction.2. Store the general registers in PSS.3. Load the new PSWs.4. Modify the new PSWs.a. The R Field of the CALL instruction is logicallyORed with the condition code register as loadedfrom memory.b. If bit 9 (AI) of X PSD or PSS contains a 1, the Rfield of the CALL instruction is added to the programcounter. If AI contains a 0, the programcounter remains unchanged from the value loadedfrom memory.Note: Return from a CALL trap wi" be to the trappinginstruction + 1 •HARDWARE ERROR TRAPWATCHDOG TIMER RUNOUT TRAPThe watchdog timer monitors and controls the maximumamount of basic processor time each instruction can take.The timer is normally in operation at all times and is initializedat the beginning of each instruction. If the instructionis not completed by the time the watchdog timer has completedits count, the instruction is aborted, TCC 1 is set to 0,and a trap occurs immediately to location X'46 I • Additionalinformation as to probable cause of delay is provided:TCC2 is set if the basic processor was using the processorbus, TCC3 is set if the basic processor was using the memorybus, TCC4 is set if the basic processor was using the DIObus. The register altered flag of the PSWs is also set if anyregister or main memory location has been changed whenthe trap occurred.A watchdog timer runout is considered a basic processorfault and the PDF is set. (See "Processor Detected FaultFlag", later in this chapter.)PROGRAMMED TRAPThe programmed trap occurs at instruction interruptiblepoint. It is set by a WRITE DIRECT (WD). See Chapter 3.The basic processor traps to location X 147'.A hardware error trap occurs when either a parity or a sequencecheck fault error is detected by a memory unit, basicprocessor, or any processor communicating with the basicprocessor, resulting in a basic processor trap to locationX'4C. The Trap Condition Code bits (TCCs) are set toX'0001 ' for all hardware fault conditions except generalregister and control register parity errors, where the TCCsare set to X 10000 1 .To determine which of the possible detectable errors is responsiblefor the hardware error trap, the fault status registersof the various processors in the system must be polledwith either the POLP or POLR instruction; the memory'sstatus register must be read with the LMS instruction. Thefault status register bit settings for processors and interfacesare given in Appendix C, Table C-1. The fault status registerbit settings for the memory unit are given in AppendixC, Table C-2.If the basic processor detects or receives a report of a hardwareerror, it attempts automatic retry of the current instruction.If retry is unsuccessful, the basic processor trapsto location X '4C. If retry is successful, the basic processorresumes execution of the next instruction in the program,the Processor Fault Interrupt (PFI) and the "successful instructionretryll bit (bit position 11) in the Basic Processor FaultStatus Register are set to 1. There is automatic instructionTrap System 43

etry only for hardware errors that would otherwise resultin a basic processor trap to location X I 4C. Automatic instructionretry is inhibited if:1 • The current instruction is being executed as a trap orinterrupt instruction;2. The Register Altered bit (bit position 60) of the currentPSWs is set to 1 at the time of detection of thehardware error; or3. The Retry Inhibit bit (bit position 0) in the basic processorcontrol register is set to 1.INSTRUCTION EXCEPTION TRAPThe instruction exception trap occurs whenever the basicprocessor detects a set of operations that are called for inan instruction but cannot be executed because of either ahardware restriction or a previous event.The different conditions that cause the instruction exceptiontrap are:1. A processor-detected fau It that occurs during the executionof an interrupt or trap entry sequence. Aninterrupt or trap entry sequence is defined as the sequenceof events that consists of: (a) initiating aninterrupt or trap; (b) accessing the instruction in theinterrupt or trap location; and (c) executing that instruction,including the exchange of the programstatus words, if required. Note that instructions executedas a result of the interrupt or trap location arenot considered part of the entry sequence.2. An illegal instruction is found in the trap (not XPSD orPSS) or interrupt (not XPSD, PSS, MTB, MTH, MTW) locationwhen executing a trap or interrupt sequence.3. Bit positions 12-14 of the MOVE TO MEMORY CONTROL (MMC) instruction are interpreted as an illegalconfiguration. This is, any configuration other than100, 010, 101, 001, or 011 •4. The set of operations, primarily doubleword and bytestringinstructions, that yield an unpredictable resultwhen an incorrect register is specified; this type offault is called "invalid register designation II and includesthe following instructions ll • tRegister 0 SpecifiedEdit Byte String (EBS)Floating Add Long (FAL)Floating Subtract Long (FSL)Floating Multiply Long (FML)Floating Divide Long (FDL)Translate Byte String (TBS)Translate and Test Byte String (TTBS)Edit Byte String (EBS)Move to Memory Control (MMC)TRAP CONDITION CODEThe Trap Condition Code (TCC) differentiates between thedifferent fault types. Table 4 shows the settings of the TCCfor the various faults that may be detected during a trap orinterrupt entry sequence.Table 4. TCC Setting for Instruction ExceptionTrap X I 4D 1Fault TypeTCCTrap or interrupt sequence and 1 1 1pro~essor-detected fault.Trap or interrupt sequence with 1 1 0invalid instruction.MMC configuration invalid. 0 0 1Invalid register designation. 0 0 0POWER ON TRAPPower On causes the basic processor to reset and then traptolocationX I 50 I • This will occur only following restorationof power after an interruption of less than 500 milliseconds.POWER OFF TRAPPower Off occurs at interruptible point. As source power isgoing off, the basic processor traps to location X 1511 andallows sufficient time for storage of information before thesystem becomes inoperable.1001Odd Register SpecifiedAdd Doub I ewo rd (A D)Subtract Doubleword (SD)tliInvalid register designation II faults do not set the PDFflag.PROCESSOR DETECTED fAULT fL~GThe Processor Detected Fault (PDF) flag aids in solving amultiple error problem. Most traps occur because of a dynamicprogramming consideration (i.e., overflow, attempteddivision by zero, incorrect use of an instruction or address,etc.) and recovery is easi Iy handled by another software44 Trap System

subroutine. However, with certain classes of errors, if asecond error occurs while the basic processor is attemptingto recover from the first error, unpredictable results occur.Inc I uded in th is c lass of traps are the hardware error trap,some cases of the instruction exception trap, and the watchdogtimer runout trap. Upon the first occurrence of thistype of trap, the PDF flag is set.When the PDF flag is set, the processor fault interrupt, thememory fault interrupt, and count pulse interrupts are automaticallyinhibited. The other interrupts mayor may notbe inhibited as specified by the program status words, whichare loaded when the trap entry XPSD or PSS is executed.The PDF flag is normally reset by the last instruction of atrap routine, which is an LPSD or PLS instruction havingbit 10 equal to 0 and bit 11 equal to 1.If a second PDF is detected before the PDF flag is reset, thebasic processor "hangs Up" unti I the PDF flag is reset eitherby the operator entering the command for RESET BASICPROCESSOR or RESET SYSTEM on the operator1s console.This reset wi II cause the following actions:1. The processor fault status register is cleared.2. The PDF flag is cleared and the processor fault interruptgenerated flag is cleared.3. The PSWs are cleared to zero except that the instructionaddress is set to location X 126 1 •4. The basic processor will begin execution with the instructioncontained in location X126 1 .REGISTER ALTERED BITComplete recoverability after a trap may require that nomain memory location, no fast memory register, and nopart (or flags) of the PSWs be changed when the trap occurs.If any of these registers or flags are changed, the RegisterAltered bit (60) of the old PSWs is set to 1 and is saved bythe trap XPSD.Changes to CC1-CC4 cause the Register Altered bit to beset only if the instruction requires these condition code bitsas subsequent inputs.Traps caused by conditions detected during operand fetchand store memory cycles, such as nonexistent memory, accessprotection violation, and memory parity error mayormay not leave registers, memory, and PSWs unchanged, dependingon when they occur during instruction execution.Generally, these traps are recoverable. This is done bychecking for protection violations and nonexistent memoryat the beginning of execution in case of a multiple operandaccess instruction, restoring the original register contentsif execution cannot be completed because of a trap, andnot loading the first word of the PSWs until a possible trapcondition due to access of the second word could have beendetected. Table 5 contains a list of instructions and indicatesfor these instructions what registers, memory locations,and bits of the PSWs, if any, have been changed when atrap due to an operand access memory cycle occurs.Tabie 5. RegiSTers Changed aT Time or a Trap Due TO an Operand AccessInstructi onsAI, CI, LCFI, LI, MICALl-CAL4, SF,S, WAIT, RD, WD, RIO,POLR, POLP, DSALRALB, LCF, LRP, CBLH, LAH, LCH, AH, SH, MH, DH, CHLW, LAW, LCW, AW, SW, MW, OW, CWLD, LAD, LCD, AD, SO, CD, CLM, CLREaR, OR, AND, LS, INT, CSFAS, FSS, FMS, FDS, FAL, FSL, FML, FDLAWM, XW, STS, MTB, MTH, MTWSTB, STCF, 5TH, STW, LASEXU, BCR, BCSBAL, BDR, BIRChangesImmediate type, no operand access.No operand access.Has operand access but traps are suppressed; register bits andcondition codes are set instead.No operand store, registers and PSWs unchanged when trapdue to operand fetch. CCl-4 may be changed but are notused as input to any of these instructions.Registers and memory are preserved, condition codes may bechanged but are not used as input to these instructions.Memory will be altered and the Register Altered bit set.If the branch condition is true (always for EXU and BAL) anda trap occurs due to access of the indirect address or of thenext (branched to or executed) instruction, the register usedis left unchanged and the program address saved in the PSWsis the address of the branch or execute instruction.Trap System 45

Table 5. Registers Changed at Time of a Trap Due to an Operand Access (cont.)InstructionsMBS, CBS, TBS, TTBS, EBS, MMCDA, DS, DL, DST, DC, DM, DD, PACK,UNPK, LM, STM, PLM, PSM, STDCVA, CVSXPSD, LPSD, PSS, PLSSIO, no, TDV, HIO, Ala, RIO*ANLZChangesRegisters and memory may be changed and the Register Alteredbit set.If a trap occurs, the instruction will be aborted before alteringregisters. CCl-4 may be changed but not used as input to anyof these instructions.If a trap occurs due to storing the old PSWs or fetching thenew PSWs, the instruction is aborted before changing the oldPSWs.If trap occurs, the instruction will be aborted without alteringcondition codes, registers, or memory.An indirect ANALYZE instruction executed in the masterprotectedmode wi II trap. No registers are altered.46 Trap System

3. INSTRUCTION REPERTOIREThis chapter describes the instructions, grouped in thefollowing functional classes:1. Load anc;! Store2. Analyze and Interpret3. Fixed-Point Arithmetic4. Comparison5. Logical6. Shift7. Conversion8. Floating-Point Arithmetic9. Decimal10. Byte String11. Push Down12. Execute and Branch13. Call14. Control (privi leged)15. Input/Output (privi leged)Instructions are described in the following format:MNEMONICQ)Affected®Symbolic Notation@INSTRUCTION NAME@(Addressing Type~ Privi leged~Interrupt Actio~)T rap®Condition Code Settings@Trap Action@Example@1. MNEMONIC is the code used by Xerox assemblers toproduce the instruction IS basi c operation code.2. INSTRUCTION NAME is the instructionls descriptivetitle.3. The instruction IS addressing type is one of the following:a. Byte index alignment: the reference address fieldof the instruction {plus the displacement value}can be used to address a byte in mai n memory orin the current block of general registers.b. Halfword index alignment: the reference addressfield of the instruction (plus the displacementvalue) can be used to address a halfword in mainmemory or in the currentblockofgeneral registers.c. Word-index alignment: the reference address fieldof the instruction {plus the displacement value}can be used to address any word in main memoryor in the current block of general registers.d. Doubleword index alignment: the reference addressfield of the instruction (plus the displacementvalue) can be used to address any doubleword inmain memory or in the current block of generalregisters. The addressed doubleword is automaticallylocated within doubleword storageboundari es. {The low order bit of the referenceaddress is ignored. }e. Immediate operand: the instruction word containsan operand value used as part of the instructionexecution. If indirect addressing is attemptedwith this type of instruction (i. e., bit 0 of thei nstructi on word is a 1), the i nstructi on is treatedas a nonexistent instruction, and the basi c processorunconditionally aborts execution of the instruction{at the time of operation code decoding} and trapsto location X 1 40 1 , the "nonallowed operation"trap. Indexing does not apply to this type ofinstruction.f. Immediate displacement: the instruction wordcontains an address displacement used as part ofthe instruction execution. If indirect addressingis attempted with this type of instruction, the basicprocessor treats the instruction as a nonexistent instruction,and it unconditionally aborts executionof the instruction (at the time of operation codedecoding) and traps to location X140'. Indexingdoes not apply to this type of instruction.4. If the instruction is not executable while the basic processoris in the slave mode, it is labeled "privileged"If execution of a privileged instruction is attemptedwhile the basic processor is in the slave mode, it unconditionallyaborts execution of the instruction (at thetime of operation code decoding) and traps to locationX1401.5. If the instruction can be successfully resumed afterits execution sequence has been interrupted by aninterrupt acknowledgment, the instruction is labeledInstruction Repertoi re 47

IIcontinue after interruptll. In the case of the IIcontinueafter interrupt ll instructions, certain general registerscontain intermediate results or control informationthat allows the instruction to continue properly.6. Instruction format:a. Indirect addressing - If bit position 0 of the instructionformat contains an asterisk (*), theinstruction can use either indirect or directaddressing. If bit position 0 of the instructionformat contains a 0, the instruction is of theimmediate operand type, which is treated as anonexistent instruction if indirect addressing isattempted (resulting in a trap to location X'40').b. Operation code - The operation code field (bitpositions 1-7) of the instruction is shown in hexadecimalnotation. For certain I/O instructions,the operation code field is extended and includesbit positions 15-17 of the instruction.c. R field - If the register address field (bit positions8-11) of the instruction format contains thecharacter 11 RII, the instruction can specify anyregister in the current block of general registersas an operand source, result destination, or both;otherwise, the function of this field is determinedby the instruction.d. X field - If the index register address field (bitpositions 12-14) of the instruction format containsthe character IIXII, the instruction specifies indexingwith anyone of registers 1 through 7 inthe current block of general registers; otherwise,the function of this field is determined by theinstruction.e. Reference address field - Normally, the addressfield (bit positions 15-31) of the instruction formatis used as the reference address value forreal, real extended, and virtual addresses (seeChapter 2). This reference address field is alsoused to oddress I/o systems (see I/o instructionslater in this chapter and also Chapter 4). For immediateoperand instructions, this field is augmentedwith the contents of the X field, asillustrated, to form a 20-bit operand.f. Value field - In some fixed-point arithmeticinstructions, bit positions 12-31 of the instructionformat contain the word "value ll . Thefield is treated as a 20-bit integer, with negativeintegers represented in two's complementform.g. Displacement field - In the byte string instructionsbit positions 12-31 of the instruction format containthe byte "displacement". In the executionof the instruction, this field is used to modify thesource address of an operand, the destination addressof a result, or both.h. Reserved fields -In any format diagram that depictssystem inputs (i. e., instruction, data word), ashaded area represents a field that is ignored bythe bas i c processor (i . e. , the content of the shadedfield has no effect on instruction execution). Itshould not be used or must be coded with O's topreclude conflict with possible future modifications.In any format di agram that depi cts system outputs(i. e., general register, memory word modified byan instruction, or I/O status word), a shaded arearepresents a field whose content is indeterminateand must not be used (i. e., masked).7. The description ofthe instruction defines the operationsperformed by the basic processor in response to the instructionconfiguration depi cted by the instruction formatdiagram. Any instruction configuration that causes anunpredictable result is so specified in the description.8. All programmable registers and storage areas that canbe affected by the instruction are listed (symbolically)after the word "Affected". The instruction addressportion of the program status words is considered to beaffected only if a branch condition can occur as a resultof the instruction execution, since the instructionaddress is incremented by 1 as part of every instructionexecution.9. All trap conditions that may be invoked by the executionof the instruction are listed after the word "Trap".Trap locations are summarized in the section "TrapSystem" in Chapter 2.10. The symbolic notation presents the instruction operationas a series of generalized symbolic statements.The symbolic terms used in the notation are defined inthe Appendix, "Glossary of Symbolic Termsll.11. Condition Code settings are given for each instructionthat affects the condition code. A 0 or a 1 under anyof columns 1, 2, 3, or 4 indicates that the instructioncauses a 0 or 1 to be placed in CC1; CC2; CC3 orCC4, respectively, for the reasons given. Ifahyphen (-)appears in columns 1, 2, 3, or 4, that portion of thecondition code is not affected. For example, thefo 1I0wing condition code settings are given for a comparisoninstruction:2 3 4 Result of comparisonoo 0oEqual.Register operand is arithmetically lessthan effecti ve operand.o Register operand is or: thmeti ca!!y greate rthan effective operand.The logical product of the two operandsis nonzero.The logical product (AND) of the two operandsis zero.48 Instruction Repertoire

CC1 is unchanged by the instruction. CC2 indicateswhether or not the two operands have lis in correspondingbit positions, regardless of their arithmeticrelationship. CC3 and CC4 are set according to thearithmeti c re lationshi p of the two operands, regard lessof whether or not the two operands have lis in correspondingbit positions. For example, if the registeroperand is arithmetically less than the effective operand,and the two operands both have lis in at leastone corresponding bit position, the condition codesetting for the comparison instruction is:234oThe above statements about the condition code arevalid only if no trap occurs before the successful completionof the instruction execution cycle. If a trapdoes occur during the instruction execution, the conditioncode is normally reset to the value it containedbefore the instruction was started and the registeraltered bit (bit 60 in PSWs) is set to 1 if a register hasbeen altered. Then the appropriate trap locationis activated.12. Adionstakenbythebasic processor for those trap conditionsthat may be invoked by the execution of the instructionare described. The description includes thecriteria for the trap condition, any control I ing trapmask or inhibit bits, and the action taken by the basicprocessor.Nnte~ Tn avnin IJnnpcpc;c;nrv rpnptitinn thp thrpp t .. "n~ , -.---------, ---- -_.--- -'--rconditions that apply to all instructions (i. e.,nona"owed operations, parity error, and watchdogtimer runout) are not described for eachinstruction.13. Some instruction descriptions provide one or more examplesto i "ustrate the results of the instruction.These examples are intended only to show how the instructionsoperate, and not to demonstrate their fullcapabi lity. Within the examples, hexadecimal notationis used to represent the contents of general registersand storage locations. Condition code settings areshown in binary notation. The character "x" is usedto indicate irrelevant or ignored information.Note: In the following text, BP is used as an abbreviationfor basi c processor.LOAD jSTORE INSTRUCTIONSInstruction NameLoad HalfwordLoad WordLoad DoublewordLoad Complement HalfwordLoad Absolute HalfwordLoad Complement WordLoad Absolute WordLoad Complement DoublewordLoad Absolute DoublewordLoad Read Address (see "ControlInstructions" )Load and SetLoad Memory Status (see "ControlInstructions ")Load SelectiveLoad MultipleLoad Conditions and Floating ControlImmediateLoad Conditions and Floating ControlLoad Virtual Address WordExchange WordStore ByteStore HalfwordStore WordStore DoublewordStore SelectiveStore MultipleStore Conditions and Floating ControlMnemonicLHLWLDLCHLAHLCWLAWLCDLADLRALASLMSLSLMLCFILCFLVAWXWSTBSTHSTWSTDSTSSTMSTCFThe load/store instructions are as follows:Instruction NameLoad ImmediateLoad ByteMnemonicLILBThe load and store instructions operate with informationfields of byte, halfword, word, and doubleword lengths.Load instructions load the information indicated into one ormore of the general registers in the current register block.Load instructions do not affect the source of information;however, nearly all load instructions provide a conditioncode setting that indicates the following information aboutLoad/Store Instructions 49

the contents of the affected genera I register(s) after theinstruction is successfully completed:Condition code settings:2 3 4 Resulto 0Zero - the result in the affected register(s)is all OIS.- 0 Negative - register R contains a 1 in bitposition O.o Positive - register R contains a 0 in bit position0, and at least one 1 appears in theremainder of the affected register(s) (orappeared during execution of the currentinstruction. )- 0 No fixed-point overflow - the result in theaffected register(s) is arithmetically correct.Fixed-point overflow - the result in the affectedregister(s) is arithmetically incorrect.Store instructions affect only that portion of memory storagethat corresponds to the length of the information fieldspecified by the operation code of the instruction; thus,register bytes are stored in memory byte locations, registerhalfwords in memory ha Ifword locations, register words inmemory word locations, and register doublewords in memorydoubleword locations. Store instructions do not affectthe contents of the general register specified by the R fieldof the instruction, unless the same register is also specifiedby the effective virtual address of the instruction.LILOAD IMMEDIATE(Immedi ate operand)execution of the instruction (at the time of operation codedecoding) and traps to location X l 40 1 with the contents ofregister R and the condition code unchanged.LBLOAD BYTE(Byte index alignment)LOAD BYTE loads the effecti ve byte into bi t posi ti ons 24-31of register R and clears bit positions 0-23 of the register toall OIS.Affected: (R), CC3, CC4EB- R 24- 31; 0-R O_ 23Condition code settings:LH2 3 4 Result in Ro 0Zeroo NonzeroLOAD HALFWORD(Halfword index alignment)LOAD HALFWORD extends the sign of the effective halfword16 bit positions to the left and then loads the 32-bitresult into register R.Affected: (R), CC3, CC4EHSE-RLOAD IMMEDIATE extends the sign of the value field (bitposition 12 of the instruction word) 12 bit positions to theleft and then loads the 32-bit result into register R.Affected: (R), CC3, CC4(I)12-31SE- RCondition code settings:2 3 4 Result in Ro 0Zero- 0 Negativeo PositiveTrap: Nonexistent instruction,if bit 0 is a 1.If LI is indirectly addressed, it is treated as a nonexistentinstruction, in which case the BP unconditionally abortsCondition code settings:LWU I 2,., ..... n __ IL •. nL .J "'t "~:'UII III "-"- 0 0 Zero- 0 Negative0 PositiveLOAD WORD(Word index alignment)32 I R I X I : Referenc~ addressLOAD WORD loads the effective word into register R.Affected: (R), CC3, CC4EW-R50 Load/Store Instructi ons

Condition code settings:2 3 4 Result in RExample 3, odd R field value:Before executionAfter execution0 0 Zero0 Negative0 PositiveED X 100000000 1 2345678 1 XI 00000000 1 2345678 1(R) xxxxxxxx XI 00000000 ICC xxxx xx 10LDLOAD DOUBLEWORD(Doubleword index alignment)LCHLOAD COMPLEMENT HALFWORD(Halfword index alignment)LOAD DOUBLEWORD loads the 32 low-order bits of theeffective doubleword into register Ru1 and then loadsthe 32 high-order bits of the effective doubleword intoregister R.If R is an odd value, the result in register R is the 32 highorderbits of the effective doubleword. The condition codesettings are based on the effective doubleword, rather thanthe final result in register R (see example 3, below).Affected: (R), (Ru1), CC3, CC4ED 32_ 63Ru1; ED O_ 31RLOAD COMPLEMENT HALFWORD extends the sign of theeffective halfword 16 bit positions to the left and then loadsthe 32-bit twols complement of the result into register R.(Overflow cannot occur. )Affected: (R), CC3, CC4{EHSEJ-RCondition code settings:2 3 4 Result in R- 0 0 ZeroCondition code settings:234o 0 Zero- 0 Negativeo PositiveLAH- 0 Negativeo PositiveLOAD ABSOLUTE HALFWORD(Halfword index alignment)Example 1, even R field value:Before execution After executionED X'0123456789ABCDEF' X'0123456789ABCDEF'(R) xxxxxxxx X I 0 1234567 1(Ru1) = xxxxxxxx X'89ABCDEF'CC xxxx xxlOExample 2, odd R field value:If the effective halfword is positive, LOAD ABSOLUTEHALFWORD extends the sign of the effective halfword16 bit positions to the left and then loads the 32-bit resultin register R. If the effective halfword is negative, LAHextends the sign of the effective halfword 16 bit positionsto the left and then loads the 32-bit twols complement ofthe result into register R. (Overflow cannot occur.)Affected: (R), CC3, CC4EHSE -RBefore executionAfter executionCondition code settings:ED X'0123456789ABCDEF' X'0123456789ABCDEF'2 3 4 Result in R(R) xxxxxxxx X'01234567 1o 0ZeroCC xxxx xx 10o NonzeroLoad/Store Instructi ons 51

LCWLOAD COMPLEMENT WORD0/Vord index alignment)If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after executionof LOAD ABSOLUTE WORD; otherwise, the BP executesthe next instruction in sequence.LOAD COMPLEMENT WORD loads the 32-bit two's complementof the effective word into register R. Fixed-pointoverflow occurs if the effective word is -231 (X'80000000')in which case the result in register R is -231 and CC2 is setto 1; otherwise, CC2 is reset to O.LCDLOAD COMPLEMENT DOUBLEWORD(Doubleword index alignment)Affected: (R),CC2,CC3,CC4-EW-RCondition code settings:2 3 4 Result in R- 0 0 0 Zero- 0 Negative- 0 0 Positive- 0 No fixed-point overflowoFixed-point overflowTrap: Fixed-pointoverflow.If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after executionof LOAD COMPLEMENT WORD; otherwise, the BP executesthe next instruction in sequence.LOAD COMPLEMENT DOUBLEWORD forms the 64-bittwo's complement of the effective doubleword, loads the32 low-order bits of the resu It into register Ru 1, and thenloads the 32 high-order bits of the result into register R.If R is an odd value, the result in register R is the 32 highorderbits of the two's complemented doubleword. The conditioncode settings are based on the two's complement ofthe effective doubleword, rather than the final result inregister R.Fixed-point overflow occurs if the effective doubleword is_~3 (X'8000000000000000'), in which case the result inregisters Rand Ru1 is _~3 and CC2 is set to 1; otherwise,CC2 is reset to O.Affected: (R),(Rul),CC2,CC3,CC4[-ED]32_63 -Condition code settings:Ru1; [-ED] 0-31- RTrap: Fixed-point overflow2 3 4 Two's complement of effective doublewordLAWLOAD ABSOLUTE WORD0/Vord index alignment)- 0 0 0 Zero- 0 Negative- 0 0 PositiveIf the effective word is positive, LOAD ABSOLUTE WORD!oads the effective v.'ord into regi$ter R. If the effectiveword is negative, LAW loads the 32-bit two's complementof the effective word into register R. Fixed-point overflowoccurs if the effective word is -~ 1 (X'80000000'), inwhich case the result in register R is _2 31 , and CC2 is setto 1; otherwise, CC2 is reset to O.Affected: (R),CC2,CC3,CC4IEWI-RTrap: Fixed-point overflow- 0 No fixed-point overflowoFixed-point overflowIf CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after executionof LOAD COMPLEMENT DOUBLEWORD; otherwise, theBP executes the next instruction in sequence.Example 1, even R field value:Condition code settings:2 3 4 Resu I tin R- 0 0 0 Zero0 Nonzero- 0 No fixed-point overflow0 Fixed-point overflow (sign bit on)ED(R)(Ru 1)CCBefore executi on",,,,,.,,"' A t=,""'nn A n""~""r-'- /\ VIL..J"t..JU/07t-\O\...LJLrxxxxxxxxxxxxxxxxxxxxAfter execution·V"""I')AC:1.70nfl nr"l"'\cr:'/\ I VL..J"t.JVI U 7 ,...,1) ..... L..I1..1X'FEDCBA98'X'765432 1 l'xOOl52 Load/Store Instructions

Example 2, odd R field value:Before executionAfter executionED X'0123456789ABCDEP X'0123456789ABCDEF'(R) xxxxxxxx X'FEDCBA98'CC xxxx x001LADLOAD ABSOLUTE DOUBLEWORD(Doubleword index alignment)of LOAD ABSOLUTE DOUBLEWORDi otherwise, the BPexecutes the next instruction in sequence.Example 1, even R field value:Before executionAfter executionED X'0123456789ABCDEF' X'0123456789ABCDEF'(R) xxxxxxxx X'01234567'(Ru1) = xxxxxxxx X'89ABCDEF'CC xxxx xOlOIf the effective doubleword is positive, LOAD ABSOLUTEDOUBLEWORD loads the 32 low-order bits of the effectivedoubleword into register Ru1, and then loads the 32 highorderbits of the effective doubleword into register R. If R isan odd value, the result in register R is the 32 high-orderbits of the effective doubleword. The condition code settingsare based on the effective doubleword, rather thanthe final result in register R.If the effective doubleword is negative, LAD forms the64-bit two's complement of the effective doubleword, loadsthe 32 low-order bits of the two's complemented doublewordinto register Ru 1, and then loads the 32 high-orderbits of the two's complemented doubleword into register R.If R is an odd value, the result in register R is the 32 highorderbits of the two's complemented doubleword. The conditioncode settings are based on the two's complement of.LL __ CC_ ... - _I II I .1.1 .1,... I I ••11'1:: I::1II::~IIVl:: UUUUII::VVUIU, IUHH:::r IrIun rne nnol resulT Inregister R.Fixed-point overflow occurs if the effective doubleword is-2 63 (X'8000000000000000'), in which case the result inregisters Rand Rul is -263 and CC2 is set to 1; otherwise,CC2 is reset to O.Affected: (R), (Ru 1),CC2,CC3,CC4Trap: Fixed-point overflowExample 2, even R field value:Before executionAfter executionED X' FEDCBA9876543210' X' FEDCBA987654321 0'(R) xxxxxxxx X'01234567'(Rul) = xxxxxxxx X'89ABCDFO'CC xxxx xOlOExample 3, odd R field value:Before executionAfter executionED - X'G.23456789ADCDEF X'G.23456789ADCDEF(R) xxxxxxxx X'01234567'CC xxxx xOlOLASLOAD AND SET(Word index alignment)IED1 32_ 63-Ru1i IEDI 0_ 31-RCondition code settings:2 3 4 Absolute value of effective doubleword- 0 0 0 Zeroo Nonzero- 0 No fixed-point overflowoFixed-point overflow (sign bit on)If CC2 is set to 1 and the fixed-point arithmeti c trap mask(AM) is a 1, the BP traps to location X'43' after executionLOAD AND SET loads the effective word into R. Ifthe effective address is equal to or greater than 16, aone is stored in the sign position of the effective location.If the effective address is equal to or less than 15(effective location is a general register), the sign bitremains unchanged. This instruction is used to interlockmultiple processors from the simultaneous execution ofcertai n secti ons of code or from the si mu I taneous accessto certain tables.Affected: (R), CC3, CC4EW-R1 -EW O ' if EA ~ 16Load/Store Instructions 53

Condition code settings:2 3 4 Result in RExample 2, odd R field value:Before executionAfter execution0 0 Zero0 Negative0 PositiveEW X'89ABCDEF' X'89ABCDEF'(R) XI FOFOFOFO ' X' 80AOCOEO'CC xxxx xxOlNote: Write locks protect memory and traps are not inhibitedduring the execution of LAS.LMLOAD MULTIPLE(Word index alignment)LSLOAD SELECTIVE(Word index alignment)Register Ru 1 contains a 32-bit mask. If R is an even value,LOAD SELECTIVE loads the effective word into register Rin those bit positions selected by a 1 in corresponding bitpositions of register Ru 1. The contents of register R are notaffected in those bit positions selected by a 0 in correspondingbit positions of register Rul.If R is an odd value, LS logically ANDs the contents ofregister R with the effective word and loads the result intoregister R. If corresponding bit positions of register Randthe effective word both contain lis, a 1 remains in registerR; otherwise, a 0 is placed in the corresponding bitposition of register R.Affected: (R), CC3, CC4If R is even, [EWn(Rul)] u [(R)n(Rul)]-RIf R is odd, EWn(R) -Condition code settings:R2 3 4 Result in R- 0 0 Zero.LOAD MULTIPLE loads a sequential set of words into a sequentia I set of registers, the set of words to be loaded beginswith the word pointed to by the effective address of LM,and the set of registers begins with register R. The set ofregisters is treated modulo 16 (i. e., the next register loadedafter register 15 is register 0 in the current register block).The number of words to be loaded into the general registersis determined by the setting of the condition code immediateybefore the execution of LM. (The desired value of thecondition code can be set with LCF or LCFI.) An initia Ivalue of 0000 for the condition code causes 16 consecutivewords to be loaded into the register block.Affected: (R) to (R-tCC-l)(EWL - R; (EWL + 1) - R+ 1), ... , (EWL -tCC-l) - R-tCC-lThe LM instruction may cause a trap if its operation extendsinto a page of memory that is protected by the accessprotection codes. A trap may also occur if the operationextends into a nonexistent memory region.If the effective virtual address of the LM instruction is inthe range 0 through 15, then the words to be loaded aretaken from the general registers rather than from main memnrv_./. Tn _...... thi~ - r:n~p ----- thp ...- ._-_ rp~lIlt~ ..- will ..... -- hp IInnrpriir:tnhlp _...... _-.-._-._ if .. nn\l _...,_.nfthe source registers are also used as destination registers.- 0 Bit 0 of register R is a 1.OBit 0 of register Ris a 0 andbitpositions 1-31of register R contain at least one 1.LCFILOAD CONDITIONS AND FLOATINGCONTROL IMMEDIATE(Immedi ate operand)Example 1, even R field value:r' ~,C vvBefore execution After execution- X'01234567 1 X'01234567 1(Ru 1) XI FFOOFFOO ' XI FFOOFFOO '(R) xxxxxxxx X'Ol xx45xx'CC xxxx xx 10If bit position 10 of the instruction word contains a 1, LOADCONDITIONS AND FLOATING CONTROL IMMEDIATEloads the contents of bit positions 24 through 27 of the instructionword into the condition code; however, if bit 10is 0, the condition code is not affected.If bit position 11 of the instruction word contains a 1,LCFI loads the contents of bit positions 28 through 31 ofthe instruction word into the floating round (FR), floating54 Load/Store Instructions

significance (FS), floating zero (FZ), and floating normalize(FN) mode control bits, respectively (in the program statuswords); however, if bit 11 is 0, the FR, FS, FZ, and FNcontrol bits are not affected. The functions of the floatingpointcontrol bits are described in the section "FloatingPoint Arithmetic Instructions".Affected: CC, FR, FS, FZ, FNIf (1)10 = 1, (1)24-27 -CCIf (1)10 = 0, CC is not affected.If (1)11 = I, (1)28-31 -FR, FR, FS, FZ, FNIf (1)11 = 0, FR, FS, FZ, and FN not affected.Condition code settings, if (1)10 = 1:2 3 4(1)27Trap: Nonexistent instruction,if bit 0is a 1.If LCFI is indirectly addressed, it is treated as a nonexistentinstruction, in whi ch case the computer unconditiona IIyaborts execution of the instruction (at the time of operationcode decoding) and traps to location X'40 ' with the conditioncode unchanged.Condition code settings, if (1)10 = 1:LVAW2 3 4(EB)lLOAD VIRTUAL ADDRESS WORD(Word index alignment)H 34 I R I X I: Reference;address Io 1 2 3 14 5 6 7 6 9 10 11 12 13 14 15 16 17 16 19120 21 22 23 24 25 26 27128 29 30 31LOAD VIRTUAL ADDRESS WORD loads bit positions 15-31of register R with the effective virtual word address of theinstruction whi Ie bit positions 0-14 of register R are clearedto zero.Affected: (R)EVA -R 15- 31 ,O-R O_ 14Note: Condition code is not affected by LVAW.xwEXCHANGE WORD(Word index alignment)LCFLOAD CONDITIONS AND FLOATINGCONTROL(Byte index aiignment)EXCHANGE WORD exchanges the contents of register RAffected: (R), (EWL), CC3, CC4(R)-(EWL)If bit position 10 of the instruction word contains a 1,LOAD CONDITIONS AND FLOATING CONTROL loadsbits 0 through 3 of the effective byte into the conditioncode; however, if bit 10 is 0, the condition code is notaffected.If bit position 11 of the instruction word contains aI, LCFloads bits 4 through 7 of the effective byte into the floatinground (FR), floating significance (FS), floating zero (FZ),and floating normalize (FN) mode control bits, respectively;however, if bit 11 is 0, the FR, FS, FZ, and FN controlbits are not affected. The functions of the floating-pointmode control bits are described in the section "FloatingPoint Arithmetic Instructions".Affected: CC , FR, FS , FZ, FNIf (1)10 = 1, EB O_ 3-CCIf (I) 10 = 0, CC not affectedCondition code settings:2 3 4 Result in R0 0 Zero- - 0 NegativeSTB0 PositiveSTORE BYTE(Byte index alignment)H 75 I R I X I: Referenc~ address Io 1 2 314 5 6 78 9 1011 12 13 14 15 16 17 18 19120 21222324252627128293031STORE BYTE stores the contents of bit positions 24-31 ofregister R into the effective byte location.If (I) 11 = 1, EB 4-7 -FR, FS, FZ, FNAffected: (EBL)If (1)11 = 0, FR, FS, FZ, FN not affected(R)24-31 -EBLLoad/Store Instructions 55

STHSTORE HALFWORD(Halfword index alignment)Example 2, odd R field value:Before executionAfter execution(R)X I 89ABCDEF'X'89ABCDEF'STORE HALFWORD stores the contents of bit positions 16-31of register R into the effective halfword location. If theinformation in register R exceeds halfword data limits, CC2is set to 1; otherwise, CC2 is reset to O.Affected: (EHL), CC2(R)16-31- EHL(E D L) = xxxxxxxxxxxxxxxxSTSSTORE SE LECTNE(Word index alignment)X I 89ABCDEF89ABCDEF'Condition code settings:2 3 4 Information in R- 0 (R)0-16 = all O's or all lis.STW(R)0-16 I all O'S or all l'.s.STORE WORD(Word index alignment)Register Rul contains a 32-bit mask. If R is an even value,STORE SELECTIVE stores the contents of register R into theeffective word location in those bit positions selected bya 1 in corresponding bit positions of register Rul; the effectiveword remains unchanged in those bit positions selectedby a 0 in corresponding bit positions of register Rul.If R is an odd value, STS logically inclusive ORs the contentsof register R with the effective word and stores theresult into the effective word location. The contents ofregister R are not affected.STORE WORD stores the contents of register R into the effectiveword location.Affected: (EWL)Affected: (EWL)If R is even, [(R)n(Rul)] u [EWn(Rul)] -If R is odd, (R) u EW - EWLExample 1, even R field value:EWL(R) -EWLBefore executionAfter executionSTDSTORE DOUBLEWORD(Doubleword index alignment)(R)X'12345678'(Ru 1) = X' FOFOFOFO 'X'12345678'X' FOFOFOFO'EWxxxxxxxxX'lx3x5x7x'STORE DOUBLEWORD stores the contents of register R intothe 32 high-order bit positions of the effective doublewordlocati on and then stores the contents of regi ster Ru 1 intothe 32 low-order bit positions of the effective doublewordlocation.Affected: (E D L)(R)EWBefore executionX'OOFFOOFF'X'12345678'After executionX'OOFFOOFF'C' 12FF56FF I(R) - EDL _ ; (RuH - O 31EDL _ 32 63Example 1, even R field value:Before execution After execution(R) X 1 01234567' X 1 01234567'(Rul) = X'89ABCDEF' X'89ABCDEF '(ED L):::= xxxxxxxxxxxxxxxx X'Q 123456789ABCDEF'STMSTORE MULTIPLE(Word index alignment)/*/ 2B I R I X I I Reference address I10 1 ] 23145 718 9 ]0 11112 13 14'151]6 17 18 19120 21 22 23!24 25 26 27128 29 30 31'STORE MULTIPLE stores the contents of a sequential set ofregisters into a sequential set of word locations. The set oflocations begins with the 10catiol1 pointed to by the effectiveword address of STM, and the set of registers begins with register R. The set of regi sters is treated modu fo 16 (i. e., the56 Load/Store Instructions

next sequential register after register 15 is register 0). Thenumber of registers to be stored is determined by the valueof the condition code immedi ate Iy before execution of STM.(The condition code can be set to the desired value beforeexecution of STM with LCF or LCFI.) An initial valueof 0000 for the condition code causes 16 general registersto be stored.Affected: (EWL) to (EWL +CC-1)(R)-EWL, (R+1)-EWL+1, ... , (R+CC-1)-EWL+CC-1The STM instruction may cause a trap if its operation extendsinto a page of memory that is protected by the accessprotection codes or the write locks. A trap may also occurif the operation extends into a nonexistent memory region.If the effective virtual address of the STM instruction is inthe range 0 through 15, then the registers indicated by theR field of the STM instruction are stored in the general registersrather than main memory. In this case, the resultswill be unpredictable if any of the source registers are alsoused as destination registers.Table 6. ANALYZE Table for Operation CodesX'n' X'OO'+n X'20'+n X'40'+n X'60'+n00 - AI TTBS CBS01 - CI TBS tt MBS02 LCFI ®tt LI -CD -03 - MI - EBS04 CAll SF ANLZ BDR05 CAL2 S CS BIR06 CAL3 LAS XW AWM07 CAL4 - STS EXU08 PLW CYS EOR BCR09 PSW CYA tt OR BCSOA PLM LM@ LS BALOB PSM STM AND INTOC PLS t LRAt SlOt RDtOD psst LMst TIot WDtOE LPSDt@tt WAITt TDyt AIOtOF XPSD t LRPt HIOt MMC tSTCFSTORE CONDITIONS AND FLOATINGCONTROL(Byte index alignment)10 AD SW AH LCF11 CD CW CH CB12 LD LW LH LB13 MSP MTW MTH MTBSTORE CONDITIONS AND FLOATING CONTROL storesthe current condition code and the current value of thefloating round (FR), floating significance (FS), floatingzero (FZ), and floating normalize (FN) mode control bitsof the program status words into the effective byte locationas fo lIows:14 - LYAW - STCF15 STD STW STH STB16 - DWnl-l(A)tt- .. ~ .17 - MW MH UNPK18 SD SW SH DS19 CLM CLR - DA1A LCD LCW LCH DD1B LAD LAW LAH DM- --.. '-.::/PArI( (ffittAffected: (EBL)(PSWs)0_7 -EBL1C FSL FSS - DSA1D FAL FAS - DC1E FDL FDS - DL1F FML FMS - DSTANLZANAL YZEjlNTERPRET INSTRUCTIONSANALYZE(Word index alignment)tPrivileged instructions.tt Decimal value of condition code settings when analyzedinstruction calls for direct addressing. If analyzedinstruction calls for indirect addressing, add 2to the value shown.ANALYZE evaluates the effective word as an instruction.The ANALYZE instruction always sets the condition codesto indicate the addressing type of the analyzed instruction(see condition code settings and Table 6). Except whenthe analyzed instruction is an immediate operand instruction,an effective virtual address for the analyzedinstruction is also calculated and loaded into register R.Analyze/Interpret Instructions 57

The nonexistent instruction, the privi leged instructionviolation, and the unimplemented instruction trap conditionscan never occur during execution of the AN LZ instruction.However, either the nonexistent memory address conditionor the memory protection violation trap condition (or both)can occur as a result of any memory access initiated by theANLZ instruction. If either of these trap conditions occurs,the instruction address stored by an XPSD in trap locationX'40' is always the virtual address of the AN LZ instruction.The detai led operation of ANALYZE is as follows:1. The contents of the location pointed to by the effectivevirtual address of the AN LZ instruction is obtained.This effective word is the instruction to be analyzed.From a memory-protection viewpoint, the instruction(to be analyzed) is treated as an operand of the ANLZinstruction; that is, the analyzed instruction may beobtained from any memory area to which the programhas read access.2. If the operation code portion of the effective wordspecifies an immediate-addressing instruction type, thecondition code is set to indicate the addressing type,and instruction execution proceeds to the next instructionin sequence after AN LZ. The original contentsof register R are not changed when the analyzedinstruction is of the immediate-addressing type.If the operation code portion of the effective wordspecifies a reference-addressing instruction type, thecondition code is set to indicate the addressing typeof the analyzed instruction and the effective addressof the analyzed instruction is computed (using all ofthe normal address computation rules). If bit 0 of theeffective word is a 1, the contents of the memory locationspecified by bits 15-31 of the effective wordare obtained and then used as a direct address. Thenonallowed operation trap (memory protection violationor nonexistent memory address) can occur as aresult of the memory access. Indexing is always performed(with an index register in the current registerblock) if bits 12-14 of the analyzed instruction arenonzero. During rcc! extended cddrcs5ing, the effectivevirtual address of the analyzed "instruction isaligned as an integer displacement value and loadedinto register R, according to the instruction addressingtype, as follows:Byte Addressing: MA=OByte Addressing: MA=l, MM=OHalfword Addressing: MA=OHalfword Addressing: MA=l, MM=OWord Addressing: MA=OWord Addressing: MA=l, MM=ODoubleword Addressing: MA=ODoubleword Addressing: MA=l, MM=OWhen the ANALYZE instruction is executed in the masterprotectedmode and a trap condition occurs, it traps onlyon an indirect ANALYZE. Otherwise, instead of trappingit completes its execution by storing in register R the addressthat would have caused the instruction to trap. Sincethe mode is master-protected, the access protection codeswi II apply to the interpretation of addresses. If a slavemode program is trapped because an instruction has referencedprotected memory, the ANALYZE instruction in themaster-protected mode can determine which address actuallycaused the trap.To aid the interpreting program, when operating in themaster-protected mode, theANLZinstruction uses bits 1, 2,and 3 of register R to indicate which memory access initiatedby the ANLZ would have trapped. The meaning of the possiblecodes in register R(l-3) is as follows:R1 R2 R3 Meaningo 0 0 Successful generation of the effective virtualaddress of the analyzed instruction. The CCsare set to the addressing type of the analyzedinstruction and R(lO-3l) contain the effectivevirtual address of the analyzed instructionaligned as an integer displacement value accordingto the instruction addressing type.o 0The indirect reference of the analyzed instruc-•• , • I , I I _ . -1- .. • ........ _Tlon woula nave rrappea oe\,;uu:>e II WU!) elillelnonexistent, memory protected, or had aparity error. The CCs are set to the addressingtype of the analyzed instruction andR(lO-3l) contain the virtual address of the indirectreference of the analyzed instructionaligned as a word displacement.58 Ana Iyze/lnterpret Instru ctions

R 1 R2 R3 MeaningoThe effective virtual address of the AN LZinstruction would have trapped because it waseither nonexistent, memory protected, or hada parity error. The CCs are indeterminatesince the instruction to be analyzed may nothave been fetched {nonexistent memory}.R(l0-31) contain the effective virtual addressof the AN LZ instruction aligned as a worddisplacement.If no trap condition occurs, ANLZ will execute normallyand return the effective address of the instruction analyzed.Table 6 shows the instruction set as a 4 by 32 matrix {arrangedas a function of the operation code}. This table alsoshows how the instruction set is divided into six groups asa function of the addressing type {delineated by heavylines}. For example, if the operation code of the analyzedinstruction is either X'02 1 , X'20', X'21 1 , X'22 1 , or X'23 1 ,then CCl is set to 1, CC2 is set to 0, CC3 is set to 0 {whenanalyzed instruction specifies direct addressing}, and CC4is set to 1. The decimal equivalent of the condition codesetting for this group of immediate, word addressing type ofinstructions is shown as a 9 within a circle. The decimalequivalents of the condition code settings for the otherfive groups are shown in the same manner. If the analyzedinstruction calls for indirect addressing, CC3 is always setto a 1 and the decimal value of the condition code settingshown in Table 6 should be increased by 2.Affected: {R}, CCeffective word into bit positions 20-31 of register R (andclears the remaining bits of register R). If R is an odd value,INT loads bits 0-3 of the effective word into the conditioncode, loads bits 16-31 of the effective word into bit positions16-31 of register R, and loads OIS into bit positions0-15 of register R (bits 4-15 of the effective word areignored in this case).Affected: {R}, (Rul), CCEW O_ 3-CCEW 4_ 15_R 20_ 31;0- R O- 19EW 16-31- Rul 16_ 31;0 _Rul 0_ 15Condition code settings:2 3 4{EW)lExample 1, even R field value:Before executionAfter executionEW XI 12345678 1 XI 12345678 1(R) xxxxxxxx XI 00000234 1(Ru 1) = xxxxxxxx X I 000056 78 1CC xxx x 0001r ___ -1·.L~_.____ 1 ___ .1..1.- __ _,",VIIUIIIUIi .... vuc :>ClllIll:;I:>;2 3 4 Instruction addressing typeFIXED-POINT ARITHMETIC INSTRUCTIONS0 0 - 0 Byte0 0 Immediate, byte0 - 0 Halfword0 - 0 Word0 Immediate, word- 0 Doubleword- 0 - Direct addressing {EWO = O}- Indi rect addressi ng {EWO = 1}The fixed-point arithmetic instructions are:Instruction NameAdd Immedi ateAdd Ha If wordAdd WordAdd DoublewordSubtract HalfwordMnemonicAIAHAWADSHINTINTERPRET(Word index alignment)Subtract WordSubtract DoublewordSWSDMultiply ImmediateMIINTERPRET loads bits 0-3 of the effective word into thecondi ti on code, loads bits 16-31 of the effecti ve word intobit positions 16-31 of register Ru1 {and loads OIS into bitpositions 0-15 of register Rul, loads bits 4-15 of theMultiply HalfwordMultiply WordDi vi de Ha If wordMHMWDHFixed-Point Arithmetic Instructions 59

Instruction NameDivide WordMnemonicDWAIADD IMMEDIATE(Immediate operand)Add Word to MemoryAWMModify and Test ByteModify and Test HalfwordModify and Test WordMTBMTHMTWThe va I ue fi e Id (bi t posi ti ons 12-31 of the i nstructi on word)is treated as a 20-bit, two's complement integer. ADDIMMEDIATE extends the sign of the value field (bit position12 of the instruction w~rd) 12 bit positions to the left,adds the resulting 32-bit value to the contents of register R,and loads the sum into register R.The fixed-point arithmetic instruction set performs binaryaddition, subtraction, multiplication, and division withinteger operands that may be data, addresses, index values,or counts. One operand may be either in the instructionword itself or may be in one or two of the current generalregisters; the second operand may be either in main memoryor in one or two of the current general registers. For mostof these instructions, both operands may be in the samegeneral register, thus permitting the doubling, squaring,or clearing the contents of a register by using a referenceaddress value equal to the R field value.Affected: (R), CC(R) + (I)12-31SE - RCondition code settings:2 3 4 Result in R- 0 0 Zero- 0 NegativeTrap: Fixed-point overflow,or nonexi stent i nstructionif bit 0 is a 1.All fixed-point arithmetic instructions provide a conditioncode setting that indicates the following information aboutthe result of the operation called for by the instruction:Condition code settings:2 3 4 Resultoo 0oZero - the result in the specified generalregister(s) is all zeros.Negative - the instruction has produced afixed-point negative result.o Positive - the instruction has produced afixed-point positive result.Fixed-point overflow has not occurred duringexecution of an add, subtract, or divide instruction,and the result is correct.o Positive- 0 No fixed-point overflowFixed-point overflowo No carry from bit position 0- Carry from bit position 0If AI is indirectly addressed, it is treated as a nonexistentinstruction, in which case the BP unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contents ofregister R and the condition code unchanged.If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after loadingthe sum into register R; otherwise, the BP executes thenext instruction in sequence.oFixed-point overflow has occurred duringexecution of an add, subtract, or divide instruction.For addition and subtraction, theincorrect result is loaded into the designatedregister(s). For a divide instruction, thedesignated register(s), and CC1, CC3, andCC4 are not affected.No carry - for an add or subtract instruction,there \,ves no carrl of a l-bit cut of the h:ghorder(sign) bit position of the result.- Carry - for an add or subtract instruction,there was a l-bit carry out of the sign bitposition of the result. (Subtracting zero wi IIa Iways produce carry. )AHo 1 2ADD HALFWORD(Halfword index alignment)ADD HALFWORD extends the sign of the effective halfword16 bit positions to the left (to form a 32-bit word in whichbit positions 0-15 contain the sign of the effective ha!fword),adds the 32-bit result to the contents of register R,and loads the sum into register R.Affected: (R), CC(R)+EHSE-RTrap: Fixed-point overflow60 Fixed-Point Arithmetic Instructions

Condition code settings:2 3 4 Result in R- 0 0 ZeroADADD DOUBLEWORD(Doubleword index alignment)- 0 Negative0 Positive- 0 - No fixed-point overflow- - Fixed-point overflowo - No carry from bit position 0- - - Carry from bit position 0If CC2 is set to 1 and the fixed-point arithmetic trap maskis 1, the BP traps to location X'43 1after loading thesum into register R; otherwise, the BP executes the nextinstruction in sequence.ADD DOUBLEWORD adds the effective doubleword to thecontents of registers Rand Ru 1 (treated as a single, 64-bitregister); loads the 32 low-order bits of the sum into registerRul and then loads the 32 high-order bits of the suminto register R. R must be an even value; if R is anodd value, the BP traps with the contents in register Runchanged.Affected: (R), (Rul), CC(R, Ru 1) + ED - R, Ru 1Condi tion code settings:2 3 4 Result in R, Ru1Trap: Fixed-point overflow,instruction exceptionAWADD WORD0Nord index alignment)- 0 0 ZerooNegativeo 1 230o Positive- 0 - No fixed-point overflowADD WORD adds the effective word to the contents of registerR and loads the sum into reqister R.Affected: (R), CC(R) + EW-RCondition code settings:2 3 4 Result in R- - 0 0 Zero- 0 Negativeo Positive- 0 - - No fixed-point overflow- Fixed-point overflowo No carry from bit position 0Carry from bit position 0Trap: Fixed-point overflowIf CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43 1 after loadingthe sum into register R; otherwise, the BP executes thenext instruction in sequence.- Fixed-point overflowo - - - No carry from bit position 0- - - Carry from bit position 0If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43 1after loadingthe sum into registers Rand Ru1; otherwise, the BP executesthe next instruction in sequence.The R field of the AD instruction must be an even value forproper operation of the instruction; if the R field of AD isan odd value, the instruction traps to location X'4D ',instruction exception trap.Example 1, even R field value:Before executionAfter executionED X'33333333EEEEEEEE' X'33333333EEEEEEEE '(R) X' 11111111 1 X' 44444445 1(Ru 1) X 133333333 I X 1222222211CC xxxx 0010Fixed-Point Arithmetic Instructions 61

SHSUBTRACT HALFWORD(Halfword index alignment)2 3 4 Result in Ro Positive- 0 No fixed-point overflowSUBTRACT HALFWORD extends the sign of the effectivehalfword 16 bit positions to the left (to form a 32-bit wordin which bit positions 0-15 contain the sign of the effectivehalfword), forms the two's complement of the resultingword, adds the complemented word to the contents of registerR, and loads the sum into register R.Affected: (R), CC-EH + (R)-RSETrap: Fixed-point overflow- Fixed-point overflowo - No carry from bit position 0- Carry from bit position 0If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X143' after loadingthe sum into register R; otherwise, the BP executes thenext instruction in sequence.Condition code settings:2 3 4 Resu It in R- 0 0 ZerosoSUBTRACT DOUBLEWORD(Doubleword index alignment)- 0 Negativeo Positive- 0 No fixed-point overflow- - Fixed-point overflowo - No carry from bit position 0- - - Carry from bit position 0If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after loadingthe sum into register R; otherwise, the BP executes thenext instruction in sequence.SUBTRACT DOUBLEWORD forms the 64-bit two's complementof the effective doubleword, adds the complementeddoubleword to the contents of registers Rand Rul (treatedas a single, 64-bit register), loads the 32 low-order bits ofthe sum into register Rul and loads the 32 high-order bitsof the sum into register R.Affected: (R), (Rul), CC-E D + (R, Ru 1) - R, Ru 1Condition code settings:2 3 4 Result in R, Rul- - 0 0 ZeroTrap: Fixed-point overflow,instruction exceptionSWSUBTRACT WORD0/'Iord index alignment)- - 0 Negativeo Positive- 0 - - No fixed-point overflowSUBTRACT WORD forms the two's complement of the effectiveword, adds that complement to the contents of registerR, and loads the sum into register R.Affected: (R), CC-EW + (R)-RCcnd:ticr: cede sett:ng~:2 3 4 Resu I tin R- 0 0 Zero- 0 NegativeTrap: Fixed-point overflowFixed-point overflowo - - No carry from bit position 0- Carry from bit position 0If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after the resultis loaded into registers Rand Rul; otherwise, the BPThe R fie Id of the SD instruction must be an even va lue forproper operation of the instruction; if the R fie Id of SD isan odd value, the instruction traps to location X'4D',instruction exception trap; the contents in register R remainunchanged.62 Fixed-Point Arithmetic Instructions

MIMULTIPLY IMMEDIATE(Immediate operand)Example 2, odd R field value:Before executionAfter execution(I) 12-31X'01234 1 X'01234 1The value field (bit positions 12-31 of the instruction word)is treated as a 20-bit, twols complement integer. MULTIPLYIMMEDIATE extends the sign of the value field (bit position12) of the instruction word 12 bit positions to the leftand multiplies the resulting 32-bit value by the contentsof register Ru1, then loads the 32 high-order bits of theproduct into register R, and then loads the 32 low-orderbits of the product into regi ster Ru 1.If R is an odd value, the result in register R is the 32 loworderbits of the product. Thus, in order to generate a64-bit product, the R field of the instruction must be evenand the multiplicand must be in register R+1. The conditioncode settings are based on the 64-bit product formedduring instruction execution, rather than on the final contentsof register R. Overflow cannot occur.Affected: (R), (Rul), CC2,CC3,CC4(Rul) x (I)12-31SE -R,Ru1Condition code settings:2 3 4 64-bi t product- - 0 0 Zero." ~ 1 _ ___ .L-. __- V I"'C~UIIVC.oo PositiveTrap: Nonexistent instructionif bit 0 is a 1.Result is correct, as represented in registerRu1.Result is not correctly representable in registerRu1 alone.(R) X'00030002 1 XI 369C2468 ICC xxxx xOlOMHMULTIPLY HALFWORD(Halfword index alignment)H 57 I R I X I: Reference: address Io 1 2 3 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19120 21 22 23 24 25 26 27128 29 30 31MULTIPLY HALFWORD multiplies the contents of bit positions16-31 of register R by the effective halfword (withboth halfwords treated as signed, twols complement integers)and stores the product in register Ru 1 (overflow cannotoccur). If R is an even value, the original multiplierin register R is preserved, allowing repetitive halfwordmultiplication with a constant multiplier; however, if R isan odd value, the product is loaded into the same register.Overflow cannot occur.Affected: (Rul), CC3, CC4(R)16-31 x EH -Ru1Condition code settings:2 3 4 Result in Ru 1- 0 0 Zero- 0 Negative0 PositiveExample 1, even R field value:If MI is indirectly addressed, it is treated as a nonexistentinstruction, in which case the BP unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contentsof register R, register Ru1, and the condition code unchanged;otherwise, the BP executes the next instructionin sequence.EH(R)(Rul)Before executionX'FFFF'XI xxxxOOOA IxxxxxxxxAfter executionX'FFFF'XI xxxxOOOA IX' FFFFFFF6 1Example 1, even R field value:CCxxxxxx01Before executionAfter executionExample 2, odd R field value:(1)12-31X '70000 I XI 70000 1Before executionAfter execution(R) xxxxxxxx X I 00007000 IEHX'FFFF 'X'FFFF'(Ru1 ) XI 10001000 1 X 170000000 I(R)XI xxxxOOOA IX' FFFFFFF6 1CC xxxx x110CCxxxxxx01Fixed-Point Arithmetic Instructions 63

MWMULTIPLY WORD0Nord index alignment)Condition code settings:2 3 4 Result in R- 0 0 a Zero quotient, no overflow.MULTIPLY WORD multiplies the contents of register Rulby the effective word, loads the 32 high-order bits ofthe product into register R and then loads the 32 loworderbits of the product into register Rul (overflow cannotoccur).If R is odd value, the result in register R is the 32 loworderbi ts of the product. Thus, in order to generate a64-bit product, the R field of the instruction must be evenand the multiplicand must be in register R+l. The conditioncode settings are based on the 64-bit product formedduring instruction execution, rather than on the final contentsof register R.- a a Negative quotient, no overflow.- 0 o Positive quotient, no overflow.- Fixed-point overflow.If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' with the contentsof register R, CC1, CC3, and CC4 unchanged.OWDIVIDE WORD(Word index alignment)Affected: (R), (Ru 1), CC(Ru 1) x EW - R, Ru 1Condi ti on code setti ngs:2 3 4 64-bi t product- - 0 0 Zero.oNegative.o Positive.- 0 Result is correct, as represented in registerRul.OHo 0Result is not correctly representable in registerRul alone.D NIDE HALFWORD(Halfword index alignment)DIVIDE WORD divides the contents of registers Rand Ru 1(treated as a 64-bit fixed-point integer) by the effectiveword, loads the integer remainder into register R and thenloads the integer quotient into register Rul. If a nonzeroremainder occurs, the remainder has the same sign as thedividend (original contents of register R). If R is an oddvalue, DW forms a 64-bit register operand by extendingthe sign of the contents of register R 32 bit positions to theleft, then divides the 64-bit register operand by the effectiveword, and loads the quotient into register R. In thiscase, the remainder is lost and only the contents of registerR are affected.If the absolute value of the quotient cannot be correctlyrepresented in 32 bits, fixed-point overflow occurs; inwhich case CC2 is set to 1 and the contents of register R,register Rul, CC1, CC3, and CC4 remain unchanged;otherwise, CC2 is reset to 0, CC3 and CC4 reflect thequotient in register Rul, and CCl is unchanged.Affected: (R), (Rul), CC2CC3, CC4Trap: Fixed-point overflow(R, Rul) -;- EW- R (remainder), Rul (quotient)DNIDE HALFWORD divides the contents of register R(treated as a 32-bit fixed-point integer) by the effectivehalfword and loads the quotient into register R. If theabsolute value of the quotient cannot be correctly representediii 32 bits, fixed--point oveiflov; OCCUiSi iii ·whichcase CC2 is set to 1 and the contents of register R, andCC1, CC3, and CC4 are unchanged.Condition code settings:2 3 4 Resu I tin Ru 1- 0 0 a Zero quoti ent, no overflow.- a a Negative quotient, no overflow.- a a Positive quotient, no overflow.Fixed-point overflow.Affected: (R), CC2, CC3, CC4 Trap: Fixed-pointoverflowIf CC2 is set to 1 and the fixed-point arithmetic trap mask(R) -;- EH- R (AM) is a 1, the BP traps to location X'43' with the64 Fixed-Point Arithmetic Instructions

original contents of register R, register Rul, CC1, CC3,and CC4 unchangedj otherwise, the BP executes the nextinstruction in sequence.AWMADD WORD TO MEMORy t0/Vord index alignment)ADD WORD TO MEMORY adds the contents of register Rto the effective word and stores the sum in the effectiveword location. The sum is stored regardless of whether ornot overflow occurs.Affected: (EWL), CCEW + (R) -EWLCondition code settings:2 3 4 Result in EWL- 0 0 Zero- 0 Negativeo Positive- 0 No fixed-point overflowoFixed-point overflowNo cnrrv from hit nnc::itinn nI - -- - .- - - .. - -" -Carry from bit position 0Trap: Fixed-pointoverflowIf CC2 is set to 1 and fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43 1 after the resultis stored in the effective word locationj otherwise, theBP executes the next instruction in sequence.the R field. This byte is added to the effective byte andthen (if no memory protection violation occurs) the sum isstored in the effective byte location and the condition codeis set according to the value of the resultant byte. Thisprocess allows modification of a byte by any number in therange -8 through +7, followed by a test.If the value of the R field is zero, the effective byte istested for being a zero or nonzero value. The conditioncode is set according to the result of the test, but theeffective byte is not affected. A memory write-protectionviolation cannot occur in this casej however, a memoryread-protection violation can occur.Affected: CC if (1)8-11/0(EBL) and CC if (1)8-11 -10If (1)8-11 -10, EB + (1)8-11 SE -If (1)8-11 = 0, test byte and set CCCondi ti on code setti ngs:2 3 4 Result in EBL- 0 0 0 Zero- 0 o NonzerooNo carry from byte- Carry from byteEBL and set CC!f ~.ATB :!: ~~(!~:..;tcd ;~ (::i'i ;iitCii;';p~ vi !'iup :0CCitiv{t, thecondition code is not affected and a 20-bit reference addressis used, as described under "Interrupt and Trap EntryAddressing", Chapter 2.Note: All "Modify and Test" instructions in interrupt locationsother than Counter 4 use real, or real extended,addressing mode. Counter 4 uses virtual addressingmode.MTBMODIFY AND TEST BYTE t(Byte index alignment)MTHMODIFY AND TEST HALFWORD t(Halfword index alignment)If the value of the R field is nonzero, the high-order bit ofthe R field (bit position 8 of the instruction word) is extended4 bit positions to the left, to form a byte with bitpositions 0-4 of that byte equal to the high-order bit oftThis instruction requires two memory references to the samelocation for its execution. To preclude other processorsfrom accessing the effective location during this time, thememory unit containing the effective location is reserved(not accessible to other processors) unti I the instruction iscompleted.If the value of the R field is nonzero, the high-order bitof the R field (bit position 8 of the instruction word) is extended12 bit positions to the left, to form a halfword withbit positions 0-11 of that halfword equal to the high-orderbit of the R field. This halfword is added to the effectivehalfword and then (if no memory protection violation occurs)the sum is stored in the effective halfword locationand the condition code is set according to the value of theresultant halfword. The sum is stored regardless of whetheror not overflow occurs. This process allows modification ofa halfword by any number in the range -8 through +7, followedby a test.Fixed-Point Arithmetic Instructions 65

If the value of the R field is zero, the effective halfwordis tested for being a zero, negative, or positive value.The condition code is set, according to the result of thetest, but the effective halfword is not affected. A memorywrite-protection violation cannot occur in this case; however,a memory read-protection violation can occur.Affected: CC if (1)8-11 = 0; Trap: Fixed-pointoverflow(EH L) and CC if (1)8-11 10If (1)8-11 = 0, test halfword and set CCIf (1)8-11/0, EH + (I)8-11SE -EHL and set CCCondition code settings:2 3 4 Result in EH L- 0 0 Zero- 0 Negative0 Positive- 0 No fixed-point overflowoFixed-point overflowNo carry from halfword- Carry from halfwordIf CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43 1 after the resultis stored in the effective halfword location; otherwise,the BP executes the next instruction in sequence.If MTH is executed in an interrupt or trap location, thecondition code is not affected and a 20-bit reference addressis used, as described under "Interrupt and Trap EntryAddressing", Chapter 2.MTWMODIFY AND TEST WORD t(Word index alignment)If the value of the R field is nonzero, the high-order bitof the R field (bit position 8 of the instruction word) isextended 28 bit positions to the left, to form a word withbit positions 0-27 of that word equal to the high-order bitof the R field. This word is added to the effective wordand then (if no memory protection violation occurs) thesum is stored in the effective word location and conditioncode is set according to the value of the resultant word.The sum is stored regardless of whether or not overflowoccurs. This process allows modification of a word byany number in the range -8 through +7, followed bya test.If the value of the R field is zero, the effective word istested for being a zero, negative, or positive value. Thecondition code is set according to the result of the test,but the effective word is not affected. A memory writeprotectionviolation cannot occur in this case; however,a memory read-protection violation can occur.Affected: CC if (1)8-11 = 0;(EWL) and CC if (1)8-11 1 0If (1)8-11 = 0, test word and set CCIf (1)8-11 10, EW + 18-11 SE -Condition code settings:2 3 4 Result in EWL- 0 0 Zero- 0 Negativeo Positive- 0 - - No fixed-point overflow- Fixed-point overflowo - - No carry from word- - - Carry from wordTrap: Fixed-pointoverflowEWL and set CCIf CC2 is set to 1 and the fixed-point arithmetic trap mask(f1to.A\ :c: n 1 +ho RP +rnnc: +1"'1 Il"'Irn+:l"'ln )(1A.11 nf+or +ho rQ-\' .. ,,'/ 'v - II ••• - _ •.• -.-.- ' ___ "_" .... - _ .. _ •... _._suit is stored in the effective word location; otherwise, theBP executes the next instruction in sequence.If MTW is executed in an interrupt or trap location, thecondition code is not affected and a 20-bit reference addressis used, as described under "Interrupt and Trap EntryAddressing ll , Chapter 2.COMPARISON INSTRUCTIONStThis instruction requires two memory references to the samelocation for its execution. To preclude other processorsfrom accessing the effective location during this time, thememory unit containing the effective location is reserved(not accessi bl e to other processors) unti I the i nstructi on iscompleted.The compuri:>on in:)ilu~iiulI:) ure:Instruction NameCompare Immedi ateCompare ByteMnemonicCICB66 Compari son Instructi ons

Instruction NameCompare HalfwordMnemonicCHCBCOMPARE BYTE(Byte index alignment)Compare WordCWCompare DoublewordCompare SelectiveCompare With Limits in RegisterCompare With Limits in MemoryCDCSCLRCLMCOMPARE BYTE compares the contents of bit positions 24-31of register R with the effective byte (with both bytes treatedas positive integer magnitudes) and sets the condition codeaccording to the results of the comparison.Affected: CC2, CC3, CC4All comparison instructions produce a condition codesetting which is indicative of the results of the comparison,without affecting the effective operand in memoryand without affecting the contents of the designatedregister.(R)24-31 : EBCondition code settings:2 3 4 Resu I t of Compari son- 0 0 Equal.CICOMPARE IMMEDIATE(Immediate operand)0 Register byte less than effective byte.0 Register byte greater than effective byte.o 1COMPARE IMMEDIATE extends the sign of the value field(bi t posi tion 12) of the instruction word 12 bi t posi ti ons tothe left, compares the 32-bit result with the contents ofregister R (with both operands treated as signed fixed-pointquantities), and then sets the condition code according torhe resuirs or rhe comparison.- 0 No 1-bits compare, (R)24-31 n EB = O.CHOne or more 1-bits compare,(R)24-31 n EB I O.COMPARE HALFWORD(Halfword index alignment)Affected: CC2, CC3, CC4(R) : (I)12-31SECondition code settings:2 3 4 Result of Comparison- 0 0 Equal.Trap: Nonexistent instructionif bit 0 is a 1.- 0 Register value less than immediate value.o Register value greater than immediate value.- 0 No 1-bits compare, (R) n (1)12-32SE = O.One or more 1-bi ts compare,(R) n (I) 12-32S E I O.If CI is indirectly addressed, it is treated as a nonexistentinstruction, in which case the basic processor unconditionallyaborts execution of the instruction (at the time ofoperation code decoding) and then traps to location X'40'with the condition code unchanged.COMPARE HALFWORD extends the sign of the effectivehalfword 16 bit positions to the left, then compares theresultant 32-bit word with the contents of register R (withboth words treated as signed, fixed-point quantities) andsets the condition code according to the results of thecomparison.Affected: CC2, CC3, CC4(R) : EHSECondition code settings:2 3 4 Result of Comparison- 0 0 Equal.- 0 Register word less than effective halfwordwith sign extended.o Register word greater than effective halfwordwith sign extended.Comparison Instructions 67

2 3 4 Result of Comparison- 0 No I-bits compare, (R) n EHSE = O.One or more I-bits compare,(R) n EHSE -I O.Condition code settings:2 3 4 Result of Comparison- 0 0 Equal.- 0 Register doubleword less than effectivedoub I eword.CWCOMPARE WORD(Word index alignment)o Register doubleword greater than effectivedoubleword.CSCOMPARE SELECTIVECOMPARE WORD compares the contents of register R withthe effective word, with both words treated as signed fixedpointquantities, and sets the condition code according tothe results of the comparison.Affected: CC2, CC3, CC4(R) : EWCondition code settings:2 3 4 Result of Comparison- 0 0 Equal.- 0 Register word less than effective word.o Register word greater than effective word.- 0 No I-bits compare, (R) n EW = O.One or more I-bits compare, (R) n EW -10.COMPARE SE LECTIVE compares the contents of register Rwith the effective word in only those bit positions selectedby a I in corresponding bit positions of register Ru I (mask).The contents of register R and the effective word are ignoredin those bit positions designated by a 0 in corresponding bitpositions of register Rul. The selected contents of register Rand the effective word are treated as positive integer magnitudes,and the condition code is set according to the resultof the comparison. If the R fieldof CS is an odd value;CS compares the contents of register R with the logicalproduct (AND) of the effective word and the contents ofregister R.Affected: CC3, CC4If R is even: (R) n (Rul) : EW n (Rul)If R is odd: (R): EW n (R)Condi ti on code setti ngs:2 3 4 Resu I ts of Compari son under Mask in Ru 1CDCOMPARE DOUBLEWORD- 0 0 Equal.- - 0 Register word less than effective word.o Register word greater than effective word.(if R is even).COMPARE DOUBLEWORD compares the effective doublewordwith the contents of registers Rand Rul (with bothdoublewords treated as signed, fixed-point quantities)and sets the condition code according to the results of thecomparison. If the R field of CD is an odd value, CD formsa 64-bit register operand (by duplicating the contents ofregister R for both the 32 high-order bits and the 32 loworderbits) and compares the effective doubleword with the64-bit register operand. The condition code settings arebased on the 64-bit comparison.Affected: CC3, CC4(R, Run: EDCLRCOMPARE WITH LIMITS IN REGISTERS(Word index alignment)COMPARE WITH LIMITS IN REGISTERS simultaneouslycompares the effective word with the contents of register Rand with the contents of register Rui (with aii three wordstreated as signed fixed-point quantities), and sets the conditioncode according to the results of the comparisons.Affected: CC(R) : EW, (Rul) : EW68 Comparison Instructions

Condition code settings:2 3 4 Result of Comparisonthe other operand is the effective word. The result of thelogical operation is loaded into register R.- a a Contents of R equal to effective word.aContents of R less than effective word.a Contents of R greater than effective word.OROR WORD0Nord index alignment)a a - Contents of Ru 1 equa I to effecti ve word.a - Contents of Ru1 less than effective word.a - Contents of Ru 1 greater than effective word.OR WORD logically ORs the effective word into register R.If corresponding bits of register R and the effective wordare both 0, a a remains in register R; otherwise, a 1 isplaced in the corresponding bit position of register R. Theeffective word is not affected.elMCOMPARE WITH LIMITS IN MEMORY(Doubleword index alignment)Affected: (R), CC3, CC4(R) u EW - R, where a u a = 0, a u 1 = 1, 1 u a = 1,1 u 1 = 1COMPARE WITH LIMITS IN MEMORY simultaneously comparesthe contents of register R with the 32 high-order bitsof the effective doubleword and with the 32 low-order bitsof the effective doubleword, with all three words treatedas 32-bit signed quantities, and sets the condition codeaccording to the results of the comparisons.Affected: CC(R) : ED O_ 31; (R) : ED 32_ 63Condi ti on code setti ngs:2 3 4 Result in R- 0 0 Zero.o Bit 0 of register R is a 1.o Bit 0 of register R is a a and bit positions 1-31of register R contain at least one 1.Condition code settings:2 3 4 Result of ComparisonEOREXCLUSIVE OR WORD0Nord index alignment)- - a a Contents of R equal to most significant word,(R) = ED O_ 31'- 0 Contents of R less than most significant word,(R) < ED O_ 31'a Contents of R greater than most significantword, (R) > ED O_ 31'a a - Contents of R equal to least significant word,(R) = ED _ . 32 63EXCLUSIVE OR WORD logically exclusive ORs the effectiveword into register R. If corresponding bits of registerR and the effective word are different, a 1 is placed inthe corresponding bit position of register R; if the contentsof the corresponding bit positions are alike, a a is placedin the corresponding bit position of register R. The effectiveword is not affected.Affected: (R), CC3, CC4a- Contents of R less than least significant word,(R) < ED 32_ 63.(R) @ EW-Ra- Contents of R greater than least signifi cantword, (R) > ED 32_ 63.LOGICAL INSTRUCTIONSCondition code settings:2 3 4 Resu I tin R- - 0 a Zero.- 0 Bit 0 of register R is a 1.All logical operations are performed bit by correspondingbit between two operands; one operand is in register Rando Bit a of register R is a a and bit positions 1-31of register R contain at least one 1.Logical Instructions 69

ANDAND WORD0Nord index alignment)amount of the shift are determined by bits 25-31 of theindirect word plus bits 25-31 of the specified index register.AND WORD logically ANDs the effective word into registerR. If corresponding bits of register R and the effectiveword are both 1, a 1 remains in register R; otherwise,a 0 is placed in the corresponding bit position of register R.The effective word is not affected.Affected: (R), CC3, CC4(R) n EW-RCondition code settings:2 3 4 Result in R- 0 0 Zero.- 0 Bit 0 of register R is a 1.OBit 0 of register R is a 0 and bit positions 1-31of register R contain at least one 1.SHIFT INSTRUCTIONSThe instruction format for logical, circular, arithmetic,and searching shift operations is:SSHIFT0Nord index alignment)If neither indirect addressing nor indexing is called for inthe instruction SHIFT, bit positions 21-23 of the referenceaddress field determine the type, and bit positions 25-31determine the direction and amount of the shift.If on Iy indirect addressing is called for in the instruction,bits 15-31 of the instruction are used to access the indirectword and then bits 21-23 and 25-31 of the indirect worddetermine the type, direction, and amount of the shift.If only indexing is called for in the instruction, bits 21-23of the instruction word determine the type of shift; thedirection and amount of shift are determined by bits 25-31of the instruction plus bits 25-31 of the specified indexregister.If both indirect addressing and indexing are called for inthe instruction, bits 15-31 of the instruction are used toaccess the indirect word and then bits 21-23 of the indirectword determine the type of shift; the direction andThe effective address does not reference memory. Bitpositions 15-20 and 24 of the effective virtual address areignored. Bit positions 21, 22, and 23 of the effectivevirtual address determine the type of shift, as follows:21 22 23 Shift Type0 0 0 Logical, single register0 0 Logical, double register0 0 Circular, single register0 Circular, double register0 0 Arithmetic, single register0 Arithmetic, double register0 Searching, single registerSearching, double registerBit positions 25 through 31 of the effective virtual addressare a shift count that determines the direction and amountof the shift. The shift count (C) is treated as a 7-bitsigned binary integer, with the high-order bit (bit position25) as the sign (negative integers are represented intwo's complement form). A positive shift count causes aleft shift of C bit positions. A negative shift count causesa right shift of Ici bit positions. The value of C is withinthe range: -64 ~ C ~ +63.All double-register shift operations require an even valuefor the R field of the instruction, and treat registers RandRul as a 64-bit register with the high-order bit (bit position0 of register R) as the sign for the entire register. Ifthe R field of SHIFT is an odd value and a double-registershift operation is specified, a register doubleword is formedby duplicating the contents of register R for both the32 high-order bits and the 32 !ov/-order b!ts of the doub!cword.The shift operation is then performed and the32 high-order bits of the result are loaded into register R.Overflow occurs (on left shifts only) whenever the value ofthe sign bit (bit position 0 of register R) changes. At thecompletion of logical left, circular left, arithmetic left, andsearching left shifts, the condition code is set as follows:2 3 4 Result of Shifto - Even number of l's shifted off left end ofregister R.Odd number of l's shifted off left end ofregister Rt.t Not appli cable for searching shift.70 Shift Instructions

2 3 4 Result of ShiftCircular Shift, Double Register- a No overflow on left shift.- Overflow on left shift.Searching shift terminated with Ra equal to 1.At the completion of right shifts, the condition code is setas follows:a a2 3 4If the shift count, C, is positive, the contents of registers Rand Rul are shifted left C places. Bits shifted past bitposition a of register R are copied into bit position 31of reg i ster Ru 1. (No bi ts are lost.) If Cis negati ve, thecontents of registers Rand Rul are shifted right lei places.Bits shifted past bit position 31 of register Ru1 are copiedinto bit position 0 of register R. (No bits are lost.)Affected: (R), (Rul), CC1, CC2Logical Shift, Single RegisterArithmetic Shift, Single RegisterIf the shift count, C, is positive, the contents of register Rare shifted left C places, the O's copied into vacated bitpositions on the right. (Bits shifted past RO are lost.) If Cis negative, the contents of register R are shifted right Iciplaces, with O's copied into vacated bit positions on theleft. (Bits shifted past R31 are lost.)Affected: (R), CC1, CC2Logical Shift, Double RegisterIf the shift count, C, is positive, the contents of register Rare shifted left C places, with O's copied into vacated bitpositions on the right. (Bits shifted past RO are lost.) If Cis negative, the contents of register R are shifted right leiplaces, with the contents of bit position a copied into vacatedbit positions on the left. (Bits shifted past R31are lost.)Affected: (R), CC1, CC2Arithmetic Shift, Double Registernr£.,Jo 1 2If the shift count, C, is positive, the contents of registersRand Ru1 are shifted left C places, with O's copied intovacated bit positions on the right. Bits shifted past bitposition a of register Ru1 are copied into bit position 31of register R. (Bits shifted past RO are lost.) If C is negative,the contents of registers Rand Ru1 are shifted rightIci places with O's copied into vacated bit positions on theleft. Bits shifted past bit position 31 of register Rarecopied into bit position a of register Ru 1. (Bits shiftedpast Ru 131 are lost.)Affected: (R), (Ru1), CC1, CC2Circular Shift, Single RegisterIf the shift count, C, is positive, the contents of register Rand Rul are shifted left C places, with O's copied into vacatedbit positions on the right. Bits shifted past bit positiona of register Ru1 are copied into bit position 31 ofregister R. (Bits shifted past RO are lost.) If C is negative,the contents of registers Rand Ru1 are shifted right Iciplaces, with the contents of bit position a of register Rcopied into vacated bit positions on the left. Bits shiftedpast bit position 31 of register R are copied into bit positiona of register Ru1. (Bits shifted past Ru131 are lost.)Affected: (R), (Rul), CC1, CC2Searching Shift, Single RegisterIf the shift count, C, is positive, the contents of register Rare shifted left C places. Bits shifted 'past bit position 0are copied into bit position 31. (No bits are lost.) If Cis negative, the contents of register R are shifted rightlei places. Bits shifted past bit position 31 are copiedinto bit position O. (No bits are lost.)Affected: (R), CC1, CC2The searching shift is circular in either direction. If theshift count, C, is positive, the contents of register Rareshifted left C bit positions or unti I a 1 appears in bit positionO. If C is negative, the contents are shifted right Icipositions or unti I a 1 appears in bit position O. When theshift is terminated, the remaining count is stored in register1, which is dedicated to the searching shift instruction.Shift Instructions 71

Bits 0-24 of register 1 are cleared and the remaining countis loaded into bits 25-31. If the initial contents of bit 0is equal to I, then no bits are shifted by the instruction.In this case the original count in the instruction is storedin register 1.Searching shift causing a change in bit position 0 causesCC2 to be set to 1. If bit position 0 is not changed duringa searching shift, CC2 is cleared. CC4 is set to 1 if theshift is terminated with a 1 in bit position O.Affected: (R), (Rl), CC2, CC4Searching Shift, Double RegisterThe searching shift is circular in either direction. If theshift count, C, is positive, the contents of registers RandRul are shifted left C bit positions or until a 1 appears inbit position 0 of register R. If C is negative, the contentsare shifted right lei positions or unti I a 1 appears in bitposition O. When the shift is terminated, the remainingcount is stored in register I, which is dedicated to thesearching shift instruction. Bits 0-24 of register 1 arecleared and the remaining count is loaded into bits 25-31.Searching shift causing a change in bit position 0 causesCC2 to be set to 1. If bit position 0 is not changed duringa searching shift, CC2 is cleared. CC4 is set to 1 if theshift is terminated with a 1 in bit position O.Affected: (R), (Rul), (Rl), CC2, CC4If direct addressing and indexing are called for in theinstruction, bit 23 of the reference address (not affectedby subsequent indexing) determines the type of shift.Bits 25-31 of the reference address plus bits 25-31 of thespecified indexed register determine the direction andamount of the shift.If indirect addressing and indexing are called for in the instruction,bits 15-31 of the reference address are used toaccess the indirect word. Bit 23 of the indirect word (notaffected by subsequent indexing) determines the type ofshift. Bits 25-31 of the indirect address plus bits 25-31 ofthe specified index register determine the direction andamount of the shift.The shift count, C, in bit positions 25-31 of the effectivevirtual address determines the amount and direction ofthe shift. The shift count is treated as a 7-bit signedbinary integer, with the high-order bit (bit position 25) asthe sign (negative integers are represented in two's complementform).The absolute value of the shift count determines the numberof hexadecimal digit positions the floating-point number isto be shifted. If the shift count is positive, the floatingpointnumber is shifted left; if the count is negative, thenumber is shifted right.SHIFT FLOATING loads the floating-point number from theregister(s) specified by the R field of the instruction into aset of internal registers. If the number is negative, itis twols complemented. A record of the original sign isretained. The floating-point number is then separated intoa characteristic and a fraction, and CCI and CC2 are bothreset to OIS.A positive shift count produces the following left shiftoperations:FLOATING-POINT SHIFTFloating-point numbers are defined in the IIFloatingPoint Arithmetic Instructions ll section. The format for the&I~_": _____ :_,, _L:C" : __ L_ •• _": __ : __IIV,",III'~-tJVlIlI ~'IIII II'~IIU"""VII ,~;SFSHIFT FLOATING(Word index alignment)If direct addressing and no indexing is called for in the instructionSHIFT FLOATING, bit position 23 of the referenceaddress field determines the type (long or short format) ofshift, and bit positions 25-31 determine the direction andamount of the shift.If indirect addressing and no indexing is called for in theinstruction, bit positions 15-31 of the instruction are usedto access the indirect word and then bit positions 23 and25-31 of the indirect word determine the type, direction,and amount of the shift.1. If the fraction is normalized (i. e., is less than 1 andis equal to or greater than 1/16), or the fraction isall OIS, CCl is set to 1.,.. 1'1: LL _ r. __ _ L- r-. '.1 -_ II ".... •• rl .-L. 11 HIt:: IrU~lIon rlt::IU I:> UII V:>, rn~ enflr~ flouflng-polnTnumber is set to all OIS (lltrue ll zero), regardless of thesign and the characteristic of the original number.3. If the fraction is not normalized, the fraction field isshifted 1 hexadecimal digit position (4 bit positions) tothe left and the characteristic field is decrementedby 1. Vacated digit positions at the right of the fractionare fi lied with hexadecimal OIS.If the characteristic field underflows (i.e., is all lisas the result of being decremented), CC2 is set to 1.However, if the characteristic field does not underfiow,the shift process (shift fraction, and decrementcharacteristic) continues until the fraction isnormalized, unti I the characteristic field underflows,or unti I the fraction is shifted left C hexadecimaldigit positions, whichever occurs first. (Any two,or all three, of the terminating conditions can occursimultaneously. )72 Shift Instructions

4. At the completion of the left shift operation, thefloating-point result is loaded back into the generalregister(s}. If the number was originally negative, thetwols complement of the resultant number is loadedinto the general register(s}.5. The condition code settings following a floating-pointleft shift are as follows:2 3 4 Result- - 0 0 "True" zero (all OIS).o 02 3 4 Resulto Positive.IC/ digits shifted (no characteristicoverflow).o - Characteristi c overflow.Floating Shift, Single Register- - 0 Negative.o Positive.o 0 - - C digits shifted (fraction unnormalized,no characteristic underflow).- - - Fraction normalized {includes "true"zero}.- Characteristic underflow.The short-format floating-point number in register R isshifted according to the rules established above for floatingpointshift operations.Affected: (R), CCFloating Shift, Double RegisterA negative shift count produces the following right shiftoperations (again assuming that negative numbers are twolscomplemented before and after the shift operation):1. The fraction field is shifted 1 hexadecimal digit positionto the right and the characteristi c field is incrementedby 1. Vacated digit positions at the left arefi lied with hexadecimal OIS.2. If the characteristic field overflows (i. e., is all OIS asthe result of being incremented), CC2 is set to 1.However, if the characteristic field does not overflow,the shift process (shift fraction, and increment characteristic)continues until the characteristic fieldoverflows or unti I the fraction is shifted right lei hexa-"decimal digit positions, whichever occurs first. (Bothterminating conditions can occur simultaneously.)3. If the resultant fraction field is all OIS, the entirefloating-point number is set to all OIS ("true" zero),regardless of the sign and the characteristic of theoriginal number.4. At the completion of the right shift operation, thefloating-point result is loaded back into the generalregister(s}. If the number was originally negative,the twols complement of the resu Itant number is loadedinto the general register(s}.5. The condition code settings following a floating-pointright shift are as follows:2 3 4 Result- 0 0 IITrue ll zero (all zeros).- 0 Negative.The long-format floating-point number in registers RandRul is shifted according to the rules established above forfloating-point shift operations. (If the R field of the instructionword is an odd value, a long-format floatingpointnumber is generated by duplicating the contents ofregister R, and the 32 high-order bits of the result are1 __ ..1_..1 !_ ..____!_..__ D \Iv\.,n."IIi;;U I"IV 1'II;;~I~11I;;1 n .• IAffected: (R), (Ru 1), CCCONVERSION INSTRUCTIONSThe conversion instructions are:Instruction NameConvert by AdditionConvert by SubtractionMnemonicCVACVSThese two conversion instructions can be used to accomplishbidirectional translation between binary code and anyother weighted binary code, such as BCD.The effective addresses of the instructions CONVERT BYADDITION and CONVERT BY SUBTRACTION each pointto the starting location of a conversion table of 32 words,containing weighted values for each bit position of registerRul. The 32 words of the conversion table are consideredto be 32-bit positive quantities, and are referredConversion Instructions 73

to as conversion values. The intermediate results of theseinstructions are accumulated in internal basic processorregisters unti I the instruction is completed; the result isthen loaded into the appropriate general register. Bothinstructions use a counter (n) that is set to 0 at the beginningof the instruction execution and is incremented by 1 witheach iteration, until a total of 32 iterations has beenperformed.If a memory parity or protection violation trap occurs duringthe execution of either instruction, the instruction sequenceis aborted (without having changed the contents ofregister R or Rul) and may be restarted (at the beginning ofthe instruction sequence) after the trap routine is processed.eVACONVERT BY ADDITION(yVord index alignment)CONVERT BY ADDITION initially clears the internal A registerand sets an internal counter (n) to O. If bit position nof register Rul contains a 1, CVA adds the nth conversionvalue (contents of the word location pointed to by the effectiveaddress plus n) to the contents of the A register,accumulates the sum in the A register, and increments nby 1. If bit position n of register Ru 1 contains a 0, CVAonly increments n. If n is less than 32 after being incremented,the next bit position of register Rul is examined,and the addition process continues through n equal to 31;the resu It is then loaded into register R. If, on any iteration,the sum has exceeded the value 2 32 - 1, CCl is setto 1 i otherwise, CCl is reset to O.Affected: (R), CC1, CC3, CC4O-A,O-nIf (Rul) =1, then (EWL + n) + (A) -A, n + 1 -nIf (Run =0. then n + 1-n, 'n 'If n < 32, repeat; otherwise, (A) -next instruction.Condition code settings:2 3 4 Resu It in R- 0 0 Zero.- 0 Bit 0 of register R is a 1.nR and continue toOBit 0 of register R is a 0 and bit positions 1-31of register R contain at least one 1.evsCONVERT BY SUBTRACTION(yVord index alignment)CONVERT BY SUBTRACTION loads the internal A registerwith the contents of register R, clears the internal B register,and sets an internal counter (n) to O. All conversionvalues are considered to be 32-bit positive quantities. Ifthe nth conversion value (the contents of the word locationpointed to by the effective address plus n) is equal to orless than the current contents of the A register, CVS incrementsn by 1, adds the two's complement of the nth conversionvalue to the contents of the A register, stores thesum in the A regi ster, and stores ali n bi t position n of theB register. If the nth conversion value is greater than thecurrent contents of the A register, CVS only increments nby 1. If n is less than 32 after being incremented, thenext conversion value is compared and the process continuesthrough n equal to 31; the remainder in the A registeris loaded into register R, and the converted quantityin the B register is loaded into register Ru1.Affected: (R), (Rul), CC3, CC4(R)-A, O-B, O-nIf (EWL + n) $ (A) then A - (EWL + n) -A,l-B ,n + l-nnIf (EWL + n) > (A) then n + 1-nIf n < 32, repeat; otherwise, (A) - R, (B) - Ru1 andcontinue to the next instruction.Condition code settings:2 3 4 Result in Rul- 0 0 Zero.oBit 0 of register Ru i is a Lo BitOofregisterRu1 is a 0 and bit positions1-31 of register Ru 1 contain at leastone 1.FLOATING-POINT ARITHMETIC INSTRUCTIONSThe floating-point arithmetic instructions are:Instruction f'~amcFloating Add Short~,~ncmon;cFASo- - Sum is correct (less than ~2).Floating Add LongFAL- - Sum is greater than 2 32 _1.Floating Subtract ShortFSS74 Floating-Point Arithmetic Instructions

Instruction NameFloating Subtract LongFloating Multiply ShortFloating Multiply LongMnemonicFSLFMSFMLfor addition and subtraction, an abnormal zero istreated the same as any nonzero operand.3. A positive floating-point number is normalized if andonly if the fraction is contained in the interval1/16 $ F < 1Floating Divide ShortFloating Divide LongFLOATING-POINT NUMBERSFDSFDLTwo number formats are accommodated for floating-pointarithmetic: short and long. A short-format floating-pointnumber consists of a sign (bit 0), a biased t , base 16 exponent,which is called a characteristic (bits 1-7), and asix-digit hexadecimal fraction (bits 8-31). A long-formatfloating-point number consists of a short-format floatingpointnumber followed by an additional eight hexadecimaldigits of fractional significance, and occupies a doublewordmemory location or an even-odd pair of generalregisters.A floating-point number (N) has the following format:4. A negative floating-point number is the two1s complementof its positive representation.5. A negative floating-point number is normalized if andonly if its two1s complement is a normalized positivenumber.By this definition, a floating-point number of the form1 xxx xxxx 1111 0000 . .• 0000is normalized, and a floating-point number of the form1 xxx xxxx 0000 0000 . .. 0000is illegal and, whenever generated by floating-point instructions,is converted to the form1 yyy yyyy 1111 0000 . .. 0000where yy ... Y is 1 less than xx ... x.examples of floating-point numbers.Table 7 containsModes of OperationA floating-point number (N) has the following formaldefinition:1.C-64N = F x 16where F = 0 or-616 s IFI s 1 (short format) or-1416 S IFI $ 1 {long format)There are four mode control bits that are used to qual ify£"1 __ . .L- __ .• .L ____ .I..- _ _ TI _ _ ___ I. __ L.. I I -.1.__ _IIUUIIII~-PUIIII Upt::IUIIUII:>. 1111::::>1::: IIIUUI::: ,",UIIIIUI Uti:> utI:::identified as FR (floating round), FS (floating significance),FZ (floating zero), and FN (floating normalize); they arecontained in bit positions 4, 5, 6, and 7, respectively, ofthe program status words (PSWs4_7).The floating-point mode is established by setting the fourfloating-point mode control bits. This can be performed byany of the following instructions:Instruction NameMnemonicand 0 $ C $ 127.Load Conditions and Floating ControlLCF2. A positive floating-point number with a fraction ofzero and a characteristic of zero is a "true" zero.A positive floating-point number with a fraction ofzero and a nonzero characteristic is an "abnorma I"zero. For floating-point multiplication and division,an abnormal zero is treated as a true zero. However,Load Conditions and Floating ControlImmediateLoad Program Status WordsExchange Program Status WordsLCFILPSDXPSDThe floating-point mode control bits are stored by executingeither of the following instructions:t The bias value of 4016 is added to the exponent for thepurpose of making it possible to compare the absolute magnitudeof two numbers, i. e., without reference to a signbit. This manipulation effectively removes the sign bit,making each characteristic a 7-bit positive number.Instruction NameStore Conditions and Floating ControlExchange Program Status WordsMnemonicSTCFXPSDFloating-Point Arithmetic Instructions 75

Table 7.Floating-Point Number RepresentationDec i rna I Number ± CShort Floating-Point FormatFHexadecimal Value+(16 +63)(1_2- 24 ) 0 111 1111 1111 1111+(16+ 3 )(5/16) 0 100 0011 0101 0000+(16- 3 )(209/256) 0 011 1101 1101 0001+(16 -63)(2047/4096) O· 000 0001 0111 1111+(16 -64)(1/16) 0 000 0000 0001 0000o (called true zero) 0 000 0000 0000 0000- (16-64)( 1/16) 1 111 1111 1111 0000-(16-63)(2047/4096) 1 111 1110 1000 0000- (16-3)(209/256) 1 100 0010 0010 1111-(16 +3)(5/16) 1 011 1100 1011 0000-(16 +63)(1_2 24 ) 1 000 0000 0000 00001111 1111 1111 1111 7F FFFFFF0000 0000 0000 0000 43 5000000000 0000 0000 0000 3D DlO0001111 0000 0000 0000 01 7FFOOO0000 0000 0000 0000 00 1000000000 0000 0000 0000 00 0000000000 0000 0000 0000 FF FOOOOO0001 0000 0000 0000 FE 8010000000 0000 0000 0000 C2 2FOOOO0000 0000 0000 0000 BC BooooO0000 0000 0000 0001 80 000001Special Case-(16 e)(l) 1-e0000 00000000 0000 0000 0000is changed to-(16 e + 1 )(1/16) 1 en 1111 00000000 0000 0000 0000whenever generated as the result of a floating-point instruction.FLOAnNG-POINT ADD AND SUBTRACTThe floating round (FR), floating normalize (FN), floatingzero (FZ), and floating significance (FS) mode controlbits determine the operation of floating-point additionand subtraction {if characteristi c overflow does not occur}as follows:FRFloating round:Note: The floating round faci lity is avai lable only inthe hardware floating-point. In the absenceof this feature, the floating-point subroutinesoffer only truncation; hence, to guaranteehardware and software i denti ca I resu Its, FR(bit 4 of PSWs) must be zero.FR = 0FR = 1No rounding specified (truncation).The results of additions and subtractions areto be rounded. Each value associated withthe operation (i. e., augend, addend, andintermediate result of an add) is extended bythe hardware to include one guard digit.(Short-format values are extended into bitpositions 32-35 and long-format values areextended into bit positions 64-67.) Contentsof guard digits may be affected during prealignment,computation, or postnormalization.Rounding is perfoiiiied by evaluating the gUGiddigit of the intermediate result after any requiredpostnormalization. If the value of theguard digit is 0-7, the other digits are notmodified. If the value of the guard digitis 8-F, the value contained within the otherdigits is incremented by one.76 Floating-Point Arithmetic Instructions

The following table shows the possible cases:Pre-alignment(exponents I)ooooPostnorma I i zati onScaleAnswerleftooooScaleAnswerRightGuard Digit Actiono (Guard digit = 0.)oooRound on guard digit.

If characteristic overflow occurs, the basic processor alwaystraps to location X'44 1 with the general registers unchangedand the condition code set to 0110 if the result is positive,or to 0101 if the result is negative.FLOATING-POINT MULTIPLY AND DIVIDEThe floating round (FR) and floating zero (FZ) mode controlbits determine the operation of floating-point multiplicationand division (if characteristic overflow does notoccur and division by zero is not attempted) as follows:FRFloating round:FR = 0No roundi ng speci fi ed.CONDITION CODES FORFLOATING-POINT INSTRUCTIONSThe condition code settings for floating-point instructionsare summarized in Table 8. The following provisions applyto all floating-point instructions:1. Undeflow and overflow detection apply to the finalcharacteristic, not to any "intermediate" value.2. If a floating-point operation results in a trap, the originacontents of all general registers remain unchanged.3. All shifting, truncation, and rounding are performedon absolute magnitudes. If the fraction is negative,then the two's complement is formed after shifting ortruncation.FZFR = 1Note:The results of floating multiplication anddivision instructions are to be rounded. Formultiply or divide operations, a normalizedproduct or quotient is produced, appendedby a guard digit. This wi II be an absolutevalue.The example above (under "Floating-PointAdd and Subtract") is not possible for multiplyand divide. Therefore, there is never a timepenalty for rounding.Floating zero:FZ = 0If the final result of a multiplication or divisionoperation cannot be expressed in normalizedform because of the characteristic beingreduced below zero, underflow has occurred.If underflow occurs, the result is set equal to"true" zero and the condition code is set to1100. If underflow does not occur, thecondition code is set to 0010 if the result ispbsitive, to 0001 if the resulT is negutive, orto 0000 if the result is zero.FASFLOATING ADD SHORT0Nord index alignment)The effective word and the contents of register R are loadedinto a set of internal registers and a low-order hexadecimalzero (guard digit) is appended to both fractions, extendingthem to seven hexadecimal digits each. FAS then forms thefloating-point sum of the two numbers. (See "FR Floatinground" under "Floating-Point Add and Subtract", if roundingapplies.) If no floating-point arithmetic fault occurs,the sum is loaded into register R as a short-format floatingpointnumber.Affected: (R), CC(R) + EW-RFALFLOATING ADD LONG(Doubleword index alignment)Trap: Floating-point arithmeticfaultFZ = 1Underflow causes the basic processor to trapto location X'44 1 with the contents of thegeneral registers unchanged. The conditioncode is set to 1110 if the result is positive,or to 1101 if the result is negative. If underflowdoes not occur, the resultant action isthe same as that for FZ = O.If the divisor is zero in a floating-point division; the basicprocessor always traps to location X'44 1 with the generalregisters unchanged and the condition code set to 0100. Ifcharacteristic overflow occurs, the basic processor alwaystraps to location X'44' with the general registers unchangedand the condition code set to 0110 if the result is positive,or to 0101 if the result is negative.The effective doubleword and contents of registers Rand Ru1are loaded into a set of internal registers.The operation of FAL is identical to that of FLOATINGADD SHORT (FAS) except that the fractions to be addedare each 14 hexadecimal digits long, guard digits are appendedto the fractions only if rounding is specified, and Rmust he an even value for correct results. If no flootingpointarithmetic fault occurs, the sum is loaded into registersRand Ru 1 as a long-format floating-point number.Affected: (R), (Rul), CC(R, Rul) + ED -R, RulTrap: Floating-point arithmetic fault, instructionexception78 Floating-Point Arithmeti c Instructions

Table 8.Condition Code Settings for Floating-Point InstructionsCondition Code1 2 3 4 Meaning If No Trap to Location X'44 1 Meaning If Trap to Location X'44 1 Occurs0 0 0 0 A x 0, 0/ A, or -A + A 0 *0 1 0 0 *@Divide by zero )0 1 0 1 * Overflow, N < 0 Always trapped0 1 1 0 * Ov~rflow, N >0 2 Postnorma 1- d = I, FN=O, d} "" h"ft no underflow• • • an no un er-0 1 0N > 0 I ZI ng SISN > 0 Izmg shifts flow with FZ= 11 1 0 0 Underflow wi th FZ = 0 and no trap by FS = 1 0Notes:

FMSFLOATING MULTIPLY SHORT(yVord index alignment)H 3F I R I X I: Referenc~ address Io 1 2 314 5 6 7 8 9 10 11 12 13 14 15 16 17 1819120 21 222324252627128293031FOLFLOATING DNIDE LONG(Doubleword index alignment)The effective word (multiplier) and the contents of register R(multiplicand) are loaded into a set of internal registers,and both numbers are then prenormalized (if necessary). Anormalized 6-digit product is produced, appended by aguard digit. If FR equals 1, and the guard digit contains 8or greater, the fraction is incremented. If no floatingpointarithmetic fault occurs, the product is loaded intoregister R as a short-format floating-point number.The effective doubleword (divisor) and the contents ofregisters Rand Rul (dividend) are loaded into a set ofinternal registers. FLOATING DIVIDE LONG then operatesidentically to FLOATING DIVIDE SHORT (FDS), exceptthat the operands are each 14 hexadecimal digits long.R must be an even value for correct results. If no floatingpointarithmetic fault occurs, the quotient is loaded intoregisters Rand Ru1 as a long-format floating-point number.Affected: (R), CC(R) x EW-RTrap: Floating-point arithmeticfaultAffected: (R), (Rul), CC(R, Ru1}.;. ED-R, Ru1Trap: Floating-point arithmeticfault, instruc~tion exceptionFMLFLOATING MULTIPLY LONG(Doubleword index alignment)The R field of the FDL instruction must be an even valuefor proper operation of the instruction; if the R field of FDLis an odd value, the instruction traps to location X'4D'instruction exception trap.The effective doubleword (multiplier) and the contents ofregisters Rand Ru1 (multiplicand) are loaded into a set ofinternal registers. (FLOATING MULTIPLY LONG thenoperates identically to FLOATING MULTIPLY SHORT(FMS), except that the operands are each 14 hexadecimaldigits long. R must be an even value for correct results.If no floating-point arithmetic fault occurs, the product isloaded into registers Rand Ru1 as a long-format floatingpointnumber.Affected: (R), (Ru1), CC(R, Ru1) x ED -R, RulTrap: Floating-point arithmeticfault, instructionexceptionThe R field of the FML instruction must be an even valuefor proper operation of the instruction; if the R field ofFML is an odd value, the instruction traps to location X'4D',instruction exception trap.DECIMAL INSTRUCTIONSThe following instructions comprise the decimal instructionset:Instruction NameDecimal LoadDecimal StoreDecimal AddDecimal SubtractMnemonicDLDSTDADSFOSFLOATING DIVIDE SHORT(Word index alignment)Decimal MultiplyDMDecimal DivideDDThe effective word (divisor) and the contents of register R(dividend) are loaded into a set of internal registers andboth numbers are then prenormalized (if necessary). Anormalized 6-digit quotient is produced, appended by aguard digit. If FR equals 1, and the guard digit contains 8or greater, the fraction is incremented. If no floatingpointarithmetic fault occurs, the quotient is loaded intoregister R as a short-format floating-point number.Decimal CompareDecimal Shift ArithmeticPack Decimal DigitsUnpack Decimal DigitsDCDSAUNPKAffected: (R), CC(R).;. EW-RTrap: Floating-point arithmeticfaultEdit Byte String (described under"Byte-String Instructions")EBS80 Decimal Instructions

PACKED DECIMAL NUMBERSAll decimal arithmetic instructions operate on packeddecimal numbers, each consisting of from 1 to 31 decimaldigits t (in absolute form) plus a decimal sign. A decimaldigit is a 4-bit code in the range 0000 through 1001,where 0000 = 0, 0001 = 1, 0010 = 2, 0011 = 3, 0100 = 4,0101 = 5, 0110 = 6, 0111 = 7, 1000 = 8, and 1001 = 9.A positive decimal sign is a 4-bit code of the form:101O(X'A'), 1100(X'C'), 111O(X'E'), or 1111 (X'F'). A negativedecimal sign is a 4-bit code of the form: 1011 (X'B'),or 1101 (X'D'). However, the decimal sign codes generatedfor the result of a decimal instruction are: 1100 (X'C') forpositive results, and 1101 (X'D') for negative results. Theformat of packed decimal numbers is:For the decimal arithmetic instructions, a packed decimalnumber must occupy an integral number (l through 16) ofconsecutive bytes. Thus, a decimal number must contain anodd number of decimal digits, the high-order digit (zero ornonzero) of the number must be in bit positions 0-3 of thefirst byte, the decimal sign must be in bit positions 4-7 ofthe last byte, and all decimal digits and the decimal signmust be 4-bit codes of the form described above.ZONED DECIMAL NUMBERSIn zoned decimal format, a single decimal digit is contained_••!.LL!_ L'!L ____'!L'! ____ ..f "7 _£ __ L __ L __. _I I -.I. _ ••.• _ 1'\ "") ,.VVI'"I" UII t-'V:>IIIVII:> ~-I v, U ur"';, UIIU UII PV:>IIIVII:> v-v v,the byte are referred to as the "zone" of the decimal digit.A zoned deci ma I number consi sts of from 1 to 31 bytes, withthe decimal sign appearing as the zone for the last byte, asfollows:decimal accumulator, and registers 12 through 15 are treatedas a single 16-byte register. The entire decimal accumulatoris used in every decimal arithmetic instruction.DECIMAL INSTRUCTION FORMATThe general format of a decimal instruction is as follows:The indirect address bit (position 0), the operation code(positions 1-7), the index field (12-14), and the referenceaddress field (15-31) all have the same functions for thedecimal instructions as they do for any other byte-addressinginstruction. However, bit positions 8-11 of the instructionword do not refer to a general register; instead, the contentsof this field (designated by the character II L") designate thelength, in bytes, of a packed decimal number. (If L = 0, alength of 16 bytes is assumed. )ILLEGAL DIGIT AND SIGN DETECTIONPrior to executing any decimal instruction, the basic processorchecks a II deci ma I operands for the presence ofillegal decimal digits or illegal decimal signs. For all decimalarithmetic instructions, an illegal decimal digit is asign code (i. e., in the range X'A' through X'F') that appearsanywhere except in bit positions 4-7 of the leastsignificant byte (the sign position) of the packed decimalnumber; an illegal decimal sign is a digit code (i. e., in therange XIO I through X'9') that appears in the sign position ofthe packed decimal number.The sign format is EBCDIC and the zones are 1111.A decimal number can be converted from zoned to packedformat by means of the instruction PACK DECIMAL DIGITS.A decimal number can be converted from packed to zonedformat by means of the instruction UNPACK DECIMALDIGITS.For the instructions DECIMAL MULTIPLY and DECIMALDIVIDE, the illegal sign and digit check also includes acheck for an illegal L field in the instruction. IllegalL fields are X'O' and the range X'9' to XI F'.For the DECIMAL MULTIPLY instruct~on, only registers R14and R15 are checked for illegal digits. The original contentsof R12 and R13 are ignored and are presumed to bezeros.DECIMAL ACCUMULATORAll decimal arithmetic instructions imply the use of registers12 through 15 of the current register block as thet Except EDIT BYTE STRING (EBS), which has no limit onthe size of numbers.If an illegal digit or sign is detected, the basic processorunconditionally aborts the execution of the instruction (atthe time that the illegal digit or sign is detected), setsCC 1 to 1 and resets CC2 to O. If the deci ma I ari thmeti cfault trap mask (bit position 10 of the program status words)is a 0, the basic processor then executes the next instructionin sequence; however, if the decimal arithmetic faulttrap mask is a 1, the basic processor traps to location X'45'.In either case, the contents of the decimal accumulator,the effective decimal operand, CC3, and CC4 remainunchanged.Decimal Instructions 81

OVERFLOW DETECTIONArithmetic overflow can occur during execution of thefollowing decimal instructions:DECIMAL ADD. Overflow occurs when the sum of thetwo decimal numbers exceeds the 31-digit capacity of thedecimal accumulator (+103 1 -1 to -1031 + 1).DECIMAL SUBTRACT. Overflow occurs when the differencebetween the two decimal numbers exceeds the 31-digitcapacity of the decimal accumulator.DECIMAL DIVIDE. Overflow occurs either when the divisoris zero, or when the dividend is greater than 14 digits inlength and the absolute value of the significant digitsto the left of the 15th digit position (counting from theright) is greater than or equal to the absolute value ofthe divisor.CONDITION CODE SETTINGSAll decimal instructions provide condition code settings,using CCl to indicate whether or not an illegal digit orsign has been detected, and CC2 to indicate whether ornot overflow has occurred. Most (but not all) of the decimalinstructions provide condition code settings, using CC3and CC4 to indicate whether the decimal number in thedecimal accumulator is zero, negative, or positive, asfollows:CC3 CC4 Result in DECAoo°Zero - the decimal accumulator contains apositive or negative decimal sign code in thefour low-order bit positions; the remainder ofthe decimal accumulator contains all OIS.Negative - the decimal accumulator containsa negative decimal sign code in thefour low-order bit positions; the remainderof the decimal accumulator contains at leastone nonzero decimal digit.If arithmetic overflow occu;"s during execution of DECIMALADD, DECIMAL SUBTRACT, or DECIMAL DIVIDE, thebasic processor unconditionally aborts execution of theinstruction (at the time of overflow detection), resets CClto 0, and sets CC2 to 1. Then, if the decimal arithmeticfault trap mask (PSWslO) is a 1, the basic processor trapsto location Xl45 1 ; if the decimal arithmetic fault trap maskis a 0, the basic processor executes the next instruction insequence. In either case, the contents of the decimalaccumulator, memory storage, CC3, and CC4 remainunchanged.DLo Positive - the decimal accumulator containsa positive decimal sign code in the four loworderbit positions; the remainder of the decimalaccumulator contains at least one nonzerodecimal digit.DECIMAL LOAD(Byte index alignment)DECIMAL INSTRUCTION NOMENCLATUREFor the purpose of abbreviating the instruction descriptionsto follow, the symbolic term "DECA" is used to representthe decimal accumulator, and the symbolic term "EDO" isused to represent the effective decimal operand of the instruction.For the instructions DECIMAL LOAD, DECIMALADD, DECIMAL SUBTRACT, DECIMALMULTIPLY, DECIMALDIVIDE, and DECIMAL COMPARE, the effective decimaloperand is a packed decimal number that is II L" bytesin length, where L is the numeric value of bit positions8-11 of the instruction word, and a value of 0 for Ldesignates 16 bytes. The effective byte addresses ofthese instructions point to the byte location that containsthe most significant byte (high-order digits) of the decimalnumber, and the effective byte address plus L-l (whereL = ° = 16) points to the least significant byte (low-orderdigit and sign) of the decimal number. Thus, for these instructions,the effective decimal operand (EDO) is the contentsof the byte string that begins with the effective bytelocation, is L bytes in length, and ends with the effectivebyte location plus L-l.If no illegal digit or sign is detected in the effectivedecimal operand, DECIMAL LOAD expands the effectivedecimal operand to 16 bytes (31 digits + sign) by appendinghigh-order OIS, and then loads the expanded decimal numberinto the decimal accumulator. If the result in thedecimal accumulator is zero! the converted sign remainsunchanged.Affected: (DECA), CC(EBL to EBL + L - 1) -Condition code settings:DECA2 3 4 Result in DECA°Trap: Decimal arithmetic- Illegal digit or sign detected, i nstructi onaborted0 0 0 0 ZeroINo illegal digit or illegal sign0 0 0 Negativedetected, instruction completed0 0 0 Positive82 Decimal Instructions

DSTDECIMAL STORE(Byte index alignment)Condition code settings:2 34 Result in DECAIf no illegal digit or sign is detected in the decimalaccumulator, DECIMAL STORE stores the low-order L bytesof the decimal accumulator into memory from the effectivebyte location to the effective byte location plus L-l.If the decimal accumulator contains more significant informationthan is actually stored (i. e., at least one nonzerodigit was not stored), CC2 is set to 1; otherwise, CC2is reset to O. If the result in memory is zero, the convertedsi gn remains unchanged.Affected: (EBL to EBL + L-l),CC1, CC2Trap: Decimal arithmetic(DECA) low-order bytes - EBL to EBL + L -1000 0 00 0 00 0DS- Illegal digit orIsi gn detectedOverflow0 ZeroNegative0 PositiveDECIMAL SUBTRACT(Byte index alignment)Instruction abortedNo illegal digit or signdetected, no overflow,instruction completedCondition code settings:2 3 4 Result of DSTo - - Illegal digit or sign detected, instructionaborted0 0 - All significant informationstored0 Some significantinformaTion norstoredDADECIMAL ADD(Byte index alignment)1JNo illegal digit orillegal sign detected,instruction completedIf no illegal digit or sign is detected in the effective decimaloperand or in the decimal accumulator, DECIMALSUBTRACT algebraically subtracts the decimal number fromthe contents of the decimal accumulator, and then loadsthe difference into the decimal accumulator. If the resultin the decimal accumulator is zero, the resulting sign isforced to the positive form.Overflow occurs if the difference exceeds the capacity ofthe decimal accumulator (i. e., if the absolute value of thedifference is equal to or greater than 10 31 ), in which caseCCl is reset to 0, CC2 is set to 1, and the instruction isaborted with the contents of the previous decimal accumulator,CC3 and CC4 unchanged.79Affected: (DECA), CCTrap: Decimal arithmetico 1 2(DECA) - EDO -DECAIf no illegal digit or sign is detected in the effective decimaloperand or in the decimal accumulator, DECIMAL ADDalgebraically adds the decimal number to the contents ofthe decimal accumulator. If the result in the decimalaccumulator is zero, the resulting sign is forced to thepositive form.Overflow occurs if the sum exceeds the capacity of thedecimal accumulator (i. e., if the absolute value of the sumis equal to or greater than 1031 ), in which case CCl isreset to 0, CC2 is set to 1, and the instruction aborted withthe previous contents of the decimal accumulator, CC3and CC4 unchanged.Affected: (DECA), CC(DECA) + EDO -DECATrap: Decimal arithmeticCondition code settings:o0002 3 4 Result in DECAo0 00 00- Illegal digit or )si gn detected- Overflow0 ZeroNegative0 PositiveInstruction abortedNo illegal digit or signdetected, no overflow,instruction completedDecimal Instructions 83

DMDECIMAL MULTIPLY(Byte index alignment, continue after interrupt)Condition code settings:2 3 4 Result in DECAIf no illegal digit or sign is detected in the effective decimaloperand or decimal accumulator, DECIMAL MULTIPLYmultiplies the effective decimal operand (multiplicand) bythe contents of the decimal accumulator registers R14 andR15 (multiplier) and then loads the product into the entiredecimal accumulator. If the result in the decimal accumulatoris zero, the resulting sign is forced to the positive form.Affected: {DECA}, CC(DECA) x EDO -DECACondition code settings:2 3 4 Result in DECAoTrap: Decimal arithmeticIllegal di git or sign detected, instructionabortedo 0 0 0 Zero J N ·,1 I d· . t .o I ega Igl or signo 0 0 Negative detected, instruction.. completedo 0 O P oSltlveDDDECIMAL DIVIDE(Byte index alignment, continue after interrupt)0 - Illegal digit orsign detected0 Overflow0 0 0 0 Zero quotientJ0 0 0 Negative quotient0 0 0 Positive quotientDCDECIMAL COMPARE(Byte index alignment)Instruction abortedNo illegal digit orsign detected, nooverflow, i nstructioncompletedIf there is no illegal digit or sign in the effective decimaloperand or in the decimal accumulator, DECIMAL COMPAREexpands the effective decimal operand to 16 bytes (31 digitsplus sign) by appending high-order O's, algebraically comparesthe expanded decimal number to the contents of theentire decimal accumulator, and sets CC3 and CC4 accordingto the result of the comparison (a positive zero comparesequal to a negative zero).Affected: CCTrap: Decimal arithmetic(DECA) : EDOIf there is no illegal digit or sign in the effective decimaloperand and if there is at least one decimal sign in thedecimal accumulator, DECIMAL DIVIDE divides the contentsof the decimal accumulator (dividend) by the effectivedecimal operand (divisor). Then, if no overflow hasoccurred, the basic processor loads the quotient (15 decimaldigits plus sign) into the eight low-order bytes of thedecimal accumulator (registers 14 and 15), and loads theremainder (also 15 decimal digits plus sign) into the eighthigh-order bytes of the decimal accumulator (registers 12and 13). The sign of the remainder is the same as that ofthe original dividend. If the quotient is zero, the sign ofthe quotient is forced to the positive form.Condition code settings:2 3 4 Result of comparisonoIllegal digit or sign detected, instructionaborted0 0 0 0 (DECA) equals EDO1 No i! lega! digit0 0 0 (DECA) less than EDO or sign detected,instruction0 0 0 (DECA) greater than ) completedEDOOverflow occurs if any of the following conditions are notsatisfied before the initial execution of DECIMAL DIVIDE:1. The divisor must not be zero.DSADECIMAL SHIFT ARITHMETIC(Byte index alignment)2. If the length of the dividend is greater than 15 decimaldigits, the absolute value of the significant digits tothe left of the 15th digit position (i. e., those digits inregisters 12 and 13) must be less than the absolute valueof the divisor.Affected: (DECA), CC(DECA) .;- EDO -DECATrap: Decimal arithmeticIf no illegal digit or sign is detected in the decimal accumulator,DECIMAL SHIFT ARITHMETIC arithmetically shiftsthe contents of the decimal accumulator (excluding thedecimal sign), with the direction and amount of the shiftdetermined by the effective virtual address of the instruction.If the result in the decimal accumulator is zero, theresulting sign remains unchanged.84 Decimal Instructions

If no indirect addressing or indexing is used with DSA, theshift count C is the confents of bit positions 16-31 of theinstruction word. If on Iy indirect addressing is used withDSA, the shift count is the contents of bit positions 16-31of the word pointed to by the indirect address in the instructionword. If indexing only is used with DSA, theshift count is the contents of bit positions 16-31 of theinstruction word plus the contents of bit positions 14-29of the designated index register (bits 0-13, 30, and 31 ofthe index are ignored). If indirect addressing and indexingare both used with DSA, the shift count is the sum of thecontents of bit positions 16-31 of the word pointed to by theindirect address and the contents of bit positions 14-29 ofthe designated index register.The shift count, C, is treated as a 16-bit signed binaryinteger, with negative integers in two·s complement form.If the shift count is positive, the contents of the decimalaccumulator are shifted left C decimal digit positions; ifthe shift count is negative, the contents of the decimalaccumulator are shifted right -C decimal digit positions.In either case, the decimal sign is not shifted, vacateddecimal digit positions are fi lied with O·s, and any digitsshifted out of the decimal accumulator are lost. Althoughthe range of possible values for C is 2-15 $ C $ 215-1.a shift count greater than +31 or less than -31 is interpretedas a shift count of exactly +31 or -31.PACKPACK DECIMAL DIGITS(Byte index alignment)PACK DECIMAL DIGITS converts the effective decimaloperand (assumed to be in zoned format) into a packeddecimal number and, if necessary, appends sufficient highorderO·s to produce a decimal number that is 16 bytes(31 decimal digits plus sign) in length. The zone (bits 0-3)of the low-order digit of the effective deci mal operand isused to select the sign code for the packed decimal number;all other zones are ignored in formatting the packed decimalnumber. If no i /legal digit or sign appears in the packeddecimal number, it is then loaded into the decimal accumulator.If the result in the decimal accumulator is zero,the resulting sign remains unchanged.The L field of this instruction specifies the length, in bytes,of the resultant packed decimal number in the decimal accumulator;therefore, the length of the effective decimaloperand is 2L-1 bytes (where L = 0 implies a length of31 bytes for the effecti ve deci ma I operand).Affected: (DECA), CCTrap: Decimal arithmeticIf any nonzero decimal digit is shifted out of the decimalaccumulator during a left shift, CC2 is set to 1; otherwise,CC2 is reset to O. CC2 is unconditionally reset to 0 at the •completion of a right shift.packed (EBL to EBL + 2L - 2) -DECACondition code settings:Affected: (DECA), CCCondition code settings:Trap: Decimal arithmetic2 3 4 Result in DECAo - - Illegal digit or sign detected, instructionaborted2 3 4 Result in DECAoo - 0 0 ZeroIllegal digit or sign detected, instructionabortedo 0 0 0 ZeroNo i /legal digit or sign0 0 0 Negative detected, instructioncompleted0 0 0 Positiveo - 0NegativeExample 1, L = 6:o - 0 Positiveo 0oRight shift or no nonzerodigit shifted outof DECA on left shiftOne or more nonzerodigit(s) shifted out ofDECA on left shiftNo illegal digitor sign detected,i nstructi oncompletedBefore executionAfter executionEDO X·FOF1F2F3 X·FOF1F2F3F4F5F6F7F4F5F6F7F8F9FO·F8F9FO·(DECA) xxxxxxxx X·OOOOOOOOxxxxxxxx 00000000xxxxxxxx 00000123xxxxxxxx 4567890C·CC xxxx 0010Decimal Instructions 85

ExamEle 2, L = 6:Example 1, L = 10:Before executionAfter executionBefore executionAfter executionEDO X'000938F7 X'000938F7E655B483E655B48302F1 BO'02F1BO'(DECA)X'ooOOOOOO00000001234567890123456D'X'OOOOOOOO00000001234567890123456D'(DECA) xxxxxxxx X'ooOOOooOxxxxxxxx 00000000xxxxxxxx 00000987xxxxxxxx6543210D'CC xxxx 0001EDOCCxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxX'FOFOFOFlF2F3F4F5F6F7F8F9FOF1F2F3F4F5D6'OOxxUNPKUNPACK DECIMAL DIGITS(Byte index alignment, continue after interrupt)Example 2, L = 8:Before executionAfter executionIf no illegal digit or sign is detected in the decimal accumulator(assumed to be in packed decimal format), UNPACKDECIMAL DIGITS converts the contents of the low-orderL bytes of the decimal accumulator to zoned decimal formatand stores the result, as a byte string, from the effectivebyte location to the effective byte location plus 2L-2.The contents of the four low-order bit positions of the decimalaccumulator are used to select the sign code for thelast digit of the string; for all other digits, the zones are1111 (X'F'). The contents of the decimal accumulator remainunchanged, and only 2L-l bytes of memory are altered.If the decimal accumulator contains more significant informationthan is actually unpacked and stored, CC2 is set to 1;otherwise, CC2 is reset to O. If the result in memory iszero, the resulting sign remains unchanged.Affected: (EBltoEBL+2L-2),CC1, CC2zoned (DECA) - EBL to EBL + 2L -2Trap: Decimal arithmetic(DECA)EDOCCX'OOOOOOOO23000000100012340012345C'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxExample 3, L = 4:(DECA)EDOBefore executionX '0000 100 100001002000010030001004F'xxxxxxxxxxxxxxxxX '000000002300000010001234OO12345C'X'F1FOFOFOF1F2F3F4FOFOF1 F2F3F4C5'01xxAfter executionX'OOOOlool00001002000010030001004F'X'FOFOFOF1FOFOC4'Condition code settings:CCxxxxOlxx2 3 4 Result of UNPKoIllegal digit or sign detected, instructionabortedo 0 - - All significant informationzoned andstoredoSome signifi cantinformation notzoned and storedNo illegal digitor sign detected,instructioncompletedBYTE -STRING INSTRUCTIONSFive instructions provide for the manipulation of strings ofconsecutive bytes. The byte-string instructions and theirmnemonic codes ore as f()lI()ws~Instruction NameMnemonicMove Byte StringMBSCompare Byte StringCBS86 Byte-String Instructions

Instruction NameMnemonicDesignationFunctionTranslate Byte StringTrans I ate and Test Byte Stri ngEdit Byte StringTBSTTBSEBSThese instructions are in the immediate byte operand classand are memory-to-memory operations. These operationsare under the control of information that must be loadedinto certain general registers before the instruction is executed.Except for the MOVE BYTE STRING instruction,which proceeds four bytes at a time under certain conditions,a byte string instruction proceeds one byte at a timeand may be interrupted after any individual byte operation.Upon return, execution resumes from the pointofinterruption.The general format for the information in the instructionword and in the general registers is as follows:Instruction word:Contents of register R:Contents of register Ru 1 :CountDesi gnationOperationRFunctionDesti nation nrlrlr~~~The 7-bit operation code of the instruction.(If any byte-string instruction isindirectly addressed, the basi c processortraps to location X l 40 1 at the time of operationcode decoding. )The 4-bit field that identifies register Rof the current general register block.Source Address(cont. )CountDestinationAddressbyte of the source byte string operand.The effective source address is the sourceaddress in register R plus the displacementvalue in the instruction word.An 8-bit field that contains the true count(from 0 to 255) of the number of bytesinvolved in the operation. This field isdecremented by 1 as each byte in thedestination byte string is processed. Ao count means IIno operation ll with respectto the registers and main memory.A 19-bit field that contains the byteaddress of the first (most significant)byte of the destination byte-string operand.This field is incremented by 1 aseach byte in the destination byte stringis processed.In any byte-string instruction, any portion of register Ror Ru1 that is not explicitly defined (i. e., bit positions8-12), should be coded with zeros for real and virtualaddressi ng.Since the value Ru1 is obtained by performing a logicalinclusive OR with the value 0001 and the value of theR field of the instruction word, the two control registersare Rand R + 1 if R is even. However, if R is an odd value,register R contains an address value that functions both as asource operand address and as a destination operand address.Also, if register 0 is designated in any byte-string instruc-... ___ 1 _______ .. ~ ___ TnA ... IC"1 ATe A"'I/""'\ TeC"T n'\rre C"TnT"'I"" ____ IIIVII \CAvCPI IVI "'\r\I'4"'LJ"'IL r\1'4V IL ... I U,I ........'\11'4'\,.7 UIIUEDIT BYTE STRING), its contents are ignored and a zerosource address value is obtained. Thus, the followingthree cases exist for most byte-string instructions, dependingon whether the value of the R field of the instruction wordis even and nonzero, odd, or zero:Case I, R is even and nonzeroThe effective source address is the address in register R plusthe displacement in the instruction word; the destinationaddress is the address in register R + 1, but without thedisplacement added.DisplacementMask/FillSource AddressA 20-bit field that contains a signedbyte displacement va lue, used to forman effective byte address. The displacementvalue is right-justified in the 20-bitfield, and negative values are in twolscomplement form.An 8-bit field used only with TRANSLATEAND TEST BYTE STRING and EDIT BYTESTRING. The purpose of this field isexplained in the detai led discussion ofthe TTBS and EBS instructions.A 19-bit field that normally contains thebyte address of the first (most significant)Case II, R is oddThe effective source address is the address in register R plusthe displacement in the instruction word; the destinationaddress is also the address in register R, but without thedisplacement added.Case III, R is zeroThe effective source address is the displacement value inthe instruction word; the destination address is the addressin register 1. In this case, the source byte-string operandis always a single byte.Byte-String Instructions 87

In the descriptions of the byte-string instructions, thefollowing abbreviations and terms are used:MBSMOVE BYTE STRING(Immediate Displacement, continue after interrupt)o Displacement, (1)12-31.SAESACDASBSDBSSource address, (R)13-31Effecti ve source address, [(R) 13 -31 +(1) 12 -31} 3 -31The contents of bit positions 13-31 of register Rare added (right aligned) to the contents of bitposi tions 12-31 of the instruction word; the 19 loworderbits of the result are used as the effectivesource address.Count, (Ru1)0_7Destination address, (Ru1)13_31Source byte string, the byte' string that begins withthe byte location pointed to by the 19-bit effectivesource address and is C bytes in length (ifR is 0).Destination byte string, the byte string that beginswith the byte location pointed to by the destinati on address and is always C bytes in length.MOVE BYTE STRING copies the contents of the source bytestring (left to right) into the destination byte string. Theprevious contents of the destination byte string are destroyed,but the contents of the source byte string are notaffected unless the destination byte string overlaps thesource byte string.When the destination byte string overlaps the source bytestring, the resulting destination byte string contains one ormore repetitions of bytes from the source byte string. Thus,if a destination byte string of C bytes begins with thekth byte of a source byte string (numbering from 1), the firstk-1 bytes of the source byte string are duplicated in thedestination byte string x number of times, where x = C/{k-1).For example, if the destination byte string begins with thesecond byte of the source byte string, the first byte of thesource byte string is duplicated throughout the destinationbyte string.If both byte strings begin with the same byte (i. e., k = 1)and the R field of MBS is nonzero, the destination bytestring is read and replaced into the same memory locations.However, if both byte strings begin with the same byte andthe R field of MBS is zero, the first byte of the byte stringis duplicated throughout the remainder of the byte string(see "Case 111", below).Affected: (DBS), (R), (Ru1)(SBS) -DBSTRAPS BY BYTE-STRING INSTRUCTIONSByte-string instructions cause a trap if either of the addressedbyte strings come from memory pages that are protected byeither access protection or write locks. A trap also occursif elther byte stdng is fully or partly contoi!"'!ed with!!"'! memorypages that are physically not present. A check forthese access trap conditions is made prior to initiation ofany byte relocation or general register change. These testsare performed for MOVE BYTE STRING and TRANS LATEBYTE STRING. The source and destination locations aretested for MOVE BYTE STRING; only the destination locationis tested for TRANSLATE BYTE STRING, since thereis no assurance that the translate table wi II be accessed inits entirety in the course of execution. If an access protectionviolation were to occur in trying to reach a byte inthe translate table or decimal digit strings during the courseof execution, then the instruction would trap and result inCi pCii-tiCilly executed condition. However, if the destinationbyte string does overlap the translation table, the registerswould be restored in such a manner that the instructioncould be restarted after the protection violation had beencorrected. When a trap occurs resulting in a partiallyexecuted instruction, the Register Altered indi cator wi"be set.If MBS is indirectly addressed, it is treated as a nonexistentinstruction. The basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contents ofregister R and the destination byte string unchanged. See"Traps by Byte String Instructions" (in this section) for othertrap conditions.Case I, even, nonzero R fi e Id (Ru 1 =R + 1)Contents of register R:Contents of register R+1:The source byte string begins with the byte location pointedto by the source address in register R plus the displacementin MBS; the destination byte string begins with the byte locationpointed to by the destiratior address in register R+l.88 Byte-String Instructions

Both byte strings are C bytes in length. When the instructionis completed, the destination and source addresses are eachincremented by C, and C is set to zero.Case II, odd R fi e Id (Ru 1 =R)Contents of register R:The source byte string begins with the byte location pointedto by the address in register R plus the displacement in MBS;the destination byte string begins with the byte locationpointed to by the destination address in register R. Bothbyte strings are C bytes in length. When the instruction iscompleted, the destination address is incremented by C,and C is set to zero.Condition code settings:2 3 4 Result of CBS- 0 0 Source byte string equals destination bytestring or initial byte count is equal to zero.- 0 Source byte string less than destination bytestring.o Source byte string greater than destinationbyte string.If CBS is indirectly addressed, it is treated as a nonexistentinstruction. The basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contentsof register R and the destination byte string unchanged.See "Traps By Byte String Instructions" (in this section) forother trap conditions.Case III, zero R field (Rul=l)Contents of register 1:Case I, even, nonzero R field {Rul=R+l}Contents of register R:The source byte string consists of a single byte, the contentsof the byte location pointed to by the displacement inMBS; the destination byte string begins with the byte locationpointed to by the destination address in register 1 andis C bytes in length. In this case, the source byte is duplicatedthroughout the destination byte string. When theinstruction is completed, the destination address is incrementedby C, and C is set to zero.Contents of register R+l:Ihe source byte string begins with the byte iocatlon pointedto by the source address in register R plus the displacementin CBS; the destination byte string begins with the byte locationpointed to by the destination address in register R+l.Both byte strings are C bytes in length.CBSCOMPARE BYTE STRING{Immediate displacement, continue after interrupt}Case II, odd R field (Ru l=R)Contents of register R:COMPARE BYTE STRING compares, as magnitudes, thecontents of the source byte string with the contents ofthe destination byte string, byte by corresponding byte,beginning with the first byte of each string. The comparisoncontinues unti I the specified number of bytes havebeen compared or unti I an inequality is found. When CBSis terminated, CC3 and CC4 are set to indicate the resultofthe last comparison. If the CBS instruction terminates due toinequality, the count in register Rul is one greater than thenumber of bytes remaining to be compared; the source addressin register R and the destination address in register Rulindicate the locations of the unequal bytes.Affected: {R}, (Rul), CC3, CC4(SBS) : (DBS)The source byte string begins with the byte location pointedto by the address in register R plus the displacement in CBS;the destination byte string begins with the byte locationpointed to by the destination address in register R. Bothbyte strings are C bytes in length.Case III, zero R field (Rul=l)Contents of register 1:The source byte string consists of a single byte, the contentsof the location pointed to by the displacement in CBS;Byte-String Instructions 89

the destination byte string begins with the byte locationpointed to by the destination address in register 1 andis C bytes in length. In this case, the source byte is comparedwith each byte of the destination byte string unti I aninequality is found.TBSTRANSLATE BYTE STRING(Immediate displacement, continue after interrupt)TRANSLATE BYTE STRING replaces each byte of the destinationbyte string with a source byte located in a translationtable. The destination byte string begins with the byte locationpointed to by the destination address in regi ster Ru 1,and is C bytes in length. The translation table consists ofup to 256 consecutive byte locations, with the first bytelocation of the table pointed to by the displacement in TBSplus the source address in register R. A source byte is definedas that which is in the byte location pointed to by the19 low-order bits of the sum of the following values.1. The displacement in bit positions 12-31 of the TBSinstruction.Contents of register R+l:The destination byte string begins with the byte locationpointed to by the destination address in register R + 1 andis C bytes in length. The source byte string {translationtable} begins with the byte location pointed to by the displacementin TBS plus the. source address in register R.When the instruction is completed, the destination addressis incremented by C, C is set to zero, and the source addressremains unchanged.Case II, odd R fi e Id {Ru 1 =R}Because of the interruptible nature of TRANSLATE BYTESTRING, the instruction traps with the contents of register Runchanged when an odd-numbered general register is specifiedby the R field of the instruction word.Case III, zero R field {Ru1=1}Contents of register 1:2. The current contents of bit positions 13-31 of register R{source address}.3. The numeric value of the current destination byte, the8-bit contents of the byte location pointed to by thecurrent destination address in bit positions 13-31 ofregister {Ru 1}.The destination byte string begins with the byte locationpointed to by the destination address in register 1 andis C bytes in length. The source byte string {translationtable} begins with the location pointed to by the displacementin TBS. When the instruction is completed, the destinationaddress is incremented by C and C is set to zero.Affected: (DBS), {Ru 1}translated (DBS) -DBSTrap: Instruction exceptionTTBSTRANSLATE AND TEST BYTE STRING{Immediate displacement, continue after interrupt}The R field of the TBS instruction must be an even value forproper operation of the instruction; if the R field of TBS isen odd value, the instruction traps to location X'4D',instruction exception trap.If TBS is indirectly addressed, it is treated as a nonexistentinstruction. The basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contents ofregister R and the destination byte string unchanged.See IITraps By Byte String Instructions" (in this section) forother trap conditions. Note that the check for access trapconditions is done only for the source byte string.Case I, even, nonzero R field (Ru1=R+l)Contents of register R:TRANSLATE AND TEST BYTE STRING compares the maskin bit positions 0-7 of register R with source bytes in a bytetranslation table. The destination byte string begins withthe byte location pointed to by the destination address inregister Rul, and is C bytes in length. The byte translationtable and the translation bytes themselves are identi cal tothat described for the instruction TRANSLATE BYTE STRING.The destination byte string is examined (without beingchanged) unti I a translation byte {source byte} is found thatcontains a 1 in any of the bit positions selected by a 1 inthe mask. When such a translation byte is found, TTBSreplaces the mask with the logical product (AND) of thetransiation byte and the mask, and terminates with CC4set to 1.If the TTBS instruction terminates due to the above condition,the count (C) in register Rul is one greater thanthe number of bytes remaining to be compared and thedestination address in register Rul indicates the location90 Byte-String Instructions

of the destination byte that caused the instruction toterminate. If no translation byte is found that satisfiesthe above condition after the specified number of destinationbytes have been compared, TTBS terminates with CC4reset to O. In no case does the TTBS instruction changethe source byte stri ng.Case II, odd R fieldBecause of the interruptible nature of TRANS LATE ANDTEST BYTE STRING the instruction traps with the contentsof register R unchanged when an odd-numbered general registeris specified by the R field of the instruction word.Affected: (R), (Rul), CC4Trap: Instruction exceptionIf translated (SBS) n mask I 0, translated (SBS) n maskmaskand stopIf translated (SBS) n mask = 0, continueCase III, zero R field (Rul=1)Contents of register 1:Condition code settings:2 3 4 Result of TTBS- 0 Translation bytes and the mask do not compareones any place.The last translation byte compared with themask contained at least one 1 correspondingto a 1 in the mask.The destination byte string begins with the byte locationpointed to by the destination address in register 1 and isC bytes in length. The source byte string (translation table)begins with the location pointed to by the displacement inTTBS. In this case, the instruction automatically providesa mask of eight lis. (This is an exception to the generalrule, used in the other byte-string instructions, the register0 provides all OIS as its contents. )The R field of the TTBS instruction must be an even valuefor proper operation of the instruction; if the R field of TTBSis an odd value, the instruction traps to location X l 4D I ,instruction exception trap.If TTBS is indirectly addressed, it is treated as a nonexistentInsrrucrion. The basic processor unconciiTionaiiy abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X I 40 1 with the contents ofregister R and the destination byte string unchanged.See IITraps By Byte String Instructions" (in this section) forother trap conditions. Note that the check for access trapconditions is done only for the source byte string.Case I, even, nonzero R field (Rul=R+1)Contents of register R:Contents of register R+l:Count I !: Destination ~ddress Io 1 2 314 5 6 7 8 9 10 11112 13 14 15 16 17 18 19120 212223;2425262712829 30 31The destination byte string begins with the byte locationpointed to by the destination address in register R + 1 andis C bytes in length. The source byte string (translationtable) begins with the byte location pointed to by the displacementin TTBS plus the source address in register R.EBSo 1 2EDIT BYTE STRING(Immedi ate displacement, continue after interrupt)63 I R I : DisPlacem~nt I7 8 9 10 11 12 13 14 15 16 17 18 19120 21 22 23 24 25 26 27128 29 30 31EDIT BYTE STRING converts a decimal information fieldfrom packed decimal format to zoned decimal EBCDIC format,under control of the editing pattern in the destinationbyte string, and replaces the destination byte string with theedited, zoned result. (See "Decimal Instructions", "PackedDecimal Numbers", and "Zoned Decimal Numbers" fora description of packed and zoned decimal formats.) EBSproceeds one byte at a time, starting with the first (mostsignificant) byte of the editing pattern, and continuesunti I all bytes in the editing pattern have been processed.The fill character, contained in bit position 0-7 of registerR, replaces the pattern byte under specifi ed conditions.More than one decimal number field can be edited by asingle EBS instruction if the pattern in memory is, in fact,a series of patterns corresponding to a series of numberfields. In such cases, however, after the EBS instruction iscompleted, the condition code indicates the result of thelast decimal number field processed and register 1 containsthe byte address (or the byte address plus 1) of the last significanceindicator in the edited destination byte string.(This allows the insertion of a floating dollar sign, etc.,with a subsequent instruction. )R must be an even value (excluding 0) for proper operationof the instruction; if R is an odd value or equal to zero, thebasic processor traps to location X I 4D I , instruction exceptiontrap, with the contents in register R unchanged.Byte-String Instructions 91

••••Contents of register R:Contents of register R+l:(and only one) of the following actions with the pattern byteand the decimal digit:1. The fi II character (contents of bit positions 0-7 of registerR) or a blank character replaces the byte in thedestination byte string.2. The decimal digit is expanded to zoned decimal format'and replaces the pattern byte in the destination bytestring.The destination byte string is an editing pattern that beginsin the byte location pointed to by the destination addressin register R + 1, and is C bytes in length. The decimalinformation field, which must be in packed decimal format,begins with the byte location pointed to by the displacementin EBS plus the source address in register R. The decimalinformation field must contain legal decimal digit andsign codes (packed format) and must begin with a decimaldigit.The destination byte string (the editing pattern) may containany 8-bit codes desired. However, four byte codesin the editing pattern have special meanings. These codesare as follows:Binary value Function Abbrevi ati on0010 0000 (X'20 ') Digit selector ds0010 0001 (X'211) Signifi cance start ss0010 0010 (X'221) Field separation fs0010 0011 (X'23 1 ) Immediate signifi- sicance startBefore executing EBS, the condition code should be sett" • _____ MOO if •• tho 1.1- hi"h ..........Io .. ...Ii"a .... f tho ...Io,...;m,.,1 ..... mho .. ;., i ....".~ _. __ • _.~ _ ••••____•••• _ ••• _ ••• ....,_..... IIIthe left half of a byte, and should be set to 0100 if thehigh-order digit is in the right half of a byte.The editing operation performed on each pattern byte ofthe destination byte string is determined by the followingcondi tions:1. The pattern byte obtained from the destination bytestring.2. The decimal digit obtained from the decimal numberfield.3. The current state of the condition code.Depending upon various combinations of these conditions'the instruction EDIT BYTE STRING performs one3. The pattern byte remains unchanged.In general, the normal editing process is as follows:1. Each byte of the destination byte string is replaced bya fi II character until significance is present, either inthe destination byte string or in the decimal informationfield. Significance is indicated by any of thefollowing:a. The pattern byte is X' 23 1 (immediate significancestart), which begins significance with the currentdecimal digit.b. The pattern byte is X' 21 1 (significance start),which begins significance with the following patternbyte.c. The current decimal digit is nonzero, which beginssignifi cance with the current pattern byte.2. After significance is encountered, each pattern bytethat is X' 20' (digit selector), X' 21 1(significance start),X'22 1 (field separator), or X' 23 1 (immediate significancestart) is replaced by a zoned decimal numberfrom the decimal field and all other pattern bytes areunchanged. This process continues unti I any of thefollowing conditions occurs:a. A positive sign is encountered in the decimal field,in which case subsequent pattern bytes are replacedby blank characters unti I significance isagain present, unti I a field separator is encountered,or unti I the destination byte string is entirelyprocessed, whichever occurs first.b. A negative sign is encountered in the decimalfield, in which case subsequent pattern bytes areunchanged unti I signifi cance is again present, unti Ia field separator is encountered, or unti I the destinationbyte string is entirely processed, whi cheveroccurs fi rst.c. A pattern byte of X' 22 1 (field separator) is encountered,in which case the field separator is replacedby a fi II character; subsequent pattern bytes are replacedby the fill character until significance is92 Byte-String Instructions

again present, unti I a positive or negative sign isencountered, or unti I the destination byte stringis entirely processed, whichever occurs first.d. The destination byte string is entirely processed,in which case the basic processor executes thenext instruction in sequence.Detai led operation of EDIT BYTE STRING follows. Theexplanation is necessari Iy quite detailed due to the highdegree of flexibi lity inherent in EBS. Condition codesettings are made continuously during the editing processand these settings help determine how each subsequent patternbyte will be edited. The summary of condition codesettings given later in this section wi II help clarify thefollowing discussion:1. If the count in bit position 0-7 of register R+l is anonzero, a pattern byte is obtained from the destinationbyte string; if the count in register R+l is 0,the basi c processor executes the next instruction insequence.2. If the pattern byte is a digit selector (X'20'), a significancestart (X'211), or immediate significancestart (X'23 1 ), a digit is accessed from the decimalinformation field as follows:a. A decimal byte is obtained from the byte locationpointed to by the displacement in EBS plus thesource address in register R.b. If bits 0-3 of the decimal byte are a sign code,the basi c processor auto mati ca lIy aborts executi onor EBS ana traps ro iocarion X;45;, wlrh the contentsof register R, register R+l, the conditioncode, and the destination byte string unchangedfrom their current contents.c. If CC2 is currently set to 0, the digit to be usedfor editing is the left digit (bits 0-3) of the decimalbyte; however, if CC2 is currently set to 1,the digit to be used is the right digit (bits 4-7)of the decimal byte. In either case, CC3 is setto 1 if the digit is nonzero. If CC2 is set to 1and the right digit (bits 4-7) of the decimal byteis a sign code, the basic processor automaticallyaborts execution of EBS and traps to location X'45 1 ,as described above.d. One of the following editing actions is performed:ConditionsActionMarkConditions Action MarkPattern byte=S S (X 1211)CC4=l (cont.)(because CC4= 1 meanssignificance alreadyencountered}.Pattern byte=SS Expand digit to zoned Mode 1CC4--oformat, store in patnonzerodigittern byte location(because nonzero digitbegins significance),and set CC4 to 1.Pattern byte=SS Store fi II character in Mode 2CC4--opattern byte locationdigit=O(because significancestarts with next patternbyte) and setCC4 to 1.Pattern byte=DS(X'20'} Expand digit to zoned NoneCC4=lformat, and storedigit in pattern bytelocation.Pattern byte=DS Expand digit to zoned Mode 1CC4=Oformat, store digit innonzero digitpattern byte location,and set CC4 to 1 tosignal significance.Pattern byte=DS Store fi II character in NoneCC4=Opattern byte locati ondigit=O(because significancenot encountered yet).e. If CC2 is currently reset to 0 and if bits 4-7 ofthe decimal byte are a positive decimal sign code,CCl is set to 1, CC4 is reset to 0, and the sourceaddress in register R is incremented by 1. If CC2is currently reset to 0 and if bits 4-7 of the decimalbyte are a negative decimal sign code, CCland CC4 are both set to 1, and the source addressis incremented by 1. Otherwise, CC2 is addedto the source address and then CC2 is inverted.f. If marking is invoked at set d, above, one of thetwo following marking operations are performed:Mode 1: Load bits 13-31 of register R+l into bitpositions 13-31 of register 1; bit positions0-12 of register are unpredictable.Pattern byte=SI(X '23 1 )Expand digit to zonedformat, store in patternbyte locati on,and set CC4 to 1 (startsignificance).Mode 1Mode 2: Load bits 13-31 of register R+l into bitpositions 13-31 of register 1 and thenincrement the contents of register 1by 1; bit positions 0-12 of register 1 areunpredictable.Pattern byte=SS(X'21I)CC4=1Expand digit to zonedformat and store inpattern byte locationNoneIf marking is not applicable (i. e., significancehas not been encountered), the contents of register1 are not affected.Byte-String Instructions 93

3.4.5.If the pattern byte is a field separator (X'22'), the fillcharacter is stored in the pattern byte location. CC1,CC3, and CC4 are all reset to O's, and CC2 remainsunchanged.If the pattern byte is not a digit selector, significancestart, immediate significance start, or field separator,one of the following actions are performed:ConditionsCC1=O }CC4=OCC1=1 }CC4=OCC4=lActionStore fill character in pattern bytelocation.Store blank character (X'40') in patternbyte location.None (pattern byte remains unchanged).Increment the destination address in regi ster Ru 1 anddecrement the count in regi ster Ru 1. If the count issti II nonzero, process the next pattern byte as above;otherwise, execute the next instruction in sequence.R field is an odd value or equal to zero, the instructiontraps to location X'40', instruction exception trap.If an i "egal digit or sign is detected in the decimal informationfield, the basic processor unconditionally abortsexecution of the instruction (at the time the i "egal digitor sign is encountered) and traps to location X'45' with thecontents of register R, register Ru1, register 1, the destinationbyte string, and the condition code containing the resultsof the last editing operation performed before theillegal digit or sign was encountered.See "Traps By Byte-String Instructions llfor other trap conditions.(in this section)In the following examples, the hexadecimal codes for thedigit selector (X' 20'), the significance start (X'21'), thefield separation (X'22'), and the immediate significancestart (X'23') are represented by the character groups ds,ss, fs, and si, respectively. Also, the symbol 1:> is used torepresent the character blank (X'40'). Note that code X'5C'represents the * symbol.Affected: (R),(Ru1)(register 1),(OBS), CCedited (SBS) -OBSTraps: Nonexistentinstruction,decimal arithmetic,instructionexceptionExample 1, before execution:The instruction word isX '63600000'Condition code settings:oo2 3 4 Result of EBS- 0 Significance is not present, no sign digit hasbeen encountered.Signifi cance is present, no sign digit has beenencountered.- 0 A positive sign has been encountered.A negative sign has been encountered.- 0 Next digit to be processed is leftdigitofbyte.Nextdigit to be processed is rightdigitofbyte.- 0 No nonzero digit has been encountered.- A nonzero digit has been encountered.If EBS is indirectly addressed, it is treated as a nonexistentinstruction. The basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contents ofregister R, register Rul, register 1, the destination bytestring, and the condition code unchanged.The R field of the EBS instruction must be an even value(excluding 0) for proper operation of the instruction; if theThe contents of register 6 are:X'5C000100'The contents of register 7 are:X'OCOO1ooo'The contents of the decimal information field beginning atbyte location X'100' are:0000000+The contents of the destination byte string beginning at bytelocation X'lOOO' are:ds ds , ds ds ss . ds ds 1:> C RThe condition code is:0000Example 1, after execution:The instruction word is unchanged.The new contents of register 6 are:X'5C000104'94 Byte-String Instructions

The new contents of register 7 are:X'0000100C'The contents of the decimal information field are unchanged.The new contents of the destination byte string are:******.00'b'b'bThe new condition code is:1000The contents of register 1 are:X'xxx010061By subsequent programming, a floating dollar sign can beinserted in front of the fi rst si gn ifi cant character of theedited byte string by using the contents of register 1,minus 1, as the address of the byte location where thedollar sign is to be inserted.Example 3, after execution:The instruction word and the decimal field are unchanged.The new contents of registers 6 and 7 are identical to thatgiven for example 1.The new contents of the destination byte string are:***543.21'b'b'bThe new condition code is:1010The new contents of register 1 are:X1xxxO 1 003 1Example 4, before execution:The instruction word is:XI 63400 1 00 1The contents of register 4 dre:Example 2, before execution:The initial conditions are identical to example 1, exceptthat the contents of the decimal information field are:065432 1-X'lB001000'The contents of register 5 are:XI 19002000 1Example 2, after execution:Jhe instruction word and the decimal field are unchanged.The new contents of registers 6 and 7 are identical to thosegiven for example 1.The new contents of the destination byte string are:*6,543.21'bCRThe new condition code is:1011The new contents of register 1 are:X' xxx01001 1Example 3, before execution:The initial conditions are identical to example 1, exceptthat the contents of the decimal field are:00 54 32 1+byte location X' l100' are:06 12 50 0+ 01 23 4+ 03 5-The contents of the destination byte stri-ng beginning at bytelocation X' 2000' are: -A ds ds si . ds ds ds fs B ds ds ss . ds ds C fs Dsi ds ds ENDThe condition code is:0100Example 4, after execution:The instruction word is unchanged.The new contents of register 4 are:XI 7BOO 1 009 1The new contents of register 5 are:X'00002019 1The decimal information field is unchanged.Byte-String Instructions 95

The new contents of the destination byte string are:# 6 1 2 . 5 0 0 # # # 1 2 . 3 4 f) # # 0 3 5 ENDThe new condition code is:1011The new contents of register 1 are:X'xxx02013'Bit positions 15 through 31 of the SPD contain a 17-bitaddress field t that points to the location of the word currentlyat the top (highest-numbered address) of the operandstack. In a push operation, the top-of-stack addressis incremented by 1 and then an operand in a general registeris pushed (stored) into that location, thus becomingthe contents of the new top of the stack; the contents ofthe previous top of the stack remain unchanged. In a pulloperation, the contents of the current top of the stack arepulled (loaded) into a general register and then the topof-stackaddress is decremented by 1; the contents of thestack remain unchanged.PUSH-DOWN INSTRUCTIONS (NON-PRIVILEGED)The term "push-down processing ll refers to the programmingtechnique (used extensively in recursive routines) of storingthe context of a calculation in memory, proceeding with anew set of information, and then activating the previouslystored information. Typically, this process involves a reservedarea of memory (stack) into which operands arepushed (stored) and from which operands are pulled (loaded)on a last-in, first-out basis. The basic processor providesfor simplified and efficient programming of pushdownprocessing by means of the following non-privi legedinstructions:Instruction NamePush WordPull WordPush MultiplePull MultipleModify Stack Pointer_ ... _~T6r.1C ..... _pmNTI=R ........ _ nnnRI I=wnRn .....- ,---,I~PIl\.... -----_ .. _MnemonicPSWPLWPSMPLMMSPEach non-privileged push-down instruction operates withrespect to a memory stack that is defined by a doublewordlocated at effective address of the instruction. This doubleword,referred to as a stack pointer doubleword (SPD), hasthe following structure:I ~·I Space count I~I Word count I'32 '33 34 35136 37 ;8 39140 41 42 431« 45 46 47148 '49 50 5 d 52 53 54 55156 57 58 59160 61 62 63!tFor real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it is a17-bit field (15-31).Bit positions 33 through 47 of the SPD, referred to as thespace count, contain a 15-bit count (0 to 32,767) of thenumber of word locations currently avai lable in the regionof memory allocated to the stack. Bit positions 49 through 63of the SPD, referred to as the word count, contain a 15-bitcount (0 to 32,767) of the number of words currently in thestack. In a push operation, the space count is decrementedby 1 and the word count is incremented by 1; in a pull operation,the space count is incremented by 1 and the wordcount is decremented by 1. At the beginning of all nonprivileged push-down instructions, the space count and theword count are each tested to determine whether the instructionwould cause either count field to be incremented abovethe upper limit of 2 15 _1 (32,767), or to be decrementedbelow the lower limit of O. If execution of the push-downinstruction would cause either count limit to be exceeded,the basic processor unconditionally aborts execution of theinstruction, with the stack, the stack pointer doubleword,and the contents of general registers unchanged. Ordinari Iy,the basic processor traps to location X'42' after abortinga push-down instruction because of impending stack limitoverflow or underflow, and with the condition code unchangedfrom the value it contained before execution ofthe instruction.However, this trap action can be selectively inhibited bysetting either (or both) of the trap inhibit bits in the SPDto 1.Bit position 32 of the SPD, referred to as the trap-on-space(TS) inhibit bit, determines whether the basic processor wi IItrap to location X'42' as a result of impending overflow orunderflow of the space count (SPD33-47)' as follows:TSoSpace count overflow/underflow actionIf the execution of a pull instruction would cause thespace count to exceed 2 15 _1, or if the execution of apush instruction would cause the space count to beless than 0, the basic processor traps to location X'42'with the condition code unchanged.Instead of trapping to location X'42', the basic processorsets CCl to 1 and then executes the next instructionin sequence.Bit position 48 of the SPD, referred to as the trap-on-word('f\N) inhibit bit, determines whether the basic processor96 Push-Down Instructions (Non-Privi leged)

traps to location X'42 1 as a result of impending overflowor underflow of the word count (SPD 49-63)' as follows:the current status of the space count and the word count,respectively, as follows:TWoWord count overflow/underflow actionIf the execution of a push instruction would cause theword count to exceed 215-1, or if the execution ofa pull instruction would cause the word count to beless than 0, the basic processor traps to location X'42 1with the condition code unchanged.Instead of trapping to location X'421, the basic processorsets CC3 to 1 and then executes the nextinstruction in sequence.PUSH-DOWN CONDITION CODE SETTINGS2 3 4 Status of space and word counts- 0 - 0 The current space count and the current wordcount are both greater than zero.oThe current space count is greater than zero,but the current word count is zero, indicatingthat the stack is now empty. If the next operationon the stack is a pull instruction, theinstruction wi II be aborted.- 0 The current word count is greater than zero,but the current space count is zero, indicatingthat the stack is now fu II. If the next operationon the stack is a push instruction, theinstruction wi II be aborted.If the execution of a push-down instruction is attemptedand the basic processor traps to location X'421, the conditioncode remains unchanged from the value it containedimmediately before the instruction was executed.If the execution of a push-down instruction is attempted andthe instruction is aborted because of impending stack limitoverflow or underflow (or both) but the push-down stacklimit trap is inhibited by one (or both) of the inhibits (TSand TW), then, CC 1 or CC3 is set to 1 (or both are setto lis) to indicate the reason for aborting the push-downinstruction, as follows:If the basic processor does not trap to location X I 42 1 as aresult of impending stack limit overflow/underflow, CC2and CC4 indicate the status of the space and word countsat the termination of the push-down instruction, regardlessof whether the space and word counts were actually modifiedby the instruction. In the following descriptions ofthe push-down instructions, condition code settings givenare only those that can be produced by the instruction,provided that the basic processor does not trap to locationX1421.o2 3 4 Reason for abort- 0Impending overflow of word count on a pushoperation or impending underflow of wordcount on a pull operation. The push-downstack limit trap was inhibited by the TWbit (SPD4S).Impending overflow of space count on a pulloperation or impending underflow of spacecount on a push operation. The push-downstack limit trap was inhibited by the TS bit(SPDJ2)·Impending overflow of word count and underflowof space count on a push operation or impendingoverflow of space count and underflowof word count on a pull operation. The pushdownstack limit trap was inhibited by boththe TW and the TS bits.PSWPUSH WORD(Doubleword index alignment)PUSH WORD stores the contents of register R into the pushdownstack defined by the stack pointer doubleword locatedat the effective doubleword address of PSW. If thepush operation can be successfully performed, the instructionoperates as follows:1. The current top-of-stack address (SPD 15_ 31)t is incrementedby 1 to point to the new top-of-stack location.2. The contents of register R are stored in the locationpointed to by the new top-of-stack address.If a push-down instruction is successfully executed, CCland CC3 are reset to 0 at the completion of the instruction.Also, CC2 and CC4 are independently set to indi catet For real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it isa 17-bit field (15-31).push-I)own Instructions (Non-Privileged) 97

3. The space count (SPD33-47) is decremented by 1 andthe word count (SPD49-63) is incremented by 1.4. The condition code is set to reflect the new status ofthe space count.Affected: (SPD), (TSA+1), CC(SPD)15_31 + 1 -SPD 15_ 31tTrap: Push-down stack limit3. The space count (SPD33-47) is incremented by 1 andthe word count (SPD49-63) is decremented by 1.4. The condition code is set to reflect the status of thenew word count.Affected: (SPD), (R), CCTrap: Push-down stack limit(R) - (SPD 15_ 31)t(SPD)15_31- R; (SPD)15_31-1 -SPD 15_ 31t(SPD)33_47-1 - SPD 33_ 47{SPD)33_47 + 1 -SPD 33_ 4i(SPD) 49-63 + 1 - SPD 49-63Condi ti on code setti ngs:2 3 4 Result of PSW0 0 0 0 Space count is greaterthan O.0 0 0 Space count is now O.0 0 0 Word count = 2 15 _1 ,TW = 1.PLW0 0 Space count = 0,TS = 1.0 Space count = 0, wordcount = 0, TS = 1.0 Word count = 2 15 _1 ,space count = 0,TW = 1, and TS = 1.}PULL WORD(Doubleword index alignment)08 I R I x I 1Instructi oncompletedInstructionabortedReference address Io 1 2 3 14 5 718 9 10 llL2 13 14'15h6 17 18 19120 21 22 231242526 2712829 JO )PULL WORD loads register R with the word currently at thetop of the push-down stack defined by the stack pointerdoubleword located at the effective doubleword addressof PLW. If the pull operation can be performed successfully,the instruction operates as follows:1. Register R is loaded with the contents of the locationpointed to by the current top-of-stack address(SPD 1 5_31)t.2. The current top-of-stack address is decremented by 1,to point to the new top-of-stack location.tFor real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it isa 17-bit field (15-31).(SPD)49_63-1 -SPD 49-63Condition code settings:2 3 4 Result of PLW0 0 0 0 Word count is greaterthan O.0 0 0 Word count is now O.0 0 Word count = 0, TW = 1.0 Space count = 0,word count = 0, TW = 1.PSM0 0 00 115Space count = 2 -1,TS = 1.15Space count = 2 -1,word count = 0, TS = 1,and TW = 1.PUSH MULTIPLE(Doubleword index alignment)) InstructioncompletedInstructionabortedPUSH MULTIPLE stores the contents of a sequential set ofgeneral registers into the push-down stack defined by thestack pointer doubleword located at the effective doublewordaddress of PSM. The condition code must containa count of the number of registers to be pushed into thestack. (An initial value of 0000 for the condition codespecifics that ef! 16 genera! registers ere to be pushedinto the stack.) The registers are treated as a circular set(with register 0 following register 15) and the first registerto be pushed into the stack is register R. The last registerto be pushed in to the stack is register R + CC -1, and thecontents of this register become the contents of the newtop-of-stack location.98 Push-Down Instructions (Non-Privileged)

If there is sufficient space in the stack for all of thespecified registers, PSM operates as follows:1. The contents of registers R to R = CC - 1 are stored inascending sequence, beginning with the locationtion pointed to by the current top-of-stack address(SPD15_31)t plus 1 and ending with the current topof-stackaddress plus CC.2. The current top-of-stack address is incremented by thevalue of CC, to point to the new top-of-stack location.3. The space count (SPD33-47) is decremented by thevalue of CC and the word count is incremented by thevalue of CC.4. The condition code is set to reflect the new status ofthe space count.Affected: (SPD), (TSA+1) to(TSA+CC), CCTrap: Push-down stack limit(R) - (SPD)15_31 + 1. .. (R+CC-l) - (SPD)t 15-31 + CC(SPD)15_ 31+CC -SPD 15_ 3/(SPD)33_47-CC -SPD 33_ 47(SPD) 49-63 +CC - SPD 49-63Condition code settings:0002 3 4 Result of PSM0 0 00 00 00 0 0Space count> o.Space count = O.Word count + CC > 2 15 _1,TW = 1.Space count < CC, TS = 1.InstructioncompletedIf the instruction operation extends into a memory pageprotected either by the access protection codes or writelocks, the memory protection trap can occur. If the operationextends into a memory region"that is physically notpresent, the nonexistent memory address trap can occur.If the address of the elements within the stack (pointed toby the top-of-stack address) is in the range 0 through -15,then the registers indi cated by the R field of the PSM instructionare stored in the general registers rather than inmain memory. In this case the results wi II be unpredictable ifany source registers are also used as destination registers.PLMPULL MULTIPLE(Doubleword index alignment)PULL MULTIPLE loads a sequential set of general registersfrom the push-down stack defined by the stack pointerdoubleword located at the effective doubleword address ofPLM. The condition code must contain a count of the numberof words to be pulled from the stack. (An initiaJ valueof 0000 for the condition code specifies that 16 words areto be pulled from the stack.) The registers are treated as acircular set (with register 0 following register 15), the firstregister to be loaded from the stack is register R+CC-1, andthe contents of the current top-of-stack location becomesthe contents of this register. The last register to be loadedis register R.If there is a sufficient number of words in the stack to loadall of the specified registers, PLM operates as toiiows:1. Registers R+CC-1 to register R are loaded in descendingsequence, beginning with the contents of the locationpointed to by the current top-of-stack address(SPD15-31)t and ending with the contents of the locationpointed to by the current top-of-stack addressminus CC-1.o 0Space count < CC, worqcount = 0, TS = 1.2. The current top-of-stack address is decremented by thevalue of CC, to point to the new" top-of-stack location.0 0Space count < CC, wordcount + CC > 215_1TS = 1, and TW = 1.Instructi onaborted3. The space count (SPD33-47) is incremented by thevalue of CC and the word count is decremented by thevalue of CC.0 000Space count = 0, TS = 1.Space count = 0, wordcount = 0, TS = 1.Space count = 0, wordcount + CC > 215_1,TS = 1, and TW = 1.tFor real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it is a17-bit field (15-31).4. The condition code is set to reflect the new status ofthe word count.Affected: (SPD), (R+CC-l)to (R), CC((SPDh5_31t-R +CC -1, ... ,((SPD)15-31 -Icc - 11) - Rt(SPD)15-31 - CC- SPD 15-31 t(SPD)33-47 + CC - SPD33-47(SPD)49-63 - CC - SPD49-63Trap: Push-down stack limitpush-Down Instructions (Non-Privileged) 99

Condition code settings:2 30 0 00 0 00 00 0000 0oo4 Result of PLM0 Word count> 0Word count = 00 Word count < CC,TVV = 1Word count = 0,TVV = 10 Space count = 0,word count < CC,f\N = 10Space count = 0,word count = 0,TW = 115Space count + CC > 2 -1,TS = 115o Space count + CC > 2 -1,word count < CC, TS = 1,and TW = 115Space count + CC > 2 -1,word count = 0, TS = 1,and TW = 11 InstructioncompletedInstru cti onabortedBit positions 16 through 31 of register R are treated as asigned integer, with negative integers in two's complementform (i. e., a fixed-point halfword). The modifier is algebraica Ily added to the top-of-stack address, subtractedfrom the space count, and added to the word count in thestack pointer doubleword. If, as a resu It of MSP, eitherthe space count or the word count would be decreased below0 or increased above 215_1, the instruction is aborted.Then, the basic processor either traps to location X'42' orsets the condition code to reflect the reason for aborting,depending on the stack limit trap inhibits.If the modification of the stack pointer doubleword can besuccessfully performed, MSP operates as follows:1. The modifier in register R is algebraically added to thecurrent top-of-stack address (SPD15-31)t, to point toa new top-of-stack location. (If the modifier is negative,it is extended to 17 bits by appending a highorder1.)2. The modifier is algebraically subtracted from the currentspace count (SPD33-47) and the result becomesthe new space count.3. The modifier is algebraically added to the currentword count (SPD49-63) and the result becomes the newword count.4. The condition code is set to reflect the new status ofthe new space count and new word count.Affected: (SPD), CCTrap: Push-down stack limitIf the instruction operation extends into a memory pageprotected either by the access protection codes or writelocks, the memory protection trap can occur. If theoperation extends into a memory region that is physicallynot present, the nonexistent memory address trap canoccur.If the address of the elements within the stack (pointed toby the top-of-stack address) is in the range 0 through 15,then the words to be !o(Jded ore taken from the genera!registers rather than from main memory. In this case, theresults wi II be unpredictable if any of the source registersare also used as destination registers.(SPD)15_31 + (R)16-31SE -SPD 15-31 t(SPD)33_47 - (R)16-31 - SPD 33_ 47(SPD)49_63 + (R)16_31- SPD 49-63Condition code settings:2 3 4 Resu!t of MSPo 0 0 0 Space count> 0,word count > O.MSPMODIFY STACK POINTER(Doubleword index alignment)MODIFY STACK POINTER modifies the stack pointerdcub!e\\'ord, !oceted at the effective doublewoid addiessof MSP by the contents of register R. Register R must havethe following format:000 Space count> 0,word count = O.o 0 0 Space count = 0,word count> O.ooSpace count = 0,word count = 0,,.,.. 1"\mOalTler = v.Instruction completedtFor real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it is a17-bit fi e Id (15-31).100 Push-Down Instructions (Non-Privileged)

If CC1, or CC3, or both CC1 and CC3 are lis after!,!xecution of MSP, the instruction was aborted but the pushdownstack limit trap was inhibited by the trap-on-spaceinhibit (SPD32), by the trap-on-word inhibit (SPD48), orboth. The condition code is set to reflect the reason foraborting as follows:2 3 4 Status of space and word counts- 0 Word count> O.Word count = O.- 0 - 0 ~ word count + modifier ~ 2 15 _1.- Word count + modifier < 0, and TW = 1 orword count + modifier> 215 _1, and TW = 1.- ·0 Space count> O.Space count = O.o - 0 ~ space count - modifier < 2 15 _1.- Space count - modifier < 0, and TS = 1 orspace count - modi fi er > 215-1, and TS = 1.PUSH-DOWN INSTRUCTIONS (PRIVILEGED)The computer has two privi leged push-down instructions:PUSH STATUS (PSS) and PULL STATUS (PLS). These two instructionsand a Status Stack Pointer Doubleword faci litatethe storing (pushing) or loading (pulling) of a particularenvironment (contents of 16 general registers end ProgramStatus Words) into or out of a memory stack.STATUS STACK POINTER DOUBLEWORDThe Status Stack Pointer Doubleword (SSPD) always residesin real memory locations 0 and 1 and is dedicated for PSSand PLS instructions. The format of parameters containedwithin the Status Stack Pointer Doubleword are as follows:programming considerations, the initial TSA is a specificvalue either as the result of a Mode 0, WRITE DIRECTinstruction or as the result of a PSS or PLS instruction, asdescribed below.During each PSS instruction, the memory stack is accessed28 times and the TSA is incremented by 1 before each access.The first memory stack location accessed has a relative addressequal to the initial TSA plus 1, ... , and the 28th memorystack location accessed has a relative address equal tothe initial TSA plus 28.. Although 28 memory stack locationsare accessed in an ascending sequence, on Iy 20 locations(as selected by the hardware) wi II contain the basicprocessor environment. Eight locations (whose contents aredesignated as "indeterminate", in Figure 12) are reservedand must not be used.For each PLS instruction, access to the memory stack iscontingent upon the Word Count as described subsequently.If access is permitted, the memory stack is accessed 28 timesand the TSA is decremented by 1 after each access. Thefirst memory stack location accessed by a PLS instructionhas a relative address equal to the initial TSA, the secondmemory stack location accessed has a relative address equalto the initial TSA minus 1, ... , and the 28th memory stacklocation accessed has a relative address equal to the initialTSA minus 27. Although 28 memory stack locations areaccessed in a descending sequence, the hardware selectsand pulls the contents of only 20 locations containing validinformation, as shown in Figure 12, and loaded into thegeneral registers and PSWs ... The contents of eight locationsdesignated as indeterminate are ignored.If the terminal (last) TSA for a PSS or PLS instruction isnot modified by a Mode 0 WRITE DIRECT instruction, itmay be used as the initial TSA for a subsequent PSS or PLSinstruction. Each PSS instruction causes the memory stackto be increased by 28 word locations and each PLS instructioncauses the memory stack to be decreased by 28 wordlocations. The information is pushed and pulled on a last-in,first-out basis.Note: The PLS instruction is contingent upon the WordCount value, as described below.Real Memory Location 0:SPACE COUNTReal Memory Location 1:TOP OF STACK ADDRESSThe Top of Stack Address (TSA) is always a 20-bit real memoryword address and is never mapped. Depending uponThe Space Count field (bit positions 33-47) of the StatusStack Pointer Doubleword is a 15-bit counter that may containa value of 0 through 32,767. Depending upon programmingconsiderations, the initial Space Count is aspecific value either as the result of executing a Mode 0,WRITE DIRECT instruction or a PLS or PSS instruction.During a PSS instruction, the Space Count is decrementedby 1 for each word pushed into the memory stack. If theSpace Count is decremented to a value of zero before a"the words have been pushed, the PSS instruction continues(i. e., no trapping occurs). The environment is stored intoPush-Down Instructions (Privileged) 101

PSS OperationsPLS Operationsinitial TSA - - terminal TSA = initial TSA-28+1 (RO) -27+2 (R 1) -26+3 (R2) -25+4 (R3) -24+5 (R4) -23+6 (R5) -22+7 (R6) -21+8 (R7) -20+9 (R8) -19+10 (R9) -18+11 (R10) -17+12 (Rl1 ) -16+13 (R12) -15+14 (R13) -14+15 (R14) -13+16 (R15) -12+17 -11+18 -10+19 -9+20 -8+21 -7+22 -6+23 -5+24 -4+25 (PSWl) -3+26 (PSW2) -2+27 (PSW3) t -1initial TSA +28 (PSW4) - initial TSAtAs a function of the hardware, the contents of these 8 locations are indeterminateafter a PSS instruction and ignored by a PLS instruction. Theselocations are reserved for future enhancements and must not be used.Figure 12.Typical 28-Word Portion of Memory Stack for PSS and PLS102 Push-90wn Instructions (Privileged)

appropriate memory stack locations as specified by theTSAi however, subsequent values of the Space Count areindeterminate.PSSPUSH STATUS(Doubleword index alignment, privi leged)During a PLS instruction, the Space Count is incrementedby 1 for each word pulled from the memory stack. If theSpace Count is incremented beyond a value of 32,767, bitposition 32 is set to 1 (signifying an overflow condition);however, the PLS instruction continues (i. e., no trappingoccurs).!xlaDNote: Once bit position 32 has been set to a 1, it can bereset to a 0 only by executing a Mode 0, WRITEDIRECT instruction. That is, bit position 32 cannot be reset to a 0 by the decrementing process performedduring a PSS instruction.WORD COUNTThe Word Count field (bit positions 49-63) of the StatusStack Pointer Doubleword is a lS-bit counter that may containa value of 0 through 32,767. Depending upon programmingconsiderations, the initial Word Count is aspecific value either as the result of executing a Mode 0,WRITE DIRECT instruction or as the result of executing aPSS or PLS instruction.During a PSS instruction, the Word Count is incrementedLy 1 [V 1- ~uch yvvi"d pu~hcd il.tv th~ iii\:i;;Gr'j ~t~~k. Th~~,the terminal Word Count for a PSS instruction exceeds theinitial Word Count by 28. If the Word Count valueexceeds 32,767, bit position 48 is set to a 1 (signifyingthat an overflow condition has occurred); however, thePSS instruction continues the stacking operation (i. e., notrapping occurs).If the initial Word Count for a PLS instruction is equal toor greater than 28, the Word Count is decremented by 1 foreach word pulled from the memory stack and the terminalWord Count will be 28 less than the initial Word Count.Note that if bit position 48 was set to a 1 by a PSS instructionpreviously, it can not be reset to a 0 by the decrementingperformed during a PLS instruction.PUSH STATUS loads new Program Status Words from an effectivedoubleword location and stores the current environment(current Program Status Words and contents of all16 general registers) into a memory stack, as defined by theStatus Stack Pointer Doubleword. Note that the referen~eaddress points to the memory location of the new PSWs.The PSS instruction is used for three types of operations:as a normal instruction in an ongoing program; as an interruptinstruction; and as a trap instruction. The effectiveaddress of a PSS instruction is generated in one of thefollowing ways:PSS - normal instruction (see first instruction diagram)When a PSS instruction is encountered in the course ofexecution of normal programs, the effective address isgenerated according to the rules for addressing then ineffect as described by the currently active PSWs; that is, thebasic processor is operating in real, real extended, or virtualaddressing mode. The flags in bit positions 9 and 10 haveno effect and must be coded as zeros.PSS - interrupt instruction (see second instruction diagram)A PSS instruction (in an interrupt location) executed as aresult of an interrupt is called an interrupt instruction. Inthe interrupt execution sequence, the 20-bit referenceaddress is always real, independent of the map invokingbit in the PSWs. There is no indexing possible since thedesi gnator fi e ld is preempted by the reference address.Indirect addressing is permitted with precisely the sameconstraints. The indirect address word contains a 20-bitreal address with the same properties as the reference addressdescribed above. The flags in bit positions 9 and 10have no effect and must be coded as zeros.If the initial Word Count for a PLS instruction is equal tozero, the parameters within the Status Stack Pointer Doublewordare neither effective nor affected by the PLS instruction.However, default PSWs are loaded from real memorylocations 2 and 3.If the initial Word Count for a PLS instruction is less than 28and not equal to zero, the other parameters of the StatusStack Pointer Doubleword are not effective and none of theparameters are affected by the PLS instruction. Instead theBP traps to location X'4D ' (instruction exception trap) andTCC2 is set.PSS - trap instruction (see second instruction diagram)A PSS instruction (in a trap location) executed as a resu Itof a trap entry operation is called a trap instruction. In atrap execution sequence, the 20-bit reference address may beeither a real address or a virtual address according to themap invoking bit in the PSWs. There is no indexing possiblesince the index field is used for addressing. If indirectaddressing is specified, the effective address is generatedaccording to the rules for addressing then in effect as describedby the currently active PSWs. Bit positions 9 and 10must be coded as zeros.Push-Down Instructions (Privileged) 103

Depending upon the type of addressing, the referenceaddress of the PSS instruction is converted into an effectivevirtual doubleword address, as described under "PSS AddressCalculations", in Chapter 2. Except for the Register BlockPointer field (bit positions 56-59) and the interrupt groupinhibit bits (bit positions 37, 38, and 39), the contents ofthe effective location are always loaded as the new PSWs.If the lP flag (bit 8 of the PSS instruction) is a 1, theRegister Block Pointer of the new PSWs is also loaded. Ifthe lP flag is a 0, the old Register Block Pointerisretained.The interrupt group inhibit bits of the new PSWs are 1I0Red llwith the corresponding bits of the old PSWs.The current environment (comprised of 20 words) is storedin memory stack locations having the following relativeaddresses: initial TSA+1 through initial TSA+16, initialTSA+25, and initial TSA+26. Memory stack locationshaving ref-ative addresses of initial TSA+17 through initialTSA+24, initial TSA+27, and initial TSA+28 are reservedand the contents are indeterminate.Memory Stack:(General Register n) - (initial TSA+(n+l) where n hasascending values from 0 through 15.PSW1 -PSW2 -(initial TSA+25)(initial TSA+26)Status Stack Pointer Doubleword:TSA+1 - TSA unti I terminal TSA=initial TSA+28iWord Count + 1 - Word Count unti I terminal WordCount = initial Word Count + 28, (if Word Count>32,767, set bit 48 to 1);Space Count - 1 - Space Count unti I terminal SpaceCount = initial Space Count - 28 (if Space Count = 0,Space Count - 1 is indeterminate).The parameters of the Status Stack Pointer Doubleword (ascontained within working registers) are appropriately modifiedto reflect the progress of the PSS instruction andconditions of the memory stack (i. e., the TSA and WordCount are incremented and the Space Count is decrementedfor each memory word location accessed, as described underStatus Stack Pointer Doubleword).If the Word Count exceeds 32,767 (maximum count forbits 49-63) or if the Space Count is reduced to zero beforethe PSS instruction is completed, the stacking operationscontinue unti I 28 words have been pushed (i. e., no trappingoccurs). When the Word Count exceeds 32,767, bit 48 isset to a 1. Attempting to decrement the Space Count belowzero causes the Space Count to become indeterminate.Affected: (PSWs), CC, Memory Stack, Status Stack PointerDoubleword.(PSWs) and CC:EDO_3-CC;ED4-7- FR, FS, FZ, FN;ED8-MS;ED9-MM;ED10-DMiED11-AMiED15-31 -IAiED32-35-WK;ED37-39 u CI, II, EI - CI, II, EI(Note: "u ll represents inclusive OR. )ED 56 - 59 - RP on Iy if (I8) = 1ED60- RAED61-MAPLSPULL STATUS (nonaddressing, privileged)PULL STATUS, in conjunction with the Status Stack PointerDoubleword, may cause one or more of the following functionsto be performed:1. Selectively load a new environment (PSWs and 16 generalregisters) from the memory stack; or,2. Selectively load default PSWs from dedicated memorylocations; and,3. Selectively clear and arm or clear and disarm thehighest priority level currently in the active state.If the initial Word Count of Status Stack Pointer Doublewordis equal to or greater than 28, a new environment isloaded from the memory stack. Twenty eight memory stacklocations are accessed in a descending sequence, startingat a location having an address equal to the initial TSA(part of the Status Stack Pointer Doubleword).The hardwareselects and loads the contents of 20 memory locationsinto the general registers and as the PSWs (i. e., the contentsof locations having relative addresses of initial TSA-2,initial TSA-3, and initial TSA-12 through initial TSA-27).The contents of 10 memory stack locations (having relativeaddresses equal to initial TSA, initial TSA-l, and initialTSA-4 through initial TSA-11) are ignored.Portions of the new PSWs are dependent upon the LP flagII-Ln\ r~t nlr- I.- 11.1...\011 OJ or me fL.) JnsrruclJon as well as me mTerrupT groupinhibit bits of the old PSWs and the PSWs as pulled fromthe memory stack. If the LP flag is a 1, a new RegisterBlock Pointer (as pulled from the memory stack) is loadedas part of the new PSWs. If the LP flag is a 0, the old RegisterBlock Pointer is retained as the Register Block Pointerfor the new PSWs. The new interrupt group inhibit bits (CI,104 Push-Down Instructions (Privileged)

II, EI) are generated by II ORing" the old CI, II, EI bitswith the contents of bits 37, 38, and 39 of the PSWs aspu II ed from the memory stack.The clearing and arming or disarming the highest priorityinterrupt level currently active is dependent upon thecoding of the CL and AD flags (bit positions 10 and 11,respectively) of the PLS instruction. If the CL flag is a 0 7the interrupt level is not affected. If the CL flag fs-a 1and the AD flag is a Or the interrupt level is set to the disarmedstate. If the CL flag is a 1 and the AD flag is a 1rthe interrupt level is set to the armed state. Note that -ifthe interrupt level is to be modifie~ (CL flag is set to a 1),the instruction maybe delayed unti I the interrupt system isavai lable. -Summary description of CL and AD flags and effect on in-terrupt level and PDF flag follows:armed state. Note that if the interrupt_level is to bemodified (i. e., the CL flag is a 1), the instruction may bedelayed unti I the interrupt system is avai lab Ie.A summary description of the action on the interrupt leveias a function of the C1 and AD .flag is as follows:Bit Positions10 (CL)oo11 (AD)ooFunctionNo effect upon interrupt levelor PDF flagReset PDF flagClear and disarm interrupt levelClear and arm interrupt levelBit Positions10 (CL)oo11 (AD)ooFunctionNo effect upon interrupt levelor PDF flag.Reset PDF flagClear and disClrm interrupt levelClear and arm interrupt levelIf the initial Word Count within the Status Stack PointerDoubleword is less than 28 cmd not equal to 0, the basicprocessor traps to location X'4D~ (instruction exceptiontrap) without loading-any new status or affecting the parametersof the Status Stack Pointer Doubleword and ther-CC2 bit is set to 1.Affected: If word count ~ 28,(PSWs), CC,Status Stack PointerDoublewordInterrupt System if(1)10=1.Traps: Instruction exception,if word countis less than 28 andnot 0; nonexistentinstruction ifbit 0=1.If the initial Word Count is zero r default PSWs are loaded -from real memory locations 2 and 3 and the other parametersof the Status Stack Pointer Doubleword are not effectiveand no parameters are affected.Portions of the new PSWs (interrupt inhibit group bits andthe Register Block Pointer) may be selected or generated inthe following manner:If the LP flag (bit 8) of the PSL instruction is a 1r the newRegister Block Pointer wi II be as obtained from the defaultPSWs. If the LP flag is a 0, the Register Block Pointer ofthe old PSWs is retained as the Register Block Pointer forthe new PSWs.The CI, II, and EI bits of the old PSWs are "ORed II withthe contents of bit positions 37, 38 r and 39 of the defaultPSWs to generate the CI, II, and EI bits of the new PSWs.Depending upon the coding of the CL and AD flags (bitpositions 10 and 11, respectively) of the PLS instruction,the highest priority interrupt level currently in the activestate may be modified. If the CL flag is a 0, the interruptlevel is not affected. If the CL flag is a 1 and the AD flagis a 0, the interrupt level is cleared and placed into thedisarmed state. If the CL flag is a 1 and the AD flag isa 1, the interrupt level is cleared and placed into the(PSWs) and CCIf word count = 0, (PSWs), ec, and InferruptSystem, if 1(10)=1.ED O_ 3-CC;ED 5-7 -ED 8-MS;-ED 9-MM;ED lO-DM;ED 11-AM;ED 15- 31-FS, FZ, FN;IA;ED 32_ 35-WKED37-39 u CI, II,-EI -CI, II, EI(Note: "u" represents inclusive OR. )[D 56- 59- RP only if (1)8= 1ED 60-RAED 61-MApush-Down Instructions (Privi leged) 105

Note; If the word count ~ 28, the effective doubleword(ED) is pulled from memory stack locations (relativeaddresses initial TSA-24 and initial TSA+l).If the word count=O, the ED is pulled from realmemory locations 2 and 3.Status Stack Pointer Doubleword; (Only if initial WordCount ~ 28)TSA-1 --TSA until terminal TSA = initial TSA-28;Word Count - 1 --Word Count unti I terminal WordCount = initial Word Count - 28 (if initial Word Count> 32,767, bit 48 not affected); and,Space Count + 1 - Space Count untir terminal SpaceCount = initial Space Count + 28 (if Space Count> 32,767, then set bit 32 to 1).Interrupt System;. If (1)10 = 1 and (1)11 = 1, clear and arm interruptlevel.If (1)10 = 1 and (1)11 = 0, clear and disarm interruptlevel.EXECUTE/BRANCHINSTRUCT~NSThe following instructions can cause the basic processor toexecute instructions in an order other than that of sequentiallyascending instruction addresses:NONALLOWED OPERATION TRAP DURING EXECUTIONOF BRANCH -INSTRUCTIONThe next instruction after a branch instruction may residein two possible places: the location following the branchinstruction or a location designated by the branch instruction.Either of these two locations may be in a protectedmemory region or in a region that is physically nonexist~nt.The executio-n of th~ branch does not cause a trap un lessthe instruction that is actually to follow the branch instructionis in a protected or nonexistent memory region. Trapsdo not occur because of any anticipation on the part of thehardware.A nonallowed operation trap condition during execution ofa branch instruction wi II occur for the following reasons;1. The branch instruction -is indirectly addressed~ and thebranch conditions are satisfied, but the address of thelocation containing the direct address is either nonexistentor unavai lable for read access fo the programin the slave mode.2. The branch instruction is unconditional (or the branchis conditional and the condition for the branch is satisfied),but the effective address of the branch instructionis either nonexistent or unavailable for instructionor read access to the program (in slave -or masterprotectedmode).If either of the above situations occurs, the basic processoraborts execution of the branch instruction and executes anonallowed operation trap.Instruction NameExecuteBranch on Conditions SetBranch on Conditions ResetBranch on Incrementing RegisterBranch on Decrementing RegisterBranch and LinkMnemonicEXUBCSBCRBIRBDRBALPrior to the time that an instruction is accessed from memoryfor execution, bit positions 15-31 of the program statuswords contain the virtual address of the instruction~ referredto as the instruction address. At this time, the basic processortraps to location X'40' if the actual address of theinstruction is nonexistent or instruction-access protected.If the instruction address is existent and is not instructionaccessprotected, the instruction is accessed and the instructionaddress portion of the program status words isincremented by 1, so that it now contains the virtual addressof the next instruction in sequence {referred to as th~ updatedinstruction address}.The EXECUTE instruction can be used to insert another instructioninto the program sequence, and the branch instructionscan be used to alter the program sequence, eitherunconditionally or conditionally. If a branch is unconditiona!(or conditional and the branch condHion is satisfied),the instruction pointed to by the effective address of thebranch instruction is normally the next instruction to beexecuted. If a branch is conditional and the conditionfor the branch is not satisfied, the next instruction is normallytaken from the next location, in ascending sequence,after the branch instruction.If a trap condition occurs during the execulion sequence ofany instruction, the basic proces~r decrements the updatedinstruction address by 1 and then traps to the location assignedto the trap condition. If neither a trap conditionnor a satisfied branch condition occurs during the executionof an instruction, the next instruction is accessed from thelocation pointed to by the updated instruction address. Ifa satisfied branch condition occurs during the execution ofa branch instruction (and no trap condition occurs), thenext instruction is accessed from the location pointed to bythe effective address of the branch instruction.106 Execute/Branch Instructions

In the real extended addressing mode, a 20-bit address maybe used as a branch address via indexing or indirect addressing.If such a branch address, (A), is beyond the first128Kofreal memory, the instruction at (A) will be executed,but the next instruction address will be (A+1) in the original128K block unless (A) contains a branch instruction. Notethat with this exception all instructions executed in thereal extended addressing mode must lie in the first 128K ofrea I memory.EXUEXECUTE(word index alignment)BCSBRANCH ON CONDITIONS SET(Word index alignment)BRANCH ON CONDITIONS SET forms the logical product(AND) of the R field of the instruction word and the currentcondition code. If the logical product is nonzero, thebranch condition is satisfied and instruction execution proceedswith the instruction pointed to by the effective addressof the BCS instruction. However, if the logical productis zero, the branch condition is unsatisfi ed and instructionexecution then proceeds with the next instruction innormal sequence.EXECUTE causes the basic processor to access the instructionin the location pointed to by the effective address of EXUand execute the subject instruction. The execution of thesubject instruction, including the processing of trap andinterrupt conditions, is performed exactly as if the subjectinstruction were initially accessed instead of the EXU instruction.If the subject instruction is another EXU, thebasic processor executes the subject instruction pointed toby the effective address of the second EXU as describedabove. Such "chains" of EXECUTE instructions may be ofany length, and are processed (without affecting the updatedinstruction address) until an instruction other than EXU isencountered. After the final subject instruction is executed,inc:for"rtit"ln ..._.. __.. _-- Pypr"tit"ln ----------- nrt"lrpp,.lc;. r------_· with thp. np.xt instruction insequence after the initial EXU (unless the subject instructionis an LPSD or XPSD instruction, or is a branch instructionand the branch condition is satisfied).If an interrupt activation occurs between the beginning ofan EXU instruction (or chain of EXU instructions) and thelast interruptible point in the subject instruction, the BPprocesses the interrupt-servicing routine for the activeinterrupt level and then returns program control to the EXUinstruction (or the initial instruction of a chain of EXUinstructions), which is started anew. Note that a programis interruptible after every instruction access, including accessesmade with the EXU instruction, and the interruptibilityof the subject instruction is the same as the normalinterruptibility for that instruction.If a trap condition occurs between the beginning of an EXUinstruction (or chain of EXU instructions) and the completionof the subject instruction, the basic processor traps tothe appropriate trap location. The instruction address storedby the XPSD instruction in the trap location is the addressof the EXU instruction (or the initial instruction of a chainof EXU instructions).Affected: (lA) if CC n R f 0If CC n (1)8_11/0, EVA 15 - 31 -IAIf CC n (1)8-11 = 0, IA not affectedIf the R field of BCS is 0, the next instruction to be executedafter BCS is always the next instruction in ascendingsequence, thus effectively producing a "no operation IIinstruction.BCRBRANCH ON CONDITIONS RESET(Word index alignment)BRANCH ON CONDITIONS RESET forms the logical product(AND) of the R field of the instruction word and thecurrent condition code. If the logical product is zero, thebranch condition is satisfied and instruction execution thenproceeds with the instruction pointed to by the effectiveaddress of the BCR instruction. However, if the logicalproduct is nonzero, the branch condition is unsatisfied andinstruction execution then proceeds with the next instructionin normal sequence.Affected: (IA) if CC n R = 0If CC n (1)8-11 = 0, EVA 15_ 13-If CC n (1)8-11 10, IA not affectedIAAffected: Determined bysubject instructionT raps: Determined bysubject instructionCondition code settings: Determined by subject instruction.If the R field of BCR is 0, the next instruction to be executedafter BCR is always the instruction located at theeffective address of BCR, thus effectively producing a"branch unconditionally" instruction.Execute/Branch Instructions 107

BIRBRANCH ON INCREMENTING REGISTER(Word index alignment)BRANCH ON INCREMENTING REGISTER computes theeffective virtual address and then increments the contentsof general register R by 1. If the result is a negative value,the branch condition is satisfied and instruction executionthen proceeds with the instruction pointed to by the effectiveaddress of the BIR instruction. However, if the resultis zero or a positive va lue, the branch condition is not satisfiedand instruction execution proceeds with the next instructionin normal sequence.If the effective address of BDR is unavailable to the program(slave or master-protected mode) for instruction access andthe branch condition is satisfied, or if the effective addressof BDR is nonexistent, the basi c processor aborts executionof the BDR instruction and traps to location X'40'. In thiscase, the instruction address stored by the XPSD instructionin location X'40' is the virtual address of the aborted BDRinstruction. If the basi c processor traps because of instructionaccess protection, register Rwill contain the value thatexisted just before the BDR instruction. If a memory parityerror occurs due to the accessing of the instruction to whi chthe program is branching, the basic processor aborts executionof the BDR and traps to location X'4C r with register Runchanged.Affected: (R),(IA)(R) + 1 - RIf (R)O = 1, EVA 15_ 31-IAIf (R)O = 0, IA not affectedBALBRANCH AND LINK(Word index alignment)If the branch condition is satisfied and if the effective addressof BIR is either unavailable to the program (slave ormaster-protected mode) for instruction access or is nonexistent,the basi c processor aborts execution of the BIRinstruction and traps to location X'40'. In this case, theinstruction address stored by the XPSD instruction in locationX'40' is the virtual address of the aborted BIR instruction.If the basic processor traps because of instructionaccess protection, register R will contain the value thatexisted just before the BIR execution (i.e., updated instructionaddress). If a memory parity error occurs due to theaccessing of the instruction to which the program is branching,the basic processor aborts execution of the BIR andtraps to location X'4C' with register R unchanged.BDRBRANCH ON DECREMENTING REGISTER(Word index alignment)BRANCH AND LINK determines the effective virtual address,loads the updated instruction address (the virtual addressof the next instruction in normal sequence after theBAL instruction) into bit positions 15-31 of general registerR, clears bit positions 0-14 of register R to O's and thenreplaces the updated instruction address with the effectivevirtual address. Instruction execution proceeds with theinstruction pointed to by the effective address of the BALinstruction.The BAL instruction in real extended addressing will storethe full address of the next instruction in the specified Rregister. Positions 0-9 of the specified register will be setequal to zero.Affected: (R), (IA)BRANCH ON DECREMENTING REGISTER computes theeffective virtual address and then decrements the contentsof general register R by 1. If the result is a positive value,the branch condition is satisfied and instruction executionthen proceeds with the instruction pointed to by the effectiveaddress of the BDR instruction. However, if the resultis zero or a negative value, the branch condition is unsatisfiedand instruction execution proceeds with the next instructionin normal sequence.Affected: (R), (IA)(R) - 1 -RIf (R)O = 0 and (R)1-31 j 0, EVA 15 _ 31 -If (R)O = 1 and (R) = 0, IA not affectedIAIf the effective address of BAL is unavailable to the program(slave or master-protected mode) for instruction access andthe branch condition is satisfied, or if the effective addressof BAL is nonexistent, the basic processor aborts executionofthe BAL instruction and traps to location X'40' (nonallowedoperation trap). In this case, the instruction address storedby the XPSD instruction in location X'40' is the virtual addressof the aborted SAL instruction. If the basic processortraps because of instruction access protection, register R willcontain the updated instruction address. If a memory parityerror occurs due to the accessing of the instruction to whichthe program is branching, the basic processor aborts executionof the BA L and traps to location X'4C r with register Rchanged to the updated instruction address.108 Execute/Branch Instructions

CAll INSTRUCTIONSEach ofthe four CA LL instructions causes the basi c processorto trap to a specifi c location for the next instruction in sequence.The four CALL instructions, their mnemonics, andthe locations to wh i ch the basi c processor traps are:Instru ct ionTrapName Mnemonic LocationCALL 1 CAll X'48'CALL 2 CAL2 X'49'CALL 3 CAL3 X'4A'CALL 4 CAL4 X'4B'Each ofthese four trap locations must contain an EXCHANGEPROG RAM STATUS WORDS (XPSD) instruction. Executionof XPSD in the trap location for a CALL instruction is describedunder "Control Instructions, XPSD Exchange ProgramStatus Words". If the XPSD instruction is coded withbit position 9 set to 1, the next instruction (executed afterthe XPSD) is taken from one of 16 possible locations, asdesignated by the value in the R field of the CALL instruction.Each of the 16 locations may contqin an instructionthat causes the basic processor to branch to a specificroutine; thus, the four CALL instructions can be used toenter any of as many as 64 unique routines.The effective address of either a direct or indirect CALLinstruction is not used for a memory reference and, therefore,cannot cause a trap.CALI CALL 1(Word index alignment)CAL4 CALL 4(Word index al ignment)~CALL 4 causes the basic processor to trap to location X'4B'.CONTROL INSTRUCTIONSThe following privileged instructions are used to control thebasi c operating conditions-of the basic processor:Instruction NameLoad Program Status WordsExchange Program Status WordsLoad Register PointerMove to Memory Contro ILoad Real AddressLoad Memory StatusWaitRead DirectWrite DirectMnemonicLPSDXPSDLRPMMCLRALMSWAITRDWDIf execution of any control instruction is attempted whilethe basic processor is in the slave mode (i. e., while bit 8of the current program status words is a 1), the basi c processorunconditionally traps to location X'40' prior toexecuting the instruction.PROGRAM STATUS WORDSProgram status words have the following structure whenstored in memory:CALL 1 causes the basi c processor to trap to location X'48'.CAL2 CALL 2(Word index alignment)CA LL 2 causes the basi c processor to trap to location X '49'.BitPositionDesignationFunctionCAL3 CALL 3(Word index al ignment)0-34CCFRCondition codeFloating round5FSFloating significance mask6FZFloating zero maskCA LL 3 causes the basi c processor to trap to location X '4A '.7FNFloating normal ize maskCall Instructions/Control Instructions 109

BitPosition Designation. Function8 MS Master/slave mode control9 MM Memory map mode control10 DM Decimal arithmetic trapmask11 AM Fixed-point arithmeticoverflow trap mask15-31 IA Instruction address32-35 WK Write key37 CI Counter interrupt groupinhibit38 II I/O interrupt group inhibit39 EI External interrupt inhibit56-59 RP Reg i ster po inter60 RA Register altered61 MA Mode alteredThe detailed functions of the various portions of the programstatus words are described in Chapter 2, "Program StatusWords".of lPSD is a 1, or is disarmed if bit 11 of LPSD is a O.If bit 10 of lPSD is a 0, no interrupt level is affectedin any way, regardless of whether b-it 11 of LPSD is 1or O. If bit 10 of the lPSD is a 0 and bit 11 of lPSDis 1, the PDF flag is cleared. (Interrupt levels are describedin detai I in Chapter 2, "Interrupt System". )Bit position10 (CL) 11 (AD) FunctionooClear and disarm interrupt level.Clear and arm interrupt level.Clear PDF flag.o o No control action.3. The PDF flag is normally reset by the last instructionof a trap routine, which is an LPSD instruction havingbit 10 equal to 0 and bit 11 equal to 1.These portions of the effective doubleword that correspondto undefined fields in the program status words are ignored.Affected: (PSWs), interrupt system if (1)10 = 1ED O_ 3- CC; ED 5_ 7- FS,FX,FN;LPSDLOAD PROGRAM STATUS WORDS(Doubleword index alignment, privileged)ED -MS' ED - MM·8 '9 'ED 15_ 31- IA; ED 32_ 35- WK;LOAD PROGRAM STATUS WORDS replaces bits o through 39,60 and 61 of the current program status words with bits 0through 39, 60 and 61 of the effective doubleword.Control bits used in the LPSD instruction are:BitPosition Designation Control Function8 LP Load pointer control10 Cl Clearing of interrupt level11 AD Armed/disarmed stateThe following conditional operations are performed:1. If bit position 8 (LP) of LPSD conta ins a 1, bits 56through 59 (register pointer) of the current programstatus words are replaced by bits 56 through 59 of theeffedive doublewOid; if bit 8 of LPSD is u 0, tht=: cu,-rent register pointer value remains unchanged.2. If bit position 10(CL}of LPSD contains a 1, the highestpriority interrupt level currently in the active state iscleared (i. e., reset to either the armed state or the disarmedstate); the interrupt level. is armed if bit 11 (AD)ED 37_ 39- CI, II, EI; if (1)8 = 1, ED 56_ 59- RPED60 - RA; ED61 - MAu: In = 1 ~ ... ,J In"\"10 · ....·1\··\·'11 = . 1 , C!CCi and aim iiitciruptIf (1)10 = 1 and (1)11 = 0, clear and disarm interruptXPSDEXCHANGE PROGRAM STATUS WORDS(Doubleword index alignment, privileged)EXCHANGE PROGRAM STATUS WORDS stores the currentlyactive PSWs in the doubleword location addressed bythe effective address of the XPSD instruction. The followingdoubleword is then accessed from memory and loadedinto the active PSWs registers.110 Control Instructions

The XPSD instruction' is used for three distinct types ofoperations: as a norma I instruction in an ongoing program;as an interrupt instruction; and as a trap instruction.Control bits used in the XPSD instructions are:XPSD (trap instruction)An XPSD instruction (in a trap location) executed as a resultof a trap entry operation is called a trap instruction. Addressingis the same as for the interrupt XPSD (see above).BitPosition8DesignationLPControlFunctionLoad pointercontrolWhere usedAll XPSDsThe fol lowing additional operations are performed on thenew program status words if, and only if I the XPSD is beingexecuted as the result of a nonallowed operation (trap tolocation X'40') or a CALL instruction (trap to location X'48',X'49', X'4A', or X'4B'):910AIATAddress IncrementAddress i ng typeTrap XPSDA I I X PS Ds1. Nonal lowed operations - the fol lowing additional functionsare performed when XPSD is being executed as aresult of a trap to location X'40':The effective address of an XPSD instruction is generatedin one of the following ways:XPSD (normal instruction)When an XPSD instruction is encountered in the course ofexecution of normal programs, the AT (bit 10) of the instructiondetermines the type of addressing to be used.If AT = 0, the reference address is 20 bits (12-31). Indexingis not allowed. Indirect addressing is allowed with thesame constraints as the reference address. Addressing isalways real, independent of the current PSWs.If AT = 1, the reference address is 17 bits (15-31). Addresscalculations are according to standard addressing rules asdetermined by the current PSWs. Indexing and indirect addressingare allowed.XPSD (interrupt instruction)An XPSD instruction (in an interrupt location) executed asa result of an interrupt is called an interrupt instruction.The type of addressing to be used is determined by the basicprocessor mode and the AT (bit 10) of the instruction.In the extended addressing mode (MA = 1 and MM = 0), theAT bit is used to determine the type of addressing to beused. If AT = 0, the reference address is 20 bits {12-31}.Indexing is not allowed. Indirectaddressing is allowed withthe same constraints as the reference address. Addressing isalways real, independent of the current PSWs. If AT = 1,the reference address is 17 bits (15-31). Address calculationsare according to standard addressing rules as determinedby the current PSWs. Indexing and indirect addressingare allowed.When the addressing mode is not extended addressing, thereference address is 20 bits (l2-31). If AT = 0, indexing·is not allowed. Indirect addressing is allowed with thesame constraints as the reference address. Addressing isalways real, independent of the current PSWs. If AT = 1,the 20-bit reference address is subject to PSWs bit 9,as is the contents of the indirect address if indirect isspecified.a. Nonexistent instruction - if the reason for the trapcondition is an attempt to execute a nonexistentinstruction, bit position Oof the new program statuswords (CC 1) is set to 1. Then, if bit 9 (AI) ofXPSD is a 1, bit positions 15-31 of the new programstatus words (next instruction address) areincremented by 8.b. Nonexistent memory address - if the reason for thetrap condition is an attempt to access or write intoa nonexistent memory region, bit position 1 of thenew program status words (CC2) is set to 1. Then,if bit 9 of XPSD is a 1, the instruction address portionof the new program status words is in crementedby 4.c. Privileged instruction violation - if the reason forthe trap condition is an attempt to execute a privilegedinstruction while the basic processor is inthe slave mode, bit position 2 of the new programstatus words (CC3) is set to 1. Then, if bit positionOof XPSD is 1, the instruction address portionof the new program status words is incremented by 2.d. Memory protection violation - ifthe reason for thetrap condition is an attempt to read from or writeinto a memory region to which the program doesnot have proper access, bit position 3 of the newprogram status words (CC4) is set to 1. Then, ifbit 9 of XPSD is a 1, the instruction address portionof the new program status words is incrementedby 1.There are certain circumstances under which twoof the above nonal lowed operations can occursimultaneously. The following operation codes(including their counterparts) are considered to beboth nonexistent and privileged: X'QC' and X'OD'.If either of these operation codes is used as an instructionwhile the basi c processor is in the slaveor master-protected mode, CC 1 and CC3 are bothset to l's; if bit 9 of XPSD is a 1, the instructionaddress portion of the new program status words isincremented by 10. If an attempt is made to accessor write into a memory region that is both nonexistentand prohibited to the program by means of theControl Instructions 111

memory control feature, CC2 and CC4 are bothset to 1 IS; if bit 9 of XPSD is a 1, the instructionaddress of the new program status words is incrementedby 5.2. CALL instructions - the following additional functionsare performed when XPSD is being executed as a resultof a trap to location X'48', X'49' i X'4A', orX'4B'.a. The R field of the CA LL instruction causing thetrap is logica"y inclusively ORed into bit positions0-3 (CC) of the new PSWs.b. If bit position 9 of XPSD contains a 1, the R fieldof the CALL instruction causing the trap is addedto the instruction address portion of the new PSWs.3. Watchdog timer, parity error, or instruction exceptiontrap - the following additional functions are performedwhen XPSD is being executed a~ a result of a trap tolocation X'46', X'4C', or X'4D', respectively.a. The contents of TCC 1-4 are logically inclusivelyORed into bit positions 0-3 (CC) of the new PSWs.b. If bit position 9 of XPSD contains a 1, the contentsof TCC 1-4 are added to the instruction addressportion of the new PSWs.If bit position 9 of XPSD contains a 0, the instruction addressportion of the new PSWs always remains at the valueestablished by the second effective doubleword. Bit position9 of XPSD is effective only if the instruction is beingexecuted as the result of a nonallowed operation, CALLinstruction watchdog timer, parity error, or instruction exceptiontrap. Bit position 9 of XPSD must be coded with ao in all other cases; otherwise, the results of the XPSDinstruction are undefined.2. Bits 0-35, 60, and 61 of the current program statuswords are unconditionally replaced by bits 0-35, 60,and610f the secondeffectivedoubleword. The affectedportions of the program status words are:BitPosition Designation Function0-3 CC Condition code4-7 FR,FS,FZ, Floating controlFN8 MS Master/slave mode control9 MM Mapping mode control10 DM Decimal arithmetic trap mask11 AM Fixed-point arithmetic trap mask15-31 IA Instruction address (real or virtual)32-35 WK Write key60 RA Register altered61 MA Mode altered3. A logical inclusive OR is performed between bits 37through 39 of the current program status words andbits 37 through 390f the second effective doubleword.BitPosition Designation Function37 CI Counter interrupt inhibit38 II I/O interrupt inhibit39 EI External interrupt inhibitThe current program status words are stored in the doubl eword location pointed to by the effective address of XPSDin the following form:Program Status WordsIf any (or all) of bits 37, 38, or 39 of the second effectivedoubleword are O's, the corresponding bits inthe current program status words remain unchanged; ifany (or all) of bits 37, 38, or 39 of the second effectivedoubl eword are 1 IS, the corresponding bits in thecurrent program status words are set to 1 'so See "InterruptSystem", Chapter 2, for a detailed discussionof the interrupt inhibits.The current program status WOrds (as iI hjs~ra~ed above) arE:replaced by new program status words as described below.1. The effective address of XPSD is incremented by 2 sothat it points to the next doubleword location. Thecontents of the next doubl eword location are referredto as the second effective doubleword, or ED2.4. If bit position 8 (LP) of XPSD contains a 1, bits 58and 59 (register pointer) of the current program statuswords are replaced by bits 58 and 59 of the secondeffective doubieword; if bit 8 of XPSD is a 0, the currentregister pointer value remains unchanged.Affected: (EDL), (PSWs)If (1)10 = 1, trap or interrupt instructions only, effectiveaddress is subject to current active addressing mode.112 Control Instructions

If (I)1O = 0, trap or interrupt instructions only, effectiveaddress is independent of current active addressing mode.PSD -EDLED2 0_ 3-CC; ED24_7 -ED2S - MS; ED29 - MMFR,FS,FZ,FNED210 - DM; ED211 - AM; ED 15 - 31 - IAED232-35 -WKED2 37_ 39u CI, II, EI -If {I)s = 1, ED2 56_ 59-If {I)s = 0, RP not affectedED260 -RACI, II, EIRPMOVE TO MEMORY CONTROL INSTRUCTIONSThe following instructions may be used to sel ectively movea string of control words from a control image area to specifiedmemory control registers:Instruction NameMove to Memory ControlLoad Map (S-bit format)Load Map ell-bit format)Load Protection CodeLoad Locks (2-bit format)Load Locks (4-bit format)MnemonicsMMCLMAPLMAPRELPCLLOCKSLLOCKSEED261 -MAIf nonexistent instruction, 1 -CCl then, if (1)9 = 1,IA+S-IAMMCMOVE TO MEMORY CONTROL(Word index alignment, privileged, continueafter interrupt)If nonexistent memory address, 1 -(1)9 = 1, IA + 4 - IACC2 then, ifIf privileged instruction violation, 1 -{I)9 = 1, IA + 2 - IACC3 then, ifIf memory protection violation, 1 - CC4 then, if (1)9 = 1,IA + 1 - IAIf CALL instruction, CC u CALLS_ll -(I)9 = 1, IA + CALLS_ll - IACC then, ifThe MMC instruction may be used to perform any move tomemory control operation. Depending upon the type andformat of the control image, the move to memory controloperation may be performed either by an MMC instructionwitn a specifi c vaiue in The conTroi fieid (biT position 12-14.)or by a special purpose instruction (i. e., LMAP, LMAPRE,LPC, LLOCKS, or LLOCKSE), as shown below:If (1)9 = 0, IA not affe ctedIf watchdog timer, parity error, or instruction exceptiontrap, ED2 0_3 u TCCl-4 -CCl-4 then, if (1)9= 1,IA + TCC 1-4 - IAControl Field ofMMC instruction:Bit positions12 13 14Type and format ofcontrol image to beloadedAlternateInstructionMnemonicLRPLOA.D REG ISTER POINTER(Word index al ignment, privileged)0 0Memory write protectionlocks (2-bit format)LLOCKSReferenc~ address0Memory write protectionlocks (4-b it format)LLOCKSELOAD REGISTER POINTER loads bits 24-27 of the effectiveword into the register pointer (RP) portion of the currentprogram status words. Bit positions 0 through 23 and 2Sthrough 31 of the effective word are ignored, and no otherportion ofthe program status words is affected. If the LOADREGISTER POINTER instruction attempts to load the registerpointer with a value that points to a nonexistent block ofgeneral registers, the basi c processor traps to location X'4D'.0 00 00Access protection(always 2-bit format)Memory map (S-bitformat)Memory map (ll-bitformat)LPCLMAPLMAPREAffected: RPEW 24_ 27-RPTrap: Instruction exceptionAttempting to execute an MMC instruction with any codeother than the five shown above causes the instruction totrap to location X'4D' (instruction exception trap).Control Instructions 113

Normally, bit positions 15-31 may be ignored insofar as theoperation of the MMC instruction is concerned. The resultsof the instruction are the same whether MMC is indirectlyor directly addressed. However,if MMC is indirectly addressedand the indirect reference address is nonexistent,the nona II owed operation trap (location X' 40 ' ) is activated.The R field, which must be coded with an even value, designatesan even-odd pair of general registers (R and Ru1)that contain additional control information required by theMMC instruction. If the R fi eld is coded with an odd va I uea trap to location X'4D ' (instruction exception trap) occurs.Depending upon the type of addressing, the contents ofregister R may be as follows:If MA = 0, contents of register Rare:The Control Start field (bit positions 15-20, 21, or 22)points to the beginning of the memory region controlled bythe registers to be loaded. The significance of this fieldis different for the 5 modes of MMC operations and is describedwithin each mode below.Affected: (R),(Ru1),memory controlstorageCONTROL IMAGELOADING THE MEMORY MAPT raps: Instruction exception,nonallowed operation.Each word of the memory map control image contains eitherfour a-bit page addresses or two ll-bit extended page addresses,as illustrated below:Typical memory map control image word (a-bit format):If MA = 1 and MM = 0, the contents of register Rare:Typical memory map control image word (ll-bit format):In either case, the Control Image Address is the virtual addressof a control word within the control image area to beloaded into a block of memory control registers, as specifiedby the contents of register Ru 1.Depending upon the type of control image being loaded,the contents of register Ru 1 may be in one of the followingthree formats:Depending upon the memory map control image format, theinstruction format is one of the following:LMAPLOAD MAP (a-bit format)For loading memory map image (either a-bit or 11-bit format),contents of register Ru 1 are:LMAPRELOAD MAP REAL EXTENDED (ll-bit format)For loading 4-bit write lock images, contents of registerRu1 are:Depending upon the type of addressing, the format of registerR contents is one of the following:If MA = 0;For loading access protection or 2-bit write lock images,contents of register Ru 1 are:Map lma~e AddressIIf MA = 1 and MM = 0;The Count field (bit positions 0-7) specifies the numberofwords to be loaded from the control image area. If theinitial word count is zero, a word count of 256 is implied.114 Controi Instructions

For either memory map format and either type of addressing,the contents of register Ru 1 are:The instruction format for loading the access protectioncode is:MEMORY MAP LOADING PROCESSThe initial map image address (in register R) is the virtualaddress of the first word of the memory map control image.The initial count, as contained in register Ru1 specifies theword length of the control image to be loaded. A wordcount of 64 (for 8-bit format) or 128 (for 11-bit format) issufficient to load an entire block of 256 memory map controlregisters. The memory map control registers are treatedas a circular set, with the first register following the last;thus, a word count greater than 64 (8-bit format) or 128(ll-bit format) causes the first registers to be overwritten.The initial value of the control start field of register Ru1points to the first page (512 words) of virtual addresses thatare to be controlled by the memory map control image beingloaded. The memory map control image is loaded into thememory map control registers one word at a time. As thecontents of each word are loaded into either two orfour memorymap control registers, the map image address is incrementedby 1, the word count is decremented by 1, and thevalue in the control start field is incremented either byfour(if the memory map control image is in the 8-bit format)or by two (if the memory map control image is in the 11-bitformat). The loading process continues until the word countis reduced to zero.When the load process is completed, the map image addressof register R contains a value equal to the sum of the initialmap image address plus the initial word count, the wordcount of register Ru1 has a value of zero, and the controlstart field of register Ru1 contains a value equal to the sumof the initial contents plus four or two times the initialword count.LOADING THE ACCESS PROTECTION CONTROLSCONTROL IMAGEEach access protection control image word contains sixteen2-bit fields; or, the access protection codes for 16 consecutivepages of virtual memory. Thus, the access protectioncontrol image for 128K word (256 page) virtual memory iscontained within 16 contiguous memory locations, designatedas the access protection control image area.The format of a typi ca I access protection control imageword is:Depending upon the type of addressing, the format of registerR contents is one of the following:IfMA=O;If MA = 1 and MM = 0;Ac cess Prote ionFor either type of addressing, the contents of register Ru1 are:ACCESS PROTECTION LOADING PROCESSThe initial access protection control image address in registerR is the virtual address of the first word of the accessprotection control image.The initial count in register Ru1 specifies the word length ofthp rnnt .. nl ;rn,.,,.,p tn h., In,.,r1.,r1---- -----.- • • "--.;;;J- -- -- .--- ..... -_.A \A/1"\",..1 ,..""n+ "j: 11.. :...."j:-- •• -.- --_••• _ •.• - ........-.~fi cient to load the entire block of 256 access protection controlregisters. The access protection control registers aretreated as a circular set, with the first register following thelast; thus, a word count greater than 16 causes the first-registersloaded to be overwritten.The initial value of the control start field of register Ru 1points to the first page (512 words) of virtual addresses thatare to be controlled by the access protection control imagebeing loaded. The access protection control image is loadedinto the access control registers one word at a time, .. thusloading the control registers for 16 consecutive pages with thecontents of each image word. As each image word is loaded,the access protection control imag~ address is incrementedby 1, the word count is decremented by 1, and the value inthe control start field is incremented by 4. The lo~dingprocess continues until the word count is reduced to O.When the loading process is completed, the parameters containedwithin registers Rand Ru1 have the following values:Access protectioncontrol image address = initial access protection controlimage address plus the initial wordcount.Count = O.Control Start =initial contents plus 4 times theinitial word count.Control Instructions 115

MEMORY WRITE PROTECTION LOCKSWhen loading 2-bit write lock images, the contents ofregister Ru1 are:CONTROL IMAGEEach write lock control image word may contain eithereight 4-bit write lock images or sixteen 2-bit write lockimages, as illustrated below:Typi cal write locks image word {4-bit format};When loading 4-bit write lock images, the contents of registerRu1 are:Typical write locks image word {2-bit format};The number of words required to define the memory writelocks control image is dependent upon the format of thewrite lock images and the number of write lock registers tobe loaded by a single MMC instruction. {For example, ifthe write lock images are of the 4-bit format and the memorysystem is maximum size (1,024,000 words or 2048 pages)with 2048 write lock control registers, the control imagemay be defined by 256 words (i. e., 256 words times 8 writelock images per word is equal to 2048 write lock images orone write lock image per each write lock control register).If the write lock images are of the 2-bit format and thememory size is the same, as described above, the controlimage may be defined by 128 words.The instruction format for loading 2-bit write lock images is:LLOCKSLOAD LOCKS (2-bit format)The instruction format for loading 4-bit v:rite !eck imcges is:LLOCKSELOAD LOCKS (4-bit format)If MA = 0, the contents of register Rare:If MA = 1 and MM =0, the contents of register Rare:lock lmag~ AddressI , ,LOADING PROCESSDepending upon the addressing mode of the basi c processor,the contents of register R are interpreted as either a 17-bitor a 20-bit virtual address of an image word within thememory write locks control image area (source of write lockimages). The initial lock image address points to the firstimage word. After the contents of the image word (either 8or 16 write lock images) are loaded into an equivalent numberof write lock registers, the lock image address is incrementedby one. Thus, successive image words are accessedin an ascending sequence.Depending upon the instruction format, the hardware appendseither one or two low order zeros, as necessary, to convertthe 9-bit or 10-bit control start field into an 11-bit real _page address. In addition to being the real page addressof 512 consecutive memory word locations, the value of thell-bit control start field is also the address of the asso~iatedwrite lock control register. The value of the control startfield at the time the image word is accessed is the addressof the first of either 8 or 16 write lock control registersthat will be loaded by the write lock images containedwithin one image word. When all of the write lock imagesof a given word have been loaded into either 8 or 16 writelock control registers, the val ue of the 9-bit or 10-bit controlstart field is incremented by 4. (Note that this is equivalentto incrementing the \-'c!ue of the effective l1-bitfield by a value of either 8 or 16, the number of controlregisters loaded.)The count field of register Ru1 specifies the number of imagewords, and indirectly the number of write lock images to beloaded. Depending upon the instruction format, each imageword is interpreted as containing either eight 4-bit writelock images or sixteen 2-bit write lock images. In the caseof 2-bit write lock images, the hardware appends two highorder zeros to each image as it is loaded into the 4-bit controlregister. Thus, the number of write lock control registersloaded is always either 8 or 16 times the initial valueof the count field. If the initial valut:: of -the count fieldis zero, it is interpreted to be 256 words. During the loadingoperation, the count field is decremented by one afterthe contents of each image word are loaded into the appropriatenumber of control registers. The loading operationcontinues until the word count is reduced to zero. At thattime, the value of the lock image address is equal to its116 Control Instructions

initial value plus the initial value word count and the valueof the 9- or 10-bit control start field is equal to its initialvalue plus 4 times the initial word count.The memory write loc~ registers are treated as a circularset, with the register for memory addresses X'O'-X'lFF' (firstpage) immediately following the register for memory addressesX'FFEOO'-X'FFFFF' (last page). Overwriting thefirst registers occurs when 2-bit write lock images are beingprocessed and the word count is greater than 128.Prior to executing an LRA instruction, CC 1 and CC2 mustbe set to an appropriate value (as shown below).CCl CC2 Type of real address to be generated0 0 Byte (22 bits)0 Halfword (21 bits)0 Word (20 bits)Doubleword (19 bits)INTERRUPTION -OF MMCThe execution of MMC can be interrupted after each wordof the control image has been moved into the specified controlregister. Immediately prior to the time that the instructionin the interrupt ortrap location is executed, the instructionaddress portion of the program status words contains thevirtual address of the MMC instruction, register R containsthe virtual address of the next word of the control image tobe locided, and register Ru 1 contains a count of the numberof control image words remaining to be moved and a valuepointing to the next memory control register to be loaded.After interrupt, the MMC instruction may be resumed fromthe point it was interrupted.MEMORY ACCESS TRAPS BY MMC INSTRUCTIONA trap during execution of the MMC instruction can occurif the pages containing the control images are nonexistentor are protected in the master-protected mode. The registersRand Ru 1 may be a I tered for the above case. If aparity error should occur during access of a control imageword, theMMC instruction will trap with the RegisterAIteredindicator set indicating that a change has been made to thememory control registers. The registers Rand Ru 1 will berestored to their initial values, prior to the point at whichthe trap occurred.LRALOAD REAL ADDRESS(Word index al ignment, privileged)The effective virtual address for the LRA instruction itselfmay be generated in a normal manner (i. e., indirect addressing,indexing, and/or mapping, as applicable, may bespecified and performed) with all standard trapping conditionsin effect.The address loaded into the R register is dependent uponthe value of the address portion of the effective word. If theaddress portion of the effective word is equal to or greaterthan 16, it is converted (mapped) into a 19, 20, 21, or 22-bitreal address, as specified by CC 1 and CC2.Note: Converting an effective virtual address into a realaddress by mapping is performed independently ofthe state of the map bit in the current PSWs.If the address portion of the effective word is less than 16,it is not mapped into a real address. Instead, a 19, 20, 21,or 22-bit effective virtual address is generated, as specifiedby CC 1 and CC2.In either case a 19, 20, 21, or 22-bit real or effective virtualaddress is loaded into a corresponding number of loworder bit positions of the R register (i. e., the least significantbit of the address is always loaded into bit position 31of register R). Except for bit positions reflecting status information,all high order bit positions within register Rareset to zero. Contents of the various bit positions of registerR after an LRA instruction are as follows:Bits0-910-31ContentsReserved; always set to O.Real or effective virtual address. For 21-, 20-,and 19-bit addresses, as specified by initial valueof CC 1 and CC2, bit positions 10, 11, and 12will be set to zeros, as required.Affected: (R),CCLOAD REAL ADDRESS converts the address portion of theeffective word into a reaf byte, halfword, word, or doublewordaddress (as specified by CC 1 and CC2 at the beg inn ingof the LRA instruction) and loads that real address and statusinformation (as listed below) into register R. Upon completionof the LRA instruction, additional information pertainingto the LRA instruction or to the real address is providedvia the condition code.Condition code settings:o 02 3 4 Results in R registerNo abnormal condition.- Address in R is real but for a nonexistentmemory location.Control Instructions 117

2 3 4 Results in R register- 0o11o 0 Address in R is an effective virtual address(address of a general register).Note: Condition code setting 11-- and 1100--- may be distinguished in the softwareby examining the address (bits 10-31).~1 Access protect code for the page containingo the memory location specified by the gener-1 ated address.Note: This instruction requires two memory references tothe same location for its execution. To precludeother processors from accessing the effective locationduring this time, the memory unit containingthe effective location is reserved (not accessible toother processors) until the LRA· instruction iscompleted.2 3 4 LMS ActionIt does, however, generate the Memory ParityError signal. The basic processor inhibits thetrap that would·ordinarily occur for the memoryparity error.o 0 o Clear memory - stores zero in the memorylocation specified by the address.o 0oooo 0oReserved.Reserved.Reserved.o Read write lock - loads a pair of 4-bit writelocks into byte 3 of R (bits 24-31) and 0 in allother bit positions of R. The write lock storedin bits 24-27 is stored in the memory system'sWrite Lock memory at the location correspondingto bits 17-21 of the effective address,bit 22=0. The write lock stored in bits 28-31corresponds to bits 17-21 of the effective address,bit 22=1.LMSLOAD MEMORY STATUS(Word index al ignment, privileged)oWrite write lock - stores byte 3 of the dataword sent to memory as a pair of write locksin the memory system's Write Lock memory ata location corresponding to bits 17-21 of theeffective address, bit 22= 0 (for data bits 24-27)and bits 17-21 ofthe effective address, bit 22=1(for data bits 28-31).LOAD MEMORY STATUS is used to determine memory unitstatus and/or to perform diagnostic action on a memory unit.The effective address is used to determine the memory unit.The condition code setting immediately before executiondetermines the diagnostic action to be performed. The effectiveaddress always references memory even if it is lessthan 16. The condition code can be set to the desired valuebefore execution of LMS with the LCF or LCFI instructions.RegisTer R is loaded with the result of the action. Thecondition code is set at the conclusion of execution toreflect the status of the word loaded (if any).Affected: (R),CC T rap: See liT rap System ",Chapter 2.Initial condition code settings:2 3 4 LMS Actiono 0 0 0 Read and set - causes the same action as theLOAD AND SET (LAS) instruction, except for·condition code serrmgs. Normai traps areallowed including write protect.000 Read and inhibit parity - loads the effectiveword into R. If a memory parity error is detected,the memory does not take a "snapshot 11or generate a Memory Fau I t Interrupt (MFI).o 0 0 Read status word ot - loads status word 0 intoR (see Table 9).o 0 Reserved.o 0 Read status word 1t - loads status word 1 intoR (see Table 10).oReserved.o 0 Read status word 0 and clear.oReserved.o Write double error - stores an arbitrary wordinto a specified memory location, with twodifferences compared to a normal Write Wordinstruction: (1) Byte 3 in memory is forced tozero; (2) the arbitrary word is stored in memorywith an intentional wrong parity; on a sUbsequentread of that word, the memory issuesthe parity error-signal.Reserved.Condition code settings after execution.t Primarily of diagnostic concern.118 Control Instructions

Table 9. Status Word 0Field Bits Comments0 Reserved1 Power status2-7 Memory un i t error cod e8-9 Memory typePorts 10 Port 1 enabled11 Port 2 enabled12 Port 3 enabled13 Port 4 enabled14 Port 5 ena bl ed15 Port 6 enabled16 Port 1 serv iced17 Port 2 serviced18 Port 3 serviced19 Port 4 serviced20 Port 5 serviced21 Port 6 servi cedMemory fau I t 22 0types23 Uncorrectable memory unit error24 Memory module selection error,..e: A 1.1. ____ ._____!L__________Lv /",,\UUIC;:);:) pUllly CliVI26 Data in parity error27 Write lock parity error28 Port selection error29 Undefined operation30 Control error31 Multiple errorFor IIread and inhibit parityll operations, the status of theword loaded (if any) is stored in the condition code bits atthe conclusion of execution as follows:CC 1:Memory Parity Error (from memory)CC2: Data Bus Check (from CPU)CC3: Parity Bit (from memory)CC4: 0T abl e 10. Status Word 1Field Bits Comments0 Interleave switch ON1-3 Memory un it size:000 8K001 16K010 24K011 32K100 40K101 48K110 56K111 64K4-6 Memory unit number (binary code)Starting 7 Starting address bit 12Address8 Starting address bit 13WAIT9 Starting address bit 1410 Starting address bit 1511 Starting address bit 1612 Starting_ address bit 1713 Starting address bit 1814 Reserved15-31 Address received, bits 15-31WAIT(Word index al ignment, privileged)WAIT causes the basic processor to cease all operations untilan interrupt activation occurs, or until the operator putsthe basic processor in the IDLE mode and then back to RUN(see Chapter 5). The instruction address portion of the PSWsis updated before the basic processor begins waiting; therefore,while it is waiting, the INSTRUCTION ADDRESS indicatorscontain the virtual address of the next location inascending sequence after WAIT and the contents in the nextlocation are displayed in the DISPLAY indicators on theprocessor control console. If any input/output operationsare being performed when WAIT is executed, the operationsproceed to their normal termination.When an interrupt activation occurs while the basic processoris waiting, it processes the interrupt-servi cing routine.Normally, the interrupt-servicing routine begins with anXPSD instruction in the interrupt location, and ends withan LPSD instruction at the end of the routine. After theLPSD instruction is executed, the next instruction to be executedin the interrupted program is the next instruction insequence after the WAIT instruction. If the interrupt is to aControl Instructions 119

single-instruction interrupt location, the instruction in theinterrupt location is executed and then instruction executionproceeds with the next instruction in sequence after theWAIT instruction. When the basic processor execution modeis changed from RUN mode to IDLE mode and back to RUNwhile the basic processor is waiting, instruction executionproceeds with the next instruction in sequence after theWAIT instruction.Affected: PCIf WAIT is indirectly addressed and the indirect referenceaddress is nonexistent, the nonallowed operation trap tolocation X'40 ' will not occur. The effective virtual addressof the WAIT instruction, however, is not used as a memoryreference (thus does not affect the norma I operation of theinstruction).RDREAD DIRECT(Word index alignment, privileged)16 17 18 19a a: ]Unassigned.Special systems control (for customer usewith specially designed equipment).If bits 16-19 select mode 2 through mode F, CC 1 and CC2are set to zero and CC3 and CC4 are set according to thestate of the two condition code lines from the externaldevice.READ DIRECT. INTERNAL BASIC PROCESSORCONTROL (MODE 0)In this mode, the basic processor is able to read the senseswitches, the basic processor address, and the interrupt inhibitbits of the PSWs as follows:READ SENSE SWITCHESThe following configuration of RD can be used to read thefour SENSE switches in the System Control Processor:The basic processor is capable of directly communicatingwith other elements of the system, as well as performinginternal control operations, by means of the READ DIRECT /WRITE DIRECT (RD/'ND) lines. The RD;WD lines consist of16 address lines, 32 data lines, two condition code lines,and various control I ines that are connected to various basicprocessor circuits and to special system equipment.READ DIRECT causes bits 16 through 31 of the effectivevirtual address to be presented to other elements ofthe systemon the RD/'ND address lines. Bits 16-31 of the effectivevirtual address identify a specific elementof the system thatis expected to return information (two condition code bitsplus a maximum of 32 data bits) to the basic processor. Thesignificance and number of data bits returned depend on theselected element. If the R field of RD is nonzero, up to32 bits of the returned data are loaded into general registerR; however, if the R field of RD is 0, the returned datais ignored and general register a is not changed. Bits CC3and CC4 of the condition code are set by the addressedelement, regardless of the value of the R field.Bits 16-19 of the effective virtual address of RD determinethe mode of the RD instruction, as follows:Bit Position16 17 18 19 Modea a a ao a aInterna I basi c processor control.Interrupt control.a a a Xerox testers.If a particular SENSE switch is set, the corresponding bit ofthe condition code is set to 1; if a SENSE switch is zero,the corresponding bit of the condition code is set to a (see"Read Sense Switches" in Chapter 5).In this case, only the condition code is affected.READ BASIC PROCESSORThe following RD configuration is used to read the basicprocessor's address:If the R field is nonzero, the cluster number in which thebasic processor resides is obtained from the associated processorinterface and loaded into register R bits 21-23. Allother bits in the register are cleared to zero.Affected: (R)Cluster Address - R 21- 230- R O- 20and R 24- 31120 Control Instructions

READ INTERRUPT INHIBITSThe following configuration of RD can be used to read thecontents of the interrupt inhibit field:loaded into register R. Although the Q address field permitsany of 32 addresses to be specified, only the following maybe used:Q AddressContentsX'lD'(Bits 0-13) - Reserved{ (Bits 14-31) - "Branch from" ProgramCounterIf the R field of RD is nonzero, the contents of the interruptinhibit field (bits 37, 38, 39) of the program status wordsare transferred to the least significant 3 bits of the specifiedR register (bits 29, 30, 31). The remainder of the Rregister (bits 0-28) is cleared to zeros.Affected: (R)(PSWs)37_39 - R 29 - 310- R O- 28Note that a copy of the interrupt inhibits is retained in theInterrupt Status Register in the Processor Interface associatedwith each basic processor.X'lP(Bits 0-7) - Reserved{(Bits 8-31) - Load Device AddressAll other Q addresses from X'OO' - X'lF' are reserved.Affected: (R)EW-RREAD DIRECT, INTERRUPT CONTROL (MODE 1)The following configuration of RD is used to control thesensing of the various states of the individual interruptlevels within the basi c processor interrupt system:LOAD FROM LOW MAIN MEMORY1* I 6C I R I X I~):; 0000Rff~o~~c1~fJ~~~~~~es;~~~ Io 1 2 31456718910 11112 13 14';5116 17 18 19120212223124252627128 29 30 31The instruction allows reading the contents of real memorylocations 0-31 (locations 0-15 shadowed by the genera Ipurpose registers). This allows access to the Status StackPointer Doubleword in locations 0-1 and the default ProgramStatus Words (Interrupt Stack is empty) in locations 2-4.If the R field is nonzero, the contents of the main memorylocation identified by bits 27-31 are loaded into R.Affected: (R)EW-RREAD INTERNAL CONTROL REGISTERSThe following configuration of RD is used to read the contentsof internal control (or Q) registers:II * 6C I R I X~)~ I i 0000 Rtfe[eDOr 0011 }}}t@ Ad~fe~s Q add ~o 1 2 314 5 6 7 8 9 10 1112 13 14 ';516 17 18 19 ~ 21 22 23 '24--2';"26 27 28 29 30 31If the R field of the RD instruction is nonzerO, the contentsof the internal control register, as specified by the IIQ Address"field of the rnstruction (bit positions 27-31), areBits 28 through 31 of the effective address specify the identificationnumber of the group of interrupt levels to be controlledby the READ DIRECT instruction.The R field of the RD instruction specifies a general registerthat will contain the bits sensed from the individual interruptlevels within a specified group. For external interruptgroups, bit position 16 of register R contains the appropriateindicator bit for the highest priority (lowest number) interruptlevel within the group and bit position 31 of register Rcontains the indi cator bit for the lowest priority interruptlevel within the group. For assignments in Group X'O', seeTable 11. Each interrupt level in the designated group issensed according to the function code specified by bits 21through 23 of the effective address of RD. The codes andtheir associated functions are as fol lows:Code001010FunctionRead Armed or Waiting State. Set to 1 the bits inthe selected register which correspond to interruptlevels in this group that are in either the armed orthe waiting state. Reset all other bits to zero.Read Waiting or Active State. Set to 1 the bitsin the selected register which correspond to eachinterrupt level in this group that is in either thewaiting or the active state. Reset all other bitsto zero.100 Read Enabled. Set to 1 the bits in the selectedregister which correspond to each interrupt levelin this group which is enabled. Reset all otherbits to zero.Control Instructions 121

READ DIRECT (MODE 9)READ CONFIGURATION CONTROL PANELWRITE DIRECT, INTERNAL BASIC PROCESSORCONTROL (MODE 0)LOAD SENSE SWITCHESThe fol lowing configuration of WD can be used to load thesense switches in the System Control Processor:The mode 9 instruction reads the state of the ConfigurationControl Panel for the addressed cluster or unit. Physicaladdresses are assigned at the time of system configuration.The returned status to Register R is shown in Tables 11 and 12.WDWRITE DIRECT0/Vord index alignment, privileged)If the R field is nonzero, bits 0 through 3 of Register Rwill be loaded into sense switches 1 through 4 in the SystemControl Processor. If the R field is zero, sense switches willbe reset to zeros. (See the section "System Control Panel"in Chapter 5.)SET INTERRUPT INHIBITSWRITE DIRECT causes bits 16-31 of the effective virtual addressto be presented to other elements of the system on theRD;WD address lines (see READ DIRECT). Bits 16-31 of theeffective virtual address identify a specific element of thesystem that is to receive control information from the basicprocessor. If the R field of WD is nonzero, the 32-bit contentsof register R are transmitted to the specified elementon the RD;WD data I ines. If the R field of WD is 0,32 O'sare transmitted to the specified element (instead of the contentsof register 0). The specified element may returninformation to set the condition code.Bits 16-19 of the effective virtual address determine themode of the WD instruction, as follows:16 17 18 19 ModeThe following configuration of WD can be used to set theinterrupt inhibits (bit positions 37-39 of the PSWs):A logical inclusive OR is performed between bits 29-31 ofthe effective virtual address and bits 37-39 of the PSWs. Ifany (or all) of bits 29-31 of the effective virtual addressare l's, the corresponding inhibit bits in the PSWs are setto l's; the current state of an inhibit bit is not affected if acorresponding bit position of the effective virtual addresscontains a O.Note that a copy of the Interrupt Inhibits is retained in theInterrupt Status Register in the Processor Interface associatedwith each basic processor.o 0 0 0Interne! basic processor centro!.000 Interrupt control.000 Xerox testers.o 0Unassigned.RESET INTERRUPT INHIBITSThe following configuration of WD can be used to reset theinterrupt inhibits:Special systems control (for customer use•• I • 'I •• • • • \wlfn speCIallY aeslgnea equlpmenr).If bits 16-19 select mode 2 through mode F, CC 1 and CC2are set to zero and CC3 and CC4 are set according to thestate of the two condition code I ines from the externa Idevice.If any (or al I) of bits 29-31 of the effective virtual addressare l's, the corresponding inhibit bits in the PSWs are resetto 0'5, the current state of an inhibit bii is not affected ifa corresponding bit position of the effective virtual addresscontains a O.Note that a copy of the Interrupt Inhibits is retained in theInterrupt Status Register in the Processor Interface associatedwith each basic processor.122 Control Instructions

Table 11.Read Direct Mode 9 Status WordRD Status WordBit No. Processor Cluster 1 Memory Unit 100 System Select System Select01 Clock Select Clock Select02 Processor Cluster Address 22 Unit No. 2203 Processor Cluster Address 21 Unit No. 2104 Processor Cluster Address 2 0 Unit No. 2°05 BP Enable Port Enable 106 MIOP Enable Port Enable 207 DIO Enable Port Enable 308 Not Assigned Port Enable 409 ALTSEL Port Enable 510 FSELA Port Enable 611 FSELBO Not Assigned12 FSELBI Not Assigned13 Real Time Clock 1-S0 Interleave Enable14 Real Time Clock 1-S 1 Starting Address S 1215 Real Time Clock 2-S0 Starting Address S 1316 Real Time Clock 2-S 1 Starting Address S 1417 Real Time Clock 3-S0 Starting Address S 1518 Real Time Clock 3-S 1 Starting Address S 1619 Subjective Time Clock -so Starting Address S 1720 Subjective Time Clock -S 1 Starting Address S 1821 Not Assigned Not Assigned22 Not Assigned Not Assigned23 Not Assigned Not Assigned24 Not Assigned Not Assigned25 Not Assigned Not Assigned26 Not Assigned Not Assigned27 tChassis Type-~ tChassis Type-2 428 Chassis Type-2 3 Chassis Type-2 329 Chassis Type-2 2 Chassis Type-2 230 Chassis T ype-2 1 Chassis Type-2 131 Chassis Type-2 0 Chassis Type-2 0tSee Chassis Type Table.Control Instructions 123

Table 12. Chassis Type AssignmentsChassis Type 24 23 22 21 20 Configuration InformationProcessor Clusters 1 1 0 0 0 Reserved1 1 0 0 1 Reserved1 1 0 1 0 Processor Cluster Type 11 1 0 1 1 Reserved1 1 1 0 0 Reserved1 1 1 0 1 Reserved1 1 1 1 0 Reserved1 1 1 1 1 ReservedController Clusters 1 0 0 0 0 Reserved1 0 0 0 1 Reserved1 0 0 1 0 Reserved1 0 0 1 1 Reserved1 0 1 0 0 Reserved1 0 1 0 1 Reserved1 0 1 1 0 Reserved1 0 1 1 1 ReservedMemory Un its 0 1 0 0 0 Memory Un itT ype 10 1 0 0 1 Reserved0 1 0 1 0 Reserved0 1 0 1 1 Reserved0 1 1 0 0 Reserved0 1 1 0 1 Reserved0 1 1 1 0 Reserved0 1I1 1 1 ReservedReserved 0 0 0 0 0 Not available0 0 0 0 1 Reserved0 0 0 1 0 Reserved0 0 0 1 1 Reserved0 0 1 0 0 Reserved0 0 1 0 1 Reserved0 0 1 1 0 Reserved0 0 1 1 1 Reserved124 Control Instructions

SET ALARM INDICATORThe following configuration ofWD is used to set the ALARMindicator on the maintenance section of the processor controlpanel:LOAD INTERRUPT INHIBITSThe following configuration of WD can be used to transferthe contents of the specified R register (R29-31) to theInterrupt Inhibit field (PSWs 37_ 39).If the processor is in the RUN mode and the AUDIO switchon the maintenance section of the processor control panelis in the ON position, a 1000-Hz signal is transmitted tothe basic processor speaker. The signal may be interruptedby changing from RUN mode to IDLE mode, by moving theAUDIO switch to the OFF position, or by resetting theALARM indicator.Affected: (PSWs 37_ 39)(R 29- 31) - PSWs 37_ 39TURN ON MODE ALTERED FLAGThe following configuration of WD is used to set the ModeAltered Flag (PSWs 61) to 1:RESET ALARM INDICATORThe following configuration of WD is used to reset theALARM indicator:TURN OFF MODE ALTERED FLAGThe following configuration of WD is used to reset the ModeAltered Flag (PSWs 61) to 0:The ALARM indicator is also reset by either the RESET BPor the RESET SYSTEM Command entered from the operator'scontro I conso Ie.STORE IN LOW MAIN MEMORYTOG G LE PROG RAM-C ONT ROLLED-FREQUENCYFLIP-FLOPThe following configuration of WD is used to set and resetthe basic processor program-controll ed-frequency (PCF)flip-flop:This instruction writes into main memory locations 0-31(locations 0-15 shadowed by the general purpose registersand reserved locations). This allows storing or changing theStatus Stack Pointer Doubleword in locations 0-1 and thedefault Program Status Words (Status Stack is empty) inlocations 2 through 4. .If the R field is nonzero, the contents of R are stored in themain memory location identified by bits 27-31.TRAP TO LOCATION X'47 1The output of the PCF flip-flop is transmitted to the basicprocessor speaker through the AUDIO switch on the maintenancesection of the System Control Panel. If the PCFfl ip-flop is reset when the above configuration of WD isexecuted, the WD instruction sets the PCF flip-flop; if thePCF fI ip-flop was previously set, the WD instruction resetsit. A program can thus generate a desired frequency bysetting and resetting the PCF flip-flop at the appropriaterate. Execution of the above configuration of WD also resetsthe ALARM indicator.This instruction causes the basic processors to trap to locationX'471.A line in the Processor Bus is raised by the initiating basicprocessor (or the associated PI). This line, when true, causesthe basic processors to trap to X' 47 1 (including the one thatexecutes the instruction).Control Instructions 125

WRITE INTO INTERNAL CONTROL REGISTERThe following configuration of WD is used to write into theinternal control (or O) registers:If the R field is nonzero, the contents of register Rareloaded in the control register, as specified by the 110 Addressll field (bit positions 27-31) of the WD instruction.Except for the four 0 addresses listed below, all other addressesare reserved:The R field of the WD instruction specifies a general registerthat contains the selection bits for the individual interruptlevels within the specified group. For external interruptgroups, bit 16 of register R contains the selection bit forthe highest-priority (lowest-numbered) interrupt level withinthe group, and bit 31 of register R contains the selection bitfor the lowest-priority (highest-numbered) interrupt levelwithin the group. For assignments in Group X'O', see Table 11.Except for Power on/Power off interrupt levels, which cannot be disabled, disarmed, or inhibited, each level in thedesignated group is operated on according to the functioncode specified by bits 21-23 of the effective address of WD.The codes and their associated functions are as follows:o AddressSignificanceCodeFunctionX'lD'X'lE'{{(Bits 00-13) - Reserved.(Bits 14-31) - Write into the IIBranch From IIprogram counter.(Bits 00 through 07) - Reserved.(Bits 08 through 3l) - Write into the IILoadDevice Address ll register.If the R field is zero, the specified register is loaded withall zeros.Affected: (EL)(R) -(EL)000 Setactive all selected levels currently in the armedor waiting states.001 t Disarm all levels selected by a 1; all levels selectedby a 0 are not affected.o lOt011 t100Arm and enable all levels selected by a 1; alllevels selected by a 0 are not affected.Arm and disable all levels selected by a 1; alllevels selected by a 0 are not affected.Enable all levels selected by a 1; all levels selectedby a 0 are not affected.WRITE DIRECT, INTERRUPT CONTROL (MODE 1)101Disable all levels selected by a 1; all levels selectedby a 0 are not affected.The following configuration of WD is used to set and resetthe various states of the individual interrupt levels withinthe basi c processor interrupt system:110Enable all levels selected by a 1 and disable alllevels selected by a O.111 Trigger all levels selected by a 1. All such levelsthat are currently armed advance to waiting state.Bits 28-31 of the effective address specify the identifi cationnumber (see Table 11) of the group of interrupt levels to becontrolled by the WD instruction.tThese codes clear the current interrupts! i. e.! remove fromthe active or waiting state all levels selected by a 1 (seeFigure 12).126 Control Instructions

INPUT jOUTPUT INSTRUCTIONSThe I/o instruction set is comprised of eight instructions,as listed below.Instruction NameStart Input/OutputTest Input/OutputTest DeviceMnemonicSIOTIOTDYI/O STATUS INFORMATIONSIO, TIO, TDY, AND HIO INSTRUCTIONSIf the R field is coded with a 0, no status information is requestednor loaded. If the R field is odd, one word of statusinformation is requested to be loaded into register R as specifiedby the R field. If the R field is even (not zero), twowords of status information are requested to be loaded intoregisters Rand Ru 1 .The following I/O status information may be loaded intoregister R only when the R field is coded with an even(nonzero) value.Halt Input/OutputReset Input/OutputPoll ProcessorPoll and Reset ProcessorAcknowledge Input/Output InterruptOVERALL CHARACTERISTICSHIORIOPOLPPOLRAIOThe significance of each bit within register R is describedin Table 14.The following I/O status information may be loaded intoregister R if the R field is odd, or into register Ru 1 if theR fi e I dis even and not zero.The format of information within the specified general register(R or Ru1) is shown below.All I/o instructions are privi leged and can be performedonly when the basic processor (BP) is in either the masteror master-protected mode. If the BP attempts to executean I/o instruction when it is in the slave mode (bit 8 ofthe current PSW is a 1), the instructi on is aborted at thetiml'> thl'> nnl'>rntinn c-nrll'> is rlpc-nrlprl nnrl thp RP trnns to 10-. - - - - - - - - 1- - - -- - - - - - - - - - - - - - - Ication X1401. Programs operating in the slave mode mustrequest I/O services from the System Monitor.At the end of every I/O instruction, the condition codebits represent a summary descri pti on of the resu I ts of theI/O operation and conditions within the addressed I/Osubsystem. Specific condition code settings and meanings(unique for each I/O instruction) are contained in the detaileddescription for each I/O instruction.All I/O instructions, except RIO, may request detailedI/O status information. The type and amount of I/o statusinformation that may be requested is determined by the operationcode and the R field of the I/O instruction. TheR field also designates which general register(s) is to beloaded with the requested information. (Refer to I/o StatusInformati on for further detai Is. )I/O instructions are similar to other word-addressing instructionsin that bits 15-31 may be modified by indirectaddressing and/or indexing. However, the final value ofthese bits is not used as an effective virtual address formemory reference. Instead, depending upon the I/o instruction,these bits are used as an extension to the operationcode field, as an I/O address to select a particularI/o subsystem, or they may be reserved. Further detai Isof I/o instructions are illustrated in Figure 13 and describedin Table 13.Device Status Byte. These eight bits (0-7) when loadedinto the specified general register provide status informationpertaining to the addressed device and device controller orlOP. The significance of each bit when requested by anSIO, TIO, and HIO instruction is described in Table 15.The significance of these bits when requested by a TDY instructionis different and is described in the applicableperipheral device reference manual.Operational Status Byte. Bits 8-15 of the specified generalregister (R or Ru1) indicate either the presence (1) orabsence (0) of various errors which may have occurredduring an I/O operation. The significance of the individualbits within the operational status byte are describedin Table 16.Table 17 is the summary description of the Device StatusByte and the Operational Status Byte.Byte Count. Bits 16-31 of register Ru1 indicate the numberof bytes that have to be transmitted to or from memoryin the operation called for by the current I/o commanddoubleword.RIO INSTRUCTIONNo status information is returned to the general registersfor an RIO instruction (the R field is ignored). Only conditioncode bits (CC 1 - CC3) are set to reflect the I/Oconditions.Input/Output Instructions 127

o 2 3 4 5 6 78 9 10 11 12 13 '4'5 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31MnemonicSIOTIOTDVHIORIOPOlP111* I Operation Code R X t&o~~ I/o Address I ~~~~~~;:~~:!;;-~. ~--------------~--------~------~-~~-----~~----------------------------~-ing and/orOperation Code(Hexadecimal)444444CDEFFFRRRRRRXxxxxxoo 0)15 (2) 17 18 20 21 23 24 27 28 31o 000 DCACA UA 1 DCA DAo 000 DCACA UA1 DCA DAo 000 DCACA UA1 DCA DAo 000 DCA000 CA UA1 DCA DA001 CA010 CAindexingPOlRAlO46FERRXxo 1 1CA00 000o Portions of a word format that are shaded represent bits that are reserved (after the I/o address is generated) andmust be coded with zeros to ensure program compatibility with possible enhancements to software and/or hardware.o OCE = operation code field extension; CA = cluster address; UA = unit address; DCA = device controller address;DA = device address.o To address a single-unit device controller, bit 24 must be a 0; to address a multiunit device controller, bit 24must be a 1.Figure 13. Formats of I/O InstructionsTable 13.Description of I/o InstructionsBit Applicable InstructionsPosition (Mnemonics) Function and/or Description0 A!! I/O instructions If this bit is a 1; bits 15-31 of the initla! Vo instruction are modified by indirectaddressing.1-7 SIO, no, TDY, and AIO For these four instructions, the operation code uniquely defines the I/O operationthat is to be performed.HIO, RIO, POLP, and Within bit positions 1-7, these four instructions all have the same operationPOLR code (X I 4F'). The instructions are differentiated by using bits 15, 16, and 17as an extension of the operation code field.8-11 SIO, no, TDY, and HIO The value of the R field specifies how much status information is requestedfrom the addressed I/O subsystem (lOP, device controller, and device) andinto which general register{s) the status information is to be loaded. If thevalue of the R field is even and not 0, two words of status infol'rTIution OlE: IE:-quested to be loaded into registers Rand Rul. If the value of the R field is odd,one word of status information is requested to be loaded into register R.RIOAlthough the R field is not used by the RIO instruction, the R field may becoded with any value as required by the program.128 Input/Output Instructions

Table 13.Description of I/o Instructions (cont.)BitPositionApplicable Instructions(Mnemonics)Function and/or Description8-11 POLP and POLR(cont. )This field specifies which general register (including register 0) is to receiveprocessor(MIOP, RMP, BP, MI, PI, or System Control Processor) fault information.AIOIf the R field is 0, no status information is requested. If the R field is not 0, thedesignated general register is to be loaded with the requested status information.12-14All I/O instructionsThe X field may be used to specify indexing.15-17510, TIO, TDY, and AlOAfter the I/O address is generated, these bits are reserved and must be codedwith zeros.HIO, RIO, POLP, andPOLRThese bits are an extension to the operation code field (bits 1-7) and permiteach of these instructions to be uniquely defined.Note that these bits are subject to modifications due to indirect addressing orindexing. The final configuration of these bits must be as shown below:HIO = 000RIO = 001POLP = 010POLR = 01118-31All I/o instructions(except AIO)The I/O address (after any indirect addressing and/or indexing) is containedwithin these bits. Depending upon the I/O instruction, the required I/oaddress may be comprised of (1) a cluster address; (2) a cluster address and auni t addressi (3) a cluster address, a uni t address, and a devi ce controll eraddressi or (4) a cluster address, a unit address, a device controller address,and a device address.Subfields of the final I/o address field are described below.----- - -------- - - - - -1-- - - - - - - - - - - - - - - - - - - - - - - - - - --1823All I/o instructions(except Ala)These bits constitute the cluster address (CA) and the unit address (UA) fieldof an I/O instruction. Cluster and unit addresses may be assigned in thefollowing manner:1. The assignment of addresses is mutually exclusive, that is, no two unitsmay have the same address.2. Bits 18-20 represent a cluster address.3. Bits 21-23 represent a unique unit within that cluster. Since all processorclusters contain as a minimum a Processor Interface (PI) unit and a memoryinterface (MI) unit, the address (110) 21-23 and (111) 21-23 have beenpreassigned to these units.- - - - - - -- - - - - - - - - - - - - - - - - - - -AlOAfter the I/o address is generated, these bits are reserved and must be codedwith zeros.24510, TIO, TDY , and HIOIf the I/O instruction is addressed to a single-unit device controller, this bitmust be coded as a O. If the I/O instruction is addressed to a multiunit devicecontroller, this bit must be coded as a 1. Note that bit 24 is not consideredas part of the device controller address.Input/Output Instructions 129

Table 13. Description of I/O Instructions (cont.)Bit Applicable InstructionsPosition (Mnemonics) Function and/or Description24 RIO, POlP, POlR, and AlO After the I/O address is generated, this bit is reserved and must be coded(cont.)with a zero.'"--- ~---- - ---------------------2531510, TIO, TDV, and HIO If the I/o instruction is addressed to a single-unit device controller (bit 24is a D), bits 25-31 represent one of 16 possible device controller addresses(X'OO' - X'OF'). There is no need to specify a device address.If the I/o instruction is addressed to a multiunit (e. g., magnetic tape) devicecontroller (bit 24 is a 1), bits 25-27 represent one of eight possible devicecontroller addresses (X'D' - X'7') and bits 28-31 represent one of 16 possibledevice addresses (X'D' - X'FI).Device controller addresses assigned to controllers within the same I/O channel(e. g., MIOP), must be mutually exclusive. Note that bit 24, which mustbe a 0 when addressing a single-unit device controller and a 1 when addressinga multiunit device controller, is not considered a part of the decive controlleraddr~ss. Thus, for example, if the device controller address X'D' is assignedto a multiunit device controller within an MIOP, no other device controller(single or multiunit) within that MIOP may have an address of XIOI.-- - - - -- - - - - - - - - - - - - - - - ---RIO, POlP, POlR, and AIOAfter the I/o address is generated, these bits are reserved and must be codedwith zeros.Table 14. I/o Status Information (Register R)Table 14. I/o Status Information (Register R) (cont.)BitBitPosition Significance Position SignificanceoReserved tBus Check Fault (BCF). This bit is set to 1if a discrepancy exists between the parityerror status in the memory unit and the lOPwhen an lOP is performing a main memoryread cycle. If the error occurs whi Ie accessingdata then the devi ce halt is controlledby the Halt-on-Transmission-Error flag (bitposition 36 of an I/O command doubleword).If the error occurs whi Ie fetching a command,the operation is terminated immediatelywith an "unusual end ll •Control Check Fault (CCF). This bit is setto 1 when a parity error occurs during a subchannelread operation within the MIOP.The operation terminates immediately withan "unusual end".3 tt Memory Interface Error (MIE). lOP Haltcondition is the same as a Bus Check Fault.4-1213-31Reserved tCurrent Command Doubl eword Address. The19 high-order bits of the main memory addressfrom which the command doubleword for theI/o operation currently being processed bythe addressed I/O subsystem is fetched.tTo ensure program compatibility with possible softwareand/or hardware enhancements, it is recommended thatreserved bits be treated as indeterminate and not used(L e, i masked),ttThe lOP unconditionally sets the Processor Fault Indicator(PFI) whenever a Bus Check Fault, Control CheckFault, Control Memory Fault, or Memory Interface Erroroccurs. The lOP fault status registerisset with status informationas listed under the POlP or POlR instructions.130 Tnput/Output Instruction

Table 15.Device Status Byte (Register R or Rul)(510, no, and HIO only)Table 15. Device Status Byte (Register R or Ru1)(510, no, and HIO only) (cont.)BitPositionSignificanceBitPositionSignificancea1,2Interrupt Pending. This bit is set to a 1 ifthe addressed device has requested an interruptthat has not been acknowl edged by theBP with an AIO instruction. If this bit isa 1, the current 510 instruction is not accepted.Condition code bits are set to reflectthis action and any requested statusinformation is loaded into the designatedgeneral register(s). 510 instructions wi II notbe accepted unti I the interrupt pendi ng conditionis cleared.Normally, before a device can request aninterrupt, the following conditions mustprevail:1. Appropriate flag(s) (IZC, ICE, and/orIUEi bit positions 33, 35, and 37, respectively)within the I/o commanddoubleword must be set to 1.2. The flagged event (byte count reducedto zero for the IZC flag, "channel end"condition for the ICE flag, or "unusualend" condition for the IUE flag) mustoccur.3. lOP may signal device controller to__ ~ __ !_"" ___.._" ... :""L_.. .a.IUI~v_,,_ .......:_:__ :_""_ ... _IIIICI'VtJl YYIIIIVVI "''''...... III1II1.I~ 1'11,,-,"1rupt flags, if:a. A connection address error isdetected.b. Any error is detected when lOP isaccessing an IOCD.For case a, no interrupt status wi II beset in response to an AIO.For case b, an IUE signal is sent backin response to an AIO.An I/O interrupt may also be requested bycertain devices via M modifier bits withinthe basic order for that device (see OperationalCommand Doublewords).A BP wi II respond to an interrupt requestfrom a particular I/O subsystem if (1) theI/O interrupt level (X I 5C') is armed, enabled,and not inhibited; and (2) that thereis no higher priority interrupt level in theactive or waiting state.Device Condition. If bits 1 and 2 are 00 (device"ready"), all device conditions required1,2(cont. )3for proper operation are satisfied. If bits 1and 2 are 01 (device "not operational"), theaddressed device has developed some conditionthat wi II not allow it to proceed; ineither case, operator intervention is usuallyrequired. If bits 1 and 2 are 10 (device "unavailable"), the device has more than onechannel of communication available and it isengaged in an operation controlled by a controllerother than the one specified by theI/O address. If bits 1 and 2 are 11 (device"busy "), the device has accepted a previous510 instruction and is already engaged in anI/O operation.Device Mode. If this bit is 1, the device isin the "automatic" mode; if this bit is a, thedevice is in the "manual" mode and requiresoperator intervention. This bit can be usedin conjunction with bits 1 and 2 to determinethe type of action required. For example,assume that a card reader is able to operate,but no cards are in the hopper. The cardreader would be in state 000 (device "ready",but manual intervention required), wherethe state is indicated by bits 1, 2, and 3 ofthe I/O status response. If the operator subsequentlyloads the card hopper and pressesthe card reader START switch, the readerwould advance to state 001 (device "ready"and in automatic operation). If the cardreader is in state 000 when an 510 instructionis executed, the 510 would be acceptedby the reader and the reader would advanceto state 110 (device "busy", but operator interventionrequired). Should the operatorthen place cards in the hopper and press theSTART switch, the card reader state wouldadvance to 111 (device II busy II and in "automatic"mode), and the input operation wouldproceed. Should the card reader subsequentlybecome empty (or the operator press theSTOP switch) and command chaining is beingused to read a number of cards, the cardreader would return to state 110. If the cardreader is in state 001 when an 510 instructionis executed, the reader advances tostate 111, and the input operation continuesas normal. Should the hopper subsequentlybecome empty (or should the operator pressthe card reader STOP switch) and commandchaining is being used to read a number ofcards, the reader would go to state 110 unti Ithe operator corrected the situation.For RMP, this bit is always set to one.Input/Output Instructions 131

Table 15. Device Status Byte (Register R or Ru 1)(510, no, and HIO only) (cont.)BitPosition45,67SignificanceUnusual End. If this bit is a 1, the previousI/o operation terminated in an " unusualend". Unusual end conditions occurfor various reasons that are unique to eachdevice (refer to applicable peripheral referencemanual for further details).Device Controller or lOP Condition. Thefunction of these two bits is dependent uponthe type of lOP (MIOP or RMP) addressed bythe I/o instruction.MIOP Operations: If bits 5 and 6 are 00(device controller "ready"), all devicecontroller conditions required for its properoperation are satisfied. If bits 5 and 6are 01 (device controller "not operational"),some condition has developed that does nota II ow it to operate properly. Operator i ntervention is usually required. If bits 5and 6 are 10 {device controller II unavailable"},the device controller is currentlyengaged in an operation controlled by anlOP other than the one addressed by theI/O instruction. If bits 5 and 6 are 11(device controller II busy"), the device controllerhas accepted a previous 510 instructionand is currently engaged in performingan operation for the addressed lOP.RMP Operations: If bits 5 and 6 are 00(lOP "ready"), all RMP conditions requiredfor its proper operation are satisfied. Ifbits 5 and 6 are 11 (lOP II busy"), thelOP has accepted a previous 510 instructionand is currently engaged in performingthat I/o operation. If bits 5 and 6are 01, the lOP is not operational. Ifbits 5 and 6 are 10, the lOP is in an undefined state.Reserved . To ensure program compati bi 1-ity with possible software and/or hardwareenhancements, it is recommendedthat this bit be treated as indeterminateand not used (i. e., masked).Table 16. Operational Status Byte (Register Ru1)BitPosition89SignificanceIncorrect Length. This bit is set to 1 if anincorrect length condition occurred withinthe responding subchannel. An incorrectlength condition is caused by a IIchannelend" (or end of record) condition occurringbefore the device controller has a "countdone" signal from the lOP (indicating thatthe byte count has been reduced to zero), oris caused by the device controller receivinga count done signal before channel end (orend of record): e. g., count done before80 columns have been read from a card.When set to a 1, the incorrect length bit,by itself, always signifies that an incorrectlength condition has occurred. If the SIL flag(bit 38 of the I/o command doubleword) iscoded with a 0, the detected incorrect lengthcondition is to be interpreted as an error condition.If the SIL flag is coded with a 1, thedetected. incorrect length condition is to beinterpreted as a nonerror condition. If an incorrectlength condition is to result in a devicehalt, the SIL flag must be coded witha 0 and the HTE flag (bit 36 of the I/o commanddoubl eword) must be coded wi th a 1.Transmission Data Error. This bit is set to 1if the device controller or lOP detected aparity error or data overrun in the transmittalinformation. A device halt occurs as aresult of a transmission data error only if theHTE flag of the I/o command doubleword iscoded with a 1.10 Transmission Memory Error. This bit is set to 1if a memory parity error was detected duringa data input/output operation. A device haltoccurs as a result of a transm:ss:on memoryerror only if the HTE flag of the I/O commanddoubleword is coded with a 1.11Memory Address Error. This bit is set to 1 ifa nonexistent memory address is detectedduring a chaining operation or a data input/output operation. This bit is cleared duringa successful 510 or HIO.12 lOP Memory Error. This bit is set to 1 if thelOP detects a memory parity error whilefetching a command. The bit is cleared dur-: ___ ~ .. ___ ~~.c .. 1 C'l" ~_ WI'"', III~ 1.1 ::IU\.o\.oC::I::IIUI ..JJ.V UI IIJ.V.13lOP Control Error. This bit is set to 1 if thelOP detects two successive Transfer in Channelcommands. The bit is cleared during asuccessful 510 or HIO.132 Input/Output Instru ctions

Table 16. Operational Status Byte (Register Ru 1) (cont.)Table 16. Operati onal Status Byte (Register Ru 1) (cont.)BitPositionSignificanceBitPositionSignificance14 lOP Halt. This bit is set to 1 Wan error conditionis detected which causes the lOP toissue a halt order to the addressed I/O device.Error conditions which may causean lOP halt (independent of the HTE flagwithin the I/O command doubleword) are:1. Bus check fault that occurs while fetching a command2. Control check fault3. Memory address error4. lOP memory error5. lOP control error14(cont.)Error conditions which may cause an lOP haltonly if the HTE flag is coded with a 1 are:1. Bus check fault that occurs while fetchingdata2. Transmission memory error3. Transmission data error4. Incorrect length condition occurringwhile the SIL flag is coded with a O.An lOP halt condition causes the currentoperation to terminate immediately as anII unusua I end ll •15 This bit is set to a 1 if a Write Lock Violation(WL V) occurs.Position and State in Register Ru 1Table 17. Status Response Bits for I/O InstructionsDevice Status ByteOperational Status ByteSignificance forSignificance0 1 2 3 4 5 t 6 t 7 8 9 10 11 12 13 14 15 SIO, HIO, and no for TDV1 - - - - - Tinterrupt pendi ng0 0 - - - - - - - device ready- 0 1 - - - - - - - - - - - - - device not operationali 0 - - - device unavai iabieI- 1 1 - - - - - - - - - - - - - device busy0 - - device manual- - - 1 - - - - - - - - - - - - device automatic1 - - - device unusual end controller0 0 device controller ready0 1 device controller not operational- 1 0 device controller unavailable1 1 - device controller busy- - - - - - - :jI~I::: - - - - - - - - reserved- - 1 - incorrect length- - 1 - transmission data error- - - - - - - - - - 1 - - - - - transmission memory errorunique to thedevice andthe device- - - - - - - - - - - 1 - - - - memory address error same as forSIO, HIO,1 - lOP memory error and no- - - - - - - - - - - - - 1 - - lOP control error- - - - - - - - - - - - - - 1 - lOP halt- - - - - - - - - - - - - - - 1 write lock violationtThe significance of bits 5 and 6 when response is from an RMP is as follows:Bit 5 . Bit 6-- --RMP Function0 0 RMP ready0 1 RMP not operational1 0 reserved1 1 RMP busyIInput/Output Instructions 133

POLP and POLR INSTRUCTIONSThe R field of these two instructions always specifiesa generalregister (including register 0) that may receive up to16 bits of fault status information from an addressed BP,RMP or MIOP. Each bit indicates the presence (l) or absence(O) of a specific fault condition within the polledprocessor (as listed in Table C-1). Note that the informationrepresented by a particular bit is also dependent uponthe type of processor polled (e. g., bit 18 may indicate amemory parity error in the BP or a control check faultwithin an MIOP).AlO INSTRUCTIONFor this instruction, if the R field has a value of 0, nostatus information is requested nor loaded. If the R fieldhas a value of X'l' through X'F', the specified register mayreceive one word of I/o information pertaining to an I/Ointerrupt.BitPositionTable 18. lOP Status Byte (cont.)Significance8 the byte count has been reduced to zero), or(cont.) is caused by the device controller receivinga count done signal before channel end (orend of record): e. g., count done before 80columns have been read from a card.When set to a I, the incorrect length bit, byitself, always signifies that an "incorrectlength" condition has occurred. If the SILflag (bit 38 of the I/O command doubleword)is coded with a 0, the detected incorrectlength condition is to be interpreted as anerror condition. If the SIL flag is coded witha 1, the detected incorrect length conditionis to be interpreted as anonerror condition.If an incorrect length condition is to result ina device halt, the SIL flag must be coded witha 0 and the HTE flag (bit 36 of the I/O commanddoubleword) must be coded with a 1.Device and Device Controller Status Byte. Bits 0-7 of thestatus word obtained by an AIO instruction from a respondingI/o subsystem are unique to the device and devicecontroller. These bits are described in the applicable peripheraldevice reference 'manual.9Transmission Data Error. This bit is set to 1if, since the last accepted SIO instructionaddressed to this subchannel, the device controlleror lOP detected a parity error or dataoverrun in the transmitted information. Adevice halt occurs as a result of a transmissiondata error only if the HTE flag of the I/Ocommand doubleword is coded with a 1.lOP Status Byte. Bits 8-15 indicate the presence (1) orabsence (0) of various operation errors and interrupts thatmay have occurred during an I/O operation. The functionsof individual bits within the lOP Status Byte are describedin Table 18.Table 19 is a summary description of the Device/DeviceController Status Byte and the lOP Status Byte.Bits 16-18. These bits of the AIO response are reserved.To ensure program compatibility with any enhancements(software and/or hardware), it is recommended that thesebits be treated as indeterminate and not used (i. e., masked).BitPositionTable 18. lOP Status ByteSignificance8 Incorrect Length. This bit is set to 1 if anincorrect length condition occurred withinthe responding subchannel. An incorrectlength condition is caused by a IIchannelend" (or end of record) condition occurringbefore the device controller has a "countdone" signal from the lOP (indicating that101112Zero Byte Count Interrupt. This bit is set to 1if the interrupt on zero byte count flag is 1and zero byte count is detected.Channel End Interrupt. This bit is set to 1 ifthe interrupt at channel end flag is 1 andIIchannel end ll is reported by the device tothe lOP.Unusual End Interrupt. This bit is set to 1 ifthe interrupt at unusual end flag is 1 and unusualend is reported by the device to thelOP, or if the lOP halt is signaled to the devicecontroller by the lOP.13 Write Lock Violation. This bit is set to 1 ifthe memory signaled a Write Lock Violationin the course of transmitting information fromthe device to the memory. If the HTE flagand the IUE flag are set, the operati on wi III terminate with an "l-'n'-'5'-'0! end".14 Reserved.15 Reserved.134 Input/Output Instructions

Table 19.Status Response Bits for AIO InstructionPosition and State in Register-RDevice Status ByteOperational Status Byteo 2 3 4 567 8 9 10 11 12 13 14 15 Significanceunique to the device andthe device controllerincorrect lengthtransmission data errorzero byte count interruptchannel end interruptunusual end interruptwrite lock violationreservedreservedI/O Address. Depending upon the type of device controllerresponding to the AIO instruction, the I/O addressmay be comprised either of a processor address and a singleunitdevice controller address or a processor address, amultiunit device controller address, and a device address.The subfields of the I/O address are described in Table 20.BitPositionTable 20. I/o Address (AIO Response)Significance18-20 This field contains the cluster address.21-23 This field contains the unit address.24-27 This field contains all ones.28-31 This field contains the device address.START INPUT/OUTPUT performs the following:1. Attempts to initiate an input or output operationwhetheran I/O operation is started or not is dependentupon conditions within the addressed I/o subsystem(see meanings of condition code settings).2. Specifies which lOP, channel, device controller, andinput/output device is to be selected (bits 18-31 ofthe effective virtual address of the instruction word).3. Specifies the address of the first command doublewordfor the subsequent I/O operation (bits 13-31 of generalregister 0).4. Specifies how much additional status information is tobe returned from the I/O system (R field, bits 8-11 ofinstruction word).SIDSTART INPUT/OUTPUT(Word index alignment, privileged)5. Specifies which general registers are to be loaded withthe requested status information (R field, bits 8-11, ofinstruction word).Instruction RegisterGeneral Register 06. Set MIOP in test mode by using device controller addressX'3P or X'7F'. Note that device controlleraddresses X'3F' and X'7F' are prohibited for normaloperation.General register 0 is temporari Iy dedicated during SIO instructionexecution and must contain the doubleword memoryaddress of the first command doubleword specifying theoperation to be started. The required address informationmust be in general register 0 when the SIO is executed.Input/Output Instructions 135

Status information for an S10 instruction isalways returnedvia condition code bits. Additional information may berequested and returned via the general registers as specifiedby the R field of the S10 instruction. However, thereturn of the additional information is dependent uponconditions encountered within the addressed I/O subsystem(see meanings of condition code settings).If the R field is coded with a 0, no additional status informationis requested.If the R field is coded with an odd value, one word ofstatus information is requested to be loaded into register R.The format of this information is as follows:If the R field is coded with an even (nonzero) value, twowords of status information are requested. The format ofinformation within register Ru1 is as shown above. Theformat of information within register R is as follows:These responses provide the program with information necessaryto determine the current status of the addressed I/osubsystem. The byte count field indicates the number ofbytes that are to be transmitted to or from memory in theoperation called for by the current command doubleword.The other fields are described in Tables 14-17.Affected: (R), (Ru1), CCThe meaning of the condition code bits during an SIO instructionis:2 3 4 Meaningo 0 0 0 I/O address recognized, S10 accepted, andstatus information in general registers iso 0ooocorre~t.o For RMP, I/O address recognized and S10accepted; however, status i nformati on ingeneral registers may be incorrect. ForMIOP, not possible.0 0 I/O address recognized, SIO not acceptedbecause device controller or device is busy,and status information in general registers iscorrect.o For RMP, I/O address recognized, SIO notaccepted because device controller or deviceis busy, and status information in generalregisters may be incorrect. For MIOP, notpossible.o Processor Interface detected parity error onreturned status and/or condition code. Theresult of the SIO is indeterminate.2 3 4 Meaningo 0 I/o address not recognized, SIO not accepted,and status information returned togeneral registers is incorrect.o No I/O address recognized and SIO abortedbecause an error detected when the lOP attemptedto read and transfer the _S10 parameters(device/device controller address, Rfield information, and first command doublewordaddress) from the BP to the lOP via mainmemory. Status information returned to generalregisters is incorrect.If CC4 = 1, the MIOP is in test mode and the meaning ofthe condition code during an SIO is:TID2 3 4 Meaningo 0oSet test mode is successful.Set test mode is successful, but a Bus CheckFault was detected.TEST INPUT/OUTPUT(Word index alignment, privileged)TEST INPUT/OUTPUT is used to make an inquiry on thestatus of data transmission. The operation of the selectedlOP, device controller, and device is not affected, andno operations are initiated or terminated by this instruction.The responses to no provide the program with the informationnecessary to determine the current status of the device,device controller, and lOP, the number of bytes remainingto be transmitted into or from main memory in the operation,and the present point at which the lOP is operating in thecommand list.If the R field of the no instruction is 0, no generalregisters are affected, but the condition code is set.If the R field of no is an odd value, the condition codeis set and the I/o status and byte count are loaded intoregister R as follows:If the R field of the no instruction is an even value andnot 0, the condition code is set, register Ru1 is loaded asshown above, and register R is loaded as follows:Refer to Tables 14 -17 for functions of individual bits withinstatus words.Affected: (R), (Ru1), CC136 Input/Output Instructions

If CC4 = 0, the MIOP is in a normal mode of operation andthe meaning of the condition code during a no is:TDVTEST DEVICE(Word index alignment, privileged)2 3 4 Meaning000o 0o 0oo I/O address recognized, acceptable SIO iscurrently possible, and status information ingeneral registers is correct.o For RMP, I/O address recognized, acceptableSIO is currently possible; however, statusinformation in the general registers may beincorrect. For MIOP, not possible.o I/o address recognized but acceptable SIOis not currently possible because device controlleror device is busy. Status informationin general registers is correct.o For RMP, I/O address recognized but acceptableSIO is not currently possible becausedevice controller or device is busy; statusinformation in general registers may be incorrect.For MIOP, not possible.TEST DEVICE is used to provide information about a deviceother than that obtainable by means of the no instruction.The operation of the selected lOP, device controller, anddevice is not affected, and no operations are initiated orterminated. The responses to TDV provide the program withinformation giving details on the condition of the selecteddevice, the number of bytes remaining to be transmitted inthe current operation, and the present point at which thelOP is operating in the command list.If the R field of the TDV instruction is 0, the conditioncode is set, but no general registers are affected.If the R field of TDV is an odd value, the condition codeis set and the device status and byte count are loaded intoregister R as follows:oo 0o Processor Interface detected parity error onreturned status and/or condition code. Theresult of the no is indeterminate.I/O address not recognized, no not accepted,and status information returned togeneral registers is incorrect .If the value of the R field of TDV is an even value andnot 0, the condition code is set, register Ru1 is loaded asshown above, and register R is loaded as follows:o..... 1_ T Ir. _...1...1__________ : __ ...1 __...I TTr. _L... __ ~_.J.'v 1./ '-' \,oiu ...... C;~ • C,"",~III~vU ..... I.U .... '"" ......,va ."""'"because an error detected when the lOP attemptedto read and transfer the no parameters(device/device controller address andR field information) from the BP to the lOP viamain memory. Status information returned togeneral registers is incorrect.If CC4 = 1, the MIOP is in the test mode and the meaningof the condition code during a no is:2 3 4 Meaning000o 0o 0Unit is performing an Order Out operation.Unit is performing an Order In operation.Unit is performing a Data Out operation.D_C __ ~_ ~L... __ ~_I: __ L...I~ ~""r:_L...""r_1 r""&",,ro ... _o .... ,.. ..... ,..1 &,..r""'''' 'v "'" "'"t't""""'"~'" t"'" 't""""~' ''', .... "" ... " .. ,-,,--, ''''description of Device Status Byte. Refer to Tables 16 and 17for functions of other bits within status words.Affected: (R), (Ru 1), CCIf CC4 = 0, the MIOP is in a normal mode of operation andthe meaning of the condition code during a TDV is:2 3 4 Meaningo 0 0 0 I/O address recognized, no device-dependentcondition present, and status information ingeneral registers is correct.o 0o For RMP, I/O address recognized and nodevice-dependent condition present; however,status information in general registers may beincorrect. For MIOP, not possible.oParity error detected by Processor Interfaceon returned status and/or condition code.The result of the no is indeterminate.oo 0I/O address recognized and device-dependentcondition is present or device controller is intest mode.oUnit is performing a Data In operation.BCF detected while unit performing a DataIn operati on.oo For RMP, I/o address recognized, devicedependentcondition is present, or device controlleris in test mode; but status informationin the general registers may be incorrect. ForMIOP, not possible.Input/Output Instructions 137

2 3 4 Meaningoo Processor Interface detected parity error onreturned status and/or condition code. Theresult of the TDY is indeterminate.If the R field of the HIO instruction is 0, the conditioncode is set, but no general registers are affected.If the R field is an odd value, the condition code is setand the following information is loaded into register R.o 0I/O address not recognized, TDY not accepted,and status information returned tothe general registers is incorrect.o No I/o address recognized and TDY abortedbecause an error detected when the lOP attemptedto read and transfer the TDY parameters(device/device controller address andR field information) from the BP to the lOPvia main memory. No status information returnedto general registers.If CC4 = 1, the MIOP is in the test mode and the meaningof the condition code during a TDY is:2 3 4 Meaning0 0 0 Unit is performing an Order Out operation.0 0 Unit is performing an Order In operation.HIO0 0 Unit is performing a Data Out operation.0 Parity error detected by Processor Interfaceon returned status and/or condition code. Theresult of the TDY is indeterminate.0 Unit is performing a Data In operation.BCF detected while unit performing a DataIn operati on.HAL T INPUT/OUTPUT0/Vord index alignment, t privileged)HALT INPUT/OUTPUT causes the addressed device to immediatelyhalt its current operation (perhaps improperly,in the case of magnetic tape units, when the device isforced to stop at other than an i nterrecord gap). If thedevice is in an interrupt-pending condition, the conditionis cleared.tWhen indexing operation code 4F instructions (HIO; RIO;POLP, POLR), the programmer must make certain that thesummation of the contents of the index register and the I/oaddress (bits 18-31 of the instruction word) does not affectbits 15-17. When indirect addressing is used, the contentsof the indirect address location (bits 15, 16, and 17) mustspecify the desired operation code extension.If the R field of HIO is an even value and not 0, thecondition code is set, register Ru 1 is loaded as shown above,and register R contains the following information.This information shows the status of the addressed I/O subsystemat the time of the halt. The byte count field showsthe number of bytes remaining to be transmitted to or frommemory. Other fields are described in Table 14-17.The HIO instruction must have zeros in bit positions 15, 16,and 17 to differentiate it from the RIO, POLP, and POLRinstructions, which also have X'4F' as an operation code(bits 1-7).Affected: (R), (Ru1), CCIf CC4 = 0, the MIOP is in a normal mode of operationand the meaning of the condition code during an HIOinstruction is:2 3 4 Meaningo 0 0 0 I/O address recognized, HIO accepted, devicecontroller not busy at time of HIO,and status information in general registers iscorrect.o 0 0 For R.MP, I/O address recognized, HIO ac=ooo 0cepted, and device controller not busy at timeof HIO; but status information ingeneral registersmay be correct. For MIOP, not possible.I/O address recognized, HIO accepted, anddevice controller busy at the time of the HIO,and status i nformati on is correct.o For RMP, I/O address recognized, HIO accepted,and device controller busy at the timeof the HIO; but the status information in thegeneral registers may be incorrect. For MIOP,not pO$5ible.o 0 0 Not possible.o 0 Processor Interface detected parity error onreturned status and/or condi ti on code. Theresult of the HIO is indeterminate.138 Input/Output Instructions

2 3 4 Meaningo 0 I/o address not recognized, HIO not accepted,and no status i nformati on returned togeneral registers.o No I/O address recognized and HIO abortedbecause an error detected when the lOP attemptedto read and transfer the HIO parameters(device/device controller address andR field information) from the BP to the lOP.No status information returned to generalregisters.If CC4 = 1, the MIOP is in the test mode and the meaningof the condition code during an HIO is:2 3 4 Meaningo 0 0 Unit is performing an Order Out operation.ooo 0ooUnit is performing an Order In operation.Unit is performing a Data Out operation.Processor Interface detected parity error onreturned status and/or condition code. Theresult of the HIO is indeterminate.Unit is performing a Data In operation.BCF detected while unit performing a DataIn operati on.RF~FT TNPIIT /()IITPIIT0N~~d i~de~ '~Iig~~e~i, t privileged)contains either a BP, MIOP, and/or-RMP). Unit addressesX 101_X 15 1 may be assigned to processors within the cluster.Unit address X'5 1 in cluster XIO I is reserved for the BP. Unitaddress X'6 1 is assigned always to the MI and unit addressX?I is assigned always to the PI for all clusters.Status information is returned only in the condition codebits. The R field is not used.Affected: CC1, CC2, CC3Condition code settings are as shown below:2 3 4 Meaningo 0 0 - I/O address recognized.POLPo -I/O address not recognized.POLL PROCESSOR(Word index alignment, t privileged)POLL PROCESSOR causes the addressed unit to return unitfau I t status in bi ts 16-31 of reg i ster Rtt. Th i s status i nformationis unit dependent (see Appendix C, Table C-1).In addition to the operation code of X'4F' I bits 15, 16,and 17 must be coded as 010, respectively.Affected: (R), CC1, CC2, CC~Condition Code settings are as shown below:RESET INPUT/OUTPUT causes the selected lOP to generatean I/O reset signal to all devices attached to it. In additionto the operation code X'4F', bits 15, 16, and 17 mustbe coded as 001, respectively.An RIO instruction resets the selected unit in the samemanner as ZCRIO on the operator's control console. However,unlike the control command, the RIO instructionresets only the addressed unit and may be controlled bythe executing program. Since the BP may be addressed asan lOP, it wi II accept an RIO instruction that causes theBP to reset itself in the same manner as ZCRBP. (Note thatthis procedure is not normal practice.)C luster addresses (CA), bit positions 18-20, may have valuesof XIOI_X?I. Cluster addresses X'0'-X ' 6 1 may be assignedto any cluster containing processors (i .e., BP, MIOP, and/or RMP). In a monoprocessor system, cluster address XIO Iis assi.gned to the c luster containing the basic processor(BP). Cluster address X?I is assigned only to the clustercontaining a system processor. If CA equals X?I I the UAfield is reserved. Unit addresses (UA), bit positions 21-23,may have values of XIOI_X?I. Unit addresses are requiredonly if the cluster address is X'0'_X '6 1 , (i.e., cluster2 3 4 Result of POLPo 0 0 - Processor fault interrupt not pending.o 0 - Processor fault interrupt pending.POLRo ~Unit address not recognized.POLL AND RESET PROCESSOR(Word index alignment, t privileged)POLL AND RESET PROCESSOR causes the selected unit toreturn unit fault status in bits 16 to 31 of register Rtt andresets the unit's fault status register. This status informationis unit dependent (see Appendix C, Table C-1).tSee footnote to HIO instruction.ttThis fault status is duplicated in bits 0 to 15 of register R.Input/Output Instru ctions 139

The POLR instruction also resets and clears this unit'sProcessor Fault Interrupt signal and the error status register.In addition to the operation code of X'4F', bits 15,16, and 17 must be coded as 011 , respectively.Affected: (R), CC1, CC2, CC3Condition code settings for the POLR instruction are:2 3 4 Result of POLRSome error conditi ons (e. g., parity error on reading commanddoubleword) will unconditionally cause an I/O interrupt.The various conditions which may result in an I/O interrupt,the coding of the corresponding control flags withinthe lOCO, and the bit position within the status word (returnedto register R) that indicates the presence (1) or absence(0) of that interrupt condition are listed below:ConditionControl FlagsCodingStatusBit Seto 0 0 - Processor fault interrupt not pending.Zero byte countIZC = 110o o -Processor fault interrupt pending.Channel endICE = 111o -Unit address not recognized.T~ansmission memory errorIUE = 1, HTE = 112AIDACKNOWLEDGE INPUT/OUTPUT INTERRUPT(Word index alignment, privileged)Write lock violationIncorrect lengthIUE = 1, HTE = 1IUE = 1, HTE = 1and SIL = 0128, 12ACKNOWLEDGE INPUT/OUTPUT INTERRUPT is used toacknowledge an input/output interrupt and to identify theI/O subsystem (processor, device controller, device) thatis causing the interrupt and why. If more than one I/osubsystem has an interrupt pending, only the subsystemwith the highest priority will respond to the AIO. Bits 18-23 of the effective virtual address of the AIO instruction(normally used to specify the cluster and unit addresses ofthe I/O address field) must be coded 000000 to specifythe standard I/O system interrupt acknowledgment (othercodings of these bits are reserved for use with special I/Osystems). The remainder of the I/o selection code field(bit positions 24-31) are not used in the standard I/O interruptacknowledgment (the address of the interrupt sourceis a part of the response from the standard I/O system tothe AIO instruction).Standard I/O interrupts are program controlled via the controlflags (IZC, ICE, IUE, HTE, and SIL) within the I/ocommand doublewords (lOCOs) that comprise the commandlist for the I/o operation. If a particular flag is coded asa 1 and if the corresponding condition occurs within theI/O operation, then an I/O interrupt is requested (e. g. , ifthe IZC flag is set to 1 and if the byte count for the I/Ooperation has been decremented to zero, then an I/Ointerrupt is requested by that I/o subsystem to indicate theend of that I/O operation; if the IZC flag is coded as a 0,no I/O interrupt is requested as a result of the byte countbei ng decremented to zero).If two or more flags are coded to ClJuse lJn !nterrupt for twoor more conditions, an interrupt is requested whenever anyof the IIflagged ll conditions is detected.For some conditions (transmission errors, incorrect length),two or more flags must be properly coded (see Chapter 4for further details on lOCOs).Memory address error IlOP memory error,lOP control error, ordevice connection addressparity errorT ransm i ssi on data errorUnusual endlOP halt) (no flag needed)IUE=l,HTE=lIUE = 1IUE = 1129, 121212, 14Interrupts may also be requested by certain I/O deviceswhen they execute specific orders (e. g., when a magnetictape unit executes a Rewind and Interrupt order). Referto the applicable peripheral reference manual for furtherdetails.When a device interrupt condition occurs, the lOP forwardsthe request to the interrupt system I/o interrupt level. Ifthis interrupt level is armed: enabled: and not inhibited;the BP eventually acknowledges the interrupt request andexecutes the XPSD instruction in main memory locationX ' 5C', which normally leads to the execution of an AIOi nstructi on.For the purpose of acknowledging standard I/O interrupts,the lOPs, device controllers, and devices are connected ina preestablished priority sequence that is customer-assignedand is independent of the physical locations of the portionsof the I/o system in a particular installation.If the R field of the AIO instruction is 0, the condition code;s set but the genera! iegistsi is not affected.If the R field of AIO is not 0, the condition code is set andregister R is loaded with the following information.140 Input/Output Instructions

The functions of bits within the DC status byte (which areunique to the device and device controller) are describedin applicable peripheral reference manuals. The functionsof other bits in the Ala _response word are described inTables 18, 19, and 20.The Ala instruction resets the interrupt request signal forthe I/O subsystem responding to the Ala (i.e., I/O subsystemidentified by bits 19-31 of register R).Affected: (R), CCIf CC4 = 0, the MIOP is operating in a normal mode ofoperation and thecondition code settings for Ala areshown below:2 3 4 Result of Alao 0 0 0 Normal interrupt recognized and reset.Status information in general register iscorrect.o 0 0 For RMP, normal interrupt recognized andreset; status information in the general registermay be incorrect. For MIOP, notpossible. Parity error on returned statusand/or condition code. The result of theAla is indeterminate.o 0 Processor interface detected.o 0 0 Unusual condition interrupt recognized andreset. Status information in general regisTel is (;orrecT.2 3 4 Result of Alao 0 For RMP, unusual condition interrupt recognizedand reset; status information in the generalregister may be incorrect. For MIOP,not possible.1 0 0 0 Interrupt recognized and reset. Status informationnot returned.o 0No I/O device requesting an interrupt andno status information returned to the generalregister.o Not possible.If CC4 = I, the MIOP is in the test mode and the meaningof the condition code during an Ala is:2 3 4 Meaning0 0 0 Unit is performing an Order Out operation.0 0 Unit is performing an Order In operation.0 0 Unit is performing a Data Out operation.0 Parity error detected by Processor Interface.0 Unit is performing a Data In operation.BCF detected while unit is performing a Datain operation.Input/Output Instructions 141

4. INPUT jOUTPUT OPERATIONSTo accommodate the variety and number of I/o devi ceswhich may be required for scientific and commercial applications,a Xerox 560 computer system may include the following:External Direct Input/Output (DIO) interface,Multiplexor Input/Output Processors (MIOPs), and RotatingMemory Processors (RMPs).more of the following types of device controllers may beconnected to an MIOP:1. Single-unit device controller {internal or external}.2. Multi-unit device controller {internal or external}."3. Unit-record controller {internal or external}.EXTERNAL DlO INTERFACEAn external DIO interface permits standard and speciallydesigned I/O devices to perform I/O operations (normallyin a real-time environment) that are controlled directly bythe basic processor (BP). Appropriate control signals andup to one word {32 bi ts} of data may be exchanged betweenthe BP and an addressed I/O device for each READ DIRECTor WRITE DIRECT instruction executed by the BP.During a WRITE DIRECT instruction (Mode 2 through F),the BP holds the control and data-lines stable until anacknowledgment signal is received from the addressed I/Odevice. During a READ DIRECT instruction (Mode 2through F), the BP holds the control lines stable until theaddressed I/o device furnishes the data accompanied withan acknowledgment signa/. Any delay encountered inreceiving the acknowledgment signal, for either READDIRECT or WRITE DIRECT instructions, does not have anadverse effect upon I/O operations being performed bythe MIOP or RMP systems.Refer to Xerox publication 90 09 73 {Interface DesignManual} for further detai Is pertaining to the external DIOinterface. Also, refer to appropriate peripheral referencemanuals for details on control and data signals.MULTIPLEXOR INPUT/OUTPUT PROCESSOR (MIOP)An MIOP permits standard and commercially available I/Odevices (e. g., card readers, card punches, magnetic tapeunits, etc.) to be controlled primari Iy by individual I/Osubchannels within the MIOP and associated device controllers.Depending upon the number of I/o subchannelsassigned (maximum of 16, as described under II Device Controllers"),an equivalent number of I/O operations may beperformed si mu I taneously.Generally, an internal device controller is physically connectedvia the internal I/o interface.An external device controller is located remotely to theMIOP and may require one or more separate chassis to accommodateit.A single-unit device controller {internal or external} isspecifically designed to control only one I/o device,usually a unit-record device such as a card reader, a cardpunch, or a line printer. Characteristics of a single-unitdevice controller are dependent upon the device controlled.(Refer to an appropriate peripheral reference manual forfurther information. )A multi -unit device controller (internal or external) isspecially designed to control more than one I/o device,where all the I/O devices are of the same type {e. g.,magnetic tape units or RADs}. However, only one I/odevice at a time may be actively involved in a data transferoperation. Characteristics of a multi-unit device controllerare dependent upon the I/O devices controlled. Forexample, a multi -unit device controller for magnetic tapeunits may control up to eight units. (Refer to an appropriateperipheral reference manual for further information.)Unit-record controllers {internal or external} are designedto control up to eight unit record type of I/O devi ces (e. g. ,card readers; card PlJnches; line printers). AI! I/o devicesattached to a unit-record controller need not be ofthe same type. All I/o devices attached to a unit-recordcontroller may perform separate I/O operations, includingdata transfers, si mu I taneously.The number of device controllers, as well as the number ofI/O devices, that may be connected to an MIOP is dependentupon the following considerations:1. The maximum number of I/O subchannels within anMIOP is 16.DEVICE CONTROLLERSAll I/O devices associated with an MIOP are connectedvia an appropriate device controller. Depending upon thenumber and type of I/o devices to be connected, one or2. Each single-unit device controller {internal or external}requires one I/o subchannel.3. Each multi-unit device controller (internal or external)requires one of the first eight subchannels withinthe MIOP.142 Input/Output Operati ons

4. Each unit-record controller (internal or external)requires one I/O subchannel per each unit record deviceattached, up to a maximum of eight.5. The maximum number of internal device controllerswithin an MIOP is eight (where a unit-record devicecontroller is equivalent to one, regardless of thenumber of assigned subchannels).6. Any I/O subchannel not assigned to an internal devicecontroller may be assigned to an external device controller.Thus, if an MIOP has no internal device controller,all 16 I/O subchannels may be assigned toexternal device controllers.ROTATING MEMORY PROCESSOR (RMP)Each RMP is a speci_al purpose, single-channel lOP designedto enhance high-speed data transfers between main memoryand anyone of up to eight disk units. Functionally, anRMP is comparable to an MIOP, except: (1) at any giventime, only one disk unit may be selected for a data transferoperation, . (2) data transfer rate of disk units are generallyhigher than data transfer rates of I/O devices attached toan MIOP, and (3) the device controller function is performedby the RMP, hence disk units are connected directlyto the RMP rather than via a device controller. (Note:Although only one disk unit may be actively transferdngdata at any given time, the other units may be active inperforming control functions, e. g., seeking).2. Depending upon various programming considerations,the command list may be contained within one or moreareas of memory and each area may be comprised ofone or more I/O command doublewords (IOCDs).3. Command list continuity between 10CDs relating to thesame logical record or to the same logical file may bespecified (see "Data Chain Flag" and "Command ChainFlag ll under II Operationa I 10CDs"). Command listcontinuity between portions of a command list locatedin different areas of main memory may be accomplishedby including a control 10CD within the command list(see "Transfer in Channel II under "Control 10CDs").4. Each 10CD is comprised of two words in contiguousmemory word locations. The first word must be storedin an even memory word location and the second wordmust be stored in the next consecutive (odd) memoryword location. Each IOCD is either an operationalIOCD or a control IOCD and contains coded parametersto define either a complete I/Ooperation or an integralportion of an I/Ooperation. (See "Operational IOCD"and IIControl IOCD" for further detai Is. )OPERATIONAL lOCOAn operational IOCD may contain up to five fields ofparameters, as required, to define either an entire I/o operationor an integral portion of an I/o operation._ Thegeneral format and description of parameters containedwithin an operational 10CD are as follows:iNPUT jOUTPUT PKOCESSOR liOfij FUNUAMENTAlSThis section contains general information, programming concepts,and definition of terms pertaining to I/O operationsperformed by Input/Output Processors (i. e., MIOP andRMP systems). The large variety of I/O devices which maybe used with these lOPs precludes a detailed or exhaustivedescription of features which are unique to each device.Likewise, a general reference "Refer to an appropriateXerox peripheral reference manual" is made rather thanciting specific manuals.Within this manual, the following terminology is used todifferentiate the hierarchy of control during an I/o operation:The BP executes instructions, the lOPs execute commands,and the device controller/device execute orders.COMMAND LISTEach I/O operation performed by an lOP must be definedby a command list. The characteristics and requirements ofa command list are as follows:1. It is normally created by a BP-executed programprior to the time that the defined I/o operation isinitiated. It must reside in main memory when the I/ooperation is initiated and subsequently executed.ORDERThis 8-bit field (bit positions 0-7), if required, may becoded to specify either an input or an output order that isexecuted by the device controller/device. General codingformats and functions of typical I/o orders are listed below:Bit Positiono 1 2 3 4 5 6 7 Order FunctionMMMMMM01MMMMMM10MMMMMM11MMMMOMMMM10000WriteReadControlSenseReadBackwardOutput operationInput operationOutput controlinformationInput control informationInput data, in reversesequenceRotating Memory Processor (RMP)/Input/Output Processor (lOP) Fundamentals 143

Orders that are executed by a specific type of device arelisted and described in the appropriate Xerox peripheralequi pment reference manua I.When an operational 10CD is fetched by the lOP, the contentof the order field, if required, is loaded into an orderregister within the device controller/device. If two ormore 10CDs are required to define a logical record (as describedunder "Data Chain Flag"), the order obtained fromthe first 10CD prevai Is for all subsequent 10CDs within thatlogical record and any orders contained within the subsequent10CDs are ignored.MEMORY BYTE ADDRESSThis 22-bit field (bit positions 10-31), if required, iscoded with the initial memory byte address for the I/o operationthat wi II be performed when the current 10CD isexecuted. When the 10CD is fetched by the lOP, the contentof the memory byte address field is loaded into amemory byte address register within the appropriate I/Osubchannel of the lOP. Thereafter, the content of thememory byte address register is incremented (or decrementedduring Read Backward operations) by one for each byte ofdata or information transmitted, even though access to mainmemory may be inhibited (as described under "Skip Flag")or the data is rejected by a memory unit (as described underItWrite Keylt).Depending upon the characteristics of the I/O device, thecontent of bit positions 10-31 may either be ignored (e. g.,HRewind" order for magnetic tape units) or specify memorybyte locations that contain supplemental control information(e. g., starting address for a disk seek operation). Refer toan appropriate Xerox peripheral equipment reference manualfor further detai Is.FLAGSEach operational IOCD contains eight control flogs (bifpositions 32-39). As described below, each control flagis coded to specify a particular control function that maybe performed by the lOP either during or at the end of thecurrent 10CD.Data Chain Flag (Bit Position 32). Coding of the data chainflag is dependent upon the number of 10CDs required todefi ne the data transfers for a logi ca I record. If two ormore 10CDs are required (e. g. , to perform a "gather-write"or a "scatter-read It operation), the data chain flag of eachoperational IOCD, except the last 10CD, must be coded asa i. The data chain fiag of the iast iOCD or the oniy10CD (if the record is defined by a single 10CD) is codedas O. If data chaining is specified and no error conditionsare encountered, the lOP wi II automatically fetch the nextoperational 10CD when the byte count (described later) ofthe current 10CD is reduced to zero. {Note: The lOP mayalso fetch and execute a control 10CD containing a Transferin Channel command, as described later, before fetchingthe next operational 10CD.) As a result of fetching thenext operational 10CD, all parameters, except the I/oorder, are updated and the device controller/device continueto operate as if the I/o operation were defined bya single 10CD (i. e., the data chain operation is transparentto the device controller/device). If data chaining is notspecified, the lOP wi II generate a "count done" signal whenthe byte count of the current 10CD is reduced to zero. The"count done ll signal indicates that the lOP has completedall data transfers for the current logical record. However,as described under II Interrupt on Channel End Flag ll , theI/o order is not completed until the device signals a IIchannelend".Interrupt at Zero Byte Count Flag (Bit Position 33). If anI/o interrupt is to be requested when the byte count of thecurrent 10CD is reduced to zero, the Interrupt at ZeroByte Count (IZC) flag must be coded as a 1. If the I/ointerrupt level within the interrupt system (location XISC')is armed, enabled, and not inhibited, the request will beprocessed by the BP in accordance with the priority thatprevai Is within the interrupt system, the lOPs, and the I/osubchannels within an MIOP. The occurrence of an I/ointerrupt because of a zero byte count condition is reportedas status information (bit position 10 of register R) when theBP executes an AIO instruction (normally part of the I/ointerrupt handling routine). The I/O interrupt request maybe processed without interfering with the I/o operation.(Note: An I/O interrupt may be requested at "channel end"or on "unusual end lt condition, as described later.)Command Chain Flag (Bit Position 34). Command chainingpermits an I/O device to execute a multiple number oforders relating to the same I/o operation in a consecutivemanner (e. g., when reading a multi-record file, the I/odevice may automatically receive a new Read order uponcompleting the current Read order without the BP executinganother SIO instruction). Command chaining, if required,is specified by coding the command chain flag asa 1 in the 10CD of each record, except the last.If command chaining is specified, the lOP wi II fetch thenext operational 10CD when the devi'ce signals a "channelend" unless terminated by an lIunusual end" condition. Asa result, new parameters are stored in the appropriateregisters within the I/O subchannel and a new I/O orderis received by the device controller/device.Thus, an lOP wi II automatically access main memory andfetch the next operational 10CD if either data chaining orcommand chaining is specified. If data chaining and commandchaining are both specified in the same commanddoubleword, a data chaining operation wi" be performed ifthe byte count is reduced to zero before the devi ce si gna Isa "channel end" and a command chaining operation will beperformed if a "channel end" occurs before the byte countis reduced to zero. If neither data chaining or commandchaining is specified, the I/o operation is completed whenthe device signals a "channel end". Note that commandchaining is inhibited by "unusual end".144 Input/Output Processor (IO P) Fundamenta Is

Interrupt at Channel End (Bit Position 35). An I/o interruptmay be requested when the device signals a "channelend" (signifying that the current order has been either completedor terminated) by coding the Interrupt at ChannelEnd (ICE) flag as a 1. If the I/O interrupt level within theinterrupt system (location X'5C) is armed, enabled, and notinhibited, the request wi II be processed by the BP in accordancewith the priority that prevai Is within the interruptsystem, the lOPs, and the I/O subchannels of the MIOP.The occurrence of an I/o interrupt because of a "channelend" is reported as status info.rmation (bit position 11 ofregister R) when the BP executes an AIO instruction (normallypart of the I/O interrupt-handling routine). The I/ointerrupt request may be processed without affecting theI/o operation. (Note: Specific conditions under which a"channel end ll signal may be generated are dependent uponthe characteristics of the device. Refer to an appropriateXerox peri pheral reference manua I for further detai Is. )Halt on Transmission Error Flag (Bit Position 36). The followingerrors (or lIunusual end ll condition) may be detectedby the MIOP when an 10CD is being executed:1. Bus check fault (BCF) whi Ie fetching data.2. Transmission Data Error (TDE); may also be detected bydevice controller.3. Transmission Memory Error (TME).4. Write Lock Violation 0NLV), during input operationsonly.5. Incorrect length, conditional; see IISuppress IncorrectLength Flag".6. Memory Interface Error (MIERR) whi Ie fetching data.If the HTE flag is coded as a 0, the above errors are recordedwhen detected and reported as status information when theBP executed an SIO, TIO, or HIO instruction, but the I/ooperation is not halted.If the HTE flag is coded as a 1, and any error (as listedabove) is detected, the I/O operation is terminated immediately.The error is also reported as status informationwhen the BP executes an SIO, HIO, or TIO instruction.The HTE flag must be coded identically in every 10CD associatedwith the same logical record. Thus, if data chainingis specified, the HTE flag in the new 10CD must be thesame as the HTE flag in the previous 10eD. This restrictionapplies to data chaining only, and not to command chaining.In addition to the "unusual end ll conditions listed above,which may terminate the I/O operation only if the HTEflag is coded as a 1, any of the following "unusual end llconditions wi II unconditionally terminate the I/O operation:1. Memory Address Error (MAE).2. lOP Control Error (IOPCE).3. Control Check Error (CCF).4. lOP Memory Error (IOPME).5. Bus Check Fault (BCF) whi Ie fetching an 10CD.6. Memory interface Error (MIE) whi Ie fetching an 10CD.Interrupt on Unusual End Flag (Bit Position 37). If an I/oInterrupt is to be requested when an "unusual end" conditionis detected while either fetching or executing an 10CD,the Interrupt on Unusual End (IUE) flag must be coded asa 1. If the I/O interrupt level within the interrupt system(location X'5C) is armed, enabled, and not inhibited, the requestwill be processed by the BP in accordance with thepriority that prevalis within the interrupt system, the lOPs,and the I/O subchannels within an MIOP. The occurrenceof an I/O interrupt because of an "unusual end" conditionis reported as status i nforma ti on (bi t posi ti on 12 of registerR) when the BP executes an AIO instruction (normallypart of an I/o interrupt-handling routine). The I/O interruptrequest may be processed wi thout affecti ng the progressof the I/O operation.If the IUE flag is coded as a 0, an "unusual end" conditionmay be detected but no interrupt will be requested.Suppress Incorrect Length Flag (Bit Position 38). An incorrectlength condition may occur when the specified bytecount is not equal to a fixed or prescribed byte count for arecord (e. g., attempting to read more than 80 columns ofdata from a punched card). Specific conditions under whichan incorrect length signal is generated are dependent uponthe device. Refer to an appropriate Xerox peripheral equipmentreference manua I for further detai Is.If the Suppress Incorrect Length (SIL) flag is coded as a °when an incorrect length condition is detected, it is reportedas an incorrect length and, depending upon the device,may be reported as an lIunusual end ll • If the HTE flagis also coded as a 1, the I/o operation is terminated andreported as an lIunusual end ll •If the SIL flag is coded as a 1 when an incorrect length conditionis detected, it is reported as an incorrect length butsuppressed as an lIunusual end ll • Hence, the I/O operationis not terminated.The presence or absence of an incorrect length conditionis reported as status information when the BP executes anSIO, HIO, AIO, or TIO instruction.Skip Flag (Bit Positi on 39). If the Skip (S) flag is coded asa 0, it has no effect upon the I/o operation.If the S flag is coded as a 1, the lOP is inhibited from accessingmain memory and consequently no data is transferredbetween the main memory and the data buffers of the I/osubchannel. All other operations or functions within theInput/Output Processor (lOP) Fundamentals 145

I/o subchannel (i. e., data transfers between the deviceand data buffers, updati ng the memory byte address andbyte count, and functions as specified by the control flags)are performed in a normal manner.For input operations, the Skip flag (in conjunction withdata chaining) provides the capabi lity to selectively readportions of a record.For output operations, the lOP wi II generate and transmitzeros (XIOOI) unti I the byte count is reduced to zero. Thus,for example, if the 10CD contains a Punch Binary order, abyte count of 120, and the S flag is coded as.a 1, a blankcard may be punched without accessing main memoryfor data.WRITE KEYThis four-bit field (bit positions 40-43), if required, maybe coded with an appropriate write key. During input operationsand providing the Skip control flag is coded as aD,the lOP will access main memory and furnish a memory unitwith up to four bytes of data or information accompaniedwith a four-bit write key. If the write key matches thepreassigned write lock for the memory word location accessed,or if either the key or lock has a value of 0000,the memory unit accepts and stores the information. If thewrite key does not match the write lock, and neither thekey nor the lock has a value of 0000, the memory unit rejectsthe information, does not disturb the previous content,and transmits a Write Lock Violation (WLV) signal to thelOP. The write key/write lock relationship is comparedevery time a memory word location is accessed for storingdata or information. (Note: The write key/write lock relationshipmay change during an input operation when thebyte address is incremented (or decremented) across a memorypage boundary. )As long as the write key matches the write lock for eachmemory word location accessed, or the value of either thelock or the key is 0000, the input operation is performedcs specified by the other parameters within this IOCD; orthe input operation is terminated by an "unusual end" conditionwhich can not be inhibited (i. e., memory addresserror, control check fault, or lOP memory error).If the HTE control flag is coded as a 1 when a WLV signalis received, the I/O operation is terminated immediately.If either the ICE or IUE control flag is coded as a 1, anI/O interrupt is requested.If the HTE control flag is coded as a ° when a WLV signalis received, the I/O operation continues i.n a normal manner,even though the data or information may be rejectedby a memory unit.When the lOP receives a WLV signal, the WLV bit withinthe status information register is set to 1 and remains setuntil a new I/o operation is initiated within this I/O subchannelby an SIO instruction. Thus, after the first WLVsignal has been recorded, subsequent WL.V signals have nofurther effect upon the WLV bit. The status of the WLVbit is reported when the BP executes an SIO, no, TDV,HIO, or AIO instruction.The contents of the write key field is not required and maybe ignoredwhen the write key/write lock memory protectionfeature is not operative (i. e., during any output operationor during any input operation, if the Skip control flag ofthe current 10CD is coded as a 1).BYTE COUNTThis 16-bit field (bit positions 48-63), if required, may becoded to specify the total number of data or informationbytes that are to be transmitted by the current 10CD.The minimum number of bytes is 1 and the maximum is65,356 bytes (16,384 words). When the 10CD is fetched,the content of the byte count field is loaded into a bytecount register within the appropriate I/o subchannel.Thereafter, the content of the byte count register is decrementedby one for each byte transmitted and then testedfor a zero byte count condition. (Note: As a consequenceof decrementing before testing for a zero byte count condition,an initial byte count value of a is interpreted as65,356 bytes.) Unless the I/O operation is terminated(e. g., as the result of detecting an "unusual end"), datais transmitted until the byte count is reduced to zero. Atany time, the progress of the I/o operation may be ascertainedby evaluating the current byte count which isfurnished as status information when the BP executes anSIO, no, HIO, or TDV instruction. {That is, current bytecount is equal to the number of bytes remaining to be transmittedand initial byte count minus current byte count isequal to the number of bytes transmitted.} When the bytecount is reduced to zero, the MIOP may perform the followingfunctions:1. Transmit a "count done" signal to the device controller/device if data chaining is not specified.2. Request an I/o interrupt, if the IZC flag is codedas a i.3. Fetch the next IOCD, if the data chain flag is codedas a 1.Depending upon the characteristics of the I/o device,certain I/o orders (e. g., Rewind for magnetic tape units)may not require a byte count field. In such case, the bytecount fie Id is ignored. Refer to an appropriate Xerox peripheralequipment reference manual for further detai Is.CONTROL lOCOA control IOCD may contain either a Transfer in Channelor a Stop command.146 Input/Output Processor (lOP) Fundamentals

Transfer in Channel. A control lOCO containing a Transferin Channe I command has the fo Ilowi ng format:LocationsOescri pti on of CommandA +6, A + 7 Transfer in Channel to location A +4.A+8,A+9StopThe Transfer in Channel command is executed within thelOP and has no direct effect on any of the I/o elementsexternal to the addressed lOP. The primary purpose of thiscommand is to permit branching within the command list(i. e., fetching the next operational lOCO from a pair ofmemory word locations other than the next two consecutiveword I ocati ons).When the lOP executes the Transfer in Channel command,it loads the command address register of the appropriateI/o subchannel with the contents of bit positions 13-31(the "next command doubleword address" field), fetchesand loads the new operational 10CD into appropriate registerswithin the I/O subchannel and order register withinthe device controller/device (unless data chaining is specified),and then executes the new lOCO. (Bit positions8-12 and 32-61 are ignored and should be coded aszeros. )If data chaining or command chaining is specified in thelOCO preceding the lOCO containing a Transfer in Channelcommand, the chaining flags are not significant to noraltered by the Transfer in Channel command.When used in conjunction with command chaining, Transferin Channel command faci litates the control of devi ces suchas unbuffered card punches or unbuffered line printers. Forexample, assume that it is desired to present the same cardimage twelve times to an unbuffered card punch. The punchcounts the number of times that a record is presented to itand automatically generates a "chain modifier" signal whentwelve rows have been pu·nched. The command addressregister within the I/o subchannel is incremented by twoby the "chain modifier" signal and the next consecutivelOCO within the command list is skipped over (not fetchedor executed). A command list for punching two cards mightbe as shown in the following example:The Transfer in Channel command can be used also in conjunctionwith data chaining. As one example, considera situation often encountered in data acquisition applications,where data is transmitted in extremely long, contiguousstreams. In this case, the data can be storedalternately in two or more buffer storage areas so thatcomputer processing can be carried out on the data in onebuffer whi Ie additional data is being input into the otherbuffer. The command list for such an application might beshown in the following example:LocationsOescri pti on of CommandB, B + 1 Read data, store in buffer 1, data chain.B+2, B+3Store into buffer 2, data chain.B+4, B+5 Transfer in Channel to location B.If the lOP encounters two successive Transfer in Channelcommands, an lOP control error (IOPCE) occurs and theI/O operation is terminated immediately. An 10PCE isreported as status information (bit 13 of register Rul) whenthe BP executes an SIO, HIO, no, or TOV instruction.STOPA control lOCO with a Stop command has the followingformat:LocationsDescription of CommandA, A + 1 Punch row for card 1, command chain.A + 2, A + 3 Transfer in Channe I to locati on A.A +4, A +5Punch row for card 2, command chain.The Stop command causes certain devices to stop, generatea "channel end II signal, and also request an I/o interruptif bit 0 in the lOCO is coded as a 1. If the I/O interruptInput/Output Processor (lOP) Fundamentals 147

level within the interrupt system (location X'5C) is armed,enabled, and not inhibited, the request wi II be processedby the BP in accordance with the priority that prevailswithin the interrupt system, the lOPs, and the I/O subchannelswithin an MIOP. The occurrence of an I/Ointerrupt because of a Stop command is reported as statusinformation (bit position 7 of register R) when the BPexecutes an AIO instruction (normally part of an I/Ohandling routine).Bi t posi ti ons 1-7 must be coded as zeros. Bi t posi ti ons 8-31and 40-63 are ignored; but it is recommended that they alsobe coded as zeros. Bit positions 32-39 are devi ce dependentand must be coded as specified in the appropriate peripheralreference manual.The Stop command is primari Iy used to terminate a commandchain for an unbuffered device, as illustrated in the firstexample given for the Transfer in Channel command. Notethat not all devices recognize the Stop order.I/O OPERATION PHASESThis section describes the genera I sequence of events (orphases) of any I/O operati on performed by an lOP, thefunction performed by the BP, lOP, and device controller/device during each phase, and a description of each typeof I/O operation including the applicability of parametersthat may be contained within a typical operational lOCO.For explanation purposes, each I/O operation has five majorphases: preparation, initiation, fetching, executing,and termination phase. Each phase is further describedbelow.PREPARATION PHASEBefore an I/O operation may be performed by an lOP, anappropriate command list must reside in main memory.INITIATION PHASEAssuming that an appropriate command list resides in mainmemory, an I/O operation is initiated only if the BP executesan SIO instruction that is accepted by the addressedlOP, device controller, and device. The acceptance orrejection of an SIO instruction is contingent upon conditionswithin the addressed lOP, device controller, anddevice and is indicated by the condition codes at the compietionof the SIO instruction. in either case, the BP isable to perform other instructions or tasks immediately afterexecuting an S10 instruction. (Refer to "SIO" instruction,Chapter 3, for further detai Is. )A successfu I 510 i nstructi on causes the addressed devi ce togo from the "ready" condition to the "busy" condition.FETCHING PHASEAlthough the services of the BP are not required duringthis phase, the BP may at any time execute either a TIO,TDV, or POL instruction without interfering with the I/Ooperation. However, excessive TIOs and TDVs may causea data overrun condition. The BP may also execute eitheran HIO or RIO instruction and stop the I/O operation. (AnHIO may leave the device in an unpredictable state; anRIO resets all controllers and devices on the addressed lOP. )As a result of accepting an SIO instruction, a command addressregister within the I/o subchannel (assigned to controlthe addressed device controller/device) is loaded withthe first command doubleword address, the content of GeneralRegister 0 when the 510 instruction is accepted. Atthe appropriate time, as determined by the priority, thedevice controller/device wi II request that the lOP accessmain memory and fetch the first word of the lOCO from aneven memory word location and increment the commandaddress register by one. The disposition of the first wordis dependent upon the contents of the first word.If the order field contains an I/o order for a devicecontroller/device, the content of the order field is eitherloaded into an order register within the appropriate devicecontroller/device or ignored (if the lOCO is being fetchedfor a data chained operation). If the order is a Read Backwardorder, a control flag is also set within the lOP whichallows the memory byte address to be decremented ratherthan incremented during the data transfer.For all orders (excluding the Transfer in Channel command,described below), the contents of bit positions 10-31 of thefirst word is loaded into a memory byte address register ofan appropriate I/o subchannel. Depending upon the I/Oorder, as described under "Execution Phase", the content ofthe memory byte address register may be used or ignored. Ifused, it specifies which memory word location is to be accessedand also the number of bytes of data {or control information}to be transferred into or out of that location.If the order field contains a Transfer in Channel command,it is recognized and executed immediately by the lOP. Thecontent of bit positions 13=31 (designated as,the IInext com-=mand doubleword address" field) is loaded directly into thecommand address register. The Transfer in Channel commandis recognized and executed by the lOP, it is fetchedand executed as the result of fetching one word (rather thantwo), and it is transparent to the device controller/device(that is, it is executed without affecting the continuity ofan order that is data chained or an I/o operation that iscommand chained). Note: Although bit positions 0-3and 8-12 are currently ignored, it is recommended that theybe coded as zeros.Immediately after executing a Transfer in Channel command,the iOP wiii automaticaiiy fetch the first word or the nextlOCO as specified by the contents of the "next commanddoublewordaddress" field. If the order field ofthe next lOCOalso contains a Transfer in Channel command, the I/o operationis terminated immediately and the lOP enters a Halt statebecause an lOP control error (IOPCE) occurred (attemptingto execute two successive Transfer in Channel commands).148 I/O Operation Phases

Otherwise, the first word of the next lOCO is fetched andloaded as described above, and the second word is fetchedand loaded as described below.Since the Transfer in Channel command permits lOCOs tobe fetched from nonconsecutive locations, lOCOs containingTransfer in Channel commands may be included withina command list either to achieve command list continuityfrom one segment of a command list to another segment orto c?nstruct reiterative loops.For all lOCOs, except a control lOCO containing a Transferin Channel command, the lOP will automatically accessmain memory at the appropriate time, as determined by thepriority that prevails for accessing main memory, and fetchthe second word of the lOCO from the next consecutiveascending (odd) memory word location of the command listand increment the command address register by one. Thus,in all cases, after a fetching operation is completed, thecontent of the command address register wi II be an even(or doubleword) address.The contents of the second word are stored in appropriateregisters within the I/O subchannel. Depending upon theI/o order, as described under IIExecution Phase ll , the contentsof the various fields are either used or ignored.In addition to the lOP Control Error (IOPCE), the followingtypes of lIunusual end ll conditions may be detected duringthe fetching phase of an I/O operation: Memory AddressError (MAE), Control Check Fault (CCF), lOP Memory Error(IOPME), Bus Check Fault (BCF), and Memory InterfaceError (MIE). The detection of any of these errors causes theI/O operation to be terminated and if the IUE flag is set toa 1, an "unusual end" interrupt is requested.Depending upon the control function performed, certainControl orders may be a part of an I/o operationwhich may be continued after the Control order isexecuted. For example, an I/o operation involvinga magnetic tape unit may contain a Rewind order toreposition the tape prior to reading (or writing) one ormore records.Note: Within the context of the above explanation,the Control order is defined to be one thatdoes not transfer any information; thus, datachaining is precluded within the lOCO containingthe Control order; however, commandchaining may be specified. Control orders thatinvolve information transfers when executedare described below (see paragraphs 2 and 4).2. If the order specifies an input operation (e. g., Read,Read Backward, or Sense) and the Skip flag is codedas a 0, all parameters of the current lOCO may beapplicable. As a result of receiving an appropriateinput order, the devi ce transmits data (Read, or ReadBackward order) or information from special registers(Sense order) into data buffers of the associated I/Osubchannel within the lOP.Depending upon the priority that prevai Is for accessingmain memory, the lOP accesses a memory word location(as specified by the current memory byte address),transfers up to four bytes of data or i nformati on fromthe data buffers to a memory unit, provides a writekey, and increments (or decrements, if Read Backward",,.,.10,.' _._-'J +ho ...- ... mom",r" _..._., -,.- h.,+o ,..",1,.1roc:" --_._-- nn,.l -..- ,.Iorromon+c: --_._..._.. -- +ho ----byte count by one for each byte transferred out of thedata buffers.EXECUTION PHASEAlthough the services of the BP are not required duringthis phase, the BP may at any time execute either a TIO,TDV, or POL instruction without interfering with the I/ooperation. However, excessive testing may cause a dataoverrun condition. The BP may also execute either anHIO or P.IO instruction and stop the I/o operation. Afterthe second word of an lOCO is fetched and providing nolIunusual end ll condition was detected, the lOCO is executedas prescribed by the parameters contained therein. As afunction of the order and the status of the Skip flag, ifapplicable, an lOCO may be executed in one of five ways,as described below:1. Certain Control orders (e. g., Stop) may be executedby the device whi Ie the lOP monitors the operation inaccordance with the applicable control flags. Sinceno memory accesses and data (or information) transfersoccur, the contents of the memory byte address register,write key register, and byte count register maybe ignored. Other Control orders (e. g., Rewind for amagnetic tape unit) are listed and described in applicableXerox peripheral equipment reference manuals.The write key is evaluated against the preassignedwrite lock for the memory word location accessed.If the write key is valid for each memory word locationaccessed, the input operation continues, as describedabove, unti I it is completed or terminatedby an "unusual end" condition, other than Write LockViolation. If the write key is not valid, the memoryunit (1) generates and transmits a Write Lock Violation(WLV) signal to the lOP, (2) rejects the new data,and (3) does not disturb the previous contents of thememory word location accessed.If the write key is invalid for any memory word locationaccessed and the HTE flag is coded as a 1, the inputoperation is terminated immediately upon receipt of aWLV signal (see "Termination Phase ll ).If the HTE flag is coded as a 0, the memory unit mayaccept or reject the data or information, based on thewrite key/write lock evaluation for each memory wordlocation accessed, without affecting the operationswithin the lOP, device controller, or device. Theinput operation continues unti I either completed orterminated by an "unusual end" condition, other thana Write Lock Violation.I/O Operation Phases 149

Note: Since the same write key prevai Is for the entirelOCO and all memory locations within a memorypage are assigned the same write lock, thewrite key/write lock relationship may changewhen the memory byte address is incremented(or decremented) across a memory page boundary.3. If the order specifies an input operation (e. g., Read,Read Backward, or Sense) and the Skip flag is codedas a 1, all parameters within the 10CD, except thewrite key, may be applicable. As a result of receivingan appropriate input order, the device transmits data(Read or Read Backward order) or information fromspecial registers (Sense order) into the data bufferswithin the I/o subchannel of the lOP. Because theSkip flag is coded as a 1, the lOP can not access mainmemory (the write key may be ignored and a Write LockViolation can not occur). Although the data can notbe stored in the main memory, the lOP increments thememory byte address (except during a Read Backwardorder, when it is decremented) and decrements the bytecount by one for each byte transferred out of the databuffers. The device may continue to transmit data intothe data buffers and the lOP may continue to updatethe memory byte address and byte count unti I the currentorder is either completed in a normal manner orterminated because of an "unusual end" condition(other than a Write Lock Violation).4. If the order specifies an output operation (e. g., Writeor Control) and if the Skip flag is coded as a 0, allparameters within the 10CD, except the write key,may be applicable. When transferring data (Writeorder) or i nformati on (Contro I order) out of mai nmemory, the write key/write lock checking is notperformed; hence, the write key may be ignored.Likewise, a Write Lock Violation will not occur. Foran output operation, the lOP wi II access main memory(in accordance with the priority that prevai Is for accessingmain memory) and transfer up to four bytes ofdata (or information), as specified by the current memorybyte address, to the data buffers of the appropri ateI/O subchannel. The lOP also increments the memorybyte address and decrements the byte count by one foreach byte of data transferred. Data is then transferredfrom the data buffers to the devi ceo The lOP may continueto access main memory, transfer up to four bytesof data from main memory to the appropriate data buffers,and update the memory byte address and bytecount. The devi ce continues to output data unti I theorder is either completed in a normal manner or terminatedbecause of an lIunusual end" condition.5. If the order specifies an output operation (e. g., Writeor Control) and if the Skip flag is coded as a 1, allparameters \A,'itn:r. the current !OCD, except the \¥ritekey, may be applicable. Because the Skip flag iscoded as a 1, the lOP can not access main memory forany data {or information}. Instead, the lOP generatesand loads zeros (XIOOI) into the data buffers of theappropriate I/O subchannel and increments the memorybyte address and decrements the byte count by one foreach byte loaded. The zeros are then transferred fromthe data buffer to the devi ceo The lOP may continueto generate and load zeros into the data buffers andupdate the memory byte address and byte count, accordingly,and the device may continue to output zerosunti I the order is either completed in a normal manneror terminated because of an "unusual end ll condition.DATA CHAININGAn order may be continued from the current operational10CD to the next operational 10CD, if data chaining isspecified in the current 10CD. In this case, the lOP wi IIautomatically fetch the next operational 10CD, asdescribedunder "Fetching Phase", when the byte count of the current10CD is reduced to zero. In the process of fetching thenext operational 10CD, the lOP may fetch and execute acontrol lOCO containing a Transfer in Channel commandwithout affecting the continuity of the order. The processof fetching and loading the next operational 10CD into thecontrol registers of the I/o subchannel is transparent to thedevice. That is, the device continues to operate as if theorder were defined by a single 10CD. Also, any changesin the status of the Skip flag or in the write key from one10CD to the next is transparent to the device. The devicecontinues to receive zeros, data, or information from thedata buffers during an output operation, or continues totransmit data (or information) into the data buffers regardlessof whether it is subsequently rejected or stored whi Ie performingan input operation.During the execution phase, an I/O interrupt may be requestedeach time the byte count of an operational 10CDis reduced to zero if the Interrupt at Zero Byte Count (IZC)flag is coded as a 1. Thus, if data chaining is specified,the lOP may request an I/O interrupt without interferingwith the process of fetching the next operational IOCD.If the I/o interrupt level (location X I 5C') within the interruptsystem is armed, enabled, and not inhibited, the I/ointerrupt may be processed by the BP in accordance withthe priority that prevai Is within the interrupt system, thelOPs, and the device controllers connected to the lOP.The order may be completed in a normal manner when theData Chain flag of the current IOCD (the last 10CD of alogical record) is coded as a O.COMMAND CHAININGAn I/o operation may be continued from the current lOCOto the next 10CD if command chaining is specified in thecurrent !OCD. Command chaining is commonly specifiedwhen reading (or writing) consecutive records of data fromthe same file. In which case, the current 10CD must bethe last lOCO for the current record and the next 10CDmust be the first 10CD of the next logical record. Althoughthe device may execute the same functional order for bothrecords, logically, it is equivalent to two separate orders.150 I/O Operation Phases

Depending upon the characteristics of the device, commandchaining may also be used to perform different operationson either different but consecutive records or upon the samerecord {e. g., a magnetic tape unit may be programmed toalternately read or write consecutive records or to read thesame record backwards after writing}. Refer to an appropriateXerox peripheral equipment reference manual forfurther detai Is.If command chaining is specified, the device controllercauses the lOP to fetch the next operational lOCO, as describedunder "Fetching Phase", when the device signals"channel end" (signifying that it is ready to accept andexecute another order). In the process of fetching the nextoperational lOCO, the lOP may fetch and execute a controllOCO containing a Transfer in Channel command withoutaffecting the continuity of the I/O operation {i. e. ,transparent to the device controller/device}; however, thefetching of the next operational lOCO is not transparentto the device controller/device. The process of automaticallyfetching the next operational lOCO because datachaining and/or command chaining is specified in the currentlOCO permits an I/o operation to continue normallyunti I an lOCO is executed in which both chaining flagsare coded as zeros (the last lOCO of the last record).If data chaining and command chaining are both specifiedwithin an lOCO, data chaining is performed if the bytecount of the current lOCO is reduced to zero before thedevice generates "channel end"; command chaining is performedif the device generates "channel end" before thebyte count is reduced to zero.During the execution phase, an I/O interrupt may also berequested each time a "channel end" occurs if the Interruptat Channel End {ICE} flag is coded as a 1. Thus, if commandchaining is specified, the lOP may request an I/ointerrupt without interfering with the process of fetchingthe next operational lOCO.TERMINATION PHASEAn I/O operation may be terminated in one of the followingmanners:1. Aborted at any time because the BP executed eitheran HIO or RIO instruction.2. Aborted when an unconditional"unusual end" conditionwas detected.3. Aborted when a conditional "unusual end" conditionwas detected whi Ie the HTE control flag was codedas a 1.4. Completed as specified by the command list but withan "unusual end" condition.5. Completed as specifi ed by the command list.6. Aborted whenever a SUPER RESET, SYSTEM RESET,or I/o RESET command is entered from the System ControlConsole (SCC).The progress of an I/O operation, including the termination,may be ascertained by evaluating the status informationreturned for I/O instructions, as described in Chapter 3.Depending upon programming considerations, these I/Oinstructions may be executed either singly or as part of anI/o handling routine and either imperatively at logicalpoi nts of a BP-executed program or on an II as needed llbasis when an I/O interrupt is requested by an lOP or devicecontroller. Normally, an I/o interrupt is requestedwhenever a critical or significant event occurs within anyI/o subchannel, device controller, or device. Typically,an I/O interrupt may be requested when the byte count ofany lOCO is reduced to zero, whenever any device detectsa "channel end ll condition, or when the lOP or any devicecontroller detects an lIunusual end" condition, providingthe appropriate control flag (IZC, ICE, and IUE) is codedas a 1.Note: An I/O interrupt may also be requested by certaindevices, e. g., a magnetic tape unit may be ableto execute a Rewind and Interrupt order and otherdevices may request an I/O interrupt when executinga Stop order in which bit 0 is coded as a 1.Refer to an appropriate Xerox peripheral referencemanual for further detai Is.Once an I/O interrupt request has been made by.a device,that device, device controller, and I/o subchannel remainin an interrupt pending condition unti I the interrupt requestis acknowledged, reset, or cleared.Normally, an I/O interrupt request is acknowledged bythe BP executing an AIO instruction, as part of an I/Ointerrupt-handling routine; reset by the BP executing eitheran HIO or an RIO instruction; or for certain devices clearedautomatically, as a function of time. Refer to an appropriateXerox peripheral equipment reference manual forfurther detai Is. )Since a multiple number of I/O interrupt requests may prevailsimultaneously {one per each de vi ce controller} andall requests are serviced by a common I/O interrupt level(location X'5C), the BP normally acknowledges an I/Ointerrupt request based on the priority that prevai Is withinthe interrupt system, the lOPs, and the I/O subchannelswithin an MIOP, if applicable. An interrupt pending conditionprevents a new I/O operation from being initiatedby an SIO instruction on a particular subchannel but doesnot affect the current I/O operation. (That is, if an I/Ointerrupt was requested as the result of a zero byte count orII channel end" condition, and data chaining or commandchaining is specified, the I/O operation may continue asspecified by the command list.)I/O Operation Phases 151

5. OPERATIONAL CONTROLEXTERNAL CONTROL SUBSYSTEMThe External Control Subsystem (ECS)isa group of elementsused in this computer system that provide operational anddiagnostic interfaces to control and maintain system hardwareand software.CENTRALIZED SYSTEM CONTROLIn many other computer systems II software-I evel II operatorinteracti ons are transacted through an operator's teletypewriterconsole while hardware level interactions are performedthrough a fixed panel of lamps and switches. Incontrast, this Xerox computer system consolidates these interactionsand controls into a console telecommunicationsdevice, designated as the System Control Console (Scq.Through the SCC, the operator has a siAgle control pointfor all normal system control activities.A Remote Diagnostic Interface (RDI) permits the localSystem Control Consol e to be augmented wi th a RemoteConsol e that may have the some degree of system control.(Usage of the RDI and Remote Console as a RemoteAssist feature is described below, under II Remote Console".)A System Control Panel (SCP) contains' indicators and basiccontrol s that the operator may use duri ng system startup orto establ ish connections with the remote location.CONTROL CONSOLE DEVICESThe ECS provides an interface for two local (primary andalternate) communications consoles and a data set interfacefor remote diagnostic connection. Each communicationsconsole must have an EIA RS232 voltage interfaceand format characters in even parity ASCII code with controlprotocols of a Model 4691 KSR 35 Keyboard/Printer.Allowed communications rates are 10 and 30 characters persecond.PRIMARY CONSOLEThe primary console always has the functional capabil ity ofthe System Control Console to communicate with softwarethrough I/O subchannel address X'Ol'. The communicationsrate of the primary console is either 120 characters perSecond or the same as the alternate end remote consolesdepending on the setting of the FSELA switch on the ConfigurationControl Panel (see Chapter 6). If the REMOTECHANNEL switch on the System Control Panel is in theSCC position (implying a remote diagnostic connection),the remote channel frequency is automatically enforced onthe primary console.REMOTE CHANNELThe alternate and remote consoles share the same data paths.Both consoles receive the some output; either one of theconsoles is selected for input by the ALTSEL switch on theConfiguration Control Panel. The communications ratesof 10 or 30 characters per second are selected for both consolesby the FSELBO and FSELB 1 switches on the ConfigurationControl Panel. Both consoles may function eitherstrictly as I/O devices or as parallel System Control Consolesselected by the REMOTE CHANNEL switch on theSystem Control Panel. Description of communications rateselection is found in Chapter 6.ALTERNATE CONSOLEThe alternate console normally functions as an output deviceresiding at I/o subchannel address X'OB'. This consolecan create an edited system log, whi Ie the operator'sconsole functions at a higher communications rate. (REMOTE CHANNEL and ALTSEL switches are both OFF.)If the primary console fai Is, the alternate console mayfunction as the System Control Console. In this case, theremote console connection is only inhibited by the operatorat the data set. (REMOTE CHANNEL switch inSCC position; ALTSEL switch in ON position.)REMOTE CONSOLEBefore the remote device can gain access to the RemoteDiagnostic Interface (RDI), the operator must manually interveneto establish the connection at the data set and theSystem Control Panel. The data set (Bell 103A or equivalent)connection is inhibited while the REMOTE CHANNELswitch is in the OFF position.The remote console may run on-line diagnostics while therest of the system performs non-maintenance work. In thiscase, the remote console preempts I/O subchannel X'OB'and the alternate (local) console creates a log of the onlinemainentance if not turned off. The remote devicedoes not have access to the SCC hardware controls, butmay enter software-level control information through theI/o system (REMOTE CHANNEL switch in I/o position,ALTSEL switch in OFF position).If the entire system is under the discretionary control of remotemaintenance personnel, the operator may connect theremote console to the RDI as the System Control Console.The remote console is then connected logically in parallel;and assumes all the functional capabi lity of the primary console,and shares I/O subchannel X'Ol'. (Note that conventionsmust be established to ensure that the primary andremote consoles do not generate overlapping input.) Theremote console communications rate is automatically imposedon the primary console and the operator may have to152 Operational Control

change the rate on the primary console to retain parallelcontrol. The alternate {local) device creates a log of allSCC transactions. The normal (log) output on I/O subchannelX'OB' is suspended for the duration of the SCCassignment to the remote channel (REMOTE CHANNELswitch in SCC position; ALTSEL switch in OFF position).CONTROL COMMANDSA set of commands and display formats implements operatorcommunication with hardware through the System ControlConsole. These hardware-control commands, called II SCCFunctions ll , are independent, direct hardware controls asdistinguished from the software-level operating controlsactivated from the SCC through the normal I/o system. Aspecial micro-processor, working independently of theBP, senses and controls the execution of SCC functions.The flexibility of character-oriented communications equipmentand micro-programmed control significantly enhancemany system operating and diagnostic features.The basic command format provides a four-level interlockon critical system controls by requiring a correct fourcharactersequence to initiate a command action. In addition,context analysis is provided to assure that commandsare executed only in appropriate system states. Thisbasic format requires that each command is preceded by theIIcontrol-Z II character (control and Z keys depressed simultaneously).Note that within this text, the control-Z characteris represented wi th the symbol II ZCII .A typical command sequence is to enter IIZ C HLTII from theSCC. The system responds by printing II (HLT)II on the nextline of the SCC printout, and forcing the system to haltinstruction execution and enter the IDLE state. If a commandcannot be executed due to improper syntax or context,the system provides an odvisory message following the commandecho indicating the probable source of error. A typicalexample of the display format is II(RSY) *EVENT A1*1I,indicating that a reset command may not be executed priorto halting instruction execution. (Refer to Table 21 fora complete listing of event messages.)The various control functions that may be exercised fromthe SCC may be generally classified into three categories:operator control commands, diagnostic control commands,and maintenance control commands.OPERATOR CONTROL COMMANDSThese commands provide controls which an operator normallyuses to control the computer system. By enteri ng the appropriatecommand the operator may direct the computer systemto load, run, halt, reset, read/set the sense switches, orissue a IIconsole interrupt ll to the operating software.The sense switch control and console interrupt commandsmay interact with the software and are always operative.All other SCC functions may be enabled or disabled bythe SCC FUNCTIONS switch on the SCPoTable 21.Event MessagesDisplay*EVENT 00**EVENT AO**EVENT A1**EVENT A2**EVENT M**EVENT A8**EVENT FO**EVENT Fl**EVENT F4**EVENT F6**EVENT F9*SignificanceSystem Initialization; POWER ON or SUPER RESET.cImproper syntax for Z format command.Command not executed; Improper syntax or system may not be in IDLE mode.Command not executed; system not in maintenance mode.Command not executed; SCC FUNCTION switch is in DISABLE position.Power ride through; recoverable power line fai lure detected; power on trap requested.Trap requested occurred; inhibited in P-Mode.Basic processor error halt; watchdog timeout reset issued when watchdog timeout alarm bitset. (See II Processor Control Word ll .)Basic processor halt; Address Halt.Basic processor halt; Processor-Detected Fault (PDF).System failed micro-diagnostic test (followed by Single Clock Status Register display of theelement that fa i led).Control Commands 153

To prevent inadvertent activation from disrupting a runningsystem, the SCC FUNCTIONS switch is placed in theDISABLE position.The following operator control commands are standard featuresof this system:ZCIInput Display Name of CommandZc I (I) Operator's ConsoleInterruptZc SSW (SSW=bbbb) Read Sense SwitchesZC ss#t (Ss#t =bbbb) Set Sense Swi tchesZC LDN####t,tt,ttt (LDN@####t)ZC RSytt, ttt(RSY)Load NormalReset SystemZC RBptt, ttt (RBP) Reset Basic ProcessorZC RIOtt, ttt (RIO) Reset I/O SystemZC HLTtt (HLT) System HaltZC RU Ntt ,ttt (RUN) System RunOPERATOR'S CONSOLE INTERRUPTThe Operator's Console (or SCC) INTERRUPT command permitsthe operator to interact with the executing software bysetting interrupt level X'5D'. If this interrupt level is Armedwhen the INTERRUPT command is entered, the interruptlevel is advanced to the Waiting state. If the interruptlevel is already in the Active state or Disarmed, the INTERRUPT command has no effect upon the computer system. Thiscommand is always enabled.ZCSSWREAD SENSE SWITCHESThis command causes the status of the sense switches to bedisplayed as part of the command echo. For example, if allfour sense switches were set to a 1, the console displaywould be II (SSW=1111)1I. The status of the sense switchesis also displayed by indicators on the System Control Panel.The READ SENSE SWITCHES command is always enabled.The status of the sense switches may also be read by executinga READ DIRECT instruction (see Chapter 3).tHexadecimal digits.ttscc FUNCTIONS switch of SCP must be in the ENABLEposition.tttSystem must be in the IDLE state.zCSS#SET SENSE SWITCHESThis command causes the sense switches to be set to thevalue specified by the hexadecimal digit in the command(#). The new sense switch value is displayed as part ofthe command echo. For example, if the operator entersIIZ c SS3 11 the SCC will print II(SS3=O0l1)lI. The new statusis al~o displayed by indicators on the System ControlPanel. The SET SENSE SWITCHES command is alwaysoperative.The sense switches may also be set by executing a WRITEDIRECT instruction (see Chapter 3). The sense switchesare initialized to zero during the power on and SUPERRESET sequences. Whi Ie the ZcSS# command is active,the basic processor is momentarily put in the IDLE state.This prevents any conflict between the operator commandand a WRITE DIRECT instruction.Zct.ON####LOAD NORMALThe loading operation is normally accomplished by readyingthe load device and entering the LOAD NORMAL commandfrom the System Control Console. The four hexadecimaldigits (represented as ####) specify the load device address.Successful completion of the command is signified by thecommand echo II (LDN@#H##)II. A fai lure in the loadsequence is indicated by a display of an appropriate errormessage (see Table F- ) following the command echo. TheLOAD NORMAL command is accepted only when thesystem is in the IDLE state.This single command initiates the following sequence:1. A series of internal micro-diagnostic tests are conductedto verify the operation of system paths andelements used in the loading sequence. Each test ispreceded by a system reset. If a failure is detectedduring the micro-diagnostic tests, an error messageII *EVENT F9*1I is generated and followed by a SingleClnrk StnhlC: Rp.nic:tp.r dic:nlnv idpntifvinn thp fnilinn------ -.-.• _- ---.::1----- --'-1----' ----._--,---.;;;, .-.- ._.... _;;:)element.2. Upon completion of all micro-diagnostic tests, a systemreset is issued.3. All system memory locations are initial ized to zero.4. The basic processor loads a self-diagnostic program inmemory locations X'lOO' through X'lFF' and loads thebootstrap loader (see Figure 14) in memory locationsX'20' through X'29'. If an error is detected during theprocess, an error message "*EVENT FO*", is generated.5. The system is placed in the RUN mode.6. The basic processor executes the self-diagnostic program,beginning at location X'160'. The processorthen executes the bootstrap loader, starting at locationX'26'. If a failure occurs during the processor selfdiagnosticprogram, the processor enters the WAIT state.154 Control Commands

Location(hex) (dec)20 3221 3322 3423 3524 3625 3726 3827 3928 4029 41Hexadecimal020000A8o E000058221100296410002368000028OOOO####t22000010CCOOO025CDOOO02569COO022Symbol ic formof instructionL1, 1BDR,1BCR,O 40L1,0S10,0 *37TIO,O *37BCS,12 34t#### represents four hexadecimal digits that specifythe load device address as entered by the LOADNORMAL command.Figure 14. Bootstrap LoaderExecution of the bootstrap program causes the followingactions:1. The first record on the selected peripheral is read intomemrory locations X'2A I through X'3F ' (the previouscontents of general register 0 are destroyed as a resultof executing the bootstrap program in locationsX'26 1 through X'29 1 ).2. After the record has been read, the next instructionis taken from location X'2A' {provided that no errorcondition has been detected by the device or the(lOP).3. When the instruction in location X'2A' is executed,the unit device and device controller selected for theload operation can accept a new SIO instruction.4. Further I/o operations from the load unit may be accomplishedby coding subsequent I/O instructions toindirectly address location X'25 1 •Following the successful completion of the load sequence,the computer system usually continues execution of theloaded program and begins issuing messages to the operatorvia the I/o system to the System Control Console.RESET SYSTEMThe RESET SYSTEM command performs the combined functionsof the RESET BASIC PROCESSOR and RESET I/OSYSTEM commands, as well as the function described below:1. The system control processor bus interface is initialized.2. The processor memory bus and processor bus interfacesare initialized.3. The system memory units are initialized. This processdoes not alter any memory locations.4. AI I interrupt levels are reset to the Disarmed and Disabledstate.5. The system ALARM indicator is cleared.This command is accepted only when the system is in theIDLE state.RESET BASIC PROCESSORThe RESET BASIC PROCESSOR command initial izes the basicprocessor by performing the following:1. All bits in the Program Status Words, except the instructionaddress, are reset.2. The program counter of the BP (register 05) is set to avalue of X'26 1 •3. The Bf' remains in the IlJLt state until allowed to beginexecution at location X'26 1 •This command is accepted only when the system is in theIDLE state.Since all memory requests are inhibited during a reset, theRESET BASIC PROCESSOR command disrupts any simultaneousmemory request from the standard I/O system.RESET I/o SYSTEMWhen accepted, the RESET I/O SYSTEM command initializesthe lOPs and device controllers of the standard I/osystem. All peripheral devices under control of the systemare reset to the "ready II condition and all status, interrupt,and control indicators in the I/O system are reset. Thiscommand is accepted only when the system is in the IDLEstate. The RESET I/o SYSTEM command does not affectthe External Direct Input/Output (DIO), the BP, or othernon-input/output system elements.zcttL TSYSTEM HALTWhen the HALT command is entered, the BP ceases toexecute instructions and is forced into the IDLE state; theRUN indicator on the System Control Panel is extinguishedControl Commands 155

and the IDLE indicator is illuminated. In the IDLE statethe load commands, the reset commands, and the RUN commandare enabled. The I/O system may continue to performI/o operations initiated prior to the ZCHLT command, eventhough the BP is halted. Note that the processor HALTstatus is not set by the ZCHLT command, but is caused byinternal processor conditions (see II Processor-Control Word").SYSTEM RUNThe RUN command is accepted only if the BP is in theIDLE state. When the FUN command is accepted, the BPis allowed to execute its instruction stream. On the SCP,the IDLE indicator is extinguished and the RUN indicatoris illuminated, subject to the processor control word andsystem status.When not in the IDLE state, the system does not accept anyof the load and reset control commands. Attempti ng to enterany load and reset control command while the system is inthe RUN mode results in an error message being displayedon the control console (see Table F- ).represents the data in the location specified in the II A"field (eight hexadecimal digits). The first hexadecimaldigit of the A field is XIOI for memory addresses and X'8 1for internal register addresses. All valid commands, exceptEXIT P-MODE, produce a display in this format.The allowed diagnostic command set is listed in Table 22.An example of the resulting printout is shown in the sectionentitled ,rOperating Procedures and Information".pCENTER P-MODEThe ENTER P-MODE control command is generated by depressingthe CONTROL and P keys, simultaneously (pc).The system is forced into the IDLE state and the processorwi II execute diagnostic control commands entered from theSystem Control Console. The ECS remains in the P-Modeuntil an EXIT P-MODE command (described below) isentered or the ZC format commands SYSTEM RUN or LOADNORMAL are entered. Successful entry into the P-Modeis indicated by a P-Mode display on the SCC.(P-Mode)SELECT INTERNAL REGISTER ADDRESSINGDIAGNOSTIC CONTROL COMMANDSDiagnostic control commands facilitate isolating softwareand hardware problems by providing single-instruction execution,as well as permitting read/write access to manyprocessor internal control registers and system memory locations.To perform diagnostic commands, BP instructionexecution must be interrupted and the ECS control modealtered. This is accomplished by the ENTER P-MODE command(a "CONTROL-P" character generated by depressingCONTROL and P keys simultaneously). Once in P-Modethe system is forced into the IDLE state and the BP storesand fetches data or executes single instructions only uponrequest from the operator through the SCC.Note: Within this text the control-P character is repre-- sented by the following symbol, pc.The diagnostic control (P-Mode) command format differsfrom the basic command format. Hexadecimal digits areimmediately echoed and stored to be used as data or addressdepending on the following command. The systemtruncates the data stream to eight hexadecimal digits andassumes leading zeros if less than eight characters are entered.All non-hexadecimal characters, except basic (ZC)format commands, are treated as P-Mode commands. If thecharacter is not in the allowed commond set; it is echoedfollowed by a question mark II N?" and no action results.Valid commands are echoed; the requested operation isthen performed and a P-Mode data display of the formII P:DDDDDDDD @ AAAAAAAN' is generated on the nextline of SCC pri ntout. The II pil represents the processor address(normally 0); the II D" field (eight hexadecimal digits)(P-Mode)/ SELECT MEMORY ADDRESSINGThese commands specify the storage element whose contentsare to be displayed and operated upon with subsequentcommands. The "/" character following a hexadecimaldata stream specifies a memory address; the ". II characterspecifies an internal processor control register address. Alladdress calculations and memory accesses are subject tothe write lock keys, address mode, and mapping bits in theprogram status words.(P-Mode)+ ADD TO SELECTED LOCATIONThe "+" character, following a hexadecimal data stream,causes the value of the data to be added to the contents ofthe selected storage element.(P-Mode)SUBTRACT FROM SELECTED LOCATIONThe "_" character, followi ng a hexadecimal data stream,causes the value of the data to be subtracted from thecontents of the selected storage element.(P-Mode)MSTORE IN SELECTED LOCATIONThe II Mil character, following a hexadecimal data stream,causes the data to be stored in the selected storage element.156 Control Commands

Table 22.Diagnostic Control (P-Mode) CommandsCharacterFunctionENTER P-MODE.####. .. ## I~ut data or address value (context determined by the succeeding operator.# ##. .• ## is any hex digit string).SELECT INTERNAL REGISTER ADDRESSING./ SELECT MEMORY ADDRESSING.+ ADD TO SELECTED LOCATION.SUBTRACT FROM SELECTED LOCATION.MLRSTORE IN SELECTED LOCATION.SHIFT LEFT AND DISPLAY.SHIFT RIGHT AND DISPLAY.INCREMENT REFERENCED ADDRESS AND DISPLAY.RUBOUTSGxDISPLAY ADDRESSED LOCATION.INSTRUCTION SINGLE STEP.SPECIAL INSTRUCTION SINGLE STEP.EXIT P-MODE.(f'-Mode)LSHIFT LEFT AND DISPLAYThis command causes an image of the contents of the presentlyselected memory location or Q register to be shiftedone bit position to the left and then displayed. A zero isentered into the least significant bit of the location foreach L command.Actual contents of the memory or Q-register location referencedby the shift instruction are not altered.(P-Mode)RSHIFT RIGHT AND DISPLAYThis command causes an image of the contents of the presentlyselected memory location or Q register to be shiftedone bit position to the right and then displayed. A zero isentered into the most significant bit of the memory locationor Q register for each R command executed.Actual contents of the memory or Q register location referencedby the shift instruction are not altered.(P-Mode)IINCREMENT REFERENCED ADDRESS ANDDISPLAYThis command increments by + 1 the address of the currentlyselected memory location or Q register {as specified by apreviously executed SELECT MEMORY ADDRESSING orSELECT INTERNAL REGISTER ADDRESSING control command}.The new address and contents are displayed on thenext line.{P-Mode}RUB OUTDISPLAY ADDRESSED LOCATIONThis command displays the contents of the currently addressedmemory location or Q register {as specified bya previously executed SELECT MEMORY ADDRESSINGor SELECT INTERNAL REGISTER ADDRESSING controlcommand}.(P-Mode)SINSTRUCTION SINGLE STEPThis command causes the BP to execute a single instructionas pointed to by the current contents of the programcounter. Execution is precisely the same as if the systemwere running continuously. Upon completion, the BPreturns to the IDLE state. If a trap occurs while the instructionis being executed, the instruction in the trap locationis executed before the BP returns to the IDLE state. Theresultant display shows the next instruction to be executed.Condition codes resulti ng from the instruction executionare displayed as the second hexadecimal digit of the addressfield.Control Commands 157

(P-Mode)GSPECIAL INSTRUCTION SINGLE STEPThis command permits the contents of register Q5 to be interpretedas the current instruction, and execution by theBP proceeds as described for the INSTRUCTION SINGLESTEP command. The program counter is incremented by + l.This command thus allows any single instruction (containedin register Q5) to be executed in lieu of the instructionpointed to by the program counter without otherwise disturbingconditions within the system. The resultant displayshows the next instruction to be executed.Condition codes resulting from the instruction executionare displayed as the second hexadecimal digit of the addressfield.Input Display Name of CommandZC MM2 (MM2) SET/CLEAR CLUSTERDISPLAY MODEZC MM3 (MM3) SET/CLEAR P-MODE REPEATMODEZc MM4ttZc MM5tt(MM echo SUPER RESETinterrupted)(MM5)SET MICRO-DIAGNOSTICLOOP MODEZcMMlt (MM6) INITIATE ELEMENT MICRO-DIAGNOSTIC(P-Mode)XEXIT P-MODEZcMMlt (MM7) SET LOW CLOCK MARGINSZc MM8tt (MM8) SET HIGH CLOCK MARGINSThe EXIT P-MODE command terminates the P-Mode withinthe ECS. The BP resumes execution of instructions. Ifno SYSTEM RUN or LOAD NORMAL commands were in effectbefore entering the P-Mode, the system remains in theIDLE state.Zc MM9 tt (MM9) SET MEMORY INTERLEAVEOVERRIDEZcMMAtt (MM echo SET DISPLAY INHIBIT MODEinterrupted)ZCCLKtt (CLK) SET SINGLE CLOCK MODEIspace' t Ispace l SINGLE-CLOCK STEPMAINTENANCE CONTROL COMMANDSMaintenance control commands faci I itate isolation andanalysis of system hardware malfunctions. The 'c~mmandsare accepted only if the SCC FUNCTIONS switch is in theENABLE position. In addition, most critical maintenancecontrols can be activated only if the MAINT MODE switchon the SCP is in the ON position.The primary features of the maintenance control commandsare the provision of system clock control and single clockstatus displays. SturU5 is obtuined ffOffl feud-only regi:5tellilocated in central system elements. These Single Clock StatusRegisters (SCSR) monitor the state of internal hardwaresignals. Each SCSR display is printed on the next line ofSCC printout in the format II CE:DDDDDDDD CC". The II CEilfield contains two hexadecimal digits that represent a clusterand an element address, respectively. The 8-digit D fielddisplays the contents of the register, and the 2-digit II CC"field is a modulo 256 clock step counter. This informationis valid only when the system clock is stopped.The following maintenance control commands are includedas standard features of this computer system:ZCCNNt (CNN) MUL TIPLE-CLOCK STEPZC KIL (KIL) CLEAR SINGLE CLOCKMODEZc E ## (EN#) SELECT/DISPLAY SINGLECLOCK STATUS REGISTERZC T (T) SET/CLEAR TRANSPARENTTEXT MODEZC LDS#### (LDS@###N) LOAD SPECIALZC LDT (LDT) MEMORY SETSET SINGLE CLOCK MODEThis command sets the computer system to the II Single ClockMode" by simultaneously stopping all central system clocks,except those required by the External Control Subsystemand the I/O system. When the system is in the SingleClock Mode all control commands may be entered and executed.Operations performed in the Single Clock Modemay differ from those performed when the clock is runningInputZCIvW\ODisplay(MMO)Name of CommandCLEAR MM FEATUREStAil clock controls are inhibited unless the MAINT MODEswitch is in the ON position.ZcMM1t(MM1)SET/CLEAR REPEAT CLOCKING MODEttThese commands are accepted only if the system is in theMAINT MODE.158 Control Commands

at its normal rate (e. g., fixed duration control sequencesmay not take effect and diagnostic control commands whichoperate upon BP's registers or memory locations require a largenumberof clock steps to complete the operation). The RESETSYSTEM, RESET I/O, and RESET BASIC PROCESSOR commandsare effective in Single Clock Mode. When the·Single ClockMode is set, the contents of the currently selected SingleClock Status Register are displayed (see SELECT/DISPLAYSINGLE CLOCK STATUS REGISTER, ZCE## command).If the computer system is currently in the Single ClockMode, ZCCLK command resets the two-digit clock stepcounter to X'OO'.The Single Clock Mode may be reset by either a CLEARSINGLE CLOCK MODE, ZCKIL, command or a SUPERRESET, Z C MM4, command.Note: Entering a SET SINGLE CLOCK MODE commandwhen the basic processor is performing normal data processingoperations may have an adverse effect uponI/o operations. To prevent inadvertent entry intoSingle Clock Mode, the ZCCLK command is not acceptedunless the MAINT MODE switch is in the ONposition. Attempting to enter a ZCCLK commandwhen the MAINT MODE switch is in the OFF positionresults in an error message (*EVENT A2*) beingdisplayed and no further acti on.SELECT/DISPLAY SINGLE CLOCK STATUSREGISTERThis command causes the requested SCSR to be displayed.The Ir##lr portion of this command (two hexadecimal digits)is stored within the ECS and used as a reference address inany command which displays the contents of the currentlyselected Single Clock Status Register. The first hexadecimaldigit is the cluster address and the second digit isthe el ement address.In addition to being modified by subsequent ZcE## commands,the cluster and element addresses may also bechanged by the LOAD NORMAL command and the SETCLUSTER DISPLAY MODE command. The LOAD NORMALcommand sets the address to XIOO' and the SET CLUSTERDISPLAY MODE command causes the element address tobe set to a zero following each cluster scan.Zct

ZCfJlMlSET/CLEAR REPEAT CLOCKING MODEThis command may be used either to SET REPEAT CLOCKINGMODE or to CLEAR REPEAT CLOCKING MODE. When theRepeat Clocking Mode is set, system clocks are repeatedlyissued to the system.If the Display Inhibit Mode, as described below, is alsoset, the clock rate during Repeat Clocking Mode is approximately1600 Hertz. If the Display Inhibit Mode is not set(cleared), the clock rate is determined by the communications frequency of the System Control Consol e.The amount of information displayed when the RepeatClocking Mode is set is also dependent upon the ClusterDisplay Mode. If the Cluster Display Mode (see Z C MM2command) is not set, the contents of the selected SingleClock Status Register is displayed after each clock.If the Cluster Display Mode is set, the contents of all16 SCSRs within a selected cluster are displayed aftereach clock.The above display routine is interrupted during a ZC formatcommand. This mode is cleared by a CLEAR REPEAT CLOCKMODE, Z C MM1, a CLEAR MM FEATURES, ZCMMO, or aSUPER RESET, ZCMM4, command.The P-Mode repeat feature is particularly useful for scanningthrough sequential memory locations or Q registers(using the INCREMENT REFERENCED ADDRESS ANDDISPLAY command or INSTRUCTION SINGLE STEP commanddescribed under II Diagnostic Control Commands H ).Z~M4SUPER RESETThe primary application of the SUPER RESET command is torestore the system to a predetermined condition during andfollowing maintenance activities. The SUPER RESET commandis accepted and executed only if the MAINT MODEswitch on the SCP is in the ON position. Entering a SUPERRESET command when the system is not in the maintenancemode results in an error message without affecting thesystem.If a SUPER RESET command is accepted, all reset signals(System, I/O, and BP) are issued. In addition, the ECSis reset and initialized, and the basic processor executesan initializing routine which clears the contents of theQ scratchpad prior to executing a normal reset.After a SUPER RESET command is executed, the systemremains in the IDLE state, and the ECS is automaticallyplaced in P-Mode.Z~M2SET/CLEAR CLUSTER DISPLAY MODEThis command may be used either to SET CLUSTER DISPLAYMODE or to CLEAR CLUSTER DISPLAY MODE. Whenthe Cluster Display Mode is set, any console operationwhich causes the display of a Single-Clock Status Register(e. g., ZCCLK, ZCMM 1, ZCEIIII, ZCCIIII, ZCKIL,or II~II during Single Clock Mode) will cause the contentsof all SCSRs in the selected cluster to be displayedin successi on.If the Cluster Display Mode is set, it may be reset by aCLEAR CLUSTER DISPLAY MODE, ZCMM2, a CLEAR MMI::C ATIIOCC' ,CAAAA" ___ C'IIDCD DCCCT ,CAAAAA ______ ..1I-L/"'\I VI\L..J, L- IYIIYIV, UI U .JUI LI\ I"L.JLI, L- IYlJvr-r, ~VIIIJIIUIIU.Z~M3SET/CLEAR P-MODE REPEAT MODEThis command may be used either to SET P-MODE REPEATMODE or to CLEAR P-MODE REPEAT MODE.When the P-Mode Repeat Mode is set, any P-Mode functioncharacter (see II Diagnostic Control Commands ll ) enteredfrom the control console is automatically repeatedfollowing each line of display. The repetition of P-Modefunctions is haited by entering any character whiie repetitionis active. Repetition is automatically resumed whenanother function is entered.The P-Mode Repeat Mode may be reset by a CLEAR P-MODEREPEAT MODE, ZCMM3, a CLEAR MM FEATURES, ZCMMO,or a SUPER RESET, Z C MN't4, command.Z~M5SET MICRO-DIAGNOSTIC LOOP MODEThis command allows maintenance personnel to repetitivelyloop the micro-diagnostic test of a single system element.The operator must ensure that the system is in the IDLE stateprior to entering this command.This mode may be cleared by either a SUPER RESET,ZCMM4, or a CLEAR MM FEATURES, ZCMMO, command.Z~M6INITIATE ELEMENT MICRO-DIAGNOSTICThis command causes a single element micro-diagnostic test1._ L_ :_: .. :_1._..1 t: __ LL ___ 1 __ 1._..1 C: __ I_r"I __ LC .. _ .... __ 1 _____ ..IV IJI;; 1I1111UII;;U IVI 1111;; ;)I;;II;;~II;;U .JllIl:::Ill;; .... I~".JIUIV;) 1::11::1111::111,even if the system is in Single Clock Mode. The operatormust ensure that the normal preconditions of micro-diagnostictest execution provided in the LOAD NORMAL sequenceare met. This may be accomplished by the following commandsequence:CLEAR SINGLE CLOCK MODE (enables clocks forreset)SYSTEM HALT (system must be in IDLE state)RESET SYSTEM (test must be preceded by a systemreset)SELECT/DISPLAY SINGLE CLOCK STAfUS REGlSrEI{SET SINGLE CLOCK MODEINITIATE ELEMENT MICRO-DIAGNOSTICSELECT/DISPLAY SINGLE CLOCK STATUS REGISTERSINGLE CLOCK STEP (step-through sequence)160 Control Commands

SET LOW CLOCK MARGINSThis command causes the system clock frequency to be setto low margin. The CLOCK MARGIN indicator (see SystemControl Panel) is illuminated. If high and low clock marginsare both set, an undefi ned i ntermedi ate frequency resu Its.The system clock is restored to a normal frequency by eithera SUPER RESET, Z C MM4, or a CLEAR MM FEATURES,ZCMMO, command. The system clock also assumes the normallevel following power on.Z~M8SET HIGH CLOCK MARGINSThis command causes the system clock frequency to be setto high margin. The CLOCK MARGIN indicator (see SystemControl Panel) is illuminated. If high and low clockmargins are both set, an undefined intermediate frequencyresults.The system clock is restored to a normal level by either aCLEAR MM FEATURES, ZCMMO, command or a SUPER RESET,ZCMM4, command. The system clock also assumes the normallevel following power on.Z~M9SET MEMORY INTERLEAVE OVERRIDEThis command inhibits interleaving all memory units andis used primarily when running certain memory diagnosticprograms. It is allowed only when the system is in themaintenance mode. The change in the manner in whichmemory is accessed when i nterl eavi nQ is i nh i bi ted versuswhen i-nterleaving is permitted requires that programs bereloaded each time the interleave control is changed.Note that the SET MEMORY INTERLEAVE OVERRIDEcommand inhibits interleaving all memory units, whereasthe INTERLEAVE switches of the Configuration ControlPanel (described in Chapter 6) inhibit interleaving on anindividual memory unit basis. The INTERLEAVE DISABLEindicator on the SCP is illuminated while INTERLEAVEOVERRIDE is in effect.The SET MEMORY INTERLEAVE OVERRIDE command remainsin effect (interleaving is inhibited) unti I either aCLEAR MM FEATURES, ZCMMO, ora SUPER RESET, ZCMM4,command is executed. Interleaving is automatically enabledfollowing a power on/off cycle.The Display Inhibit Mode may be cleared by a CLEARDISPLAY INHIBIT MODE, ZCMMA, a CLEAR MM FEATURES, ZcMMO, or a SUPER RESET, ZC MM4, command.The Display Inhibit Mode is automatically cleared followingpower on.ZCLDS####LOAD SPECIALThe LOAD SPECIAL command is accepted only if thesystem is in the IDLE state. The LOAD SPECIAL commandis used in situations where all of the functions performedby the LOAD NORMAL command are not desired (e. g.,in loading a postmortem dump sequence). The LOADSPECIAL command causes only the bootstrap loader programto be written into memory without diagnostics or memoryclearing prior to the load. A II10ad device address II, specifiedby the hexadecimal digits 11####11 in the command, isstored in Q register X I 1 E'. When using the LOAD SPECIALcommand, the operator must also enter the SYSTEM RESETand SYSTEM RUN commands before loading will commence.MEMORY SETThis command causes all memory to be set to the value containedin the BP internal register Q26(X ' 1A'). The commandmay be entered only when' the system is in theIDLE state.ZCTSET/CLEAR TRANSPARENT TEXT MODEThis command is used either to SET TRANSPARENT TEXTMODE or to CLEAR TRANSPARENT TEXT MODE. Whenthe Transparent Text Mode is set, software-driven I/Ofrom the System Control Console is inhibited, but allSCC FUNCTIONS are processed in the normal manner.This feature permits the operator to make marginal notes onthe console printout for logging purposes. If two differentcontrol consoles are connected in parallel (i. e., remotedevi ce is connected as a System Control Consol e), theTransparent Text Mode permi ts messages to be exchangedbetween the two devices. If the SCC FUNCTIONS switchis in the DISABLE position, input data is passed into the I/Osystem regardless of the status of the Transparent Text Mode.The Transparent Text Mode may also be cleared by a SUPERRESET I ZC MM4, command.Z~MASET/CLEAR DISPLAY INHIBIT MODEThis command may be used either to SET DISPLAY INHIBITMODE or to CLEAR DISPLAY INHIBIT MODE. When theDisplay Inhibit Mode is set, all data output associatedwith the System Control Console (SCC) function is inhibited;however, data output generated by the softwareis not affected.The Display Inhibit Mode is normally set to inhibit printoutduring execution of SCC functions which do not requirea display.SYSTEM CONTROL PANELThe System Control Panel contains indicators and controlswhich are used primarily when maintenance and/or diagnosticactivities are performed. The computer operatornormally monitors certain indicators (as described below)to ascertain conditions within the computer system (e. g. ,status of pri mary power, status of sense swi tches, status ofBP, and status of ALARM indicators).Control Commands 161

The controls and indicators of the System Control Panel (seeFigure 15) are functioanlly described below.POWER ONThis alternate-action switch/indicator controls the applicationof power to the system. The indicator is illuminatedonly when the switch has been depressed and power is beingapplied to the system.PRIMARY POWERThis indicator is illuminated whenever PRIMARY power isapplied to the system.POWER FAULTThis indicator is illuminated only if an abnormal powersystem condition exists. Maintenance action is requiredwhen the POWER FAULT indicator is lit.MAINTENANCE MODEThis indicator is illuminated when the computer system isplaced in the maintenance mode as the result of the MAINTMODE switch being in the ON position.INTERLEAVE DISABLEThis indicator is illuminated whenever the two-way interleavingfeature of the memory system is inhibited: (See SETMEMORY INTERLEAVE OVERRIDE command, under" MaintenanceControl Commands".)CLOCK MARGINThis indicator is illuminated whenever the system clockfrequency is above or below the normal value (usually asa result of maintenance and/or diagnostic activities; see SETLOW CLOCK MARGINS and SET HIGH CLOCK MARGINScommands, under "Maintenance Control Commands ll ).POWER MARGINThis indicator is illuminated whenever any power supplywithin the computer system has its low margin switch set.SENSE SWITCHThese four indicators display the status of the four senseswitches. Each indicator is appropriately marked (1, 2,3, 4) and is illuminated only when the corresponding senseswitch is on.ALARMThis indicator is illuminated whenever the system Alarmflip-flog has been set, signifying that a condition hasoccurred which requires the attention of the operator. Thisvisual alarm may also be augmented with an audio alarm(see ALARM AUDIO, below).IDLEThis indicator is illuminated whenever the BP operationshave been interrupted by the ECS. When the system is inthe IDLE state, the BP wi II fetch and store data or executeinstructions only upon request from the System Control Console.The BP states (RUN, WAIT, or HALT) are only definedwhen the BP is executing instructions.I'OIYtRONMOOE/FAULTPOWER FAULTMAINTENANCEMODEINTERLEAVEDISABLESfNSE SWITCHIDLERUNBP STATUS ~ ALARM AUDIO see FUNCTIONS REMOTE CHANNEL MAINTNtOOEWAIT HALT 0Off ~\ H,GH /~~~p EN"', ,SAllE0""{ I /0@@ @ @CLOCK POWERALARMMARGIN MARGINI'ItIMARY POWERS~~~- ----~IEl~~y-----o1..----------------111,ii'"Figure 15. System Control Panel162 Control Commands

BP STATUS AND NO.Th i s group of i ndi cators perm i ts the processor address(usually 0) and current internal state (RUN, WAIT, orHALT) of the BP to be displayed. While executing instructions,the BP is normally in the RUN or WAIT state.The HALT state is entered only when an address halt occurs,the processor disable is on (see II Operating Procedures andInformation lr ) or an irrecoverable processor fault occurs.When the system is in the IDLE state as a result of poweron, a ZCHLT command, or a pc command, only the processoraddress is lighted and RUN, WAIT, and HALT indicatorsare extinguished.ALARM AUDIOThis 4-position rotary switch controls the connection andvolume of a loudspeaker, and also permits all indicators(except POWER ON and PRIMARY POWER) on the SCP tobe tested. When this switch is in the OFF position, theloudspeaker is disconnected. Note that this switch doesnot inhibit the ALARM indicator. When this switch is inthe LOW position, the loudspeaker is connected and thevolume is set to a low level. When this switch is in theHIGH position, the loudspeaker is connected and thevolume is set to a high level. When this switch is held inthe LAMP TEST position, all back-lighted indicators shouldilluminate, simultaneously. The switch returns to theHIGH position when released.SCC FUNCTIONSThis sWitch controis the functionai capabiiities of the SystemControl Console(s). When this switch is in the ENABLEposition, the SCC device(s) may perform the various controlfunctions attributed to a System Control Console.Certain control functions require the system to be in theIDLE state while others (as described under "MaintenanceControl Commands") require the MAINT MODE switch tobe in the ON position.When the SCC FUNCTIONS switch is in the DISABLEposition, the control functions that may be entered fromthe control console (to interact with operating software)are limited to the following:1. Operator requested interrupt (ZcI),2. Read Sense Switches (ZcSSW),3. Set Sense Switches (ZcSS#).The operator may lock out potentially disruptive controlcommands when the operating software isrunning by settingthe SCC FUNCTIONS switch to DISABLE.consoles may be connected in parallel with the SystemControl Console and may perform the same control func':"tions as the local control device. The remote console alsorequires a manual connection through the RD1 data set.Note that any restrictions upon the control functions imposedupon the local control device by the SCC FUNCTIONS switch being in the DISABLE position also applyto both consoles. Either the alternate or remote consoleis selected for input by the AL TSEL switch on the ConfigurationControl Panel (see Chapter 6).When the REMOTE CHANNEL switch is in the OFF position,the remote device is disconnected from the ECS at the dataset (if present). The alternate console functions in the I/omode.When this switch is in the I/o position, the alternate andremote consoles operate strictly as I/O devices communicatingwith the computer system via lOP subchannel addressX'OB'. Only one device is selected for input at a time bythe ALTSEL switch on the Configuration Control Panel(see Chapter 6).MAINT MODEDuring normal operations, this switch is placed in the OFFposition. During maintenance and/or diagnostic activies,this switch may be placed in the ON position or momentariIy held in the RESET position (switch automatically returnsto the ON position when released). In addition to causingthe MAINTENANCE MODE indicator to become illuminatedwhen piaced in the ON position, the sWitch aiso enablescertain hardware controls and allows their associatedcontrol commands to be entered from the operator's controlconsole (see "Maintenance Control Commands"). Thisinterlocking feature prevents inadvertent adverse effectsupon the current program.Caution should be exercised in activating RESET, sincethis position (equivalent to the SCC SUPER RESET command)causes all components of the system to be reset andinitialized.SELECT DISPLAYThese nine switches, labeled CCP/SCSR and 0 through 7,are used to specify the binary address of anyone of up to256 Single Clock Status Registers and up to 32 ConfigurationStatus Registers or Read Direct Mode 9 Status Registerswhose content is to be displayed by the 32 binaryindicators, labeled 0 through 31.REMOTE CHANNELThis 3-position rotary switch controls the manner in whichthe alternate and remote consoles may operate. When thisswitch is in the SCC position, the alternate and remoteWhen the CCP/SCSR switch is in the SCSR position,switches 0 through 3 specify the cluster address andswitches 4 through 7 specify the element address of theSingle Clock Status Register whose content is to bedisplayed.Control Commands 163

When the CCP/SCSR switch is in the CCP position andswitch 0 is in the IrO" position, switches 3 through 7specify the binary address of the cabinet whose Read DirectMode 9 Status Register is to be displayed by the 32 panelindicators.When the CCP/SCSR switch IS In the CCP position andswitch 0 is in the II 111 position, switches3 through 7 specifythe binary address of the cabinet whose 16-bit ConfigurationStatus Register is to be displayed by the 16 lower-orderindicators.SINGLE CLOCK ENABLEThis switch stops all central system clocks in the samemanner as the ZCCLK command. Activating this switchwhen the basic processor is performing normal data processingmay have an adverse effect on any active I/O operations.To prevent inadvertent activation of this control, it isdisabled unless the MAINT MODE switch is in the ONposition.SINGLE CLOCK STEPThis switch is active only when in Single Clock Mode orwhen the Single Clock Enable switch is active. Whenactive, this switch causes one system clock to be issuedeach time it is placed in the STEP position. The newsingle clock status, as selected by the MODE and SELECTswitches, may be monitored via the 32 binary indicatorson the System Control Panel; no display is generated on theSystem Control Console by activation of the SCP SingleClock Step switch.of the Read operation, neither data chaining nor commandchaining is called for in the 10CD. The Suppress IncorrectLength (SIL) flag is set to 1 so that an incorrect length indicationwill not cause a Transmission Error Halt. After theSIO instruction has been executed, the basic processor executesa no instruction with the same effective address as the SIOinstruction. The no instruction is coded to accept onlycondition code data from the lOP. The BCS instruction (inlocation X'29 1 ) will cause a branch to X'22 1 (a LOADIMMEDIATE instruction), if either CCl or CC2 is set to 1.Execution of the LOAD IMMEDIATE instruction at X'22'loads a count of XI 10029 1 into general register 1. The followingBDR instruction at location X ' 23 1 uses this as a"delay" count before executing the BCR instruction in locationX'241, which unconditionally branches to the TIOinstruction in location X'28 1 . In normal operations, CCl isreset to 0 and CC2 remains set to 1 unti I the device canaccept another SIO instruction. At that time, the nextinstruction is taken from location X'2A'.If a Transmission Error or equipment malfunction is detectedby either the device or the lOP, the lOP instructs thedevice to halt and to initiate an II unusual end" interruptsignal (as specified by appropriate flags in the IOCD, describedin Chapter 4). The II unusual end" interrupt willbe ignored since all interrupt levels have been Disarmedand Disabled by the system reset during the load sequence.The device will not accept another SIO while the interruptis pending and the BCS instruction in location X'29 1 willcontinue to branch to location X'221. The correct operatoraction at this point is to repeat the NORMAL LOAD,ZCLDN####, command. If there is no I/O address recognitionof the load unit, the SIO instruction wi II not causeany I/O acti on and CC 1 wi II conti nue to be set to 1 by theSIO and no instructions causing the BCS instruction tobranch.FETCHING and STORING DATAOPERATING PROCEDURES AND INFORMATIONThis section contains reference information which may berequired by either the operator or maintenance/diagnosticpersonnel.LOAD OPERA nON DETAILSThe first executed instruction of the bootstrap program (inlocation X'26 1 ) loads general register 0 with the address ofthe first I/O command doubleword (lOCD). The I/o addressfor the SIO instruction in location X'27 1 is the 13 low-orderbits of location X'25 1 (which have been set equal to the loaduna address asaresu!tofthe NORMAL lOAD, ZCLDN####,command). During execution of the SIO instruction, generalregister 0 points to locations X'20' and X'21 1 as thefirst 10CD for the selected device. This IOCD containsan order to the selected peripheral device to read 88 (X '58 1 )bytes of data into consecutive memory locations beginningat word location X'2A' (byte location X'A8 1 ). At the endThe following examples illustrate how diagnostic control(P-Mode) commands may be used to di splay and al ter thecontents of specified memory locations ond control reg! sterswithin the system. Control commands, as entered from akeyboard device functioning as the System Control Console,are shown in the first column. The resulting printoutsare shown in the second column. The third column of informationis an explanation of the functions performed bythe different control commands.Input Printout FunctionpcO:DDDDDDDD @ 80000000Enter P-Mode ofoperations; contentsof Q n:gister 0 isnormally displayed.100/ 100/ Select and displayO:DDDDDDDD @ 00000100 contents of memorylocation X'lOO'.164 Control Commands

Input5MPri ntout5MFunctionStore X 1 5· into theappropriate control information to perform maintenanceor diagnostic functions, such as halting and resetting thebasic processor, setting address hold, and activating various0:00000005 @ 00000100 currently selectedfault detection controls. During normal operations itmemory location.should not be necessary to access this word. The contentsIIncrement addressof the Processor Control Word are not affected by eitherprocessor or system reset, but are automatically set to zeroO:DDDDDDDD @ 00000101 of currently selected (default condition) during power-on sequencing and bymemory I ocati on and the SUPER RESET command. The bit assignments of thedisplay.Processor Control Word (register Q30) are listed and describedin Table 23.Note that all P-Mode accesses are qualified by address mappingbits and Write Lock keys in the Program Status Words.ADDRESS COMPARE WORDPROCESSOR CONTROL WORDThe Processor Control Word resides in the processor internaladdressable register, Q30. This register may be loaded withThe Address Compare Word is located in register Q31 andcontains parameters defining the type of comparison andthe desired action (alarm, halt, or none) on detecting anaddress compare. (See Table 24.)Table 23. Bit Assignments and Description, Processor Control Word, Register Q30 (XI lEI}BitPositionDescription0 Retry Inhibit:If this hit is a 0, the basic processor will automatically retry the instruction which caused the trap tolocation X'4C '; if this bit is a 1, the basic processor is inhibited from retrying the instruction whichcaused the trap to location X'4C ' •1 Parity Check Inhibit:11" .... L!_ L!.J.. ! ___ f\ _____ !.L ___ L __ L! ____ £ n ____ !_L __ L _______ L! ____ ! ____ LI_-1. !£ LL!_ L!.L ! __ 1___ !L ___ L __ I_! __11 1111;) Uti I;) U v, fJUIIIY '-'11~'-'''''III~ VI 1'1. I~~';)I~I IIUIIO>U'-'"VII;) I;) ~IIU"""~"" .. 1111;) ...... I;) Uof R register transactions is inhibited.2 Watchdog Timer Override:"PUI,'Y '-'""~'-'''''."'~If this bit is a 0, the watchdog timer is allowed to count; if this bit is a 1, the watchdog timer is inhibitedfrom counting and the machine will not execute the Watchdog Timer Trap.3 Watchdog Timer Alarm:If this bit is a 0, the Watchdog Timer Trap is enabled; if this bit is a 1, the Watchdog Timer Trap isinhibited. When a timeout occurs, a system reset is generated and the system will run to timeoutagain. This provides a dynamic loop for isolating the cause of the timeout.4-5 Reserved {must be coded as zeros}.6 Address Hold:7 Processor Ha It:8-15 Reserved.If this bit is a 0, the address hold is disabled; if this bit is a 1, the program counter is inhibited fromcounting {incrementing} causing the machine to loop on the selected instruction (i. e., when the machineis returned to RUN mode, the instruction pointed to by the program counter is executed continuously).If this bit is a 0, the processor is allowed to run under the control of system and P-Mode controls;If this bit is a 1, the processor is forced into the HALT condition.16-31 Load device address.Control Commands 165

BitPosition Status SignificanceTable 24. Bit Assignments, Address Compare Register Q31 (X11 FI)0 1 Selects mapped address comparison.0 Selects unmapped address comparison.1 1 Selects address comparison during instruction access only.0 Selects address comparison for all memory cycles.2 1 Selects comparisons only during memory write cycle.0 Selects all memory cycle comparisons.3 1 Selects page comparisons.0 Selects word comparisons.4 1 System turns on audible alarm for 220 microseconds each time an Address Compare occurs{maximum frequency 1KHz}.0 Address match alarm is disabled.5 1 The processor is forced into the HALT state when an Address Compare occurs.0 Address Halt disabled.6-7 - Reserved.8-31 - Comparison address field.166 Control Commands

6. SYSTEM CONFIGURATION CONTROLPooled resources along with flexible configuration controlprovide a high degree of continuous availability. If aproblem occurs in an individual unit of a resource pool,the system may allow that unit to be isolated with a lossonly in capacity but no loss of functional capability,assuming there is an additional unit of that type in thesystem that can absorb the added load. Specialized unitscan be duplicated (with all units being normally used,where possible) and configuration controls used to divertthe input from one to the other in the event of a failure.Chapter 2 describes the system organization and Chapter 5discusses system operational control. This chapter describesthe Configuration Control Panel (CCP), which servesas the principal element for controlling and modifying theconfiguration of the system.CONFIGURATION CONTROL PANEL (CCP)The CCP provides the capability for enabling and disablingunits in the system. It accomplishes this with centrallylocated manual selection switches used for the followingfunctions:configuration control is designed in a modular manner. Asthe system grows, previously unused rows on the panel canbe used (up to the panel IS maximum of six), and an additionalpanel may be added. Two panels represent the maximumconfiguration for one endbell assembly.Note: The Configuration Control Panel does not contain--- operational controls as the System Control Paneldoes. The CCP switches are initially positionedduring system configuration and are not normallyreposi ti oned duri ng system operati on.CONFIGURATION CONTROL STATUS WORDA program may read settings of the panel switches, type ofunit, and options installed. A READ DIRECT (RD) instructionusing the chassis address of the cluster or unitas an address allows the program to determine the configurationstatus of a particular processor cluster or memoryunit, for example. (The chassis address assignment representsthe chassis ' physical location relative to the endbellassembly.) (See Figure 16.)1. Establish starting addresses for all memory units in thesystem.2. Enable or disable memory ports.3. Enable or disable individual units and clusters.The configuration control status of a panel read by theRD instruction is a 32-bit status word consisting of panelswitch settings and type information. (The RD instruction is descri bed in Chapter 3, .. Control Instructi ons" • )The logic for these program provisions resides in eachunit.4. Control the power throughout the system.The Configuration Control Panel is mounted within the endbellassembly at the end of the row of cabinets containingthe chassis assemblies for the MUs, BP, and other systemcomponents. On the outer surface of the endbell assemblyis the System Control Panel (described and illustrated inChapter 5). Access is gained to the CCP by opening thehinged endbell assembly (see Figure 16).In addition to reading configuration status informationvia a READ DIRECT (RD) instruction in a program, thestatus information may also be obtained by manual switchselection on the System Control Panel; the 32-bit statusword is displayed on a bank of lamp indicators. (SeeChapter 5 for a discussion of the System Control Panelfeatures. )A CCP has six rows of 22 toggle switches and two lamp indicatorseach. A row may control a memory unit, processorcluster, or system control processor. (See Figure 17, andTables 25 and 26.) The active logic assocIated with eachrow of switches and indicators is located within each processorcluster or memory unit itself. Above each row is amarker strip that identifies the function of each switch. TheCONFIGURATION BUSThe configuration bus connects to each processor cl uster andprovides a path for the system control processor to select andread the switch settings on the CCP for the selected unit viaan RD instruction.System Configuration Control 167

System Control Panel (SCP)Endbell AssemblyAddress 00101 tIdentity TagChassis B Chassis A Chassis B Chassis A Chassis B Chassis ACabinet 1 Cabinet 2 Cabinet 3Configuration Control Panel (CCP)Direction of System Expansion ----... ~(Viewed from Module Side)tStarting from the endbell as cabinet number 0, the most significant four bits designate physical cabinet number.The least significant bit designates the back panel location in the halves of the cabinet.Figure 16. Chassis Physical ConfigurationPOWER POWER SYSTEM CLOCKNNORM ON SEL S ELPROCESSORI ADDRESS -, BP MIOP DIOENABLE ENABLE ENABLE,-F5EL --,AL TSEL FSELA 80 BI,------ REAL TIME CLOCK 5EL-----,r RTCl --,50 51,RTC2 --, rRTC3--,so 51 50 SIr 5TC -,50 51MeeOOOOOOOOOOOOOOOOOOOOOOPOWERPOWER SYSTEM CLOCK.-----PORT ENABlE ----, ~STARTING ADDRESS ------,NNORM ON SEL 5EL INTLV 512 513 SI4 SIS 516 517 518MUle eOOOOOOOOOOOOOOOOOOOOOO• Indicatoro SwitchFigure 17. Sample Rows of CCP Switches168 Configuration Control Panel (CCP)

Table 25. Functions of Processor Cluster Configuration Control Panel RowLabelPOWERNNORMPOWERONSwitch/Indicator1 indicator1 switchFunctionLighted when unit power is shut down due to abnormal operationalcondition.When in up or middle position, enables power-on control in theunit power supply. (Middle position inhibits the unit reset signal.)When in down position, power to unit is off.SYSTEMSEL1 switchSelects the processor bus to which the processor cluster is to beconnected (up is processor bus A, down is B).CLOCKSELPROCESSORADDRESS1 switch3 switchesSelects the clock source (up, A or down, B) for the unit clocksubsystem.Establishes the logical address of the cluster within a group ofproc essor clusters.Note: The 5-bit chassis location number and not the processoraddress is used in addressing the configuration switches fora given unit by the RD instruction directed to the ConfigurationControl Panel.BPENABLE1 switchWhen in down position, inhibits the BPinternal bus.from operating on theMIOPENABLEDIOENABLEALTSELFSELAFSELBO/FSELBl1 switch1 switch1 switch1 switch2 switchesWhen in down position, inhibits the MIOP from operating on thei nterna I bus.When in down position, inhibits external DIO interface.Selects either the remote console (down position) or alternateoperator1s console (up position) to enter data on the RemoteChannel Interface.Selects communications frequency for the primary operator1sconsole as follows:up = same frequency as remote channeldown = 1200 baudNote: The 1200 baud selection is effective only if the REMOTECHANNEL switch on the System Control Panel is not inthe SCC posi ti on.Selects communications frequency for the alternate operator1sconsole and the Remote Diagnostic Interface (Remote Channel) asfollows:BO B1 Rate (baud)- -0 0 1100 1 12001 0 unspecified1 1 300Configuration Control Panel (CCP) 169

Table 25. Functions of Processor Cluster Configuration Control Panel Row (cont.)Label I Swi tch/Indi cator FunctionREAL-TIME CLOCK SEL 8 switches Four groups (labeled RTC1, RTC2, RTC3, and STC) of 2 switcheseach (labeled SO and S 1), used for selecting the real-time clockfrequencies; each of the three real-time clock counters and the onesubjective clock counter may have their frequencies selected by theproper combination of the two switches associated with each counter:SO Sl Frequency (Hz)- -0 0 5000 1 External real-time clock source1 0 20001 1 Power lineTable 26. Functions of Memory Unit Configuration Control Panel RowLabelPOWERNNORMPOWERONSwitch/Indicator1 indicator1 switchFunctionLighted when unit power is shut down due to abnormal operationalcondition.When in up or middle position, enables power-on control in theunit power supply. (Middle position inhibits the unit reset signal.)When in down position, power to unit is off.SYSTEMSELCLOCKSEL1 switch1 switchDetermines to which central shared resources the reset signal isconnected.Selects which clock the memory shall use; up position selects systemclock A, down position selects system clock B.UNITADDRESSPORT ENABLEINTLV3 switches6 switches1 switchEstablishes the logical address of the unit within a group of memoryunits.Down position disables, up enables, corresponding port when settingup different configuration in the system. Switch 1 (leftmost) correspondsto port 1, etc., and swi tch 6 corresponds to port 6.Up position selects interleave addressing mode in each memory unit;down position means no interleaving in any memory unit. Onlytwo-way interleaving is allowed. The unit interleaved with thismemory unit must have its interleave switch on and be in the appropriateaddressing range. The interleave logic operates only formemory units with a number corresponding to a power of 2: i. e. ,16K, 32K words; if other than a power of 2, the interleave signalit receives is ignored. Interleaving is permissible only:1. Between two memory units of the same size.2. Provided the two memory units cover an addressing range thatis continuous and starts at a multiple of the size of the twomemory units taken together.170 Configuration Control Panel (CCP)

Table 26. Functions of Memory Unit Configuration Control Panel Row (cont.)LabelSTARTING ADDRESSSwitch/Indicator7 switchesFunctionUsed to set the starting addresses of the memory units. From left toright the switches are labeled S12, S13, S14, S15, S16, S17, andS 18. Using the switches as a 7-position binary field, this allowsmemory to address up to 1 mi Ilion words.When the memory system comprises memory units of different sizes,some precautions are necessary to prevent false address recognitionas well as to prevent gaps in the memory range.1. If all memory units have sizes that are powers of two, they canall be different; they must, however, be assigned in order ofdecreasing size in the address continuum.For instance, three memory units can be used in this manner:Memory Unit No.Size--Address Range1 64K words o to 64K words2 32K words 64 to 96K words3 16K words 96 to 112K words2. If a memory unit has a size that is not a power of two, it mustbe situated in a memory system that satisfies the followingrules:a. All other memory units must have sizes that are a powerof two.b. The starting address of the non-power-of-two unit must bea multiple of the next power of two above the size of thatunit.c. The memory unit whose size is not a power of two must beat the upper end of the address range.Configuration Control Panel (CCP) 171

APPENDIX A. REFERENCE TABLESThis appendix contains the following reference material:STANDARD CHARACTER SETSTitleStandard Symbo Is and CodesStandard 8-Bit Computer Codes (EBCDIC)Standard 7-Bit Communication Codes (ANSCII)Standard Symbol-Code CorrespondencesHexadecimal ArithmeticAddition TableMultiplication TableTable of Powers of Sixteen 10Table of Powers of Ten16Hexadecimal-Decimal Integer Conversion TableHexadecimal-Decimal Fraction Conversion TableTable of Powers of TwoMathematical ConstantsSTANDARD SYMBOLS AND CODESThe symbol and code standards described in this publ icationare applicable to all Xerox computer products, both hardwareand software. They may be expanded or altered fromtime to time to meet changing requirements.The symbols listed here include two types: graphic symbolsand control characters. Graphic symbols are displayableand printable; control characters are not. Hybrids are SP,the symbol for a blank space; and DEL, the delete code,which is not considered a control command.Three types of code are shown: (1) the 8-bit Xerox StandardComputer Code, i.e., the Extended Binary-Coded-DecimalInterchange Code (EBCDIC); (2) the 7-bit American NationalStandard Code for Information Interchange (ANSCII); and(3) the Xerox standard card code.1. EBCDIC57-character set: uppercase letters, numerals, space,and & / < > ( ) + I $ *% # @63-character set: same as above plus iII89-character set: same as 63-character set pi usI owercasel etters2. ANSCII64-character set: uppercase letters, numerals, space,and "! $ % & () * + ,/ \ < >? @ []A #95-character set: same as above plus lowercase lettersand { }CONTROL CODESIn addition to the standard character sets I isted above, thesymbol repertoire includes 37 control codes and the hybridcode DEi.. (hybrid code SP is considered part of aii charactersets). These are I isted in the table titled StandardSymbo I-Code Correspondences.SPECIAL CODE PROPERTIESThe following two properties of all standard codes wi" beretained for future standard code extensions:1. All control codes, and onl y the control codes, havetheir two high-order bits equal to 1100". DEL is notconsidered a control code.2. No two graphic EBCDIC codes have their seven loworderbits equal.?Appendix A 173

STANDARD 8-BIT COMPUTER CODES (EBCDIC)Hexodecimol .0 1Binary 000.0 0001.0 0000 NUL OLE1 .0001 SOH DCI2 0010 STX DC23 0011 ETX DC34 .0100 EaT DC4~L5 .0101 HTI'~I~6 .011.0 ACK SYNS7 Dill BEL ETB~ 8 1000EOMIrBS 1\-,I~9 1001 ENQ EM~A 1.010 INAK SUBB 1.011 VT ESCC 1100 FF FS0 11.01 CR GSE 111.0 SO RSF 1111 SI US,3,Most C" .,.Digits2 3 4 5 6 7 8 9 A B C 0 E F0010 .0.011 .01.0.0 iQ101 .0110 .01111000 1001 1.010 1.011 1100 11.01 111.0 11111ds SP & -~.0ss ~~ ~ / ~ a j \1 A J 1fs~~ ~ W ~ b k s 11 B K S 2si~~ ~ ~ ~ c I t ~ 1 C L T 3~~ ~ ~ ~ d m u [ 1 0 M U 4;"" """~!;~;d' ] 1e n v E N V 5'/. '/// @ ~ f 0 w F a w 6'// '// '///~ r/0Z W/g p x G P X 7~~ ~ ~ ~ h q Y H Q Y 8~ ~ ~ ~ i r z I R Z 91-2 !1:~ ~ ~ ~S , ~ ~ ~ ~< * % @'{/// '//// "~i! ~~"""."" ,n/e/d/~( )-~ ~ ~ ~I+ i > =~ ~ ~ ~2 ,2?~ ~ ~ DELIINOTES:The characters ,.. \ t ~ [] are ANSCllcharacters that do not appear in any of theEBCDIC-based character sets, though theyare shown in the EBCDIC table.The characters ~ I-.appear in the 63- and89-character EBCDIC sets but not in eitherof the ANSCIl-based sets. However, Xeroxsoftware translates the charactersinto ANSCII characters as follows:EBCDIClIANSCII\ (6-0): (7-12)- (7-14)The EBCDIC control codes in columns .0and 1 and their binary representation areexactly the same as those in the ANSClltable, except for two interchanges: IF /NLwith NAK, and HT with ENQ.4 Characters enclosed in heavy lines areincluded only in the standard 63- and89-character EBCDIC sets.These characters are included only in thestandard 89-character EBCDIC set.STANDARD 7 -BIT COMMUNICATION CODES (ANSCII) 1I.0 0000 NUL OLE1 0001 SOH DCl2 .0.01.0 STX DC23 0011 ETX DC34 .0100 EaT DC45 .0101 ENQ NAK'0,0 6 .011.0 ACK SYNCau 7 .0111 BEL ETB'cOJViMost Significant DigitsDecimal.0 1"rows) (col's.)-2 3 4 5 6 71Binary xOOD xOOI xQ1D xDll xl00 x101 xllQ xll18 1000 BS CAN0 9 1001 HT EMQI....J10 1.010LFNlSUB11 1.011 VT ESC12 1100 FF FS13 11.01 CR GS14 111.0 SO RS15 1111 SI US,1\SP .0 @I 5 1 A2 B,II3 CS 4 0% 5 E& 6 FI7 G( 8 H) 9 I* : J+ i K; < L- = M> N/ ? a.P\QRSTUVWXYZabcdefghij[ k\ I] m~" n" '0-PqrstuvwxYz1II~-"DEL,1 Most signifioont bit, odded for 8-bit format, is either .0 or even parity.Columns .0-1 are control codes.Columns 2-5 correspond to the 64-character ANSCII set.Columns 2-7 correspond to the 95-character ANSCII set.On many current teletypes, the symbolis(5-i4iis (5-15)is ESC or ALTMODE control (7-14)and none of the symbols appearing in columns 6-7 are provided. Except for the threesymbol differences noted above, therefore, such teletypes provide all the characters inthe 64-character ANSCII set. (The Xerox 7.015 Remote Keybaard Printer provides the64-character ANSCII set also, but prints A as 1\.)174 Appendix A

0-9-STANDARD SYMBOL-CODE CORRESPONDENCESEBCDICtHex. Dec. Symbol Card Code ANScn tt Meaning Remarks00 0 NUL 12-0-9-8-1 0-0 null 00 thro~h 23 and 2F are control codes.01 1 SOH 12-9-1 0-1 start of header02 2 STX 12-9-2 0-2 start of text03 3 ETX 12-9-3 0-3 end of text04 4 EOT 12-9-4 0-4 end of transmission05 5 HT 12-9-5 0-9 horizontal tab06 6 ACK 12-9-6 0-6 acknowledge (positive)07 7 BEL 12-9-7 0-7 bell08 8 BSorEOM 12-9-8 0-8 backspace or end of message09 9 ENQ 12-9-8-1 0-5 enquiryOA 10 NAK 12-9-8-2 1-5 negative acknowledgeOB 11 VT 12-9-8-3 0-11 vertical tabOC 12 FF 12-9-8-4 0-12 fonn feedOD 13 CR 12-9-8-5 0-13 carriage returnOE 14 SO 12-9-8-6 0-14 shift outOF 15 SI 12-9-8-7 0-15 shift in10 16 DLE 12-11-9-8-1 1-0 data link escape11 17 DCl 11-9-1 1-1 device control 112 18 DC2 11-9-2 1-2 device control 213 19 DC3 11-9-3 1-3 device control 314 20 DC4 11-9-4 1-4 device control 415 21 LF or NL 11-9-5 0-10 line feed or new line16 22 SYN 11-9-6 1-6 sync17 23 ETB 11-9-7 1-7 end of transmission block18 24 CAN 11-9-8 1-8 cancel19 25 EM 11-9-8-1 1-9 end of mediumlA 26 SUB 11-9-8-2 1-10 substitute Replaces characters with parity error.lB 27 ESC 11-9-8-3 1-11 escape1C 28 FS 11-9-8-4 1-12 fi Ie separatorlD 29 GS 11-9-8-5 1-13 group separatorIE 30 RS 11-9-8-6 1-14 record separatorIF 31 US 11-9-8-7 1-15 unit separator20 32 ds 11-0-9-8-1 digit selector 20 through 23 are used with21 33 ~~ ~ ...:--:&:----- -"---j,oiII.~t" ••--••-'W OIIIIYI.E:I"\TT DVTE: ('TDT"I~ IE:D(,\......... a ......... ..,In.al ... "" , .....,. .... ,22 34 fs 0-9-2 field separation instruction - not input/output con-23 35 si 0-9-3 immediate significance start trol codes.24 36 0-9-4 24 through 2E are unassigned.25 37 0-9-526 38 0-9-627 39 0-9-728 40 0-9-829 41 0-9-8-12A 42 0-9-8-22B 43 0-9-8-32C 44 0-9-8-42D 45 0-9-8-52E 46 0-9-8-62F 47 0-9-8-730 48 12-11-0-9-8-1 30 through 3F are unassigned.31 49 9-132 50 9-233 51 9-334 52 9-435 53 9-536 54 9-637 55 9-738 56 9-839 57 9-8-13A 58 9-8-23B 59 9-8-33C 60 9-8-43D 61 9-8-53E 62 9-8-63F 63 9-8-7tHexadecimal and decimal notation.ttDecimal notation {column-row}.Appendix A 175

STANDARD SYMBOL-CODE CORRESPONDENCES (cont.)E8CDlCtHex. Dec.Symbol Card Code ANscn tt Meaning Remarks40 64 SP blank 2-0 blank41 65 12-0-9-1 41 through 49 wi II not be assigned.42 66 12-0-9-243 67 12-0-9-344 68 12-0-9-445 69 12-0-9-546 70 12-0-9-647 71 12-0-9-748 72 12-0-9-849 73 12-8-14A 74 i or ' 12-8-2 6-0 cent or accent grave Accent grave used for left single48 75 12-8-3 2-14 period quote.4C 76 < 12-8-4 3-12 less tban4D 77 ( 12-8-5 2-8 left parenthesis4E 78 + 12-8-6 2-11 plus4F 79 I or I I 12-8-7 7-12 vertical bar or broken bar50 80 & 12 2-6 ampersand51 81 12-11-9-1 51 through 59 wi II not be assigned.52 82 12-11-9-253 83 12-11-9-354 84 12-11-9-455 85 12-11-9-556 86 12-11-9-657 87 12-11-9-758 88 12-11-9-859 89 11-8-1SA 90 ! 11-8-2 2-1 exclamation point58 91 S 11-8-3 2-4 dollars5C 92 * 11-8-4 2-10 asterisk5D 93 ) 11-8-5 2-9 right parenthesis5E 94 ; 11-8-6 3-11 semicolonSF 95 - or ...., 11-8-7 ~7-14 tilde or logical not60 96 - 11 2-13 minus, dash, hyphen61 97 / 0-1 2-15 slash62 98 11-0-9-2 62 through 69 will not be assigned.63 99 11-0-9-364 100 11-0-9-465 101 11-0-9-566 102 11-0-9-667 103 11-0-9-768 104 11-0-9-869 105 0-8-1.....6A 10612-11 5-14 circumflex On Model 7015 -.. is" (caret).68 107 , 0-8-3 2-12 comma6C we % 0-8-4 2-5 percent6D 109 - 0-8-5 5-15 underline Underline is sometimes called "break6E 110 > 0-8-6 3-14 greater than character"; may be printed along6F 111 ? 0-8-7 3-15 question mark bottom of character line.70 112 12-11-0 70 through 79 will not be assigned.71 113 12-11-0-9-172 114 12-11-0-9-273 115 12-11-0-9-374 116 12-11-0-9-475 117 12-11-0-9-576 118 12-11-0-9-677 119 12-11-0-9-778 120 12-11-0-9-879 121 8-17A 122 8-2 3-10 colon78 123 # 8-3 2-3 number7C 124 @ 8-4 4-0 atI7D 125 8-5 2-7 apostrophe (right single quote)7E 126 = 8-6 3-13 equals7F 127 " 8":'7 2-2 quotation marktHexadecimal and decimal notation.ttDecimal notation (column-row).I176 Appendix A

STANDARD SYMBOL-CODE CORRESPONDENCES (cont.)EBCDIC tHex. Dec. Symbol Card Code ANSell tt Meaning Remarks80 128 12-0-8-1 80 is u'lassigned.81 129 a 12-0-1 6-1 81-89, "91-99, A2-A9 comprise the82 130 b 12-0-2 6-2 lowercase alphabet. Available83 131 c 12-0-3 6-3 only in standard 89- and 95-84 132 d 12-0-4 6-4 character sets.85 133 e 12-0-5 6-586 134 f 12-0-6 6-687 135 g 12-0-7 6-788 136 h 12-0-8 6-S89 137 i 12-0-9 6-98A 138 12-0-8-2 SA through 90 are unassigned.88 139 12-0-8-38C 140 12-O-S-480 141 12-0-8-58E 142 12-0-8-68F 143 12-0-8-790 144 12-11-8-191 145 j 12-11-1 6-1092 146 k 12-11-2 6-1193 147 I 12-11-3 6-1294 148 !TI 12-11-4 6-1395 149 n 12-11-5 6-1496 150 0 12-11-6 6-1597 151 p 12-11-7 7-098 152 q 12-11-8 7-199 153 r 12-11-9 7-29A 154 12-11-8-2 9A through Al are unassigned.9B 155 12-11-8-39C 156 12-11-8-49D 157 12-11-8-59E 158 12-11-8-69F 159 12-11-8-7AO 160 11-0-8-1A1 11.1 11-0-1A2 162 s 11-0-2 7-3A3 163 t 11-0-3 7-4A4 164 u 11-0-4 7-5A5 165 v 11-0-5 7-6A6 166 w 11-0-6 7-7A7 167 x 11-0-7 7-8A8 168 y 11-0-8 7-9A9 169 z 11-0-9 7-10AA 170 11-0-8-2 AA through BO are unassigned.AB 171 11-0-8-3AC 172 11-0-8-4AD 173 11-0-8-5AE 174 11-0-8-6AF 175 11-0-8-7BO 176 12-11-0-8-1Bl 177 \ 12-11-0-1 5-12 backs lashB2 178 t 12-11-0-2 7-11 left braceB3 179 ~ 12-11-0-3 7-13 right braceB4 180 [ 12-11-0-4 5-11 left bracketB5 181 ] 12-11-0-5 5-13 right bracketB6 182 12-11-0-6 B6 through BF are unassigned.B7 183 12-11-0-7B8 184 12-11-0-8B9 185 12-11-0-9BA 186 12-11-0-8-2BB 187 12-11-0-8-3BC 188 12-11-0-8-48D 189 12-11-0-8-5BE 190 12-11-0-8-6SF 191 12-11-0-8-7tHexadecimal and decimal notation.tt Decimal notation (column-row).IAppendix A 177

STANDARD SYMBOL-CODE CORRESPONDENCES (cont.)EBCDICtHex. Dec.SY!""bol Card Code ANscn tt Meaning RemarksCO 192 12-0 CO is unassigned.Cl 193 A 12-1 4-1 Cl-C9, Dl-D9, E2-E9 comprise theC2 194 B 12-2 4-2 uppercase alphabet.C3 195 C 12-3 4-3C4 196 D 12-4 4-4C5 197 E 12-5 4-5C6 198 F 12-6 4-6C7 199 G 12-7 4-7C8 200 H 12-8 4-8C9 201 I 12-9 4-9CA 202 12-0-9-8-2 CA through CF will not be assigned.CB 203 12-0-9-8-3CC 204 12-0-9-8-4CD 205 12-0-9-8-5CE 206 12-0-9-8-6CF 207 12-0-9-8-7DO 208 11-0 DO is unassigned.Dl 209 J 11-1 4-10D2 210 K 11-2 4-11D3 211 l 11-3 4-12D4 212 M 11-4 4-13D5 213 N 11-5 4-14D6 214 0 11-6 4-15D7 215 P 11-7 5-0D8 216 Q 11-8 5-1D9 217 R 11-9 5-2DA 218 12-11-9-8-2 DA through DF will not be assigned.DB 219 12-11-9-8-3DC 220 12-11-9-8-4DD 221 12-11-9-8-5DE 222 12-11-9-8-6DF 223 12-11-9-8-7EO 224 0-8-2 EO, El are unassigned.El 225 11-0-9-1E2 226 S 0-2 5-3E3 227 T 0-3 5-4E4 228 U 0-4 5-5E5 229 V 0-5 5-6E6 230 W 0-6 5-7E7E8231232Xy0-70-85-85-9E9 233 Z 0-9 5-10EA 234 11-0-9-8-2 EA through EF will not be assigned.EB 235 11-0-9-8-3EC 236 11-0-9-8-4ED 237 11-0-9-8-5EE 238 ii-O-9-8-6EF 239 11-0-9-8-7FO 240 0 0 3-0Fl 241 1 1 3-1F2 242 2 2 3-2F3 243 3 3 3-3F4 244 4 4 3-4F5 245 5 5 3-5F6 246 6 6 3-6F7 247 7 7 3-7F8 248 8 8 3-8F9 249 9 9 3-9FA 250 12-11-0-9-8-2 FA through FE will not be assigned.FB 251 12-11-0-9-8-3FC 252 12-11-0-9-8-4FD 253 12-11-0-9-8-5FE 254 12-11-0-9-8-6FF 255 DEL 12-11-0-9-8-7 delete Special - neither graphic nor controlsymbol.tHexadecimal and decimal notation.ttDecimal notation (column-row).178 Appendix A

HEXADECIMAL ARITHMETICADDITION TABLE0 1 2 3 4 5 6 7 8 9 A B C D E F1 02 03 04 05 06 07 08 09 OA OS OC OD OE OF 102 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 113 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 124 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 135 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 146 07 08 09 OA OB OC OD OE OF 10 11 12 13 14 157 08 09 OA 08 OC OD OE OF 10 11 12 13 14 15 168 09 OA 08 OC OD OE OF 10 11 12 13 14 15 16 179 OA 08 OC OD OE OF 10 11 12 13 14 15 16 17 18A OB OC OD OE OF 10 11 12 13 14 15 16 17 18 19B OC OD OE OF 10 11 12 13 14 15 16 17 18 19 1AC OD OE OF 10 11 12 13 14 15 16 17 18 19 1A 1BD OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1CE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1DF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1EMULTIPLICATION TABLE1 2 3 4 5 6 7 8 9 A B C D E F2 04 06 08 OA OC OE 10 12 14 16 18 1A 1C 1E3 06 09 OC OF 12 15 18 1B 1E 21 24 27 2A 2D4 08 OC 10 14 18 1C 20 24 28 2C 30 34 38 3C5 OA OF 14 19 1E 23 28 2D 32 37 3C 41 46 4B6 OC 12 18 1E 24 2A 30 36 3C 42 48 4E 54 5A7 OE 15 1C 23 2A 31 38 3F 46 4D 54 5B 62 698 10 18 20 28 30 38 40 48 50 58 60 68 70 789 12 1B 24 2D 36 3F 48 51 5A 63 6C 75 7E 87A 14 1E 28 32 3C 46 50 5A 64 6E 78 82 8C 96B 16 21 2C 37 42 4D 58 63 6E 79 84 8F 9A A5C 18 24 30 3C 48 54 60 6C 78 84 90 9C A8 84D 1A 27 34 41 4E 5B 68 75 82 8F 9C A9 B6 C3E lC 2A 38 46 54 62 70 7E 8C 9A A8 B6 C4 D2F lE 2D 3C 4B 5A 69 78 87 96 A5 B4 C3 D2 ElAppendix A 179

TABLE OF POWERS OF SIXTEEN II162564 Cfi665 5361 048 57616 777 216268 435 4564 294 967 29668 719 476 7361 Cfi9 511 627 77617 592 186 044 416281 474 976 710 6564 503 599 627 370 49672 057 594 037 927 9361 152 921 504 606 846 976no234567891011121314150.10000 00000 00000 00000 x 100.62500 00000 00000 00000 x 10- 10.39062 50000 00000 00000 x 10- 20.24414 06250 00000 00000 x 10- 30.15258 78906 25000 00000 x 10- 40.95367 43164 06250 00000 x 10- 60.59604 64477 53906 25000 x 10- 70.37252 90298 46191 40625 x 10- 80.23283 06436 53869 62891 x 10- 90.14551 91522' 83668 51807 x 10-100.90949 47017 72928 23792 x 10- 120.56843 41886 08080 14870 x 10- 130.35527 13678 80050 09294 x 10- 140.22204 46049 25031 30808 x 10- 150.13877 78780 78144 56755 x 10- 160.86736 17379 88403 54721 x 10- 18TABLE OF POWERS OF TEN 1&o lnOOO 0000 0000 0000323163OEO8AC7217E89185AF3807E86F24578B6B32304A643E8271086AOF 424098 96805F5 El003B9A CAOO540B E4004876 E80004A5 10004E72 AOOO107A 4000A4C6 80006FCl 0000508A 0000A764 000089E8 000023456789101112131415161718190.19990.28F50.4 1890.680B0.A7C50.10C60.1 A070.2 AF 30.44B 80.6 OF 3O.AFE B0.11970.1 C2 59999 9999C28F 5C28374B C6A78BAC 710CAC47 1B47F7 AO B5E 0F29 A BCAF10C4 61 182FAO 9B5A7F67 5EF6FFOB CB249981 2 DE AC268 49760.2 DO 9 370 0 425 70.4 80 E BE 7 B 90580.734A CA5 f 62260.B877 AA32 36A40.12720.10835001C94F0243B602999AF5C3 xEF9E xB296 x8423 x8037 x4858 x73BF x52CC xEAOF xAAFF x1 1 19 x81C2 x3604 x5660 xFOAE xB449 xABA1 xAC35 x16- 116- 216- 316- 416- 4_ti16 -16- 616- 716- 816- 916- 916- 1016 -1116- 1216- 1316- 1416- 1416- 15180 Appendix A

HEXADECRAL-DECIMAL INTEGER CONVERSION TABLEThe table below provides for direct conversions between hexa- Hexadecimal fractions may be converted to decimal fractionsdecimal integers in the range O-FFF and decimal integers in as follows:the range 0-4095. For conversion of larger integers, thetable values may be added to the following figures: 1. Express the hexadecimal fraction as an integer times16 -n, where n is the number of significant hexadecimalHexadecimal Decimal Hexadecima I Decimal places to the right of the hexadecimal point.01 000 4096 20000 131 07202000 8 192 30000 196608O. CA9BF3 16= CA9 BF3 16x 16-603000 12288 40000 262 144 2. Find the decimal equivalent of the hexadecimal integer04 000 16384 50000 3276SO05 000 20480 60000 39321606 000 24576 70000 458752CA9 BF3 = 13 278 195 16 1007000 28672 SO 000 524288 3. Multiply the decimal equivalent by 16- n08000 32768 90 000 58982409000 36 864 AOooo 655 360 13278 195OA 000 40960 SO 000 720896 x 596 046 448 x 10- 16OB 000 45056 CO 000 786 432oe 000 49 152 00000 851 9680.791442096 10OD 000 53248 EO 000 917 504 Decimal fractions may be converted to hexadecimal fractionsOE 000 57344 FO 000 983040 by successively multiplying the decimal fraction by 16 . 10OF 000 61 440 100 000 1 048576 After each multiplication, the integer portion is removeCl to10000 65536 200000 2097 152 form a hexadecimal fraction by bui Iding to the right of the11 000 69632 300 000 3 145728 hexadecimal point. However, since decimal arithmetic is12000 73728 400 000 4 194304 used in this conversion, the integer portion of each product13000 77824 500000 52428SO must be converted to hexadecimal numbers.14 000 81920 600000 6 291 45615000 86 016 700 000 7340032 Example: Convert 0.89510 to its hexadecimal equivalent16000 90 112 800 000 8388 6080.89517000 94208 900000 9437 184J1618000 98304 AOO 000 10 485 76019000 102400 BOO 000 11 534 336~lA 000 106 496 COO 000 12582 912@.120IB 000 110592 DOO 000 13631 488lC 000 114688 Eoo 000 14 6SO 064ID 000 118784 Foo 000 15 728640 ;;;==-~lE 000 122880 1 000 000 16777216IF 000 126 976 2000 000 335544320.E51 E 16 • @.71~0 1 2 3 4 5 6 7 8 9 A B C D E F000 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015010 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031020 0032 0033 0034 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0047030 0048 0049 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 0060 0061 0062 0063040 0064 0065 0066 0067 0068 0069 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079050 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 0090 0091 0092 0093 0094 0095060 0096 0097 0098 0099 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 0110 0111070 0112 0113 0114 0115 0116 0117 0118 0119 0120 0121 0122 0123 0124 0125 0126 0127080 0128 0129 0130 0131 0132 0133 0134 0135 0136 0137 0138 0139 0140 0141 0142 0143090 0144 0145 0146 0147 0148 0149 0150 0151 0152 0153 0154 0155 0156 0157 0158 0159OAO 0160 0161 0162 0163 0164 0165 0166 0167 0168 0169 0170 0171 0172 0173 0174 0175OBO 0176 0177 0178 0179 01SO 0181 0182 0183 0184 0185 0186 0187 0188 0189 0190 0191oeo 0192 0193 0194 0195 0196 0197 0198 0199 0200 0201 0202 0203 0204 0205 0206 0207ODO 0208 0209 0210 0211 0212 0213 0214 0215 0216 0217 0218 0219 0220 0221 0222 0223OEO 0224 0225 0226 0227 0228 0229 0230 0231 0232 0233 0234 0235 0236 0237 0238 0239OFO 0240 0241 0242 0243 0244 0245 0246 0247 0248 0249 0250 0251 0252 0253 0254 0255Appendix A 181

HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)0 1 2 3 4 5 6 7 8 9 A 8 C D E F100 0256 0257 0258 0259 0260 0261 0262 0263 0264 0265 0266 0267 0268 0269 0270 0271110 0272 0273 0274 0275 0276 0277 0278 0279 0280 0281 0282 0283 0284 0285 0286 0287120 0288 0289 0290 0291 0292 0293 0294 0295 0296 0297 0298 0299 0300 0301 0302 0303130 0304 0305 0306 0307 0308 0309 0310 0311 0312 0313 0314 0315 0316 0317 0318 0319140 0320 0321 0322 0323 0324 0325 0326 0327 0328 0329 0330 0331 0332 0333 0334 0335150 0336 0337 0338 0339 0340 0341 0342 0343 0344 0345 0346 0347 0348 0349 0350 0351160 0352 0353 0354 0355 0356 0357 0358 0359 0360 0361 0362 0363 0364 0365 0366 0367170 0368 0369 0370 0371 0372 0373 0374 0375 0376 0377 0378 0379 0380 0381 0382 0383180 0384 0385 0386 0387 0388 0389 0390 0391 0392 0393 0394 0395 0396 0397 0398 0399190 0400 0401 0402 0403 0404 0405 0406 0407 0408 0409 0410 0411 0412 0413 0414 0415lAO 0416 0417 0418 0419 0420 0421 0422 0423 0424 0425 0426 0427 0428 0429 0430 0431180 0432 0433 0434 0435 0436 0437 0438 0439 0440 0441 0442 0443 0444 0445 0446 0447lCO 0448 0449 0450 0451 0452 0453 0454 0455 0456 0457 0458 0459 0460 0461 0462 0463lDO 0464 0465 0466 0467 0468 0469 0470 0471 0472 0473 0474 0475 0476 0477 0478 0479lEO 0480 0481 0482 0483 0484 0485 0486 0487 0488 0489 0490 0491 0492 0493 0494 0495lFO 0496 0497 0498 0499 0500 0501 0502 0503 0504 0505 0506 0507 0508 0509 0510 0511200 0512 0513 0514 0515 0516 0517 0518 0519 0520 0521 0522 0523 0524 0525 0526 0527210 0528 0529 0530 0531 0532 0533 0534 0535 0536 0537 0538 0539 0540 0541 0542 0543220 0544 0545 0546 0547 0548 0549 0550 0551 0552 0553 0554 0555 0556 0557 0558 0559230 0560 0561 0562 0563 0564 0565 0566 0567 0568 0569 0570 0571 0572 0573 0574 0575240 0576 0577 0578 0579 0580 0581 0582 0583 0584 0585 0586 0587 0588 0589 0590 0591250 0592 0593 0594 0595 0596 0597 0598 0599 0600 0601 0602 0603 0604 0605 0606 0607260 0608 0609 0610 0611 0612 0613 0614 0615 0616 0617 0618 0619 0620 0621 0622 0623270 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639280 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 0652 0653 0654 0655290 0656 0657 0658 0659 0660 0661 0662 0663 0664 0665 0666 0667 0668 0669 0670 06712AO 0672 0673 0674 0675 0676 0677 0678 0679 0680 0681 0682 0683 0684 0685 0686 0687280 0688 0689 0690 0691 0692 0693 0694 0695 0696 0697 0698 0699 0700 0701 0702 07032CO 0704 0705 0706 0707 0708 0709 0710 0711 0712 0713 0714 0715 0716 0717 0718 07192DO 0720 0721 0722 0723 0724 0725 0726 0727 0728 0729 0730 0731 0732 0733 0734 07352EO 0736 0737 0738 0739 0740 0741 0742 0743 0744 0745 0746 0747 0748 0749 0750 07512FO 0752 0753 0754 0755 0756 0757 0758 0759 0760 0761 0762 0763 0764 0765 0766 0767300 0768 0769 0770 0771 0772 0773 0774 0775 0776 0777 0778 0779 0780 0781 0782 0783310 0784 0785 0786 0787 0788 0789 0790 0791 0792 0793 0794 0795 0796 0797 0798 0799320 0800 0801 0802 0803 0804 0805 0806 0807 0808 0809 0810 0811 0812 0813 0814 0815330 0816 0817 0818 0819 0820 0821 0822 0823 0824 0825 0826 0827 0828 0829 0830 0831340 0832 0833 0834 0835 0836 0837 0838 0839 0840 0841 0842 0843 0844 0845 0846 0847350 0848 0849 0850 0851 0852 0853 0854 0855 0856 0857 0858 0859 0860 0861 0862 0863360 0864 0865 0866 0867 0868 0869 0870 0871 0872 0873 0874 0875 0876 0877 0878 0879370 0880 0881 0882 0883 0884 0885 0886 0887 0888 0889 0890 0891 0892 0893 0894 0895380 0896 0897 0898 0899 0900 0901 0902 0903 0904 0905 0906 0907 0908 0909 0910 0911390 0912 0913 0914 0915 0916 0917 0918 0919 0920 0921 0922 0923 0924 0925 0926 09273AO 0928 0929 0930 0931 0932 0933 0934 0935 0936 0937 0938 0939 0940 0941 0942 0943380 0944 0945 0946 0947 0948 0949 0950 0951 0952 0953 0954 0955 0956 0957 0958 09593CO 0960 0961 0962 0963 0964 0965 0966 0967 0968 0969 0970 0971 0972 0973 0974 09753DO 0976 0977 0978 0979 0980 0981 0982 0983 0984 0985 0986 0987 0988 0989 099() 09913EO 0992 0993 0994 0995 0996 0997 0998 0999 1000 1001 1002 1003 1004 1005 1006 10073FO 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023182 Appendix A

HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)0 1 2 3 4 5 6 7 8 9 A B C D E F400 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039410 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055420 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071430 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087440 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103450 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119460 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135470 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151480 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167490 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 11834AO 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 11994BO 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 12154CO 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231400 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 12474EO 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 12634FO 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279500 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295510 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311520 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327530 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343540 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359550 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375560 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423590 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 14395AO 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 14555BO 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 14715CO 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 14875DO 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 15035EO 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 15195FO 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535600 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551610 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567620 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583630 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599640 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615650 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631660 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647670 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663680 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679690 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 16956AO 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 17116BO 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 17276CO 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743600 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 17596EO 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 17756FO 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791Appendix A 183

HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)0 1 2 -3 4 5 6 7 8 9 A 8 C D E F700 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807710 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823720 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839730 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855740 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871750 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887760 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903770 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919780 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935790 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 19517AO 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967780 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 19837CO 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999700 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 20157EO 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 20317FO 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047800 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063810 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079820 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095830 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111840 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127850 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143860 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159870 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175880 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191890 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207SAO 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223880 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 22398CO 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255800 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 22718EO 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 22878FO 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303.-900 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319910 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335920 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351930 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367940 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383950 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399960 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415970 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431980 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447990 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 24639AO 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479980 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 24959C0 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 25119DO 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 25279EO 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 25439FO 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559184 Appendix A

HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)0 1 2 3 4 5 6 7 8 9 A B C D E FAOO 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575AlO 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591A20 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607A30 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623A40 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639A50 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655A60 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671A70 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687A80 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703A90 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719AAO 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735ABO 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751ACO 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767ADO 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783AEO 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799AFO 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815BOO 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831B10 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847B20 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863B30 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879B40 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895B50 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911B60 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927B70 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943B80 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959B90 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975BAO 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991BBO 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007BCO 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023BDO 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039BEO 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055BFO 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071COO 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087ClO 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103C20 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119C30 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135C40 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151C50 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167C60 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183C70 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199COO 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215C90 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231CAO 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247CBO 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263CCO 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279COO 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295CEO 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311CFO 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327Appendix A 185

HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)0 1 2 3 4 5 6 7 8 9 A B C 0 E F000 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343010 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359020 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375030 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391040 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407050 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423060 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439070 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455080 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471090 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487OAO 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503OBO 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519OCO 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535000 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551OEO 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567OFO 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583EOO 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599ElO 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615E20 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631E30 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647E40 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663E50 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679E60 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695E70 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711E80 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727E90 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743EAO 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759EBO 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775ECO 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791EDO 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807EEO 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823EFO 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839~f-------- -,--FOO 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855FlO 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871F20 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887F30 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903F40 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919F50 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935F60 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951F70 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967F80 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983F90 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999FAO 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015FBO 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031FCO 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047FOO 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063FEO 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079FFO 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095186 Appendix A

HEXADECIMAL·DECIMAL FRACTION CONVERSION TABLEHexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal.00 000000 .00000 00000 .40 00 00 00 .25000 00000 .80 000000 .50000 00000 .co 000000 .75000 00000.01 000000 .00390 62500 .41 000000 .25390 62500 .81 00 00 00 .50390 62500 .C1 000000 .75390 62500.02 000000 .00781 25000 .42 00 00 00 .25781 25000 .82 000000 .50781 25000 .C2 00 00 00 .75781 25000.03 000000 .01171 87500 .43 000000 .26171 87500 .83 00 00 00 .51171 87500 .C3 00 00 00 .76171 87500.04 000000 .0156250000 .44 000000 .26562 50000 .84 00 00 00 .5156250000 .C4 00 00 00 .7656250000.05 000000 .01953 12500 .45 00 00 00 .26953 12500 .85 00 00 00 .51953 12500 .C5 000000 .76953 12500.06 00 00 00 .02343 75000 .46 00 00 00 .27343 75000 .86 00 00 00 .5234375000 .C6 000000 .77343 75000.07 00 00 00 .02734 37500 .47 000000 .27734 37500 .87 000000 .52734 37500 .C7 00 00 00 .77734 37500.08 000000 .03125 00000 .48 000000 .28125 00000 .88 000000 .53125 00000 .C8 00 00 00 .78125 00000.09 00 00 00 .03515 62500 .49 000000 .2851562500 .89 000000 .5351562500 .C9 000000 .78515 62500.OA 00 00 00 .03906 25000 .4A 00 00 00 .28906 25000 .8A 000000 .53906 25000 .CA 00 00 00 .78906 25000.OB 000000 .04296 87500 .4B 00·00 00 .29296 87500 .8B 00 00 00 .5429687500 .CB 00 00 00 .79296 87500.DC 000000 .04687 50000 .4C 000000 .29687 50000 .8C 00 00 00 .54687 50000 .CC 000000 .79687 50000.00 000000 .05078 12500 .40 00 00 00 .30078 12500 .800000 00 .55078 12500 .CD 00 00 00 .80078 12500.OE 000000 .05468 75000 .4E 000000 .30468 75000 .8E 00 00 00 .5546875000 .CE 00 00 00 .80468 75000.OF 000000 .05859 37500 .4F 00 00 00 .3085937500 .8F 000000 .5585937500 .CF 00 00 00 .80859 37500.10 00 00 00 .06250 00000 .50 000000 .31250 00000 .90 00 00 00 .56250 00000 .DO 00 00 00 .81 250 00000.11 000000 .06640 62500 .51 00 00 00 .31640 62500 .91 000000 .56640 62500 .01 000000 .81640 62500.12 00 00 00 .07031 25000 .52 000000 .32031 25000 .92 00 00 00 .57031 25000 .02 00 00 00 .82031 25000.13 000000 .07421 87500 .53 000000 .32421 87500 .93 000000 .57421 87500 .03 000000 .82421 87500.14 000000 .0781250000 .54 000000 .3281250000 .94 00 00 00 .57812 50000 .04 00 00 00 .8281250000.15 000000 .08203 12500 .55 000000 .33203 12500 .95 000000 .58203 12500 .05 000000 .83203 12500.16 000000 .08593 75000 .56 00 00 00 .33593 75000 .96 00 00 00 .5859375000 .06 00 00 00 .83593 75000.17 000000 .08984 37500 .57 000000 .33984 37500 .97 000000 .58984 37500 .07 000000 .83984 37500.18 000000 .09375 00000 .58 000000 .34375 00000 .98 000000 .59375 00000 .08 00 00 00 .84375 00000.19 000000 .09765 62500 .59 000000 .34765 62500 .99 000000 .59765 62500 .09 000000 .84765 62500.IA 000000 .10156 25000 .5A 00 00 00 .35156 25000 .9A 00 00 00 .60156 25000 .DA 00 00 00 .85156 25000.IB 000000 .10546 87500 .5B 000000 .35546 87500 .9B 00 00 00 .60546 87500 .DB 00 00 00 .85546 87500.1C 000000 .10937 50000 .5C 000000 .35937 50000 .9C 00 00 00 .60937 50000 .DC 00 00 00 .85937 50000.10 000000 .11328 12500 .50 000000 .36328 12500 .90 000000 .61328 12500 .0000 00 00 .86328 12500.IE 000000 .11718 75000 .5E 000000 .3671875000 .9E 000000 .6171875000 .DE 000000 .8671875000.IF 000000 .1210937500 .5F 000000 .3710937500 .9F 000000 .6210937500 .DF 000000 .8710937500.20 000000 .1 2500 00000 .60 000000 .37500 00000 .AO 00 00 00 .62500 00000 .EO 000000 .87500 00000.21 000000 .12890 62500 .61 000000 .37890 62500 .Al 00 00 00 .62890 62500 .El 00 00 00 .87890 62500.22 000000 .13281 25000 .62 00 00 00 .38281 25000 .A2 000000 .63281 25000 .E2 000000 .88281 25000.23 000000 .13671 87500 .63 000000 .38671 87500 .A3 00 00 00 .63671 87500 .E3 000000 .88671 87500.24 000000 .1406250000 .64 00 00 00 .39062 50000 .A4 00 00 00 .64062 50000 .E4 00 00 00 .8906250000.25 000000 .14453 12500 .65 000000 .39453 12500 .A5 00 00 00 .64453 12500 .E5 00 00 00 .89453 12500.26 000000 · 14843 75000 .66 000000 .39843 75000 .A6 00 00 00 .64843 75000 .E6 00 00 00 .89843 75000.27 000000 .1523437500 .67 000000 .40234 37500 .A7 000000 .65234 37500 .E7 00 00 00 .90234 37500.28 000000 .15625 00000 .68 000000 .40625 00000 .A8 000000 .65625 00000 .E8 000000 .90625 00000.29 00 00 00 .16015 62500 .69 000000 .4101562500 .A9 000000 .66015 62500 .E9 000000 .9101562500.2A 000000 · 16406 25000 .6A 000000 .41406 25000 .AA 00 00 00 .66406 25000 .EA 000000 .91406 25000.2B 000000 .1679687500 .6B 00 00 00 .41796 87500 .AB 00 00 00 .667% 87500 .EB 000000 .9179687500.2C 000000 .17187 50000 .6C 000000 .42187 50000 .AC 00 00 00 .67187 50000 .EC 00 00 00 .92187 50000.20 000000 .17578 12500 .60 00 00 00 .42578 12500 .AD 00 00 00 .67578 12500 .ED 000000 .92578 12500.2E 000000 .1796875000 .6E 000000 .42968 75000 .AE 000000 .67968 75000 .EE 00 00 00 .92968 75000.2F 00 00 00 .1835937500 .6F 000000 .43359 37500 .AF 000000 .68359 37500 .EF 000000 .93359 37500.30 000000 .1875000000 .70 000000 .43750 00000 .BO 000000 .68750 00000 .FO 000000 .93750 00000.31 000000 .1914062500 .71 00 00 00 .44140 62500 .Bl 000000 .6914062500 .FI 00 00 00 .94140 62500.32 00 00 00 · 1953 1 25000 .72 000000 .44531 25000 .B2 000000 .69531 25000 .F2 00 00 00 .94531 25000.33 000000 .19921 87500 .73 00 00 00 .44921 87500 .B3 000000 .69921 87500 .F3 00 00 00 .94921 87500.34 000000 .20312 50000 .74 00 0000 .45312 50000 .84 00 00 00 .7031 2 50000 .F4 00 00 00 .953 12 50000.35 000000 .20703 12500 .75 00 00 00 .45703 12500 .B5 00 00 00 .70703 12500 .F5 00 00 00 .95703 12500.36 00 00 00 .2109375000 .76 00 00 00 .46093 75000 .86 00 00 00 .71093 75000 .F6 00 00 00 .9609375000.37 000000 .2148437500 .77 00 00 00 .46484 37500 .B7 00 00 00 .71484 37500 .F7 00 00 00 .96484 37500.38 00 00 00 .2187500000 .78 00 00 00 .46875 00000 .88 00 00 00 .71875 00000 .F8 00 00 00 .%87500000.39 000000 .2226562500 .79 00 00 00 .47265 62500 .B9 00 00 00 .72265 62500 .F9 00 00 00 .97265 62500.3A 000000 .22656 25000 .7A 00 00 00 .47656 25000 .BA 00 00 00 .72656 25000 .FA 00 00 00 .97656 25000.3B 000000 .23046 87500 .7B 00 00 00 .48046 87500 .BB 00 00 00 .73046 87500 .FB 000000 .98046 87500.3C 000000 .23437 50000 .7C 000000 .48437 50000 .BC 000000 .73437 50000 .FC 000000 .98437 50000.30 000000 .23828 12500 .70 00 00 00 .48828 12500 .BD 00 00 00 .73828 12500 .FD 00 00 00 .98828 12500.3E 000000 .2421875000 .7E 000000 .4921875000 .BE 00 00 00 .7421875000 .FE 000000 .9921875000.3F 00 00 00 .2460937500 .7F 000000 .49609 37500 .BF 000000 .74609 37500 .FF 000000 .99609 37500Appendix A 187

HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal.0000 0000 .00000 00000 .00 40 00 00 .00097 65625 .00 80 0000 .0019531250 .00 CO 0000 .00292 96875.0001 0000 .00001 52587 .00 41 00 00 .00099 18212 .0081 0000 .0019683837 .00 Cl 0000 .00294 49462.0002 0000 .0000305175 .0042 0000 .00100 70800 .00 82 0000 .00198 36425 .00 C2 0000 .00296 02050.00 03 0000 .00004 57763 .0043 0000 .00102 23388 .0083 0000 .00199 89013 .00 C3 0000 .00297 54638.00 04 0000 .00006 10351 .00 44 0000 .00103 75976 .0084 00 00 .00201 41601 .00 C4 0000 .00299 07226.0005 0000 .00007 62939 .00 45 00 00 .00105 28564 .00 85 0000 .00202 94189 .00 C5 0000 .00300 59814.00 06 00 00 .00009 15527 .00 46 00 00 .00106 81152 .0086 0000 .00204 46777 .00 C6 0000 .00302 12402.00 07 0000 .0001068115 .00 47 00 00 .00108 33740 .00 87 0000 .00205 99365 .00 C7 0000 .0030364990.00 08 0000 .00012 20703 .00 48 00 00 .0010986328 .00 88 0000 .00207 51 953 .00 C8 0000 .00305 17578.00 09 0000 .0001373291 .00 49 00 00 .00111 38916 .00 89 0000 .00209 04541 .00 C9 0000 .00306 70166.00 OA 00 00 .00015 25878 .00 4A 00 00 .0011291503 .00 8A 00 00 .0021057128 .00 CA 0000 .00308 22753.00 08 00 00 .0001678466 .00 4B 00 00 .0011444091 .00 88 0000 .0021209716 .00 C8 0000 .00309 75341.00 OC 0000 .0001831054 .00 4C 00 00 .00115 96679 .008C 00 00 .0021362304 .00 CC 0000 .00311 27929.00 00 00 00 .0001983642 .00 4D 00 00 .0011749267 .00 8D 00 00 .00215 14892 .00 CD 00 00 .0031280517.00 OE 00 00 .00021 36230 .00 4E 00 00 .0011901855 .00 8E 0000 .0021667480 .00 CE 0000 .00314 33105.00 OF 00 00 .0002288818 .00 4F 00 00 .00120 54443 .008F 00 00 .00218 20068 .00 CF 0000 .00315 85693.00 10 0000 .00024 41406 .0050 0000 .00122 07031 .00 90 00 00 .0021972656 .00 DO 0000 .00317 38281.0011 0000 .00025 93994 .00 51 00 00 .0012359619 .00 91 0000 .00221 25244 .00 Dl 0000 .00318 90869.00 12 0000 .00027 46582 .00 52 00 00 .00125 12207 .00 92 00 00 .0022277832 .00 D2 0000 .00320 43457.00 13 0000 .00028 99169 .0053 00 00 .00126 64794 .00 93 0000 .00224 30419 .00 D3 0000 .00321 96044.00 14 00 00 .00030 51757 .00 54 0000 .00128 17382 .00 94 00 00 .00225 83007 .00 D4 0000 .00323 48632.00 15 0000 .00032 04345 .0055 00 00 .0012969970 .00 95 00 00 .00227 35595 .00 D5 0000 .00325 01 220.00 16 0000 .00033 56933 .00 56 0000 .00131 22558 .0096 00 00 .00228 88183 .00 D6 0000 .00326 53808.00 17 00 00 .00035 09521 .00 57 00 00 .0013275146 .00 97 00 00 .00230 40771 .00 D7 00 00 .00328 06396.00 18 0000 .0003662109 .0058 0000 .00134 27734 .00 98 0000 .00231 93359 .00 D8 0000 .00329 58984.00 19 00 00 .00038 14697 .00 59 0000 .00135 80322 .00 99 0000 .00233 45947 .00 D9 00 00 .00331 11572.00 lA 00 00 .0003967285 .00 5A 00 00 .00137 32910 .00 9A 00 00 .00234 98535 .00 DA 00 00 .0033264160.00 18 00 00 .00041 19873 .00 58 00 00 .00138 85498 .00 9B 00 00 .00236 51123 .00 DB 0000 .00334 16748.001C 0000 .00042 72460 .00 5C 00 00 .00140 38085 .00 9C 0000 .00238 03710 .00 DC 0000 .00335 69335.00 10 00 00 .00044 25048 .00500000 .00141 90673 .00 90 00 00 .00239 56298 .00 DO 00 00 .00337 21923.00 IE 00 00 .00045 77636 .00 5E 00 00 .0014343261 .00 9E 00 00 .00241 08886 .00 DE 0000 .00338 74511.00 IF 00 00 .00047 30224 .00 5F 00 00 .00144 95849 .00 9F 00 00 .0024261474 .00 DF 0000 .00340 27099.00 20 00 00 .00048 82812 .0060 00 00 .00146 48437 .00 AO 0000 .00244 14062 .00 EO 0000 .00341 79687.00 21 00 00 .0005035400 .0061 00 00 .00148 01025 .00 Al 00 00 .00245 66650 .00 El 00 00 .00343 32275.00 22 00 00 .00051 87988 .00 62 0000 .0014953613 .00 A2 0000 .00247 19238 .00 E2 0000 .00344 84863.0023 0000 .00053 40576 .0063 0000 .00151 06201 .00 A3 00 00 .00248 71826 .00 E3 00 00 .00346 37451.00 24 00 00 .0005493164 .00 64 00 00 .0015258789 .00 A4 00 00 .00250 24414 .00 E4 0000 .00347 90039.0025 0000 .00056 45751 .00 65 00 00 .00154 11376 .00 A5 0000 .00251 77001 .00 E5 0000 .0034942626.0026 00 00 .00057 98339 .0066 00 00 .00155 63964 .00 A6 00 00 .00253 29589 .00 E6 00 00 .00350 95214.0027 0000 .00059 50927 .00 67 0000 .00157 16552 .00 A7 00 00 .00254 82177 .00 E7 0000 .00352 47802.0028 00 00 .00061 03515 .00 68 00 00 .0015869140 .00 A8 00 00 .00256 34765 .00 E8 00 00 .00354 00390.0029 00 00 .0006256103 .0069 0000 .00160 21728 .00 A9 00 00 .00257 87353 .00 E9 00 00 .00355 52978.00 2A 0000 .00064 08691 .00 6A 0000 .00161 74316 .00 AA 00 00 .00259 39941 .00 EA 0000 .00357 05566.002S 0000 .00065 6 i 279 .00 6B 0000 .00i63 26904 .00 AB 0000 .00260 92529 .00 ED 0000 .0035858154.002C 0000 .00067 13867 .00 6C 0000 .00164 79492 .00 AC 00 00 .0026245117 .00 EC 0000 .00360 10742.002D 0000 .00068 66455 .006D 0000 .00166 32080 .00 AD 0000 .00263 97705 .00 ED 0000 .00361 63330.00 2E 00 00 .00070 19042 .00 6E 00 00 .0016784667 .00 AE 00 00 .00265 50292 .00 EE 00 00 .00363 15917.002F 0000 .00071 71630 .006F 0000 .00169 37255 .00 AF 0000 .00267 02880 .00 EF 00 00 .00364 68505.0030 0000 .00073 24218 .0070 00 00 .00170 89843 .0080 0000 .00268 55468 .00 FO 0000 .00366 21 093.0031 0000 .00074 76806 .0071 0000 .00172 42431 .00 81 0000 .00270 08056 .00 Fl 00 00 .0036773681.0032 0000 .00076 29394 .0072 0000 .0017395019 .00 B2 0000 .00271 60644 .00 F2 0000 .00369 26269.0033 0000 .00077 81982 .0073 0000 .0017547607 .00 B3 00 00 .00273 13232 .00 F3 00 00 .00370 78857.0034 00 00 .00079 34570 .0074 0000 .00177 00195 .00 B4 0000 .00274 65820 .00 F4 0000 .00372 31445.00 35 00 00 .0008087158 .0075 00 00 .0017852783 .00 B5 0000 .00276 18408 .00 F5 0000 .0037384033.0036 0000 .00082 39746 .0076 0000 .0018005371 .0086 0000 .00277 70996 .00 F6 0000 .00375 36621.00 37 00 00 .00083 92333 .0077 0000 .00181 57958 .0087 0000 .00279 23583 .00 F7 0000 .0037689208.0038 0000 .00085 44921 .0078 0000 .00183 10546 .00 B8 0000 .0028076171 .00 F8 0000 .00378 41796.0039 00 CO .00086 97509 .0079 0000 .00184 63134 I .00 B9 0000 .00282 28759 .00 F9 0000 .00379 94384.003A 0000 .0008850097 .007A 0000 .00186 15722 .00 BA 0000 .00283 81347 .00 FA 0000 .00381 46972.003B 0000 .0009002685 .007B 0000 .0018768310 .00 BB 0000 .00285 33935 .00 FB 0000 .00382 99560.003C 0000 .00091 55273 .007C 0000 .0018920898 .00 BC 0000 .00286 86523 .00 FC 0000 .0038452148.00 3D 0000 .0009307861 .007D 0000 .00190 73486 .00 BD 0000 .00288 39111 .00 FD 0000 .00386 04736.003E 0000 .00094 60449 .007E 0000 .00192 26074 .00 BE 0000 .0028991699 .00 FE 0000 .00387 57324.003F 0000 .00096 13037 .007F 0000 .0019378662 .00 BF 0000 .00291 44287 .00 FF 0000 .0038909912188 Appendix A

HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal.000000 00 .00000 00000 .000040 00 .00000 38146 .000080 00 .00000 76293 .0000 CO 00 .00001 14440.000001 00 .00000 00596 .00 00 41 00 .00000 38743 .000081 00 .00000 76889 .0000 Cl 00 .00001 15036.000002 00 .00000 01192 .00 00 42 00 .00000 39339 .000082 00 .00000 77486 .00 00 C2 00 .00001 15633.000003 00 .00000 01788 .000043 00 .00000 39935 .000083 00 .00000 78082 .00 00 C3 00 .00001 16229.00 00 04 00 .00000 02384 .000044 00 .00000 40531 .000084 00 .00000 78678 .0000 C4 00 .00001 16825.000005 00 .00000 02980 .000045 00 .00000 41127 .000085 00 .00000 79274 .00 00 C5 00 .00001 17421.000006 00 .00000 03576 .00 00 46 00 .00000 41723 .000086 00 .00000 79870 .00 00 C6 00 .00001 18017.000007 00 .00000 04172 .000047 00 .00000 42319 .000087 00 .00000 80466 .00 00 C7 00 .00001 18613.000008 00 .00000 04768 .00 00 48 00 .00000 42915 .000088 00 .00000 81062 .00 00 C8 00 .00001 19209.000009 00 .00000 05364 .00 00 49 00 .00000 43511 .000089 00 .00000 81658 .00 00 C9 00 .00001 19805.00 00 OA 00 .00000 05960 .00 00 4A 00 .00000 44107 .00 00 8A 00 .00000 82254 .0000 CA 00 .00001 20401.OOOOOB 00 .00000 06556 .00 00 4B 00 .00000 44703 .00008B 00 .00000 82850 .0000 CB 00 .00001 20997.OOOOOC 00 .00000 07152 .00 00 4C 00 .00000 45299 .00 00 8C 00 .00000 83446 .0000 CC 00 .00001 21593.OOOOOD 00 .00000 07748 .00 00 4D 00 .00000 45895 .00008D 00 .00000 84042 .0000 CD 00 .00001 22189.OOOOOE 00 .00000 08344 .00 00 4E 00 .00000 46491 .00 00 8E 00 .00000 84638 .0000 CE 00 .00001 22785.0000 OF 00 .00000 08940 .0000 4F 00 .00000 47087 .00008F 00 .00000 85234 .00 00 CF 00 .00001 23381.0000 10 00 .00000 09536 .000050 00 .00000 47683 .000090 00 .00000 85830 .0000 DO 00 .00001 23977.0000 11 00 .00000 1m32 .00 00 51 00 .00000 48279 .00 00 91 00 .00000 86426 .00 00 Dl 00 .00001 24573.0000 12 00 .00000 10728 .000052 00 .00000 48875 .000092 00 .00000 87022 .0000 D2 00 .00001 25169.0000 13 00 .00000 11324 .000053 00 .00000 49471 .00 00 93 00 .00000 87618 .0000 D3 00 .00001 25765.0000 14 00 .00000 11920 .000054 00 .00000 50067 .000094 00 .00000 88214 .0000 D4 00 .00001 26361.0000 15 00 .00000 12516 .000055 00 .00000 50663 .00 00 95 00 .00000 88810 .0000 D5 00 .00001 26957.000016 00 .00000 13113 .00 00 56 00 .00000 51259 .00 00 96 00 .00000 89406 .0000 D6 00 .00001 27553.0000 17 00 .00000 13709 .000057 00 .00000 51856 .00 00 97 00 .00000 90003 .00 00 D7 00 .00001 28149.000018 00 .00000 14305 .000058 00 .00000 52452 .00 0098 00 .00000 90599 .0000 DB 00 .00001 28746.00 0019 00 .00000 14901 .000059 00 .00000 53048 .000099 00 .00000 91195 .0000 D9 00 .00001 29342.0000 1A 00 .00000 15497 .00 00 5A 00 .00000 53644 .0000 9A 00 .00000 91791 .00 00 DA 00 .00001 29938.0000 1 B 00 .00000 16093 .0000 5B 00 .00000 54240 .00 00 9B 00 .00000 92387 .0000 DB 00 .00001 30534.0000 1C 00 .00000 16689 .00 00 5C 00 .00000 54836 .00 00 9C 00 .00000 92983 .0000 DC 00 .00001 31130.00001 D 00 .00000 17285 .00 00 5D 00 .00000 55432 .0000 9D 00 .00000 93579 .0000 DD 00 .00001 31726.0000 1 E 00 .00000 17881 .00005E 00 .00000 56028 .0000 9E 00 .00000 94175 .00 00 DE 00 .00001 32322.0000 IF 00 .00000 18477 .0000 5F 00 .00000 56624 .00009F 00 .00000 94771 .00 00 DF 00 .00001 32918.000020 CO .cccce ! 90731'\" nn Lr. "".uv vv uv vv .vvvvv """"" J1 r~""''''''' LLV .wwAO w .VVVUU 95367 .00 00 to OU .UUUOI JJ~ 14.000021 00 .00000 19669 .000061 00 .00000 57816 .0000 Al 00 .00000 95963 .00 00 El 00 .00001 34110.000022 00 .00000 20265 .000062 00 .00000 58412 .0000 A2 00 .00000 96559 .00 00 E2 00 .00001 34706.00 00 23 00 .00000 20861 .000063 00 .00000 59008 .0000 A3 00 .00000 97155 .0000 E3 00 .00001 35302.000024 00 .00000 21457 .00 0064 00 .00000 59604 .0000 A4 00 .00000 97751 .0000 E4 00 .00001 35898.000025 00 .00000 22053 .00 00 65 00 .00000 60200 .0000 A5 00 .00000 98347 .0000 E5 00 .00001 36494.00 0026 00 .00000 22649 .000066 00 .00000 60796 .0000 A6 00 .00000 98943 .0000 E6 00 .00001 37090.000027 00 .00000 23245 .000067 00 .00000 61392 .00 00 A7 00 .00000 99539 .00 00 E7 00 .00001 37686.000028 00 .0000023841 .000068 00 .00000 61988 .00 00 A8 00 .00001 00135 .0000 E8 00 .00001 38282.000029 00 .00000 24437 .00 00 69 00 .00000 62584 .0000 A9 00 .00001 00731 .0000 E9 00 .00001 38878.00002A 00 .00000 25033 .0000 6A 00 .00000 63180 .0000 AA 00 .00001 01327 .0000 EA 00 .00001 39474.00002B 00 .00000 25629 .00 00 6B 00 .00000 63776 .0000 AB 00 .00001 01923 .0000 EB 00 .00001 40070.00002C 00 .00000 26226 .0000 6C 00 .00000 64373 .0000 AC 00 .00001 02519 .0000 EC 00 .00001 40666.00 00 2D 00 .00000 26822 .0000 6D 00 .00000 64969 .0000 AD 00 .00001 03116 .00 00 ED 00 .00001 41263.00002E 00 .00000 27418 .00006E 00 .00000 65565 .0000 AE 00 .00001 03712 .0000 EE 00 .00001 41859.00 00 2F 00 .00000 28014 .00006F 00 .00000 66161 .0000 AF 00 .00001 04308 .00 00 EF 00 .00001 42455.000030 00 .00000 28610 .000070 00 .00000 66757 .0000 BO 00 .00001 04904 .0000 FO 00 .00001 43051.000031 00 .00000 29206 .00 00 71 00 .00000 67353 .0000 B1 00 .00001 05500 .0000 F1 00 .00001 43647.00 00 32 00 .00000 29802 .00 00 72 00 .00000 67949 .0000 B2 00 .00001 06096 .0000 F2 00 .00001 44243.000033 00 .00000 30398 .00 00 73 00 .00000 68545 .00 00 B3 00 .00001 06692 .0000 F3 00 .00001 44839.000034 00 .00000 30994 .00 00 74 00 .00000 69141 .00 00 B4 00 .00001 07288 .0000 F4 00 .00001 45435.000035 00 .00000 31590 .000075 00 .00000 69737 .00 00 B5 00 .00001 07884 .00 00 F5 00 .00001 46031.000036 00 .0000032186 .000076 00 .00000 70333 .0000 B6 00 .00001 08480 .0000 F6 00 .00001 46627.00 00 37 00 .00000 32782 .000077 00 .00000 70929 .0000 B7 00 .00001 09076 .0000 F7 00 .00001 47223.000038 00 .00000 33378 .000078 00 .00000 71525 .00 00 B8 00 .00001 09672 .00 00 F8 00 .00001 47819.000039 00 .00000 33974 .000079 00 .00000 72121 .00 00 B9 00 .00001 10268 .00 00 F9 00 .00001 48415.00003A 00 .00000 34570 .00007A 00 .00000 72717 .0000 BA 00 .00001 10864 .00 00 FA 00 .00001 49011.00 00 3B 00 .00000 35166 .00007B 00 .00000 73313 .0000 BB 00 .00001 11460 .00 00 FB 00 .00001 49607.00003C 00 .00000 35762 .00007C 00 .00000 73909 .00 00 BC 00 .00001 12056 .00 00 FC 00 .00001 50203.0000 3D 00 .00000 36358 .0000 7D 00 .00000 74505 .0000 BD 00 .00001 12652 .0000 FD 00 .00001 50799.00003E 00 .00000 36954 .00 00 7E 00 .00000 75101 .0000 BE 00 .00001 13248 .0000 FE 00 .00001 51395.00003F 00 .00000 37550 .00 00 7F 00 .00000 75697 .0000 BF 00 .00001 13844 .00 00 FF 00 .00001 51991Appendix A 189

HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal Hexadecimal Decimal.00000000 .00000 00000 .00000040 .00000 00149 .00000080 .00000 00298 .00 00 00 CO .00000 00447.00000001 .00000 00002 .00000041 .00000 00151 .00000081 .00000 00300 .0000 00 Cl .00000 00449.00000002 .00000 00004 .00000042 .0000000153 .00000082 .00000 00302 .000000 C2 .00000 00451.00000003 .00000 00006 .00000043 .00000 00155 .00000083 .00000 00305 .0000 00 C3 .00000 00454.00000004 .00000 00009 .00000044 .00000 00158 .00 00 00 84 .00000 00307 .00 00 00 C4 .00000 00456.00000005 .00000 00011 .00000045 .00000 00160 .0000 00 85 .00000 00309 .000000 C5 .00000 00458.00000006 .00000 00013 .0000 0046 .0000000162 .00 00 00 86 .00000 00311 .00 00 00 C6 .00000 0046 1.0000 00 07 .00000 00016 .00000047 .00000 00165 .00 00 00 87 .00000 00314 .000000 C7 .00000 00463.00000008 .00000 00018 .00 00 00 48 .00000 00167 .00000088 .00000 00316 .00 00 00 C8 .00000 00465.00000009 .00000 00020 .00 00 00 49 .00000 00169 .00000089 .00000 00318 .00 00 00 C9 .00000 00467.00 00 00 OA .00000 00023 .0000 00 4A .00000 00172 .00 00 00 8A .00000 00321 .000000 CA .00000 00470.000000 OB .00000 00025 .0000 004B .00000 00174 .00 00 00 8B .00000 00323 .0000 00 CB .00000 00472.000000 OC .00000 00027 .00 00 004C .00000 00176 .000000 8C .00000 00325 .00 00 00 CC .00000 00474.OOOOOOOD .00000 00030 .00 0000 4D .00000 00179 .0000008D .00000 00328 .00 00 00 CD .00000 00477.00 00 OOOE .0000000032 .00 00 004E .0000000181 .000000 8E .00000 00330 .00 00 00 CE .00000 00479.000000 OF .00000 00034 .0000004F .00000 00183 .000000 8F .00000 00332 .00 00 00 CF .00000 00481.000000 10 .0000000037 .00000050 .00000 00186 .00000090 .00000 00335 .000000 DO .00000 00484.000000 11 .00000 00039 .00000051 .00000 00188 .00 00 00 91 .00000 00337 .00 00 00 D1 .00000 00486.00000012 .00000 00041 .00 00 00 52 .00000 00190 .00000092 .00000 00339 .000000 D2 .00000 00488.000000 13 .00000 00044 .00 00 00 53 .00000 00193 .00000093 .00000 00342 .000000 D3 .00000 00491.000000 14 .00000 00046 .00000054 .00000 00195 .00000094 .00000 00344 .00 00 00 D4 .00000 00493.00000015 .00000 00048 .00000055 .00000 00197 .000000 95 .00000 00346 .00 00 00 D5 .00000 00495.000000 16 .00000 00051 .00000056 .00000 00200 .000000 96 .0000000349 .00 00 00 D6 .00000 00498.00000017 .00000 00053 .0000 0057 .00000 00202 .00 000097 .00000 00351 .00 00 00 D7 .00000 00500.00000018 .00000 00055 .00 00 00 58 .0000000204 .00000098 .00000 00353 .000000 D8 .00000 00502.000000 19 .00000 00058 .00 00 00 59 .00000 00207 .00 00 00 99 .00000 00356 .00 00 00 D9 .00000 00505.OOOOOOIA .00000 00060 .00 00 00 5A .00000 00209 .000000 9A .00000 00358 .00 00 00 DA .00000 00507.000000 IB .00000 00062 .0000 00 5B .00000 00211 .00 00 00 9B .00000 00360 .00 00 00 DB .00000 00509.00 00 00 lC .00000 00065 .00 00 00 5C .00000 00214 .000000 9C .00000 00363 .00 00 00 DC .00000 0051 2.000000 ID .00000 00067 .00 00 00 5D .00000 00216 .00 00 00 9D .00000 00365 .00 00 00 DD .00000 00514.000000 IE .00000 00069 .00 00 00 5E .00000 00218 .00 00 00 9E .00000 00367 .00 00 00 DE .00000 00516.000000 IF .00000 00072 .0000005F .00000 00221 .000000 9F .00000 00370 .00 00 00 DF .00000 0051 9.00000020 .00000 00074 .0000 00 60I.00000 00223 .00 00 00 AO .00000 00372 .000000 EO .00000 00521.00000021 .00000 00076 .00 00 00 61 .00000 00225 .00 00 00 Al .0000000374 .00 00 00 El .00000 00523.000000 22 .00000 00079 .0000 00 62 .00000 00228 .00 00 00 A2 .00000 00377 .00 00 00 E2 .00000 00526.0000 00 23 .00000 00081 .00 00 00 63 .00000 00230 .000000 A3 .00000 00379 .00 00 00 E3 .00000 00528.00000024 .00000 00083 .00000064 .00000 00232 .00 00 00 A4 .00000 00381 .00 00 00 E4 .00000 00530.00000025 .00000 00086 .00000065 .00000 00235 .00 00 00 A5 .00000 00384 .000000 E5 .00000 00533.00 000026 .00000 00088 .0000 00 66 .00000 00237 .00 00 00 A6 .00000 00386 .00 00 00 E6 .00000 00535.00000027 .00000 00090 .00000067 .00000 00239 .00 00 00 A7 .00000 00388 .000000 E7 .00000 00537.00000028 .00000 00093 .00000068 .00000 00242 .00 00 00 A8 .00000 00391 .00 00 00 E8 .00000 00540.00000029 .00000 00095 .00 00 00 69 .00000 00244 .00 00 00 A9 .00000 00393 .00 00 00 E9 .00000 00542.0000002A . 00000 00097 .000000 Y· . .00000 00246 .00 00 00 A.A, .00000 00395 .000000 EA .00000 00544.00 00 00 2B .00000 00100 .00 00 00 6B .00000 00249 .00 00 00 AB .00000 00398 .000000 EB .00000 00547.000000 2C .00000 00102 .00 00 00 6C .00000 00251 .00 00 00 AC .00000 00400 .00 00 00 EC .00000 00549.000000 2D .00000 00104 .00 00 006D .00000 00253 .0000 00 AD .00000 00402 .000000 ED .00000 00551.0000002E .00000 00107 .0000006E .00000 00256 .00 00 00 AE .00000 00405 .00 00 00 EE .00000 00554.0000002F .00000 00109 .0000 00 6F .00000 00258 .000000 AF .00000 00407 .000000 EF .00000 00556.00000030 .00000 00111 .00000070 .00000 00260 .00 00 00 BO .00000 00409 .00 00 00 FO .00000 00558.00000031 .00000 00114 .000000 71 .00000 00263 .00 00 00 Bl .00000 0041 2 .000000 F1 .00000 00561.00000032 .00000 00116 .00000072 .00000 00265 .00 00 00 B2 .00000 00414 .000000 F2 .00000 00563.00000033 .00000 00118 .00000073 .00000 00267 .000000 B3 .00000 00416 .00 00 00 F3 .00000 00565.00000034 .00000 00121 .00000074 .0000000270 .000000 B4 .00000 0041 9 .00 00 00 F4 .00000 00568.00000035 .00000 00123 .00000075 .00000 00272 .00 00 00 B5 .00000 00421 .000000 F5 .00000 00570.00000036 .00000 00125 .00000076 .0000000274 .000000 B6 .00000 00423 .0000 00 F6 .0000000572.0000 00 37 .00000 00128 .00000077 .00000 00277 .000000 B7 .00000 00426 .00 00 00 F7 .00000 00575.00000038 .00000 00130 .00000078 .00000 00279 .00 00 00 B8 .00000 00428 .000000 F8 .00000 00577.00000039 .00000 00132 .00000079 .00000 00281 .000000 B9 .00000 00430 .00 00 00 F9 .00000 00579.0000003A .00000 00135 .00 00 00 7A .00000 00284 .00 00 00 BA .00000 00433 .000000 FA .00000 00582.0000003B .00000 00137 .00 00 00 7B .00000 00286 .00 00 00 SB .00000 00435 .000000 FB .00000 00584.00 0000 3C .00000 00139 .0000007C .00000 00288 .000000 BC .00000 00437 .0000 00 FC .00000 00586.000000 3D .00000 00142 .00000070 .00000 00291 .00 00 00 SD .00000 00440 .000000 FD .00000 00589.0000003E .00000 00144 .00 00 00 7E .00000 00293 .000000 BE .00000 00442 .000000 FE .00000 00591,00 00 00 3F .00000 00146 .0000 00 7F .00000 00295 .000000 SF .00000 00444 .000000 FF .00000 00593190 Appendix A

TABLE OF POWERS OF TWOMATHEMATICAL CONSTANTSL.!!..L1 0 1.02 1 0.54 2 0.258 3 0.12516 4 0.062 532 5 0.031 2564 6 0.015 625128 7 0.007 812 5256 8 0.003 906 25512 9 0.001 953 1251 024 10 0.000 976 562 52 048 11 0.000 488 281 254096 12 0.000 244 140 6258 192 13 0.000 122 070 312 516 384 14 0.000 061 035 156 2532768 15 0.000 030 517 578 12565 536 16 0.000 015 258 789 062 5131 072 17 0.000 007 629 394 531 25262 144 18 0.000 003 814 697 265 625524 288 19 0.000 001 907 348 632 812 51 048 576 20 0.000 000 953 674 316 406 252 097 152 21 0.000 000 476 837- 158 203 1254 194 304 22 0.000 000 238 418 579 101 562 58 388 608 23 0.000 000 119 209 289 550 781 2516 m 216 24 0.000 000 059 604 644 775 390 62533 554 432 25 0.000 000 029 802 322 387 695 312 567 108 864 26 0.000 000 014 901 161 193 847 656 25134 217 728 27 0.000 000 007 450 580 596 923 828 125268 435 456 28 0.000 000 003 725 290 298 461 914 062 5536 870 912 29 0.000 000 001 862 645 149 230 957 031 251 073 741 824 30 0.000 000 000 931 322 574 615 478 515 6252 147 483 648 31 0.000 000 000 465 661 287 307 739 257 812 54 274 YOl 270 ~2 U.UVU uvu uvu 2~2 o:;u ~ 05:i 007 620 7UO 258 589 934 592 33 0.000 000 000 116 415 321 826 934 814 453 12517 179 869 184 34 0.000 000 000 058 207 660 913 467 407 226 562 534 359 738 368 35 0.000 000 000 029 103 830 456 733 703 613 281 2568 719 476 736 36 0.000 000 000 014 551 915 228 366 851 806 640 625137 438 953 472 37 0.000 000 000 007 275 957 614 183 425 903 320 312 5274 877 906 944 38 0.000 000 000 003 637 978 807 091 712 951 660 156 25549 755 813 888 39 0.000 000 000 001 818 989 403 545 856 475 830 078 1251 099 511 627 776 40 0.000 000 000 000 909 494 701 772 928 237 915 039 062 52 199 023 255 552 41 0.000 000 000 000 454 747 350 886 464 118 957 519 531 254 398 046 511 104 42 0.000 000 000 000 227 373 675 443 232 059 478 759 765 6258 796 093 022 208 43 0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 517 592 186 044 416 44 0.000 000 000 000 056 843 418 860 808 014 869 689 941 406 2535 184 372 088 832 45 0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 12570 368 744 177 664 46 0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5140 737 488 355 328 47 0.000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25ConstantIT-l~Inne-Ie.JeloglO elog2 eYInY.J2In2logl02.JITfIn 10Decimal Value3.14159 26535 897930.31830 98861 837901 .77245 38509 055161.14472 98858 494002.71828 18284 590450.36787 94411 714421.64872 12707 001280.43429 44819 032521 .44269 50408 889630.57721 56649 01533-0.54953 93129 816451.41421 35623 730950.69314 71805 599450.30102 99956 639813.16227 76601 683792.30258 40929 94046Hexadecimal Value3.243F 6A890.517C C1B7I.C5BF 891C1.2500 O48F2.B7El 51630.5E2D 5809I.A612 98E20.6F2D EC551.7154 76530.93C4 67E4-0.8CAE 9BCl1.6A09 E668O.BI72 17F8004010 40423.298B 075C2.4076 3777281 474 976 710656 48 0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625562 949 953 421 312 49 0.000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5I 125899906 842 624 50 0.000 000 000 000 000 888 178 419 700 125232 338 905 334 472 656 252251799 813 685 248 51 0.000 000 000 000 000 444 089 209 850 062 616 169452667236 328 1254 503 599 627 370 496 52 0.000 000 000 000 000 222 044 604 925 031 308 084 726 333 618 164 062 59 007 199 254 740 992 53 0.000 000 000 000 000 111 022 302 462 515 654 042 363 166 809 082 031 2518014398509 481984 54 0.000 000 000 000 000 055511 151231257827021 18158340454101562536 028 797018 963 968 55 0.000 000 000 000 000 027 755 575 615 628 913 510 590 791 702 270 507 812 572 057 594037 927936 56 0.000 000 000 000 006 013 877 787 807 814 456 755 295 395 851 135 253 906 25144 115 188 075 855 872 57 0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626 953 125288 230 376 151 711 744 58 0.000 000 000 000 000 003 469 446 931 953614 188 823 848 962 783813476 562 5576 460 752 303 423 488 59 0.000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281 251 152 921 504 606 846 976 6IJ 0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 6252 305 843 009 213 693 952 61 0.000 000 000 000 000 000 433 680 868 994201 773602 981 120 347 976 684 570 312 54 611.086 018 427 387 904 62 0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 56IJ 173 988 342 285 156 259 223 372 036 854 775 808 63 0.000 000 000 000 000 000 108 420 217 248 550 443 400 745 280 086 994 171 142 578 125Appendix A 191

APPENDIX B.GLOSSARY OF SYMBOLIC TERMSTermMeaningTermMeaning( )nuContents of.AND (logical product, where 0 n 0 = 0,o n 1 = 0, 1· n 0 = 0, and 1 n 1 = 1).OR (logical inclusive OR, where 0 u 0 = 0,o u 1 = 1, 1 u 0 = 1, and 1 u 1 = 1) •EDL(cont .)EDOforced to O. Hence, odd-numbered wordaddress (referring to middle of doubleword)des ignates same doub I eword as even-numberedword address when used for a doub I ewordoperation.Effective decimal operand.@AMCCCIDADBSDECADMEBEBLEDEDLEOR {logical exclusive OR, whereo @ 0 = 0, 0 @ 1 = 1, 1 @ 0 = 1,and 1 @ 1 = 0).Fixed-point arithmetic trap mask-bit position 11 of PSWs. If set (= 1 ), bas i c processortraps to location X'43' after executing aninstruction causing fixed-point overflow; ifnot set, basi c processor does not trap.Condition code - 4-bit value (bit positionslabeled CC1, CC2, CC3, and CC4), establishedas part of the execution of mostinstructions.Counter interrupt group inhibit - bit position37 of PSWs. If set (=1), all interruptlevels within this group are inhibited.Destination address-in byte-string instructions,address of the destination byte string.Destination byte string-operand specifiedby byte-string instruction.Decimal accumulator - general registers 12,13, 14, and 15 in decimal instructions.Decimal arithmetic trap mask-bit position 10or PS'v'Vs. 'vVnen set (= i), deci rna I aritnmeti cfault trap is in effect.Effective byte - 8-bit contents of effectivebyte location (EBL).Effective byte location - byte locationpointed to by effective virtual address of aninstruction for byte operation.Effective doubleword - 64-bit contents ofeffective doubleword location (EDL).Effective doubieword iocation-doublewordlocation pointed to by effective virtualaddress of an instruction for a doublewordoperation. If odd-numbered word locationis specifi ed, low-order bit of effective addressfield (bit position 31) is automaticallyEHEH LEIESAEVAEWEWLFNFRFSEffective halfword - 16-bit contents ofeffective halfword location, or (EHL).Effective halfword location-halfword locationpointed to by effective virtual addressof an instruction for halfword operation.External interrupt group inhibit - bitposition 39 of PSWs. If set (= 1), allinterrupt levels within this group areinhibited.Effective source address - in byte-stringinstructi ons, address of the source bytestring.Effective virtual address - virtual addressvalue obtained as result of indirect addressingand/or indexing. This address value isindependent of the program's actual locationin main memory, and is final addressvalue before memory mapping is performed.Effective word - 32-bit contents of effectiveword location (EWL).Effective word location - word locationpointed to by effective virtual address ofan instruction for a word operation.Floating normalize mode control-bit position7 of PSWs. If not set, results offloatingpointadditions and subtractions are to benormalized; if set (=1), results are notnormalized.Floating round mode control-bit position 40fPSWs. If set (=1), basic processor roundsfloating-point results. If not set, resultsare truncated.Floating significance mode control-bit position5 of PSWs. If set (=1), basic processortraps to location X'44' when more than twohexadecimal places of postnormalizationshifting are required for a floating-point additionor subtraction; if not set, no significancechecking is performed.192 Appendix B

TermMeaningTermMeaningFZFloating zero mode control-bit position 6of the PSWs. If set (=1), basic processortraps to location X·44· when either characteristicunderflow or zero result occurs fora floating-point multiplication or division;if not set, characteristic underflow and zeroresu It are treated as normal conditions.Ref.Add.(cont .)general register in current register block(by using a value in range 0-15) or any wordin main memory in address range 16 through131,071. This address value is initial addressvalue for any subsequent address computations,memory mapping, or bothcomputation and mapping.Instruction register-internal basic processorregister that holds instructions obtained frommemorywhile they are being decoded.RPRegister pointer - bit positions 58 and 59 ofPSWs; these bits select one of four possibleregister blocks.IAIILMAMMMSInstruction address- 17~bit value that definesvirtual address of instruction immediatelyprior to the time that it is executed.I/o interrupt group inhibit - bit position 38of the PSWs. If set (=1), all interrupt levelswithin this group are inhibited.Numeric value of bits 8-11 of decimal instructionword (value of. 0 is 16 bytes).Mode altered - bit position 61 of PSWs.This bit is set (= 1) during master-protectedmode of operation and during real extendedtype of addressing.Memory map mode control-position 9 ofPSWs. When set (=1), the memory map isin effect.Master/slave mode control-bit position 8of PSWs. When set (=1), basic processor isin slave mode; when not set, basic processormay be in master or master-protectedmode as determined by bit 40.Ru1SASBSSEOdd register address value - register Ru1 isgeneral register pointed to by value obtainedby logically ORing 0001 into address forregister R. Thus, if R field of instructioncontains even value, Ru 1 = R + 1 and if Rfield contains odd value, Ru1 = R.Source address - in byte-string instructions,contents of speci fi ed R reg ister.Source byte string-operand specified bybyte string instruction.Sign extension - some instructions operateon two operands of different lengths; theyare made equal in length by extendingsign of shorter operand by required numberof bit positions. For positive operands,result of sign extension is high-order O·sprefixed TO Tne operano; Tor negative operands,high-order l·s are prefixed to operand.Sign extension process is performedafter operand accessed from memory andbefore operation called for by instructioncode is performed.PSWsProgram status words - collection of separateregisters and flip-flops treated as aninternal basi c processor register to store anddisplay criti cal control information.SPDStack pointer doubleword - contains thecontext (TSA, space count, word count, andTS, TW inhibit bits) of the push-downinstructions.RRAGeneral register address value-4-bit contentsof bit positions 8-11 (R field) ofinstruction word, also expressedsymbolicallyas (I)8-11. In instruction descri ptions, registerR is general register (of current registerblock) that corresponds to R fi eld addressvalue.Register altered - bit position 60 of PSWs.When trap occurs, this bit set (= 1) when generalregister or memory location altered inexecution of instruction causing the trap.TCCTSTSATrap condition code - 4-bit value (bitpositions labeled TCC1, TCC2, TCC3,and TCC4), established as part of trapoperations.Trap-on-space inhibit bit - conditions pushdownstack limit trap for impending overflowor underflow of space count.Top-of-stack address - pointer that pointsto highest-numbered address of operand stackin push-down instructions.Ref.Add.Reference address - contents of bit positions15-31 of instruction word, a 17-bitfield capable of directly addressing anyTWTrap-on-word inhibit bit-conditions pushdownstack limit trap for impending overflowor underflow of word count.Appendix B 193

TermMeaningTermMeaningWKxWrite key - bit positions 32, 33, 34,and 35 of PSWs; they are evaluated bythe memory write-protect feature to determineaccessibility of real memory bycurrent program.Index register address value - 3-bit contentsof bit positions 12-14 (X field) ofinstruction word. In instruction word,if X = 0, no indexing is performed;X(cont .)Xln lif X f 0, indexing is performed (after indirectaddressing if indirect addressing is called for)with general registerX in current registerblock.Hexadecimal qualifier - hexadecimal value(n) is unsigned string of hexadecimal digits(0 through 9 and A through F}surrounded bysingle quotation marks and preceded by thequalifier "X" (for example, 7B0 16is writtenX?BO I •194 Appendix B

APPENDIX C.FAULT STATUS REGISTERSTable C-1. Fault Status RegistersStatus Registers - Faults Detected By:BitSystem ControlPosition Basic Processor MIOP RMP MI PI Processor0 16 PFI PFI PFI PFI PFI PFI1 17 General register Bus Check Fault BCF Mapor access- Cluster bus Parity error onparity error (BCF) protect register parity error processor buspari ty error2 18 Control register ·Control Check CCF Cluster bus Processor bus Operationparity error Fault (CCF) parity error parity error code error3 19 Internal basic processor Control Memory CMF Reserved Unrecognized Reservedbus pari ty error Fault (CMF) operation code4 20 Clusterbus parity error CMF I/o adapter ECE Reserved Reserved Reserved5 21 Processor-Detected MIE MIE Cluster bus Reserved ReservedFault flag (PDF)sequence checkfault6 22 Memory parity error Data/order Order Reserved Reserved Reservedindicator t type t7 23 Memory Interface Out indicator t Order Reserved Multiple error ReservedError (MIE)type t8 24 Processor interface Contro I Memory Reserved Reserved Control Memory Reservedsequence check Fault (CMF) Fault (CMF)fault address bit 0 address bit 09 25 Extended arithmetic CMF Reserved Reserved CMF Reserved~'"'_ ..'"'__'"' _L__ L !'_.. IL _1.1 I •• 'I~"""''1'''''''''''' I """v """llv\,,,o~ I \..IV II UUUI t::>:> on Iaddress bit 110 26 Basi c processor CMF Reserved Reserved CMF Reservedsequence check fau It address bit 2 address bit 211 27 Successfu I instruc- CMF Reserved Reserved CMF Reservedtion retry address bit 3 address bit 312 28 Control memory parity CMF Reserved Reserved CMF Reservederror (BPE module) address bit 4 address bit 413 29 Control memory parity CMF Reserved Reserved CMF Reservederror (BPF module) address bit 5 address bit 514 30 Control memory parity CMF Reserved Reserved CMF Reservederror (B PG modu Ie) address bit 6 address bit 615 31 Control memory parity CMF Reserved Reserved CMF Reservederror (BPH module) address bit 7 address bit 7tThis is a 2-bit code indicating type of service call, as follows:Bits MIOP RMP-6 7 Signifi cance Significance- -0 0 Data In Sense0 1 Data Out Write1 0 Order In Read1 1 Order Out ControlAppendix C 195

Table C-2. Memory Unit Status RegisterBit PositionFau Its Detected by Memory Unit:0-21 Fau It address snapshot22 Reserved23 Memory unit parity error24 Storage module selection error25 Address In parity error26 Data In parity error27 Write-lock memory storage parity error28 Port se I ect i on error29 Operation mode undefined30 Control sequence check fault error31 Multiple error196 Appendix C

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