VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

VLSISolution yVS1033cVS1033CCONTENTSContents1 Licenses 92 Disclaimer 93 Definitions 94 Characteristics & Specifications 104.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.3 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.5 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.6 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . . 125 Packages and Pin Descriptions 135.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.1.1 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.1.2 BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.2 LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Connection Diagram, LQFP-48 167 SPI Buses 177.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177.2.1 VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . . 17Version 1.00, 2008-02-01 2

VLSISolution yVS1033cVS1033CCONTENTS7.2.2 VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177.3 Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.4 Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . 187.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.4.2 SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . 187.4.3 SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . 197.4.4 Passive SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197.5 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . . 197.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197.5.2 SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.5.3 SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.5.4 SCI Multiple Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.6 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.7 SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . . 237.7.1 Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.7.2 Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.7.3 SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . . 248 Functional Description 258.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258.2 Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258.2.1 Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . . . . . . . 258.2.2 Supported MP1 (MPEG layer I) Formats . . . . . . . . . . . . . . . . . . . . . 268.2.3 Supported MP2 (MPEG layer II) Formats . . . . . . . . . . . . . . . . . . . . . 268.2.4 Supported AAC (ISO/IEC 13818-7) Formats . . . . . . . . . . . . . . . . . . . 27Version 1.00, 2008-02-01 3

VLSISolution yVS1033cVS1033CCONTENTS9.4 ADPCM Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469.4.1 Activating ADPCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469.4.2 Reading IMA ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469.4.3 Adding a RIFF Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479.4.4 Playing ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489.4.5 Sample Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489.4.6 AD Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489.4.7 Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489.5 SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509.6 Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509.7 Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519.8 Extra Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529.8.1 Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539.8.2 WMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539.8.3 AAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549.8.4 Midi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549.9 Fast Forward / Rewind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.9.1 AAC - ADTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.9.2 AAC - ADIF, MP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.9.3 WMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569.9.4 Midi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569.10 SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579.10.1 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579.10.2 Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Version 1.00, 2008-02-01 5

VLSISolution yVS1033cVS1033CCONTENTS9.10.3 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589.10.4 SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5810 VS1033 Registers 5910.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.3 VS1033 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6010.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6110.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6210.9 A/D Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6310.10Watchdog v1.0 2002-08-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6410.10.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6410.11UART v1.1 2004-10-09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.11.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.11.2 Status UARTx STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.11.3 Data UARTx DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6610.11.4 Data High UARTx DATAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6610.11.5 Divider UARTx DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6610.11.6 Interrupts and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6710.12Timers v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6810.12.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6810.12.2 Configuration TIMER CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . 68Version 1.00, 2008-02-01 6

VLSISolution yVS1033cVS1033CCONTENTS10.12.3 Configuration TIMER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.12.4 Timer X Startvalue TIMER Tx[L/H] . . . . . . . . . . . . . . . . . . . . . . . 6910.12.5 Timer X Counter TIMER TxCNT[L/H] . . . . . . . . . . . . . . . . . . . . . . 6910.12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910.13I2S DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7010.13.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7010.13.2 Configuration I2S CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7010.14System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7110.14.1 AudioInt, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7110.14.2 SciInt, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7110.14.3 DataInt, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7110.14.4 ModuInt, 0x23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7110.14.5 TxInt, 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.14.6 RxInt, 0x25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.14.7 Timer0Int, 0x26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.14.8 Timer1Int, 0x27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7210.14.9 UserCodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7310.15System Vector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7310.15.1 WriteIRam(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7310.15.2 ReadIRam(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7310.15.3 DataBytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7310.15.4 GetDataByte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7410.15.5 GetDataWords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7411 Document Version Changes 75Version 1.00, 2008-02-01 7

VLSISolution yVS1033cVS1033CLIST OF FIGURES12 Contact Information 76List of Figures1 Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . 164 BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 SCI Multiple Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2210 Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311 Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2312 Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . . 2413 Data Flow of VS1033. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3214 EarSpeaker externalized sound sources vs. normal inside-the-head sound . . . . . . . . . 3315 ADPCM Frequency Responses with 8 kHz sample rate. . . . . . . . . . . . . . . . . . . 3716 User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6017 RS232 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6518 I2S Interface, 192 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Version 1.00, 2008-02-01 8

VLSISolution yVS1033cVS1033C1. LICENSES1 LicensesMPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson.Note: if you enable Layer I and Layer II decoding, you are liable for any patent issues that mayarise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patentspertaining to layers I and II.VS1033 contains WMA decoding technology from Microsoft.This product is protected by certain intellectual property rights of Microsoft and cannot be usedor further distributed without a license from Microsoft.VS1033 contains AAC technology (ISO/IEC 13818-7) which cannot be used without a proper licensefrom Via Licensing Corporation or individual patent holders.To the best of our knowledge, if the end product does not play a specific format that otherwise wouldrequire a customer license: MPEG 1.0/2.0 layers I and II, WMA, or AAC, the respective license shouldnot be required. Decoding of MPEG layers I and II are disabled by default, and WMA and AAC formatexclusion can be easily performed based on the contents of the SCI HDAT1 register.2 DisclaimerThis is a preliminary datasheet. All properties and figures are subject to change.3 DefinitionsB Byte, 8 bits.b Bit.Ki “Kibi” = 2 10 = 1024 (IEC 60027-2).Mi “Mebi” = 2 20 = 1048576 (IEC 60027-2).VS DSP VLSI Solution’s DSP core.W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide.Version 1.00, 2008-02-01 9

VLSISolution yVS1033cVS1033C4. CHARACTERISTICS & SPECIFICATIONS4 Characteristics & Specifications4.1 Absolute Maximum RatingsParameter Symbol Min Max UnitAnalog Positive Supply AVDD -0.3 3.6 VDigital Positive Supply CVDD -0.3 2.7 VI/O Positive Supply IOVDD -0.3 3.6 VCurrent at Any Non-Power Pin 1 ±50 mAVoltage at Any Digital Input -0.3 IOVDD+0.3 2 VOperating Temperature -40 +85 ◦ CStorage Temperature -65 +150 ◦ C1 Higher current can cause latch-up.2 Must not exceed 3.6 V.4.2 Recommended Operating ConditionsParameter Symbol Min Typ Max UnitAmbient Operating Temperature -30 +85 ◦ CAnalog and Digital Ground 1 AGND DGND 0.0 VPositive Analog AVDD 2.7 2.8 3.6 VPositive Digital CVDD 2.4 2.5 2.7 VI/O Voltage IOVDD CVDD-0.6V 2.8 3.6 VInput Clock Frequency 2 XTALI 12 12.288 13 MHzInput Clock Freq., SM CLK RANGE set 2 XTALI 24 24.576 26 MHzInternal Clock Frequency CLKI 12 36.864 50 MHzInternal Clock Multiplier 3 1.0× 3.0× 4.5×Master Clock Duty Cycle 40 50 60 %1 Must be connected together as close the device as possible for maximum latch-up immunity.2 The maximum sample rate that can be played with correct speed is XTALI/256 (or XTALI/512 ifSM CLK RANGE is set). Thus, XTALI must be at least 12.288 MHz (24.576 MHz) to be able to play48 kHz at correct speed.3 Reset value is 1.0×. Recommended SC MULT=3.0×, SC ADD=1.0× (SCI CLOCKF=0x9000). Donot exceed Max CLKI.Version 1.00, 2008-02-01 10

VLSISolution yVS1033cVS1033C4. CHARACTERISTICS & SPECIFICATIONS4.3 Analog CharacteristicsUnless otherwise noted: AVDD=2.7..2.85V, CVDD=2.4..2.7V, IOVDD=CVDD-0.6V..3.6V, TA=-30..+85 ◦ C,XTALI=12..13MHz, Internal Clock Multiplier 3.5×. DAC tested with 1307.894 Hz full-scale outputsinewave, measurement bandwidth 20..20000 Hz, full analog output load: LEFT to GBUF 30 Ω, RIGHTto GBUF 30 Ω. Microphone test amplitude 30 mVpp per input pin, f=1 kHz. Line input test amplitude2.2 Vpp, f=1 kHz. ADC sample rate 48 kHz.Parameter Symbol Min Typ Max UnitDAC Resolution 18 bitsTotal Harmonic Distortion THD 0.1 0.4 %Dynamic Range (DAC unmuted, A-weighted) IDR 90 dBS/N Ratio (full scale signal) SNR 70 85 dBInterchannel Isolation (Cross Talk) 75 dBInterchannel Isolation (Cross Talk), with GBUF 40 dBInterchannel Gain Mismatch -0.5 ±0.04 0.5 dBFrequency Response -0.1 0.1 dBFull Scale Output Voltage (Peak-to-peak) 1.3 1.5 1 1.8 VppDeviation from Linear Phase 5◦Analog Output Load Resistance AOLR 16 30 2 ΩAnalog Output Load Capacitance 3 100 pFMicrophone input amplifier gain MICG 26 dBMicrophone input amplitude, balanced 60 140 4 mVppMicrophone Total Harmonic Distortion MTHD 0.02 0.10 %Microphone S/N Ratio MSNR 60 66 dBLine input amplitude 2200 AVDD 4 mVppLine input Total Harmonic Distortion LTHD 0.02 0.10 %Line input S/N Ratio LSNR 75 86 dBLine and Microphone input impedances 100 kΩ1 3.0 volts can be achieved with +-to-+ wiring for differential mono sound.2 AOLR may be much lower, but below Typical distortion performance may be compromised.3 Requires ESD protection as shown in Figure 3.4 Above typical amplitude Total Harmonic Distortion increases.Version 1.00, 2008-02-01 11

VLSISolution yVS1033cVS1033C4. CHARACTERISTICS & SPECIFICATIONS4.4 Power ConsumptionOutput at full volume. Internal clock multiplier 3.0×.Reset Min Typ Max UnitPower Supply Consumption AVDD 0.6 20 1 µAPower Supply Consumption CVDD = 2.5V 3.7 40 1 µAPower Supply Consumption IOVDD 3 12 1 µASine Test Min Typ Max UnitPower Supply Consumption AVDD, sine test, 30Ω + GBUF 36 45 mAPower Supply Consumption CVDD = 2.5V 13 18 mAMPEG 1.0 Layer-3 128 kbps music sample Min Typ Max UnitPower Supply Consumption AVDD, no load 7 mAPower Supply Consumption AVDD, output load 30Ω 11 mAPower Supply Consumption AVDD, 30Ω + GBUF 16 mAPower Supply Consumption CVDD = 2.5V 14 mA1 Numbers are this high only at maximum temperature +85 ◦ C.4.5 Digital CharacteristicsParameter Symbol Min Typ Max UnitHigh-Level Input Voltage 0.7×IOVDD IOVDD+0.3 1 VLow-Level Input Voltage -0.2 0.3×IOVDD VHigh-Level Output Voltage at I O = -1.0 mA 2 0.7×IOVDD VLow-Level Output Voltage at I O = 1.0 mA 2 0.3×IOVDD VInput Leakage Current -1.0 1.0 µACLKI7MHzSPI Input Clock Frequency 2Rise time of all output pins, load = 50 pF 50 ns1 Must not exceed 3.6V2 Exception: ±0.35 mA for XTALO.3 Value for SCI reads. SCI and SDI writes allow CLKI4.4.6 Switching Characteristics - Boot InitializationParameter Symbol Min Max UnitXRESET active time 2 XTALIXRESET inactive to software ready 20000 50000 1 XTALIPower on reset, rise time to CVDD 10 V/s1 DREQ rises when initialization is complete. You should not send any data or commands before that.Version 1.00, 2008-02-01 12

1.10 REFVLSISolution yVS1033cVS1033C5. PACKAGES AND PIN DESCRIPTIONS5 Packages and Pin Descriptions5.1 PackagesBoth LPQFP-48 and BGA-49 are lead (Pb) free and also RoHS compliant packages. RoHS is a shortname of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electricaland electronic equipment.5.1.1 LQFP-48148Figure 1: Pin Configuration, LQFP-48.LQFP-48 package dimensions are at http://www.vlsi.fi/ .5.1.2 BGA-49A1 BALL PAD CORNER1 2 3 4 5 6 7ABCDE0.80 TYP4.807.00FG1.10 REF0.80 TYP4.807.00TOP VIEWFigure 2: Pin Configuration, BGA-49.BGA-49 package dimensions are at http://www.vlsi.fi/ .Version 1.00, 2008-02-01 13

VLSISolution yVS1033cVS1033C5. PACKAGES AND PIN DESCRIPTIONS5.2 LQFP-48 and BGA-49 Pin DescriptionsPad NameLQFPPinBGABallPinTypeFunctionMICP 1 C3 AI Positive differential microphone input, self-biasingMICN 2 C2 AI Negative differential microphone input, self-biasingXRESET 3 B1 DI Active low asynchronous reset, schmitt-trigger inputDGND0 4 D2 DGND Core & I/O groundCVDD0 5 C1 CPWR Core power supplyIOVDD0 6 D3 IOPWR I/O power supplyCVDD1 7 D1 CPWR Core power supplyDREQ 8 E2 DO Data request, input busGPIO2 / DCLK 1 9 E1 DIO General purpose IO 2 / serial input data bus clockGPIO3 / SDATA 1 10 F2 DIO General purpose IO 3 / serial data inputGPIO6 11 F1 DIO General purpose IO 6GPIO7 12 G1 DIO General purpose IO 7XDCS / BSYNC 1 13 E3 DI Data chip select / byte syncIOVDD1 14 F3 IOPWR I/O power supplyVCO 15 G2 DO For testing only (Clock VCO output)DGND1 16 F4 DGND Core & I/O groundXTALO 17 G3 AO Crystal outputXTALI 18 E4 AI Crystal inputIOVDD2 19 G4 IOPWR I/O power supplyIOVDD3 (19) F5 IOPWR I/O power supplyDGND2 20 (G5) DGND Core & I/O groundDGND3 21 G5 DGND Core & I/O groundDGND4 22 F6 DGND Core & I/O groundXCS 23 G6 DI Chip select input (active low)CVDD2 24 G7 CPWR Core power supplyGPIO5 / I2S MCLK 3 25 E5 DIO General purpose IO 5 / I2S MCLKRX 26 E6 DI UART receive, connect to IOVDD if not usedTX 27 F7 DO UART transmitSCLK 28 D6 DI Clock for serial busSI 29 E7 DI Serial inputSO 30 D5 DO3 Serial outputCVDD3 31 D7 CPWR Core power supplyTEST 32 C6 DI Reserved for test, connect to IOVDDGPIO0 / I2S SCLK 3 33 C7 DIO General purpose IO 0 (SPIBOOT) / I2S SCLKuse 100 kΩ pull-down resistor 2GPIO1 / I2S SDATA 3 34 B6 DIO General purpose IO 1 / I2S SDATAGND 35 B7 DGND I/O GroundGPIO4 / I2S LROUT 3 36 A7 DIO General purpose IO 4 / I2S LROUTAGND0 37 C5 APWR Analog ground, low-noise referenceAVDD0 38 B5 APWR Analog power supplyRIGHT 39 A6 AO Right channel outputAGND1 40 B4 APWR Analog groundAGND2 41 A5 APWR Analog groundGBUF 42 C4 AO Common buffer for headphones, do NOT connect toground!AVDD1 43 A4 APWR Analog power supplyRCAP 44 B3 AIO Filtering capacitance for referenceAVDD2 45 A3 APWR Analog power supplyLEFT 46 B2 AO Left channel outputAGND3 47 A2 APWR Analog groundLINEIN 48 A1 AI Line inputVersion 1.00, 2008-02-01 14

VLSISolution yVS1033cVS1033C5. PACKAGES AND PIN DESCRIPTIONS1 First pin function is active in New Mode, latter in Compatibility Mode.2 Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.5 for details.3 If I2S CF ENA is ’0’ the pins are used for GPIO. See Chapter 10.13 for details.Pin types:TypeDIDODIODO3AIDescriptionDigital input, CMOS Input PadDigital output, CMOS Input PadDigital input/outputDigital output, CMOS Tri-stated Output PadAnalog inputTypeAOAIOAPWRDGNDCPWRIOPWRDescriptionAnalog outputAnalog input/outputAnalog power supply pinCore or I/O ground pinCore power supply pinI/O power supply pinIn BGA-49, D4 is a no-connect ball.Version 1.00, 2008-02-01 15

VLSISolution yVS1033cVS1033C6. CONNECTION DIAGRAM, LQFP-486 Connection Diagram, LQFP-48Figure 3: Typical Connection Diagram Using LQFP-48.The common buffer GBUF can be used for common voltage (1.24 V) for earphones. This will eliminatethe need for large isolation capacitors on line outputs, and thus the audio output pins from VS1033 maybe connected directly to the earphone connector.GBUF must NOT be connected to ground in any circumstance. If GBUF is not used, LEFT and RIGHTmust be provided with coupling capacitors. To keep GBUF stable, you should always have the resistorand capacitor even when GBUF is not used. See application notes for details.Unused GPIO pins should have a pull-down resistor. If UART is not used, RX should be connected toIOVDD and TX be unconnected. Do not connect any external load to XTALO.Note: This connection assumes SM SDINEW is active (see Chapter 8.7.1). If also SM SDISHARE isused, xDCS should be tied low or high (see Chapter 7.2.1).Version 1.00, 2008-02-01 16

VLSISolution yVS1033cVS1033C7. SPI BUSES7 SPI Buses7.1 GeneralThe SPI Bus - that was originally used in some Motorola devices - has been used for both VS1033’sSerial Data Interface SDI (Chapters 7.4 and 8.5) and Serial Control Interface SCI (Chapters 7.5 and 8.6).7.2 SPI Bus Pin Descriptions7.2.1 VS1002 Native Modes (New Mode)These modes are active on VS1033 when SM SDINEW is set to 1 (default at startup). DCLK andSDATA are not used for data transfer and they can be used as general-purpose I/O pins (GPIO2 andGPIO3). BSYNC function changes to data interface chip select (XDCS).SDI Pin SCI Pin DescriptionXDCS XCS Active low chip select input. A high level forces the serial interface intostandby mode, ending the current operation. A high level also forces serialoutput (SO) to high impedance state. If SM SDISHARE is 1, pinXDCS is not used, but the signal is generated internally by invertingXCS.SCK Serial clock input. The serial clock is also used internally as the masterclock for the register interface.SCK can be gated or continuous. In either case, the first rising clock edgeafter XCS has gone low marks the first bit to be written.SI Serial input. If a chip select is active, SI is sampled on the rising CLK edge.- SO Serial output. In reads, data is shifted out on the falling SCK edge.In writes SO is at a high impedance state.7.2.2 VS1001 Compatibility ModeThis mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active.SDI Pin SCI Pin Description- XCS Active low chip select input. A high level forces the serial interface intostandby mode, ending the current operation. A high level also forces serialoutput (SO) to high impedance state.BSYNC - SDI data is synchronized with a rising edge of BSYNC.DCLK SCK Serial clock input. The serial clock is also used internally as the masterclock for the register interface.SCK can be gated or continuous. In either case, the first rising clock edgeafter XCS has gone low marks the first bit to be written.SDATA SI Serial input. SI is sampled on the rising SCK edge, if XCS is low.- SO Serial output. In reads, data is shifted out on the falling SCK edge.In writes SO is at a high impedance state.Version 1.00, 2008-02-01 17

VLSISolution yVS1033cVS1033C7. SPI BUSES7.3 Data Request Pin DREQThe DREQ pin/signal is used to signal if VS1033’s 2048-byte FIFO is capable of receiving data. IfDREQ is high, VS1033 can take at least 32 bytes of SDI data or one SCI command. DREQ is turned lowwhen the stream buffer is too full and for the duration of a SCI command.Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time withoutchecking the status of DREQ, making controlling VS1033 easier for low-speed microcontrollers.Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ shouldonly be used to decide whether to send more bytes. It does not need to abort a transmission that hasalready started.Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1003 and VS1033 DREQis also used to tell the status of SCI.There are cases when you still want to send SCI commands when DREQ is low. Because DREQ isshared between SDI and SCI, you can not determine if a SCI command has been executed if SDI is notready to receive. In this case you need a long enough delay after every SCI command to make certainnone of them is missed. The SCI Registers table in section 8.7 gives the worst-case handling time foreach SCI register write.7.4 Serial Protocol for Serial Data Interface (SDI)7.4.1 GeneralThe serial data interface operates in slave mode so DCLK signal must be generated by an external circuit.Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.7).VS1033 assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSbfirst, depending of contents of SCI MODE (Chapter 8.7.1).The firmware is able to accept the maximum bitrate the SDI supports.7.4.2 SDI in VS1002 Native Modes (New Mode)In VS1002 native modes (SM NEWMODE is 1), byte synchronization is achieved by XDCS. The state ofXDCS may not change while a data byte transfer is in progress. To always maintain data synchronizationeven if there may be glitches in the boards using VS1033, it is recommended to turn XDCS every nowand then, for instance once after every flash data block or a few kilobytes, just to keep sure the host andVS1033 are in sync.If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.For new designs, using VS1002 native modes are recommended.Version 1.00, 2008-02-01 18

VLSISolution yVS1033cVS1033C7. SPI BUSES7.4.3 SDI in VS1001 Compatibility ModeBSYNCSDATAD7 D6 D5 D4 D3 D2 D1 D0DCLKFigure 4: BSYNC Signal - one byte transfer.When VS1033 is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensurecorrect bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, dependingon selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-firstorder is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiverstays active and next 8 bits are also received.BSYNCSDATAD7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0DCLKFigure 5: BSYNC Signal - two byte transfer.7.4.4 Passive SDI ModeIf SM NEWMODE is 0 and SM SDISHARE is 1, the operation is otherwise like the VS1001 compatibilitymode, but bits are only received while the BSYNC signal is ’1’. Rising edge of BSYNC is stillused for synchronization.7.5 Serial Protocol for Serial Command Interface (SCI)7.5.1 GeneralThe serial bus protocol for the Serial Command Interface SCI (Chapter 8.6) consists of an instructionbyte, address byte and one 16-bit data word. Each read or write operation can read or write a singleregister. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytesare always send MSb first. XCS should be low for the full duration of the operation, but you can havepauses between bits if needed.The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.See table below.InstructionName Opcode OperationREAD 0b0000 0011 Read dataWRITE 0b0000 0010 Write dataNote: VS1033 sets DREQ low after each SCI operation. The duration depends on the operation. It is notallowed to finish a new SCI/SDI operation before DREQ is high again.Version 1.00, 2008-02-01 19

VLSISolution yVS1033cVS1033C7. SPI BUSES7.5.2 SCI ReadXCSSCK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1730 31SI0 0 0 0 0 0 1 1 0 0 0 03 2 1 0don’t caredon’t careinstruction (read)addressdata outSO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 015 14 1 0XexecutionDREQFigure 6: SCI Word ReadVS1033 registers are read from using the following sequence, as shown in Figure 6. First, XCS line ispulled low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed byan 8-bit word address. After the address has been read in, any further data on SI is ignored by the chip.The 16-bit data corresponding to the received address will be shifted out onto the SO line.XCS should be driven high after data has been shifted out.DREQ is driven low for a short while when in a read operation by the chip. This is a very short time anddoesn’t require special user attention.7.5.3 SCI WriteXCSSCK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1730 31SI0 0 0 0 0 0 1 0 0 0 0 03 2 1 0 15 141 0Xinstruction (write)addressdata outSO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XexecutionDREQFigure 7: SCI Word WriteVS1033 registers are written from using the following sequence, as shown in Figure 7. First, XCS lineis pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followedby an 8-bit word address.Version 1.00, 2008-02-01 20

VLSISolution yVS1033cVS1033C7. SPI BUSESAfter the word has been shifted in and the last clock has been sent, XCS should be pulled high to end theWRITE sequence.After the last bit has been sent, DREQ is driven low for the duration of the register update, marked“execution” in the figure. The time varies depending on the register and its contents (see table in Chapter8.7 for details). If the maximum time is longer than what it takes from the microcontroller to feedthe next SCI command or SDI byte, status of DREQ must be checked before finishing the next SCI/SDIoperation.7.5.4 SCI Multiple WriteXCSSCK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1729 30 3132 33m−2m−1SI0 0 0 0 0 0 1 0 0 0 0 03 2 1 015 141 0 15 14X1 0Xinstruction (write)addressSO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0data out 1 data out 2 d.out n0 0 0 00 0 XexecutionexecutionDREQFigure 8: SCI Multiple Word WriteVS1033 allows for the user to send multiple words to the same SCI register, which allows fast SCIuploads, shown in Figure 8. The main difference to a single write is that instead of bringing XCS upafter sending the last bit of a data word, the next data word is sent immediately. After the last data word,XCS is driven high as with a single word write.After the last bit of a word has been sent, DREQ is driven low for the duration of the register update,marked “execution” in the figure. The time varies depending on the register and its contents (see tablein Chapter 8.7 for details). If the maximum time is longer than what it takes from the microcontrollerto feed the next SCI command or SDI byte, status of DREQ must be checked before finishing the nextSCI/SDI operation.Version 1.00, 2008-02-01 21

VLSISolution yVS1033cVS1033C7. SPI BUSEStXCSStWLtWHtXCSHXCS0 1 14 15 1630 31tXCSSCKSISOtZtHtSUtVtDISFigure 9: SPI Timing Diagram.7.6 SPI Timing DiagramSymbol Min Max UnittXCSS 5 nstSU 0 nstH 2 CLKI cyclestZ 0 nstWL 2 CLKI cyclestWH 2 CLKI cyclestV 2 (+25 ns 1 ) CLKI cyclestXCSH 1 CLKI cyclestXCS 2 CLKI cyclestDIS 10 ns1 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0×mode, thus CLKI=XTALI. After you have configured a higher clock through SCI CLOCKF and waitedfor DREQ to rise, you can use a higher SPI speed as well.Note: Because tWL + tWH + tH is 6×CLKI + 25 ns, the maximum speed for SCI reads is CLKI/7.Version 1.00, 2008-02-01 22

VLSISolution yVS1033cVS1033C7. SPI BUSES7.7 SPI Examples with SM SDINEW and SM SDISHARED set7.7.1 Two SCI WritesSCI Write 1 SCI Write 2XCS0 1 2 3 30 3132 33 61 62 63SCKSI1 0 2 1 00 0 0 0 X0 0XDREQ up before finishing next SCI writeDREQFigure 10: Two SCI Operations.Figure 10 shows two consecutive SCI operations. Note that xCS must be raised to inactive state betweenthe writes. Also DREQ must be respected as shown in the figure.7.7.2 Two SDI BytesSDI Byte 1SDI Byte 2XCS0 1 2 36 7 8 9 13 14 15SCK7 6 5 4 3 1 0 7 6 5 2 1 0SIXDREQFigure 11: Two SDI Bytes.SDI data is synchronized with a raising edge of xCS as shown in Figure 11. However, every byte doesn’tneed separate synchronization.Version 1.00, 2008-02-01 23

VLSISolution yVS1033cVS1033C7. SPI BUSES7.7.3 SCI Operation in Middle of Two SDI BytesSDI ByteSCI OperationSDI ByteXCS0 178 9 39 40 41 46 47SCKSI7 6 5 10 00 7 6 5 1 0XDREQ high before end of next transferDREQFigure 12: Two SDI Bytes Separated By an SCI Operation.Figure 12 shows how an SCI operation is embedded in between SDI operations. xCS edges are used tosynchronize both SDI and SCI. Remember to respect DREQ as shown in the figure.Version 1.00, 2008-02-01 24

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8 Functional Description8.1 Main FeaturesVS1033 is based on a proprietary digital signal processor, VS DSP. It contains all the code and datamemory needed for MP3, AAC, WMA and WAV PCM + ADPCM audio decoding, MIDI synthesizer,together with serial interfaces, a multirate stereo audio DAC and analog output amplifiers and filters.Also ADPCM audio encoding is supported using a microphone amplifier and A/D converter. A UARTis provided for debugging purposes.8.2 Supported Audio CodecsMarkConventionsDescription+ Format is supported- Format exists but is not supportedFormat doesn’t exist8.2.1 Supported MP3 (MPEG layer III) FormatsMPEG 1.0 1 :Samplerate / HzMPEG 2.0 1 :Samplerate / HzMPEG 2.5 1 :Samplerate / HzBitrate / kbit/s32 40 48 56 64 80 96 112 128 160 192 224 256 32048000 + + + + + + + + + + + + + +44100 + + + + + + + + + + + + + +32000 + + + + + + + + + + + + + +Bitrate / kbit/s8 16 24 32 40 48 56 64 80 96 112 128 144 16024000 + + + + + + + + + + + + + +22050 + + + + + + + + + + + + + +16000 + + + + + + + + + + + + + +Bitrate / kbit/s8 16 24 32 40 48 56 64 80 96 112 128 144 16012000 + + + + + + + + + + + + + +11025 + + + + + + + + + + + + + +8000 + + + + + + + + + + + + + +1 Also all variable bitrate (VBR) formats are supported.Version 1.00, 2008-02-01 25

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.2.2 Supported MP1 (MPEG layer I) FormatsNote: Layer I / II decoding must be specifically enabled from SCI MODE register.MPEG 1.0:Samplerate / HzMPEG 2.0:Samplerate / HzBitrate / kbit/s32 64 96 128 160 192 224 256 288 320 352 384 416 44848000 + + + + + + + + + + + + + +44100 + + + + + + + + + + + + + +32000 + + + + + + + + + + + + + +Bitrate / kbit/s32 48 56 64 80 96 112 128 144 160 176 192 224 25624000 ? ? ? ? ? ? ? ? ? ? ? ? ? ?22050 ? ? ? ? ? ? ? ? ? ? ? ? ? ?16000 ? ? ? ? ? ? ? ? ? ? ? ? ? ?8.2.3 Supported MP2 (MPEG layer II) FormatsNote: Layer I / II decoding must be specifically enabled from SCI MODE register.MPEG 1.0:Samplerate / HzMPEG 2.0:Samplerate / HzBitrate / kbit/s32 48 56 64 80 96 112 128 160 192 224 256 320 38448000 + + + + + + + + + + + + + +44100 + + + + + + + + + + + + + +32000 + + + + + + + + + + + + + +Bitrate / kbit/s8 16 24 32 40 48 56 64 80 96 112 128 144 16024000 + + + + + + + + + + + + + +22050 + + + + + + + + + + + + + +16000 + + + + + + + + + + + + + +Version 1.00, 2008-02-01 26

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.2.4 Supported AAC (ISO/IEC 13818-7) FormatsVS1033 decodes MPEG2-AAC-LC-2.0.0.0 and MPEG4-AAC-LC-2.0.0.0 streams, i.e. the low complexityprofile with maximum of two channels can be decoded. If a stream contains more than one elementand/or element type, you can select which one to decode from the 16 single-channel, 16 channel-pair,and 16 low-frequency elements. The default is to select the first one that appears in the stream.Dynamic range control (DRC) is supported and can be controlled by the user to limit or enhance thedynamic range of the material that has DRC information.Both Sine window and Kaiser-Bessel-derived window are supported.For MPEG4 pseudo-random noise substitution (PNS) is supported. Short frames (120 and 960 samples)are not supported.For AAC the streaming ADTS format is recommended. This format allows easy rewind and fast forwardbecause resynchronization is easily possible.In addition to ADTS (.aac), MPEG2 ADIF (.aac) and MPEG4 AUDIO (.mp4 / .m4a) files are played,but these formats are less suitable for rewind and fast forward operations. You can still implement thesefeatures by using the safe jump points table and seek mechanism provided, or using slightly less robustbut much easier automatic resync mechanism (see Section 9.9).Note: To be able to play the .mp4 and .m4a files, the mdat atom must be the last atom in the MP4 file.Because VS1033 receives all data as a stream, all metadata must be available before the music data isreceived. Several MP4 file formatters do not satisfy this requirement and some kind of conversion isrequired. This is also why the streamable ADTS format is recommended.Programs exist that optimize the .mp4 and .m4a into so-called streamable format that has the mdat atomlast in the file, and thus suitable for web servers’ audio streaming. You can use this kind of tool to processfiles for VS1033 too. For example mp4creator -optimize file.mp4.AAC 12 :Samplerate / HzMaximum Bitrate kbit/s - for 2 channels≤96 132 144 192 264 288 384 529 ≥57648000 + + + + + + + + +44100 + + + + + + + +32000 + + + + + + +24000 + + + + + +22050 + + + + +16000 + + + +12000 + + +11025 + +8000 +1 64000 Hz, 88200 Hz, and 96000 Hz AAC files are played but with wrong speed.2 Also all variable bitrate (VBR) formats are supported. Note that the table gives the maximum bitrateallowed for two channels for a specific sample rate as defined by the AAC specification. The decoderdoes not actually have a lower or upper limit.Version 1.00, 2008-02-01 27

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.2.5 Supported WMA FormatsWindows Media Audio codec versions 2, 7, 8, and 9 are supported. All WMA profiles (L1, L2, and L3)are supported. Previously streams were separated into Classes 1, 2a, 2b, and 3. The decoder has passedMicrosoft’s conformance testing program.WMA 4.0 / 4.1:SamplerateBitrate / kbit/s/ Hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192WMA 7:8000 + + + +11025 + +16000 + + + +22050 + + + +32000 + + + + + +44100 + + + + + + +48000 + +SamplerateBitrate / kbit/s/ Hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192WMA 8:8000 + + + +11025 + +16000 + + + +22050 + + + +32000 + + + +44100 + + + + + + + +48000 + +SamplerateBitrate / kbit/s/ Hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192WMA 9:8000 + + + +11025 + +16000 + + + +22050 + + + +32000 + + + +44100 + + + + + + + +48000 + + +SamplerateBitrate / kbit/s/ Hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192 256 3208000 + + + +11025 + +16000 + + + +22050 + + + +32000 + + + +44100 + + + + + + + + + + +48000 + + + + +In addition to these expected WMA decoding profiles, all other bitrate and samplerate combinations aresupported, including variable bitrate WMA streams. Note that WMA does not consume the bitstream asevenly as MP3, so you need a higher peak transfer capability for clean playback at the same bitrate.Version 1.00, 2008-02-01 28

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.2.6 Supported RIFF WAV FormatsThe most common RIFF WAV subformats are supported.Format Name Supported Comments0x01 PCM + 16 and 8 bits, any sample rate ≤ 48kHz0x02 ADPCM -0x03 IEEE FLOAT -0x06 ALAW -0x07 MULAW -0x10 OKI ADPCM -0x11 IMA ADPCM + Any sample rate ≤ 48kHz0x15 DIGISTD -0x16 DIGIFIX -0x30 DOLBY AC2 -0x31 GSM610 -0x3b ROCKWELL ADPCM -0x3c ROCKWELL DIGITALK -0x40 G721 ADPCM -0x41 G728 CELP -0x50 MPEG -0x55 MPEGLAYER3 + For supported MP3 modes, see Chapter 8.2.10x64 G726 ADPCM -0x65 G722 ADPCM -Version 1.00, 2008-02-01 29

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.2.7 Supported MIDI FormatsGeneral MIDI and SP-MIDI format 0 files are played. Format 1 and 2 files must be converted to format0 by the user. The maximum simultaneous polyphony is 40. Actual polyphony depends on the internalclock rate (which is user-selectable), the instruments used, whether the reverb effect is enabled, andthe possible global postprocessing effects enabled, such as bass enhancer, treble control or EarSpeakerspatial processing. The polyphony restriction algorithm makes use of the SP-MIDI MIP table, if present.36.86 MHz (3.0× input clock) achieves 16-26 simultaneous sustained notes. The instantaneous amountof notes can be larger. 36 MHz is a fair compromise between power consumption and quality, but higherclocks can be used to increase the polyphony.Reverb effect can be controlled by the user. In addition to reverb automatic and reverb off modes, 14different decay times can be selected. These roughly correspond to different room sizes. Also, eachmidi song decides how much effect each instrument gets. Because the reverb effect uses about 4 MHz ofprocessing power the automatic control enables reverb only when the internal clock is at least 3.0×.When EarSpeaker spatial processing is active, MIDI reverb is not used.New instruments have been implemented in addition to the 36 that are available in VS1003. VS1033now has unique instruments in the whole GM1 instrument set and one bank of GM2 percussions.Version 1.00, 2008-02-01 30

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTIONVS1033 Melodic Instruments (GM1)1 Acoustic Grand Piano 33 Acoustic Bass 65 Soprano Sax 97 Rain (FX 1)2 Bright Acoustic Piano 34 Electric Bass (finger) 66 Alto Sax 98 Sound Track (FX 2)3 Electric Grand Piano 35 Electric Bass (pick) 67 Tenor Sax 99 Crystal (FX 3)4 Honky-tonk Piano 36 Fretless Bass 68 Baritone Sax 100 Atmosphere (FX 4)5 Electric Piano 1 37 Slap Bass 1 69 Oboe 101 Brightness (FX 5)6 Electric Piano 2 38 Slap Bass 2 70 English Horn 102 Goblins (FX 6)7 Harpsichord 39 Synth Bass 1 71 Bassoon 103 Echoes (FX 7)8 Clavi 40 Synth Bass 2 72 Clarinet 104 Sci-fi (FX 8)9 Celesta 41 Violin 73 Piccolo 105 Sitar10 Glockenspiel 42 Viola 74 Flute 106 Banjo11 Music Box 43 Cello 75 Recorder 107 Shamisen12 Vibraphone 44 Contrabass 76 Pan Flute 108 Koto13 Marimba 45 Tremolo Strings 77 Blown Bottle 109 Kalimba14 Xylophone 46 Pizzicato Strings 78 Shakuhachi 110 Bag Pipe15 Tubular Bells 47 Orchestral Harp 79 Whistle 111 Fiddle16 Dulcimer 48 Timpani 80 Ocarina 112 Shanai17 Drawbar Organ 49 String Ensembles 1 81 Square Lead (Lead 1) 113 Tinkle Bell18 Percussive Organ 50 String Ensembles 2 82 Saw Lead (Lead) 114 Agogo19 Rock Organ 51 Synth Strings 1 83 Calliope Lead (Lead 3) 115 Pitched Percussion20 Church Organ 52 Synth Strings 2 84 Chiff Lead (Lead 4) 116 Woodblock21 Reed Organ 53 Choir Aahs 85 Charang Lead (Lead 5) 117 Taiko Drum22 Accordion 54 Voice Oohs 86 Voice Lead (Lead 6) 118 Melodic Tom23 Harmonica 55 Synth Voice 87 Fifths Lead (Lead 7) 119 Synth Drum24 Tango Accordion 56 Orchestra Hit 88 Bass + Lead (Lead 8) 120 Reverse Cymbal25 Acoustic Guitar (nylon) 57 Trumpet 89 New Age (Pad 1) 121 Guitar Fret Noise26 Acoustic Guitar (steel) 58 Trombone 90 Warm Pad (Pad 2) 122 Breath Noise27 Electric Guitar (jazz) 59 Tuba 91 Polysynth (Pad 3) 123 Seashore28 Electric Guitar (clean) 60 Muted Trumpet 92 Choir (Pad 4) 124 Bird Tweet29 Electric Guitar (muted) 61 French Horn 93 Bowed (Pad 5) 125 Telephone Ring30 Overdriven Guitar 62 Brass Section 94 Metallic (Pad 6) 126 Helicopter31 Distortion Guitar 63 Synth Brass 1 95 Halo (Pad 7) 127 Applause32 Guitar Harmonics 64 Synth Brass 2 96 Sweep (Pad 8) 128 GunshotVS1033 Percussion Instruments (GM1+GM2)27 High Q 43 High Floor Tom 59 Ride Cymbal 2 75 Claves28 Slap 44 Pedal Hi-hat [EXC 1] 60 High Bongo 76 Hi Wood Block29 Scratch Push [EXC 7] 45 Low Tom 61 Low Bongo 77 Low Wood Block30 Scratch Pull [EXC 7] 46 Open Hi-hat [EXC 1] 62 Mute Hi Conga 78 Mute Cuica [EXC 4]31 Sticks 47 Low-Mid Tom 63 Open Hi Conga 79 Open Cuica [EXC 4]32 Square Click 48 High Mid Tom 64 Low Conga 80 Mute Triangle [EXC 5]33 Metronome Click 49 Crash Cymbal 1 65 High Timbale 81 Open Triangle [EXC 5]34 Metronome Bell 50 High Tom 66 Low Timbale 82 Shaker35 Acoustic Bass Drum 51 Ride Cymbal 1 67 High Agogo 83 Jingle bell36 Bass Drum 1 52 Chinese Cymbal 68 Low Agogo 84 Bell tree37 Side Stick 53 Ride Bell 69 Cabasa 85 Castanets38 Acoustic Snare 54 Tambourine 70 Maracas 86 Mute Surdo [EXC 6]39 Hand Clap 55 Splash Cymbal 71 Short Whistle [EXC 2] 87 Open Surdo [EXC 6]40 Electric Snare 56 Cowbell 72 Long Whistle [EXC 2]41 Low Floor Tom 57 Crash Cymbal 2 73 Short Guiro [EXC 3]42 Closed Hi-hat [EXC 1] 58 Vibra-slap 74 Long Guiro [EXC 3]Version 1.00, 2008-02-01 31

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.3 Data Flow of VS1033SDIBitstreamFIFOMP3WAV/ADPCM/WMA / AAC /MIDI decodeSM_ADPCM=0AIADDR = 0SB_AMPLITUDE=0ST_AMPLITUDE=0UserApplicationBassenhancerTrebleenhancerEarSpeakerAIADDR != 0SB_AMPLITUDE!=0ST_AMPLITUDE!=0VolumecontrolAudioFIFOS.rate.conv.and DACLRSCI_VOL2048 stereosamplesFigure 13: Data Flow of VS1033.First, depending on the audio data, and provided ADPCM encoding mode is not set, MP3, WMA, AAC,PCM WAV, IMA ADPCM WAV, or MIDI data is received and decoded from the SDI bus.After decoding, if SCI AIADDR is non-zero, application code is executed from the address pointed toby that register. For more details, see Application Notes for VS10XX.Then data may be sent to the Bass Enhancer and Treble Control depending on the SCI BASS register.Next, headphone processing is performed, if the EarSpeaker spatial processing is active.After that the signal is fed to the volume control unit, which also copies the data to the Audio FIFO.The Audio FIFO holds the data, which is read by the Audio interrupt (Chapter 10.14.1) and fed to thesample rate converter and DACs. The size of the audio FIFO is 2048 stereo (2×16-bit) samples, or 8KiB.The sample rate converter upsamples all different sample rates to XTALI/2, or 128 times the highest usablesample rate with 18-bit precision. This removes the need for complex PLL-based clocking schemesand allows almost unlimited sample rate accuracy with one fixed input clock frequency. With a 12.288MHz clock, the DA converter operates at 128 × 48 kHz, i.e. 6.144 MHz, and creates a stereo in-phaseanalog signal. The oversampled output is low-pass filtered by an on-chip analog filter. This signal is thenforwarded to the earphone amplifier.Version 1.00, 2008-02-01 32

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.4 EarSpeaker Spatial ProcessingWhile listening to the headphones the sound has a tendency to be localized inside the head. The soundfield becomes flat and lacking the sensation of dimensions. This is unnatural, awkward and sometimeseven disturbing situation. This phenomenon is often referred in literature as ‘lateralization’, meaning’in-the-head’ localization. Long-term listening to lateralized sound may lead to listening fatigue.All real-life sound sources are external, leaving traces to the acoustic wavefront that arrives to the eardrums. From these traces, the auditory system in the brain is able to judge the distance and angle of eachsound source. In loudspeaker listening the sound is external and these traces are available. In headphonelistening these traces are missing or ambiguous.The EarSpeaker processing makes listening via headphones more like listening the same music fromreal loudspeakers or live music. Once the EarSpeaker processing is activated, the instruments are movedfrom inside to the outside of the head, making it easier to separate the different instruments (see figure14). The listening experience becomes more natural and pleasant, and the stereo image is sharper as theinstruments are widely on front of the listener instead of being inside the head.Figure 14: EarSpeaker externalized sound sources vs. normal inside-the-head soundNote that EarSpeaker differs from any common spatial processing effects, such as echo, reverb, or bassboost. EarSpeaker simulates accurately human auditory model and real listening environment acoustics.Thus is does not change the tonal character of the music by introducing artificial effects.EarSpeaker processing can be parameterized to a few different modes, each simulating a little differenttype of acoustical situation and suiting for different personal preference and type of recording. Seesection 8.7.1 for how to activate different modes.• Off: Best option when listening through loudspeakers or if the audio to be played contains binauralpreprocessing• minimal: Suits well for listening to normal musical scores with headphones, very subtle• normal: Suits well for listening to normal musical scores with headphones, moves sound sourcefarther than minimal• extreme: Suits well for old or ’dry’ recordings, or if the audio to be played is artificial, for examplegenerated MIDIVersion 1.00, 2008-02-01 33

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.5 Serial Data Interface (SDI)The serial data interface is meant for transferring compressed MP3, WMA, or AAC data, WAV PCM andADPCM data as well as MIDI data.If the input of the decoder is invalid or it is not received fast enough, analog outputs are automaticallymuted.Also several different tests may be activated through SDI as described in Chapter 9.Version 1.00, 2008-02-01 34

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.6 Serial Control Interface (SCI)The serial control interface is compatible with the SPI bus specification. Data transfers are always 16bits. VS1033 is controlled by writing and reading the registers of the interface.The main controls of the control interface are:• control of the operation mode, clock, and builtin effects• access to status information and header data• access to encoded digital data• uploading user programs8.7 SCI RegistersVS1033 sets DREQ low when it detects an SCI operation and restores it when it has processed theoperation. The duration depends on the operation. If DREQ is low when an SCI operation is performed,it also stays low after SCI operation processing.If DREQ is high before a SCI operation, do not start a new SCI/SDI operation before DREQ is highagain. If DREQ is low before a SCI operation because the SDI can not accept more data, make certainthere is enough time to complete the operation before sending another.SCI registers, prefix SCIReg Type Reset Time 1 Abbrev[bits] Description0x0 rw 0x800 70 CLKI 4 MODE Mode control0x1 rw 0x0C 3 40 CLKI STATUS Status of VS10330x2 rw 0 2100 CLKI BASS Built-in bass/treble enhancer0x3 rw 0 11000 XTALI 5 CLOCKF Clock freq + multiplier0x4 rw 0 40 CLKI DECODE TIME Decode time in seconds0x5 rw 0 3200 CLKI AUDATA Misc. audio data0x6 rw 0 80 CLKI WRAM RAM write/read0x7 rw 0 80 CLKI WRAMADDR Base address for RAM write/read0x8 r 0 - HDAT0 Stream header data 00x9 r 0 - HDAT1 Stream header data 10xA rw 0 3200 CLKI 2 AIADDR Start address of application0xB rw 0 2100 CLKI VOL Volume control0xC rw 0 50 CLKI 2 AICTRL0 Application control register 00xD rw 0 50 CLKI 2 AICTRL1 Application control register 10xE rw 0 50 CLKI 2 AICTRL2 Application control register 20xF rw 0 50 CLKI 2 AICTRL3 Application control register 31 This is the worst-case time that DREQ stays low after writing to this register. The user may choose toskip the DREQ check for those register writes that take less than 100 clock cycles to execute.2 In addition, the cycles spent in the user application routine must be counted.3 Firmware changes the value of this register immediately to 0x58, and in less than 100 ms to 0x50.4 When mode register write specifies a software reset the worst-case time is 20000 XTALI cycles.5 Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not agood idea to send SCI or SDI bits while this register update is in progress.Version 1.00, 2008-02-01 35

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.7.1 SCI MODE (RW)SCI MODE is used to control the operation of VS1033 and defaults to 0x0800 (SM SDINEW set).Bit Name Function Value Description0 SM DIFF Differential 0 normal in-phase audio1 left channel inverted1 SM LAYER12 Allow MPEG layers I & II 0 no1 yes2 SM RESET Soft reset 0 no reset1 reset3 SM OUTOFWAV Jump out of WAV decoding 0 no1 yes4 SM EARSPEAKER LO EarSpeaker low setting 0 off1 active5 SM TESTS Allow SDI tests 0 not allowed1 allowed6 SM STREAM Stream mode 0 no1 yes7 SM EARSPEAKER HI EarSpeaker high setting 0 off1 active8 SM DACT DCLK active edge 0 rising1 falling9 SM SDIORD SDI bit order 0 MSb first1 MSb last10 SM SDISHARE Share SPI chip select 0 no1 yes11 SM SDINEW VS1002 native SPI modes 0 no1 yes12 SM ADPCM ADPCM recording active 0 no1 yes13 SM ADPCM HP ADPCM high-pass filter active 0 no1 yes14 SM LINE IN ADPCM recording selector 0 microphone1 line in15 SM CLK RANGE Input clock range 0 12..13 MHz1 24..26 MHzWhen SM DIFF is set, the player inverts the left channel output. For a stereo input this creates virtualsurround, and for a mono input this creates a differential left/right signal.SM LAYER12 enables MPEG 1.0 and 2.0 layer I and II decoding in addition to layer III. If you enableLayer I and Layer II decoding, you are liable for any patent issues that may arise. Joint licensingof MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II.Software reset is initiated by setting SM RESET to 1. This bit is cleared automatically.If you want to stop decoding a WAV, WMA, or MIDI file in the middle, set SM OUTOFWAV, and senddata honouring DREQ until SM OUTOFWAV is cleared. SCI HDAT1 will also be cleared. For WMAand MIDI it is safest to continue sending the stream, send zeroes for WAV.Bits SM EARSPEAKER LO and SM EARSPEAKER HI control the EarSpeaker spatial processing. Ifboth are 0, the processing is not active. Other combinations activate the processing and select 3 differenteffect levels: LO = 1, HI = 0 selects minimal, LO = 0, HI = 1 selects normal, and LO = 1, HI = 1 selectsextreme. EarSpeaker takes approximately 12 MIPS at 44.1 kHz sample rate. EarSpeaker is automaticallydisabled with AAC files.Version 1.00, 2008-02-01 36

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTIONIf SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 9.10.SM STREAM activates VS1033’s stream mode. In this mode, data should be sent with as even intervalsas possible and preferable in blocks of less than 512 bytes, and VS1033 makes every attempt to keep itsinput buffer half full by changing its playback speed upto 5%. For best quality sound, the average speederror should be within 0.5%, the bitrate should not exceed 160 kbit/s and VBR should not be used. Fordetails, see Application Notes for VS10XX. This mode only works with MP3 and WAV files.SM DACT defines the active edge of data clock for SDI. When ’0’, data is read at the rising edge, when’1’, data is read at the falling edge.When SM SDIORD is clear, bytes on SDI are sent MSb first. By setting SM SDIORD, the user mayreverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still sent in thedefault order. This register bit has no effect on the SCI bus.Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, ifalso SM SDINEW is set.Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 7.2.1 and 7.4.2.Note, that this bit is set as a default when VS1033 is started up.By activating SM ADPCM and SM RESET at the same time, the user will activate IMA ADPCM recordingmode (see section 9.4). If SM ADPCM HP is set (use only for 8 kHz sample rate), ADPCM modewill start with a high-pass filter. This may help intelligibility of speech when there is lots of backgroundnoise. The difference created to the ADPCM encoder frequency response is as shown in Figure 15.5VS1023 AD Converter with and Without HP FilterNo High−PassHigh−Pass0Amplitude / dB−5−10−15−200 500 1000 1500 2000 2500 3000 3500 4000Frequency / HzFigure 15: ADPCM Frequency Responses with 8 kHz sample rate.SM LINE IN is used to select the input for ADPCM recording. If ’0’, microphone input pins MICP andMICN are used; if ’1’, LINEIN is used.SM CLK RANGE activates a clock divider in the XTAL input. When SM CLK RANGE is set, fromthe chip’s point of view e.g. 24 MHz becomes 12 MHz. When used, SM CLK RANGE should be set assoon as possible after a chip reset.Version 1.00, 2008-02-01 37

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.7.2 SCI STATUS (RW)SCI STATUS contains information on the current status of VS1033.Name Bits DescriptionSS VER 6:4 VersionSS APDOWN2 3 Analog driver powerdownSS APDOWN1 2 Analog internal powerdownSS AVOL 1:0 Analog volume controlSS VER is 0 for VS1001, 1 for VS1011, 2 for VS1002, 3 for VS1003, 4 for VS1053, 5 for VS1033, 7for VS1103.SS APDOWN2 controls analog driver powerdown. SS APDOWN1 controls internal analog powerdown.These bits are meant to be used by the system firmware only. Use SCI VOL to control the analog driverpowerdown.SS AVOL is the analog volume control: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. This register is meant to beused automatically by the system firmware only.8.7.3 SCI BASS (RW)Name Bits DescriptionST AMPLITUDE 15:12 Treble Control in 1.5 dB steps (-8..7, 0 = off)ST FREQLIMIT 11:8 Lower limit frequency in 1000 Hz steps (1..15)SB AMPLITUDE 7:4 Bass Enhancement in 1 dB steps (0..15, 0 = off)SB FREQLIMIT 3:0 Lower limit frequency in 10 Hz steps (2..15)The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most outof the users earphones without causing clipping.VSBE is activated when SB AMPLITUDE is non-zero. SB AMPLITUDE should be set to the user’spreferences, and SB FREQLIMIT to roughly 1.5 times the lowest frequency the user’s audio system canreproduce. For example setting SCI BASS to 0x00f6 will have 15 dB enhancement below 60 Hz.Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music material,or when the playback volume is not set to maximum. It also does not create bass: the source materialmust have some bass to begin with.Treble Control VSTC is activated when ST AMPLITUDE is non-zero. For example setting SCI BASSto 0x7a00 will have 10.5 dB treble enhancement at and above 10 kHz.Bass Enhancer uses about 2.1 MIPS and Treble Control 1.2 MIPS at 44100 Hz sample rate. Both can beon simultaneously.Version 1.00, 2008-02-01 38

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.7.4 SCI CLOCKF (RW)The operation of SCI CLOCKF is different in VS1003 and VS1033 than in VS10x1 and VS1002. Forgeneral applications with 12.288 MHz clock use 0x9000 for 3.0 × ..4.0×, or 0xa800 for 3.5 × ..4.0×.SCI CLOCKF bitsName Bits DescriptionSC MULT 15:13 Clock multiplierSC ADD 12:11 Allowed multiplier additionSC FREQ 10: 0 Clock frequencySC MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.The values are as follows:SC MULT MASK CLKI0 0x0000 XTALI1 0x2000 XTALI×1.52 0x4000 XTALI×2.03 0x6000 XTALI×2.54 0x8000 XTALI×3.05 0xa000 XTALI×3.56 0xc000 XTALI×4.07 0xe000 XTALI×4.5SC ADD tells, how much the decoder firmware is allowed to add to the multiplier specified by SC MULTif more cycles are temporarily needed to decode a WMA stream. The values are:SC ADD MASK Multiplier addition0 0x0000 No modification is allowed1 0x0800 0.5×2 0x1000 1.0×3 0x1800 1.5×SC FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz. XTALIXT ALI−8000000is set in 4 kHz steps. The formula for calculating the correct value for this register is4000(XTALI is in Hz).Note: The default value 0 is assumed to mean XTALI=12.288 MHz.Note: because maximum sample rate isMHz.XT ALI256, all sample rates are not available if XTALI < 12.288Note: Automatic clock change can only happen when decoding WMA files. Automatic clock change isdone one 0.5× at a time. This does not cause a drop to 1.0× clock and you can use the same SCI andSDI clock throughout the WMA file.Example: If SCI CLOCKF is 0x9BE8, SC MULT = 4, SC ADD = 3 and SC FREQ = 0x3E8 = 1000.This means that XTALI = 1000×4000+8000000 = 12 MHz. The clock multiplier is set to 3.0×XTALI =36 MHz, and the maximum allowed multiplier that the firmware may automatically choose to use is(3.0 + 1.5)×XTALI = 54 MHz.Version 1.00, 2008-02-01 39

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.7.5 SCI DECODE TIME (RW)When decoding correct data, current decoded time is shown in this register in full seconds.The user may change the value of this register. In that case the new value should be written twice.SCI DECODE TIME is reset at every software reset and also when WAV (PCM or IMA ADPCM), AAC,WMA, or MIDI decoding starts or ends.8.7.6 SCI AUDATA (RW)When decoding correct data, the current sample rate and number of channels can be found in bits 15:1and 0 of SCI AUDATA, respectively. Bits 15:1 contain the sample rate divided by two, and bit 0 is 0 formono data and 1 for stereo. Writing to SCI AUDATA will change the sample rate directly.Example: 44100 Hz stereo data reads as 0xAC45 (44101).Example: 11025 Hz mono data reads as 0x2B10 (11024).Example: Writing 0xAC80 sets sample rate to 44160 Hz, stereo mode does not change.To reduce the digital power consumption when in idle, you can write a low samplerate to SCI AUDATA,and also write 0 to SCI CLOCKF to turn off the PLL.8.7.7 SCI WRAM (RW)SCI WRAM is used to upload application programs and data to instruction and data RAMs. The startaddress must be initialized by writing to SCI WRAMADDR prior to the first write/read of SCI WRAM.As 16 bits of data can be transferred with one SCI WRAM write/read, and the instruction word is 32 bitslong, two consecutive writes/reads are needed for each instruction word. The byte order is big-endian (i.e.most significant words first). After each full-word write/read, the internal pointer is autoincremented.8.7.8 SCI WRAMADDR (W)SCI WRAMADDR is used to set the program address for following SCI WRAM writes/reads. Addressoffset of 0 is used for X, 0x4000 for Y, and 0x8000 for instruction memory. Peripheral registers can alsobe accessed.SM WRAMADDR Dest. addr. Bits/ DescriptionStart. . . End Start. . . End Word0x1800. . . 0x187F 0x1800. . . 0x187F 16 X data RAM0x5800. . . 0x587F 0x1800. . . 0x187F 16 Y data RAM0x8030. . . 0x84FF 0x0030. . . 0x04FF 32 Instruction RAM0xC000. . . 0xFFFF 0xC000. . . 0xFFFF 16 I/OOnly user areas in X, Y, and instruction memory are listed above. Other areas can be accessed, but shouldnot be written to unless otherwise specified.Version 1.00, 2008-02-01 40

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTION8.7.9 SCI HDAT0 and SCI HDAT1 (R)For WAV files, SCI HDAT1 contains 0x7665 (“ve”). SCI HDAT0 contains the data rate in double wordincrements for all supported RIFF WAVE formats: mono and stereo 8-bit or 16-bit PCM, mono andstereo IMA ADPCM. To get the byte rate of the file, multiply the value by 4. To get the bit rate of thefile, multiply the value by 32. Note: usage of SCI HDAT0 with WAV files has changed from VS1003.For AAC ADTS streams, SCI HDAT1 contains 0x4154 (“AT”). For AAC ADIF files, SCI HDAT1 contains0x4144 (“AD”). For AAC .mp4 / .m4a files, SCI HDAT1 contains 0x4D34 (“M4”). SCI HDAT0contains the average data rate in bytes per second. To get the bit rate of the file, multiply the value by 8.For WMA files, SCI HDAT1 contains 0x574D (“WM”) and SCI HDAT0 contains the data rate measuredin bytes per second. To get the bit rate of the file, multiply the value by 8.for MIDI files, SCI HDAT1 contains 0x4D54 (“MT”) and SCI HDAT0 contains the average data rate inbytes per second. To get the bit rate of the file, multiply the value by 8. Note: usage of SCI HDAT0 withMIDI has changed from VS1003.For MP3 files, SCI HDAT1 is between 0xFFE0 and 0xFFFF. SCI HDAT1 / 0 contain the following:Bit Function Value ExplanationHDAT1[15:5] syncword 2047 stream validHDAT1[4:3] ID 3 ISO 11172-3 MPG 1.02 ISO 13818-3 MPG 2.0 (1/2-rate)1 MPG 2.5 (1/4-rate)0 MPG 2.5 (1/4-rate)HDAT1[2:1] layer 3 I2 II1 III0 reservedHDAT1[0] protect bit 1 No CRC0 CRC protectedHDAT0[15:12] bitrate see bitrate tableHDAT0[11:10] sample rate 3 reserved2 32/16/ 8 kHz1 48/24/12 kHz0 44/22/11 kHzHDAT0[9] pad bit 1 additional slot0 normal frameHDAT0[8] private bit not definedHDAT0[7:6] mode 3 mono2 dual channel1 joint stereo0 stereoHDAT0[5:4] extension see ISO 11172-3HDAT0[3] copyright 1 copyrighted0 freeHDAT0[2] original 1 original0 copyHDAT0[1:0] emphasis 3 CCITT J.172 reserved1 50/15 microsec0 noneVersion 1.00, 2008-02-01 41

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTIONWhen read, SCI HDAT0 and SCI HDAT1 contain header information that is extracted from MP3 streamcurrently being decoded. After reset both registers are cleared, indicating no data has been found yet.The “sample rate” field in SCI HDAT0 is interpreted according to the following table:“sample rate” ID=3 ID=2 ID=0,13 - - -2 32000 16000 80001 48000 24000 120000 44100 22050 11025The “bitrate” field in HDAT0 is read according to the following table. Notice that for variable bitratestream the value changes constantly.Layer I Layer II Layer III“bitrate” ID=3 ID=0,1,2 ID=3 ID=0,1,2 ID=3 ID=0,1,2kbit/s kbit/s kbit/s15 forbidden forbidden forbidden forbidden forbidden forbidden14 448 256 384 160 320 16013 416 224 320 144 256 14412 384 192 256 128 224 12811 352 176 224 112 192 11210 320 160 192 96 160 969 288 144 160 80 128 808 256 128 128 64 112 647 224 112 112 56 96 566 192 96 96 48 80 485 160 80 80 40 64 404 128 64 64 32 56 323 96 56 56 24 48 242 64 48 48 16 40 161 32 32 32 8 32 80 - - - - - -8.7.10 SCI AIADDR (RW)SCI AIADDR indicates the start address of the application code written earlier with SCI WRAMADDRand SCI WRAM registers. If no application code is used, this register should not be initialized, or itshould be initialized to zero. For more details, see Application Notes for VS10XX.8.7.11 SCI VOL (RW)SCI VOL is a volume control for the player hardware. The most significant byte of the volume registercontrols the left channel volume, the low part controls the right channel volume. The channel volumeVersion 1.00, 2008-02-01 42

VLSISolution yVS1033cVS1033C8. FUNCTIONAL DESCRIPTIONsets the attenuation from the maximum volume level in 0.5 dB steps. Thus, maximum volume is 0x0000and total silence is 0xFEFE.Note, that after hardware reset the volume is set to full volume. Resetting the software does not reset thevolume setting.Setting SCI VOL to 0xFFFF will activate analog powerdown mode.Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (2.0/0.5) = 4,3.5/0.5 = 7 → SCI VOL = 0x0407.Example: SCI VOL = 0x2424 → both left and right volumes are 0x24 * -0.5 = -18.0 dB8.7.12 SCI AICTRL[x] (RW)SCI AICTRL[x] registers ( x=[0 .. 3] ) can be used to communicate with the user’s application program.They are also used in the ADPCM recording mode.Version 1.00, 2008-02-01 43

VLSISolution yVS1033cVS1033C9. OPERATION9 Operation9.1 ClockingVS1033 operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clockcan be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface(pins XTALI and XTALO).VS1033 can also use 24..26 MHz clocks when SM CLK RANGE is set to 1. From the chip’s point ofview the input clock is then 12..13 MHz.9.2 Hardware ResetWhen the XRESET -signal is driven low, VS1033 is reset and all the control registers and internal statesare set to the initial values. XRESET-signal is asynchronous to any external clock. The reset modedoubles as a full-powerdown mode, where both digital and analog parts of VS1033 are in minimumpower consumption stage, and where clocks are stopped. Also XTALO is grounded.When XRESET is asseted, all output pins go to their default states. All input pins will go to highimpedancestate (to input state), except SO, which is still controlled by the XCS.After a hardware reset (or at power-up) DREQ will stay down for around 20000 clock cycles, whichmeans an approximate 1.6 ms delay if VS1033 is run at 12.288 MHz. After this the user should setsuch basic software registers as SCI MODE, SCI BASS, SCI CLOCKF, and SCI VOL before startingdecoding. See section 8.7 for details.If the input clock is 24..26 MHz, SM CLK RANGE should be set as soon as possible after a chip resetwithout waiting for DREQ.Internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF registerare 1.0 × . . . 4.5× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If typical valuesare wanted, the Internal Clock Multiplier needs to be set to 3.0× after reset. Wait until DREQ rises, thenwrite value 0x9800 to SCI CLOCKF (register 3). See section 8.7.4 for details.Version 1.00, 2008-02-01 44

VLSISolution yVS1033cVS1033C9. OPERATION9.3 Software ResetIn some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register(Chapter 8.7.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for at least 20000clock cycles, which means an approximate 1.6 ms delay if VS1033 is run at 12.288 MHz. After DREQis up, you may continue playback as usual.If you want to make sure VS1033 doesn’t cut the ending of low-bitrate data streams and you want to doa software reset, it is recommended to feed 2052 zeros (honoring DREQ) to the SDI bus after the file andbefore the reset. This is especially important for MIDI files.If you want to interrupt the playing of a WAV, AAC, WMA, or MIDI file in the middle, set SM OUTOFWAVin the mode register, and send data honouring DREQ (with a three-second timeout) until SM OUTOFWAVis cleared (SCI HDAT1 will also be cleared) before continuing with a software reset. For WMA andMIDI it is safest to continue sending the stream, send zeroes for WAV.Version 1.00, 2008-02-01 45

VLSISolution yVS1033cVS1033C9. OPERATION9.4 ADPCM RecordingThis chapter explains how to create RIFF/WAV file with IMA ADPCM format. This is a widely supportedADPCM format and many PC audio playback programs can play it. IMA ADPCM recordinggives roughly a compression ratio of 4:1 compared to linear, 16-bit audio. This makes it possible torecord 8 kHz audio at 32.44 kbit/s.9.4.1 Activating ADPCM modeIMA ADPCM recording mode is activated by setting bits SM RESET and SM ADPCM in SCI MODE.Optionally a high-pass-filter can be enabled for 8 kHz sample rate by also setting SM ADPCM HP at thesame time. Line input is used instead of mic if SM LINE IN is set. Before activating ADPCM recording,user must write a clock divider value to SCI AICTRL0 and gain to SCI AICTRL1.The differences of using SM ADPCM HP are presented in figure 15 (page 37). As a general rule, audiowill be fuller and closer to original if SM ADPCM HP is not used. However, speech may be moreintelligible with the high-pass filter active. Use the filter only with 8 kHz sample rate.Before activating ADPCM recording, user should write a clock divider value to SCI AICTRL0. Thesampling frequency is calculated from the following formula: f s =F c256×d , where F c is the internalclock (CLKI) and d is the divider value in SCI AICTRL0. If the sample rate is < 16000 Hz, additionalsoftware decimation by two is performed and the lowest valid value for d is 4, otherwise the lowest validvalue for d is 2. If SCI AICTRL0 contains 0, the default divider value 12 is used.Examples:F c = 2.0 × 12.288 MHz, d = 12. Now f s = 2.0×12288000256×12= 8000 Hz.F c = 2.5 × 14.745 MHz, d = 18. Now f s = 2.5×14745000256×18= 8000 Hz.F c = 2.5 × 13 MHz, d = 16. Now f s = 2.5×13000000256×16= 7935 Hz.Also, before activating ADPCM mode, the user has to set linear recording gain control to registerSCI AICTRL1. 1024 is equal to digital gain 1, 512 is equal to digital gain 0.5 and so on. If the userwants to use automatic gain control (AGC), SCI AICTRL1 should be set to 0. Typical speech applicationsusually are better off using AGC, as this takes care of relatively uniform speech loudness inrecordings.Since VS1033c SCI AICTRL2 controls the maximum AGC gain. If SCI AICTRL2 is zero, the maximumgain is 65535 (64×), i.e. whole range is used. This is compatible with previous operation.9.4.2 Reading IMA ADPCM DataAfter IMA ADPCM recording has been activated, registers SCI HDAT0 and SCI HDAT1 have newfunctions.The IMA ADPCM sample buffer is 1024 16-bit words. The fill status of the buffer can be read fromSCI HDAT1. If SCI HDAT1 is greater than 0, you can read as many 16-bit words from SCI HDAT0. Ifthe data is not read fast enough, the buffer overflows and returns to empty state.Note: if SCI HDAT1 ≥ 896, it may be better to wait for the buffer to overflow and clear before readingsamples. That way you may avoid buffer aliasing.Version 1.00, 2008-02-01 46

VLSISolution yVS1033cVS1033C9. OPERATIONEach IMA ADPCM block is 128 words, i.e. 256 bytes. If you wish to interrupt reading data and possiblycontinue later, please stop at a 128-word boundary. This way whole blocks are skipped and the encodedstream stays valid.9.4.3 Adding a RIFF HeaderTo make your IMA ADPCM file a RIFF / WAV file, you have to add a header before the actual data.Note that 2- and 4-byte values are little-endian (lowest byte first) in this format:File Offset Field Name Size Bytes Description0 ChunkID 4 "RIFF"4 ChunkSize 4 F0 F1 F2 F3 File size - 88 Format 4 "WAVE"12 SubChunk1ID 4 "fmt "16 SubChunk1Size 4 0x14 0x0 0x0 0x0 2020 AudioFormat 2 0x11 0x0 0x11 for IMA ADPCM22 NumOfChannels 2 0x1 0x0 Mono sound24 SampleRate 4 R0 R1 R2 R3 0x1f40 for 8 kHz28 ByteRate 4 B0 B1 B2 B3 0xfd7 for 8 kHz32 BlockAlign 2 0x0 0x1 0x10034 BitsPerSample 2 0x4 0x0 4-bit ADPCM36 ByteExtraData 2 0x2 0x0 238 ExtraData 2 0xf9 0x1 Samples per block (505)40 SubChunk2ID 4 "fact"44 SubChunk2Size 4 0x4 0x0 0x0 0x0 448 NumOfSamples 4 S0 S1 S2 S352 SubChunk3ID 4 "data"56 SubChunk3Size 4 D0 D1 D2 D3 Data size (File Size-60)60 Block1 256 First ADPCM block316 . . . More ADPCM data blocksIf we have n audio blocks, the values in the table are as follows:F = n × 256 + 52R = F s (see Chapter 9.4.1 to see how to calculate F s )B = Fs×256505S = n × 505. D = n × 256If you know beforehand how much you are going to record, you may fill in the complete header beforeany actual data. However, if you don’t know how much you are going to record, you have to fill in theheader size datas F , S and D after finishing recording.The 128 words (256 bytes) of an ADPCM block are read from SCI HDAT0 and written into file asfollows. The high 8 bits of SCI HDAT0 should be written as the first byte to a file, then the low 8 bits.Note that this is contrary to the default operation of some 16-bit microcontrollers, and you may have totake extra care to do this right.A way to see if you have written the file in the right way is to check bytes 2 and 3 (the first byte countsas byte 0) of each 256-byte block. Byte 3 should always be zero.Version 1.00, 2008-02-01 47

VLSISolution yVS1033cVS1033C9. OPERATION9.4.4 Playing ADPCM DataIn order to play back your IMA ADPCM recordings, you have to have a file with a header as describedin Chapter 9.4.3. If this is the case, all you need to do is to provide the ADPCM file through SDI as youwould with any audio file.9.4.5 Sample Rate ConsiderationsVS10xx chips that support IMA ADPCM playback are capable of playing back ADPCM files withany sample rate. However, some other programs may expect IMA ADPCM files to have some exactsample rates, like 8000 or 11025 Hz. Also, some programs or systems do not support sample rates below8000 Hz.However, if you don’t have an appropriate clock, you may not be able to get an exact 8 kHz sample rate.If you have a 12 MHz clock, the closest sample rate you can get with 2.0 × 12 MHz and d = 12 isf s = 7812.5Hz. Because the frequency error is only 2.4%, it may be best to set f s = 8000Hz to theheader if the same file is also to be played back with an PC. This causes the sample to be played back alittle faster (one minute is played in 59 seconds).Note, however, that unless absolutely necessary, sample rates should not be tweaked in the way describedhere. If you want better quality with the expense of increased data rate, you can use higher sample rates,for example 16 kHz.9.4.6 AD Startup TimeDepending on the external components it may take 2-5 seconds for the MIC and LINE bias to wakeup properly. You can reduce the settling time by changing the components. You can also speed up theprocess by enabling the AD with a low sample rate some time before the recording starts by writing0xc01e to SCI WRAMADDR, then 0x0800 to SCI WRAM. Notice that hardware and software resetdisables the AD.9.4.7 Example CodeThe following code initializes IMA ADPCM encoding on VS1033 and shows how to read the data.const unsigned char header[] = {0x52, 0x49, 0x46, 0x46, 0x1c, 0x10, 0x00, 0x00,0x57, 0x41, 0x56, 0x45, 0x66, 0x6d, 0x74, 0x20, /*|RIFF....WAVEfmt |*/0x14, 0x00, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00,0x40, 0x1f, 0x00, 0x00, 0x75, 0x12, 0x00, 0x00, /*|........@.......|*/0x00, 0x01, 0x04, 0x00, 0x02, 0x00, 0xf9, 0x01,0x66, 0x61, 0x63, 0x74, 0x04, 0x00, 0x00, 0x00, /*|........fact....|*/0x5c, 0x1f, 0x00, 0x00, 0x64, 0x61, 0x74, 0x61,0xe8, 0x0f, 0x00, 0x00};Version 1.00, 2008-02-01 48

VLSISolution yVS1033cVS1033C9. OPERATIONunsigned char db[512]; /* data buffer for saving to disk */void RecordAdpcm1003(void) { /* VS1003b/VS1033c */u_int16 w = 0, idx = 0;}... /* Check and locate free space on disk */SetMp3Vol(0x1414); /* Recording monitor volume */WriteMp3SpiReg(SCI_BASS, 0); /* Bass/treble disabled */WriteMp3SpiReg(SCI_CLOCKF, 0x4430); /* 2.0x 12.288MHz */Wait(100);WriteMp3SpiReg(SCI_AICTRL0, 12); /* Div -> 12=8kHz 8=12kHz 6=16kHz */Wait(100);WriteMp3SpiReg(SCI_AICTRL1, 0); /* Auto gain */Wait(100);if (line_in) {WriteMp3SpiReg(SCI_MODE, 0x5804); /* Normal SW reset + other bits */} else {WriteMp3SpiReg(SCI_MODE, 0x1804); /* Normal SW reset + other bits */}for (idx=0; idx < sizeof(header); idx++) { /* Save header first */db[idx] = header[idx];}/* Fix rate if needed *//*db[24] = rate;*//*db[25] = rate>>8;*//* Record loop */while (recording_on) {do {w = ReadMp3SpiReg(SCI_HDAT1);} while (w < 256 || w >= 896); /* wait until 512 bytes available */while (idx < 512) {w = ReadMp3SpiReg(SCI_HDAT0);db[idx++] = w>>8;db[idx++] = w&0xFF;}idx = 0;write_block(datasector++, db); /* Write output block to disk */}... /* Fix WAV header information */... /* Then update FAT information */ResetMP3(); /* Normal reset, restore default settings */SetMp3Vol(vol);Version 1.00, 2008-02-01 49

VLSISolution yVS1033cVS1033C9. OPERATION9.5 SPI BootIf GPIO0 is set with a pull-up resistor to 1 at boot time, VS1033 tries to boot from external SPI memory.SPI boot redefines the following pins:Normal ModeGPIO0GPIO1DREQGPIO2SPI Boot ModexCSCLKMOSIMISOThe memory has to be an SPI Bus Serial EEPROM with 16-bit addresses (i.e. at least 1 KiB). The serialspeed used by VS1033 is 245 kHz with the nominal 12.288 MHz clock. The first three bytes in thememory have to be 0x50, 0x26, 0x48.9.6 Play/DecodeThis is the normal operation mode of VS1033. SDI data is decoded. Decoded samples are converted toanalog domain by the internal DAC. If no decodable data is found, SCI HDAT0 and SCI HDAT1 are setto 0 and analog outputs are muted.When there is no input for decoding, VS1033 goes into idle mode (lower power consumption than duringdecoding) and actively monitors the serial data input for valid data.All different formats can be played back-to-back without software reset in-between. Send at least 2052zeros after each stream. However, using software reset between streams may still be a good idea, as itguards against broken files. In this case you shouldt wait for the completion of the decoding (SCI HDAT1and SCI HDAT0 become zero) before issuing software reset.Version 1.00, 2008-02-01 50

VLSISolution yVS1033cVS1033C9. OPERATION9.7 Feeding PCM dataVS1033 can be used as a PCM decoder by sending a WAV file header. If the length sent for theWAV/DATA is 0xFFFFFFFF, VS1033 will stay in PCM mode indefinitely (or until SM OUTOFWAVhas been set). 8-bit linear and 16-bit linear audio is supported in mono or stereo. A WAV header lookslike this:File Offset Field Name Size Bytes Description0 ChunkID 4 "RIFF"4 ChunkSize 4 0xff 0xff 0xff 0xff8 Format 4 "WAVE"12 SubChunk1ID 4 "fmt "16 SubChunk1Size 4 0x10 0x0 0x0 0x0 1620 AudioFormat 2 0x1 0x0 Linear PCM22 NumOfChannels 2 C0 C1 1 for mono, 2 for stereo24 SampleRate 4 S0 S1 S2 S3 0x1f40 for 8 kHz28 ByteRate 4 R0 R1 R2 R3 0x3e80 for 8 kHz 16-bit mono32 BlockAlign 2 A0 A1 2 for mono, 4 for stereo 16-bit34 BitsPerSample 2 B0 0xB1 16 for 16-bit data52 SubChunk2ID 4 "data"56 SubChunk2Size 4 0xff 0xff 0xff 0xff Data sizeThe rules to calculate the four variables are as follows:• S = sample rate in Hz, e.g. 44100 for 44.1 kHz.• For 8-bit data B = 8, and for 16-bit data B = 16.• For mono data C = 1, for stereo data C = 2.• A = C×B8.• R = S × A.Example: A 44100 Hz 16-bit stereo PCM header would read as follows:0000 52 49 46 46 ff ff ff ff 57 41 56 45 66 6d 74 20 |RIFF....WAVEfmt |0100 10 00 00 00 01 00 02 00 44 ac 00 00 10 b1 02 00 |........D.......|0200 04 00 10 00 64 61 74 61 ff ff ff ff |....data....|Version 1.00, 2008-02-01 51

VLSISolution yVS1033cVS1033C9. OPERATION9.8 Extra ParametersThe following structure is in X memory at address 0x1940 and can be used to change some extra parametersor get various information. The chip ID is also easily available.#define PARAMETRIC_VERSION 0x0001struct parametric {u_int32 chipID; /*1940/41 Initialized at reset for your convenience */u_int16 version; /*1942 - structure version */u_int16 midiConfig; /*1943 */u_int16 config1; /*1944 */u_int16 config2; /*1945 configs are not cleared between files */};u_int32 jumpPoints[16]; /*1946..65 file byte offsets */u_int16 latestJump; /*1966 index to lastly updated jumpPoint */s_int16 seek1; /*1967 file data inserted/removed bytes -32768..32767*/s_int16 seek2; /*1968 file data inserted/removed kB -32768..32767*/s_int16 resync; /*1969 > 0 for automatic m4a, ADIF, WMA resyncs */union {struct {u_int32 curPacketSize;u_int32 packetSize;} wma;struct {u_int16 sceFoundMask; /* SCE’s found since last clear */u_int16 cpeFoundMask; /* CPE’s found since last clear */u_int16 lfeFoundMask; /* LFE’s found since last clear */u_int16 playSelect; /* 0 = first any, initialized at aac init */s_int16 dynCompress; /* -8192=1.0, initialized at aac init */s_int16 dynBoost; /* 8192=1.0, initialized at aac init */} aac;struct {u_int32 bytesLeft;} midi;} i;Notice that reading two-word variables through the SCI WRAMADDR and SCI WRAM interface isnot protected in any way. The variable can be updated between the read of the low and high parts. Theproblem arises when both the low and high parts change values. To determine if the value is correct, youshould read the value twice and compare the results.The following example shows what happens when bytesLeft is decreased from 0x10000 to 0xffff andthe update happens between low and high part reads or after high part read.Address0x196a0x196b0x196a0x196bRead InvalidValue0x0000 change after this0x00000xffff0x0000Address0x196a0x196b0x196a0x196bRead ValidValue0x00000x0001 change after this0xffff0x0000No UpdateAddress Value0x196a0x196b0x196a0x196b0x00000x00010x00000x0001You can see that in the invalid read the low part wraps from 0x0000 to 0xffff while the high part stays thesame. In this case the second read gives a valid answer, otherwise always use the value of the first read.The second read is needed when it is possible that the low part wraps around, changing the high part, i.e.when the low part is small. bytesLeft is only decreased by one at a time, so a reread is needed onlyif the low part is 0.Version 1.00, 2008-02-01 52

VLSISolution yVS1033cVS1033C9. OPERATION9.8.1 Common ParametersParameter Address UsagechipID 0x1940/41 Fuse-programmed unique ID (copy)version 0x1942 Structure version – 0x0001jumpPoints[16] 0x1946-65 Packet offsets for WMA and AAClatestJump 0x1966 Index to latest jumpPointseek1 0x1967 Seek amount in bytesseek2 0x1968 Seek amount in kilobytesresync 0x1969 Automatic resync selectorThe fuse-programmed ID is read at startup and copied into the chipID field. The version field canbe used to determine the layout of the rest of the structure. The version number is changed when thestructure is changed.jumpPoints contain 32-bit file offsets. Each valid (non-zero) entry indicates a start of a packet forWMA or start of a raw data block for AAC (ADIF, .mp4 / .m4a). latestJump contains the index ofthe entry that was updated last. If you only read entry pointed to by latestJump you do not need toread the entry twice to ensure validity. Jump point information can be used to implement perfect fastforward and rewind for WMA and AAC (ADIF, .mp4 / .m4a).seek1 and seek2 fields are used when music data is skipped or inserted. Negative values mean thatdata has been added (for example in rewind operation), positive values mean that data has been skipped.You can use either seek1, which gives the seek amount in bytes, or seek2 which gives the seek amountin kilobytes, or you can use both. The field value is zeroed when the firmware has detected the seek.resync field is used to force a resynchronization to the stream for WMA and AAC (ADIF, .mp4 / .m4a).This field can be used to implement almost perfect fast forward and rewind for WMA and AAC (ADIF,.mp4 / .m4a). The user should set this field before performing data seeks if they are not in packet or datablock boundaries. The field value tells how many tries are allowed before giving up. The value 32767gives infinite tries, in which case the user must use SM OUTOFWAV or software reset to end decoding.In every case remember to use seek1 and/or seek2 fields to indicate the skipped/inserted data.Note: WMA, ADIF, and .mp4 / .m4a files begin with a metadata section, which must be fully processedbefore any fast forward or rewind operation. When the first jumpPoint appears it is safe to perform seeks.You can also detect the start of decoding from SCI DECODE TIME.9.8.2 WMAParameter Address UsagecurPacketSize 0x196a/6b The size of the packet being processedpacketSize 0x196c/6d The packet size in ASF headerThe ASF header packet size is available in packetSize. With this information and a packet start offsetfrom jumpPoints you can parse the packet headers and skip packets in ASF files.Version 1.00, 2008-02-01 53

VLSISolution yVS1033cVS1033C9. OPERATION9.8.3 AACParameter Address UsagesceFoundMask 0x196a Single channel elements foundcpeFoundMask 0x196b Channel pair elements foundlfeFoundMask 0x196c Low frequency elements foundplaySelect 0x196d Play element selectiondynCompress 0x196e Compress coefficient for DRC, -8192=1.0dynBoost 0x196f Boost coefficient for DRC, 8192=1.0playSelect determines which element to decode if a stream has multiple elements. The value isset to 0 each time AAC decoding starts, which causes the first element that appears in the stream to beselected for decoding. Other values are: 0x01 - select first single channel element (SCE), 0x02 - selectfirst channel pair element (CPE), 0x03 - select first low frequency element (LFE), S ∗ 16 + 5 - selectSCE number S, P ∗ 16 + 6 - select CPE number P, L ∗ 16 + 7 - select LFE number L. When automaticselection has been performed, playSelect reflects the selected element. The value can be changedwhile decoding is in progress.sceFoundMask, cpeFoundMask, and lfeFoundMask indicate which elements have been foundin an AAC stream since the variables have last been cleared. The values can be used to present an elementselection menu with only the available elements.dynCompress and dynBoost change the behavior of the dynamic range control (DRC) that is presentin some AAC streams. These are also initialized when AAC decoding starts.SCI HDAT0 contains the average bitrate in bytes per second, is updated once per second and it can beused to calculate an estimate of the remaining playtime.9.8.4 MidiParameter Address UsagemidiConfig 0x1943 Miscellaneous configurationbits [3:0] Reverb: 0 = auto (ON if clock >= 3.0×)1 = off, 2 - 15 = room sizebits [6:4] Play speed: 0 = 1×, 1 = 2×, 2 = 4×, 3 = 8× .. 7 = 128×bits [15:7] reservedbytesLeft 0x196a/6b The number of bytes left in this trackmidiConfig controls the reverb effect and play speed.SCI HDAT0 contains the average bitrate in bytes per second, is updated once per second and it can beused together with bytesLeft to calculate an estimate of the remaining playtime.Version 1.00, 2008-02-01 54

VLSISolution yVS1033cVS1033C9. OPERATION9.9 Fast Forward / Rewind9.9.1 AAC - ADTSMPEG2.0 Advanced Audio Coded (AAC) defines a stream format suitable for random-access (ADTS).When you want to skip forward or backwards in the file, first send 2052 zeros, then continue sending thefile from the new location.By sending zeros you make certain a partial frame does not cause loud artefacts in the sound. The normalfile type checking then finds a new ADTS header and continues decoding.9.9.2 AAC - ADIF, MP4MPEG4.0 Advanced Audio Codec (AAC) specifies a multimedia file format (.mp4 / .m4a) but does notspecify a stream format and MPEG2.0 AAC specifies a file format (ADIF) in addition to the streamableADTS format. ADIF and .mp4 / .m4a are not suitable for random-access and it is recommended thatthey are converted to ADTS format for playback.However, it is also possible to implement fast forward and rewind for ADIF and .mp4 / .m4a files. Theeasiest way is to use the resync field (see section 9.8.1):• Write 8192 to resync– Write 0x1969 to SCI WRAMADDR, Write 0x2000 to SCI WRAM• Send 2048 zeroes• Make a seek X in the file (X > 0 for forward seek)• Indicate the low part of the seek amount by writing to seek1– Write 0x1967 to SCI WRAMADDR, Write (X − 2048)&1023 to SCI WRAM• Indicate the high part of the seek amount by writing to seek2– Write 0x1968 to SCI WRAMADDR, Write (X − 2048)/1024 to SCI WRAM• Continue sending the file from the new locationPerfect fast forward and rewind can be implemented by using the jumpPoints table and making seeksonly on packet or data block boundaries.Version 1.00, 2008-02-01 55

VLSISolution yVS1033cVS1033C9. OPERATION9.9.3 WMAWindows Media Audio (WMA) is enclosed as data packets into Advanced Systems Format (ASF) files.This file format is not suitable for random-access.However, it is also possible to implement fast forward and rewind for WMA files. The easiest way is touse the resync field (see Section 9.9.2), perfect fast forward and rewind can be implemented by usingthe jumpPoints table and making seeks only on packet or data block boundaries.9.9.4 MidiMidi is not at all suitable for random-access. You can implement fast forward using the playSpeedbits of the midiConfig field to select 1-128× play speed. SCI DECODE TIME also speeds up.If necessary, rewind can be implemented by restarting the decoding of a MIDI file and fast forwardingto the appropriate place. SCI DECODE TIME can be used to decide when the right place has beenreached. This is best suited for soundless rewind.Version 1.00, 2008-02-01 56

VLSISolution yVS1033cVS1033C9. OPERATION9.10 SDI TestsThere are several test modes in VS1033, which allow the user to perform memory tests, SCI bus tests,and several different sine wave tests.All tests are started in a similar way: VS1033 is hardware reset, SM TESTS is set, and then a testcommand is sent to the SDI bus. Each test is started by sending a 4-byte special command sequence,followed by 4 zeros. The sequences are described below.9.10.1 Sine TestSine test is initialized with the 8-byte sequence 0x53 0xEF 0x6E n 0 0 0 0, where n defines the sine testto use. n is defined as follows:n bitsName Bits DescriptionF s Idx 7:5 Sample rate indexS 4:0 Sine skip speedF s Idx F s0 44100 Hz1 48000 Hz2 32000 Hz3 22050 Hz4 24000 Hz5 16000 Hz6 11025 Hz7 12000 HzThe frequency of the sine to be output can now be calculated from F = F s × S128 .Example: Sine test is activated with value 126, which is 0b01111110. Breaking n to its components,F s Idx = 0b011 = 3 and thus F s = 22050Hz. S = 0b11110 = 30, and thus the final sine frequencyF = 22050Hz × 30128 ≈ 5168Hz.To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0.Note: Sine test signals go through the digital volume control, so it is possible to test channels separately.9.10.2 Pin TestPin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant for chipproduction testing only.Version 1.00, 2008-02-01 57

VLSISolution yVS1033cVS1033C9. OPERATION9.10.3 Memory TestMemory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After thissequence, wait for 500000 clock cycles. The result can be read from the SCI register SCI HDAT0, and’one’ bits are interpreted as follows:Bit(s) Mask Meaning15 0x8000 Test finished14:7 Unused6 0x0040 Mux test succeeded5 0x0020 Good I RAM4 0x0010 Good Y RAM3 0x0008 Good X RAM2 0x0004 Good I ROM1 0x0002 Good Y ROM0 0x0001 Good X ROM0x807fAll okMemory tests overwrite the current contents of the RAM memories.9.10.4 SCI TestSci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n − 48 is the registernumber to test. The content of the given register is read and copied to SCI HDAT0. If the register to betested is HDAT0, the result is copied to SCI HDAT1.Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI HDAT0.Version 1.00, 2008-02-01 58

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10 VS1033 Registers10.1 Who Needs to Read This ChapterUser software is required when a user wishes to add some own functionality like DSP effects to VS1033.However, most users of VS1033 don’t need to worry about writing their own code, or about this chapter,including those who only download software plug-ins from VLSI Solution’s Web site.10.2 The Processor CoreVS DSP is a 16/32-bit DSP processor core that also had extensive all-purpose processor features. VLSISolution’s free VSKIT Software Package contains all the tools and documentation needed to write, simulateand debug Assembly Language or Extended ANSI C programs for the VS DSP processor core.VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities.10.3 VS1033 Memory MapVS1033’s Memory Map is shown in Figure 16.10.4 SCI RegistersSCI registers described in Chapter 8.7 can be found here between 0xC000..0xC00F. In addition to theseregisters, there is one in address 0xC010, called SCI CHANGE.SCI registers, prefix SCIReg Type Reset Abbrev[bits] Description0xC010 r 0 CHANGE[5:0] Last SCI access addressSCI CHANGE bitsName Bits DescriptionSCI CH WRITE 4 1 if last access was a write cycleSCI CH ADDR 3:0 SCI address of last access10.5 Serial Data RegistersSDI registers, prefix SERReg Type Reset Abbrev[bits] Description0xC011 r 0 DATA Last received 2 bytes, big-endian0xC012 w 0 DREQ[0] DREQ pin controlVersion 1.00, 2008-02-01 59

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERSInstruction (32−bit)X (16−bit)Y (16−bit)000000000030 System Vectors0030UserInstruction0500 RAM0500X DATAY DATARAMRAM180018801940UserStackUserStack18001880194020002000280028004000 4000InstructionROMX DATAROMY DATAROM8000 8000C000C100I/OC000C100FFFFFFFFFigure 16: User’s Memory Map.10.6 DAC RegistersDAC registers, prefix DACReg Type Reset Abbrev[bits] Description0xC013 rw 0 FCTLL DAC frequency control, 16 LSbs0xC014 rw 0 FCTLH DAC frequency control 4MSbs, PLL control0xC015 rw 0 LEFT DAC left channel PCM value0xC016 rw 0 RIGHT DAC right channel PCM valueEvery fourth clock cycle, an internal 26-bit counter is added to by (DAC FCTLH & 15) × 65536 +DAC FCTLL. Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read anda DAC interrupt is generated.Version 1.00, 2008-02-01 60

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.7 GPIO RegistersGPIO registers, prefix GPIOReg Type Reset Abbrev[bits] Description0xC017 rw 0 DDR[7:0] Direction0xC018 r 0 IDATA[7:0] Values read from the pins0xC019 rw 0 ODATA[7:0] Values set to the pinsGPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers itsvalues even if a GPIO DIR bit is set to input.GPIO registers don’t generate interrupts.Note that in VS1033 the VSDSP registers can be read and written through the SCI WRAMADDR andSCI WRAM registers. You can thus use the GPIO pins quite conveniently.Version 1.00, 2008-02-01 61

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.8 Interrupt RegistersInterrupt registers, prefix INTReg Type Reset Abbrev[bits] Description0xC01A rw 0 ENABLE[7:0] Interrupt enable0xC01B w 0 GLOB DIS[-] Write to add to interrupt counter0xC01C w 0 GLOB ENA[-] Write to subtract from interrupt counter0xC01D rw 0 COUNTER[4:0] Interrupt counterINT ENABLE controls the interrupts. The control bits are as follows:INT ENABLE bitsName Bits DescriptionINT EN TIM1 7 Enable Timer 1 interruptINT EN TIM0 6 Enable Timer 0 interruptINT EN RX 5 Enable UART RX interruptINT EN TX 4 Enable UART TX interruptINT EN MODU 3 Enable AD modulator interruptINT EN SDI 2 Enable Data interruptINT EN SCI 1 Enable SCI interruptINT EN DAC 0 Enable DAC interruptNote: It may take upto 6 clock cycles before changing INT ENABLE has any effect.Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectivelydisables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTERalready was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are restored.An interrupt routine should always write to this register as the last thing it does, because interruptsautomatically add one to the interrupt counter, but subtracting it back to its initial value is theresponsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the registeris not 0, interrupts are disabled.Version 1.00, 2008-02-01 62

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.9 A/D Modulator RegistersInterrupt registers, prefix ADReg Type Reset Abbrev[bits] Description0xC01E rw 0 DIV A/D Modulator divider0xC01F rw 0 DATA A/D Modulator dataAD DIV bitsName Bits DescriptionADM POWERDOWN 15 1 in powerdownADM DIVIDER 14:0 DividerADM DIVIDER controls the AD converter’s sampling frequency. To gather one sample, 128 × n clockcycles are used (n is value of AD DIV). The lowest usable value is 4, which gives a 48 kHz sample ratewhen CLKI is 24.576 MHz. When ADM POWERDOWN is 1, the A/D converter is turned off.AD DATA contains the latest decoded A/D value.Version 1.00, 2008-02-01 63

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.10 Watchdog v1.0 2002-08-26The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is inactive.The counter reload value can be set by writing to WDOG CONFIG. The watchdog is activated by writing0x4ea9 to register WDOG RESET. Every time this is done, the watchdog counter is reset. Every65536’th clock cycle the counter is decremented by one. If the counter underflows, it will activate vsdsp’sinternal reset sequence.Thus, after the first 0x4ea9 write to WDOG RESET, subsequent writes to the same register with thesame value must be made no less than every 65536×WDOG CONFIG clock cycles.Once started, the watchdog cannot be turned off. Also, a write to WDOG CONFIG doesn’t change thecounter reload value.After watchdog has been activated, any read/write operation from/to WDOG CONFIG or WDOG DUMMYwill invalidate the next write operation to WDOG RESET. This will prevent runaway loops from resettingthe counter, even if they do happen to write the correct number. Writing a wrong value toWDOG RESET will also invalidate the next write to WDOG RESET.Reads from watchdog registers return undefined values.10.10.1 RegistersWatchdog, prefix WDOGReg Type Reset Abbrev Description0xC020 w 0 CONFIG Configuration0xC021 w 0 RESET Clock configuration0xC022 w 0 DUMMY[-] Dummy registerVersion 1.00, 2008-02-01 64

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.11 UART v1.1 2004-10-09RS232 UART implements a serial interface using rs232 standard.Startbit D0 D1 D2 D3 D4 D5 D6 D7 StopbitFigure 17: RS232 Serial Interface ProtocolWhen the line is idling, it stays in logic high state. When a byte is transmitted, the transmission beginswith a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logichigh). 10 bits are sent for each 8-bit byte frame.10.11.1 RegistersUART registers, prefix UARTxReg Type Reset Abbrev Description0xC028 r 0 STATUS[4:0] Status0xC029 r/w 0 DATA[7:0] Data0xC02A r/w 0 DATAH[15:8] Data High0xC02B r/w 0 DIV Divider10.11.2 Status UARTx STATUSA read from the status register returns the transmitter and receiver states.UARTx STATUS BitsName Bits DescriptionUART ST FRAMEERR 4 Framing error (stop bit was 0)UART ST RXORUN 3 Receiver overrunUART ST RXFULL 2 Receiver data register fullUART ST TXFULL 1 Transmitter data register fullUART ST TXRUNNING 0 Transmitter runningUART ST FRAMEERR is set if the stop bit of the received byte was 0.UART ST RXORUN is set if a received byte overwrites unread data when it is transferred from thereceiver shift register to the data register, otherwise it is cleared.UART ST RXFULL is set if there is unread data in the data register.UART ST TXFULL is set if a write to the data register is not allowed (data register full).UART ST TXRUNNING is set if the transmitter shift register is in operation.Version 1.00, 2008-02-01 65

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.11.3 Data UARTx DATAA read from UARTx DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there isno more data to be read, the receiver data register full indicator will be cleared.A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiverdata register.A write to UARTx DATA sets a byte for transmission. The data is taken from bits 7:0, other bits in thewritten value are ignored. If the transmitter is idle, the byte is immediately moved to the transmitter shiftregister, a transmit interrupt request is generated, and transmission is started. If the transmitter is busy,the UART ST TXFULL will be set and the byte remains in the transmitter data register until the previousbyte has been sent and transmission can proceed.10.11.4 Data High UARTx DATAHThe same as UARTx DATA, except that bits 15:8 are used.10.11.5 Divider UARTx DIVUARTx DIV BitsName Bits DescriptionUART DIV D1 15:8 Divider 1 (0..255)UART DIV D2 7:0 Divider 2 (6..255)The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending on themaster clock frequency to get the correct bit speed. The second divider (D 2 ) must be from 6 to 255.The communication speed f =TX/RX speed in bps.f m(D 1 +1)×(D 2 ) , where f m is the master clock frequency, and f is theDivider values for common communication speeds at 26 MHz master clock:Example UART Speeds, f m = 26MHzComm. Speed [bps] UART DIV D1 UART DIV D24800 85 639600 42 6314400 42 4219200 51 2628800 42 2138400 25 2657600 1 226115200 0 226Version 1.00, 2008-02-01 66

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.11.6 Interrupts and OperationTransmitter operates as follows: After an 8-bit word is written to the transmit data register it will betransmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmissionbegins a TX INTR interrupt will be sent. Status bit [1] informs the transmitter data register empty (orfull state) and bit [0] informs the transmitter (shift register) empty state. A new word must not be writtento transmitter data register if it is not empty (bit [1] = ’0’). The transmitter data register will be emptyas soon as it is shifted to transmitter and the transmission is begun. It is safe to write a new word totransmitter data register every time a transmit interrupt is generated.Receiver operates as follows: It samples the RX signal line and if it detects a high to low transition, astart bit is found. After this it samples each 8 bit at the middle of the bit time (using a constant timer),and fills the receiver (shift register) LSB first. Finally the data in the receiver is moved to the reveivedata register, the stop bit state is checked (logic high = ok, logic low = framing error) for status bit[4],the RX INTR interrupt is sent, status bit[2] (receive data register full) is set, and status bit[2] old state iscopied to bit[3] (receive data overrun). After that the receiver returns to idle state to wait for a new startbit. Status bit[2] is zeroed when the receiver data register is read.RS232 communication speed is set using two clock dividers. The base clock is the processor masterclock. Bits 15-8 in these registers are for first divider and bits 7-0 for second divider. RX samplefrequency is the clock frequency that is input for the second divider.Version 1.00, 2008-02-01 67

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.12 Timers v1.0 2002-04-23There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled,a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle.When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start valueregister, and continues downcounting. A timer stays in that loop as long as it is enabled.A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding thetimer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer isenabled (1) or disabled (0) by a corresponding bit of the enable register.10.12.1 RegistersTimer registers, prefix TIMERReg Type Reset Abbrev Description0xC030 r/w 0 CONFIG[7:0] Timer configuration0xC031 r/w 0 ENABLE[1:0] Timer enable0xC034 r/w 0 T0L Timer0 startvalue - LSBs0xC035 r/w 0 T0H Timer0 startvalue - MSBs0xC036 r/w 0 T0CNTL Timer0 counter - LSBs0xC037 r/w 0 T0CNTH Timer0 counter - MSBs0xC038 r/w 0 T1L Timer1 startvalue - LSBs0xC039 r/w 0 T1H Timer1 startvalue - MSBs0xC03A r/w 0 T1CNTL Timer1 counter - LSBs0xC03B r/w 0 T1CNTH Timer1 counter - MSBs10.12.2 Configuration TIMER CONFIGTIMER CONFIG BitsName Bits DescriptionTIMER CF CLKDIV 7:0 Master clock dividerTIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clockfrequency f i = fmc+1 , where f m is the master clock frequency and c is TIMER CF CLKDIV. Example:With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/samplingclock would thus be f i = 12MHz3+1= 3MHz.Version 1.00, 2008-02-01 68

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.12.3 Configuration TIMER ENABLETIMER ENABLE BitsName Bits DescriptionTIMER EN T1 1 Enable timer 1TIMER EN T0 0 Enable timer 010.12.4 Timer X Startvalue TIMER Tx[L/H]The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timerinterrupt frequency f t =f ic+1 where f i is the master clock obtained with the clock divider (see Chapter10.12.2 and c is TIMER Tx[L/H].Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock f i = 3MHz.If TIMER TH=0, TIMER TL=99, then the timer interrupt frequency f t = 3MHz99+1 = 30kHz.10.12.5 Timer X Counter TIMER TxCNT[L/H]TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may getknowledge of how long it will take before the next timer interrupt. Also, by writing to this register, aone-shot different length timer interrupt delay may be realized.10.12.6 InterruptsEach timer has its own interrupt, which is asserted when the timer counter underflows.Version 1.00, 2008-02-01 69

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.13 I2S DAC InterfaceThe I2S Interface makes it possible to attach an external DAC to the system.10.13.1 RegistersI2S registers, prefix I2SReg Type Reset Abbrev Description0xC040 r/w 0 CONFIG[3:0] I2S configuration10.13.2 Configuration I2S CONFIGI2S CONFIG BitsName Bits DescriptionI2S CF MCLK ENA 3 Enables the MCLK output (12.288 MHz)I2S CF ENA 2 Enables I2S, otherwise pins are GPIOI2S CF SRATE 1:0 I2S rate, ”10” = 192, ”01” = 96, ”00” = 48 kHzI2S CF ENA enables the I2S interface. After reset the interface is disabled and the pins are used forGPIO.I2S CF MCLK ENA enables the MCLK output. The frequency is either directly the input clock (nominal12.288 MHz), or half the input clock when mode register bit SM CLK RANGE is set to 1 (24-26 MHz input clock).I2S CF SRATE controls the output samplerate. When set to 48 kHz, SCLK is MCLK divided by 8,when 96 kHz SCLK is MCLK divided by 4, and when 192 kHz SCLK is MCLK divided by 2.MCLKSCLKLROUTSDATAMSB LSB MSBLeft Channel WordRight Channel WordFigure 18: I2S Interface, 192 kHz.To enable I2S first write 0xc017 to SCI WRAMADDR and 0x33 to SCI WRAM, then write 0xc040 toSCI WRAMADDR and 0x0c to SCI WRAM.See application notes for more information.Version 1.00, 2008-02-01 70

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.14 System Vector TagsThe System Vector Tags are tags that may be replaced by the user to take control over several decoderfunctions.10.14.1 AudioInt, 0x20Normally contains the following VS DSP assembly code:jmpi DAC_INT_ADDRESS,(i6)+1The user may, at will, replace the first instruction with a jmpi command to gain control over the audiointerrupt.10.14.2 SciInt, 0x21Normally contains the following VS DSP assembly code:jmpi SCI_INT_ADDRESS,(i6)+1The user may, at will, replace the instruction with a jmpi command to gain control over the SCI interrupt.10.14.3 DataInt, 0x22Normally contains the following VS DSP assembly code:jmpi SDI_INT_ADDRESS,(i6)+1The user may, at will, replace the instruction with a jmpi command to gain control over the SDI interrupt.10.14.4 ModuInt, 0x23Normally contains the following VS DSP assembly code:jmpi MODU_INT_ADDRESS,(i6)+1The user may, at will, replace the instruction with a jmpi command to gain control over the AD Modulatorinterrupt.Version 1.00, 2008-02-01 71

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.14.5 TxInt, 0x24Normally contains the following VS DSP assembly code:jmpi EMPTY_INT_ADDRESS,(i6)+1The user may, at will, replace the instruction with a jmpi command to gain control over the UART TXinterrupt.10.14.6 RxInt, 0x25Normally contains the following VS DSP assembly code:jmpi RX_INT_ADDRESS,(i6)+1The user may, at will, replace the first instruction with a jmpi command to gain control over the UARTRX interrupt.10.14.7 Timer0Int, 0x26Normally contains the following VS DSP assembly code:jmpi EMPTY_INT_ADDRESS,(i6)+1The user may, at will, replace the first instruction with a jmpi command to gain control over the Timer0 interrupt.10.14.8 Timer1Int, 0x27Normally contains the following VS DSP assembly code:jmpi EMPTY_INT_ADDRESS,(i6)+1The user may, at will, replace the first instruction with a jmpi command to gain control over the Timer1 interrupt.Version 1.00, 2008-02-01 72

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERS10.14.9 UserCodec, 0x0Normally contains the following VS DSP assembly code:jrnopIf the user wants to take control away from the standard decoder, the first instruction should be replacedwith an appropriate j command to user’s own code.The system activates the user program in less than 1 ms. After this, the user should steal interrupt vectorsfrom the system, and insert user programs.10.15 System Vector FunctionsThe System Vector Functions are pointers to some functions that the user may call to help implementinghis own applications.10.15.1 WriteIRam(), 0x2VS DSP C prototype:void WriteIRam(register i0 u int16 *addr, register a1 u int16 msW, register a0 u int16 lsW);This is the preferred way to write to the User Instruction RAM.10.15.2 ReadIRam(), 0x4VS DSP C prototype:u int32 ReadIRam(registeri0 u int16 *addr);This is the preferred way to read from the User Instruction RAM.A1 contains the MSBs and A0 the LSBs of the result.10.15.3 DataBytes(), 0x6VS DSP C prototype:u int16 DataBytes(void);Version 1.00, 2008-02-01 73

VLSISolution yVS1033cVS1033C10. VS1033 REGISTERSIf the user has taken over the normal operation of the system by switching the pointer in UserCodecto point to his own code, he may read data from the Data Interface through this and the following twofunctions.This function returns the number of data bytes that can be read.10.15.4 GetDataByte(), 0x8VS DSP C prototype:u int16 GetDataByte(void);Reads and returns one data byte from the Data Interface. This function will wait until there is enoughdata in the input buffer. Audio interrupts must be enabled for this function to work.10.15.5 GetDataWords(), 0xaVS DSP C prototype:void GetDataWords(register i0 y u int16 *d, register a0 u int16 n);Read n data byte pairs and copy them in big-endian format (first byte to MSBs) to d. This function willwait until there is enough data in the input buffer. Audio interrupts must be enabled for this function towork.Version 1.00, 2008-02-01 74

VLSISolution yVS1033cVS1033C11. DOCUMENT VERSION CHANGES11 Document Version ChangesThis chapter describes the most important changes to this document.Version 1.00 for VS1033c, 2008-02-01• Production version, removed “PRELIMINARY” tag.• Fully qualified values to tables in Chapter 4.• Added an example to Chapter 9.7, Feeding PCM Data.Version 0.92 for VS1033c, 2008-01-16• Max SCI speed changed to CLKI/7.• Typical connection diagram updated.• Max CLKI changed to 50 MHz.• AVDD recommended minimum set to 2.7 V.Version 0.91 for VS1033c, 2007-02-12• GBUF connection in Connection diagram changed (figure 3 in section 6).GBUF must have 10 Ω and 47 nF to ground.• Mention of the 8 kHz Phone Application removed.VS1033c.Other features have replaced this code inVersion 0.9 for VS1033c, 2006-08-15• EarSpeaker documentation added.Version 0.8 for VS1033b, 2006-05-19• Mention of quiet power-off added to feature list.Version 0.6 for VS1033a, 2006-01-05• ADPCM recording section added (section 9.4).Version 1.00, 2008-02-01 75

VLSISolution yVS1033cVS1033C12. CONTACT INFORMATION12 Contact InformationVLSI Solution OyEntrance G, 2nd floorHermiankatu 8FIN-33720 TampereFINLANDFax: +358-3-3140-8288Phone: +358-3-3140-8200Email: sales@vlsi.fiURL: http://www.vlsi.fi/Version 1.00, 2008-02-01 76

VS1033 - MP3/AAC/WMA/MIDI AUDIO CODEC - VLSI Solution

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