AP7175

3A ULTRA LOW DROPOUT LINEAR REGULATOR WITH ENABLE

Description Pin Assignments

The AP7175 is a 3.0A ultra low-dropout (LDO) linear regulator that
features an enable input and a power-good output.

The enable input and power-good output allow users to configure

power management solutions that can meet the sequencing
requirements of FPGAs, DSPs, and other applications with different
start-up and power-down requirements.
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The AP7175 features two supply inputs, for power conversion supply
and control. With the separation of the control and the power input
very low dropout voltages can be reached and power dissipation is
reduced.

A precision reference and feedback control deliver 1.5% accuracy

over load, line, and operating temperature ranges.

The AP7175 is available in SO-8EP and MSOP-8EP package with an

exposed PAD to reduce the junction to case resistance and extend
the temperature range it can be used in.

Features
Applications
• VIN Range: 1.2V to 3.65V VCNTL 3.0V to 5.5V
• Notebook
• Adjustable output voltage
• PC
• Continuous Output Current IOUT = 3A
• Netbook
• Fast transient response
• Wireless Communication
• Power on reset monitoring on VCNTL and VIN
• Server
• Internal Softstart
• Motherboard
• Stable with Low ESR MLCC capacitors
• Dongle
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Front Side Bus VTT (1.2V/3.3A)
• Halogen and Antimony Free. “Green” Device (Note 3)

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.

Typical Applications Circuit

PG VOUT
R3 R1 C1
5.1KΩ 12KΩ *Optional
VCNTL COUT
CCNTL FB
10uF
R2
1uF
AP7175 24KΩ
VIN
CIN
10uF
ON
OFF EN GND

Figure 1. Typical Application Circuit

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Pin Descriptions

Pin Pin Number

Function
Name SO-8EP MSOP-8EP
GND 1 1 Ground
FB 2 2 Feedback to set the output voltage via an external resistor divider between VOUT and GND.
Power Output Pin. Connect at least 10µF capacitor to this pin to improve transient response and
VOUT 3/4 3/4 required for stability. When the part is disabled the output is discharged via an internal pull-low
MOSFET.
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Power Input Pin for current supply. Connect a decoupling capacitor (≥10µF) as close as possible to
VIN 5 5
the pin for noise filtering.
BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor (≥1µF) as close
VCNTL 6 6
as possible to the pin for noise filtering.
Power Good output open drain to indicate the status of VOUT via monitoring the FB pin. This pin is
PG 7 7 pulled low when the voltage is outside the limits, during thermal shutdown and if either VCNTL or VIN
go below their thresholds.
Enable pin. Driving this pin low will disable the part. When left floating an internal current source will
EN 8 8
pull this pin high and enable it.
PAD EP EP Exposed pad connect this to VIN for good thermal conductivity.

Functional Block Diagram

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Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.)

Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 to +4.0 V
VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 to +7.0 V
VOUT VOUT to GND Voltage -0.3 to VIN +0.3 V
PG to GND Voltage -0.3 to +7.0 V
EN, FB to GND Voltage -0.3 to VCNTL +0.3 V
Power Dissipation (SO-8EP) 1.7 W
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PD
Power Dissipation (MSOP-8EP) 1.5
TJ Maximum Junction Temperature 150 °C
TSTG Storage Temperature -65 to +150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Note: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may
be affected by exposure to absolute maximum rating conditions for extended periods of time.

Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.)

Symbol Parameter Min Max Unit

VCNTL VCNTL Supply Voltage 3.0 5.5 V
VIN VIN Supply Voltage 1.2 3.65 V
VOUT VOUT Output Voltage (when VCNTL-VOUT >1.9V) 0.8 VIN - VDROP V
Continuous Current 0 3
IOUT VOUT Output Current A
Peak Current 0 4
IOUT = 3A at 25% nominal VOUT 8 1100
COUT VOUT Output Capacitance IOUT = 2A at 25% nominal VOUT 8 1700 µF
IOUT = 1A at 25% nominal VOUT 8 2400
ESRCOUT ESR of VOUT Output Capacitor 0 200 mΩ
TA Ambient Temperature -40 +85 °C
TJ Junction Temperature -40 +125 °C

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Electrical Characteristics
(VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40 to +85°C, @TA = +25°C, unless otherwise specified.)

AP7175
Symbol Parameter Test Conditions Unit
Min Typ Max
SUPPLY CURRENT
IVCNTL VCNTL Supply Current EN = VCNTL, IOUT=0A — 1.0 1.5 mA
VCNTL Supply Current at
ISD EN = GND — 15 30 µA
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Shutdown
VIN Supply Current at Shutdown EN = GND, VIN=3.65V — — 1 µA
POWER-ON-RESET (POR)
Rising VCNTL POR Threshold 2.5 2.7 2.95 V
VCNTL POR Hysteresis — 0.4 — V
Rising VIN POR Threshold 0.8 0.9 1.0 V
VIN POR Hysteresis — 0.5 — V
OUTPUT VOLTAGE
Reference Voltage FB = VOUT — 0.8 — V
VCNTL =3.0 ~ 5.5V, IOUT = 0 to 3A,
Output Voltage Accuracy -1.5 — +1.5 %
TJ = -40 to +125°C
VREF Load Regulation IOUT =0A to 3A — 0.06 0.25 %
Line Regulation IOUT =10mA, VCNTL = 3.0 to 5.5V -0.15 — +0.15 %/V
VOUT Pull-low Resistance VCNTL = 3.3V, VEN = 0V, VOUT < 0.8V — 10 — Ω
FB Input Current VFB = 0.8V -100 — 100 nA
DROPOUT VOLTAGE
TJ = +25°C 0.26 0.31
VOUT = 2.5V
TJ = -40 to +125°C 0.42
VIN-to-VOUT Dropout Voltage VCNTL = 5.0V, TJ = +25°C 0.24 0.29
VDROP VOUT = 1.8V V
(Note 5) IOUT = 3A TJ = -40 to +125°C 0.40
TJ = +25°C 0.23 0.28
VOUT = 1.2V
TJ = -40 to +125°C 0.38
TJ = +25°C, VOUT = 80% VNOMiNAL 4.5 5.7 6.7 A
ILIM Current-Limit Level
TJ = -40 to +125°C 4.2 A
PROTECTIONS
ISHORT Short Current-Limit Level VFB < 0.2V — 1.1 — A
TSD Thermal Shutdown Temperature TJ rising — 170 °C
Thermal Shutdown Hysteresis — 50 — °C
ENABLE AND SOFT-START
EN Logic High Threshold Voltage VEN rising 0.5 0.8 1.1 V
EN Hysteresis 0.1 — V
EN Pull-High Current EN = GND — 5 — uA
TSS Soft-Start Interval 0.3 0.6 1.2 ms
Turn On Delay From being enabled to VOUT rising 10% 200 350 500 us
POWER-GOOD AND DELAY
VTHPG Rising PG Threshold Voltage VFB rising 90 92 95 %
PG Threshold Hysteresis — 8 — %
PG Pull-low Voltage PG sinks 5mA — 0.25 0.4 V
VFB < falling PG voltage
PG Debounce Interval — 10 — µs
threshold
From VFB = VTHPG to rising
PG Delay Time 1 2 4 ms
edge of the VPG
Note: 5. Dropout voltage is the voltage difference between the inut and the output at which the output voltage drops 2% below its nominal value.

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Electrical Characteristics (cont.)

(VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40 to +85°C, @TA = +25°C, unless otherwise specified.)

AP7175
Symbol Parameter Test Conditions Unit
Min Typ Max
THERMAL CHARACTERISTIC
SO-8EP (Note 6) 70 °C/W
θJA Thermal Resistance Junction-to-Ambient
MSOP-8EP (Note 7) 80 °C/W
SO-8EP (Note 6) 30 °C/W
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θJC Thermal Resistance Junction-to-Ambient

MSOP-8EP (Note 7) 30 °C/W
Notes: 6. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and thermal vias to bottom layer ground
plane.
7. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper,with minimum recommended pad layout.

Typical Characteristics

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Typical Characteristics (cont.)

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Operating Waveforms (@ VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V, TA = +25°C, unless otherwise specified.)

Power On Power Off

VCNTL

VCNTL

VIN VIN
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VOUT
VOUT

VPOK VPOK

COUT=10µF, CIN=10µF, RL=0.4Ω COUT=10µF, CIN=10µF, RL=0.4Ω

CH1: VCNTL, 5V/Div, DC CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC CH2: VIN, 1V/Div, DC
CH3: VOUT, 1V/Div, DC CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC CH4: VPOK, 5V/Div, DC
TIME: 2ms/Div TIME: 2ms/Div

Load Transient Response Over Current Protection

VOUT
VOUT

IOUT
IOUT

IOUT = 10mA to 3A to10mA (rise / fall time =1µs)

COUT = 10µF, CIN = 10µF, IOUT = 2A to 5.6A
COUT = 10µF, CIN = 10µF
CH1: VOUT, 0.5V/Div, DC
CH1: VOUT, 50mV/Div, AC
CH2: IOUT, 2A/Div, DC
CH2: IOUT, 1A/Div, DC
TIME: 0.2ms/Div
TIME: 50µs/Div

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Operating Waveforms (cont.) (@ VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V, TA = +25°C, unless otherwise specified.)

Shutdown Enable

VEN VEN

VOUT
VOUT
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VPOK VPOK

IOUT IOUT

COUT = 10µF, CIN = 10µF, RL = 0.4Ω COUT = 10µF, CIN = 10µF, RL = 0.4Ω
CH1: VEN, 5V/Div, DC CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC CH2: VOUT, 1V/Div, DC
CH3: VPOK, 5V/Div, DC CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC CH4: IOUT, 2A/Div, DC
TIME: 4µs/Div TIME: 1ms/Div

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Application Information
Power Good and Delay
AP7175 monitors the feedback voltage VFB on the FB pin. An internal delay timer is started after the PG voltage threshold (VTHPG) on the FB pin
is reached. At the end of the delay time an internal NMOS of the PG is turned off to indicate that the power at the output is good (PG). This
monitoring function is continued during operation and if VFB falls 8% (typ) below VTHPG, the NMOS of the PG is turned on after a delay time of
typical 10µs to avoid oscillating of the PG signal.

Power On Reset
AP7175 monitors both supply voltages, VCNTL and VIN to ensure operation as intended. A Soft-Start process is initiated after both voltages
NEW PRODUCT

exceed their POR threshold during power on. During operation the POR component continues to monitor the supply voltage and pulls the PG low
to indicate an out of regulation supply. This function will engage without regard to the status of the output.

Soft-Start
AP7175 incorporates an internal Soft-Start function. The output voltage rise is controlled to limit the current surge during start-up. The typical
Soft-Start time is 0.6ms.

Current-Limit Protection
AP7175 monitors the current flow through the NMOS and limits the maximum current to avoid damage to the load and AP7175 during overload
conditions.

Short Circuit Current-Limit Protection

AP7175 incorporates a current limit function to reduce the maximum current to 1.1A (typ) when the voltage at FB falls below 0.2V (typ) during an
overload or short circuit situation.
During start-up period, this function is disabled to ensure successful heavy load start-up.

Enable Control
If the enable pin (EN) is left open, an internal current source of ~5µA pulls the pin up and enables the AP7175. This will reduce the bill of material
saving an external pull up resistor. Driving the enable pin low disables the device. Driving the pin high subsequently initiates a new Soft-Start
cycle.

Output Voltage Regulation

Output Voltage is set by resistor divider from VOUT via FB pin to GND. Internally VFB is compared to a 0.8V temperature compensated reference
voltage and the NMOS pass element regulates the output voltage while delivering current from VIN to VOUT.

Setting the Output Voltage

A resistor divider connected to FB pin programs the output voltage.

⎛ R1 ⎞
V OUT = VREF * ⎜1 + ⎟V
⎝ R2 ⎠

R1 is connected from VOUT to FB with Kelvin sensing connection. R2 is connected from FB to GND. To improve load transient response and
stability, a bypass capacitor can be connected in parallel with R1. (optional in typical application circuit)

Power Sequencing
AP7175 requires no specific sequencing between VIN and VCNTL. However, care should be taken to avoid forcing VOUT for prolonged times
without the presence of VIN. Conduction through internal parasitic diode (from VOUT to VIN) could damage AP7175.

Thermal Shutdown
The PCB layout and power requirements for AP7175 under normal operation condition should allow enough cooling to restrict the junction
temperature to +125°C. The packages for AP7175 have an exposed PAD to support this. These packages provide better connection to the PCB
and thermal performance. Refer to the layout considerations.

If AP7175 junction temperature reaches +170°C a thermal protection block disables the NMOS pass element and lets the part cool down. After
its junction temperature drops by 50°C (typ), a new Soft-Start cycle will be initiated. A new thermal protection will start, if the load or ambient
conditions continue to raise the junction temperature to +170°C. This cycle will repeat until normal operation temperature is maintained again.

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Application Information (cont.)

Output Capacitor
An output capacitor (COUT) is needed to improve transient response and maintain stability. The ESR (equivalent series resistance) and
capacitance drives the selection. Care needs to be taken to cover the entire operating temperature range.
The output capacitor can be an Ultra-Low-ESR ceramic chip capacitor or a low ESR bulk capacitor like a solid tantalum, POSCap or aluminum
electrolytic capacitor.

COUT is used to improve the output stability and reduces the changes of the output voltage during load transitions. The slew rate of the current
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sensed via the FB pin in AP7175 is reduced. If the application has large load variations, it is recommended to utilize low-ESR bulk capacitors.
It is recommended to place ceramic capacitors as close as possible to the load and the ground pin and care should be taken to reduce the
impedance in the layout.

Input Capacitor
To prevent the input voltage from dropping during load steps it is recommended to utilize an input capacitor (CIN). As with the output capacitor
the following are acceptable, Ultra-Low-ESR ceramic chip capacitor or low ESR bulk capacitor like a solid tantalum, POSCap or aluminum
electrolytic capacitor. Typically it is recommended to utilize an capacitance of at least 10µF to avoid output voltage drop due to reduced input
voltage. The value can be lower if VIN changes are not critical for the application.

Layout Considerations
For good ground loop and stability, the input and output capacitors should be located close to the input, output, and ground pins of the device.
No other application circuit is connected within the loop. Avoid using vias within ground loop. If vias must be used, multiple vias should be used
to reduce via inductance.

The regulator ground pin should be connected to the external circuit ground to reduce voltage drop caused by trace impedance. Ground plane is
generally used to reduce trace impedance.

Wide trace should be used for large current paths from VIN to VOUT, and load circuit.

Place the R1, R2, and C1(optional) near the LDO as close as possible to avoid noise coupling.

R2 is placed close to device ground. Connect the ground of the R2 to the GND pin by using a dedicated trace.

Connect the pin of the R1 directly to the load for Kelvin sensing.

No high current should flow through the ground trace of feedback loop and affect reference voltage stability.

For the packages with exposed pads, heat sinking is accomplished using the heat spreading capability of the PCB and its copper traces.
Suitable PCB area on the top layer and thermal vias(0.3mm drill size with 1mm spacing, 4~8 vias at least) to the Vin power plane can help to
reduce device temperature greatly.

Reference Layout Plots

Top Layer Bottom Layer

Cin
Vin Cout Vout

Vin

GND

Vcntl
FB R1

PG PG
1 GND
GND C1
Ccntl EN R2
EN

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Ordering Information
NEW PRODUCT

13” Tape and Reel

Part Number Package Code Packaging
Quantity Part Number Suffix
AP7175SP-13 SP SO-8EP 2500/Tape & Reel -13
AP7175MP-13 MP MSOP-8EP 2500/Tape & Reel -13

Marking Information
(1) SO-8EP

(2) MSOP-8EP

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Package Outline Dimensions (All dimensions in mm.)

Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for latest version.
(1) SO-8EP

SO-8EP (SOP-8L-EP)
Exposed Pad Dim Min Max Typ
8 5 A 1.40 1.50 1.45
A1 0.00 0.13 -
E1 b 0.30 0.50 0.40
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H
C 0.15 0.25 0.20
1 4 D 4.85 4.95 4.90
F
E 3.80 3.90 3.85
E0 3.85 3.95 3.90
b E1 5.90 6.10 6.00
Bottom View
e - - 1.27
E F 2.75 3.35 3.05
9° (All sides) N
45° H 2.11 2.71 2.41
7°
Q L 0.62 0.82 0.72
A 4° ± 3° C N - - 0.35
Gauge Plane
Seating Plane Q 0.60 0.70 0.65
e
A1 E0 All Dimensions in mm
D L

(2) MSOP-8EP

MSOP-8EP
D Dim Min Max Typ
A - 1.10 -
A1 0.05 0.15 0.10
4X A2 0.75 0.95 0.86
10 A3 0.29 0.49 0.39
D1 °
0.25

x b 0.22 0.38 0.30

E E2 c 0.08 0.23 0.15
Gauge Plane
D 2.90 3.10 3.00
y Seating Plane
D1 1.60 2.00 1.80
a

E 4.70 5.10 4.90

4X L
10
° E1 2.90 3.10 3.00
1 E2 1.30 1.70 1.50
e 8Xb
E3 Detail C E3 2.85 3.05 2.95
A1 A3 e - - 0.65
c
A2 L 0.40 0.80 0.60
A
a 0° 8° 4°
D E1 x - - 0.750
y - - 0.750
See Detail C All Dimensions in mm

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Suggested Pad Layout

Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.
(1) SO-8EP

X2

Value
Dimensions
(in mm)
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C 1.270
X 0.802
Y1 X1 3.502
Y2
X2 4.612
X1 Y 1.505
Y1 2.613
Y2 6.500
Y

C X

(2) MSOP-8EP
X C

Y Value
G Dimensions
(in mm)
C 0.650
G 0.450
X 0.450
Y2 Y1 X1 2.000
X1 Y 1.350
Y1 1.700
Y2 5.300

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