Maintenance Manual: MANUAL NUMBER 006-15563-0001 Revision 1 May, 2003

MAINTENANCE MANUAL
KT 73
MODE S
TRANSPONDER
MANUAL NUMBER 006-15563-0001

REVISION 1 MAY, 2003
WARNING
The enclosed technical data is eligible for export under License Designation NLR and is to be
used solely by the individual/organization to whom it is addressed. Diversion contrary to U.S. law
is prohibited.
COPYRIGHT NOTICE
©2003 Honeywell International Inc.
Reproduction of this publication or any portion thereof by any means without the express written
permission of Honeywell is prohibited. For further information contact the manager, Technical
Publications, Honeywell, One Technology Center, 23500 West 105th Street Olathe KS 66061
telephone: (913) 712-0400.
B KT 73
REVISION HISTORY
KT 73 Maintenance Manual
Part Number: 006-15563-XXXX
For each revision, add, delete, or replace pages as indicated.
REVISION: Rev. 0, April/2003
ITEM ACTION
New manual No previous manual revision exists.
REVISION: Rev. 1, May/2003
ITEM ACTION
Full Reprint Replaces revision 0.
Rev. 1, May/2003 15563M01.JA Page RH-1

B KT 73
THIS PAGE IS RESERVED
Rev. 1, May/2003 15563M01.JA Page RH-2

B KT 73
TABLE OF CONTENTS
SECTION IV
THEORY OF OPERATION
PARAGRAPH PAGE
4.1 GENERAL 4-1

4.1.1 INTERROGATOR-TRANSPONDER INTERACTION 4-3
4.1.2 INTERROGATION FORMATS 4-3
4.1.3 MODE S TRANSMISSION CONTENT 4-10
4.1.4 REPLY FORMATS 4-10
4.1.5 KT 73 REPLY PULSE CHARACTERISTICS 4-19
4.1.6 KT 73 ATCRBS/MODE S ALL-CALL REPLIES 4-21
4.1.7 KT 73 ATCRBS, ATCRBS-ONLY ALL-CALL AND ATCRBS/MODE S ALL-CALL 4-21
4.1.8 TRAFFIC INFORMATION SERVICE DATA LINK 4-23
4.1.9 DEFINITION OF AUTOMATIC DEPENDENT SURVEILLANCE - BROADCAST 4-24
4.2 GENERAL CIRCUIT THEORY 4-29
4.3 DETAILED CIRCUIT THEORY 4-30
4.3.1 RECEIVER BOARD 4-30
4.3.2 MODULATOR BOARD 4-32
4.3.3 POWER SUPPLY BOARD 4-34
4.3.4 TRANSMITTER BOARD 4-39
4.3.5 DISPLAY BOARD 4-41
4.3.6 MAIN BOARD AND EEPROM BOARD 4-43
SECTION V
MAINTENANCE
PARAGRAPH PAGE
5.1 INTRODUCTION 5-1

5.1.1 GENERAL 5-1
5.1.2 ATC TRANSPONDER TESTS AND INSPECTIONS 5-1
5.1.3 KT 73 FIELD SOFTWARE LOAD PROCEDURE 5-1
5.2 TEST, ALIGNMENT AND TROUBLE SHOOTING 5-3
5.2.1 TEST EQUIPMENT REQUIRED 5-3
5.2.2 TESTING AND TROUBLESHOOTING 5-4
5.2.3 TESTING EQUIPMENT SETUP 5-4
5.2.4 FUNCTIONAL TEST PROCEDURE 5-9
Rev. 1, May/2003 15563M01.JA Page TC-1

B KT 73
SECTION
MAINTENANCE (cont).
PARAGRAPH PAGE
5.2.5 RETURN TO SERVICE TESTS 5-15

5.2.6 ALIGNMENT PROCEDURES SETUP 5-23
5.2.7 ALIGNMENT PROCEDURES 5-23
5.3 GENERAL OVERHAUL 5-37
5.3.1 VISUAL INSPECTION 5-37
5.3.2 CLEANING 5-38
5.3.3 REPAIR 5-43
5.3.4 DISASSEMBLY/ASSEMBLY PROCEDURES 5-48
5.4 TROUBLESHOOTING 5-61
5.4.1 TROUBLESHOOTING PROCEDURES 5-61
5.4.2 TEST SETUP 5-62
5.4.3 TROUBLESHOOTING PROCEDURES 5-62
5.4.4 FAULT CODES 5-62
5.4.5 TROUBLESHOOTING WAVEFORMS 5-62
5.4.6 TROUBLESHOOTING FLOWCHARTS 5-109
SECTION VI
ILLUSTRATED PARTS LIST
PARAGRAPH PAGE
6.1 GENERAL 6-1

6.2 REVISION SERVICE 6-1
6.3 LIST OF ABBREVIATIONS 6-1
6.4 SAMPLE PARTS LIST 6-3
6.5 KT 73 FINAL ASSEMBLY 6-5
6.6 KT 73 CHASSIS ASSEMBLY 6-13
6.7 KT 73 TRANSMITTER BOARD 6-17
6.8 KT 73 MODULATOR BOARD 6-25
6.9 KT 73 FRONT PANEL ASSEMBLY 6-31
6.10 KT 73 DISPLAY BOARD 6-35
6.11 KT 73 BEZEL/DECAL ASSEMBLY 6-51
6.12 KT 73 MOUNTING RACK ASSEMBLY 6-55
6.13 KT 73 EXTERNAL EEPROM BOARD 6-59

B KT 73
SECTION VI
ILLUSTRATED PARTS LIST (cont).
PARAGRAPH PAGE
6.14 KT 73 RECEIVER BOARD 6-65

6.15 KT 73 MAIN BOARD/SOFTWARE SET 6-91
6.16 KT 73 POWER SUPPLY BOARD 6-139
CONFIGURATION APPENDIX
PARAGRAPH PAGE
KT 73 HARDWARE/SOFTWARE CONFIGURATIONS APP-1
FIGURES
FIGURE PAGE
4-1 MODE S TRANSPONDER SYSTEM, SIMPLIFIED BLOCK DIAGRAM 4-2

4-2 ATCRBS INTERROGATION PULSES FORMAT 4-4
4-3 ATCRBS/MODE S ALL-CALL FORMAT 4-4
4-4 SIDE LOBE SUPPRESSION CHARACTERISTICS 4-5
4-5 MODE S INTERROGATION, UPLINK FORMAT 4-6
4-6 UPLINK FORMATS 4-7
4-7 ATCRBS AND MODE S REPLY FORMAT 4-11
4-8 DOWNLINK FORMATS 4-13
4-9 1090 MHz ADS-B SYSTEM 4-24
4-10 KT 73 BLOCK DIAGRAM 4-25
4-11 KT 73 INTERNAL INTERCONNECTION DIAGRAM 4-27
4-12 RECEIVER BOARD BLOCK DIAGRAM 4-30
4-13 MODULATOR BOARD BLOCK DIAGRAM 4-32
4-14 POWER SUPPLY BLOCK DIAGRAM 4-35
4-15 U2843D INTERNAL BLOCK DIAGRAM 4-37
4-16 TRANSMITTER BOARD BLOCK DIAGRAM 4-39
4-17 KT 73 MAIN BOARD BLOCK DIAGRAM 4-53
4-18 KT 73 FPGA BLOCK DIAGRAM 4-55

B KT 73
FIGURES (cont).
FIGURE PAGE
5-1 KT73 TRANSPONDER, TEST SETUP 5-5

5-2 KT 73 FRONT PANEL 5-23
5-3 RECEIVER TP6 VIDEO WITH 1030 MHz +/- 3.2 MHz 5-26
5-4 TSS EXAMPLE 5-26
5-5 SAMPLE DPSK EYE DIAGRAM 5-27
5-6 MAIN BOARD TP22 & TP23 OUTPUTS 5-28
5-7 KT 73 TRANSMITTER (Top View) 5-29
5-8 WAVEFORM 1 5-63
5-9 WAVEFORM 2 5-64
5-10 WAVEFORM 3 5-65
5-17 WAVEFORM 10 5-72
5-18 WAVEFORM 11 5-73
5-19 WAVEFORM 12 5-74
5-20 WAVEFORM 13 5-75
5-21 WAVEFORM 14 5-76
5-22 WAVEFORM 15 5-77
5-23 WAVEFORM 16 5-78
5-24 WAVEFORM 17 5-79
5-25 WAVEFORM 18 5-80
5-26 WAVEFORM 19 5-81
5-27 WAVEFORM 20 5-82
5-28 WAVEFORM 21 5-83
5-29 WAVEFORM 22 5-84
5-30 WAVEFORM 23 5-85
5-31 WAVEFORM 24 5-86
5-32 WAVEFORM 25 5-87

B KT 73
FIGURES (cont).
FIGURE PAGE
5-33 WAVEFORM 26 5-88

5-34 WAVEFORM 27 5-89
5-35 WAVEFORM 28 5-90
5-36 WAVEFORM 29 5-91
5-37 WAVEFORM 30 5-92
5-38 WAVEFORM 31 5-93
5-39 WAVEFORM 32 5-94
5-40 WAVEFORM 33 5-95
5-41 WAVEFORM 34 5-96
5-42 WAVEFORM 35 5-97
5-43 WAVEFORM 36 5-98
5-44 WAVEFORM 37 5-99
5-45 WAVEFORM 38 5-100
5-46 WAVEFORM 39 5-101
5-47 WAVEFORM 40 5-102
5-48 WAVEFORM 41 5-103
5-49 WAVEFORM 42 5-104
5-50 WAVEFORM 43 5-105
5-51 WAVEFORM 44 5-106
5-52 WAVEFORM 45 5-107
5-53 WAVEFORM 46 5-108
5-54 KT 73 TROUBLESHOOTING FLOW CHART - KT 73 UNIT 5-111
5-55 KT 73 TROUBLESHOOTING FLOW CHART - POWER SUPPLY BOARD 5-113
5-56 KT 73 TROUBLESHOOTING FLOW CHART- DISPLAY BOARD 5-115
5-57 KT 73 TROUBLESHOOTING FLOW CHART - RECEIVER BOARD 5-119
5-58 KT 73 TROUBLESHOOTING FLOW CHART - MAIN BOARD 5-125
5-59 KT 73 TROUBLESHOOTING FLOW CHART - FPGA 5-131
5-60 KT 73 TROUBLESHOOTING FLOW CHART - MODULATOR/TRANSMITTER
BOARD 5-133
6-1 SAMPLE PARTS LIST 6-3
6-2 KT 73 FINAL ASSEMBLY 6-7
6-3 KT 73 CHASSIS ASSEMBLY 6-15

B KT 73
FIGURES (cont).
FIGURE PAGE
6-4 KT 73 TRANSMITTER BOARD 6-19

6-5 KT 73 TRANSMITTER BOARD SCHEMATIC 6-23
6-6 KT 73 MODULATOR BOARD 6-27
6-7 KT 73 MODULATOR BOARD SCHEMATIC 6-29
6-8 KT 73 FRONT PANEL ASSEMBLY 6-33
6-9 KT 73 DISPLAY BOARD 6-39
6-10 KT 73 DISPLAY BOARD SCHEMATIC 6-43
6-11 KT 73 BEZEL/DECAL ASSEMBLY 6-53
6-12 KT 73 MOUNTING RACK ASSEMBLY 6-57
6-13 KT 73 EXTERNAL EEPROM BOARD 6-61
6-14 KT 73 EXTERNAL EEPROM BOARD SCHEMATIC 6-63
6-15 KT 73 RECEIVER BOARD 6-75
6-16 KT 73 RECEIVER BOARD SCHEMATIC 6-83
6-17 KT 73 MAIN BOARD 6-105
6-18 KT 73 MAIN BOARD SCHEMATIC 6-113
6-19 KT 73 POWER SUPPLY BOARD 6-143
6-20 KT 73 POWER SUPPLY BOARD SCHEMATIC 6-149
TABLES
TABLE PAGE
5-1 Q8 MIXER 5-25

5-2 RECOMMENDED CLEANING AGENTS 5-39
5-3 UNSAFE CLEANING AGENTS 5-40
5-4 SEALANTS AND STAKING COMPOUNDS 5-55

B KT 73
SECTION IV
THEORY OF OPERATION
4.1 GENERAL
The KT 73 General Aviation Mode S Transponder is designed to meet TSO-C112/JTSO-2C112a
for a Class 2A ATCRBS/Mode Select Airborne Transponder System. It is a panel mounted tran-
sponder that fulfills the role of the airborne beacon equipment according to the requirements of
the Air Traffic Radar Beacon System (ATCRBS). Its functionality includes replying to ATCRBS
Mode A and C, Intermode and Mode S interrogations as well as handling Comm A and B Mode S
Data Link protocols. The basic surveillance capability of the KT 73 satisfies the European Mode
S mandate.
The KT 73 is capable of interfacing to the Traffic Information Service (TIS). The KT 73 TIS function
is FAA approved. This data link is intended to improve the safety and efficiency of “see and avoid”
flight by providing the pilot automatic display of nearby traffic and warnings of any potentially
threatening conditions. The display of TIS traffic requires a compatible MFD, currently the KMD
540. TIS is only provided within the service volume of most Mode S terminal radar facilities and
only in the contiguous United States (US).
The KT 73 (with software revision 01/02 or higher) is also capable of Automatic Dependent Sur-
veillance - Broadcast (ADS-B) operation which allows an aircraft or surface vehicle to transmit
position, altitude, vector, and other information for use by other aircraft, surface vehicles, or
ground facilities. The KT 73 ADS-B function is FAA approved. ADS-B requires a source of GPS
data, currently the KLN 94/KLN 900 are the only acceptable sources. The KT 73 has the capability
to transmit extended squitters and to operate in the Extended Squitter/Non Transponder mode.
NOTE:
The Automatic Dependent Surveillance - Broadcast
(ADS-B) function within the KT 73 Mode S Tran-
sponder was tested as compliant to RTCA/DO-260
MOPS for 1090 MHz ADS-B, dated September 13,
2000. There presently is not an infrastructure within
the USA that supports ADS-B usage. The ADS-B in-
frastructure that is in place in Alaska as part of the
Capstone Project operates on a different frequency
than the ADS-B function within the KT 73. The only
active ADS-B infrastructure that the KT 73 is com-
patible with resides on the continent of Australia.
When the USA infrastructure is completed, it is antic-
ipated that there will be additional ADS-B require-
ments that the KT 73 will have to meet to operate the
ADS-B function successfully. It is expected that
compliance to these new requirements will be ac-
complished by a software update to the KT 73 at that
time.
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B KT 73
The KT 73 has been designed to function in an air traffic environment. Refer to Figure 4-1 for a
brief overview of the KT 73 capabilities.
The KT 73 receives 1030MHz interrogations on the transponder’s antenna from ground ATC fa-
cilities. The transponder decodes and processes the interrogations and if required, replies in ei-
ther ATCRBS or Mode S on a frequency of 1090MHz. The replies will include information that is
input to the transponder such as altitude, maximum airspeed, and Mode S I.D. The transponder
reply/transmission types are summarized below:
• ATCRBS Mode A 4096 code replies and SPI.
• ATCRBS Mode C altitude reporting.
• Mode S surveillance replies.
• Squitter transmissions (unsolicited transmissions).
The main functions of the transponder are summarized below:

• Receive ATC interrogations and reply appropriately with ATCRBS Mode A, ATCRBS Mode C,
or Mode S formats.
• Process altitude information for the purpose of reply operation.
FIGURE 4-1 MODE S TRANSPONDER SYSTEM, SIMPLIFIED BLOCK DIAGRAM
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B KT 73
4.1.1 INTERROGATOR-TRANSPONDER INTERACTION

As an aircraft equipped with a transponder enters the airspace served by a Mode S interrogator,
it receives an ATCRBS/Mode S All-Call interrogation which can be understood by both ATCRBS
and Mode S transponders. ATCRBS transponders reply with standard ATCRBS reply format,
while Mode S transponders reply with a Mode S format that includes their discrete (24 bit) Mode
S address. This address, together with location of Mode S aircraft, is entered into a file (put on
roll-call), and on the next scan the Mode S equipped aircraft is discretely addressed. Once on roll-
call, all-call is locked out. Since azimuth and range are known for all aircraft on roll-call, they are
interrogated according to a precomputed schedule. Within this schedule are ATCRBS/Mode S
All-Calls, which provide the tracking of known ATCRBS aircraft and the acquisition of additional
ATCRBS and Mode S aircraft entering the served airspace.
4.1.2 INTERROGATION FORMATS

A. ATCRBS (Mode A and Mode C)
Figure 4-2 illustrates the formats for ATCRBS interrogations to which the KT 73
ATC Transponder can respond. The ATCRBS interrogation pulses; Mode A iden-
tification and Mode C pressure altitude, are decoded by the transponder if P2 is the
proper amplitude and the time interval between the P1 and P3 pulses is within the
following tolerances:
Mode A = 8.0 ±0.2 µsec
Mode C = 21.0 ±0.2 µsec
Optimum transponder operation requires response to ATCRBS interrogations from
the transmitting antenna main beam and not from side lobes. The side lobe sup-
pression (SLS) pulse P2 controls transponder response to side lobe transmissions.
P2 occurs 2 microseconds after P1. The P2 pulse is transmitted as an omni pattern
from the directional antenna as shown in Figure 4-4. When the P2 pulse is in the
main beam, it is at least 6dB less in amplitude than P1, therefore the transponder
will reply to that interrogation.
When the transponder receives an interrogation from a side lobe where P2 ampli-
tude is equal to or greater than P1, the transponder will not respond to that interro-
gation.
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FIGURE 4-2 ATCRBS INTERROGATION PULSES FORMAT
FIGURE 4-3 ATCRBS/MODE S ALL-CALL FORMAT
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B KT 73
FIGURE 4-4 SIDE LOBE SUPPRESSION CHARACTERISTICS
The KT 73 responds to these ATCRBS interrogations with standard ATCRBS reply

format (explained in the paragraph titled, "Reply Formats" later in this manual).
B. ATCRBS/Mode S All-Call
An ATCRBS/Mode S All-Call interrogation, Figure 4-3, contains formats identical
to ATCRBS Mode A and Mode C Pressure Altitude pulses, but with an added P4
pulse. The P4 pulse width is 1.6 microsec. (There is also an ATCRBS Only All-
Call interrogation identical to the ATCRBS/Mode S All-Call interrogation identical
to the ATCRBS/Mode S All-Call interrogation except that the P4 pulse width is 0.8
microsec. A Mode S transponder, although it replies to standard ATCRBS interro-
gations, will not reply to the short P4 interrogation). The Mode S transponder re-
plies to the interrogation with a Mode S reply if the amplitude of P4 is equal to or
greater than the amplitude of P3 - 1dB, or with an ATCRBS reply if the amplitude
of P4 is less than or equal to the amplitude of P3 - 6dB.
C. Mode S
Figure 4-5 illustrates the Mode S interrogation using Uplink Format (UF). The
waveforms used in conjunction with Mode S interrogations are significantly differ-
ent from the simple ATCRBS interrogations. The Mode S interrogation makes use
of Differential Phase-Shift Keying (DPSK) modulation for the purpose of transmit-
ting the 4 Million Bits Per Second (4Mbps), data burst.
The Mode S interrogation uses one of two general formats; the short format with
56 bits of DPSK data or the long format with 112 bits of DPSK data. The signal is
comprised of a P1, P2 preamble followed by a long pulse called P6.
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B KT 73
FIGURE 4-5 MODE S INTERROGATION, UPLINK FORMAT
The P1-P2 pair preceding P6, suppresses replies from ATCRBS transponders to avoid synchro-
nous garble caused by random triggering of ATCRBS transponders by the Mode S interrogation.
A series of "chips" containing the information within P6 starts 0.5 microseconds after the sync
phase reversal. A chip is an un-modulated interval of 0.25 microsecond duration preceded by pos-
sible phase reversals. If preceded by a phase reversal, a chip represents a ONE. If preceded by
no phase reversal, a chip represents a ZERO. There are either 56 or 112 chips. The last chip is
followed by a 0.5 microsecond guard interval which prevents the trailing edge of P6 from interfer-
ing with the demodulation process.
The Uplink Format (UF) consists of 25 Mode S interrogation formats (UF=0 through UF=24), as
defined by RTCA/DO-181C. The term UF=4 means uplink format 4. The UF data is DPSK mod-
ulated and contained only in pulse P6 of Mode S interrogations. Presently, KT 73 units are ca-
pable of processing six uplink formats (UF = 0,4,5,11,20, and 21). Refer to Figure 4-6 for a de-
scription of those formats.
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B KT 73
UPLINK BINARY DATA FIELDS AND NUMBER OF BITS FUNCTIONS

FORMAT FORMAT
NUMBER U #
0 0 0000 P:3 RL:1 P:4 AQ:1 BD:8 P:10 AP:24 Short Air-Air Surveil-
lance (ACAS)
4 0 0100 PC:3 RR:5 DI:3 SD:16 AP:24 Surveillance, Altitude

Request
Surveillance Identity Re-
5 0 0101 PC:3 RR:5 DI:3 SD:16 AP:24 quest
11 0 1011 PR:4 IC:4 CL:3 P:16 AP:24 Mode S-Only All-Call
20 1 0100 PC:3 RR:5 DI:3 SD:16 MA:56 AP:24 Surveillance, Altitude

Request
21 1 0101 PC:3 RR:5 DI:3 SD:16 MA:56 AP:24 Mode S-Only All-Call
Additional content and description of the uplink reply formats are described below.
Notes:
1. RL (Reply Length); commands a reply in DF=0 if zero, and a reply in DF=16 if one.
2. AQ (Acquisition Special); identifies UF=0 and 16 as acquisition transmissions and
is repeated as received by the transponder in DF=0 and DF=16.
FIGURE 4-6 UPLINK FORMATS

(Sheet 1 of 3)
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B KT 73
Notes
1. PC (Protocol): contains operating commands to the transponder and is part of the
surveillance and Comm-A interrogations. The codes are:
0 = No changes in transponder state.
1 = Non-selective All-Call lockout.
2 = Not assigned.
3 = Not assigned.
4 = Cancel B. (Closeout Comm-B)
5 = Cancel C. (Closeout Comm-C)
6 = Cancel D. (Closeout Comm-D)
7 = Not assigned.
2. RR (Reply Request): contains length and content of the reply requested by the in-
terrogations.
RR Code Reply Length MB Content
0-15 Short No MB Field
16 Long Air Initiated COMM-B
17 Long Extended Capability
18 Long Flight ID
19 Long TCAS RA Report
20-31 Long Least Significant 4 Bits interpreted as BDS1
3. DI (Designator Identification): identifies the coding contained in the SD field (ex-

plained below). The codes are:
0 = SD contains IIS, bits 21-32 are not assigned.
1 = SD contains multi-site II lockout and multisite datalink proto-
col.
2 = SD contains extended squitter control information.
3 = SD contains multisite SI lockout information and extended
data readout.
4-6 = Not assigned.
7 = SD contains extended data readout request.
(Sheet 2 of 3)
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B KT 73
4. SD (Special Designator): contains control codes affecting transponder protocol.

The content of this field is specified by the DI field (see note 3).
IIS (Interrogator Identifier): 4-bit subfield appears in all SD fields if DI code is 0, 1,
or 7.
5. MA (Message Comm-A): contains messages directed to the aircraft.
Notes
1. PR (probability of Reply): contains commands to the transponder that specify the
reply probability to the Mode S-only All-Call interrogation (UF=11) that contains the
PR. A command to disregard any lockout state can also be given. The assigned
codes are as follows:
0 = Reply with probability = 1.
1 = Reply with probability = 1/2.
5, 6, 7 = Do not reply.
8 = Disregard lockout, reply with probability = 1.
9 = Disregard lockout, reply with probability = 1/2.
13, 14, 15 = Do not reply.
2. IC (Interrogator Code)
3. CL (Code Label)
0 = IC field contains the II code.
1 = IC filed contains SI codes 1 to 15.
5-7 = Not assigned.
(Sheet 3 of 3)
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B KT 73
4.1.3 MODE S TRANSMISSION CONTENT

All discrete Mode S interrogations (56-bit or 112-bit) and replies (except the All-Call reply) contain
the 24-bit discrete address of the Mode S transponder upon which 24 error-detecting parity check
bits are overlaid. In the All-Call reply, the 24 parity check bits are overlaid on the Mode S interro-
gator’s identity code and the transponder’s discrete address included in the text of the reply.
NOTE:
Blocks of Mode S address codes will be allocated to
state aircraft registration authorities by the Interna-
tional Civil Aviation Organization (ICAO). Individual
states will set their own arrangements for code as-
signments, however, it is expected that users will ap-
ply to their state regulatory authorities for the code
assignments for their aircraft.
The primary function of Mode S is surveillance. For the Mode S transponder this function can be
accomplished by the use of "short" (56-bit) replies and interrogations. In the replies, the aircraft
reports its altitude as well as its flight status (airborne, on the ground, alert).
The "squitter" transmission is unsolicited and is transmitted by a transponder approximately once
every second. The squitter signal is observed by aircraft equipped with airborne collision avoid-
ance systems.
Air-to-air interrogations from airborne collision avoidance systems are addressed to Mode S-
equipped aircraft based upon the address extracted from squitter signals. These interrogations
are used for Mode S target tracking and collision threat assessment.
The discrete addressing and digital encoding of Mode S transmissions permit their use as a digital
data link. Certain interrogation and reply formats of the Mode S system contain coding space for
the transmission of data. Such data may be used for air traffic control purposes or air-to air data
interchange for collision avoidance.
Mode S data link transmissions are handled as one 56-bit message included as part of "long" 112-
bit interrogations or replies. These transmissions include the message, in addition to surveillance
data.
4.1.4 REPLY FORMATS
A. ATCRBS Replies
The ATCRBS reply format is illustrated in Figure 4-7. The KT 73 uses 13 serial
pulses to convey aircraft identification in response to Mode A interrogations or air-
craft altitude reporting in response to Mode C interrogations. The coded pulses are
arranged between two framing pulses located at the beginning and end of the data.
The framing pulses, identified as F1 and F2 are spaced 20.3 microseconds apart
for both Mode A and Mode C replies. The transponder receives the aircraft code
from switch settings on the control panel and altitude data from sensors in the air-
craft.
When no altitude data is available during Mode C interrogations, the transponder
replies with only F1 and F2 framing pulses. The framing pulses are transmitted
even if the altitude reporting switches on the control panel are turned off.
In addition to information pulses and framing pulses, a Special Position Identifica-
tion (SPI) pulse may be included in the reply when requested by the radar control-
ler. The pulse is initiated when the IDENT pushbutton switch is pushed at the con-
trol panel.
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B KT 73
The SPI pulse follows the last framing pulse by 4.35 microseconds and is transmit-
ted with each response that occurs during the 15- to 30- second period after the
IDENT switch is actuated. The SPI pulse causes an enhanced pattern on the air
traffic controller’s scope thus enabling more positive aircraft identification.
B. Mode S Replies
The Mode S reply is a PPM scheme, much like that used with ATCRBS. The exact
format differs, however, in that a four (4) pulse preamble is followed by the reply
data pulses. See figure 4-7. The reply data pulses are either 56 pulses (bits) if the
reply is short format or 112 pulses (bits) if the reply is long format.
In PPM coding of the reply, 0.5mSec pulses are placed within 1.0 mSec windows
of time relative to the preamble. If the positive pulse lies within the first half of the
1 mSec window, the bit is understood to be a "1". If the positive pulse lies within
the last half of the window, the bit is understood to be a "0". The downlink reply
provides for 25 format possibilities. The 25 Mode S transponder transmission
downlink formats DF=0 through DF=24 are defined in RTCA/DO-181 and DO-
181C. The term DF=4 means downlink format 4.
The short reply format (56-bit) is used exclusively for the purpose of surveillance,
squitter, and TCAS acquisition.
The long format Mode S interrogations and replies are 112 bits of data within P6.
The long format interrogations provide the same surveillance data as their short
format counterparts but include provisions for 56 bits of non-surveillance type mes-
sages.
FIGURE 4-7 ATCRBS AND MODE S REPLY FORMAT
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B KT 73
Only nine downlink formats (DF=0, 4, 5, 11, 16, 17, 18, 20, 21) are defined and pro-
cessed by the KT 73 transponder. Refer to figure 4-8 for a description of these for-
mats.
The first field (D # ) in all downlink formats is the format number. It is coded in bi-
nary form e.g., the first five bits of DF=20 are 10100.
The last 24 bits (AP) of each downlink format except DF=11 (33 thru 56, short or
89 thru 112, long) or DF=17/18, represents the unique 24-bit Mode S transponder
address plus parity bits overlaid on the address.
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DOWNLINK BINARY DATA FIELDS AND

FORMAT FORMAT NUMBER OF BITS FUNCTION
NUMBER D #
0 0 0000 VS:1 CC:1 P:1 SL:3 P:2 RI:4 P:2 AC:13 Short Air-Air Surveil-
AP:24 lance (ACAS)
4 0 0100 FS:3 DR:5 UM:6 AC:13 AP:24 Surveillance, Altitude
5 0 0101 FS:3 DR:5 UM:6 ID:13 AP:24 Surveillance, Identity
11 0 1011 CA:3 AA:24 PI:24 All-Call Reply
16 1 0000 VS:1 P:2 SL:3 P:2 RI:4 P:2 AC:13 MV:56 Long Air-Air Surveillance
AP:24
17 1 0001 CA:3 AA:24 ME:56 PI:24 Extended Squitter
18 1 0010 CA:3 AA:24 ME:56 PI:24 Extended Squitter (Non-
Transponder)
20 1 0100 FS:3 DR:5 UM:6 AC:13 MB:56 AP:24 Comm-B, Altitude
21 1 0101 FS:3 DR:5 UM:6 ID:13 MB:56 AP:24 Comm-B, Identity
NOTE: Downlink format 16 is required only with TCAS operation.
Additional content and description of the downlink reply formats are described below.
Notes
1. VS (Vertical Status):
0 = airborne, 1 = on the ground
2. CC (Crosslink Capability) DF=0 only
0 = not supported, 1 = supported
3. SL (Sensitivity Level): TCAS operating levels that determine the area of protected
volume around a TCAS-equipped aircraft. See DO-185 for additional information.
The coding is as follows:
0 = No TCAS sensitivity level reported.
1 = TCAS is operating at sensitivity level 1.
FIGURE 4-8 DOWNLINK FORMATS
(Sheet 1 of 6)
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B KT 73
4. RI (Reply Information): reports airspeed capability and type of reply to the interro-
gating aircraft. The coding is as follows:
0-7 = Codes indicate that this is the reply to an air-to-air non-acquisition interro-
gation.
0 = No on-board TCAS.
8-15 = Codes indicate that this is an acquisition reply.
8 = No maximum airspeed data available.
9 = Airspeed is less than or equal to 75 knots.
10 = Airspeed is greater than 75 and less than 150 knots.
14 = Airspeed is greater than 1200 knots.
15 = Not assigned.
5. AC (Altitude Code): contains altitude code. Zero is transmitted in each of the 13
bits if altitude information is not available. Metric altitude is contained in this field if
bit 26 is set to "1".
6. MV (Message, Comm-V): contains information used in air-to-ground exchanges.

(Sheet 2 of 6)
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B KT 73
Notes:
1. FS (Flight Status): reports the flight status of the aircraft. The codes are:
Code Alert SPI Airborne On the Ground
0 no no yes no
1 no no no yes
2 yes no yes no
3 yes no no yes
4 yes yes either
5 no yes either
6,7 not assigned
2. DR (Downlink Request): used to request extraction of downlink messages from

transponder by the interrogator. The codes are:
0 = No downlink request.
1 = Request to send Comm-B message (B bit set).
2 = TCAS information available.
3 = TCAS information available and request to send Comm-B message.
4 = Comm-B broadcast #1 available.
5 = Comm-B broadcast #2 available.
6 = TCAS information available and Comm-B broadcast #1 available.
7 = TCAS information available and Comm-B broadcast #2 available.
(Sheet 3 of 6)
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B KT 73
2. DR (Downlink Request continued):

8 to 15 = not assigned.
16 to 31 = future use.
3. UM (Utility Message): contains transponder status readouts.
4. AC (Altitude Code): contains altitude code. Zero is transmitted in each of the 13
bits if altitude information is not available. Metric altitude is contained in this field if
bit 26 is set to 1.
5. MB (Message Comm-B): contains messages to be transmitted to the interrogator
and is part of Comm-B replies DF=20 and 21.
BDS (Comm-B Definition Subfield): contained within MB. Defines the content of
the MB message field of which it is a part.
6. ID (Identification): contains the 4096 identification code reporting the number set
on the front panel.

(Sheet 4 of 6)
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B KT 73
Notes
1. CA (Transponder Capability): reports transponder capability. Codes are:
0 = Signifies no communication capability (surveillance only),
no ability to set CA code 7, either on the ground or
airborne
1, 2, or 3 = Not used
4= Signifies at least Comm-A and Comm-B capability
ability to set CA code 7, on the ground.
ability to set CA code 7, airborne.
6= Comm-A and Comm-B capable, can set CA=7, either
on ground or airborne.
7= DR is not equal to zero or FS = 2,3,4,5, either on ground
or airborne.
2. AA (Address, Announced): contains the aircraft address.
3. PI (Parity/Interrogator Identity): contains the parity overlaid on the interrogator’s
identity code.

(Sheet 5 of 6)
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B KT 73
Notes
1. CA (Transponder Capability): reports transponder capability. Codes are:
0 = Signifies no communication capability (surveillance only),
no ability to set CA code 7, either on the ground or
airborne
1, 2, or 3 = Not used
ability to set CA code 7, on the ground.
ability to set CA code 7, airborne.
6= Comm-A and Comm-B capable, can set CA=7, either
on ground or airborne.
7= DR is not equal to zero or FS = 2,3,4,5, either on ground
or airborne.
2. AA (Address, Announced): contains the aircraft address.
3. ME (Extended Squitter Message)
4. PI (Parity/Interrogator Identity): contains the parity overlaid on the interrogator’s
identity code.

(Sheet 6 of 6)
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4.1.5 KT 73 REPLY PULSE CHARACTERISTICS

ATCRBS Replies:
ATCRBS Reply Pulse Positions:

The reply function will consist of two framing pulses (nominally spaced 20.3 µsec apart) and 13
information pulses. The pulse spacing tolerance for each pulse (including the last framing pulse)
with respect to the first framing pulse of the reply group will be ±.10 µsec. The pulse spacing tol-
erance of any pulse in the reply group with respect to any other pulse (except the first framing
pulse) will be no more than ±.15 µsec.
Pulse position from the first framing pulse are as follows:
PULSE POSITION (µsec)
F1 ...................0.00 (Reference)
C1 ...................1.45
A1 ...................2.90
C2 ...................4.35
A2 ...................5.80
C4 ...................7.25
A4 ...................8.70
B1 ...................11.60
D1 ...................13.05
B2 ...................14.50
D2 ...................15.95
B4 ...................17.40
D4 ...................18.85
F2 ................... 20.30
SPI .................. 24.65
ATCRBS-SPI Reply Pulse:

Upon activation of the IDENT switch, the SPI pulse will be transmitted when replying to ATCRBS
Mode A interrogations for a period of 18 ±1 seconds. The pulse spacing tolerance of the SPI pulse
with respect to the last framing pulse will be ±0.10 µsec. The SPI pulse will not be transmitted
when replying to Mode C interrogations.
ATCRBS Reply Pulse Shape:

NOTE:
All reply pulses and SPI pulses will be 0.45 µsec
±.10 µsec duration and have rise times of 0.05 µsec
through 0.1 µsec and decay times of 0.05 µsec
through 0.2 µsec.
The Mode S reply spectrum requirement is an acceptable specification for meeting ATCRBS min-
imum rise and fall time requirement.
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B KT 73
ATCRBS Reply Delay and Jitter:

A. At all RF input levels from MTL to -21 dBm, the time delay from the leading edge
of P3 to the leading edge of F1 (the first pulse of the reply) will be 3.0 ±.5 µsec.
B. At all RF levels from MTL +3 to -21 dBm the time delay variations between AT-
CRBS modes will not exceed 0.2 µsec.
C. At all RF input levels from MTL +3 to -21 dBm the jitter at the leading edge of the
first pulse of the reply with respect to P3 will not exceed ±0.10 µsec.
Mode S Replies:
The reply data block is formed by PPM encoding of the reply data. A pulse transmitted in the first
half of the interval represents a ONE while a pulse transmitted in the second half represents a ZE-
RO. An example of a Mode S reply waveform is shown in Figure 2-3, paragraph 2.2.4.2, of DO-
181C.
Mode S Preamble:
The preamble will consist of four 0.5, ±.05 µsec pulses. The second, third, and fourth pulses will
be spaced 1.0, 3.5, and 4.5 µsec, respectively, from the first transmitted pulse. The spacing toler-
ance of the second, third, and fourth pulse with respect to the first pulse will be ±0.05 µsec.
Mode S Reply Pulse Width:

The block of reply data pulses will begin 8.0 µsec after the first transmitted pulse. A pulse width
of 0.5 µsec ±0.05 µsec will be transmitted either in the first or in the second half of each interval.
If a pulse in the second half of one interval is followed by another pulse transmitted in the first half
of the next interval, the two pulses will merge and a 1.0 µsec ±0.05 µsec pulse will be transmitted.
Mode S Reply Pulse Shape:

A. The pulse rise time will not exceed 0.1 µsec.
B. The pulse decay time will not exceed 0.2 µsec.
C. The pulse amplitude variation between one pulse and any other pulse in a reply
shall not exceed 2 dB.
Transmitter Spectrum:
The spectrum of a Mode S reply will not exceed the following bounds:
Frequency Difference Maximum Relative Response

(MHz From Carrier) (dB Down From Peak)
Greater than 1.3 and less than 7 3
Greater than 7 and less than 23 20
Greater than 23 and less than 78 40
Greater than 78 60
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B KT 73
Mode S Reply Delay and Jitter:

A. At all RF input levels from MTL to -21 dBm the first preamble pulse of the reply will
occur 128 µsec ±0.25 µsec after the sync phase reversal of the Mode S interroga-
tion.
B. At all RF input levels from MTL to -2 1dBm the jitter of the reply delay will not ex-
ceed ±0.08 µsec.
4.1.6 KT 73 ATCRBS/MODE S ALL-CALL REPLIES

ATCRBS/Mode S All-Call Reply Delay and Jitter:
A. At all RF input levels from MTL to -21 dBm the first preamble pulse of the reply will
occur 128 µsec ±0.5 µsec after the P4 pulse of the ATCRBS/Mode S All-Call inter-
rogation.
B. At all RF input levels from MTL+3 dB to -21dBm the jitter of the reply delay will not
exceed ±0.1µsec, peak.
Suppression I/O:
This pin is both an input and an output. The transponder will be suppressed if the input is +18 V
dc to +70 V dc. While the transponder is transmitting it will drive this pin above 18 V dc. (See
ARINC 718A Attachment 6).
Suppression In:
The transponder will be suppressed if the voltage applied to this pin is +5V dc to +9V dc. If the
voltage is <3.5V dc, the transponder will not be suppressed. This follows a Honeywell standard.
Side Lobe Suppression Characteristics:
Side lobe suppression is accomplished separately for ATCRBS, ATCRBS-Only All-Call, ATCRBS/
Mode S All-Call and for Mode S interrogations.
4.1.7 KT 73 ATCRBS, ATCRBS-ONLY ALL-CALL AND ATCRBS/MODE S ALL-CALL
SLS Decoding and Dynamic Range:

A. The transponder will reply to no more than 10% of the interrogations when the RF
input signal is varied from +3 dB above the MTL to -21 dBM and the level of P2
equals or exceeds the level of P1 and the pulse interval between P1 and P2 is var-
ied over the range from 1.85 to 2.15 µsec.
B. The transponder will reply to at least 90% of the interrogations when the RF input
signal is varied from +3 dB above the MTL to -21 dBM and the level of P1 exceeds
the level of P2 by 9 dB or more and that no pulse is received at the position 2 ±0.7
µsec following P1.
P2 Duration For 90% Replies:

The transponder will reply to at least 90% of the interrogations when the duration of P2 is less than
0.3 µsec. This is applicable for signal levels from MTL +3 dB thru -21 dBm.
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B KT 73
Mode S Side Lobe Suppression:

Side lobe suppression for Mode S formats is characterized by the reception of P5, overlaying the
location of the sync phase reversal of P6.
A. At all RF input levels from MTL +3 dB to -21 dBm the reply ratio will be less than
10% if the received amplitude of P5 exceeds the received amplitude of P6 by 3 dB
or more.
B. At all RF input levels from MTL +3 dB to -21 dBm the reply ratio will be at least 99%
if the received amplitude of P6 exceeds the received amplitude of P5 by 12 dB or
more.
Pulse Decoder Characteristics:

Unless otherwise specified, the following pulse decoder characteristics will apply for an RF input
signal levels of MTL +1 dB to -21 dBm and nominal interrogation signal characteristics. Applicable
"valid" interrogations will result in at least 90% replies, and interrogations which are "invalid" will
result in less than 10% replies.
Pulse Level Tolerances:
A. The transponder will accept an ATCRBS/Mode S All-Call as a valid Mode S if the
received amplitude of P4 is above the amplitude of P3 -1 dB.
B. The transponder will not accept the interrogation of an ATCRBS-Only All-Call if the
received amplitude of P4 is above the amplitude of P3 -1 dB.
C. The transponder will accept an ATCRBS/Mode S All-Call as a valid ATCRBS inter-
rogation if the received amplitude of P4 is below the amplitude of P3 -6 dB.
D. The transponder will accept an ATCRBS-Only All-Call as a valid ATCRBS interro-
gation if the received amplitude of P4 is below the amplitude of P3 -6 dB.
NOTE:
Mode S transponders do not accept the ATCRBS-
Only All-Call.
Pulse Position Tolerances:

A. The transponder will accept the pulse position of ATCRBS interrogations as valid
if the spacing between P1 and P3 is within ±0.2 µsec of the nominal spacing.
B. The transponder will accept the pulse position of ATCRBS/Mode S All-Call’s as val-
id if the spacing between P1 and P3 is within ±0.2 µsec of the nominal spacing and
if the spacing between P3 and P4 is within ±0.05 µsec of nominal.
C. The transponder will not accept the pulse position of ATCRBS, ATCRBS-Only All-
Call’s or ATCRBS/Mode S All-Call’s as valid if the spacing between P1 and P3 dif-
fers from the nominal spacing by 1.0 µsec or more.
D. The transponder will not accept the pulse position of ATCRBS/Mode S All-Call’s if
the leading edge of P4 is not detected within the interval from 1.7 to 2.3 µsec fol-
lowing the leading edge of P3.
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B KT 73
Pulse Duration Tolerances:

A. The transponder will accept the pulses of an ATCRBS interrogation as valid if the
duration of both P1 and P3 is between 0.7 and 0.9 µsec.
B. The transponder will accept an ATCRBS/Mode S All-Call interrogation as valid if
the duration of both P1 and P3 is between 0.7 and 0.9 µsec and if the duration of
P4 is between 1.5 and 1.7 µsec.
C. The transponder will not accept an ATCRBS/Mode S All-Call as valid if the duration
of the P4 pulse is outside of the range between 1.2 and 2.5 µsec.
D. The transponder will accept no more than 10% of ATCRBS or ATCRBS/Mode S
All-Call interrogations as valid if the duration of either the P1 pulse or the P3 pulse
is less than 0.3 µsec, for all signal levels from MTL to -45 dBm.
Simultaneous Interrogation of Mode A and Mode C:

When the transponder receives two valid ATCRBS pulse patterns simultaneously, the transpon-
der will enter the ATCRBS suppression state if one of the received pulse patterns is a P1-P2 sup-
pression pair, or generate a valid Mode C reply if the two received pulse patterns are Mode A and
Mode C.
Sync Phase Reversal Position Tolerance:

Valid SPR Position: At signal levels of MTL +1 dB thru -21 dBm the transponder will accept the
sync phase reversal, of a standard Mode S-Only All-Call, if it is received within the interval from
1.2 to 1.3 µsec following the leading edge of P6.
Invalid SPR Position: At signal levels of MTL +1 dB thru -21 dBm the transponder will not accept
the sync phase reversal, of a Mode S-Only All-Call, if it is received outside of the interval from 1.05
to 1.45 µsec following the leading edge of P6.
NOTE:
In the gray zones, in the zones from 1.05 to 1.2 µsec
and from 1.3 to 1.45 µsec, the transponder may or
may not accept the sync phase reversal.
Squitter: Random Intervals Uniformly Distributed over the range from .8 thru 1.2 seconds, full self
verification of every squitter’s data and occurrence.
4.1.8 TRAFFIC INFORMATION SERVICE DATA LINK

The Traffic Information Service (TIS) data link function is intended to improve the safety and effi-
ciency of “see and avoid” flight by providing automatic display to the pilot of nearby traffic and
warnings of any potentially threatening conditions. The source of TIS information is the file of air-
craft tracks maintained by the ground Mode S sensor providing coverage for a region of airspace.
While TIS can provide traffic information alerts to only those Mode S equipped aircraft under sur-
veillance track, TIS has knowledge of all ATCRBS aircraft in coverage (and, potentially, of non-
transponder-equipped aircraft when a primary radar’s coverage is integrated with the Mode S sen-
sor). TIS generates alerts for any traffic aircraft in Mode S coverage that carry a transponder (AT-
CRBS or Mode S). TIS provides traffic advisories similar to those of TCAS-I but does not provide
resolution advisories. By utilizing the surveillance database maintained by Mode S ground inter-
rogators and the data link, TIS can provide airborne traffic alerting with modest airborne equipage.
The TIS service is provided without ground controller involvement.
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B KT 73
4.1.8.1 Differences between TIS and TCAS

The major functional difference between TIS and TCAS is the source of surveillance data. TCAS
uses an airborne interrogator with a one second update rate. TIS, on the other hand, uses the
terminal Mode S ground interrogator and its data link to provide about a five second update rate.
The range accuracy of TIS and TCAS are similar. TCAS angular accuracy is limited to a few de-
grees of azimuth measured with respect to the aircraft while TIS angular accuracy is that of Mode
S (about 1 milliradian) measured with respect to the ground interrogator. These differences in sur-
veillance accuracy, coordinate system, and update rate impact the design of TIS. The algorithms
and parameters of TIS have been developed to offset the differences in surveillance performance
in order to yield equivalent alerting service to TCAS-I. TCAS practice may also be used in the
design of TIS display symbology.
4.1.9 DEFINITION OF AUTOMATIC DEPENDENT SURVEILLANCE - BROADCAST
ADS-B is a system for aircraft or surface vehicles operating within the airport surface movement
area that periodically transmits its state vector (horizontal and vertical position, horizontal and ver-
tical velocity) and other information. ADS-B is automatic as no external stimulus is required. It is
dependent as it relies on on-board navigation sources and on-board broadcast transmission sys-
tems to provide surveillance information to other users. The aircraft or vehicle originating the
broadcast may or may not have knowledge of which users are receiving its broadcast. Any user,
either aircraft or ground based within the range of this broadcast, may choose to receive and pro-
cess the ADS-B surveillance information. ADS-B supports the improved use of airspace, reduced
ceiling/visibility restrictions, improved surface surveillance, and enhanced safety such as conflict
management.
Figure 4-9 shows the extent of the 1090 MHz ADS-B system and its major components. As indi-
cated in the figure, the ADS-B system includes the following components: message generation/
transmission by the source A/V, propagation medium, and message reception/report assembling
by the user. The ADS-B system does not include the sources of the data to be sent by the source
subsystem on board the transmitting aircraft. Neither does it include the client applications, which
use the information received by the ADS-B user subsystem on board the receiving aircraft. Some
ADS-B participants may be able to transmit by not receive. In addition, some ground based users
may be able to receive but not to transmit.
FIGURE 4-9 1090 MHZ ADS-B SYSTEM
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B KT 73
FIGURE 4-10 KT 73 BLOCK DIAGRAM
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B KT 73
FIGURE 4-11 KT 73 INTERNAL INTERCONNECTION DIAGRAM
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B KT 73
4.2 GENERAL CIRCUIT THEORY

Refer to Figure 4-10 for a block diagram and Figure 4-11 for an internal interconnect diagram.
The older ATCRBS interrogation signals, Mode A and Mode C, are a combination of pulse ampli-
tude modulated (PAM) and pulse position modulated (PPM) type of signals. The new Mode S in-
terrogation signals are a combination of PAM, PPM, and differential phase shift keying (DPSK)
type of signals. Interrogation signals at 1030 MHz are coupled into the unit via the antenna con-
nector. The signal passes through a 1300 MHz low pass filter and is routed through a 1030 MHz
bandpass filter. After passing through the bandpass filter signal is mixed with a 970 MHz local
oscillator (LO) signal to generate an intermediate frequency (IF) signal at 60 MHz. The output
from the mixer is processed by a bandpass filter to reject undesired mixing frequencies. The de-
sired IF signal is amplified logarithmically, then demodulated by the video processor and DPSK
module to obtain the PAM/PPM and DPSK base-band interrogation pulses. The demodulated sig-
nals are then routed into the FPGA (Field Programmable Gate Array) for further processing. The
operation of KT 73 can be better understood if it is broken into blocks as shown in Figure 4-10.
A brief description of each block is presented. Detailed circuit theory information is presented in
Section 4.3.
The KT 73 has an AMD 80C186, 16 bit Micro-controller that controls the FPGA and performs sev-
eral other functions:
• Reads the front panel rotary switches and pushbutton selections.
• Generates appropriate characters for the front panel display and controls the display bright-
ness.
• Programs and reads the internal and external (if installed) EEPROM.
• Reads the Gillham code lines, EXT STBY_NOT, EXT IDT_NOT, EXT GND_NOT, and AUDIO
INHB_NOT through a parallel to serial converter.
• Checks operational status of unit by monitoring the TX_SENSE line from the transmitter power
amplifier.
• For ATCRBS interrogations, the FPGA validates the video signal and generates the appropri-
ate reply (MOD_TRIG) signal.
• For Mode S interrogations, the FPGA validates the video signal and transfers the received
data to the AMD 80C186 Micro-controller.
The AMD 80C186 will decipher the data and send the appropriate reply data back to the FPGA.
On receipt of data, the FPGA generates proper MOD_TRIG signal. The MOD_TRIG signal from
the FPGA is used by the modulator to generate the appropriate drive signals to turn on/off the pow-
er oscillator and power amplifier. The power oscillator outputs 100W typical at 1090 MHz every
time it is turned on by the modulator. This pulsed RF output is further amplified by the power am-
plifier to 300W. The amplified output goes through the transmit/receive switch, low pass filter and
is coupled out to the antenna. The input power to the KT 73 can vary from 11 to 33Vdc. The power
supply converts the dc-input voltage into the following fixed voltages: +3.3V, +5V, +65V, ±12V,
±95V and +6V that are needed by the circuitry in the KT 73.
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B KT 73
4.3 DETAILED CIRCUIT THEORY

4.3.1 RECEIVER BOARD
The receiver of the KT73 consists of a 1030 MHz bandpass filter, low noise amplifier (LNA), local
oscillator (LO), Mixer, 60 MHz IF bandpass filter & amplifier, log amplifier/detector, 60 MHz phase
reference, and phase detector. The reference schematic is 002-08273-0020. A block diagram is
shown in figure 4-12.
FIGURE 4-12 RECEIVER BOARD BLOCK DIAGRAM
4.3.1.1 Receiver Front End

The receiver front end consists of a ceramic bandpass filter and low noise amplifier. The ceramic
bandpass filter, FL1, which has a center frequency of 1030 MHz and a bandwidth of 30 MHz, pro-
cesses the input RF signal. The signal is amplified by Q7, a low noise amplifier (LNA). Q6 pro-
vides a regulated bias for the LNA.
4.3.1.2 Local Oscillator (LO)
The local oscillator (LO) consists of several stages. A crystal oscillator (Q1, Y1, and etc.) gener-
ates a fundamental frequency of 161.667 MHz. This signal is multiplied by three (Q2), amplified
by Q3, and multiplied by 2 (Q4), to obtain a LO frequency of 970 MHz. A microstrip bandpass
filter (Z16, C18, C19, and Z17) is used to select out the desired 970 MHz LO signal. The LO signal
is buffered and amplified by Q5 before injection into the mixer.
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B KT 73
4.3.1.3 Amplified Input Signal

The amplified input signal is multiplied with the LO signal by the Q8 mixer, a low noise dual gate
MOSFET, to obtain the 60 MHz difference frequency used in the IF. Bias adjustment for the input
and LO injection to the mixer is provided by R2156 and R2157 respectively.
4.3.1.4 IF Filter and Amplifier
The IF filter and amplifier then process the signal. A network with T1 and T2, which extracts the
60MHz IF, filters the signal from the mixer output. The IF is subsequently amplified by Q9 and
further processed by a bandpass filter consisting of T3, T4, and T5. Before proceeding to the Log
Amp, the IF is filtered and balanced through T8 and C188. The signal enters the T8 primary, is
coupled to its center tapped secondary, and is shunted to ground through C188 . Each secondary
output feeds one of the balanced inputs to the U1 Log Amp.
4.3.1.5 Log Amp
The U1 Log Amp takes the 60 MHz balanced IF input signal and converts it from a logarithmic
scaling to linear. It is then detected, producing video for both the video and DPSK signal require-
ments on the Main Board. The Log Amp provides a log linear output from -65dBm to 0dBm at its
input. With gain of the LNA, insertion loss from filtering, and conversion gain of the mixer and IF
amplification, an input signal from the RF input has a down converted gain of 18 dB. A -74 dBm
input signal would produce a -56 dBm IF at the input to the Log Amp, which is easily within the
range of linear Log Amp output. Two Log Amp outputs are used to provide video and DPSK sig-
nals.
U1 outputs a video signal with a gain of 20 mV/dB. U4, a video amplifier, inverts and has a voltage
gain of unity. The output passes to a buffer consisting of Q15, Q16, Q19, and Q20. The buffer
inverts the video signal and boosts the gain to 60 mV/dB. The buffer is configured to provide a
DC level near ground for the video signal. The output is passed to the main board through TP6.
A limited IF output of 60 MHz is amplified by U2 and U3 and then split into two paths for DPSK
signal processing.
4.3.1.6 60 MHz Phase Reference
The 60 MHz Phase Reference is created by first generating a 120 MHz signal using a non-linear
amplifying process. Q13 is a tuned 120 MHz amplifier that selectively amplifies this second har-
monic. The 120 MHz output is processed by a high Q bandpass filter (C101-C104, L24, L25) and
amplified by Q14 to obtain a constant phase 120 MHz signal. The 120 MHz signal is divided by
two creating a constant phase 60 MHz reference. This “division by two” process is done by the
feedback arrangement of mixer U12 and Q21, a 60 MHz tuned amplifier. Capacitor C151 provides
phase adjustment of the 60 MHz reference.
4.3.1.7 Active Phase Detector
The active phase detector, U14, receives the 60 MHz phase reference together with Limited IF
from U3 to extract the DPSK data from the Limited IF signal. The positive/negative pulses of I14,
corresponding to DPSK transitions, are low pass filtered and level translated by U15 to TTL signal
level. This TTL level signal is the demodulated DPSK signal that goes to the RLSI for further pro-
cessing.
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4.3.2 MODULATOR BOARD

The modulator board drives the transmitter according to the signals received from the RLSI chip
on the main board. The KT 73 modulator can be divided into the five major blocks: TX_SENSE
module, 50V regulator, collector modulator, emitter modulator, and TX/RX switch as shown in fig-
ure 4-13. The modulator schematic is P/N 002-08274-0020.
FIGURE 4-13 MODULATOR BOARD BLOCK DIAGRAM
4.3.2.1 TX_SENSE Module

The TX_SENSE circuit detects the transmitted pulse, converts it to TTL format, and sends it to the
RLSI. The detected signal is used to verify that the squitter function is working. The detection
circuit consists of a detector diode CR2, resistor R5, and capacitor C18 on the transmitter board.
The detected RF is sent to the modulator board via E4 and is then buffered by Q12 on the modu-
lator board. U1, whose output is TTL compatible, then inverts the TX_SENSE.
4.3.2.2 50 V Regulator
The 50 V regulator takes the 65 V from the power supply and regulates it to 50 +/- 1.5 VDC. The
circuit uses two power transistors, Q2 and Q3 (both Darlington), on the modulator board and a
voltage divider network that supplies the base drive to the two Darlington transistors. The regula-
tor consists of Q1, CR3, R4, R5, R34, and R6 on the modulator board. In a steady state, when
the 65 V line is at 65 V, the regulator keeps the bases of the Q2 and Q3 Darlington at 50 VDC. As
the voltage on the 65 V line drops, the base voltage for Q3 drops, reducing the collector current
of Q3 and raising the base currents on the darlingtons. As the 65 V line drops, the voltage drop
through the darlingtons is decreased, and the collector voltages for the RF transistors stay at 50
VDC.
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B KT 73
4.3.2.3 Collector Modulator

The collector modulator is used to increase the fall time of the RF output pulse. The final RF am-
plifier is powered by a series of 50 V collector voltage pulses that correspond to MOD_TRIG puls-
es. The collector voltage starts with the rising edge of each MOD_TRIG pulse and ends when the
gate of Q10 discharges to below its threshold level. MOD_TRIG is inverted by I1 and fed to Q11
through C24. I1 also provides isolation between MOD_TRIG and the 65 V line. Transistor Q11
is a medium power p-channel FET that drives the high current driver Q10, IRF540. Integrated cir-
cuit I1 pulls one end of C24 from 12 V to ground, causing a 12 V drop in the gate to source voltage
of Q11. The threshold voltage, VGS of Q11, is negative 2-4 volts, so the falling edge on the 12 V
pulse drives Q11 into saturation. The result is a 65 pulse on R28 and R26 that turns on Q10 which,
in turn, delivers a 50 V pulse to the collector of the final amplifier. R28 and the capacitance of Q10,
from gate to source, control the rate at which the gate voltage of Q10 is discharged, effectively
slowing down the fall time of the 50 volt pulse that appears on the collector of the final amplifier.
4.3.2.4 Emitter Modulator
The emitter modulator is a circuit that turns on the power oscillator during the interval that the
MOD_TRIG is high. When running the emitter modulator unloaded, the output is a negative 12 V
pulse that occurs while MOD_TRIG is high. As in the collector modulator, I1 inverts the
MOD_TRIG pulse and drives Q4 with a negative going pulse. Q4 is a small signal p-channel FET
which saturates whenever MOD_TRIG is high. This results in a positive going pulse which turns
on Q6, a high current driver for the power oscillator. Transistor Q5 provides an active turnoff for
Q6. This “turnoff” operation works as follows:
When Q4 and Q6 are turned on, the gate and the source of Q5 are essentially at the same voltage.
Since Q5 is a p-channel FET, it is off when Q4 and Q6 are turned on. When the MOD_TRIG pulse
goes low, the VGS for Q4 becomes zero volts and Q4 turns off. Simultaneously, VG for Q5 goes
to -12 volts, but VS remains at +12 volts as CR2 is reverse biased and a charge is stored in C10.
Therefore, VGS for Q5, at the end the MOD_TRIG pulse, turns on Q5 very hard. The charge on
the gate of Q6 is the returned through Q5 and R11 to the -12 V supply. R11 is an adjustable re-
sistor that varies the discharge rate of Q5, which is used primarily for the RF output pulse width.
Q5 stays on until it VGS is less than two volts and CR5 prevents the gate of Q3006 from going
below -12 volts.
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B KT 73
4.3.3 POWER SUPPLY BOARD

The KT 73 power supply is a dc to dc converter delivering 29 W to meet the energy requirements
for the rest of the unit. Typical conversion efficiency is close to 70%. The design is based on a
discontinuous inductor current mode of a flyback (or buck-boost) configuration. The control meth-
od used is the fixed frequency, varying pulse width, current mode control. Input voltage to the con-
verter can range from 11 Vdc to 33 Vdc. The output voltages are +3.3 V, +5 V, +6 V, ±12 V, +65
V, ± 95V. Reference schematic is P/N 002-09862-0000.
4.3.3.1 General
A block diagram of the KT 73 Power Supply is shown in Figure 4-14. There are six major blocks:
input filter, input regulator, oscillator, switcher #1, switcher #2 and RESET. Two switchers with
their own controllers are used to separate output voltage lines with widely changing loads from
those with constant loads.
Input power is filtered and routed to the input regulator and both switchers. Control of both switch-
ers is accomplished using Unitrode's UC2843D PWM Current Mode Controller in each switcher.
The input regulator output is about +12 V and is used to power up both controllers. Start up and
shut down of the converter is achieved by turning on and off the input regulator +12 V.
The oscillator outputs a pulse train at a frequency of 80 kHz with a 50% duty cycle. The output is
buffered/inverted and is used as a clock signal to drive the controller in switcher #2. This clock
signal is inverted/buffered (now it has same phase as oscillator output) and is used to drive the
controller in switcher #1. The controller output is active only during the LOW state of the incoming
clock signal. This arrangement enables the two switchers to be alternately operational, each with
a maximum output duty cycle of 50%.
The RESET output is a logical OR of two conditions: goes LOW when the +6 V line is above 5.9
V and the UC2843D power input is above +9.1 V, goes HIGH if either the +6 V line drops below
+5.6 V or UC2843D power input is below +8.3 V. This output is inverted on the KT 73 Main Board
and is used to reset the Micro Processor on power up and whenever there is a possibility of an
invalid +3.3 V for the micro controller.
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B KT 73
FIGURE 4-14 POWER SUPPLY BLOCK DIAGRAM
4.3.3.2 Input Filter

Capacitor C52, C59, L8, C61, C51, form a EMI Filter. Coil L1, C50, C60, C1, L2, C12, C49, C53,
C54, C25, C26, forms an input pi filter with a first roll-off around 100 Hz and a second roll-off
around 900 Hz. This filter has a dual function; one is to reduce the effects of high frequency noise
on the input voltage line that may affect the switching controller; the other is to smooth out the
current ramps demanded by the switchers so that the input current is essentially dc. The bulk of
the instantaneous current ramp is delivered by the charge stored by the capacitors in the second
stage of the input filter. In particular, C12 feeds switcher #1 while C25 and C26 feed switcher #2.
Diode CR1 is a transient surge absorber that protects the converter from transient high voltage
spikes that may appear on the input line.
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B KT 73
4.3.3.3 Input Regulator

The on/off control signal from the unit mode selector switch is latched by Q4. This is to overcome
possible contact bounce from the switch which may erroneously turn the regulator on and off dur-
ing switching transients. The input voltage is series-pass regulated by Q1 to about +12 V. Control
of Q1 base drive is provided by differential pair Q2 and Q3 which compares the regulator output
with a reference voltage. The reference voltage is provided by a +6.8 V zener, CR4. When the
input voltage drops below +13 V, the regulator output drops out of regulation and just follows the
input. CR5 provides protection against possible reverse emitter-base bias of Q2 and Q3.
4.3.3.4 Oscillator
Comparator U2 is configured to work as a pulse oscillator. The output frequency is set to 80 kHz
and is determined by R12 and C5. R9, R10 and R11 are set equal to achieve an output pulse train
of 50% duty cycle. The oscillator output is buffered/inverted by a NAND gate in U9 before driving
the controller in switcher #2. This signal is further inverted by another NAND gate in U3 before
driving the controller in switcher #1.
4.3.3.5 Switcher #1
The switching controller U4 (UC2843D) block diagram is shown in Figure 4-15. Power to the con-
troller is +12 V (nominal) fed from the input regulator. After startup, the under voltage lock out
feature of the controller, will shut down the output stage whenever Vcc is below 8.2 volts.
An on board chip regulator provides a +5 V reference voltage. Timing is provided by the 80 kHz
clock signal input from the external oscillator.
The output drive is enabled only during the LOW state of the clock input and is disabled during
this interval by a reset from the internal flip flop. This reset signal is generated by two conditions.
The first is a comparison of the switcher output voltage with an internal +2.5 V reference by the
error amplifier. The output from the error amplifier then serves as a reference for the current sense
comparator.
A description of the sequence of events during start up is as follows:
On power up, the voltage feedback from the switcher regulated output (+6 V line) is near zero.
The output of the error amplifier will swing up to its limit, raising the threshold of the current sense
limit. Since little or no current is flowing through current sense resistor R24 at power up, no reset
will be generated for this first cycle.
The enabled output drive turns on the switching MOSFET Q6. Current starts to ramp up through
transformer T1 primary winding, building up flux and storing energy in the air gap within the core.
During this interval, the rectifiers CR7, CR8, CR9, and CR16 on the secondary side are reversed
biased. At the end of the cycle, Q6 is turned off and the collapsing flux reverses the secondary
windings polarity. Therefore, CR7, CR8, CR9 and CR16 are now forward biased and conduct.
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B KT 73
FIGURE 4-15 U2843D INTERNAL BLOCK DIAGRAM
The energy stored in T1 is now transferred to the storage capacitors C13, C64, C14, C62, C15,
C16, C20, C63 and their respective loads. The voltage on C14, C62, C15, C16 (regulated line) is
connected to the +3.30 volt regulator (U6), the +5.0 volt regulator (U7), and the anode of CR16.
The cathode of CR16 is fed back to the error amplifier for comparison against the +2.5 V refer-
ence. The outcome of the comparison will determine the limit that the current through T1 can ramp
to in the next ON cycle. This may mean terminating the output driver before the cycle is complet-
ed. The sequence then repeats itself.
Equilibrium will be reached when the voltage on the anode of CR16 maintains its intended value
(+6 V) over several cycles. In this situation, Q6 is turning on long enough during each cycle to
store sufficient energy in T1 to transfer energy to C13, C14, C15, C16, C20, C62, C63, C64 and
their loads when Q6 turns off.
Any changes in load during operation, will be taken care of by the error amplifier comparison,
keeping the output voltage (+6 V) in regulation. This regulation effect is extended to the ± 95 volt
lines through the magnetic coupling in T1.
The +6.0 volt output is filtered by L7 and C17 before leaving the Power Supply Board.
Dummy loads R25, R26, R28, R29 are placed on the ±95 volt lines to counteract the tendency of
them to rise in voltage when lightly loaded.
One advantage of having a current sense loop within the voltage feedback loop is insensitivity of
the switcher to input voltage line changes. This simplifies the compensation needed to close the
control loop.
Frequency compensation for closing the control loop is provided by C7, R16, R17, R19, R18. The
nominal loop bandwidth of switcher #1 is about 5 kHz.
Potentiometer R16 provides fine adjustment of the +6.0 volt output. Components R14 and R15
sets the maximum current peak permissible through R24 to about 8 Amps.
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B KT 73
Transistor Q5 provides compensation for the 2 diode voltage drops inside the controller chip over
temperature.
Soft start, i.e. limiting the in-rush current during start up, is provided by C56 which slowly charges
up on power up through R14. It takes approximately 12 ms after turn on for switcher #1 outputs
to reach steady state values.
4.3.3.6 Switcher #2
The operation and control of switcher #2 is essentially the same as switcher #1. Frequency com-
pensation is provided by C22, R48, R49, and R50. The nominal loop bandwidth of switcher #2 is
about 1 kHz. The current through R54 is limited to about 23 A by R46 and R47.
4.3.3.7 RESET
Comparator U5-A is used to check on two conditions that govern the output state of the RESET
line. The reference voltage used in the comparison (+4 V) is provided by linear regulator U1. The
first comparator in U5-A checks the +6.0 volt line output and is configured as an inverting compar-
ator with hysteresis and trip points set at +5.9 V and +5.6 V.
The second comparator in U5-B checks the power input to the switching controllers and is also
configured as an inverting comparator with hysteresis and trip points at +9.3 V and +8.3 V.
The output of the two comparators are logically ORed by CR11 and drives an emitter follower, Q9.
The RESET signal is taken off from the emitter of Q9 and is used on the KT 73 Main Board to reset
the Microprocessor. As configured, the RESET line will reset the KT 73 during power up.
Diodes CR2 and CR3 are used to feedback +12 V from switcher #2 so that operation down to an
abnormal low of +8 V at the input is possible. Diode CR10 is used to harness the residual energy
of the +12 V output after turn-off to hold the RESET line LOW until the +5 V decays to zero.
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B KT 73
4.3.4 TRANSMITTER BOARD

The transmitter board has three RF devices. The TX/RX switch, the power oscillator, and the pow-
er amplifier. The TX/RX switch routes RF signals received and transmitted through the antenna
by way of the RF input/output port to the receiver and transmitter. Q1 is a power amplifier used
in an oscillator configuration. Q2 is a class C power amplifier providing 6 dB of gain. A block di-
agram of the KT 73 transmitter is shown below in Figure 4-16. Reference schematic for the trans-
mitter is P/N 002-08275-0040.
FIGURE 4-16 TRANSMITTER BOARD BLOCK DIAGRAM
4.3.4.1 Power Oscillator

In order for an amplifier to oscillate, it must have some of its output power fed back to its input at
360 degrees of phase shift. A classic oscillator definition is that an active device must have a loop
gain of one and total phase shift of zero degrees. (360 degrees).
(1) The active device is Q1. The loop includes the output microstrip matching network,
C6, FL1 in series with the entire Q1 output, a 6 dB coupler, the 50 ohm phase match-
ing network (serpentine line), C2, and the input matching network. The transistor
has some un-quantified insertion phase as well.
(2) When the emitter modulator pulls low with the Q1 collector at 50 volts, the circuit be-
gins to oscillate.
(3) The total length of the feedback path determines the frequency of the oscillation.
The reason for the adjustable length 50 ohm line is to compensate for the variance
in insertion phase between different transistors populating the Q1 part inventory.
Even though C3 is used to adjust the frequency when the oscillator is close to 1090
MHz., decreasing the length of the 50 ohm line can raise the frequency higher, while
lengthening the line makes oscillations lower in frequency. Smaller length loops can
be added or removed for smaller frequency change and larger loops will change the
frequency in greater increments.
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B KT 73
4.3.4.2 Bandpass Filter

Bandpass Filter FL1 is centered at 1090 MHz. with a 3 dB bandwidth of 10 MHz. The purpose of
the filter is to keep the oscillator on frequency over temperature. As the temperature varies, so
does the insertion phase through the transistor. This causes a change in oscillation frequency.
Bandpass filter FL1 has a temperature coefficient of 15 PPM/degree. The variable capacitors
change at 10 PPM/degree. The combined effect of the capacitors and the filter keep the frequency
of oscillation within the +/-1 MHz. limits.
4.3.4.3 6 dB Coupler
The 6 dB Coupler, W1, is used to couple 25% of the FL1 RF output energy back to the input of the
Q1 oscillator to maintain oscillations. The oscillator outputs 130 Watts and is filtered by FL1. The
insertion loss of FL1 is 1.45 dB leaving its output at 93 Watts. The coupled output being fed back
is 23 Watts or 17% of the oscillator output. Therefore, the output is reduced 25% to 70 Watts.
Loss in phase matching network is negligible.
4.3.4.4 Zero dB Attenuator
The Zero dB Attenuator follows W1 but is currently shorted across R2, the series member of the
network. Two shunt members, R3 and R4, make this a PI type design. The purpose is to reduce
the output from W1 to the Power Amp to a level not exceeding the 1 dB compression point. At
higher power inputs, the power amplifier becomes saturated and the output pulse shape of the
power amplifier becomes distorted.
4.3.4.5 Power Amplifier
The final amplifier is a class C RF amplifier with a gain of 6 dB. C4 and C7 are variable capacitors
used to tune the matching networks to power transistor Q2. Tuning C7 may also effect the fre-
quency of the power oscillator due to loading of the power oscillator output. With 70 Watts driving
the input, nominal power amp output is 280 Watts with 180 Watts reaching the antenna. 2 dB of
insertion loss is dissipated in the coaxial cable connecting the output port of the unit to the anten-
na.
4.3.4.6 TX/RX Switch
The TX/RX switch works by biasing two surface mount diodes, CR1 and CR2, to route RF signals
from the antenna to the receiver or to the antenna from the transmitter. The RLSI generates the
RX_EN_NOT signal, which controls the TX/RX switch.
(1) During the transmit cycle, the RX_EN_NOT line is set low by the RLSI. Integrated
circuit I1 inverts the signal that turns on Q7 and connects +5 V to E5. Applying +5
V to E5 turns on both CR1 and CR3. A low impedance path is now formed that di-
rects all the energy from the transmitter output to the antenna while isolating the re-
ceiver with a high impedance path. CR3 is in series with the transmitter output.
While forward biased, it passes the output power to the antenna. CR1 is effectively
shunted to RF ground a quarter wave length away at the receiver input. A shorted
quarter wave length stub is effectively an open circuit path to the transmitter high
power RF. The open circuit isolates the receiver path protecting the receiver.
(2) During the receive cycle, the RX_EN_NOT line is set low by the RLSI. Integrated
circuit I1 inverts the signal that turns on Q8 and connects -12 V to E5. With -12 V
on E5, a low impedance path is now formed which directs all energy from the anten-
na to the receiver input. R22 on the modulator board set the current through the di-
odes at 60 ma.
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B KT 73
4.3.4.7 Low Pass Filter

The Low Pass Filter is designed to reduce the level of the conducted harmonics of the 1090 MHz
transmitter carrier. The filter is a seven-pole Chebyshev response with a 0.1 dB ripple. The 3 dB
corner frequency is 1.3 GHz. The inductors are implemented using 26 AWG wire and the capac-
itors are ATC 500 volt chip capacitors. The silver plated housing with the wire in the center creates
an air dielectric coax whose characteristic impedance is 130 ohms. The coaxial cavity was creat-
ed to have a high impedance line that would, in turn, create high Q inductors. The filter has 55 dB
of attenuation at the second and third harmonics.
4.3.5 DISPLAY BOARD

The Display Board provides the following:
• A custom gas discharge display.
• Cathode/anode display drivers
• The photocell used to detect the ambient lighting conditions.
• Panel back lighting
• The mode selection switch.
• The push button switches for the IDT and VFR functions.
• The rotary switches for the 4096 code entry.
• The light bulb to light the IDT button.
• A Main board interface for each of these functions.
4.3.5.1 Gas Discharge Display (GDD)
The lighting of the Gas Discharge Display (GDD) requires an initial high voltage of 150 ± 7 volts
to ionize the gas between the anode and cathode of the display. Once the gas is ionized, the re-
sistance of the inter-electrode gap drops and the voltage required to sustain the illumination de-
creases. Thus, the ideal driver would be a current source rather than a voltage source.
The driving circuitry is capable of placing up to 195 volts (divided between the cathode and anode
display drivers) across the display to induce ionization and also limit and control the current level.
To stop ionization or to extinguish the Gas Discharge Display, a voltage of 140 ± 7 volts is required
between the anode and cathode.
4.3.5.2 Cathode Display Drivers
The cathode display drivers are located on the Main board. Each cathode driver is buffered by
the FPGA then demultiplexed and controlled by the Micro Processor. Each cathode has a current
limiting resistor in series with each segment of the display which provides constant current during
the time the display segments are illuminated.
4.3.5.3 Anode Display Drivers
The Message Anode driver is demultiplexed by the FPGA on the Main board. All other anodes
are demultiplexed by U1 which comes from the FPGA. Then it goes to the Micro Processor which
controls all the anodes drivers. Both the anode and cathode drivers act as a voltage level trans-
lator between the FPGA and the display (from +3.3 volts to ±95 volts).
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B KT 73
4.3.5.4 Photocell
External light variation is detected by the photocell, R77. The resistance of R77 varies with differ-
ent intensities of light. The photocell plus R77 and R214 on the Main board are part of a voltage
divider. This difference in voltage is feed into a A/D converter (U44 on Main board). From the A/
D converter, digital information goes to the Micro Processor.
Using the information from the A/D, the Micro Processor acts as a PWM (Pulse Width Modulator)
to control the dimming and brightness of the display.
4.3.5.5 +14, +28 Volt Back Panel Lighting:
The Back panel lighting consist of eight lamps connected in a series parallel circuit. They are con-
nected to P1 pins 20, 21 and 40. When the panel lighting is set to the +14 volt mode, all the lamps
are in parallel with the +14 volt lighting. When the panel lighting is set to the +28 volt mode, all
the lamps are in series parallel with the +28 volt lighting.
4.3.5.6 Mode Select Switch:
The mode select switch has 7-positions: OFF, FLT_ID, SBY, TST, GND, ON and ALT. The “OFF”
position provides a ground to the gate of Q19 and to the base of Q4 located on the power supply
board. This, in turn, prevents Q19 and Q4 from being turn on by the pull up resistor, R540, located
on the Main board. When the mode select switch is turned to any other position, the ground is
removed from the gate of Q19 and the base of Q4. With the absence of ground on the gate of
Q19, Q19 is allowed to turn on and pull its drain low. The drain of Q19 is connected to the anode
of CR4 on the power supply board which turns on the power supply +12 volt regulator. The base
of Q4 is connected to a resistor, R6, on the power supply board which is connected to the regu-
lated +12 volt supply. This causes Q4 to turn on and latch the power supply on.
4.3.5.7 VFR, IDT Switches:
The “VFR”, “IDT” and the remaining Mode switch positions are connected to a multiplexer (U2).
The output of the multiplexer (U2) goes to the FPGA on the Main board. Here, the information is
read, decoded and processed by the microprocessor.
4.3.5.8 Code Select Switches:
The information from the four Code Select switches go through a level translator (U8) on the Main
board. Then, the information goes to the FPGA and microprocessor where the information is read,
decoded and processed.
4.3.5.9 Fail Indicator Light:
The fail indicator light is controlled by the microprocessor on the Main board. The fail light DS19
(LED) is connected in series with a resistor R111and to +5 volts. The anode of DS19 is connected
to the drain of Q22. When the FPGA applies a high (+3.3 volts) to the gate of Q22, the source to
drain voltage drops from +5 volts to about 0.0 volts. This provides a current path to ground for the
fail light DS19 which drops about 2.4 volts and illuminates.
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B KT 73
4.3.6 MAIN BOARD AND EEPROM BOARD

Refer to the KT 73 main board schematic, P/N 002-09321-0000, and Figure 4-17, the Main board
block diagram, as required.
The Main Board performs or provides the following:
• Data processing for the received interrogation signals.
• The rear connector interface with the outside world.
• The switching scheme that provides dual functions of the rear connector pins.
• The video processing circuit.
• The front panel gas discharge display drivers.
• Suppression pulse input/output.
• Serial ports including RS232 and ARINC429 receive/transmit logic.
• Temperature sensor.
• The voice synthesis circuit.
Most of the digital IC’s are 3.3V except the A429 LSI and the voice synthesis IC which are 5V.
There are several 5 volt logic gates e.g., U63 through U68 which are used as 3.3V to 5V level
shifters.
The external EEPROM Board is installed on the back of the KT73 mounting rack and interfaces
with the Main Board via the small rear connector J1. The purpose of the external EEPROM Board
is to allow specific, exclusive aircraft information to remain with the host aircraft in case the tran-
sponder is removed. This allows units to be swapped without the need for reprogramming the
unit.
The following paragraphs will give a brief description of operation on each of the blocks shown in
Main board block diagram.
4.3.6.1 System Clock
A 40MHz crystal (Y1) in conjunction with the bypass capacitors form the 40MHz system oscillator.
The generated 40MHz signal feeds the clock inputs of both the microprocessor, U1, and the Field
Programmable Gate Array (FPGA) U5, and UART U19. This clock is divided inside the FPGA to
generate different clocks for ARINC 429 LSI, U18, and voice synthesis IC, U70.
4.3.6.2 Microprocessor
U1 AMD 186ER, is a 3.3V integrated microprocessor which contains 32 Kbytes zero-wait state
RAM, general purpose configurable I/O pins, a UART, and two independent DMA channels. It has
a programmable interrupt controller with total of 6 external interrupts. A high speed synchronous
serial port is used to send configuration data to the FPGA. It has three 16-bit timers and a hard-
ware watchdog timer. The non-multiplexed address and data bus provide glueless interface to ex-
ternal RAM, U2, and external FLASH, U3. The microprocessor program resides in the FLASH.
The major tasks performed by the microprocessor include the following:
(1) Lights the display with the appropriate characters and brightness and communicates
to the display via the FPGA.
(2) Reads front panel rotary switches and buttons via the FPGA
(3) Reads external data lines i.e. Gillham altitude lines, Standby, On/Ground, Ident dis-
crete inputs via the FPGA.
(4) Receives Mode-S data from the FPGA and sends Mode-S reply data to the FPGA.
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B KT 73
(5) Receives and transmits ARINC429 data via the ARINC429 LSI, U18.
(6) Communicates with three UARTs within U19.
(7) Provides ATE communications interface via the UART.
(8) Sets front panel display brightness by monitoring the photocell output via A/D con-
verter.
(9) The A/D converter also monitors the internal power supply voltages.
(10) Reads both the internal EEPROM on the Main Board and the external EEPROM on
the External EEPROM board (located inside configuration module).
(11) Initiates squitter by calculating the proper time intervals for the squitter and send a
signal to the FPGA to send the squitter.
(12) Checks squitter operation by reading TXSENSE signal.
(13) Communicates with the voice synthesizer U70 to generate audio message.
The 16-bit data bus and 18-bit address bus of the processor are tied to RAM and Flash. U3 is
AMD AM29LV200 2 Megabit 3.0 volt Flash memory. Processor lower and upper memory chip se-
lects, LCS and UCS are the chip selects to the RAM and Flash. The Flash has 44 pin TSOP pack-
age which is footprint compatible with 4/8/16 Megabit parts, AM29LV400/800/160. U2 is Cypress
CY62126 1 Megabit 3.3 volt SRAM.
The five processor interrupts are used as follows:
(1) INT0 is used to send an interrupt from the FPGA after the Mode-S data is sent to the
processor.
(2) INT4 will go active (high) at the end of mode-S reply.
(3) INT1 and INT2 are used to interrupt the processor by the UART A, B, C and D.
(4) INT3 is used by the ARINC429 LSI to interrupt the processor.
The processor sends and receives Mode-S data to and from the FPGA using DMA channel 0. The
sequence of events during interrogation are as follows:
(1) During a Mode-S interrogation, data flows from the FPGA to the processor. The
FPGA decodes and saves data one byte at a time. After the data is saved, the
FPGA will set the DRQ0 pin high which will initiate a DMA read from the FPGA.
(2) The processor will activate PCS5 to read the data from a known address.
(3) The FPGA decodes the address bus and PCS5. When the appropriate address oc-
curs along with PCS5, it will clear DRQ0 pin.
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During Mode-S reply, data flows from processor to the FPGA. When the FPGA sets DRQ0 high,
the processor will initiate a DMA write (1 byte/DMA) to the FPGA. The FPGA loads it to a internal
shift register. The sequence of events during reply is as follows:
(1) During mode-S reply, data flows from the processor to the FPGA. The FPGA re-
ceives 1 byte of data at a time and writes it to an internal shift register.
(2) The processor will activate PCS5 when writing the data to a known address.
(3) The FPGA decodes the address bus and PCS5. When the appropriate address oc-
curs along with PCS5, it will clear DRQ0 pin.
The processor uses INT0 and INT4 interrupt inputs to set the DMA pointer to the proper direction.
When INT0 occurs, the DMA pointer will set to execute a write operation. When INT4 occurs, the
DMA pointer will set to execute a read operation. Note that INT0 occurs after a complete Mode-
S interrogation is received and INT4 occurs after a complete reply is sent out.
The processor sends display data to the FPGA using DMA channel 1. The sequence of events is
as follows:
(1) The Processor sends a pulse DSPLY_PW from its timer output 0 to the FPGA.
(2) When the FPGA detects the pulse, it will set DSP_REQ at DRQ1 pin of the proces-
sor high. The processor activates PCS3 to write the display data to FPGA.
(3) When the FPGA sees PCS3, it clears the signal at DRQ1 pin. The handshaking con-
tinues every time periodic display refresh pulse DSPLY_PW occurs.
The processor timer out1 is used as a general purpose IO. The processor holds this pin low until
the FPGA is fully configured. That will prevent the reply output, MOD_TRIG, from being set high
for a prolonged period of time during power up which may damage the transistors on the transmit-
ter board.
The processor uses the synchronous serial port to configure the FPGA. During configuration, the
pins INIT and DONE provide status outputs to the processor. The output INIT and DONE are held
low and RED_LED held high after the application of power. The processor starts the configuration
process by applying a pulse via PI022 at the program pin of the FPGA. SDATA and SCLK output
from the processor provides serial configuration data and clock to the FPGA. The INIT pin will go
high when there is a data error.
DONE pin will go high after a successful configuration is completed. The red LED DS1 will turn on
during the configuration and turn off after a successful configuration.
The chip selects PCS0 through PCS6 and MCS2 go to the FPGA except PCS2 which goes to the
429 LSI via bus translator. The pin MCS0_PIO14 is configured as IO and provides the reset pulse
to the UART and internal flip-flops of the FPGA. The internal UART of the processor is used for
the RS485 communication.
4.3.6.3 FPGA (refer to Figure 4-18)
U5, the KT 73 Main board field programmable gate array (FPGA) is a 208 pin Xilinx XCS40XL that
is programmed by the microprocessor using a dedicated synchronous serial port. FPGA program-
ming data resides in the main board Flash memory. A JTAG connector J9 may be used for de-
bugging and programming the FPGA which will last until the next power cycle.
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The FPGA contains the digital logic to decode ATCRBS and Mode S interrogations and generate
appropriate replies to these interrogations. It interfaces with the following:
• The main board microprocessor U1.
• The display board through connector J3.
• The A/D converter U44.
• The serial nonvolatile memory U45.
• The external configuration memory via J6.
• UART U19.
• ARINC429 transceiver U18.
• Temperature sensor U60.
• Audio volume control U61.
• Audio synthesizer U71.
Also, it provides multiplexing control functions of the various pins in the two main board connectors
J1 and J6, which are external to KT73.
4.3.6.4 FPGA Input/Output Description
The FPGA has 44 single inputs, a 6-bit switch data bus SWDATA input, a 6-bit address bus, and
the ADDRBUS input. It has 58 single outputs, a 4-bit switch select bus SWSEL output, a 16-bit
Mode-S test points bus (TP_ModeS), and a 8-bit mode-C test points bus TP_mode-C. It has a
single bi-directional IO temp_SDA and a 16-bit bi-directional data bus.
The 40 MHz clock is provided from an on-board clock oscillator. The clock is internally divided to
20 MHz clock which is used in most of the functions. Microprocessor controls reset input (active
high). The 20 MHz clock uses a global clock buffer inside the FPGA. The microprocessor read
and write lines, pcs0 and pcs5 use global clock buffers. Remaining chip selects pcs1, pcs3, pcs6
and mcs2 do not use global clock buffer. These chip selects along with the address bus and read/
write lines are used to read and write from various addresses in the FPGA.
Amplitude video AMP_VIDn, limited video LIM_VIDn, 6dB video PW_6DBn, along with the sup-
pression inputs SUPR_9VBn and SUPR_ARCn are used to decode interrogations during mode-
C and mode-S interrogations. DPSKIN input from the receiver board is used to decode mode-S
DPSK data.
Eleven Gillham Altitude inputs ALT_A1 through ALT_D4, Ident input IDTx, standby input STBYx,
and on/ground input ONGNDx are read by the processor via FPGA.
There are two EEPROMs, one on-board and the other one is located in the external configuration
module. These EEPROMs are controlled via FPGA logic. Their read data lines are EEI_RDAT and
EEX_RDAT, chip selects are EE_ICS and EE_XCS. Data write and clock lines are EE_DAT and
EE_CLK. XEEPRM input represents logic 1 if external configuration module is present.
Audio volume control chip U61 also shares same data write and clock lines with a separate chip
select line VOLUME_CS.
The five pins A_D_DIN, A_D_DATA, A_D_CLK, and A_D_CSn and EOC provides A/D converter
interface to the processor. The four output pins RS485_429_EN, ADLP_EN, TISCNTL_EN,
TIS_EN, DISC_EN select between Gillham altitude input function and serial ports in J1 (TIS, serial
altitude, GPS) and between ARINC 429 TIS control function and RS232 ADLP/ADSB in the con-
nector J6. SQTR_HALT is an active low input applied from jumper CJ1 to turn off squitter trans-
mission.
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UARTCSa, UARTCSb, UARTCSc and UARTCSd are generated by decoding the processor ad-
dress bus. These are the four chip selects for the four UART. The pin SWITCH_3DB controls 3
dB switch in the receiver board; however, this function is not currently used. Four switch select
outputs SWSEL and six switch data inputs SWDATA are used to read the current state of the four
4096 knobs on the front panel. The Mode switch input MODE_DAT and the three address bits
ANODE_A0, ANODE_A1 and ANODE_A2 are used to read the state of the Mode Switch knob on
the front panel.
DSPLY_PW input starts a display data transaction. Anode signals ANODE_A0 through
ANODE_E2, cathode signals CATH_A through CATH_R, and DSP_CSn and DSP_REQ control
display. ATCRBS and Mode-S reply monitor data. MON_DAT from the modulator board is fed
back into the FPGA which is read by the processor periodically.
RX_429INT and TX_429INT interrupt outputs from the 429 transceiver are combined and routed
through a single A429_INT output pin to the processor. TEMP_SDA and TEMP_SCL pins are
used to read and write to the temperature monitor IC. AUDIO_INHIBIT input and VOICE_RESET
output holds audio synthesizer, U70, into reset. VOICE_CLK and VOICE_DATA output and VCK
input provides interface to the synthesizer.
4.3.6.5 RESET Logic
The power valid signal PWR_VAL from the power supply board is an active high signal. When 12V
and 6V signal are both active on the power supply board, PWR_VAL will be 0 volt, which will drive
Reset to high. When either of these voltages is not present PWR_VAL will go to 4V which will drive
Reset line (U30 output) low and hold the processor in reset.
The output of a separate processor reset IC, U32, is wired-OR with the output of U30-B. When
the 3.3 volt returns to an in-tolerance condition, the U32 output will drive the reset signal in active
state for 150ms to allow the power supply and processor to stabilize.
4.3.6.6 Voltage Surge Protector
The voltage surge protector consists of CR12, C229, L10, C238, Q46, Q48, U57 and associated
bias resistors. This circuit will pass through 11V to 40V from source to drain of Q48. U57 is a
shunt regulator with a 2.495 volt internal reference. When the REF input exceeds the internal ref-
erence voltage, it will drive the cathode pin voltage towards anode pin voltage such that the REF
input, pin 8, voltage is close to the internal reference voltage. When the input voltage is 36 volts
or above, the circuit will regulate the drain output of Q48 to around 36 volts. When a nominal volt-
age (e.g., 28V) is applied at the source input, Q46 will turn on, which will turn on Q48.
The resistor network of R535 and R539 divides the drain output of Q48 and applies it to the REF
input of U57, which controls the gate of Q46. As the output voltage increases, the voltage applied
to the REF input increases. As the input voltage reaches 36 volts, the voltage applied to the REF
pin of U57 reaches 2.5 volts, which begins to regulate the output voltage via Q46 and Q48. As
the input voltage increases beyond 36 volts Q46 will gradually turn off in order to maintain 2.5 volts
at the REF input. This will gradually turn off Q48 (voltage drop will increase from source to drain)
reducing the output voltage to 36 volts.
4.3.6.7 Suppression IO
The suppression circuitry outputs a pulse on the SUPP_I/O line whose amplitude is greater than
18V for the duration that the KT 73 is transmitting. This pulse is applied to the aircraft suppression
bus. The function of the output pulse on the SUPP_I/O line is to disable nearby pulsed RF equip-
ment for the duration of the pulse. An input suppression pulse seen on the SUPP_I/O line signifies
that other pulsed RF equipment is transmitting and stops the FPGA from responding to received
interrogations for that duration.
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The output suppression pulse is generated by the FPGA when KT 73 is replying to ATCRBS or
Mode-S type interrogation or during the transmission of a squitter. Prior to the suppression pulse,
C208 is at -12 volts (Suppression IO, KT73 Main board). The signal SUPR_OUT from the FPGA
turns on Q42 which turns on Q45. The voltage on the negative side of the capacitor C208 goes
to 24 volts. Since capacitor will try to hold constant voltage across it, the voltage on the positive
side will also go to 24 volts resulting in a 24 volt pulse on the suppression bus. Diode CR27 will
prevent the capacitor (+ polarity) voltage from going below ground by more than the diode drop.
Diode CR26 isolates C208 from suppression input. A suppression input will charge C185 via
R381 and R524 to +5 volts (due to clamping diode CR25-B). When this voltage exceeds the ref-
erence voltage at the non-inverting input of U47-A, its output will go low. Capacitor C186 discharg-
es through diode CR25-A and R381. R524 acts as a current limiting resistor. A similar circuit
(without a clamping diode, e.g., CR25-B) accepts 9V King suppression input. These suppression
inputs are fed as active low pulses into the FPGA.
4.3.6.8 Mode-C Reply Rate Limit Circuit
The FPGA produces 46 microsec pulse via XMIT_C pin each time an ATCRBS reply pulse is
transmitted and charges capacitor C271 via R551 and diode CR7. When the voltage at the invert-
ing input of U43-A goes over the voltage at the non-inverting input, its output at pin 1 will go low.
This will turn on Q44 and C272 charging approximately 6 volts via R477. The discharge of C271
is accomplished by R446. The discharge of C272 is accomplished by R447. C271 and C272 will
charge faster than they will discharge. Diode CR2 and Q36 provides isolation when the rate limit
circuit is not active. When the rate limit circuit is active, it decreases the effective receiver sensi-
tivity by about 30 dB. The reduction in sensitivity is caused by increasing the threshold voltage on
the video comparator U10 to a voltage which equals a receive signal level of 30dB above MTL.
4.3.6.9 MOD TRIG RST
The processor pin TMR_OUT1_PI01 is configured as a general purpose output PI01. This output
drives one input of AND gate U33 while the other input is driven by reply modulation signal. The
output MOD_TRIG drives the modulator board. MOD_TRIG is always held low except during re-
ply to prevent device failure on the transmitter board. The processor keeps PI01 low and hence
MOD_TRIG low until the FPGA is initialized. A pull down resistor R581 also ensures that
MOD_TRIG is low during power up and subsequent initialization.
4.3.6.10 Switch Interface
The front panel switches are read by the processor via the FPGA signal SWSEL1 through
SWSEL4, SW_MODE, and SWDATA0 through SWDATA5. A level translator, U8, shifts the 5 volt
input to 3.3 volt logic. The processor holds one of the 4 SW_SEL lines low and reads the switch
position of one of the 4096 switches via SWDATA0 through SWDATA5. The processor reads the
position of mode switch and the status of IDT and VFR switches via the line SW_MODE.
Voltages +90 volt and -90 volt are regulated on the main board before they go to the display board.
U7 with R570, R571 and R572 regulates -90 volt. Q1, CR1, R463, R464 and R466 regulate +90
volt line.
4.3.6.11 Display Interface
The processor via the FPGA controls the display. The processor writes appropriate cathode data
into the FPGA which drives the cathodes via 16-bit cathode bus CATH_A through CATH_R. The
cathode bus switches -90 volt to the appropriate cathodes via the connector J3. When CATH_A
goes high, it will turn on Q10 which will turn on Q26 and apply -90 volt to the cathode
DSP_CATH_A via pin 23 of J3. Similarly, other cathode bus signals from the FPGA turn on sep-
arate pair of transistors and apply -90 volts to the appropriate cathode.
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Display anodes are controlled by the processor via six FPGA signals. These are ANODE_A0,
ANODE_A1, ANODE_A2, ANODE_E2, ANODE_ELX, and ANODE_MSG which go to the display
board via J3. These signals drive a 3-to-8 decoder which applies +90 volts to the appropriate an-
odes (display board).
4.3.6.12 Analog to Digital Converter
The TLV2543 is an ADC (U44) that converts the analog signals of SUPPRESS_IO, PHOTO, +3.3
volt, +5 volt, +6 volt, +12 volt, +65 volt, +90 volt, -12 volt, - 90 volt and -5 volt lines to their digital
equivalents. The digitized signals are read by the processor through the FPGA. The amount of
ambient light determines the resistance of the photocell which, in turn, determines the voltage at
the input to the A/D converter.
4.3.6.13 Serial EEPROM
The 32K bit serial EEPROM (U45) stores information for the unit when it is turned off. The EE-
PROM stores the aircraft address, maximum airspeed, VFR code, last 4096 code, flight ID, SPR
delay, fault codes (when a failure occurs) including time and temperature, etc. Use of an optional
external EEPROM Board allows a unit to be removed from one aircraft and installed in another
without reprogramming the address, airspeed, etc. of the specific aircraft.
The information for the EEPROM is read in from the front panel by means of a special program-
ming mode. The presence of an external EEPROM is determined by the logic of the signal EX-
TERNAL EEPROM at pin 2 of J6. Processor writes necessary data to the internal EEPROM and
the external EEPROM, if present. It reads the data from the external EEPROM if present; other-
wise, the internal EEPROM is used.
4.3.6.14 Transmitter Monitor
The transmitter monitor signal TX_SENSE_5V comes from the modulator board via pin 7 of J5.
U34 level shifts the signal and feeds it to the FPGA for storage. The processor reads data later
and compares it with the actual reply data.
4.3.6.15 UART
UART circuitry consists of U19 quad UART IC and U20 RS232 driver which are used to provide
the KT73 with RS-232 communications capability. Processor RD/WR and partial address and
data lines are used to read and write to the UART.
It uses the 40 MHz clock while chip selects are driven by the FPGA. Three out of four UARTs are
used; GPS, altitude, and ADLP serial communication. The ADLP port is also used for new pro-
gram loading and communicating with the KT 73 via a PC serial port. This facilitates automated
software and hardware testing.
4.3.6.16 ARINC429
The 429 circuitry consists of 429 LSI (U18), level shifter U16 and U17, transmitter driver U40, Q49
through Q52 and associated resistors. U39C/D will disconnect the driver circuit from connector
pins. Processor RD/WR and partial address and data lines go to the LSI via level shifter. Proces-
sor PCS2 drives the chip select input and clock signal is driven by the FPGA.
4.3.6.17 RS485
The UART inside the processor and a 485 driver U41 comprises RS485 circuitry. The analog
switch U58 can connect RS485 receivers and transmitters to the connector J1.
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4.3.6.18 Discrete Inputs

Discrete inputs are Gillham altitude inputs, audio inhibit, standby, on/ground, and Ident inputs.
These inputs are diode isolated and fed to non-inverting inputs of comparators U21, U22, U23 and
U46. Most of the Gillham inputs share their pins with RS232, ARINC429 and RS485 IO serial
communication busses . The KT 73 can use either Gillham altitude inputs or the serial bus. The
processor enables Gillham altitude input by writing a logic ’1’ to DISC_EN signal. This will turn on
Q41, which will turn on Q43. This will apply +12 volt (SW_DISC_V+) at anodes of the diodes and
allow the comparators to switch high when discrete input is open and switch low when it is tied to
GND. The processor disables Gillham input by writing a logic ’0’ to DISC_EN signal. This will turn
off Q41 and Q43 and reverse bias the diodes by applying -12 volt to the anodes.
4.3.6.19 Analog Switches
U38, U39, U58 and U69 each contain quad analog switches which are used to multiplex KT 73 IO
pins on connectors J1 and J9. The processor disables Gillham altitude input by asserting a high
at the signal DISC_EN input of Q41. These analog switches are controlled by four signals
429_ON, TIS_ON, ADLP_ON and TISCNTL_ON. The processor writes to these signals via the
FPGA and transistors Q53 through Q56.
4.3.6.20 Video Processing Circuits
The video processor converts analog pulses from the detected log IF amplifier located in the re-
ceiver board and converts the signals to digital logic levels used by the FPGA. Upon entering the
video processing circuit the video signal is split into three channels.
Two peak detecting circuits are used. One is used for pulse width measurement and has a short
time constant in its sample and hold circuit. The other peak detector has a relatively long time
constant and is used to compare pulse amplitudes, specifically P1 versus P2 and P3 versus P4.
The third channel is a delayed video channel. The video is delayed by approximately 100nsec.
This delayed video is then compared with the two sample and hold channels resulting in a series
of pulses generated by the comparators U10, U11, and U12. These signals are sent to the FPGA
to be decoded.
An additional circuit, which provides ATCRBS rate limiting, integrates pulses from the FPGA which
are generated when the transponder replies to an ATCRBS interrogation.
The output of the integrator is compared with the delayed video channel and effectively reduces
the receiver sensitivity by 30dB if the integration circuit detects an overload condition.
In order to prevent receiver noise from interfering with the video processing operation, a DC level
is generated which is set slightly above the receiver noise level. This level is ORed with the output
of the sample and hold amplifiers and prevents spurious pulses from being delivered to the FPGA.
The sample and hold amplifiers must be discharged at a certain rate and time as specified by
MOPS DO-181C. The average recovery rate is specified as 4dB per microsecond. The FPGA
sends SAMPLE_HOLD signal which is used to start the recovery at about 3.0 microsec after the
falling edge of P1 or P3.
Upon entering the video processing circuit, the video is split into three paths. One video signal
runs through a 100ns delay line consisting of L9, C182, L7, C218, L8, and C217. R574 provides
the proper termination for the delay line. Capacitor C16 and CR4 are a speed up network driving
Q37 which is configured as an emitter follower. The output of Q37 is a low impedance source for
the video comparators.
The other two signals are used to drive sample and hold amplifiers. The pulse width channel con-
sists of R497, R397, and C184. They function as a DC level shifter with the AC amplitude re-
tained. Diode CR6 charges C423 and C219 to the peak value of the detected pulse.
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Q38, in an emitter follower configuration, presents a high input impedance to the hold capacitors
C219 and C423 and provides a low output impedance for the video comparators.
Resistor R476 is used to discharge the hold capacitors C219 and C423 once the pulses are de-
coded. R497 is adjusted to set the DC level at the output of Q38 to be approximately 4dB below
the peak level of the pulses present at the emitter of Q37.
The pulse amplitude channel consists of R576, R399, and C183. They function as a DC level
shifter with the AC amplitude retained. Diode CR5 charges C232 to the peak value of the detected
pulse.
Transistor Q35, in an emitter follower configuration, presents high input impedance to the hold ca-
pacitor C232 and provides low output impedance for the video comparator U12.
Resistor R486 is used to discharge C232 once the pulses are decoded. Resistor R576 is adjusted
by monitoring reply rate of an ACL interrogation at -70dBm and -21 dBm. It is adjusted such that
at both input power levels, when P4 is equal to P3-1dB, Mode-S reply rate must exceed 90%.
When P4 is P3- 6dB, ATCRBS reply must exceed 90% at -21 dBm and -70 dBm.
The sample and hold circuit in the pulse width channel charges considerably faster than the one
in the pulse amplitude channel. With both channels there is a finite time required to charge the
hold capacitors. This is the reason for the delay line.
It is desirable to have the hold capacitor charge to its maximum value before making a comparison
with the video. However, the same current is required by the buffers following the capacitors, so
the capacitors have to be large enough to supply the current.
The pulse width channel needs to hold its value only long enough to make pulse by pulse mea-
surements. The pulse amplitude channel compares amplitude from one pulse to another making
it necessary for the hold capacitor to be much larger.
As a result of the different charge rates and sample points in the two sample and hold channels,
the pulse widths and pulse positions at the output of the video comparators are different.
The pulse position on the pulse amplitude channel will be delayed by about 100ns from the pulse
width channel. The pulse widths on the pulse amplitude channel will also vary because the sam-
ple capacitor is still charging when the first pulse is compared. This results in the first pulse (P1)
being about 50ns longer than the second pulse (P2).
Additionally, because of this slow charge rate, the pulse positions will increase from the nominal
2 microsec spacing by about 50ns. The FPGA looks at the pulse width channel,
UNLIMITED_VIDEO, to determine whether a pulse of correct width and spacing has been detect-
ed.
During the time the FPGA is measuring the pulse width, it looks at the pulse amplitude channel to
see if the pulse amplitude threshold has been exceeded. This is done 450ns after the leading
edge of a pulse on the pulse width channel.
The FPGA samples at this channel, ATCRBS RATE LIMITED VIDEO, during ATCRBS interroga-
tion. If a pulse is not detected 450ns after the leading edge of a pulse on the pulse width channel,
the FPGA assumes that a rate limit condition exists and does not generate a reply. The rate lim-
iting will occur at 1200 PRF.
The FPGA sends SAMPLE_HOLD signal to turn on Q34 3.0 microsec after the falling edge of a
pulse (P1, P3) and discharges the pulse width hold capacitors C219, C423 and pulse amplitude
hold capacitor C232.
The resistive divider combination of R573, R478 and R575 set a DC voltage for the noise thresh-
old. Q39 and Q40 provide the necessary buffering. The output of Q40 is wired OR with the output
of the pulse amplitude channel Q35. The output voltage level of Q40 is adjusted to set the tran-
sponder MTL and prevent noise from triggering the video comparator U12. The output of Q39 is
wired OR with the output of the pulse width channel Q38.
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The resistive divider network of R411 and R412 lowers the noise threshold for the pulse width
channel by approximately half. This lower threshold setting enables the video comparator U11 to
make an accurate pulse width measurement while preventing noise from triggering the compara-
tor.
4.3.6.21 Voltage Regulator
The -5 volt regulator (U9) provides clean -5V used in the bias network which is particularly sensi-
tive to noise and power supply ripple. Examples are the divider networks of the PULSE WIDTH
and PULSE AMPLITUDE channels. The comparators U10, U11, and U12 require a clean supply
voltage. R413, C205 and C156 are used to provide a clean +12V_C as positive supply to the com-
parators. -12V is filtered through R493 and C207 to provide -10V_C as negative supply to the
comparators. This reduces power supply noise and ripple on the +12V_C and -10V_C lines which
are then used to power up the comparators.
4.3.6.22 Audio Circuit
The Audio circuit comprises of audio synthesizer U70, digital attenuator U61, buffer U72-A, audio
amplifier U73, and audio transformer T1. U70 synthesizes voice messages. Messages consist
of 16 bit words that are stored in the Flash memory. The processor sends the 16 bit words to a
FIFO built inside the FPGA. Necessary control logic for the FIFO and audio synthesis IC is de-
signed inside the FPGA where 16 bit words are split into 4 bit nibbles. A 625 kHz clock from the
FPGA is applied to U70 (XT input) which outputs a 7.8 kHz sampling frequency (VCK output) with
a cut off frequency 3.12 kHz. The voice chip has an on-board DAC. The DAC produces an analog
signal which is then attenuated by a digital attenuator. The attenuator shares the same data input
and clock lines as the internal and external EEPROM with a separate chip select line. Attenuation
can be controlled from the front panel to give the desired volume. The next op-amp buffers the
signal before it is ac coupled. U73A inverts and amplifies the signal. U73B invert and amplifies
U73A output. The true and inverted signals drive the transformer primary. The secondary of the
transformer is the output which will drive a 600 ohm load.
4.3.6.23 Temperature Sensor
U60 is a 9 bit digital temperature sensor with built in temperature to digital converter. The data is
read out serially by the processor. It has a bi-directional data line and a clock input. The processor
accomplishes read and write operation via the FPGA. It has a temperature accuracy of +/-2 deg.
C over a range of -25 deg. C and 100 deg. C.
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FIGURE 4-17 KT 73 MAIN BOARD BLOCK DIAGRAM
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FIGURE 4-18 KT 73 FPGA BLOCK DIAGRAM
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SECTION V
MAINTENANCE
5.1 INTRODUCTION
5.1.1 GENERAL
The maintenance section contains test and alignment procedures for an operational KT 73 Mode
S Transponder, unit P/N 066-01164-0101. This section also contains troubleshooting and assem-
bly/disassembly procedures. Before maintenance is attempted it is advisable to have thorough
understanding of the theory of operation of the unit.
5.1.2 ATC TRANSPONDER TESTS AND INSPECTIONS
5.1.2.1 General
Every two years, the FAA requires that transponders, including the KT 73, be tested and inspected
and found to comply with appendix F of part 43 of chapter 91.413, ATC transponder tests and in-
spections.
5.1.2.2 Display Readability Test
At the same time that the tests noted in section 5.1.2.1 are performed, inspect the KT 73 display
to verify that the display readability is sufficient to provide operational usage in the normal lighting
conditions of the aircraft. If the display readability is unsatisfactory, contact a dealer to have the
display replaced.
5.1.3 KT 73 FIELD SOFTWARE LOAD PROCEDURE
CAUTION:
All work must be conducted in an ESD safe en-
vironment.
NOTE:
All work must be performed by Honeywell approved
Repair & Overhaul facilities personnel.
5.1.3.1 Requirements
1. An IBM compatible PC running MS Windows 95, 98, NT, or 2000.
2. KT 73 Load Media CD (P/N: 222-30035-0102).
3. A wiring harness for loading the KT 73 software.
This harness can be built using a KT 73 Bench Test kit (P/N: 050-03675-0000). Re-
fer to the installation manual (006-10563-00XX) for pin out information and figure 5-
1 of this manual for an assembly diagram. The harness must include the following
provisions.
a. 28V or 14V DC Power.
b. A female DB-9 Connector wired to the RS-232 port on the 7 pin configuration
module connector. Optionally, wire to the small card edge connector, bypass-
ing the configuration module. It is critical that TX, RX, and GROUND all be
wired. Without a signal ground, the connection will be unreliable.
Rev. 1, May/2003 15563M01.JA Page 5-1

B KT 73
NOTE:
A PC serial port pin out is shown below.
PIN Signal
1 Received Line Signal Detector (CD)
2 Received Data (RX)
3 Transmitted Data (TX)

4 Data Terminal Ready (DTR)
5 Signal Ground (GND)
6 Data Set Ready (DSR)

7 Request to Send (RTS)
8 Clear to Send (CTS)
9 Ring Indicator
5.1.3.2 Load Procedure

1. Apply power to the KT 73.
2. Turn the Mode selector to SBY.
3. Dial 4096 code 0000.
4. Press and hold the IDT button.
5. Press and hold the VFR button.
6. Continue holding the two buttons until the radio enters programming mode. (The dis-
play will change.)
7. Turn the left code knob until the display reads ENH FUNC.
8. Press the IDT button.
9. Turn the left code knob until the display reads ADLP.
10. Press the IDT button.
11. Turn the Mode selector to OFF.
12. Turn the Mode selector to ON.
13. Connect a PC to the DB-9 connector.
14. Start the KT73Loader.exe program provided on the Load Media CD.
15. Follow the on-screen prompts to load the code.
16. The load should complete successfully.
17. Turn the mode selector to TST.
18. Wait for the lamp test to complete.
19. Press the VFR button.
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B KT 73
20. Verify that the following software versions are displayed:

a. APPL XXXX, where XXXX is the version number for the Application code in
the service bulletin.
b. BOOT XXXX, where XXXX is the version number for the Boot code in the
service bulletin.
c. FIRM XXXX, where XXXX is the version number for the Firmware in the ser-
vice bulletin.
d. VOIC XXXX, where XXXX is the version number for the Voice data in the
service bulletin.
21. Remove power from the unit.
22. Remove the old software MOD sticker from the rear of the unit.
23. Apply the new software MOD sticker to the rear of the unit.
24. The software upgrade is complete.
5.2 TEST, ALIGNMENT AND TROUBLE SHOOTING

5.2.1 TEST EQUIPMENT REQUIRED
This section contains information on special tools, fixtures, and test equipment used to test, trou-
bleshoot, align, and repair the KT73 Transponder unit. The following is a listing the test equipment
required to perform the testing and troubleshooting procedures described in this manual. Equip-
ment other than that listed can be substituted if the characteristics fulfill those required. Quantities
required are one unless otherwise specified. Refer to Figure 5-1 for a test setup diagram.
• KT 73 test harness and setup (customer fabricated, see Figure 5-1).
• IFR ATC-1400A, S-1403DL or S-1403 DME/Transponder test set.
• Oscilloscope: Tektronix TDS 380 or equivalent.
• Digital multi-meter, 3 1/2 digit, 10 mv.
• Spectrum Analyzer, Hp 8591E or equivalent (optional but recommended).
• High Frequency Probe , AGILENT (HP) 85024A or equivalent.
• Frequency counter, 250 Mhz. (optional).
• BOONTON 41A RF power meter and BOOTON 41-4a RF probe. (optional).
• 6db RF combiner HP 11636a.
• BK PRECISION Power Supply, 0 to 30 Volts, 5 Amps (or equivalent).
• PELTOR HEADSET (300 ohms) or equivalent.
• External EEPROM ASSY. P/N 200-09889-0010.
• Standard P.C. (IBM compatible) computer (laptop or desktop).
• Standard 9 pin P.C. serial (comm) port cable (generic).
• Standard 9 pin D-SUB serial connector with backshell (generic, 3 required).
• Standard 1/4 in. inline 2 conductor (mono) jack (generic).
• Standard 1/4 in. inline 3 conductor (stereo) jack (generic, 3 required).
• Bench Test Kit 050-03675-0000 which contains the following:
Rev. 1, May/2003 15563M01.JA Page 5-3

B KT 73
SYMBOL PART NUMBER DESCRIPTION UM QUANTITY

P1 030-01094-0002 CONNECTOR 12/24 P EA 1.00
P2 030-01094-0009 CONNECTOR CE EA 1.00
030-01096-0000 KEY POLARIZER EA 2.00
030-01107-0012 CONNECTOR TERM 12T EA 12.00
030-01107-0024 CONNECTOR TERM 24T EA 1.00
030-01407-0000 CONTACT FEMALE EA 7.00
030-01464-0000 HOOD W/JACKS D9 EA 3.00
030-02346-0001 CONN SUB-D CA 9S EA 3.00
030-03454-0002 CONN, RECT, RECPT, EA 1.00
222-30067-0000 KT 73 DIAGNOSTIC UTILITY EA 1.00
5.2.2 TESTING AND TROUBLESHOOTING

This section of the manual contains instructions for functional testing, troubleshooting, and align-
ing the KT 73. The functional test is a cover-on test performed to determine the operational status
of the KT 73. The alignment procedures are used after a misalignment has been isolated during
troubleshooting, or a module or component has been replaced, that requires realignment.
In general, entry into "Troubleshooting Procedure" paragraph 5.4 is from "Functional Test Proce-
dure" Paragraph 5.2.4. The test equipment should have been properly setup and turned on prior
to entry into the "Troubleshooting Procedure". If necessary, recheck the test equipment setup
procedures (paragraph 5.2.4.B.2 of the "Functional Test Procedure").
NOTE:
In KT 73 installations where an external configura-
tion module is not used, the original configuration
data stored in internal memory will be lost when the
functional test procedures are performed. Before
performing functional test procedures, record the
original programmed parameters of the unit. Then,
reprogram the unit to its original parameters upon
test completion.
CAUTION:
THIS EQUIPMENT CONTAINS ELECTRO-
STATIC DISCHARGE SENSITIVE (ESDS) DE-
VICES. EQUIPMENT MODULES AND ESDS
DEVICES MUST BE HANDLED IN ACCOR-
DANCE WITH SPECIAL ESDS HANDLING
PROCEDURES.
5.2.3 TESTING EQUIPMENT SETUP

Refer to Figure 5-1 for information on test equipment required for testing, troubleshooting, and
aligning the KT 73.
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B KT 73
FIGURE 5-1 KT73 TRANSPONDER, TEST SETUP

(Sheet 1 of 2)
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B KT 73
FIGURE 5-1 KT73 TRANSPONDER, TEST SETUP

(Sheet 2 of 2)
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B KT 73
5.2.4 FUNCTIONAL TEST PROCEDURE
A. General
The purpose of functional testing, a cover-on test, is to determine the operational
status of the KT 73 Mode S Transponder. Functional test procedures are provided
for a Return to Service condition. If an in-service unit tests within the acceptable
limits given in this test procedure, no further testing is required and the unit should
be considered suitable for installation in an aircraft. If the unit fails any portion of
the functional test, proceed to paragraph 5.2.6 of this section for fault isolation. In
general, after fault repair and/or alignment, the unit should be tested again to make
sure that it meets the performance criteria.
B. Minimum Performance Test Procedures for In-Service Field Units

(1) General
This paragraph contains functional test procedures, which specify the min-
imum performance limits within which an existing field service unit shall
meet and still be suitable for installation in an aircraft. As such, this test pro-
cedure may be used to bench test a unit, which has been removed from an
aircraft.
(2) KT 73 Test System Operating Instructions
This paragraph contains information pertaining to the test equipment re-
quired to test the KT 73 ATC Transponder. For additional test equipment
information, refer to test equipment manufacturer’s publications.
NOTE:
The software level for the ATC-1400A must be revi-
sion 4.02 and for the S-1403DL or S-1403 the revi-
sion level must be as follows: processor and display
1.4 and the pulse must be revision 2.4.
(a) Initial Setup

To initially setup the test system refer to Figure 5-1 and proceed as
follows:
1) Ensure all plugs and cables are secure and connected as
shown in Figure 5-1.
2) Allow a 30-minute warm up for the unit under test and the
test equipment.
3) On Transponder/DME test set ATC-1400A, set switches as
follows:
SWITCH POSITION
SUPPRESSOR OFF
CW/NORM/OFF NORM
F2/P2 - F1/P1 F2/P2
GPIB Address A2 ON
GPIB Address all others OFF
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B KT 73
NOTE:
The following switches are on the front of the ATC-
1400A: SUPPRESSOR, CW/NORM/OFF, and F2/
P2. The following switches are on the backside of
the ATC-1400A: GPIB Address A2, GPIB Address
all others.
4) At S-1403DL or S-1403 turn (sequence) number 0 or 1 ON

all other sequence numbers off.
(b) Turn-on/Turn-off
1) Turn-on
To turn the KT 73 test system on, proceed as follows:
On KT 73 test harness ( Bench Power Supply ), place ON/
OFF power switch ON.
Verify ON/OFF POWER indicator is illuminated.
(c) Turn-off
To turn the KT 73 test system off, proceed as follows:
On the KT 73 test harness ( Bench Power Supply ) place ON/OFF
POWER switch OFF.
(3) ON/OFF and Display Check and Function
KT 73 SELECTOR KT 73 DISPLAY
SBY position Only 4096 code

GND position Only Altitude
TST position All segments should be lit
ON position Only 4096 code
ALT position Only Altitude
FLT ID position Only Flight Identification Number
OFF position None of the segments should be lit.
The display should turn ON for FLT ID, SBY, GND, TST, ON, and ALT po-
sitions; and the display should turn OFF in the OFF position.
(4) Fault code Reporting
Initial Set Up:
Place the KT 73 in program mode, (See KT 73 Install Manual). Program
the KT 73 as follows:
1. AA1 = 5252
2. AA2 = 5252
3. MAX AIR = 75 - 150
4. ALT SRC = GILLHAM
5. ENH FUNC = NONE
6. AUTO GND = ENABLE
7. AIR VOL = 100
8. GND VOL = 100
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B KT 73
Sequentially, place the Mode Select Switch in the following positions:

OFF -> ON -> TST
After the Display Segments Test, the unit should display “TEST OK”, and
also produce an audible announcement “TEST OK”. This message can be
monitored at the Audio outputs, with a Aviation Head Set (300 ohms).
(5) Fault Code Test:
(a) Fault Code Test (A): Program the KT 73 as follows:
ALT SRC = RS-232
ENH FUNC = NONE
Sequentially, place the Mode Select Switch in the following posi-
tions:
OFF -> ON -> TST
The unit should display Fault Code “F603”, and also produce an au-
dible announcement “CHECK FAULTS CODES”.
(b) Fault Code Test (B): Program the KT 73 as follows:
ALT SRC = GILLHAM
ENH FUNC = ADLP
tions:
OFF -> ON -> TST
The unit should display Fault Code “F605”,( “F502” Only about 10
seconds) and also produce an audible announcement “CHECK
FAULTS CODES”.
(c) Fault Code Test (C): Program the KT 73 as follows:
ALT SRC = GILLHAM
ENH FUNC = TIS
tions:
OFF -> ON -> TST
The unit should display Fault Code “F602”,( “F502” Only about 10
seconds) and also produce an audible and also produce an audible
announcement “CHECK FAULTS CODES”.
(d) Fault Code Test (D): Program the KT 73 as follows:
ALT SRC = RS - 232
ENH FUNC = TIS
tions:
OFF -> ON -> TST
The unit should display Fault Codes “F602” & “F603”, and also pro-
duce an audible announcement “CHECK FAULTS CODES”.
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B KT 73
(e) Fault Code Test (E): Program the KT 73 as follows:

ALT SRC = RS - 232
ENH FUNC = ADLP
tions:
OFF -> ON -> TST
The unit should display Fault Codes “F603” & “F605”, and also pro-
duce an audible announcement “CHECK FAULTS CODES”.
(f) Fault Code Test (F): Program the KT 73 as follows:
ALT SRC = GILLHAM
ENH FUNC = NONE
With the KT 73 mode select switch turned OFF and the power dis-
connected, disconnect the ribbon-cable connector that is connected
to the modulator board from the main board.
tions:
OFF -> ON -> TST
This is a critical fault. The unit should display Fault Code “F101” and
turn on the amber “FAIL” light, located on the front panel of the unit.
The audible announcement should be “TRANSPONDER TEST
FAILED”.
NOTE:
After completing this test re-connect the ribbon cable
to the modulator board.
(6) Setup References / Pass-Fail Criteria

For ATCRBS and Mode-S testing, set the RF signal level to 60dBm ±3dBm
and use a coaxial cable of 2.0dB loss to connect the KT 73 unit to the ATC-
1400A (1400-A) test set. Program the external EEPROM as follows: set
AA1 to 5252, and AA2 to 5252; max-air speed to 150-300, and VFR to
7700. Set the KT 73 Altitude Source to “Gillham”, Enhanced Function to
“None”. The following can be viewed on the 1400-A: the transmitted power
should be at least 125 watts; the transmitted frequency should be 1090
MHz ±1 MHz; and the ATCRBS reply % that should be 100%. The follow-
ing can be viewed on the IFR S-1403DL or S-1403 (S-1403DL or S-1403)
test set: time between two squitters; the squitter’s data content (select [2nd]
[ExSyn], On the S-1403 only); and the MODE-S reply % that should be
100%.
(7) Voltage / Current Requirements
(a) For ATCRBS Mode A:
When Vin = 28 Volts; 4096 code=7777; and PRF = 1200;
then, Iin = 1.7 Amps (max)
and
when Vin = 14 Volts; 4096 code = 7777; and PRF = 1200;
then, Iin = 3.4 Amps (max).
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B KT 73
(b) For Mode S DF = 11 for a Short Reply (56 µsec ):

When Vin = 28 Volts; PRF = 200; then, Iin = 1.5 Amps (max)
and
when Vin = 14 Volts; PRF = 200; then, Iin = 3 Amps (max)
(c) For Mode S DF = 04, RR = 20 for a Long Reply (112 µsec ):
When Vin = 28 Volts; PRF = 45; then, Iin = 1.1 Amps (max)
and
when Vin = 14 Volts; PRF = 45; then, Iin = 2.05 Amps (max)
(8) ATCRBS Testing
On the KT 73, turn the Mode Select switch to the ON position. On the 1400-
A select PRF = 450. Set the S-1403DL or S-1403 for ATCRBS interroga-
tion (function1). The reply should be 100%.
(a) ATCRBS Mode A
Select Mode A on the 1400A;. The transmitted 4096 code can be
viewed on the 1400-A display. When the Ident button is pressed
(actuated) the SPI pulse will go in effect for 18 seconds. The trans-
mitted SPI pulse can be viewed by selecting AC1 on the 1400A.
(b) ATCRBS Mode C
Select Mode C on the 1400A; and turn the Mode Select switch to
the ALT position on the KT 73. The transmitted pressure altitude in
feet can be viewed by selecting AC2 on the 1400-A. The altitude
can also be viewed on the S-1403DL / S-1403.
(9) ATCRBS / Mode-S (All Call) Testing
On the 1400-A select PRF = 45. Set the S-1403DL / S-1403 for ATCRBS/
Mode S All Call (ACL) interrogation (function 4). The reply should be 100%.
(a) ATCRBS Mode-A/MODE-S All Call
Select Mode A on the 1400A; and select ON, on the KT 73. The re-
ply % will be displayed on the S-1403DL / S-1403. Here a DF-11 is
transmitted.
(b) ATCRBS Mode-C/Mode-S All Call
Select Mode C on the 1400A; and select ALT on the KT 73. The
reply % will be displayed on the S-1403DL / S-1403. Here a DF-11
is transmitted.
(10) Mode-S Testing
On the 1400-A select PRF = 45. Set the S-1403 for MODE-S interrogation
(function 2). The reply should be 100%.
(a) Mode S (UF-0):
The KT 73 should be in the ALT selector position. In the S-MENU
of the S-1403DL / S-1403 select UF-00; set the address parity (AP)
field to 52525252; and the AQ field to 1. In this mode, max-air
speed and vertical status (VS) can be checked. For different selec-
tions of KT 73 modes of operations, the VS field has different data
i.e., VS = 1 for GND; VS = 0 for ON/ALT; and VS = - for TST.
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B KT 73
(b) Mode S (UF-4):

of the S-1403DL / S-1403 select UF-04; the address parity (AP) field
to 52525252. In this mode the pressure altitude, vertical status
(VS), and flight status (FS) can be checked. Normal reply should
occur when the KT 73 and the S-1403DL / S-1403 have the same
aircraft address.
(c) Mode S (UF-5):

The KT 73 should be in the ON selector position. In the S-MENU of
the S-1403 select UF-05; set the PR and II fields to 0. In this mode
the identification code, flight status (FS), and reply ID can be
checked. For different selections of KT 73 modes of operations, the
VS field has different data i.e., VS = 1 for GND; VS = 0 for ON/ALT;
and VS = - for TST.
(d) Mode S (UF-11)
The KT 73 should be in the ON selector position. In the S-MENU of
the S-1403 select UF-11; set the aircraft address to be 77777777;
and set the data field to be 007777777. Reply AA will display the
aircraft address (the AA field should display 52525252). The alti-
tude selected through the test harness switches can be viewed on
the S-1403DL / S-1403.
(e) Mode S (UF-04, RR- 12)
On the 1400-A select PRF = 20. Set the S-1403DL / S-1403 for
MODE-S interrogation.
of the S-1403DL / S-1403 select UF-04, RR-12. Turn the KT73
Mode Select Knob to “FLT ID” set ID to “00000000”. Turn the unit
to the ALT position. On the S-1403DL / S-1403 the MB field will
equal the following.
MB = 040 60 60 60 60 60 60
Turn the KT73 Mode Select Knob to :FLT ID” set ID to “KT73TIS”.
The MB field will equal the following.
MB = 040 1324 6763 2411 2340
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B KT 73
5.2.5 RETURN TO SERVICE TESTS

The return to service function is a test sequence that provides a comprehensive evaluation of the
KT 73 Basic Mode S Transponder.
A. Signals and Conditions
Standard ATCRBS Interrogations: 450 PRF, 4096 code = 7777
Standard Mode S Interrogations: 45 PRF, UF-11, short replies
Mode S Address all 7’s, (56 µsec),
Standard Mode S Interrogations: 20 PRF, UF-04, RR-12 Long replies
Mode S Address “52525252” (112 µsec)
B. Unit Program Set Up:

Program the Unit under Test as follows:
1. Mode S Address = “52525252”
2. Air Speed = 75 / 150
3. Altitude Source = GILLHAM
4. Enhanced Function = NONE
5. Auto Ground= ENABLE
6. Air Volume= “63”
7. Ground Volume = “63”
C. Test Procedures
The following procedure/data sheet will assist in determining whether the transpon-
der is ready to return to service.
NOTE:
Measurement reference point is antenna end of 2.0
± 0.1 dB loss coaxial cable to the unit under test.
Make sure the antenna connector of the transponder
is connected to the RF I/O of the ATC-1400A test
set, before turning ON the transponder.
(1) Current Drain:

Aircraft Back Lighting Current:
@ +13.75 volts _______________ ma 320 ± 16 ma
@ +27.50 volts _______________ ma 160 ± 8 ma
Note:
With a standard RF level, measure the current drain
of the transponder. Aircraft DC Power Supply Cur-
rent: (Mode A, 4096 = 7777, PRF = 750)
@ +13.75 volts _______________ Amps 2.50 Amps Max.

@ +27.50 volts _______________ Amps 1.25 Amps Max.
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B KT 73
(2) Display Dimming:

Momentarily cover the display photocell.
Does the display intensity change? ________ Yes
Display segments: Turn the mode select Switch to the “TEST” position.
Are all segments are lit? ________ Yes
(3) IDENT:
With mode select Switch in the “ON” Position, Press the Ident button Ident
Pulse Duration:
The “IDT” should be lit on the Display _______ Yes.
Note:
Use a standard ATCRBS interrogations, and stan-
dard RF level.
Ident duration:
Use an oscilloscope and measure the Ident pulse transmit duration of the
transponder. _______ sec 18 ±2 sec
(4) Suppressor In/Out:
Use standard RF level, monitor the output of the suppress in/out line, and
measure the following using an oscilloscope:
For standard ATCRBS interrogations, during transmission:
Amplitude = _______ V 18-70 volts
Duration = _______ µsec., not to exceed 35 µsec
For standard Mode S (UF-04, RR-00, “52525252”) interrogations, during
transmission:
Amplitude = ________ V 18-70 volts
Duration = ________ µsec., not to exceed 75 µsec
For standard Mode S (UF-04, RR-12, “52525252”) interrogations, during
transmission:
Amplitude = ________ V 18-70 volts
Duration = ________ µsec., not to exceed 130 µsec
For standard ATCRBS interrogations:
Does the transponder transmit when a 18-70 volt Pulse dc is applied to the
suppress in/out pin? ______ No
Does the transponder transmit when 18-70 volts dc is applied to the sup-
press in/out pin? ______ Yes
(5) 9V Suppression In:
Note:
Use a standard interrogations and RF level.
Does the transponder transmit when a 6-12 volt Pulse dc is applied to this
pin? ____ No
Does the transponder transmit when 6-12 volts dc is applied to this pin?
____ Yes
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B KT 73
(6) Receiver Characteristics:

Sensitivity Variation with Frequency:
Use standard ATCRBS interrogations and determine the varying RF level
to produce 90% reply rate at the following two frequencies:
1029.8MHz ____ dbm- 1030.2MHz ____ dbm= ____ db 1db max
Bandwidth:
With a standard ATCRBS Interrogation signal below 1005 Mhz and above
1055 Mhz, shell be at least 60 dB stronger than that required to produce the
same reply efficiency at 1030.00 Mhz.
Adjust frequency on the 1400A to 1000 Mhz.
Is the RF level required > 60 dB _______ Yes
Adjust frequency on the 1400A to 1060 Mhz.
Is the RF level required > 60 dB _______ Yes
Sensitivity and Dynamic Range:
Determine the Minimum Trigger Level (MTL) for the following conditions:
(MTL, The Required Signal Level To Produce 90% Reply)
ATCRBS Mode A MTL ________ dBm -74 dBm ±3 dB
ATCRBS Mode C MTL ________ dBm -74 dBm ±3 dB
ATCRBS Mode A/Mode S All Call MTL________ dBm -74 dBm ±3 dB
ATCRBS Mode C/Mode S All Call MTL________ dBm -74 dBm ±3 dB
(MTL, The Required Signal Level To Produce 99% Reply)
Mode S UF 11 ________ dBm -74 dBm ±3 dB
The reply ratio shell be = 99%, @MTL+3 dB thru -21 dBm for the following
conditions:
ATCRBS Mode A ________
ATCRBS Mode C ________
ATCRBS Mode A/Mode S All Call ________
ATCRBS Mode C/Mode S All Call ________
Mode S UF 11 ________
(7) Side Lobe Suppression, Dynamic Range & Decoding: (SLS)
Determine ATCRBS SLS for the following conditions:
( P2 = P1 -9dbm ) (Dynamic Range = MTL +3 thru -21dbm )
Mode A, Reply % _________ [ @ Dynamic Range ] (Reply = 90% )
Mode C, Reply % _________ [ @ Dynamic Range ] (Reply = 90% )
( P2 = P1 ) (Dynamic Range = MTL +3 thru -21dbm )
Mode A, Reply % _________ [@ Dynamic Range ] (Reply < 10% )
Mode C, Reply % _________ [@ Dynamic Range ] (Reply < 10% )
Determine Mode S, Side Lobe Suppression for the following conditions:
Note:
Unit Set Up: UF = 04, RR = 16, PRF = 25: (Dy-
namic Range = MTL +3 thru -21dbm )
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B KT 73
( P1 = P2 = P6 & P5 = P6 -12dbm )
MODE S Reply % _______ [ @ Dynamic Range ](Reply = 99% )
( P1 = P2 = P6 & P5 = P6 +3dbm )
MODE S Reply % _______ [ @ Dynamic Range ](Reply < 10% )
(8) Pulse Level Tolerance:
Determine Pulse level decoding for the following ATCRBS/Mode S All Call
conditions:
(P1 = P3 & P4 = P3 -1dbm ) ( Dynamic Range = MTL +3 thru -21dbm )
MODE S Reply % _________ [@ Dynamic Range ] (Reply = 90% )
ATCRBS Reply % _________ [ @ Dynamic Range ] (Reply < 10% )
( P1 = P3 & P4 = P3 -6dbm ) (Dynamic Range = MTL +3 thru -21dbm )
ATCRBS Reply % _________ [ @ Dynamic Range ] (Reply = 90% )
MODE S Reply % _________ [@ Dynamic Range ] (Reply < 10% )
(9) TRANSMITTER CHARACTERISTICS:
NOTE:
Measurement reference point is antenna end of 2.0
± 0.1 dB loss coaxial cable to the unit under test.
ATCRBS MODE A/C TRANSMITTER POWER & FREQUENCY

( Peak Power > 125W: Peak Power < 500W )
(1090 Mhz ± 1 Mhz, When observed into a 50 ohm load with a VSWR of
1.5:1 or less)
( Rise Time > 50 nsec. & Rise Time < 100 nsec.)
( Fall Time > 50 nsec. & Fall Time < 200 nsec.)
( Pulse Width = 450 ± 100 nsec )
Unit Set Up: 4096 Code = “7777”, PRF = 500
FREQUENCY _______________ 1090 ± 1.0Mhz
First Pulse:
__________ Peak Power > 125W: Peak Power < 500W
__________ Pulse Width = 450 ± 50 nsec
__________ Rise Time > 50 nsec. & Rise Time < 100 nsec
__________ Fall Time > 50 nsec. & Fall Time < 200 nsec
Last Pulse:
__________ Pulse Width = 450 ± 50 nsec
MODE S TRANSMITTER POWER & FREQUENCY (Short Reply 56 µsec)
Unit Set UP: UF = 04, RR = 16, PRF = 45
FREQUENCY _______________ 1090 ± 1.0Mhz
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B KT 73
First Pulse:
__________ Pulse Width = 500 ± 50 nsec
Last Pulse:
__________ Pulse Width = 500 ± 50 nsec
MODE S TRANSMITTER POWER & FREQUENCY ( Long Reply 112
µsec )
Unit Set Up: UF = 04, RR = 20,21or 22, PRF = 20
FREQUENCY _______________ 1090 ± 1.0Mhz
First Pulse:
__________ Pulse Width = 500 ± 50 nsec
Last Pulse:
__________ Pulse Width = 500 ± 50 nsec
(10) REPLY RATE CAPABILITY:
ATCRBS Mode A/C Reply Rate Limit
Unit Set Up: RF Level = MTL + 20dbm, 4096 Code = “7777”
PRF = 750 Reply __________%( Mode A/C Reply = 99% )
PRF = 1200 Reply __________%( Mode A/C Reply = 99% )
PRF = 1800 Reply __________%( Mode A/C Reply < 72% )
PRF = 2400 Reply __________%( Mode A/C Reply < 56% )
Rev. 1, May/2003 15563M01.JA Page 5-19

B KT 73
(11) Discrete Inputs / Outputs:

ALTITUDE :
Gillham Altitude Coding:
IFR Display
Altitude in Feet Discrete InputsY / N
900 C1 C2
1,000 B1 B2 C2
2,000 B1 B4C2
6,800 A2 A4 C4
10,000 A2 A4 B1 B4 C2
26,100 A1 A4 B1 B4 C1 C2
33,500 A1 B1 B2 B4 C2 D4
41,400 A1 A2 A4 B1 B2 B4 C1 C2 D4
60,000 B1 B2 B4 C2 D4
62,100 C1 C2 B4 D4
INVALIDC1 C2 D4 D2
(12) MODE SWITCH Confirm the following:
a. With Valid Gillham inputs and the Mode Switch in the “ALT” posi-
tion. The unit Will Reply with altitude information _____Yes
b. With Invalid Gillham inputs and the Mode Switch in the “ON” posi-
tion. The unit Will Not Reply with altitude information _____Yes
(13) External Ident: Confirm the following condition:
When the external Ident is grounded, the unit will transmit a SPI Pulse for
about 18 seconds._________ Yes
(14) External Stand By: Confirm the following condition:
When the external Stand By is grounded, the unit will go into stand by
_______ Yes
(15) Audio Output: Confirm the following condition:
Connect a 300-ohm head set to the Audio Hi and Lo Outputs.
Turn the KT73 Mode Select Switch from “ON” to “TST”.
After the Display Light All Segments Test, the unit should display “TEST
OK”, and also produce an audible announcement “TEST OK”.
_______ Yes
(16) Audio Inhibit: Confirm the following condition:
Connect a 300-ohm head set to the Audio Hi and Lo Outputs.
With the Audio Inhibit grounded, turn the KT 73 Mode Select Switch from
“ON” to “TST”.
After the Display Segments Test, the unit should display “TEST OK”, and
also produce an audible announcement ”TEST OK”. _______ Yes
Rev. 1, May/2003 15563M01.JA Page 5-20

B KT 73
(17) Serial I / O Test:
Note:
Use Diagnostic Utility CD-ROM P/N 222-30067-
XXXX.
Test Selected: Test Results:
Verify Connected Responds with communication verification: OK?

________ Yes
Current Temp Responds with Unit’s temperature: __________ Yes
Temp Extremes Responds with Unit’s Min & Max temperature:

________ Yes
Hobbs Time Responds with time: __________ Yes
Serial Number Responds with Unit’s Serial Number: _________ Yes
Software Revision Responds with Unit’s Revisions of Firmware, Boot,

Application & Voice: ________ Yes
Generic Loop-back Responds with communication verification & current

(ALT_RS232) Baud Rate: ________ Yes
Generic Loop-back Responds with communication verification & current

(GPS_RS232) Baud Rate: ________ Yes
(18) Configuration Module

Note:
This section of the test may be omitted if deemed
"Not Applicable".
a. Generator set up: PRF = 50, UF11, Address = "77777777".

b. Observe the Mode S address on the S-Menu of the generator.
c. Install configuration Module program unit’s mode address to
"11112222".
d. Turn the unit OFF, then ON.
e. Verify the Mode S address is "11112222". ____________ Yes
f. Remove the configuration Module
g. Verify the Mode S address is "11112222". ____________ Yes
h. Install configuration Module program unit’s mode address to
"52525252".
i. Turn the unit OFF, then ON.
j. Verify the Mode S address is "52525252". ____________ Yes
k. Remove the configuration Module
l. Verify the Mode S address is "52525252". ____________ Yes
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B KT 73
(19) TIS Receive / Transmit Test (ARINC 429)

Note:
This test is optional and requires the KMD 540 MFD.
a. Setup Instructions:
1. Install a KMD 540 per procedures in the KT 73 Install Man-
ual.
2. Program the KT 73 for TIS mode.
3. Apply power to both units.
4. Turn the KT 73 Mode Select switch to the altitude position
("OFF" -> "ALT"), and displaying a valid altitude.
5. On the KMD 540, select the Traffic Page.
b. Test Procedure
1. With the KT 73 Mode Select Switch in the "ALT" position.
KMD 540 Message displayed:
"TIS ON" ___________ Y
"TIS UNAVAILABLE" ___________ Y
2. Turn the KT 73 Mode Select Switch to the "ON" position.

"TIS ON" ___________ Y
"TIS IS NOT ENABLED. TRANSPONDER MUST BE
REPORTING ALTITUDE." ___________ Y
3. On the KT 73, interrupt the ARINC 429 receiver.

"TIS FAIL" ___________ Y
"REPORTED TRAFFIC SYSTEM FAILURES.
TIS CONTROL" ___________ Y
4. On the KT 73, interrupt the ARINC 429 transmitter.

"TIS FAIL" ___________ Y
"NO DATA RECEIVED
FROM TRAFFIC UNIT" ___________ Y
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B KT 73
5.2.6 ALIGNMENT PROCEDURES SETUP

Alignment procedures in this paragraph are intended only for use when the KT 73 transponder
does not meet functional test requirements as presented in paragraph 5.2.4 of this section "Test-
ing and Troubleshooting".
The alignment should be performed with particular attention to the sequence of steps. Certain
segments of the radio must be pre-aligned using sub-sections of the alignment procedures before
a complete alignment can be accomplished.
The test equipment required to perform the alignment procedure described in this manual is the
same as previously listed. Equipment other than that listed can be substituted if their character-
istics are the same.
The setup for the alignment is similar to the test setup recommended in paragraph 5.2.1 of this
section. The IFR ATC-1400A/S-1403 must be specifically setup in order to perform the DPSK
alignment as described in Section 5.2.8 C.
5.2.7 ALIGNMENT PROCEDURES

A. Power Supply Alignment
1. With the UUT Mode Select switch "ON", adjust R16 for 6.0 ± 0.1 volts at
TP13.
2. Adjust R77 for 3.3 +/- 0.1 VDC.
B. Programming the Internal EEPROM (Reference Figure 5-2)
The unit’s build is assumed to be complete including software installation.
Note: The third knob from the left is the “Blank” knob.
FIGURE 5-2 KT 73 FRONT PANEL
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B KT 73
1. When the unit is turned on for the first time, it will display "AA1" in the alti-
tude window and the four most significant OCTAL digits of the aircraft ad-
dress in the Ident window which will be zeros. Then it will cycle to "AA2" and
four zeros will be displayed for the 4 least significant OCTAL digits of the
aircraft address. To change the aircraft address from all 0’s to a valid ad-
dress, the KT73 will need to be put in the programming mode.
a. The KT 73 will enter the programming mode after the following front
panel control sequences:
b. Put the unit in Standby Mode.
c. Select 0000 ident code.
d. Depress the IDT button (and hold) and then the VFR button for a
minimum of 3 seconds and the first menu "A/C ADDR" appears.
e. Press the IDT pushbutton and "AA1 0000" menu appears. Turn
Ident code selector knobs to enter the four most significant OCTAL
digits of aircraft address. "5252" is suggested.
2. Depress the "IDT" pushbutton and "AA2 0000" menu appears. Turn Ident
code selector knobs to enter the four least significant OCTAL digits of air-
craft address. "5252" is suggested.
3. Set Max Air Speed: Depress the "IDT" pushbutton and "MAX AIR " menu
appears. Depress the IDT button. Turn the "CRSR" Ident code select knob
until "75 150" appears. Depress the "IDT" button.
4. Set Altitude Source: Turn the Ident code select knob until "ALT SRC" ap-
pears. Depress the IDT button. Turn the Ident code select knob until "GILL-
HAM" appears. Depress the "IDT" button.
5. Set Auto Ground: Turn the Ident code select knob until "AUTO GND" ap-
pears. Depress the "IDT" button. Turn the "CRSR" Ident control knob until
"ENABLE" appears. Depress the "IDT" button.
6. Set Air Volume: Turn the "CRSR" Ident code select knob until "AIR VOL"
appears. Depress the "IDT" button. Turn the Ident control knob until "40"
appears. Depress the "IDT" button.
7. Set Ground Volume: Turn the "CRSR" Ident code select knob until "AUTO
GND" appears. Depress the "IDT" button. Turn the Ident control knob until
"40" appears. Depress the "IDT" button.
8. Recycle the power of KT73 and the new address will replace previous all
zero address.
C. Receiver Tuning Procedure

NOTE:
The receiver cover should be left off and the Local
Oscillator should have both covers installed
1. Local Oscillator Alignment

a. Adjust the cores of IF transformers T2 through T6 to center position
and R217 to its center position.
b. Inject a CW 1030 MHz ± 10 kHz signal to the unit under test at an
RF level that can be seen at TP2 but not saturating the IF log amp.
The suggested level is - 40 dBm.
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B KT 73
c. Connect the spectrum analyzer at TP2. (limited IF).

NOTE:
The spectrum analyzer is optional but recommend-
ed. Some steps in this procedure require a spectrum
analyzer. If not available, use a power meter and ad-
just for optimum output.
d. Set R156 for the voltage specified in TABLE 1 at the non-ground

side of C33.
NOTE
The NEC mixer transistor is graded into four IDSS
categories U71, U72, U73, and U74. This category is
marked on the top the transistor package.
IDSS CATEGORY GATE 1 BIAS SET VIA R156

U71 -0.15VDC
U72 -0.30VDC
U73 -0.60VDC
U74 -0.80VDC
TABLE 5-1 Q8 MIXER
e. Set R157 for 0.0 VDC at the non-ground side of C32.

f. Adjust C4, C18, C19, and R157 for maximum signal strength to
noise at TP2. Adjust C4 through its complete range while monitoring
the lowest and highest frequency at TP2. Use C4 to adjust the fre-
quency to be halfway between the highest and lowest frequency ob-
served. This frequency should be 60 MHz ± 29.70 kHz.
g. Reduce the CW 1030 MHz signal level if necessary for good obser-
vation and re-adjust R157, C18, and C19 for minimum DC voltage
at TP1 using the oscilloscope. Without touching R157 again, re-ad-
just R156 for minimum DC voltage.
2. I.F. Alignment
a. Inject a -60 dBm 1030 MHz ATCRBS interrogation into the receiver
input using IFR S-1403 DL/ATC-1400A. (reference figure 5-3)
b. Connect an oscilloscope to TP6 to display the video magnitude of
the interrogations (log video output).
c. Adjust T2, T3, T4, T5, and T6 for a peak video output amplitude at
TP6.
d. Video Gain Adjust: Connect the oscilloscope to TP6. With a stan-
dard ATCRBS interrogation of -70 dBm input power, observe peak
video voltage and note it for reference in the steps to follow. Change
the input power to -30 dBm and determine the difference in peak
voltage. Adjust R217 to obtain 2.40 +/- 0.07 VDC difference in peak
voltages as level is changed repetitively from - 70 to -30 dBm.
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B KT 73
e. Install the receiver cover. Set ATCRBS level to -50 dBm and estab-
lish a reference line on the oscilloscope, using the horizontal cursor
if available, at the pulse top seen at TP6. Set the test set delta fre-
quency to 3.200 MHz. Switch between +delta and - delta repetitively
while tuning T2 through T6 to obtain a response that is as high as
possible for both +delta and - delta, while also maintaining a good
pulse shape. While tuning each slug, if two peaks are possible, use
the bottom position peak. With the delta off, the pulse top should not
be lower than 120 mV from the original reference line. Now reset the
reference line to the new pulse top position. With +delta and -delta,
the pulse tops must be within 180 mV (3 dB) of the new reference
line. Some pulse distortion is permissible at +delta and -delta, but
not permissible with the delta off.
FIGURE 5-3 RECEIVER TP6 VIDEO WITH 1030 MHz +/- 3.2 MHz
f. Verify that TSS at TP6 is less than or equal to -84 dBm. TSS, tan-
gential signal sensitivity, is the pulse signal strength needed to bring
the detected negative signal plus noise peaks tangent to the posi-
tive noise peaks as illustrated in Figure 5-4.
FIGURE 5-4 TSS EXAMPLE
g. Receiver saturation should not occur below -19 dBm input RF signal
level.
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B KT 73
3. DPSK Detector Alignment

The purpose of this procedure is to align the receiver to allow it to be close
to providing the required performance in Mode S operation. This is accom-
plished by observing the shape and noise generated (in the phase detector
"eye") while following this procedure.
a. Set the ATC 1400A for a MODE-S interrogation (UF11 with
017777777 in the data field and 7’s in the address field), and at a
signal frequency of 1030 MHz. The MODE-S level is fixed at about
-50 dBm.
b. Use an oscilloscope(s) to monitor the log video output (TP6) and the
phase detector output (TP3). Using TP6, find a single data chip,
~250 nanosec wide, at approximately 16 to 18 nanosec from P1.
c. Display the phase detector "eye" pattern by superimposing the sig-
nals at TP3 and TP4 on the oscilloscope. Set both channels to equal
reference levels (display grid position) and vertical sensitivities. (V/
display grid square) There is a spot where no signal will be present
between the upper and lower traces of the "eye". See Figure 5-5
Sample DPSK Eye Diagram. The upper and lower traces will cross
each other and the reference position twice approximately 250
nanosec apart during a phase transition in the MODE-S data field.
Repetitively adjust C151, L24, and L25 for maximum signal level at
TP3 and TP4.
FIGURE 5-5 SAMPLE DPSK EYE DIAGRAM
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B KT 73
D. Main Board Alignment (initial)

1. Set R478 fully CCW. (Noise Threshold Level)
2 Set the ATC 1400A for an ATCRBS RF output of -50 dBm.
3. Observe the P1 pulse top at TP23 on the oscilloscope. Reduce the signal
to -54 dBm and establish a horizontal reference line at the pulse top. See
Figure 6 Main Board TP22 & TP23 Outputs below.
4. Return the ATC 1400A to -50 dBm interrogation output and move the probe
to TP22 without disturbing the DC offset or vertical sensitivity on the oscil-
loscope. Adjust R497 so that the flat-topped portion of the TP22 signal cor-
responding to the TP23 pulse top is equal to the reference line. In this way,
TP22 is adjusted 4 dB below TP23.
FIGURE 5-6 MAIN BOARD TP22 & TP23 OUTPUTS
E. Transmitter Alignment
1. On the UUT set the Mode Select Switch to "ON" and use the four other
knobs to enter an IDENT Code of "7777".
2. Set all variable capacitors on the transmitter board to mid-range. On the
modulator board, set R28 all the way clockwise and R11 to midrange.
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B KT 73
3. Check that the voltage supplied to the power oscillator is 50 VDC +/-1.5
VDC at E2.
4. Apply a 450 PRF ATCRBS Mode A interrogation signal. Connect oscillo-
scope to "XMTR" on IFR S-1403 DL/ATC1400A. On the transmitter, tune
C4, C7, C8 and C11 to obtain good pulse shape, maximum peak power,
least delay of pulse start, and 1090 MHz frequency. Set the frequency out
of the unit to 1090 +/-0.1 MHz. Apply 016-01007-0005 thread-locker to tun-
ing screw of FL1.
5. If difficulty is encountered refer to the "Supplemental Transmitter Align-
ment" section.
6. Once the adequate power is achieved, adjust R11 and R28 to set the de-
tected RF pulse width from IFR S-1403 DL/ATC-1400A "XMTR" to 460 +/
-5 nS and the fall time to above 50 nS.
7. Check for pulse rise time 50 to 100 nS, fall time 50 to 200 nS, pulse width
350 to 550 nS, peak power 125 W minimum, and frequency 1090 +/-0.3
MHz. Repeat steps 4, 6, and 7 as necessary.
8. Apply a 45 PRF long Mode S interrogation signal and repeat checks of pre-
vious step except width to be 500 +/-50 nS. Repeat steps 4, 6, and 7 as
necessary.
9. Interrogate for a long Mode S reply and check for in spec pulse width at the
end of the pulse train. Repeat steps 4, 6, and 7 as necessary. If necessary,
the width may be adjusted other than as in step 6.
FIGURE 5-7 KT 73 TRANSMITTER (Top View)
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B KT 73
F. Supplemental Transmitter Alignment (optional, requires a spectrum analyzer)

The following procedures may be used to isolate circuit difficulties. Use as re-
quired.
1. Ceramic Filter Check (done with UUT power off)
a. Remove C6 from the board to isolate the ceramic filter from the rest
of the circuit.
b. Connect center lead of a coax to Point "A" in figure 6 and shield to
Coax Ground. Connect this coax to the RF output port of a tracking
generator with a spectrum analyzer. Set the tracking generator to
1090 MHz, RF level to -l0 dBm and the span to 100 MHz. Note: If
a tracking generator is not available the IFR S-1403 DL/ATC-1400A
in CW mode may be used for input and the regular spectrum ana-
lyzer for output to measure approximate center frequency and loss.
c. Connect center lead of another coax to point "K" and shield to Coax
Ground. Connect this coax to the spectrum analyzer input.
d. Using spectrum analyzer, check for a center frequency of 1090 +/-
2 MHz. The insertion loss should not exceed 2.5 dB (for filter and
coupler). Allow additional loss for estimated cable loss. Adjust the
screw in the filter as necessary.
e. Remove the first coax cable completely and be sure to disconnect
the second coax from the spectrum analyzer before re-installing C6.
The point "K" coax may now be connected to the IFR S-1403 DL/
ATC-1400A for the Power Oscillator Check. Failure to disconnect
from the spectrum analyzer while turning on the power oscillator will
damage the analyzer.
2. Power Oscillator Check
a. Unless it is already done, connect a coax from point "K" as above to
the IFR S-1403 DL/ATC-1400A.
b. Apply a 450 PRF ATCRBS interrogation signal and observe the out-
put power, detected pulse shape and spectrum.
c. Adjust the variable capacitors C4 and C8 to obtain the best pulse
shape, power, frequency and least delay of pulse start. The delay
between MOD_TRIG start and the start of IFR XMTR pulse should
not exceed 200 nS. Ideal delay is about 160 nS. Excessive delay
can cause the second preamble pulse to be wider than the first.
Keep in mind that both capacitors affect the center frequency, but
C4 will primarily control the frequency while C8 will mainly control
the output power. The FL1 screw may also be used to adjust fre-
quency. Adjust to obtain 1090 +/-0.1 MHz and at least 70 watts.
The required power reading may be reduced to allow for coax loss.
d. If the oscillator is not putting out any power, or is low on power and
the Q1 transistor is known to be good, several adjustments can be
performed.
e. First, try shortening the serpentine line in figure 7 by removing the
smallest line from the chain. If that helps, shorten the network some
more.
f. If shortening the serpentine line does not help, try lengthening it by
adding the smallest line first and a longer one if it seems to help.
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B KT 73
g. If the spectrum looks skewed to one side, try adjusting the serpen-
tine line.
h. If the power is low, shim stock 024-05021-0005 shown in drawing
300-08275-0040 can be removed or added to try to improve the
power.
i. Next remove the point "K" coax, re-connect the output of the power
oscillator to the final amplifier with 0.035" shim stock, and replace
the unit coax to normal.
3. Final Amplifier Check
a. Tune C7 and C11 to maximize peak power. Note that frequency and
other parameters will have shifted some with the reconnection and
may need readjustment.
b. If adequate power cannot be obtained, shim stock 024-05021-0005
shown in drawing 300-08275-0040 can be removed or added at Q2
collector to try to improve the power.
c. Some units may have trouble with excessive droop or with pulse
width shrinkage or with poor pulse shape over a Mode S pulse train.
In this case it is necessary to re-tune C8 and C7 to obtain the best
compromise between first and last pulse. Ideal first pulse power is
about 180 W. Sometimes a pulse top instability can be improved by
adding a serpentine link and then re-adjusting tuning capacitors and
FL1 to get back on frequency. Pulse width shrinkage is sometimes
helped by setting R28 full CCW and re-adjusting R11 for width. This
may lead to too fast fall time (<50 nS). If fall time is too fast then the
optional mag wire across CR10 should be used. By thus connecting
CR9 directly to ground the fall time will be lengthened but the last
pulses of a long train may have less power.
d. Return to paragraph 5.2.8.E.5 and complete regular alignment.
G. Main Board Alignment (continued from previous)

1. P4 Adjust
a. Adjust the RF level of the ATCRBS/Mode S test set to -70 dBm and
set for an ACL interrogation.
b. Set the P4 level on the test set to P4 = P3 - l dB and adjust R576 for
greater than 90% Mode S reply efficiency.
c. Set the P4 level on the test set to P4 = P3 - 6dB and adjust R576 for
greater than 90% ATCRBS reply efficiency.
d. Set the P4 level, on the test set, to P4 = P3 - l dB and verify that the
Mode S reply efficiency is greater than 90%. If the Mode S reply rate
is less than 90%, then adjust R576.
e. Adjust the RF level of the test set to -2ldBm and check for a Mode
S reply rate of greater than 90%. Adjust R576 to achieve a reply rate
greater than 90%, if needed.
f. Set the P4 level, on the test set, to P4 = P3 -6dB and check for an
ATCRBS reply rate of greater than 90%. If the reply rate is less than
90%, then adjust R576 accordingly.
g. Repeat steps in 5.2.7.C.1 until all the conditions are satisfied.
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B KT 73
2. (Setting MTL) Set the RF test set for a RF level of -75 dBm and a standard
ATCRBS interrogation. Adjust R478 for approximately 50% reply rate.
Check for greater than 90% reply rate at -74 dBm.
3. Centering SPR Position tuning by the front panel
a. The KT 73 will enter the programming mode after the following front
panel control sequence:
1. Put the unit in Standby Mode.
2. Select 0000 ident code.
3. Depress the IDT button (and hold) and then VFR button for
a minimum of 3 seconds.
b. Press the IDT until "CODE>000" menu appears.
c. Rotate three knobs, marked "FLT ID", BLANK and "BRT" until the
word "SPR" appears.
d. Press IDT to enter this code. Change SPR setting from 0 by rotating
BRT knob.
e. Interrogate the unit with UF11, RF level -21 dBm, and SPR position
offset at 0 nanosec.
f. Vary the SPR position offset both plus time and minus time by rotat-
ing BRT knob on KT73 and observe the times where the reply rate
falls below 100%.
g. Increment or decrement the delay value (-3 to +4) to obtain the best
balance of plus and minus time.
h. Test the reply rate with SPR position at 0 nanosec, +50 nanosec
and -50 nanosec on S-1403DL. Verify 100% replies. Set the RF lev-
el to MTL +l and verify 100% replies at SPR positions -50nanosec,
0 nanosec, and +50 nanosec. Set the SPR position on the IFR to
+200 nanosec and -200 nanosec. See that the reply rate is zero at
both positions.
i. Store the delay by depressing the IDT button
H. Unit Level Alignment for Interfering Pulses and SLS.

The purpose of this procedure is to provide the information required for aligning the
unit so that it will meet the required SLS and interfering pulse performance. This is
accomplished by observing the noise generated in the phase detector "eye" (by the
interfering pulse) and the percent reply indicator on the ATC 1400A while following
this procedure.
1. Refer to Procedure 5.2.8.I of this section for information concerning the
proper set up of the ATC A and ATC1403 DL to provide interfering pulses
from a single generator. With the octal number base selected, set the IFR
S-1403 DL for a MODE S interrogation (UFll with 017777777 in the data
field and 7’s in the add field), and signal frequency of 1030 MHz. The
MODE-S level should be fixed at -50 dBm. Disable the squitter by using a
shorting jumper on the two pin CJ1 of the KT73 Main Board. If Antenna B
output is not -50 dBm, the power should be set on the C020 menu, Brf win-
dow of the top S1403 DL display.
2. Adjust the ATCRBS interfering pulse level to -60 dBm with the ATC1400 A
level control.
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B KT 73
3. Use an oscilloscope(s) to monitor the log video output (TP6) and the phase
detector output TP3 or TP4. With the interference pulse added by setting
the ATC 1400 A to DBL/INTERR/INTR PULSE to 5.0 microsec, watch the
interference pulse appear on P6 of the TP6 video signal.
4. Move the interference pulse to a spot with a double chip within 250 nanosec
of each other near the end of P6. A good spot to observe is somewhere be-
tween 16 and 18 microsec from P1.
5. Use the two channels to display TP3 and TP4 using delay sweep function
to place the scope CRT on the desired set of chips, while keeping the ex-
ternal trigger on the TAC SYNC output mentioned in 12.4.2.
6. Display the phase detector "eye" pattern by superimposing the signals at
TP3 and TP4 on the oscilloscope. Set both channels to equal reference lev-
els and vertical sensitivities. In the absence of interfering pulses, no signal
will be present between the upper and lower traces of the "eye". See Figure
5 Sample DPSK Eye Diagram. The upper and lower traces will cross each
other and the reference position during a phase transition in the MODE-S
data field. As the interfering pulse magnitude is increased relative to the
MODE-S interrogation, noise will become present in the "eye" at the posi-
tion in the data field coinciding with the location of the interfering pulse. Ad-
just C151, L24, and L25 for maximum signal level at TP3 and TP4.
7. Near the end of the MODE-S data field will be an area where two phase
changes occur 250ns apart with no phase changes occurring at least 500ns
on either side. Adjust the interfering pulse position such that it will be cen-
tered on these two phase changes.
8. Set the level of the interfering pulse to -3 dB.
9. Place the interference pulse over the first chip following the SPR (1.8 us fol-
lowing the leading edge of P6). Using the thumbwheel switch, slowly move
the interfering pulse to the end of P6 and observe the reply rate stays over
60%.
NOTE:
Steps 10, 11, and 12 are to be performed if the unit
does not achieve 60% reply rate after performing
steps 1 through 9.
10. Adjust L24, L25, and C151 to minimize the noise and achieve the reply rate.
The rate with interference must be at least 60%
11. While observing the eye noise and percent reply, fine adjust T5 by rotating
its core no more than ± one turn from the nominal position. Fine adjust
C151, L24, and L25 while adjusting T5 for minimum eye noise and maxi-
mum percent reply. It may be necessary to fine tune T4 and T6 (by no more
than ± one quarter turn from nominal) while fine tuning C151, L24, and L25
for maximum percent reply.
12. Repeat steps 9 and 10 until the percent reply is greater than 60% with an
interference level -3 dB.
13. Check SLS to ensure that the unit percent reply is less than 10% with
P5=P6 + 3dB with the ATC 1400A RF level at -20 dBm through MTL+3dB.
Also check for 100% replies with P5=P6-12dB with the RF level set from -
20dBm through MTL+3dB.
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B KT 73
NOTE:
If SLS is > 10% when P5=P6+3dB, this indicates that
the DPSK detector is working too efficiently in the
presence of interfering pulses to allow the specified
SLS performance. If this occurs the detector must be
de-tuned just enough to allow passing SLS but not
enough to cause failure of interfering pulse perfor-
mance. First de-tune by adjusting C151 only then
L24 and L25 (if required) and only as a last resort,
T4, T5, and T6.
14. Performing step 10 may slightly off-tune the IF filter and may lower TSS.
Unit TSS should be at least -84 dBm. When performing steps 9 and 10,
monitor TSS to ensure it remains at this level or more. The unit is now
aligned for SLS and interfering pulse performance.
I. Single IFR ATC 1400A/S1403 DL Test Set Interference Method

IFR S-1403 DL/ATC-1400A Mode S Interference Setup and Calibration
1. Overview:
Honeywell Engineering has determined that the following procedure is the
most direct method of conducting the Mode S interference measurements,
using a single IFR.
NOTE: XXXXX’s mean a "Don’t care" condition. IP means interference
pulse.
2. S-1403DL SETUP:
Power up the IFR by switching on the power switch on the left side of the
S-1403 DL and precede to setup tables below.
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B KT 73
3. ATC-1400A SETUP:
4. Process:
a. Connect the two inputs of a 50 OHM RF combiner to the S-1403 DL
Ant. B RF port and the ATC-1400A RF I/0 port. The combiner output
is used for the UUT RF I/O port connection. The Ant. B Port pro-
vides a Mode S signal to sum together with an interference pulse
supplied by the Port A of the ATC-1400A. Connect the power supply
set between 14 to 28 VDC to the aircraft power input of the KT 73
Manual Test Panel. Connect the card edge connector from the KT
73 Manual Test Panel (Happy Box) to the UUT and power up the
UUT.
b. Connect TAC SYNC output, ATC-1400A, to an oscilloscope EXT.
SYNC input.
c. After following the setup in 12.2 and 12.3, the 1400-A portion of the
IFR tester should not be interrogating. With the S-1403 DL: C Menu
10 in "Func; (2)", which is Mode S interrogation, Port B should be
Mode S interrogating and receiving 100% replies in the "AntB" sec-
tion of the C Menu 1 of the IFR test panel. Set the ATC-1400A as
follows:
1. RF LEVEL to -50dBm.
2. SLS/ECHO to 0 and OFF.
3. DBL/INTERR/INTR PULSE to 005.0 and INTERF-.
4. Set the oscilloscope for a delayed sweep of 1uS/div and a
main sweep of 2uS/div. Connect the vertical input of the os-
cilloscope to TP6 on the receiver board and set the vertical
sensitivity, of the oscilloscope, to 500 mV/div using a X10
probe. Be aware that the oscilloscope probes may cause
distortion of the video if their impedance and calibration is
not correct.
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B KT 73
d. The IP should be visible in front of the Mode S video signal on TP6.

Adjust the ATC-1400A INTR PULSE WIDTH CONTROL such that
the interference pulse (IP) is 800 nanosec in width as shown on the
oscilloscope.
e. At this point the IP is just to the left of Pl, forward in time, and the
calibration of the IP level with respect to P1 may begin. The IP must
be placed forward in time relative to P1 because of the random am-
plitude shift produced by constructive and destructive interference
between the Mode S and IP RF carriers introduced after detection
into the TP6 video.
f. Set the oscilloscope delay time position so that the IP and P1, of the
Mode S interrogation, are displayed on the oscilloscope CRT.
g. Adjust the RF LEVEL, on the ATC-1400A, and the RF level (RFLev)
on the S-1403 DL (using the S-1403 DL cursor and slew control) so
that the IP and P1 are of equal amplitude as shown on the oscillo-
scope CRT. Check the C20 menu to see Port B output is -50 dBm
by seeing "RFLvl: 50 +0.0" If not, manipulate the cursor with the ar-
rows buttons until the two digits following RFLvl are highlighted and
adjust the power to indicate 50 which is actually -50 dBm output
power. Fine-tuning of the amplitudes to the nearest tenth dB can be
done with the second part of RFLvl "+0.0".
h. The SLS/ECHO thumb wheel switch, on the ATC-1400A, is used to
control the power level of the IP, with respect to P6, instead of the
ATC-1400A RF LEVEL vernier control.
i. Adjust the delay time to 2 microsec/div on the oscilloscope.
j. Vary the oscilloscope delay time position so that the entire P6 part
of the Mode S interrogation is visible on the oscilloscope CRT.
k. The DBL INTERR/INTERF thumb wheel switches may be used to
position the IP anywhere along P6.
l. The above setup and calibration procedure MUST be repeated any
time that the S-1403 DL setup is changed. This procedure should
be done before ANY IP testing and measurements are conducted
because the S-1403 DL may not maintain identical power levels
from test-to-test. It must not be assumed that the IFR will produce
identical power levels at all times. The Mode S IP alignment/testing
is very sensitive to RF power levels and levels during alignment and
test.
m. Setup for single IFR interference testing is complete.
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B KT 73
5.3 GENERAL OVERHAUL

5.3.1 VISUAL INSPECTION
This section contains instructions and information to assist in determining, by visual inspection,
the condition of the units major assemblies and subassemblies. These inspection procedures will
assist in finding defects resulting from wear, physical damage, deterioration, or other causes. To
aid inspection, detailed procedures are arranged in alphabetical order.
A. Capacitors, Fixed
Inspect capacitors for case damage, body damage, and cracked, broken, or
charred insulation. Check for loose, broken, or corroded terminal studs, lugs, or
leads. Inspect for loose, broken, or improperly soldered connections. On chip caps,
be especially alert for hairline cracks in the body and broken terminations.
B. Capacitors, Variable
Inspect trimmers for chipped and cracked bodies, damaged dielectrics, and dam-
aged contacts.
C. Chassis
Inspect the chassis for loose or missing mounting hardware, deformation, dents,
damaged fasteners, or damaged connectors. In addition, check for corrosion or
damage to the finish that should be repaired.
D. Circuit Boards
Inspect for loose, broken, or corroded terminal connections; insufficient solder or
improper bonding; fungus, mold, or other deposits; and damage such as cracks,
burns, or charred traces.
E. Connectors
Inspect the connector bodies for broken parts; check the insulation for cracks, and
check the contacts for damage, misalignment, corrosion, or bad plating. Check for
broken, loose, or poorly soldered connections to terminals of the connectors. In-
spect connector hoods and cable clamps for crimped wires.
F. Covers and Shields
Inspect covers and shields for punctures, deep dents, and badly worn surfaces. Al-
so, check for damaged fastener devices, corrosion and damage to finish.
G. Flex Circuits
Inspect flex circuits for punctures, and badly worn surfaces. Check for broken trac-
es, especially near the solder contact points.
H. Front Panel
Check that name, serial, and any plates or stickers are secure and hardware is
tight. Check that the handle is functional, securely fastened, and handle casting is
not damaged or bent.
I. Fuse
Inspect for blown fuse and check for loose solder joints.
J. Insulators
Inspect insulators for evidence of damage, such as broken or chipped edges,
burned areas, and presence of foreign matter.
K. Jacks
Inspect all jacks for corrosion, rust, deformations, loose or broken parts, cracked
insulation, bad contacts, or other irregularities.
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B KT 73
L. Potentiometers
Inspect all potentiometers for evidence of damage or loose terminals, cracked in-
sulation or other irregularities.
M. Resistors, Fixed
Inspect the fixed resistors for cracked, broken, blistered, or charred bodies and
loose, broken, or improperly soldered connections. On chip resistors, be especially
alert for hairline cracks in the body and broken terminations.
N. RF Coils
Inspect all RF coils for broken leads, loose mountings, and loose, improperly sol-
dered, or broken terminal connections. Check for crushed, scratched, cut or
charred windings. Inspect the windings, leads, terminals and connections for cor-
rosion or physical damage. Check for physical damage to forms and tuning slug
adjustment screws.
O. Terminal Connections Soldered
(1) Inspect for cold-soldered or resin joints. These joints present a porous or
dull, rough appearance. Check for strength of bond using the points of a
tool.
(2) Examine the terminals for excess solder, protrusions from the joint, pieces
adhering to adjacent insulation, and particles lodged between joints, con-
ductors, or other components.
(3) Inspect for insufficient solder and unsoldered strands of wire protruding
from the conductor at the terminal. Check for insulation that is stripped back
too far from the terminal.
(4) Inspect for corrosion at the terminal.
P. Transformers
(1) Inspect for signs of excessive heating, physical damage to the case,
cracked or broken insulation, and other abnormal conditions.
(2) Inspect for corroded, poorly soldered, or loose connecting leads or termi-
nals.
Q. Wiring/Coaxial Cable
Inspect wiring in chassis for breaks in insulation, conductor breaks, cut or broken
lacing and improper dress in relation to adjacent wiring or chassis.
5.3.2 CLEANING
A. General
This section contains information to aid in the cleaning of the component parts and
subassemblies of the unit.
WARNING:
GOGGLES ARE TO BE WORN WHEN USING
PRESSURIZED AIR TO BLOW DUST AND
DIRT FROM EQUIPMENT. ALL PERSONNEL
SHOULD BE WARNED AWAY FROM THE IM-
MEDIATE AREA.
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B KT 73
WARNING:
OPERATIONS INVOLVING THE USE OF A
CLEANING SOLVENT SHOULD BE PER-
FORMED UNDER A VENTILATED HOOD.
AVOID BREATHING SOLVENT VAPOR AND
FUMES; AVOID CONTINUOUS CONTACT
WITH THE SOLVENT. WEAR A SUITABLE
MASK, GOGGLES, GLOVES, AND AN APRON
WHEN NECESSARY. CHANGE CLOTHING
UPON WHICH SOLVENTS HAVE BEEN
SPILLED.
WARNING:
OBSERVE ALL FIRE PRECAUTIONS FOR
FLAMMABLE MATERIALS. USE FLAMMABLE
MATERIALS IN A HOOD PROVIDED WITH
SPARK-PROOF ELECTRICAL EQUIPMENT
AND AN EXHAUST FAN WITH SPARKPROOF
BLADES.
B. Recommended Cleaning Agents

Table 5-2 lists the recommended cleaning agents to be used during overhaul of the
unit.
NOTE:
EQUIVALENT SUBSTITUTES MAY BE USED FOR
LISTED CLEANING AGENTS.
TYPE USED TO CLEAN

Denatured Alcohol Various, exterior and interior
DuPont Vertrel SMT Various, interior
PolaClear Cleaner (Polaroid Corp.) or CRT display filter, LCD displays, and
Texwipe TX129 (Texwipe Co.) general purpose lens/glass cleaner.
KimWipes lint-free tissue Various
(Kimberly Clark Corp.)
Cloth, lint-free cotton Various
Brush, flat with fiber bristles Various
Brush, round with fiber bristles Various
Dishwashing liquid (mild) Nylon, Rubber Grommets
TABLE 5-2 RECOMMENDED CLEANING AGENTS
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B KT 73
C. Recommended Cleaning Procedures
CAUTION:
DO NOT ALLOW SOLVENT TO RUN INTO
SLEEVES OR CONDUIT THAT COVERS
WIRES CONNECTED TO INSERT TERMI-
NALS.
1. Exterior
(a) Wipe dust cover and front panel with a lint-free cloth dampened with
denatured alcohol.
(b) For cleaning connectors, use the following procedure.
(1) Wipe dust and dirt from bodies, shells, and cable clamps us-
ing a lint-free cloth moistened with denatured alcohol.
(2) Wipe parts dry with a clean, dry lint-free cloth.
(3) Remove dirt and lubricant from connector inserts, insulation,
and terminals using a small soft bristled brush moistened
with denatured alcohol.
(4) Dry the inserts with an air jet.
(c) Remove cover(s).
(d) If necessary, open any blocked ventilation holes by first saturating
the debris clogging the apertures with denatured alcohol and then
blowing the loosened material out with an air stream.
2. Interior
The following solvents are no longer recommended for benchtop or rework
cleaning of printed circuit boards, modules, or sub-assemblies.
FREON TF, IMC TRICHLOROETHANE

CARBON TETRACHLORIDE DETERGENT (ALL AND EQUIVALENTS)
CHLOROFORM METHYLENE CHLORIDE
TRICHLOROETHYLENE GENESOLV 2004/2010
PROPYL ALCOHOL METHYL ALCOHOL
ETHYL ALCOHOL BUTYL ALCOHOL
XYLENE PRELETE (CFC-113)
TABLE 5-3 UNSAFE CLEANING AGENTS
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B KT 73
CAUTION:
DO NOT USE SOLVENT TO CLEAN PARTS
COMPOSED OF OR CONTAINING NYLON OR
RUBBER GROMMETS. CLEAN THESE
ITEMS WITH MILD LIQUID DISHWASHING
DETERGENT AND WATER. USE DETER-
GENT FOR THIS PURPOSE ONLY.
CAUTION:
DUPONT VERTREL SMT DOES HAVE GEN-
ERAL MATERIAL COMPATIBILITY PROB-
LEMS WITH POLYCARBONATE, POLYSTY-
RENE, AND RUBBER. IT IS RECOMMENDED
THAT THESE MATERIALS BE CLEANED
WITH DENATURED ALCOHOL.
CAUTION:
DO NOT ALLOW EXCESS CLEANING SOL-
VENT TO ACCUMULATE IN ANY OF THE AD-
JUSTMENT SCREW CREVICES AND THERE-
BY SOFTEN OR DISSOLVE THE ADJUST-
MENT SCREW EPOXY SEALANT.
CAUTION:
AVOID AIR-BLASTING SMALL TUNING COILS
AND OTHER DELICATE PARTS BY HOLDING
THE AIR NOZZLE TOO CLOSE. USE BRUSH-
ES CAREFULLY ON DELICATE PARTS.
CAUTION:
IMPROPER CLEANING CAN RESULT IN SUR-
FACE LEAKAGE AND CONDUCTIVE PARTIC-
ULATES, SUCH AS SOLDER BALLS OR ME-
TALLIC CHIPS, WHICH CAN CAUSE ELEC-
TRICAL SHORTS. SEVERE IONIC CONTAM-
INATION FROM HANDLING AND FROM
ENVIRONMENTAL CONDITIONS CAN RE-
SULT IN HIGH RESISTANCE OR OPEN CIR-
CUITS.
CAUTION:
ULTRASONIC CLEANING CAN DAMAGE
CERTAIN PARTS AND SHOULD GENERALLY
BE AVOIDED.
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B KT 73
NOTE:
Solvents may be physically applied in several ways
including agitation, spraying, brushing, and vapor
degreasing. The cleaning solvents and methods
used shall have no deleterious effect on the parts,
connections, and materials being used. If sensitive
components are being used, spray is recommended.
Uniformity of solvent spray flow should be maxi-
mized and wait-time between soldering and cleaning
should be minimized.
NOTE:
Clean each module subassembly. Then remove any
foreign matter from the casting.
Remove each module subassembly. Then remove any foreign matter from
the casting.
(a) Casting covers and shields should be cleaned as follows:
(1) Remove surface grease with a lint-free cloth.
(2) Blow dust from surfaces, holes, and recesses using an air
stream.
(3) If necessary, use a solvent, and scrub until clean, working
over all surfaces and into all holes and recesses with a suit-
able non-metallic brush.
(4) Position the part to dry so the solvent is not trapped in holes
or recesses. Use an air stream to blow out any trapped sol-
vent.
(5) When thoroughly clean, touch up any minor damage to the
finish.
(b) Assemblies containing resistors, capacitors, rf coils, inductors,
transformers, and other wired parts should be cleaned as follows:
(1) Remove dust and dirt from all surfaces, including all parts
and wiring, using soft-bristled brushes in conjunction with air
stream.
(2) Any dirt that cannot be removed in this way should be re-
moved with a brush (not synthetic) saturated with an ap-
proved solvent, such as mentioned above. Use of a clean,
dry air stream (25 to 28 psi) is recommended to remove any
excess solvent.
(3) Remove flux residue, metallic chips, and/or solder balls with
an approved solvent.
(c) Wired chassis devices containing terminal boards, resistor and ca-
pacitor assemblies, rf coils, switches, sockets, inductors, transform-
ers, and other wired parts should be cleaned as follows:
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B KT 73
NOTE:
When necessary to disturb the dress of wires and
cables, note the positions before disturbing and re-
store them to proper dress after cleaning.
jet.
(2) Finish cleaning chassis by wiping finished surfaces with a
lint-free cloth moistened with solvent.
(3) Dry with a clean, dry, lint-free cloth.
(4) When thoroughly clean, touch-up any minor damage to the
finish.
(5) Protect the chassis from dust, moisture, and damage pend-
ing inspection.
(d) Ceramic and plastic parts should be cleaned as follows:
jet.
(2) Finish cleaning chassis by wiping finished surfaces with a
lint-free cloth moistened with solvents.
(3) Dry with a clean, dry, lint-free cloth.
5.3.3 REPAIR
A. General
This section contains information required to perform limited repairs on the unit.
The repair or replacement of damaged parts in airborne electronic equipment usu-
ally involves standard service techniques. In most cases, examination of drawings
and equipment reveals several approaches to perform a repair. However, certain
repairs demand following an exact repair sequence to ensure proper operation of
the equipment. After correcting a malfunction in any section of the unit, it is recom-
mended that a repetition of the functional test of the unit be performed.
B. Repair Precautions
1. Ensure that all ESDS and MOS handling precautions are followed.
2. Perform repairs and replace components with power disconnected from
equipment.
3. Use a conductive table top for repairs and connect table to ground conduc-
tors of 60Hz and 400Hz power lines.
4. Replace connectors, coaxial cables, shield conductors, and twisted pairs
only with identical items.
5. Reference “component side” of a printed circuit board in this manual means
the side on which components are located; “solder side” refers to the other
side. The standard references are as follows: nearside is the component
side; farside is the solder side; on surface mount boards with components
on both sides, the nearside is the side that has the J#### and P#### con-
nector numbers.
6. When repairing circuits, carefully observe lead dress and component orien-
tation. Keep leads as short as possible and observe correct repair tech-
niques.
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B KT 73
7. There are certain soldering considerations with surface mount compo-

nents. The soldering iron tip should not touch the ceramic component body.
The iron should be applied only to the termination-solder filet.
8. Observe cable routing throughout instrument assembly, prior to disassem-
bly, to enable a proper reinstallation of cabling during reassembly proce-
dures.
CAUTION
PROCEDURES.
C. Electrostatic Sensitive Devices (ESDS) Protection

1. Always discharge static before handling devices by touching something
that is grounded.
2. Use a wrist strap grounded through a 1MΩ resistor.
3. Do not slide anything on the bench. Pick it up and set it down instead.
4. Keep all parts in protective cartons until ready to insert into the board.
5. Never touch the device leads or the circuit paths during assembly.
6. Use a grounded tip, low wattage soldering station.
7. Keep the humidity in the work environment as high as feasibly possible.
8. Use grounded mats on the work station unless table tops are made of ap-
proved antistatic material.
9. Do not use synthetic carpet on the floor of the shop. If a shop is carpeted,
ensure that a grounded mat is placed at each workstation.
10. Keep common plastics out of the work area.
D. MOS Device Protection

MOS (Metal Oxide Semiconductor) devices are used in this equipment. While the
attributes of MOS type devices are many, characteristics make them susceptible
to damage by electrostatic or high voltage charges. Therefore, special precautions
must be taken during repair procedures to prevent damaging the device. The fol-
lowing precautions are recommended for MOS circuits, and are especially impor-
tant in low humidity or dry conditions.
1. Store and transport all MOS devices in conductive material so that all ex-
posed leads are shorted together. Do not insert MOS devices into conven-
tional plastic “snow” or plastic trays used for storing and transporting stan-
dard semiconductor devices.
2. Ground working surfaces on workbench to protect the MOS devices.
3. Wear cotton gloves or a conductive wrist strap in series with a 200KΩ re-
sistor connected to ground.
4. Do not wear nylon clothing while handling MOS devices.
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B KT 73
5. Do not insert or remove MOS devices with power applied. Check all power
supplies to be used for testing MOS devices. and be sure that there are no
voltage transients present.
6. When straightening MOS leads, provide ground straps for the apparatus for
the device.
7. Ground the soldering iron when soldering a device.
8. When possible, handle all MOS devices by package or case, and not by
leads. Prior to touching the device, touch an electrical ground to displace
any accumulated static charge. The package and substrate may be elec-
trically common. If so, an electrical discharge to the case would cause the
same damage as touching the leads.
9. Clamping or holding fixtures used during repair should be grounded, as
should the circuit board, during repair.
10. Devices should be inserted into the printed circuit boards such that leads
on the back side do not contact any material other than the printed circuit
board (in particular, do not use any plastic foam as a backing).
11. Devices should be soldered as soon as possible after assembly. All solder-
ing irons must be grounded.
12. Boards should not be handled in the area around devices, but rather by
board edges.
13. Assembled boards must not be placed in conventional, home-type, plastic
bags. Paper bags or antistatic bags should be used.
14. Before removing devices from conductive portion of the device carrier,
make certain conductive portion of carrier is brought in contact with well
grounded table top.
E. PC Board, Two-Lead Component Removal (Resistors, Capacitors, Diodes, etc.)

1. Heat one lead from component side of board until solder flows, and lift one
lead from board; repeat for other lead and remove component (note orien-
tation).
2. Melt solder in each hole, and using a desoldering tool, remove solder from
each hole.
3. Dress and form leads of replacement component; insert leads into correct
holes.
4. Insert replacement component observing correct orientation.
F. PC Board, Multi-Lead Component Removal (IC’s, etc.)

1. Remove component by clipping each lead along both sides. Clip off leads
as close to component as possible. Discard component.
2. Heat hole from solder side and remove clipped lead from each hole.
3. Melt solder in each hole, and using a desoldering tool, remove solder from
each hole.
4. Insert replacement component observing correct orientation.
5. Solder component in place from farside of board. Avoid solder runs. No sol-
der is required on contacts where no traces exist.
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B KT 73
G. Replacement of Power Transistors

1. Unsolder leads and remove attaching hardware. Remove transistor and
hard-coat insulator.
2. Apply Thermal Joint Compound Type 120 (Wakefield Engineering, Inc.) to
the mounting surface of the replacement transistor.
3. Reinstall the transistor insulator and the power transistor using hardware
removed in step (1).
4. After installing the replacement transistor, but before making any electrical
connections, measure the resistance between the case of the transistor
and the chassis, to ensure that the insulation is effective. The resistance
measured should be greater than 10MΩ.
5. Reconnect leads to transistor and solder in place.
H. Replacement of Printed Circuit Board Protective Coating
WARNING
CONFORMAL COATING CONTAINS TOXIC
VAPORS! USE ONLY WITH ADEQUATE VEN-
TILATION.
1. Clean repaired area of printed circuit board per instructions in the Cleaning
section of this manual.
2. Apply Conformal Coating, Humiseal #1B-31 HYSOL PC20-35M-01 (Hu-
miseal Division, Columbia Chase Corp., 24-60 Brooklyn Queens Express-
way West, Woodside, N.Y., 11377) P/N 016-01040-0000.
3. Shake container well before using.
4. Spray or brush surfaces with smooth, even strikes. If spraying, hold nozzle
10-15 inches from work surface.
5. Cure time is ten minutes at room temperature.
I. Programmable Read Only Memory (PROM) Replacement

The read only memory packages are specially programmed devices to provide
specific logic outputs required for operation in the unit. The manufacturer’s part
(type) number is for the un-programmed device, and cannot be used. The Honey-
well part number must be used to obtain the correctly programmed device. Refer
to the “Illustrated Parts List” (IPL).
5.3.3.1 REPLACEMENT OF COMPONENTS

This section describes the procedure, along with any special techniques, for replacing damaged
or defective components.
A. Connectors
When replacing a connector, refer to the appropriate PC board assembly drawing,
and follow the notes, to ensure correct mounting and mating of each connector.
B. Crystal
The use of any crystal, other than a Honeywell crystal, is considered an unautho-
rized modification.
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B KT 73
C. Diodes
Diodes used are silicon and germanium. Use long-nose pliers as a heat sink, under
normal soldering conditions. Note the diode polarity before removal.
D. Integrated Circuits
Refer to the applicable reference for removal and replacement instructions.
E. Wiring/Coaxial Cable
When repairing a wire that has broken from its terminal, remove all old solder, and
pieces of wire from the terminal, re-strip the wire to the necessary length, and re-
solder the wire to the terminal. Replace a damaged wire or coaxial cable with one of
the same type, size and length.
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B KT 73
5.3.4 DISASSEMBLY/ASSEMBLY PROCEDURES

5.3.4.1 General
This section provides information for disassembly of the KT 73. Disassembly procedures are to
be accomplished only when repairs or modifications are required and only to the extent that is re-
quired by the repair or as directed in the modification service bulletin. This section contains the
recommended procedure for removal of all PC boards and subassemblies. Complete disassem-
bly should not normally be undertaken. Provisions have been made in the design of the unit to
make complete disassembly unnecessary except to replace a damaged mechanical part that can-
not be reached otherwise. Refer to the Illustrated Parts List (IPL) for aid in disassembly.
WARNING:
REMOVE POWER FROM THE KT 73 BEFORE
DISASSEMBLY OF ANY COMPONENT, PC
BOARD, OR SUBASSEMBLY. BESIDES BE-
ING DANGEROUS TO LIFE, VOLTAGE TRAN-
SIENTS CAN CAUSE CONSIDERABLE DAM-
AGE TO THE EQUIPMENT.
CAUTION:
VICES. ESDS DEVICES INCLUDE, BUT ARE
NOT LIMITED TO, C-MOS, J-MOS, PMOS,
NMOS, SOCMOS,HMOS, MOS/FET, MICRO-
WAVE MIXER DIODES, SOME BIPLOAR DE-
VICES, AND SOME METAL FILM RESIS-
TORS.
MOST DAMAGE TO ESDS DEVICES RE-

SULTS IN DEGRADED PERFORMANCE OR
PREMATURE FAILURE,NOT IN CATA-
STROPHIC FAILURE AT THE TIME EXPERI-
ENCED.
CAUTION:
EXERCISE EXTREME CARE WHEN DISCON-
NECTING AND RECONNECTING MULTI-PIN
CONNECTORS TO ENSURE THAT CONNEC-
TORS ARE NOT DAMAGED BY MISALIGN-
MENT OF PINS.
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B KT 73
5.3.4.2 Recommended Disassembly Procedures
NOTE:
View unit from front for determining left and right
sides. Tag, or by some means, identify all discon-
nected wires or coaxial cables.
NOTE:
On the KT 73 final assembly drawing (P/N 300-
09360-0000, the 073-00892-0001 right rail and heat
sink assembly is illustrated as part of the 200-09862-
0000 power supply assembly.
The 047-09543-00XX left side rail is illustrated as

part of the 200-05049-0003 chassis assembly.
The 047-09541-0002 rear rail is illustrated as part of

the 200-05049-0003 chassis assembly.
(1) Top Dust Cover Removal and Disassembly (Refer to drawing number 300-09360-
0000 and 300-05049-0000)
(a) Remove three fasteners (089-05901-0003) securing dust cover (047-09609-

0001) to right rail and heat sink (073-00892-0001).
(b) Rotate and remove three fasteners (089-05901-0003) securing dust cover
(047-09609-0001) to left side rail (047-09543-00XX).
(c) Remove one fastener (089-05901-0003) securing dust cover (047-09609-

0001) to rear rail (047-09541-0002).
(d) Remove one fastener (089-05901-0003) securing dust cover (047-09609-

0001) and power supply chassis (047-09588-0003) to swage spacer (076-
02234-0001) on main board (205-00914-XXXX).
(e) Lift dust cover (047-09609-0001) upward from rear of unit and slide toward
back of unit.
(f) Set dust cover aside.
(2) Bottom Cover Removal and Disassembly (Refer to drawing number 300-09360-
0000 and 300-05049-0000)
(a) Rotate unit and remove three fasteners (089-06006-0003) securing dust cov-
er (047-09587-0007) to right rail and heat sink (073-00892-0001).
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B KT 73
(b) Rotate and remove one fastener (089-06006-0003) securing dust cover (047-
09587-0007) to left side rail (047-09543-00XX) at the mounting hole nearest
the front of the unit.
(c) Remove two fasteners (089-06006-0003) securing dust cover (047-09587-

0007) to the transmitter housing (073-00878-0007).
(d) Rotate and remove four fasteners (089-06006-0004) securing dust cover
(e) Remove one fastener (089-05901-0003) securing dust cover (047-09587-

0001) to rear rail (047-09541-0002).
(f) Remove one fastener (089-05901-0004) securing dust cover (047-09587-

0001) to rear rail (047-09541-0002).
(g) Lift dust cover (047-09587-0001) upward from rear of unit and slide toward the
back of unit.
(h) Set dust cover aside.
(3) Front Panel Assembly Removal and Disassembly (Refer to drawing numbers 300-
09349-0000, 300-09360-0000, 300-05049-0000, and 300-09325-0020)
(a) Refer to paragraphs (1) and (2) for top and bottom cover removal as required.
(b) Remove two fasteners (089-06368-0003 securing the front panel assembly
(200-09349-0000) to right rail and heat sink (073-00892-0001).
(c) Rotate and remove two fasteners (089-06368-0003 securing the front panel
assembly (200-09349-0000) to left side rail (047-09543-00XX).
(d) Gently rock front panel assembly (200-09349-0000) from top to bottom while
pulling straight outward. This action will cause separation of front panel as-
sembly connector pins (display board 200-09325-0020), from main board
(205-00914-XXXX) connector (J3).
(e) Loosen eight set screws (089-06200-0004), two each per knob, and remove
the four knobs (073-01015-0005).
(f) Loosen three set screws (089-06200-0004) and remove one knob (073-
00998-0006).
(g) Rotate front panel assembly (200-09349-0000) and remove two fasteners
(089-05903-0005) and one fastener (089-05927-0010) securing display
board assembly (200-09325-0020) to bezel (200-09355-0000).
(h) Separate bezel from display board.
(i) If further disassembly is required, remove four fasteners (089-05899-0003).
(j) Remove foam carrier tape (016-01124-0001) from each side of the gas dis-
charge display (037-05107-0001).
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B KT 73
(k) Carefully pull gas discharge display (037-05107-0001) outward. This action
will cause separation of the display connector pins from 200-09325-00XX
connector J1.
(l) Carefully remove RTV (016-01082-0000) securing eight lamps DS1 - DS8
(037-00012-0014) to support bracket (088-02511-0004).
(m) Carefully remove RTV (016-01082-0000) securing LED DS19 (007-07008-

0001) to support bracket (088-02511-0004).
(n) Remove nut/washer hardware from switches SW1 - SW 5 (031-00759-0000).
(o) Separate the support bracket from the display board.
(4) Receiver Board Assembly Removal and Disassembly (Refer to drawing numbers
300-09360-0000, 300-05049-0000, and 300-08273-0020)
(a) Refer to paragraph (2) for bottom cover removal.
(b) Remove three (089-05901-0004) fasteners securing receiver board assembly

(c) Assembly including the receiver board, transmitter board, and modulator
board will now swing on the leaf hinges (047-09608-00XX).
(d) Disconnect the main board (205-00914-XXXX) ribbon cable (155-02654-

0000) connector (J5) from plug (P1), on modulator board (200-08274-0020).
(e) Disconnect the main board (205-00914-XXXX) ribbon cable (155-02654-

0001) connector (J4) from plug (P4) on receiver board assembly (200-08273-
0020).
(f) Remove two (089-06006-0003) fasteners securing the assembly to left rail
(047-09543-00XX).
(g) Remove two fastener (089-06006-0004) securing the assembly to rear rail
(047-09541-0002). Leaf hinge (047-09608-0001) will be removed as well.
(h) Remove the assembly including the receiver board, transmitter board, and
modulator board which is now separate from the rest of the unit.
(i) Remove three fasteners (089-05901-0004) securing receiver board assembly

(200-08273-0000) to transmitter housing (073-00878-0007). Leaf hinge (047-
09608-0000) will be removed as well.
(l) Remove two screws (089-06368-0003) from preselector shield cover (047-
12775-0004).
(k) Remove one screw (089-05901-0003) from preselector shield cover (047-
12775-0004).
(l) Remove preselector shield cover (047-12775-0004).
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B KT 73
(m) Unsolder transmitter board (200-08275-0040) coaxial cable (024-00074-

0000) from receiver board assembly (200-08273-0020).
(n) Receiver board assembly (200-08273-0020) can now be removed.
(o) Remove fences, shields, and covers as necessary to access components.

Refer to sheet 3 of 300-08273-0020 for additional information.
(p) If necessary, remove two screws (089-05901-0004) and remove leaf hinge
(075-05097-0001). Leaf hinge (047-09608-0002) will be removed as well.
(5) Modulator Board Assembly Removal and Disassembly (Refer to drawing numbers
300-09360-0000, 300-05049-0000, 300-08273-0020, and 300-08274-0020)
(a) Refer to paragraph (4), steps (a) through (d). If removal of entire assembly
including receiver, modulator and transmitter assemblies is desired, perform
steps paragraph (4), steps (a) through (i).
(b) Unsolder six (from transmitter board 200-08275-0040) connections (E1

through E6) on modulator board (200-08274-0020).
(c) Remove six fasteners (089-05901-0003) securing modulator board (200-

08274-0020) to transmitter housing (073-00878-0007).
(d) Remove four fasteners (089-05903-0004), bushings (091-00156-0000) and

insulators (091-00286-0002) securing four modulator board (200-08274-
0020) transistors (Q2, Q3, Q6, Q10) to transmitter housing (073-00878-0007).
(e) Modulator board assembly (200-08274-0020) may now be removed.
(6) Transmitter Board Assembly Removal and Disassembly (Refer to drawing numbers
300-09360-0000, 300-05049-0000, 300-08273-0020, 300-08274-0020 and 300-
08275-0040)
(a) Refer to paragraph (5).
(b) Remove eight fasteners (089-06006-0003) securing shield (047-12625-0003)

to transmitter housing (073-00878-0007).
(c) Unsolder coaxial cable (024-00074-0000) from connection points; center wire
from E8 and shield from E9 and withdraw cable through holes in fence/bracket
(047-12680-0002) and transmitter housing (073-00878-0007).
(d) Transmitter board assembly 200-08275-0040) including transmitter housing

(073-00878-0007) may now be removed.
(e) If necessary, remove four fasteners (089-05523-0003), two each from transis-
tor Q1 and two each from transistor Q2, ensuring that lock washers (089-
08109-0034) and flat washers (089-08158-0004) remain with each fastener.
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B KT 73
(f) If necessary, remove two fasteners (089-06006-0002) and two fasteners

(089-06006-0003) securing shield (047-12698-0003) to transmitter housing
(073-00878-0007).
(7) Main Board Assembly Removal and Disassembly (Refer to drawing numbers 300-
09360-0000, 300-05049-0000, 300-08273-0020, and 300-09321-0000)
(a) Refer to paragraph (3), steps (a) through (d).
(b) Refer to paragraph (4), steps (b) through (h) as required.
(c) Remove two fasteners (089-05901-0004) securing main board (205-00914-

XXXX) to right rail and heat sink (073-00892-0001).
(d) Rotate unit and remove three fasteners (089-05901-0003) securing main
board (205-00914-XXXX) to left side rail (047-09543-00XX).
(e) Remove two fasteners (089-05901-0003) securing main board (205-00914-

XXXX) to rear rail (047-09541-0002).
(f) Remove one fastener (089-06006-0004) securing main board (205-00914-

(g) Carefully separate the Main board connector J2 from the power supply board
connector P1 and remove the Main board (205-00914-XXXX).
(h) Remove top (047-09574-0001) and bottom (047-09576-0001) fence covers

as required by removing two fasteners (089-06004-0002) per cover.
(8) Power Supply Board Assembly Removal and Disassembly (Refer to drawing num-
bers 300-09360-0000, 300-05049-0000, 300-08273-0020 and 300-09862-0000)
(a) Refer to paragraph (1) for top cover removal.
(b) Refer to paragraph (4), (a) through (c).
(c) Remove four fasteners (089-06006-0004) and remove power supply cover
(047-09589-0001).
(d) Remove two standoffs (076-02232-0001 and lock washers (089-08109-0034)

from power supply board (200-09862-0000).
(e) Remove one fastener (089-05901-0003) from power supply chassis (047-
09588-0003) and remove chassis.
(f) Remove two fasteners (089-05901-0004) attaching power supply board (200-
09862-0000) to right rail and heat sink (073-00892-0001).
(g) Remove four fasteners (089-05903-0004) and bushings (091-00156-0000)

from Q1, Q6, Q8, and U6. Ensure that transistor bushings and insulators
(091-00286-0002) are saved for replacement.
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B KT 73
(h) Remove one fastener (089-05903-0004) from U7.
(i) If the main board is not already removed, lift power supply board (200-09862-
0000) upward. This action will separate connector pins (P1) from the main
board connector (J2).
(j) Power supply board (200-09862-0000) is now removed.
(9) Optional External EEPROM Board (External Configuration Module) Assembly Re-
moval and Disassembly (Refer to drawing numbers 300-09360-0000, 300-10069-
0000, and 300-09889-0010)
(a) Grasp unit pull outward from mounting rack (047-12768-0005). Radio remov-
al tool (071-06045-0000) may be used as an aid in this task.
(b) Remove two fasteners (089-05903-0007) securing EEPROM board (200-

09889-0010) to mounting rack (047-12768-0005).
(c) Remove EEPROM board (200-09889-0010).
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B KT 73
5.3.4.3 Recommended Assembly Procedures

This section provides procedures for assembly of the KT 73. Assembly procedure are to be fol-
lowed after the unit has been disassembled for repair, cleaning, inspection, or modification by ser-
vice bulletin.
The following table lists materials used in assembly of the unit. Equivalent substitutes may be
used for listed sealants, staking compounds, and thermal compounds.
REPRESENTATIVE TYPE QUANTITY USED

Loctite 425 Thin coat to threads of screws and retaining
nuts
Conformal Coating Humiseal #1B-31 Thin coats on all components, not on connec-
HYSOL PC 20-35M-01 tors
Adhesive-Sealant RTV 3145 Thin coat for adhesion
Thermal Compound Thin coat on power transistor insulator (both
sides)
Nylon Cable Tie As required to secure wiring
Solder, 60% Tin 40% Lead As required for connections
TABLE 5-4
SEALANTS AND STAKING COMPOUNDS
WARNING:
REMOVE ALL POWER FROM UNIT BEFORE
ASSEMBLY OF ANY MODULE. VOLTAGE
TRANSIENTS ARE DANGEROUS TO LIFE.
VOLTAGE TRANSIENTS CAN DAMAGE THE
EQUIPMENT.
CAUTION:
EXERCISE EXTREME CARE WHEN DISCON-
NECTING AND RECONNECTING MULTI-PIN
CONNECTORS TO ENSURE THAT CONNEC-
TORS ARE NOT DAMAGED BY MISALIGN-
MENT OF PINS.
Rev. 1, May/2003 15563M01.JA Page 5-55

B KT 73
CAUTION:
VICES. ESDS DEVICES INCLUDE, BUT ARE
NOT LIMITED TO, C-MOS, J-MOS, PMOS,
NMOS, SOCMOS,HMOS, MOS/FET, MICRO-
WAVE MIXER DIODES, SOME BIPLOAR DE-
VICES, AND SOME METAL FILM RESIS-
TORS.
MOST DAMAGE TO ESDS DEVICES RE-

SULTS IN DEGRADED PERFORMANCE OR
PREMATURE FAILURE,NOT IN CATA-
STROPHIC FAILURE AT THE TIME EXPERI-
ENCED.
NOTE:
View unit from front for determining left and right
sides.
NOTE:
On the KT 73 final assembly drawing (P/N 300-
09360-0000, the 073-00892-0001 right rail and heat
sink assembly is illustrated as part of the 200-09862-
0000 power supply assembly.
The 047-09543-00XX left side rail is illustrated as

part of the 200-05049-0003 chassis assembly.
The 047-09541-0002 rear rail is illustrated as part of

the 200-05049-0003 chassis assembly.
(1) Top Dust Cover Assembly (Refer to drawing number 300-09360-0000 and 300-
05049-0000)
(a) Install dust cover (047-09609-0001) on unit.
(b) Install one fastener (089-05901-0003) securing dust cover (047-09609-0001)

and power supply chassis (047-09588-0003) to swage spacer (076-02234-
0001) on main board (205-00914-XXXX).
(c) Install one fastener (089-05901-0003) securing dust cover (047-09609-0001)

to rear rail (047-09541-0002).
(d) Rotate and install three fasteners (089-05901-0003) securing dust cover
Rev. 1, May/2003 15563M01.JA Page 5-56

B KT 73
(e) Install three fasteners (089-05901-0003) securing dust cover (047-09609-

0001) to right rail and heat sink (073-00892-0001).
(2) Bottom Cover Assembly (Refer to drawing number 300-09360-0000 and 300-
05049-0000)
(a) Install dust cover (047-09587-0001) on unit.
(b) Install one fastener (089-05901-0004) securing dust cover (047-09587-0001)

to rear rail (047-09541-0002).
(c) Install one fastener (089-05901-0003) securing dust cover (047-09587-0001)

to rear rail (047-09541-0002).
(d) Rotate and install four fasteners (089-06006-0004) securing dust cover (047-
09587-0007) to left side rail (047-09543-00XX).
(e) Install two fasteners (089-06006-0003) securing dust cover (047-09587-

0007) to the transmitter housing (073-00878-0007).
(f) Rotate and install one fastener (089-06006-0003) securing dust cover (047-
09587-0007) to left side rail (047-09543-00XX) at the mounting hole nearest
the front of the unit.
(g) Rotate unit and install three fasteners (089-06006-0003) securing dust cover
(3) Front Panel Assembly (Refer to drawing numbers 300-09349-0000, 300-09360-

0000, 300-05049-0000, and 300-09325-0020)
(a) Connect the support bracket (088-02511-0004) to the display board (200-
09325-0020).
(b) Install nut/washer hardware on switches SW1 - SW 5 (031-00759-0000).
(c) Install four fasteners (089-05899-0003) attaching the support bracket (088-
02511-0004) to the display board (200-09325-0020).
(d) Install foam carrier tape (016-01124-0001) on each side of the gas discharge
display (037-05107-0001).
(e) Connect gas discharge display (037-05107-0001) connector pins to 200-

09325-00XX connector J1.
(f) Secure LED DS19 (007-07008-0001) to support bracket (088-02511-0004)

with RTV (016-01082-0000) per 300-09325-0020 note 8.
(g) Secure eight lamps DS1 - DS8 (037-00012-0014) to support bracket (088-
02511-0004) with RTV (016-01082-0000) per 300-09325-0020 note 9.
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B KT 73
(h) Install two fasteners (089-05903-0005) and one fastener (089-05927-0010)

securing display board assembly (200-09325-0020) to bezel (200-09355-
0000).
(i Install one knob (073-00998-0006) and tighten three set screws (089-06200-
0004).
(j) Install four knobs (073-01015-0005) and tighten eight set screws (089-06200-
0004), two each per knob.
(k) Install front panel assembly connector pins (on display board 200-09325-
0020) to main board (205-00914-XXXX) connector (J3).
(l) Install two fasteners (089-06368-0003 securing the front panel assembly
(m) Install two fasteners (089-06368-0003 securing the front panel assembly
(n) Refer to paragraphs (1) and (2) for top and bottom cover installation as appli-
cable.
(4) Receiver Board Assembly (Refer to drawing numbers 300-09360-0000, 300-05049-

0000, and 300-08273-0020)
NOTE:
If any of the aluminum tape applied to the receiver
board is removed for any reason, replace with new
tape per the aluminum tape application instructions
on assembly drawing 300-08273-0020. Do not at-
tempt to reuse the original tape.
(a) If removed, install leaf hinges (075-05097-0001) and (047-09608-0002) and

install two screws (089-05901-0004).
(b) Install fences, shields, and covers as necessary. Refer to sheet 3 of 300-
08273-0020 for additional assembly information.
(c) Solder transmitter board (200-08275-0040) coaxial cable (024-00074-0000)

to receiver board assembly (200-08273-0020) per 300-09360-0000 detail A.
(d) Install preselector shield cover (047-12775-0004).
(e) Install one screw (089-05901-0003) on preselector shield cover (047-12775-

0004).
(f) Install two screws (089-06368-0003) on preselector shield cover (047-12775-

0004).
(g) Install leaf hinge (047-09608-0000) and align transmitter housing (073-00878-
0007) in receiver board assembly (200-08273-0000).
(h) Install three fasteners (089-05901-0004) securing transmitter housing (073-

00878-0007) to receiver board assembly (200-08273-0000).
Rev. 1, May/2003 15563M01.JA Page 5-58

B KT 73
(i) Install leaf hinge (047-09608-0001) in the assembly that includes the receiver
board, transmitter board, and modulator board and align to the rest of the unit
at the rear and left rails.
(j) Install two fasteners (089-06006-0004) securing the assembly and rear leaf
hinge to the rear rail (047-09541-0002).
(k) Install one (089-06006-0003) fastener securing the assembly, including the
center leaf hinge (047-09608-0000) to the left rail (047-09543-00XX) per the
note below.
(l) Install one (089-06006-0003) fastener securing the assembly, including the
front leaf hinge (089-06006-0000) to the left rail (047-09543-00XX) per the
note below.
NOTE:
The second attachment to the front and center leaf
hinges occurs during the bottom cover assembly.
Ensure that the fasteners installed in the previous
steps are installed properly to accommodate the bot-
tom cover assembly (see 300-05049-0000 for clari-
ty).
(m) Assembly including the receiver board, transmitter board, and modulator
board will now swing on the leaf hinges (047-09608-00XX).
(n) Connect main board (205-00914-XXXX) ribbon cable (155-02654-0001) con-

nector (J4) to plug (P4) on receiver board assembly (200-08273-0020).
(o) Connect main board (205-00914-XXXX) ribbon cable (155-02654-0000) con-

nector (J5) to plug (P1) on modulator board (200-08274-0020).
(p) Hinge closed the assembly and install three (089-05901-0004) fasteners se-
curing it to the right rail and heat sink (073-00892-0001).
(q) Refer to paragraph (2) for bottom cover installation.
(5) Modulator Board Assembly (Refer to drawing numbers 300-09360-0000, 300-

05049-0000, 300-08273-0020, and 300-08274-0020)
(a) Install Modulator board (200-08274-0020) on transmitter housing (073-

00878-0007).
(b) Install four fasteners (089-05903-0004), bushings (091-00156-0000) and in-

sulators (091-00286-0002) securing four modulator board (200-08274-0020)
transistors (Q2, Q3, Q6, Q10) to transmitter housing (073-00878-0007).
(c) Install six fasteners (089-05901-0003) securing modulator board (200-08274-

0020) to transmitter housing (073-00878-0007).
(d) Solder six (from transmitter board 200-08275-0040) connections (E1 through
E6) on modulator board (200-08274-0020).
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B KT 73
(e) Refer to paragraph (4), steps (o) through (q). If entire assembly, including re-
ceiver, modulator and transmitter assemblies, is removed, perform paragraph
(4), steps (g) through (q) as required.
(6) Transmitter Board Assembly (Refer to drawing numbers 300-09360-0000, 300-

05049-0000, 300-08273-0020, 300-08274-0020 and 300-08275-0040)
(a) If removed, install two fasteners (089-06006-0002) and two fasteners (089-
06006-0003) securing shield (047-12698-0003) to transmitter housing (073-
00878-0007).
(b) If removed, install four fasteners (089-05523-0003), two each from transistor
Q1 and two each from transistor Q2, including lock washers (089-08109-
0034) and flat washers (089-08158-0004).
(c) Run coaxial cable (024-00074-0000) through holes in fence/bracket (047-

12680-0002) and transmitter housing (073-00878-0007).
(d) Solder coaxial cable (024-00074-0000) at connection points; center wire to

E8 and shield to E9.
(e) Install eight fasteners (089-06006-0003) securing shield (047-12625-0003) to

transmitter housing (073-00878-0007).
(f) Refer to paragraph (5).
(7) Main Board Assembly (Refer to drawing numbers 300-09360-0000, 300-05049-

0000, 300-08273-0020, and 300-09321-0000)
(a) If removed, install top (047-09574-0001) and bottom (047-09576-0001) fence

covers and install two fasteners (089-06004-0002) per cover.
(b) Install the Main board (205-00914-XXXX) by connecting Main board connec-
tor J2 to power supply board connector P1.
(c) Install one fastener (089-06006-0004) securing main board (205-00914-

(d) Install two fasteners (089-05901-0003) securing main board (205-00914-

XXXX) to rear rail (047-09541-0002).
(e) Rotate unit and install three fasteners (089-05901-0003) securing main board
(205-00914-XXXX) to left side rail (047-09543-00XX).
(f) Install two fasteners (089-05901-0004) securing main board (205-00914-

(g) Refer to paragraph (4), steps (g) through (q) as required.
(h) Refer to paragraph (3), steps (k) through (n).
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B KT 73
(8) Power Supply Board Assembly (Refer to drawing numbers 300-09360-0000, 300-
05049-0000, 300-08273-0020 and 300-09862-0000)
(a) Install power supply board (200-09862-0000) connecting pins (P1) to the
main board connector (J2), if main board is installed.
(c) Install one fastener (089-05903-0004) on U7.
(d) Install four fasteners (089-05903-0004), bushings (091-00156-0000), and in-

sulators (091-00286-0002) on Q1, Q6, Q8, and U6.
(e) Install two fasteners (089-05901-0004) attaching power supply board (200-
09862-0000) to right rail and heat sink (073-00892-0001).
(f) Place power supply chassis (047-09588-0003) and attach one fastener (089-
05901-0003) to chassis.
(g) Install two standoffs (076-02232-0001 and lock washers (089-08109-0034) to

power supply board (200-09862-0000).
(h) Place power supply cover (047-09589-0001) and install four fasteners (089-
06006-0004).
(i) Hinge closed the assembly including the receiver board, transmitter board,
and modulator board and install three (089-05901-0004) fasteners securing it
to the right rail and heat sink (073-00892-0001).
(j) Refer to paragraph (1) for top cover installation.
(k) Refer to paragraph (2) for bottom cover installation.
(9) Optional External EEPROM Board Assembly (External Configuration Module) (Re-
fer to drawing numbers 300-09360-0000, 300-10069-0000, and 300-09889-0010)
(a) Install EEPROM board (200-09889-0010).
(b) Install two fasteners (089-05903-0007) securing EEPROM board (200-

09889-0010) to mounting rack (047-12768-0005).
(c) Install KT 73 into mounting rack (047-12768-0005).
5.4 TROUBLESHOOTING
This section is intended for use as a guide in isolating circuit malfunctions. The guidance present-
ed here and the figures referenced by no means profess to include all possible causes of failure,
but are presented as a guideline to be used in locating the approximate section of the unit that has
failed.
5.4.1 TROUBLESHOOTING PROCEDURES
Troubleshooting information for the KT 73 is mainly contained in the fault codes and troubleshoot-
ing procedures. The troubleshooting procedures are for use as deemed necessary, when ever a
unit fails to meet the performance requirements of the functional test procedure in the Testing
paragraphs of this section.
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B KT 73
Alignment procedures are to be used after misalignment has been isolated by the use of the trou-
bleshooting flow charts, and/or other troubleshooting techniques, and to adjust levels to customer
specification.
CAUTION:
PROCEDURES.
5.4.2 TEST SETUP
(1) Refer to paragraph 5.2.1 of this manual for information on test equipment required
for testing this unit. Refer to the diagram, Figure 5-1 for equipment set-up.
(2) Preliminary Test Equipment Checkout, Test Setup, and Turn On.
In general, entry into the troubleshooting procedures is from the Testing paragraph.
The test equipment should have been properly checked out, setup, and turned on
prior to entry into troubleshooting. To recheck the test equipment or setup, refer to
paragraph 5.2.3 in this section for the procedures.
5.4.3 TROUBLESHOOTING PROCEDURES
The correct troubleshooting procedure is determined by the type of failure in the functional test
procedure. The KT 73 is equipped for minimal self-testing and should be used in conjunction with
the troubleshooting flow chart or similar detailed troubleshooting procedures. This method pro-
vides general guidelines for locating faults to the assembly level. The technicians should then use
traditional troubleshooting methods to isolate to the component level. Schematic diagrams and
theory of operation are provided to assist troubleshooting to the component level.
After the faulty area is isolated by the troubleshooting procedure, and repair is made, the unit
should be retested using the functional test procedure in the Return To Service paragraphs of this
manual.
5.4.4 FAULT CODES
Within the KT 73 unit, a fault annunciator display on the altitude window display will display the
number of a faulty circuit module. The assigned fault numbers and description are listed in Section
III of the KT 73 installation manual.
The fault codes do not isolate faults to all modules within the transponder, but it is recommended
that the fault codes be used as a first step in troubleshooting.
After noting the failed functional test and the faulty module indicated by the fault annunciator dis-
play, the appropriate troubleshooting diagram and/or schematic should be referenced to further
troubleshoot the faulty circuit module. After repair and reinsertion of the circuit module, the KT 73
should be checked again for another faulty circuit module. When all the circuit modules have been
repaired and reinserted, the functional test should be performed to assure the KT 73 is again op-
erating satisfactorily.
5.4.5 TROUBLESHOOTING WAVEFORMS
The following troubleshooting waveforms are provided as a troubleshooting aid and are refer-
enced from the troubleshooting flowcharts detailed in section 5.4.6. The waveforms depicted be-
low illustrate a typical waveform in a satisfactorily functioning unit.
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B KT 73
FIGURE 5-8 WAVEFORM 1
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B KT 73
5.4.6 TROUBLESHOOTING FLOWCHARTS

Figures 5-54 through 5-60 provides a flow chart procedure for fault isolation to a likely circuit mod-
ule.
The test setup and test equipment require for troubleshooting are given in Figure 5-1. The initial
test conditions for troubleshooting are specified at the beginning of the functional test procedure
(paragraph 5.2.3.3 of this section). The flow chart troubleshooting procedure is begun when either
the KT 73 unit fails any part of the functional test or the fault number of a fault circuit is displayed
on the fault annunciator display (altitude display window) on the front panel.
If the KT 73 under test contains more than one fault, the fault with the highest priority will be dis-
played. When that fault has been corrected, return to sheet one of the troubleshooting procedure.
The next highest priority will then be displayed. The newly displayed fault is isolated by using the
appropriate branch of the flow chart. After all the faulty circuit modules have been repaired and
reinserted, the functional test should be performed to assure the KT 73 is operating satisfactorily.
CAUTION:
TURN OFF POWER BEFORE MAKING ANY
DISCONNECTIONS OR CONNECTIONS AND
BEFORE REMOVING OR REINSERTING PC
MODULES.
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B KT 73
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B KT 73
FIGURE 5-54 TROUBLESHOOTING FLOW CHART

KT 73 UNIT
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B KT 73
FIGURE 5-55 TROUBLESHOOTING FLOW CHART

POWER SUPPLY BOARD
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B KT 73
FIGURE 5-56 KT 73 TROUBLESHOOTING FLOW CHART

DISPLAY BOARD (Sheet 1 of 2)
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B KT 73

DISPLAY BOARD (Sheet 2 of 2)
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B KT 73

RECEIVER BOARD (Sheet 1 of 3)
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B KT 73

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B KT 73

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B KT 73

MAIN BOARD (Sheet 1 of 3)
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B KT 73

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B KT 73

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B KT 73

FPGA
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B KT 73

MODULATOR/TRANSMITTER BOARD
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B KT 73
SECTION VI
ILLUSTRATED PARTS LIST
6.1 GENERAL
The Illustrated Parts List (IPL) is a complete list of assemblies and parts required
for the unit. The IPL also provides for the proper identification of replacement
parts. Individual parts lists within this IPL are arranged in numerical sequence
starting with the top assembly and continuing with the sub-assemblies. All me-
chanical parts will be separated from the electrical parts used on the sub-assembly.
Each parts list is followed by a component location drawing.
Parts identified in this IPL by Honeywell part number meet design specifications for
this equipment and are the recommended replacement parts. Warranty informa-
tion concerning Honeywell replacement parts is contained in Service Memo #1,
P/N 600-08001-00XX.
Some part numbers may not be currently available. Consult the current Honeywell
catalog or contact a Honeywell representative for equipment availability.
6.2 REVISION SERVICE
The manual will be revised as necessary to reflect current information.
6.3 LIST OF ABBREVIATIONS
Abbreviation Name
B Motor or Synchro
C Capacitor
CJ Circuit Jumper
CR Diode
DS Lamp
E Voltage or Signal Connect Point
F Fuse
FL Filter
FT Feedthru
I Integrated Circuit
J Jack or Fixed Connector
L Inductor
M Meter
P Plug
Q Transistor
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B KT 73
Abbreviation Name
R Resistor
RT Thermistor
S Switch
T Transformer
TP Test Point
U Component Network, Integrated Circuit,
Circuit Assembly
V Photocell/Vacuum Tube
W Waveguide
Y Crystal
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B KT 73
6.4 SAMPLE PARTS LIST
The above is only a sample. The actual format and style may vary slightly. A ‘Find
Number’ column, when shown, references selected items on the BOM’s accompa-
nying Assembly Drawing. This information does not apply to every BOM. There-
fore, a lack of information in this column, or a lack of this column, should not be
interpreted as an omission.
Figure 6-1
Sample Parts List
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B KT 73
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B KT 73
6.5 KT 73 FINAL ASSEMBLY
066-01164-0101 FINAL BILL OF MATERIAL, KT73 Rev. F

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0101
---------------------------------------------------------------
000-01007-0000 PRODUCT STRUCTURE, RF .00
004-02148-4000 MINIMUM PERFORMANC RF .00
011-07000-0001 ALUMINUM TAPE 2 IN IN 2.90
012-01005-0002 TAPE MYLAR .500 W IN 2.63
047-09587-0007 COVER BOTTOM EA 1.00
047-09588-0003 P/S CHASSIS EA 1.00
047-09589-0001 POWER BD COVER EA 1.00
047-09609-0001 TOP COVER KT 70 EA 1.00
047-12775-0004 PRESELECT SHIELD W EA 1.00
047-12842-0004 SHIELD, ASSY EA 1.00
057-01540-0000 WARNING HV TAG EA 2.00
057-02203-0001 FLAVOR STCKR EA 2.00
057-03511-0001 DECAL, CAUTION EA 1.00
057-05367-0000 AIRCRAFT IDENT TAG EA 1.00
057-05893-0001 S/N TAG , KT 73 EA 1.00
075-05097-0001 HINGE LEAF EA 1.00
076-02232-0001 STANDOFF EA 2.00
076-02233-0001 SPACER EA 2.00
089-05901-0003 SCR PHP 3-48X3/16 EA 15.00
089-05901-0004 SCR PHP 3-48X1/4 EA 11.00
089-06006-0003 SCR FHP 3-48X3/16 EA 8.00
089-06006-0004 SCR FHP 3-48X1/4 EA 9.00
089-06368-0003 SCR FHP 4-40X3/16 EA 4.00
089-08109-0034 WSHR SPLT LK #4 EA 2.00
090-00960-0000 FINGERSTOCK EA .20
090-00991-0000 PROTECTIVE CLOSURE EA 1.00
200-05049-0003 KT 73 CHASSIS ASSE EA 1.00
200-08273-0020 KT 73 RECEIVER BD EA 1.00
200-09349-0000 B.O.M. FRONT PANEL EA 1.00
200-09862-0000 KT 73 POWER SUPPLY EA 1.00
200-10069-0000 MOUNTING RACK EA 1.00
206-00387-0102 SOFTWARE SET, KT73 EA 1.00
300-09360-0000 FINAL ASSEMBLY, KT RF .00
Rev. 1, May/2003 15563M01.JA Page 6-5

B KT 73
NOTE: The following is a parts list from a previous manual revision and is
provided for reference only.
066-01164-0101 FINAL BILL OF MATERIAL, KT73 Rev. E

---------------------------------------------------------------
---------------------------------------------------------------
000-01007-0000 PRODUCT STRUCTURE, RF .00
004-02148-4000 MINIMUM PERFORMANC RF .00
012-01005-0002 TAPE MYLAR .500 W IN 2.63
047-09587-0007 COVER BOTTOM EA 1.00
047-09588-0003 P/S CHASSIS EA 1.00
047-09589-0001 POWER BD COVER EA 1.00
047-09609-0001 TOP COVER KT 70 EA 1.00
047-12775-0004 PRESELECT SHIELD W EA 1.00
047-12842-0004 SHIELD, ASSY EA 1.00
057-01540-0000 WARNING HV TAG EA 2.00
057-02203-0001 FLAVOR STCKR EA 2.00
057-03511-0001 DECAL, CAUTION EA 1.00
057-05367-0000 AIRCRAFT IDENT TAG EA 1.00
057-05893-0001 S/N TAG , KT 73 EA 1.00
075-05097-0001 HINGE LEAF EA 1.00
076-02232-0001 STANDOFF EA 2.00
076-02233-0001 SPACER EA 2.00
089-05901-0003 SCR PHP 3-48X3/16 EA 15.00
089-05901-0004 SCR PHP 3-48X1/4 EA 11.00
089-06006-0003 SCR FHP 3-48X3/16 EA 8.00
089-06006-0004 SCR FHP 3-48X1/4 EA 9.00
089-06368-0003 SCR FHP 4-40X3/16 EA 4.00
089-08109-0034 WSHR SPLT LK #4 EA 2.00
090-00960-0000 FINGERSTOCK EA .20
090-00991-0000 PROTECTIVE CLOSURE EA 1.00
200-05049-0003 KT 73 CHASSIS ASSE EA 1.00
200-08273-0020 KT 73 RECEIVER BD EA 1.00
200-09349-0000 B.O.M. FRONT PANEL EA 1.00
200-10069-0000 MOUNTING RACK EA 1.00
206-00387-0101 SOFTWARE SET, KT73 EA 1.00
300-09360-0000 FINAL ASSEMBLY, KT RF .00
Rev. 1, May/2003 15563M01.JA Page 6-6

B KT 73
FIGURE 6-2 KT 73 FINAL ASSEMBLY

(Dwg. No. 300-09360-0000 R-H, Sheet 1 of 3)
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B KT 73

(Dwg. No. 300-09360-0000 R-H, Sheet 2 of 3
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B KT 73

(Dwg. No. 300-09360-0000 R-H, Sheet 3 of 3)
Rev. 1, May/2003 15563M01.JA Page 6-11

B KT 73
6.6 KT 73 CHASSIS ASSEMBLY
200-05049-0003 KT 73 CHASSIS ASSEMBLY Rev. A

---------------------------------------------------------------
---------------------------------------------------------------
REF1 300-05049-0000 CHASSIS ASSEMBLY RF .00
047-09541-0002 REAR RAIL EA 1.00
047-09543-0002 LEFT SIDE RAIL EA 1.00
047-09608-0000 LEAF HINGE W/PIN EA 1.00
089-05901-0003 SCR PHP 3-48X3/16 EA 6.00
089-05903-0004 SCR PHP 4-40X1/4 EA 4.00
089-06006-0003 SCR FHP 3-48X3/16 EA 3.00
089-06006-0004 SCR FHP 3-48X1/4 EA 2.00
091-00156-0000 BUSHING EA 4.00
091-00286-0002 INSUL XSTR .687 EA 4.00
200-08274-0020 MODULATOR BOARD EA 1.00
200-08275-0040 KT 73 TRANSMITTER EA 1.00
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B KT 73
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B KT 73
FIGURE 6-3 KT 73 CHASSIS ASSEMBLY

(Dwg. No. 300-05049-0000 R-AE)
Rev. 1, May/2003 15563M01.JA Page 6-15

B KT 73
6.7 KT 73 TRANSMITTER BOARD
200-08275-0040 KT 73 TRANSMITTER BOARD Rev. D

---------------------------------------------------------------
---------------------------------------------------------------
C1 106-00044-0054 CAP CH 12PF 5% EA 1.00
C10 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C11 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C12 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C13 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C14 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C15 106-00044-0016 CAP CHIP 3.3PF500V EA 1.00
C16 106-00044-0016 CAP CHIP 3.3PF500V EA 1.00
C17 111-00001-0009 CAP CR .15UF 100V EA 1.00
C18 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C19 106-04331-0026 CAPCH330PFNPO/100V EA 1.00
C2 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C20 106-05470-0026 CAP CH47PFNPO/100V EA 1.00
C21 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C22 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C23 106-05829-0020 CH 8.2PF NPO 100V EA 1.00
C24 106-00044-0009 CAP CHIP 3.9PF500V EA 1.00
C25 106-00128-0000 CAP FEEDTHRU 1KPF EA 1.00
C28 106-00123-0000 EMI FLTR FEEDTHRU EA 1.00
C30 106-00044-0016 CAP CHIP 3.3PF500V AR 1.00
C31 106-00074-0023 CAP PF 2.7 500VDC EA 1.00
C32 106-00127-0000 CAP FT 100PF 8-36 EA 1.00
C4 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C5 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C6 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C7 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C8 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C9 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
CR1 007-06418-0000 PIN DIODE EA 1.00
CR2 007-06179-0000 DIO SI MMBD501 EA 1.00
CR3 007-06418-0000 PIN DIODE EA 1.00
FL1 017-00293-0001 CERAMIC FILTER, 10 EA 1.00
JKT703 030-00152-0000 CONN BNC HEX EA 1.00
L1 019-02400-0020 COIL 4 T EA 1.00
L2 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L3 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L4 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L5 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L6 019-02400-0023 COIL 3TX0.110 EA 1.00
L7 019-02400-0020 COIL 4 T EA 1.00
L8 019-02400-0020 COIL 4 T EA 1.00
L9 013-00038-0003 FERRITE BEAD EA 1.00
Q1 007-00922-0000 300W MODE S NPN RF EA 1.00
Q2 007-01308-0001 XTRS 300 WATTS, MO EA 1.00
R1 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R10 139-20392-0020 RES CH 3.92OHM QW EA 1.00
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B KT 73
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---------------------------------------------------------------
R11 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R2 139-00000-0004 RES CH 0 EW EA 1.00
R3 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R4 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R5 139-01500-0000 RES CH 150 EW 1% EA 1.00
R6 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R7 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R8 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R9 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
W1 015-00218-0000 CPLR 6DB 1090MHZ EA 1.00
002-08275-0040 KT 73 TRANSMITTER RF .00
009-08275-0041 KT 73 TRANSMITTER EA 1.00
016-01007-0005 LOCTITE 222 AR 1.00
016-01415-0000 SOLDER PREFORM AR 1.00
016-01426-0000 HI FREQ COAT 2577 AR 1.00
019-02705-0000 ELEMENT LP FILTER EA 1.00
019-02709-0000 SHIMSTK JMPR EA 2.00
024-00074-0000 COAX SEMI-FLEX RG- FT .38
024-05021-0005 COPPER STRAP .187 AR 1.00
024-05021-0006 STRAP COPPER .035 IN 1.00
026-00027-0000 WIRE, CU, 18AWG, T IN 1.00
026-00028-0000 WIRE, CU, 20AWG, T IN .75
047-09661-0001 RESONATOR BRKT EA 1.00
047-09676-0001 COVER LPF KT 70 EA 1.00
047-09771-0001 COVER EA 1.00
047-12625-0003 COVER W/FINGERSTOC EA 1.00
047-12680-0002 PART W / FINISH EA 1.00
047-12681-0002 PART W/FINISH EA 1.00
047-12698-0003 COVER W/FINGER STO EA 1.00
073-00878-0007 TRANSMITTER HOUSIN EA 1.00
076-02235-0001 TUNING SLEEVE EA 1.00
088-02559-0000 INSULATOR EA 1.00
089-05523-0003 SCR FLHP 4-40X3/16 EA 4.00
089-05857-0012 SCR SET 4-40X3/8 EA 1.00
089-06006-0002 SCR FHP 3-48 X 1/ EA 2.00
089-06006-0003 SCR FHP 3-48X3/16 EA 10.00
089-08109-0034 WSHR SPLT LK #4 EA 4.00
089-08158-0004 WASHER EA 4.00
300-08275-0040 KT 73 TRANSMITTER RF .00
Rev. 1, May/2003 15563M01.JA Page 6-18

B KT 73
FIGURE 6-4 KT 73 TRANSMITTER BOARD

(Dwg. No. 300-08275-0040 R-C, Sheet 1 of 2)
Rev. 1, May/2003 15563M01.JA Page 6-19

B KT 73
FIGURE 6-4 KT 73 TRANSMITTER BOARD

(Dwg. No. 300-08275-0040 R-C, Sheet 2 of 2)
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B KT 73
FIGURE 6-5 KT 73 TRANSMITTER BOARD SCHEMATIC

(Dwg. No. 002-08275-0040 R-B)
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B KT 73
6.8 KT 73 MODULATOR BOARD
200-08274-0020 MODULATOR BOARD Rev. G

---------------------------------------------------------------
---------------------------------------------------------------
C1 097-00207-0009 CAP AL 12UF 63V EA 1.00
C10 097-00204-0011 CAP AL 10UF 50V 20 EA 1.00
C11 097-00218-0005 CAP EL 22UF 100V EA 1.00
C12 106-04223-0047 CAP CH 22K X7R/50V EA 1.00
C13 106-04330-0026 CH 33PF NPO/100V EA 1.00
C14 105-00046-0004 CAP MY 3UF 100V10% EA 1.00
C15 097-00207-0008 CAP AL 270UF 25V EA 1.00
C16 106-04272-0017 CAPCH .0027 MF COG EA 1.00
C17 106-04104-0047 CH 100KX7R/50V EA 1.00
C18 106-04272-0017 CAPCH .0027 MF COG EA 1.00
C19 106-04104-0047 CH 100KX7R/50V EA 1.00
C2 105-00046-0011 CAP MY 5.0UF EA 1.00
C20 097-00214-0035 CAP AL 47UF 50V EA 1.00
C21 097-00211-0000 CAP AL 140UF 75V EA 1.00
C22 105-00046-0011 CAP MY 5.0UF EA 1.00
C24 095-00006-0072 CAP AL 3.3UF 100V EA 1.00
C3 097-00211-0001 CAP AL 78UF 100V EA 1.00
C4 106-04330-0026 CH 33PF NPO/100V EA 1.00
C5 097-00097-0016 CAP EL 220UF 80V EA 1.00
C6 106-04330-0026 CH 33PF NPO/100V EA 1.00
C7 106-04330-0026 CH 33PF NPO/100V EA 1.00
C8 097-00204-0010 CAP AL 10UF 25V 20 EA 1.00
C9 097-00204-0007 CAP AL 4.7UF 25V 2 EA 1.00
CR1 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR11 007-06444-0001 DIO 1A 100V SMD EA 1.00
CR12 999-09999-9999 PLACE HOLDER RF .00
CR8 007-06088-0000 DIO HC 1N5817 EA 1.00
P1 030-03041-0005 HEADER RT DOUBLE EA 1.00
Q1 007-00549-0000 XSTR MMBT4401 EA 1.00
Q10 007-00886-0000 XSTR MOSFET IRF540 EA 1.00
Q11 00712225-0002 XSTR,IRFR9120,P-CH EA 1.00
Q12 007-00933-0000 MMBT2369 EA 1.00
Q2 007-00399-0002 XSTR D44E3 EA 1.00
Q3 007-00399-0002 XSTR D44E3 EA 1.00
Q4 007-00926-0000 MOSFET PCH VP0300L EA 1.00
Q5 007-00926-0000 MOSFET PCH VP0300L EA 1.00
Q7 007-00532-0000 XSTR MMBT4403 EA 1.00
Q8 007-00549-0000 XSTR MMBT4401 EA 1.00
R1 139-03572-0000 RES CHIP 35.7KEW1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-25

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R10 139-00511-0020 RES CH 51.1 QW 1% EA 1.00
R11 133-00113-0006 RES VA 100 20% A EA 1.00
R12 139-02210-0000 RES CH 221 EW 1% EA 1.00
R13 139-20274-0030 RES CH 2.74 1/2W 1 EA 1.00
R14 139-20274-0030 RES CH 2.74 1/2W 1 EA 1.00
R15 130-09006-1271 RES CH 2.7 OHM 5% EA 1.00
R17 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R18 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R19 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R2 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R20 139-04751-0000 RES CH 4.75K EW 1% EA 1.00
R21 139-01000-0020 RES CH 100 QW 1% EA 1.00
R22 139-00511-0020 RES CH 51.1 QW 1% EA 1.00
R23 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R24 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R25 139-04750-0000 RES CH 475 EW 1% EA 1.00
R26 139-00200-0000 RES CH 20.0 EW 1% EA 1.00
R27 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R28 133-00113-0006 RES VA 100 20% A EA 1.00
R29 139-04750-0000 RES CH 475 EW 1% EA 1.00
R30 139-01502-0000 RES CHIP 15K EW 1% EA 1.00
R31 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R32 139-01500-0020 RES CH 150 QW 1% EA 1.00
R33 139-00332-0000 RES CH 33.2 EW 1% EA 1.00
R34 139-00000-0004 RES CH 0 EW EA 1.00
R35 999-09999-0098 PLACE HOLDER RF .00
R36 999-09999-0098 PLACE HOLDER RF .00
R4 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R5 139-03162-0000 RES CHIP 31.6KEW1% EA 1.00
R6 139-03481-0000 RES CH 3.48K EW 1% EA 1.00
R7 139-07500-0000 RES CHIP 750 EW 1% EA 1.00
R8 139-03570-0000 RES CHIP 357 EW 1% EA 1.00
R9 139-02210-0000 RES CH 221 EW 1% EA 1.00
TP1 008-00309-0000 TEST POINT SURF MN EA 1.00
U1 120-00512-0001 HEX INVERTER/BUFFE EA 1.00
002-08274-0020 KT 73 MODULATOR BO RF .00
009-08274-0021 MODULATORE BOARD EA 1.00
016-01040-0000 COATING TYPE AR AR 1.00
016-01082-0000 DC RTV 3145 AR 1.00
026-00032-0008 WIRE, CU, 28AWG, S IN .22
300-08274-0020 KT 73 MODULATOR BO RF .00
Rev. 1, May/2003 15563M01.JA Page 6-26

B KT 73
FIGURE 6-6 KT 73 MODULATOR BOARD

(Dwg. No. 300-08274-0020 R-J)
Rev. 1, May/2003 15563M01.JA Page 6-27

B KT 73
FIGURE 6-7 KT 73 MODULATOR BOARD SCHEMATIC

(Dwg. No. 002-08274-0020 R-G)
Rev. 1, May/2003 15563M01.JA Page 6-29

B KT 73
6.9 KT 73 FRONT PANEL ASSEMBLY
200-09349-0000 B.O.M. FRONT PANEL, KT73 Rev. B

---------------------------------------------------------------
---------------------------------------------------------------
REF1 300-09349-0000 FRONT BEZEL ASSEM RF .00
012-01017-0001 11 ELEC TAPE 1/4 W IN 3.40
016-01124-0001 10 FOAM CARRIER TAPE IN .70
037-05107-0001 9 GAS DISCHARGE DISP EA 1.00
073-00998-0006 5 MODE CONTROL KNOB EA 1.00
073-01015-0005 4 KNOB, W/WASHER, KT EA 4.00
089-05903-0005 7 SCR PHP 4-40X5/16 EA 2.00
089-05927-0010 8 SCR BHP 4-40X5/8 EA 1.00
089-06200-0004 6 SCR SET 2-56X1/8 EA 11.00
187-01913-0001 3 .180 ID X .270 OD EA 1.00
200-09325-0020 1 KT 73 DISPLAY BOAR EA 1.00
200-09355-0000 2 BEZEL ASSEMBLY BOM EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-31

B KT 73
Rev. 1, May/2003 15563M01.JA Page 6-32

B KT 73
FIGURE 6-8 KT 73 FRONT PANEL ASSEMBLY

(Dwg. No. 300-09349-0000 R-A)
Rev. 1, May/2003 15563M01.JA Page 6-33

B KT 73
6.10 KT 73 DISPLAY BOARD
200-09325-0020 KT 73 DISPLAY BOARD Rev. D

---------------------------------------------------------------
---------------------------------------------------------------
C1 106-04104-0047 CH 100KX7R/50V EA 1.00
C2 106-04104-0047 CH 100KX7R/50V EA 1.00
CR1 007-05117-0024 DIO Z 33V SOT EA 1.00
CR2 007-05117-0024 DIO Z 33V SOT EA 1.00
CR3 007-05117-0024 DIO Z 33V SOT EA 1.00
CR4 007-05117-0024 DIO Z 33V SOT EA 1.00
CR5 007-05117-0016 DIO Z 15V SOT EA 1.00
CR6 007-05117-0016 DIO Z 15V SOT EA 1.00
DS1 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS19 007-07008-0001 LED LIGHT BARS REC EA 1.00
DS2 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS3 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS4 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS5 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS6 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS7 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS8 037-00012-0014 LAMP INC T-1 14V EA 1.00
J1 033-00312-0033 SOCKET, SIP, .1CTR EA 1.00
P1 030-03347-0022 HEADER .630 LONG 2 EA 1.00
Q1 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q10 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q11 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q12 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q13 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q14 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q15 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q16 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q17 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q18 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q19 007-00903-0000 2N7002 MOSFET EA 1.00
Q2 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q22 007-00903-0000 2N7002 MOSFET EA 1.00
Q3 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q4 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q5 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q6 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q7 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q8 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q9 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
R1 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R10 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R100 139-02002-0010 RES CH 20K TW 1% EA 1.00
R109 139-07502-0000 RES CHIP 75KEW1% EA 1.00
R11 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R111 139-01500-0000 RES CH 150 EW 1% EA 1.00
R113 139-04991-0000 RES CHIP 4.99KEW1% EA 1.00
R114 999-09999-9999 PLACE HOLDER RF .00
R115 999-09999-9999 PLACE HOLDER RF .00
Rev. 1, May/2003 15563M01.JA Page 6-35

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R12 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R13 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R14 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R15 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R16 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R17 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R18 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R19 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R2 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R20 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R21 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R22 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R23 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R24 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R25 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R26 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R27 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R28 139-05113-0010 RES CH TW 1% EA 1.00
R29 139-05113-0010 RES CH TW 1% EA 1.00
R3 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R30 139-05113-0010 RES CH TW 1% EA 1.00
R31 139-05113-0010 RES CH TW 1% EA 1.00
R32 139-05113-0010 RES CH TW 1% EA 1.00
R33 139-05113-0010 RES CH TW 1% EA 1.00
R34 139-05113-0010 RES CH TW 1% EA 1.00
R35 139-05113-0010 RES CH TW 1% EA 1.00
R36 139-05113-0010 RES CH TW 1% EA 1.00
R37 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R38 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R4 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R40 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R41 139-03012-0010 RESISTOR CHIP 30.1 EA 1.00
R43 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R44 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R45 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R46 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R47 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R48 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R49 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R5 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R50 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R51 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R52 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R53 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R54 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R55 139-01502-0010 RES CH 15 K .1W 1% EA 1.00
R56 139-03323-0010 RES CH 332K TW 1% EA 1.00
R57 139-03323-0010 RES CH 332K TW 1% EA 1.00
R58 139-03323-0010 RES CH 332K TW 1% EA 1.00
R59 139-03323-0010 RES CH 332K TW 1% EA 1.00
R6 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-36

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R60 139-03323-0010 RES CH 332K TW 1% EA 1.00
R61 139-03323-0010 RES CH 332K TW 1% EA 1.00
R62 139-03323-0010 RES CH 332K TW 1% EA 1.00
R63 139-03323-0010 RES CH 332K TW 1% EA 1.00
R64 139-03323-0010 RES CH 332K TW 1% EA 1.00
R65 139-03323-0010 RES CH 332K TW 1% EA 1.00
R66 139-03323-0010 RES CH 332K TW 1% EA 1.00
R67 139-03323-0010 RES CH 332K TW 1% EA 1.00
R68 139-03323-0010 RES CH 332K TW 1% EA 1.00
R69 139-03323-0010 RES CH 332K TW 1% EA 1.00
R7 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R70 139-03323-0010 RES CH 332K TW 1% EA 1.00
R71 139-03323-0010 RES CH 332K TW 1% EA 1.00
R72 139-03323-0010 RES CH 332K TW 1% EA 1.00
R73 139-03323-0010 RES CH 332K TW 1% EA 1.00
R74 139-03323-0010 RES CH 332K TW 1% EA 1.00
R75 139-03323-0010 RES CH 332K TW 1% EA 1.00
R76 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R77 134-05005-0002 PHOTODETECTOR EA 1.00
R78 139-03322-0010 RES CH 33.2K TW 1% EA 1.00
R8 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R80 139-01502-0010 RES CH 15 K .1W 1% EA 1.00
R81 139-01822-0010 RES CH 18.2K TW 1 EA 1.00
R82 139-02002-0010 RES CH 20K TW 1% EA 1.00
R83 139-02002-0010 RES CH 20K TW 1% EA 1.00
R84 139-02002-0010 RES CH 20K TW 1% EA 1.00
R85 139-02002-0010 RES CH 20K TW 1% EA 1.00
R86 139-02002-0010 RES CH 20K TW 1% EA 1.00
R87 139-02002-0010 RES CH 20K TW 1% EA 1.00
R88 139-02002-0010 RES CH 20K TW 1% EA 1.00
R89 139-02002-0010 RES CH 20K TW 1% EA 1.00
R9 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R90 139-02002-0010 RES CH 20K TW 1% EA 1.00
R91 139-02002-0010 RES CH 20K TW 1% EA 1.00
R92 139-02002-0010 RES CH 20K TW 1% EA 1.00
R93 139-02002-0010 RES CH 20K TW 1% EA 1.00
R94 139-02002-0010 RES CH 20K TW 1% EA 1.00
R95 139-02002-0010 RES CH 20K TW 1% EA 1.00
R96 139-02002-0010 RES CH 20K TW 1% EA 1.00
R97 139-02002-0010 RES CH 20K TW 1% EA 1.00
R98 139-02002-0010 RES CH 20K TW 1% EA 1.00
R99 139-02002-0010 RES CH 20K TW 1% EA 1.00
SW1 031-00759-0000 SWITCH ROTARY EA 1.00
SW5 031-00759-0010 ROTARY SWITCH EA 1.00
SW6 031-00753-0000 SWITCH TACTILE EA 1.00
SW7 031-00753-0000 SWITCH TACTILE EA 1.00
U1 124-00237-0003 74HCT237 3 TO 8 LI EA 1.00
U2 124-00151-0003 IC 74HCT151 SO EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-37

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
002-09325-0020 KT 73 DISPLAY BOAR RF .00
009-09325-0020 DISPLAY BOARD RF .00
009-09325-0021 1 KT 73 DISPLAY BOAR EA 1.00
012-01005-0005 2 TAPE MYLAR 1 W IN 5.80
016-01040-0000 3 COATING TYPE AR AR 1.00
016-01082-0000 DC RTV 3145 AR 1.00
088-02511-0004 4 KT 735G W/SECONDAY EA 1.00
088-02555-0001 5 STANDOFF KEYSWITCH EA 2.00
089-05899-0003 6 SCR PHP 2-56X3/16 EA 4.00
091-00618-0440 7 LED SPACER .440 EA 1.00
150-00002-0010 8 TUBING TFLN 26AWG IN 6.00
150-00003-0010 9 TUBING TFLN 24AWG IN 1.50
300-09325-0020 DISPLAY BOARD K RF .00
Rev. 1, May/2003 15563M01.JA Page 6-38

B KT 73
FIGURE 6-9 KT 73 DISPLAY BOARD

(Dwg. No. 300-09325-0020 R-D, Sheet 1 of 2)
Rev. 1, May/2003 15563M01.JA Page 6-39

B KT 73
FIGURE 6-9 KT 73 DISPLAY BOARD

(Dwg. No. 300-09325-0020 R-D, Sheet 2 of 2)
Rev. 1, May/2003 15563M01.JA Page 6-41

B KT 73
FIGURE 6-10 KT 73 DISPLAY BOARD SCHEMATIC

(Dwg. No. 002-09325-0020 R-B, Sheet 1 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-43

B KT 73

(Dwg. No. 002-09325-0020 R-B, Sheet 2 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-45

B KT 73

(Dwg. No. 002-09325-0020 R-B, Sheet 3 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-47

B KT 73

(Dwg. No. 002-09325-0020 R-B, Sheet 4 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-49

B KT 73
6.11 KT 73 BEZEL/DECAL ASSEMBLY
200-09355-0000 BEZEL ASSEMBLY BOM, KT73 Rev. A

---------------------------------------------------------------
---------------------------------------------------------------
016-01131-0000 6 CONTACT CEMENT #77 AR 1.00
035-01361-0028 7 PROTECTIVE COVER, EA 1.00
057-05892-0001 3 DECAL PART, KT73 EA 1.00
073-01001-0004 1 BEZEL W / PAINT EA 1.00
088-03227-0029 4 PUSH BUTTON O DECO EA 1.00
088-03227-0031 5 PUSH BUTTON O DECO EA 1.00
088-03248-0002 2 LENS, W/FAIL EA 1.00
300-09355-0000 BEZEL ASSEMBLY DRA RF .00
Rev. 1, May/2003 15563M01.JA Page 6-51

B KT 73
Rev. 1, May/2003 15563M01.JA Page 6-52

B KT 73
FIGURE 6-11 KT 73 BEZEL/DECAL ASSEMBLY

(Dwg. No. 300-09355-0000 R-D)
Rev. 1, May/2003 15563M01.JA Page 6-53

B KT 73
6.12 KT 73 MOUNTING RACK ASSEMBLY
200-10069-0000 MOUNTING RACK Rev. A

---------------------------------------------------------------
---------------------------------------------------------------
047-12768-0005 MTG RACK W/FINISH EA 1.00
089-05903-0007 SCR PHP 4-40X7/16 EA 2.00
200-09889-0010 KT 73 EXTERNAL EEP EA 1.00
300-10069-0000 MOUNTING RACK ASSY RF .00
Rev. 1, May/2003 15563M01.JA Page 6-55

B KT 73
Rev. 1, May/2003 15563M01.JA Page 6-56

B KT 73
FIGURE 6-12 KT 73 MOUNTING RACK ASSEMBLY

(Dwg. No. 300-10069-0000 R--)
Rev. 1, May/2003 15563M01.JA Page 6-57

B KT 73
6.13 KT 73 EXTERNAL EEPROM BOARD
200-09889-0010 KT 73 EXTERNAL EEPRM BOARD Rev. B

---------------------------------------------------------------
---------------------------------------------------------------
C1 106-05104-1327 CAP CH 100KX7R/16V EA 1.00
C2 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
C3 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
C4 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
ITM1 009-09889-0011 KT 73 EXTERNAL EEP EA 1.00
ITM2 030-00107-0099 POLARIZING KEY EA 1.00
J1 030-01120-0000 CONN PC BD EA 1.00
J2 030-03410-0003 CONN, RECT, PLG,FX EA 1.00
R1 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
REF1 300-09889-0010 KT 73 EXTERNAL EEP RF .00
REF2 002-09889-0010 KT 73 EXTERNAL EEP RF .00
U1 120-02547-0013 SERIAL EEPROM EA 1.00
016-01140-0000 SUPERBONDER 415 AR 1.00
Rev. 1, May/2003 15563M01.JA Page 6-59

B KT 73
Rev. 1, May/2003 15563M01.JA Page 6-60

B KT 73
FIGURE 6-13 KT 73 EXTERNAL EEPROM BOARD

(Dwg. No. 300-09889-0010 R-A)
Rev. 1, May/2003 15563M01.JA Page 6-61

B KT 73
FIGURE 6-14 KT 73 EXTERNAL EEPROM BOARD SCHEMATIC

(Dwg. No. 002-09889-0010 R--)
Rev. 1, May/2003 15563M01.JA Page 6-63

B KT 73
6.14 KT 73 RECEIVER BOARD
200-08273-0020 KT 73 RECEIVER BD Rev. H

---------------------------------------------------------------
---------------------------------------------------------------
C1 106-04471-0026 CH 470PF NPO/100V EA 1.00
C10 999-09999-0098 PLACE HOLDER RF .00
C100 106-04151-0026 CH 150PF NPO/100V EA 1.00
C101 106-04150-0026 CH 15PF NPO/100V EA 1.00
C102 106-04220-0026 CH 22PF NPO/100V EA 1.00
C103 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C104 106-04220-0026 CH 22PF NPO/100V EA 1.00
C105 106-04180-0026 CAP CH18PFNPO/100V EA 1.00
C106 106-04151-0026 CH 150PF NPO/100V EA 1.00
C107 106-04103-0047 CH 10K X7R/50V EA 1.00
C108 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C109 106-04103-0047 CH 10K X7R/50V EA 1.00
C11 106-05829-0020 CH 8.2PF NPO 100V EA 1.00
C110 106-04104-0047 CH 100KX7R/50V EA 1.00
C111 106-04103-0047 CH 10K X7R/50V EA 1.00
C112 097-07000-5205 CAP AL LOW ESR SM EA 1.00
C114 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C115 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C117 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C118 106-04680-0026 CAP CH68PFNPO/100V EA 1.00
C119 106-04181-0026 CAPCH180PFNPO/100V EA 1.00
C12 106-04101-0026 CH 100PF NPO/100V EA 1.00
C120 097-00204-0004 CAP AL 1UF 50V 20% EA 1.00
C121 106-04154-0047 CH 150K X7R/50V EA 1.00
C122 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C123 106-04154-0047 CH 150K X7R/50V EA 1.00
C124 106-04154-0047 CH 150K X7R/50V EA 1.00
C125 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C126 106-05030-0020 CH 3.0PF NPO/100V EA 1.00
C127 106-04103-0047 CH 10K X7R/50V EA 1.00
C128 106-04103-0047 CH 10K X7R/50V EA 1.00
C129 999-09999-0098 PLACE HOLDER RF .00
C13 106-05569-0020 CAP CH 5.6 PF EA 1.00
C130 106-05159-0020 CH 1.5PF NPO/100V EA 1.00
C131 106-04471-0026 CH 470PF NPO/100V EA 1.00
C132 106-04104-0047 CH 100KX7R/50V EA 1.00
C133 999-09999-0098 PLACE HOLDER RF .00
C137 106-04120-0026 CAPCH 12PFNPO/100V EA 1.00
C138 106-04103-0047 CH 10K X7R/50V EA 1.00
C139 106-04100-0026 CAPCH 10PFNPO/100V EA 1.00
C14 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C140 106-04103-0047 CH 10K X7R/50V EA 1.00
C141 106-04820-0026 CAP CH82PFNPO/100V EA 1.00
C142 106-04150-0026 CH 15PF NPO/100V EA 1.00
C143 106-04104-0047 CH 100KX7R/50V EA 1.00
C144 106-04104-0047 CH 100KX7R/50V EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-65

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
C145 106-04104-0047 CH 100KX7R/50V EA 1.00
C146 106-05399-0020 CH 3.9PF NPO/100V EA 1.00
C147 106-05399-0020 CH 3.9PF NPO/100V EA 1.00
C148 106-04104-0047 CH 100KX7R/50V EA 1.00
C149 106-04150-0026 CH 15PF NPO/100V EA 1.00
C15 106-04151-0026 CH 150PF NPO/100V EA 1.00
C150 106-04103-0047 CH 10K X7R/50V EA 1.00
C151 102-00098-0001 CAP VAR 7-50PF EA 1.00
C153 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C154 106-04511-0026 CAPCH510PFNPO/100V EA 1.00
C155 106-04330-0026 CH 33PF NPO/100V EA 1.00
C156 106-04152-0026 CAP CH1500PFNPO EA 1.00
C157 106-04680-0026 CAP CH68PFNPO/100V EA 1.00
C158 106-04152-0026 CAP CH1500PFNPO EA 1.00
C159 106-04181-0026 CAPCH180PFNPO/100V EA 1.00
C16 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C160 106-04152-0026 CAP CH1500PFNPO EA 1.00
C161 106-04103-0047 CH 10K X7R/50V EA 1.00
C162 106-04104-0047 CH 100KX7R/50V EA 1.00
C163 106-04104-0047 CH 100KX7R/50V EA 1.00
C164 106-05020-0026 CAP CH 2PFNPO/100V EA 1.00
C165 106-05519-0026 CAP CH5.1PFNPO/100 EA 1.00
C166 106-05519-0026 CAP CH5.1PFNPO/100 EA 1.00
C167 106-04103-0047 CH 10K X7R/50V EA 1.00
C169 106-04560-0026 CAPCH 56PFNPO/100V EA 1.00
C17 106-04689-0020 CAP CH 6.8 NPO/100 EA 1.00
C173 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C174 106-04104-0047 CH 100KX7R/50V EA 2.00
C175 106-04104-0047 CH 100KX7R/50V EA 2.00
C176 106-04104-0047 CH 100KX7R/50V EA 1.00
C177 106-04104-0047 CH 100KX7R/50V EA 1.00
C178 106-04104-0047 CH 100KX7R/50V EA 1.00
C179 106-04104-0047 CH 100KX7R/50V EA 1.00
C18 102-00098-0003 CAP VAR 2.0-6.0PF EA 1.00
C181 106-04104-0047 CH 100KX7R/50V EA 1.00
C182 106-04104-0047 CH 100KX7R/50V EA 1.00
C184 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C185 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C186 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C187 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C188 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C189 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C19 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C190 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C191 106-00122-0000 CH CER SMT 1812 .3 EA 1.00
C193 106-04104-0047 CH 100KX7R/50V EA 1.00
C194 999-09999-0098 PLACE HOLDER RF .00
C195 106-04680-0026 CAP CH68PFNPO/100V EA 1.00
C196 106-04181-0026 CAPCH180PFNPO/100V EA 1.00
C197 106-05689-0020 CH 6.8PF NPO/100V EA 1.00
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C199 106-05229-0020 CH 2.2PF NPO/100V EA 1.00
C2 106-05829-0020 CH 8.2PF NPO 100V EA 1.00
C20 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C200 999-09999-0098 PLACE HOLDER RF .00
C201 999-09999-0098 PLACE HOLDER RF .00
C202 999-09999-0098 PLACE HOLDER RF .00
C203 999-09999-0098 PLACE HOLDER RF .00
C21 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C22 106-05229-0020 CH 2.2PF NPO/100V EA 1.00
C23 106-04154-0047 CH 150K X7R/50V EA 1.00
C24 106-04154-0047 CH 150K X7R/50V EA 1.00
C25 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C26 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C27 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C28 106-05229-0020 CH 2.2PF NPO/100V EA 1.00
C29 106-05010-0020 CAP CH 1PFNPO/100V EA 1.00
C3 106-04180-0026 CAP CH18PFNPO/100V EA 1.00
C30 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C31 106-04154-0047 CH 150K X7R/50V EA 1.00
C32 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C33 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C34 106-04154-0047 CH 150K X7R/50V EA 1.00
C35 106-05010-0020 CAP CH 1PFNPO/100V EA 1.00
C36 106-04181-0026 CAPCH180PFNPO/100V EA 1.00
C37 106-04680-0026 CAP CH68PFNPO/100V EA 1.00
C38 106-04103-0047 CH 10K X7R/50V EA 1.00
C39 106-04103-0047 CH 10K X7R/50V EA 1.00
C4 102-00098-0003 CAP VAR 2.0-6.0PF EA 1.00
C40 106-05519-0020 CAP CH 5.1PF 100V EA 1.00
C42 106-04154-0047 CH 150K X7R/50V EA 1.00
C43 106-04272-0046 CAP CH 2.7KX7R/50V EA 1.00
C44 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C45 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C46 106-05229-0020 CH 2.2PF NPO/100V EA 1.00
C47 106-04470-0026 CAPCH 47PFNPO/100V EA 1.00
C5 106-04103-0047 CH 10K X7R/50V EA 1.00
C6 106-04100-0026 CAPCH 10PFNPO/100V EA 1.00
C64 106-04180-0026 CAP CH18PFNPO/100V EA 1.00
C7 106-04270-0026 CH 27PF NPO/100V EA 1.00
C74 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C75 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C76 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C77 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C78 999-09999-0098 PLACE HOLDER RF .00
C79 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C8 106-04151-0026 CH 150PF NPO/100V EA 1.00
C80 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C81 106-04240-0026 CAP CH24PFNPO/100V EA 1.00
C82 106-04103-0047 CH 10K X7R/50V EA 1.00
C83 106-04103-0047 CH 10K X7R/50V EA 1.00
C84 106-04103-0047 CH 10K X7R/50V EA 1.00
C85 106-04103-0047 CH 10K X7R/50V EA 1.00
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C86 106-04150-0026 CH 15PF NPO/100V EA 1.00
C87 106-04150-0026 CH 15PF NPO/100V EA 1.00
C88 106-04103-0047 CH 10K X7R/50V EA 1.00
C89 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C9 106-04151-0026 CH 150PF NPO/100V EA 1.00
C90 106-04470-0024 CAP CERAMIC CHIP EA 1.00
C91 106-04201-0024 CAP CHIP EA 1.00
C92 106-04103-0047 CH 10K X7R/50V EA 1.00
C93 106-04103-0047 CH 10K X7R/50V EA 1.00
C94 106-04510-0026 CAP CH51PFNPO/100V EA 1.00
C95 106-04103-0047 CH 10K X7R/50V EA 1.00
C96 106-04103-0047 CH 10K X7R/50V EA 1.00
C97 106-04103-0047 CH 10K X7R/50V EA 1.00
C98 106-04152-0026 CAP CH1500PFNPO EA 1.00
C99 106-04100-0026 CAPCH 10PFNPO/100V EA 1.00
CJ1 026-00018-0000 WIRE CKTJMPR 22AWG EA 1.00
CR2 007-05117-0007 DIO Z 6.2V SOT EA 1.00
CR4 007-05117-0007 DIO Z 6.2V SOT EA 1.00
CR5 007-05011-0001 DIO Z 10V 1W 5% EA 1.00
FL1 017-00240-0000 FILTER CER 1030MHZ EA 1.00
L1 019-02660-0010 IND SM 80 10% EA 1.00
L10 019-02660-0015 IND SM 150 10% EA 1.00
L11 019-02660-0019 IND SM 330 10% EA 1.00
L13 019-02660-0009 IND SM 70 10% EA 1.00
L14 019-02660-0013 IND SM 100 10% EA 1.00
L15 019-02660-0009 IND SM 70 10% EA 1.00
L16 019-02660-0013 IND SM 100 10% EA 1.00
L17 019-02707-0000 INDUCTOR-1/2 TURN EA 1.00
L18 019-02707-0000 INDUCTOR-1/2 TURN EA 1.00
L19 019-02660-0051 IND SM 150 2% EA 1.00
L2 019-02660-0015 IND SM 150 10% EA 1.00
L20 019-02660-0018 IND SM 270 10% EA 1.00
L21 019-02660-0016 IND SM 180 10% EA 1.00
L22 019-02660-0028 IND SM 1000 10% EA 1.00
L23 019-02660-0019 IND SM 330 10% EA 1.00
L24 019-02312-0061 IDCTR V 2.5T EA 1.00
L25 019-02312-0061 IDCTR V 2.5T EA 1.00
L26 019-02660-0029 IND SM 1200 10% EA 1.00
L27 019-02660-0029 IND SM 1200 10% EA 1.00
L28 019-02660-0001 IND SM 8.2 20% EA 1.00
L29 019-02660-0015 IND SM 150 10% EA 1.00
L3 019-02400-0000 COIL, 4 TURNS EA 1.00
L30 019-02757-0005 SMD FERRITE BEAD EA 1.00
L36 013-00172-0001 FERR BEAD SRFC MT EA 1.00
L4 019-02400-0020 COIL 4 T EA 1.00
L5 019-02400-0022 COIL 3TX0.095 EA 1.00
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B KT 73
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L6 019-02400-0021 COIL 1TX0.100 EA 1.00
L7 019-02660-0015 IND SM 150 10% EA 1.00
L8 019-02660-0015 IND SM 150 10% EA 1.00
L9 019-02660-0010 IND SM 80 10% EA 1.00
P4 030-02174-0004 PIN CONTACT EA 9.00
Q1 007-01083-0001 NPN RF XSTR EA 1.00
Q10 999-09999-0098 PLACE HOLDER RF .00
Q13 007-01083-0001 NPN RF XSTR EA 1.00
Q14 007-00195-0001 XSTR MPSH10 EA 1.00
Q15 007-00532-0000 XSTR MMBT4403 EA 1.00
Q16 007-00549-0000 XSTR MMBT4401 EA 1.00
Q19 007-00549-0000 XSTR MMBT4401 EA 1.00
Q2 007-01083-0001 NPN RF XSTR EA 1.00
Q20 007-00549-0000 XSTR MMBT4401 EA 1.00
Q21 007-00195-0001 XSTR MPSH10 EA 1.00
Q22 999-09999-0098 PLACE HOLDER RF .00
Q3 007-01083-0001 NPN RF XSTR EA 1.00
Q4 007-01083-0001 NPN RF XSTR EA 1.00
Q5 007-01083-0001 NPN RF XSTR EA 1.00
Q6 007-00532-0000 XSTR MMBT4403 EA 1.00
Q7 007-00940-0000 RF AMP EA 1.00
Q8 007-00939-0000 DUAL GATE FET EA 1.00
Q9 007-01083-0001 NPN RF XSTR EA 1.00
R1 139-01211-0000 RES CHIP1.21KEW1% EA 1.00
R10 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R100 139-06811-0000 RES CH 6.81K EW 1% EA 1.00
R101 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R102 139-03010-0000 RES CHIP 301 EW 1% EA 1.00
R103 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R104 139-02000-0000 RES CH 200 EW 1% EA 1.00
R105 139-03920-0000 392 OHM 1/8W 1% EA 1.00
R106 139-06810-0000 RES CH 681 EW 1% EA 1.00
R107 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R108 139-01301-0000 RES CH 1.30K EW 1% EA 1.00
R109 139-06190-0000 RES CH 619 EW 1% EA 1.00
R11 139-03920-0000 392 OHM 1/8W 1% EA 1.00
R110 139-01300-0000 RES CH 130 EW 1% EA 1.00
R111 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R112 139-00909-0000 RES CH 90.9 EW 1% EA 1.00
R113 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R114 139-02000-0000 RES CH 200 EW 1% EA 1.00
R115 139-20100-0000 RES CH 1 EW 1% EA 1.00
R116 139-20392-0000 RES CH 3.92 EW 1% EA 1.00
R117 139-05110-0000 RES CH 511 EW 1% EA 1.00
R118 139-05110-0000 RES CH 511 EW 1% EA 1.00
R119 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R12 139-04750-0000 RES CH 475 EW 1% EA 1.00
R120 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R121 139-04751-0000 RES CH 4.75K EW 1% EA 1.00
R122 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R123 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R124 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-69

B KT 73
---------------------------------------------------------------
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R125 139-06811-0000 RES CH 6.81K EW 1% EA 1.00
R126 139-05621-0000 RES CHIP 5.62KEW1% EA 1.00
R127 139-02000-0000 RES CH 200 EW 1% EA 1.00
R128 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R129 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R13 139-05111-0000 RES CHIP 5.11KEW1% EA 1.00
R130 139-02211-0000 RES CH 2.21K EW 1% EA 1.00
R131 139-02211-0000 RES CH 2.21K EW 1% EA 1.00
R132 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R133 139-01004-0000 RES CHIP 1M EW 1% EA 1.00
R134 139-01004-0000 RES CHIP 1M EW 1% EA 1.00
R135 999-09999-0098 PLACE HOLDER RF .00
R136 139-02432-0000 RES CH 24.3K EW 1% EA 1.00
R137 139-03320-0000 RES CHIP 332 EW 1% EA 1.00
R138 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R139 139-05110-0000 RES CH 511 EW 1% EA 1.00
R14 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R143 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R144 139-04752-0000 RES CH 47.5K EW 1% EA 1.00
R145 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R147 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R149 139-01210-0000 RES CH 121 EW 1% EA 1.00
R15 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R150 139-03010-0000 RES CHIP 301 EW 1% EA 1.00
R151 139-05110-0000 RES CH 511 EW 1% EA 1.00
R155 139-06190-0000 RES CH 619 EW 1% EA 1.00
R156 133-00558-0003 RES VA SMD 5K .2W EA 1.00
R157 133-00558-0003 RES VA SMD 5K .2W EA 1.00
R158 139-06190-0020 RES CH 619 QW 1% EA 1.00
R159 139-06811-0000 RES CH 6.81K EW 1% EA 1.00
R16 139-01500-0000 RES CH 150 EW 1% EA 1.00
R162 139-04321-0000 RES CH 4.32K EW 1% EA 1.00
R163 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R164 139-02000-0000 RES CH 200 EW 1% EA 1.00
R165 139-03920-0020 RES CH 392 QW 1% EA 1.00
R166 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R17 139-04750-0000 RES CH 475 EW 1% EA 1.00
R176 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R177 139-20392-0000 RES CH 3.92 EW 1% EA 1.00
R18 139-08251-0000 RES CH 8.25K EW 1% EA 1.00
R19 139-08250-0000 RES CH 825 EW 1% EA 1.00
R2 139-08250-0000 RES CH 825 EW 1% EA 1.00
R20 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R200 139-20562-0000 RES CH 5.62 EW 1% EA 1.00
R204 139-20562-0000 RES CH 5.62 EW 1% EA 1.00
R206 139-00000-0004 RES CH 0 EW EA 1.00
R207 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R208 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R209 139-05110-0000 RES CH 511 EW 1% EA 1.00
R21 139-04750-0000 RES CH 475 EW 1% EA 1.00
R210 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R211 999-09999-0098 PLACE HOLDER RF .00
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B KT 73
---------------------------------------------------------------
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R212 139-04750-0000 RES CH 475 EW 1% EA 1.00
R213 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R214 139-03011-0000 RES CH 3.01K EW 1% EA 1.00
R216 139-04991-0000 RES CHIP 4.99KEW1% EA 1.00
R217 133-00560-0010 RES VA SMD 20K QW EA 1.00
R22 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R23 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R230 139-00000-0004 RES CH 0 EW EA 1.00
R232 999-09999-0098 PLACE HOLDER RF .00
R233 139-00000-0004 RES CH 0 EW EA .10
R233 139-01002-0000 RES CHIP 10K EW 1% EA .90
R234 999-09999-0098 PLACE HOLDER RF .00
R235 999-09999-0098 PLACE HOLDER RF .00
R236 999-09999-0098 PLACE HOLDER RF .00
R237 999-09999-0098 PLACE HOLDER RF .00
R24 139-04320-0000 RES CH 432 EW 1% EA 1.00
R240 139-01181-0000 RES CHIP 1.18KEW1% EA 1.00
R241 139-00619-0000 RES CH 61.9 EW 1% EA 1.00
R25 139-01501-0000 RES CH 1.5K EW 1% EA 1.00
R26 139-01621-0000 RES CH 1.62K EW 1% EA 1.00
R27 139-01621-0000 RES CH 1.62K EW 1% EA 1.00
R28 139-01211-0000 RES CHIP1.21KEW1% EA 1.00
R29 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R3 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R30 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R31 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R32 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R33 139-03010-0000 RES CHIP 301 EW 1% EA 1.00
R34 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R35 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R36 139-00681-0000 RES CH 68.1 EW 1% EA 1.00
R37 139-05111-0000 RES CHIP 5.11KEW1% EA 1.00
R38 139-05111-0000 RES CHIP 5.11KEW1% EA 1.00
R39 139-05621-0000 RES CHIP 5.62KEW1% EA 1.00
R4 139-03320-0000 RES CHIP 332 EW 1% EA 1.00
R40 139-05621-0000 RES CHIP 5.62KEW1% EA 1.00
R41 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R42 139-01101-0000 RES CH 1.1K EW 1% EA 1.00
R43 139-08250-0000 RES CH 825 EW 1% EA 1.00
R44 139-03920-0000 392 OHM 1/8W 1% EA 1.00
R45 139-02370-0000 RES CH 237 EW 1% EA 1.00
R46 139-00121-0000 RES CH 12.1 EW 1% EA 1.00
R47 139-00000-0004 RES CH 0 EW EA 1.00
R49 999-09999-0098 PLACE HOLDER RF .00
R5 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R50 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R51 139-00000-0004 RES CH 0 EW EA 1.00
R6 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R65 139-01500-0000 RES CH 150 EW 1% EA 1.00
R66 139-01820-0000 RES CH 182 EW 1% EA 1.00
R68 139-00909-0000 RES CH 90.9 EW 1% EA 1.00
R7 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
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B KT 73
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R76 139-02001-0000 RES CHIP 2K EW 1% EA 1.00
R79 139-00000-0004 RES CH 0 EW EA 1.00
R8 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R80 139-00000-0004 RES CH 0 EW EA 1.00
R81 139-00000-0004 RES CH 0 EW EA 1.00
R82 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R83 139-00000-0004 RES CH 0 EW EA 1.00
R84 139-01004-0000 RES CHIP 1M EW 1% EA 1.00
R85 139-01004-0000 RES CHIP 1M EW 1% EA 1.00
R86 139-01004-0000 RES CHIP 1M EW 1% EA 1.00
R87 139-00825-0000 RES CH 82.5 EW 1% EA 1.00
R88 139-03011-0000 RES CH 3.01K EW 1% EA 1.00
R89 139-01821-0000 RES CHIP 1.82KEW1% EA 1.00
R9 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R90 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R91 139-02000-0000 RES CH 200 EW 1% EA 1.00
R92 139-06810-0000 RES CH 681 EW 1% EA 1.00
R93 139-01301-0000 RES CH 1.30K EW 1% EA 1.00
R94 139-06190-0000 RES CH 619 EW 1% EA 1.00
R95 139-03010-0000 RES CHIP 301 EW 1% EA 1.00
R96 139-04751-0000 RES CH 4.75K EW 1% EA 1.00
R97 139-08251-0000 RES CH 8.25K EW 1% EA 1.00
R98 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R99 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
RT1 134-01044-0013 THRMSTR SURFACE MT EA 1.00
RT2 999-09999-0098 PLACE HOLDER RF .00
T1 999-09999-0098 PLACE HOLDER RF .00
T2 019-08265-0000 XFMR IF 63MHZ EA 1.00
T3 019-08265-0000 XFMR IF 63MHZ EA 1.00
T4 019-08265-0000 XFMR IF 63MHZ EA 1.00
T5 019-08265-0000 XFMR IF 63MHZ EA 1.00
T6 019-08265-0000 XFMR IF 63MHZ EA 1.00
T7 999-09999-0098 PLACE HOLDER RF .00
T8 019-03357-0000 BALUN,4:1,5/600MHZ EA 1.00
TP1 008-00096-0001 TERMINAL TEST PNT EA 1.00
U1 120-03738-0001 AMPLIFIER, LOG, 50 EA 1.00
U12 120-03027-0004 BALANCED MOD/DEMOD EA 1.00
U14 120-03027-0004 BALANCED MOD/DEMOD EA 1.00
U15 120-03448-0000 VOLTAGE COMPARITOR EA 1.00
U16 120-03026-0080 78M05 DPAK VLT REG EA 1.00
U17 120-03065-0025 MC78L08ACD VLT REG EA 1.00
U18 999-09999-0098 PLACE HOLDER RF .00
U2 120-03644-0000 MMIC 1GHZ LONO AMP EA 1.00
U3 120-03644-0000 MMIC 1GHZ LONO AMP EA 1.00
U4 120-03729-0001 OP AMP, CLAMPING, EA 1.00
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B KT 73
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Y1 044-00305-0000 XTAL 161.6667 MHZ EA 1.00
002-08273-0020 KT 73 RECEIVER BD RF .00
009-08273-0021 KT 73 RECEIVER BD EA 1.00
012-01005-0007 TAPE MYLAR 1.5 W IN 1.50
016-01082-0000 DC RTV 3145 AR 1.00
024-05021-0005 COPPER STRAP .187 IN .45
024-05065-0000 WIRE SLD 28AWG AR 1.00
026-00029-0000 WIRE, CU, 22AWG, T IN 1.00
047-09583-0001 OSC FENCE EA 1.00
047-09584-0001 OSC COVER EA 1.00
047-09585-0001 MIXER FENCE EA 1.00
047-09586-0002 MIXER COVER EA 1.00
047-09783-0001 SHIELD 120 MHZ EA 1.00
047-09784-0002 SHIELD RECEIVER EA 1.00
047-09804-0001 INSERT OSC EA 1.00
047-09905-0001 FENCE IF EA 1.00
047-12832-0002 COVER WITH/PLATING EA 1.00
089-06004-0002 SCR FHP 2-56X1/8 EA 6.00
090-00087-0000 CLIP CRYSTAL EA 1.00
090-01037-0011 FINGER STOCK EA 1.00
092-05003-0011 EYE ROLL .059X.125 EA 2.00
150-00005-0010 TUBING TFLN 20AWG AR 1.00
300-08273-0020 KT 73 RECEIVER BD RF .00
Rev. 1, May/2003 15563M01.JA Page 6-73

B KT 73
Rev. 1, May/2003 15563M01.JA Page 6-74

B KT 73
FIGURE 6-15 KT 73 RECEIVER BOARD

(Dwg. No. 300-08273-0020 R-H, Sheet 1 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-75

B KT 73

(Dwg. No. 300-08273-0020 R-H, Sheet 2 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-77

B KT 73

(Dwg. No. 300-08273-0020 R-H, Sheet 3 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-79

B KT 73

(Dwg. No. 300-08273-0020 R-H, Sheet 4 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-81

B KT 73
FIGURE 6-16 KT 73 RECEIVER BOARD SCHEMATIC

(Dwg. No. 002-08273-0020 R-C, Sheet 1 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-83

B KT 73

(Dwg. No. 002-08273-0020 R-C, Sheet 2 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-85

B KT 73

(Dwg. No. 002-08273-0020 R-C, Sheet 3 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-87

B KT 73

(Dwg. No. 002-08273-0020 R-C, Sheet 4 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-89

B KT 73
6.15 KT 73 MAIN BOARD/SOFTWARE SET
206-00387-0101 SOFTWARE SET, KT73 Rev. B

206-00387-0102 SOFTWARE SET, KT73 Rev. -
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SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0101 -0102
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057-05287-0101 SW MOD TAG EA 1.00 .
057-05287-0102 UNIT SFTWR V0102 EA . 1.00
125-00966-0101 KT 73 APPLICATION RF .00 .
125-00966-0102 KT 73 APPLICATION RF . .00
125-01034-0002 KT 73 BOOT SOFTWAR RF .00 .00
126-00215-0002 KT 73 FPGA FIRMWAR RF .00 .00
126-00216-0000 KT73 VOICE RF .00 .00
205-00914-0002 KT 73 MAIN BOARD S EA 1.00 1.00
222-30035-0101 KT 73 LOAD MEDIA C RF .00 .
222-30035-0102 KT 73 LOAD MEDIA C RF . .00
716-00356-0101 KT 73 CONFIG INDEX RF .00 .
716-00356-0102 KT 73 SOFTWARE CON RF . .00
205-00914-0002 KT 73 MAIN BOARD SW Rev. -

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057-05252-0914 1 1DT 205-00914-0000 EA 1.00
057-05335-0002 2 DECAL 205 DASH 02 EA 1.00
125-01034-0002 KT 73 BOOT SOFTWAR EA 1.00
126-00215-0002 KT 73 FPGA FIRMWAR EA 1.00
200-09321-0000 BOM, MAIN BOARD, K EA 1.00
300-09321-0000 ASSEMBLY, MAIN BOA RF .00
200-09321-0000 BOM, MAIN BOARD, KT 73 Rev. E

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C10 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C11 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C153 106-04104-0047 CH 100KX7R/50V EA 1.00
C154 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
C155 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C156 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C157 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C158 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C16 106-04104-0047 CH 100KX7R/50V EA 1.00
C160 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C18 106-04104-0047 CH 100KX7R/50V EA 1.00
C182 106-05390-0026 CAP CH39PFNPO/100V EA 1.00
C183 106-04104-0047 CH 100KX7R/50V EA 1.00
C184 106-04104-0047 CH 100KX7R/50V EA 1.00
C185 106-04104-0047 CH 100KX7R/50V EA 1.00
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B KT 73
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C186 106-04104-0047 CH 100KX7R/50V EA 1.00
C187 106-04104-0047 CH 100KX7R/50V EA 1.00
C19 106-04104-0047 CH 100KX7R/50V EA 1.00
C20 106-04104-0047 CH 100KX7R/50V EA 1.00
C203 106-04104-0047 CH 100KX7R/50V EA 1.00
C204 096-01196-0049 CAP TANT FUSE 15 U EA 1.00
C209 096-01196-0022 CAP SMT FUSIBLE TA EA 1.00
C21 106-04104-0047 CH 100KX7R/50V EA 1.00
C217 106-05100-0026 CAP CH10PFNPO/100V EA 1.00
C218 106-05270-0026 CAP CH27PFNPO/100V EA 1.00
C219 106-05101-0026 CAPCH100PFNPO/100V EA 1.00
C221 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C222 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C224 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C226 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C227 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C228 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C229 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C230 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C231 106-05101-0026 CAPCH100PFNPO/100V EA 1.00
C232 106-04751-0016 CH 750PF NPO/50V EA 1.00
C233 106-05471-0026 CAP CH470PFNPO/100 EA 1.00
C234 106-05471-0026 CAP CH470PFNPO/100 EA 1.00
C235 106-05471-0026 CAP CH470PFNPO/100 EA 1.00
C236 106-05471-0026 CAP CH470PFNPO/100 EA 1.00
C237 106-05471-0026 CAP CH470PFNPO/100 EA 1.00
C238 106-00110-0001 CAP CH22K X7R 500V EA 1.00
C239 106-00110-0001 CAP CH22K X7R 500V EA 1.00
C240 106-00110-0001 CAP CH22K X7R 500V EA 1.00
C241 106-05560-0026 CAP CH56PFNPO/100V EA 1.00
C242 106-05560-0026 CAP CH56PFNPO/100V EA 1.00
C243 106-05560-0026 CAP CH56PFNPO/100V EA 1.00
C244 106-05560-0026 CAP CH56PFNPO/100V EA 1.00
C245 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C246 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C247 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C248 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C249 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C250 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C251 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C252 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C253 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C254 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C255 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C256 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C257 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C258 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-92

B KT 73
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C259 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C260 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C261 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C262 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C263 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C264 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C27 106-04104-0047 CH 100KX7R/50V EA 1.00
C271 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C272 106-10369-0038 ATA CAP VJ1210Y474 EA 1.00
C273 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C274 106-04104-0047 CH 100KX7R/50V EA 1.00
C287 106-04100-0026 CAPCH 10PFNPO/100V EA 1.00
C288 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C289 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C290 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C291 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C292 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C293 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C294 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C295 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C296 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C297 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C298 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C299 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C300 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C302 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C303 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C305 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C306 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C307 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C309 106-04104-0047 CH 100KX7R/50V EA 1.00
C310 106-04104-0047 CH 100KX7R/50V EA 1.00
C311 106-04104-0047 CH 100KX7R/50V EA 1.00
C312 106-04104-0047 CH 100KX7R/50V EA 1.00
C313 106-04104-0047 CH 100KX7R/50V EA 1.00
C314 106-04104-0047 CH 100KX7R/50V EA 1.00
C315 106-04104-0047 CH 100KX7R/50V EA 1.00
C316 106-04104-0047 CH 100KX7R/50V EA 1.00
C317 106-04104-0047 CH 100KX7R/50V EA 1.00
C318 106-04104-0047 CH 100KX7R/50V EA 1.00
C319 106-04104-0047 CH 100KX7R/50V EA 1.00
C320 106-04104-0047 CH 100KX7R/50V EA 1.00
C321 106-04104-0047 CH 100KX7R/50V EA 1.00
C327 106-04104-0047 CH 100KX7R/50V EA 1.00
C328 106-04104-0047 CH 100KX7R/50V EA 1.00
C329 106-04104-0047 CH 100KX7R/50V EA 1.00
C330 106-04104-0047 CH 100KX7R/50V EA 1.00
C331 106-04104-0047 CH 100KX7R/50V EA 1.00
C332 106-04104-0047 CH 100KX7R/50V EA 1.00
C333 106-04104-0047 CH 100KX7R/50V EA 1.00
C334 106-04104-0047 CH 100KX7R/50V EA 1.00
C335 106-04104-0047 CH 100KX7R/50V EA 1.00
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C336 106-04104-0047 CH 100KX7R/50V EA 1.00
C337 106-04104-0047 CH 100KX7R/50V EA 1.00
C338 106-04104-0047 CH 100KX7R/50V EA 1.00
C363 106-04104-0047 CH 100KX7R/50V EA 1.00
C364 106-04104-0047 CH 100KX7R/50V EA 1.00
C365 106-04104-0047 CH 100KX7R/50V EA 1.00
C366 106-04104-0047 CH 100KX7R/50V EA 1.00
C367 106-04104-0047 CH 100KX7R/50V EA 1.00
C368 106-04104-0047 CH 100KX7R/50V EA 1.00
C369 106-04104-0047 CH 100KX7R/50V EA 1.00
C370 106-04104-0047 CH 100KX7R/50V EA 1.00
C371 106-04104-0047 CH 100KX7R/50V EA 1.00
C372 106-04104-0047 CH 100KX7R/50V EA 1.00
C373 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C374 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C375 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C380 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C381 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C382 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C383 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C384 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C385 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C386 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C387 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C388 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C389 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C390 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C391 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C392 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C393 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C394 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C395 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C396 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C398 106-04104-0047 CH 100KX7R/50V EA 1.00
C401 106-04104-0047 CH 100KX7R/50V EA 1.00
C402 106-04104-0047 CH 100KX7R/50V EA 1.00
C403 106-04104-0047 CH 100KX7R/50V EA 1.00
C404 106-04104-0047 CH 100KX7R/50V EA 1.00
C405 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C406 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C407 106-04104-0047 CH 100KX7R/50V EA 1.00
C408 106-04104-0047 CH 100KX7R/50V EA 1.00
C409 106-04104-0047 CH 100KX7R/50V EA 1.00
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B KT 73
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C413 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C414 106-05101-0226 CAP CH 100PF NP0 2 EA 1.00
C415 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C416 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C417 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C418 106-06105-0047 CAP CER 1 UF 10% 5 EA 1.00
C419 106-04182-0016 CAPCH1800PFNPO/50V EA 1.00
C420 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C422 106-05101-0026 CAPCH100PFNPO/100V EA 1.00
C423 106-05100-0026 CAP CH10PFNPO/100V EA 1.00
C5 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C94 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
C95 106-05103-0057 CAP CH 10KX7R/100V EA 1.00
CJ1 030-03305-0001 HEADER, 2MM 2X EA 1.00
CR1 007-06184-0000 DIO DUAL SWITCHING EA 1.00
CR10 007-05248-0002 600W 12V SMT TRANS EA 1.00
CR11 007-05248-0002 600W 12V SMT TRANS EA 1.00
CR12 007-05241-0008 TRANSORB 1500W 85V EA 1.00
CR13 007-05254-0001 TVS 14WV 30V CLAMP EA 1.00
CR14 007-05254-0001 TVS 14WV 30V CLAMP EA 1.00
CR15 007-05248-0002 600W 12V SMT TRANS EA 1.00
CR16 007-05248-0002 600W 12V SMT TRANS EA 1.00
CR17 007-06396-0000 DIO SW DUAL EA 1.00
CR18 007-06396-0000 DIO SW DUAL EA 1.00
CR19 007-06396-0000 DIO SW DUAL EA 1.00
CR2 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR20 007-06396-0000 DIO SW DUAL EA 1.00
CR21 007-06396-0000 DIO SW DUAL EA 1.00
CR22 007-06396-0000 DIO SW DUAL EA 1.00
CR23 007-06396-0000 DIO SW DUAL EA 1.00
CR24 007-06396-0000 DIO SW DUAL EA 1.00
CR25 007-06396-0000 DIO SW DUAL EA 1.00
CR26 007-06444-0007 DIO 1A 600V SMD EA 1.00
CR27 007-06444-0007 DIO 1A 600V SMD EA 1.00
CR28 007-06396-0000 DIO SW DUAL EA 1.00
CR29 007-06396-0000 DIO SW DUAL EA 1.00
CR3 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR30 007-06396-0000 DIO SW DUAL EA 1.00
CR4 007-06441-0000 DIODE HOT CARRIER EA 1.00
CR8 007-06180-0000 DIO SW MMBD6050 EA 1.00
CR9 007-05248-0002 600W 12V SMT TRANS EA 1.00
DS1 007-06424-0000 LED SURFACE MOUNT EA 1.00
J2 030-03006-0007 CONN RECP DUAL EA 1.00
J3 03024513-0022 CONN,BOX HORIZ. 2X EA 1.00
J4 155-02654-0000 CABLE ASSY REC EA 1.00
J5 155-02654-0001 CABLE ASSY MOD EA 1.00
J8 030-03196-0017 CONN FEMALE 34 PIN EA 1.00
J9 030-03305-0005 HEADER, 2MM 2X EA 1.00
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B KT 73
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L5 019-02660-0004 IND SM 20 20% EA 1.00
L6 019-02660-0004 IND SM 20 20% EA 1.00
L7 019-02723-0042 CHIP INDUCTOR EA 1.00
Q1 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q10 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q11 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q12 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q13 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q14 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q15 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q16 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q17 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q18 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q19 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q2 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q20 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q21 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q22 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q23 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q24 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q25 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q26 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q27 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q28 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q29 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q3 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q30 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q31 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q32 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q33 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q34 007-00549-0000 XSTR MMBT4401 EA 1.00
Q35 007-00549-0000 XSTR MMBT4401 EA 1.00
Q36 007-00549-0000 XSTR MMBT4401 EA 1.00
Q37 007-00549-0000 XSTR MMBT4401 EA 1.00
Q38 007-00549-0000 XSTR MMBT4401 EA 1.00
Q39 007-00549-0000 XSTR MMBT4401 EA 1.00
Q4 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q40 007-00549-0000 XSTR MMBT4401 EA 1.00
Q41 007-00903-0000 2N7002 MOSFET EA 1.00
Q42 007-00903-0000 2N7002 MOSFET EA 1.00
Q43 007-00532-0000 XSTR MMBT4403 EA 1.00
Q44 007-00532-0000 XSTR MMBT4403 EA 1.00
Q45 007-00532-0000 XSTR MMBT4403 EA 1.00
Q46 007-01044-0000 MOSFET N-CH 100V EA 1.00
Q48 007-01072-0001 POWER MOSFET EA 1.00
Q49 007-00383-0004 SOT-23 2N2222A XST EA 1.00
Q5 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q50 007-00383-0004 SOT-23 2N2222A XST EA 1.00
Q51 007-00261-0003 XSTR 2N2907A (SOT) EA 1.00
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B KT 73
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Q52 007-00261-0003 XSTR 2N2907A (SOT) EA 1.00
Q53 007-00903-0000 2N7002 MOSFET EA 1.00
Q54 007-00903-0000 2N7002 MOSFET EA 1.00
Q55 007-00903-0000 2N7002 MOSFET EA 1.00
Q56 007-00903-0000 2N7002 MOSFET EA 1.00
Q6 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q7 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q8 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q9 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
R100 139-01003-0010 RES CH 100K TW 1% EA 1.00
R101 139-01003-0010 RES CH 100K TW 1% EA 1.00
R107 139-01003-0010 RES CH 100K TW 1% EA 1.00
R111 139-01622-0010 RES CH 16.2K .1W 1 EA 1.00
R113 139-01002-0010 RES CH 10K TW 1% EA 1.00
R116 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R118 139-01152-0010 RES CH 11.5K TW 1% EA 1.00
R119 139-08251-0010 RES CH 8.25K TW 1% EA 1.00
R121 139-01002-0010 RES CH 10K TW 1% EA 1.00
R123 139-01822-0010 RES CH 18.2K TW 1 EA 1.00
R124 139-02002-0010 RES CH 20K TW 1% EA 1.00
R129 139-07503-0010 SM RES 750K 1/10W EA 1.00
R181 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R248 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R330 139-03323-0010 RES CH 332K TW 1% EA 1.00
R331 139-01002-0010 RES CH 10K TW 1% EA 1.00
R332 139-01002-0010 RES CH 10K TW 1% EA 1.00
R333 139-01002-0010 RES CH 10K TW 1% EA 1.00
R334 139-01002-0010 RES CH 10K TW 1% EA 1.00
R335 139-01002-0010 RES CH 10K TW 1% EA 1.00
R336 139-01002-0010 RES CH 10K TW 1% EA 1.00
R337 139-01002-0010 RES CH 10K TW 1% EA 1.00
R338 139-01002-0010 RES CH 10K TW 1% EA 1.00
R339 139-01002-0010 RES CH 10K TW 1% EA 1.00
R340 139-01002-0010 RES CH 10K TW 1% EA 1.00
R341 139-01002-0010 RES CH 10K TW 1% EA 1.00
R342 139-01002-0010 RES CH 10K TW 1% EA 1.00
R343 139-01002-0010 RES CH 10K TW 1% EA 1.00
R344 139-01002-0010 RES CH 10K TW 1% EA 1.00
R345 139-01002-0010 RES CH 10K TW 1% EA 1.00
R346 139-01002-0010 RES CH 10K TW 1% EA 1.00
R347 139-01002-0010 RES CH 10K TW 1% EA 1.00
R348 139-01002-0010 RES CH 10K TW 1% EA 1.00
R349 139-01002-0010 RES CH 10K TW 1% EA 1.00
R350 139-01002-0010 RES CH 10K TW 1% EA 1.00
R351 139-01002-0010 RES CH 10K TW 1% EA 1.00
R352 139-01002-0010 RES CH 10K TW 1% EA 1.00
R353 139-01002-0010 RES CH 10K TW 1% EA 1.00
R354 139-01002-0010 RES CH 10K TW 1% EA 1.00
R355 139-01002-0010 RES CH 10K TW 1% EA 1.00
R356 139-01002-0010 RES CH 10K TW 1% EA 1.00
R357 139-01002-0010 RES CH 10K TW 1% EA 1.00
R358 139-01002-0010 RES CH 10K TW 1% EA 1.00
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R359 139-01002-0010 RES CH 10K TW 1% EA 1.00
R360 139-01002-0010 RES CH 10K TW 1% EA 1.00
R361 139-01002-0010 RES CH 10K TW 1% EA 1.00
R362 139-02002-0010 RES CH 20K TW 1% EA 1.00
R368 139-01002-0010 RES CH 10K TW 1% EA 1.00
R369 139-01002-0010 RES CH 10K TW 1% EA 1.00
R370 139-01002-0010 RES CH 10K TW 1% EA 1.00
R371 139-01002-0010 RES CH 10K TW 1% EA 1.00
R372 139-01002-0010 RES CH 10K TW 1% EA 1.00
R373 139-01002-0010 RES CH 10K TW 1% EA 1.00
R374 139-01002-0010 RES CH 10K TW 1% EA 1.00
R375 139-01002-0010 RES CH 10K TW 1% EA 1.00
R376 139-01002-0010 RES CH 10K TW 1% EA 1.00
R377 139-01002-0010 RES CH 10K TW 1% EA 1.00
R378 139-01002-0010 RES CH 10K TW 1% EA 1.00
R379 139-01002-0010 RES CH 10K TW 1% EA 1.00
R380 139-01002-0010 RES CH 10K TW 1% EA 1.00
R381 139-01002-0010 RES CH 10K TW 1% EA 1.00
R382 139-01002-0010 RES CH 10K TW 1% EA 1.00
R383 139-01002-0010 RES CH 10K TW 1% EA 1.00
R384 139-01002-0010 RES CH 10K TW 1% EA 1.00
R386 139-04751-0010 RES CH 4.75K .1W 1 EA 1.00
R387 139-04751-0010 RES CH 4.75K .1W 1 EA 1.00
R388 139-04751-0010 RES CH 4.75K .1W 1 EA 1.00
R389 139-04751-0010 RES CH 4.75K .1W 1 EA 1.00
R390 139-04751-0010 RES CH 4.75K .1W 1 EA 1.00
R397 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R399 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R401 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R402 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R403 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R404 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R406 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R407 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R408 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R409 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R41 139-04992-0010 RES SM 49.9K 1/10W EA 1.00
R410 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R411 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R412 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R413 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R414 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R416 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R417 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R419 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R420 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R421 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R422 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R423 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R424 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R425 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R426 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-98

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R427 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R428 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R429 139-02002-0010 RES CH 20K TW 1% EA 1.00
R43 139-01002-0010 RES CH 10K TW 1% EA 1.00
R430 139-02002-0010 RES CH 20K TW 1% EA 1.00
R431 139-02002-0010 RES CH 20K TW 1% EA 1.00
R432 139-02002-0010 RES CH 20K TW 1% EA 1.00
R433 139-02002-0010 RES CH 20K TW 1% EA 1.00
R434 139-02002-0010 RES CH 20K TW 1% EA 1.00
R435 139-02002-0010 RES CH 20K TW 1% EA 1.00
R436 139-02002-0010 RES CH 20K TW 1% EA 1.00
R437 139-02002-0010 RES CH 20K TW 1% EA 1.00
R438 139-02002-0010 RES CH 20K TW 1% EA 1.00
R439 139-02002-0010 RES CH 20K TW 1% EA 1.00
R44 139-01002-0010 RES CH 10K TW 1% EA 1.00
R440 139-02002-0010 RES CH 20K TW 1% EA 1.00
R441 139-02002-0010 RES CH 20K TW 1% EA 1.00
R442 139-02002-0010 RES CH 20K TW 1% EA 1.00
R443 139-02002-0010 RES CH 20K TW 1% EA 1.00
R444 139-02002-0010 RES CH 20K TW 1% EA 1.00
R445 139-02002-0010 RES CH 20K TW 1% EA 1.00
R446 139-02002-0010 RES CH 20K TW 1% EA 1.00
R447 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R448 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R449 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R45 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R450 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R451 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R452 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R453 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R454 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R455 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R456 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R457 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R458 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R459 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R46 139-02002-0010 RES CH 20K TW 1% EA 1.00
R460 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R461 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R462 139-02003-0010 RES CH 200K .1W 1% EA 1.00
R463 139-07503-0000 RES CHIP 750KEW1% EA 1.00
R464 139-07503-0000 RES CHIP 750KEW1% EA 1.00
R466 139-00200-0010 RES CH 20.0 .1W 1% EA 1.00
R467 139-01003-0010 RES CH 100K TW 1% EA 1.00
R468 139-01003-0010 RES CH 100K TW 1% EA 1.00
R469 139-01003-0010 RES CH 100K TW 1% EA 1.00
R47 139-07503-0000 RES CHIP 750KEW1% EA 1.00
R470 139-01003-0010 RES CH 100K TW 1% EA 1.00
R471 139-01003-0010 RES CH 100K TW 1% EA 1.00
R472 139-05110-0010 RES CH 511 .1W 1% EA 1.00
R473 139-05110-0010 RES CH 511 .1W 1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-99

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R474 139-05110-0010 RES CH 511 .1W 1% EA 1.00
R475 139-05110-0010 RES CH 511 .1W 1% EA 1.00
R476 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R477 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R478 133-00560-0006 RES VA SMD 1K QW EA 1.00
R479 139-07500-0010 RES CH 750 OHMS 1% EA 1.00
R48 139-07503-0000 RES CHIP 750KEW1% EA 1.00
R480 139-03011-0010 RES CH 3.01K .1W 1 EA 1.00
R481 139-03011-0010 RES CH 3.01K .1W 1 EA 1.00
R482 139-03011-0010 RES CH 3.01K .1W 1 EA 1.00
R483 139-03011-0010 RES CH 3.01K .1W 1 EA 1.00
R484 139-03011-0010 RES CH 3.01K .1W 1 EA 1.00
R485 139-02430-0010 RES CH 243 TW 1% EA 1.00
R486 139-02672-0010 RES CH 26.7K .1W 1 EA 1.00
R487 139-02672-0010 RES CH 26.7K .1W 1 EA 1.00
R488 139-02672-0010 RES CH 26.7K .1W 1 EA 1.00
R489 139-02672-0010 RES CH 26.7K .1W 1 EA 1.00
R490 139-02672-0010 RES CH 26.7K .1W 1 EA 1.00
R491 139-00221-0010 RES CH 22.1 TW 1% EA 1.00
R493 139-02000-0010 RES CH 200 OHMS 1% EA 1.00
R494 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R495 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R497 133-00560-0004 RES VA SMD 200 QW EA 1.00
R498 139-04991-0010 RES CH 4.99K TW 1% EA 1.00
R499 139-04991-0010 RES CH 4.99K TW 1% EA 1.00
R500 139-04991-0010 RES CH 4.99K TW 1% EA 1.00
R501 139-04991-0010 RES CH 4.99K TW 1% EA 1.00
R502 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R503 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R504 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R505 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R506 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R507 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R508 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R509 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R510 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R511 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R512 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R513 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R514 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R515 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R516 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R518 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R519 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R520 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R521 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R522 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R523 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R524 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R525 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R526 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R527 139-00000-0014 CKT JUMPER 0805 EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-100

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R529 139-00332-0010 RES CH 33.2 OHM TW EA 1.00
R53 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R530 139-00332-0010 RES CH 33.2 OHM TW EA 1.00
R532 139-00332-0010 RES CH 33.2 OHM TW EA 1.00
R533 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R534 139-02432-0010 RES CH 24300 .1W 1 EA 1.00
R535 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R536 139-07502-0000 RES CHIP 75KEW1% EA 1.00
R537 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R538 139-03242-0000 RES CH 32.4K EW 1% EA 1.00
R539 139-07501-0000 RES CHIP 7.5KEW1% EA 1.00
R540 139-01623-0010 RES CH 162000 .1W EA 1.00
R543 015-00309-1002 RES ARRAYS 10K OHM EA 1.00
R545 139-03320-0000 RES CHIP 332 EW 1% EA 1.00
R546 139-03320-0000 RES CHIP 332 EW 1% EA 1.00
R547 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R548 139-01000-0000 RES CHIP 100 EW 1% EA 1.00
R549 139-00511-0010 RES CH 51.1 .1W 1% EA 1.00
R55 139-05110-0010 RES CH 511 .1W 1% EA 1.00
R550 139-00511-0010 RES CH 51.1 .1W 1% EA 1.00
R551 139-06810-0010 RES CH 681 .1W 1% EA 1.00
R552 139-02212-0010 RES CH 22.1K TW 1% EA 1.00
R554 139-00100-0010 RES CH 10 OHMS 1% EA 1.00
R556 139-04751-0010 RES CH 4.75K .1W 1 EA 1.00
R557 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R558 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R56 139-05110-0010 RES CH 511 .1W 1% EA 1.00
R561 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R562 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R563 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R564 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R565 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R566 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R567 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R569 139-01002-0010 RES CH 10K TW 1% EA 1.00
R570 139-01002-0010 RES CH 10K TW 1% EA 1.00
R571 139-01002-0010 RES CH 10K TW 1% EA 1.00
R572 133-00560-0011 RES VA SMD 50K QW EA 1.00
R573 139-07500-0010 RES CH 750 OHMS 1% EA 1.00
R574 139-08250-0010 RES CH 825 .1W 1% EA 1.00
R575 139-07500-0010 RES CH 750 OHMS 1% EA 1.00
R576 133-00560-0003 RES VA SMD 100 QW EA 1.00
R577 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R580 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R581 139-01002-0010 RES CH 10K TW 1% EA 1.00
R582 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R583 139-01623-0010 RES CH 162000 .1W EA 1.00
R584 999-09999-9999 PLACE HOLDER RF .00
R585 139-03323-0010 RES CH 332K TW 1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-101

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R586 139-02002-0010 RES CH 20K TW 1% EA 1.00
R587 139-02002-0010 RES CH 20K TW 1% EA 1.00
R588 139-01002-0010 RES CH 10K TW 1% EA 1.00
R591 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R592 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R593 139-00000-0014 CKT JUMPER 0805 EA 1.00
R594 139-00000-0014 CKT JUMPER 0805 EA 1.00
R595 139-00000-0014 CKT JUMPER 0805 EA 1.00
R596 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R597 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R598 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R599 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R600 139-04991-0010 RES CH 4.99K TW 1% EA 1.00
R601 139-04991-0010 RES CH 4.99K TW 1% EA 1.00
R602 139-00332-0010 RES CH 33.2 OHM TW EA 1.00
R603 139-00000-0014 CKT JUMPER 0805 EA 1.00
R604 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R605 139-03323-0010 RES CH 332K TW 1% EA 1.00
R607 139-04022-0000 RES CHIP 40.2KEW1% EA 1.00
R608 139-04022-0000 RES CHIP 40.2KEW1% EA 1.00
R609 139-00750-0000 RES CH 75.0 EW 1% EA 1.00
R61 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R610 139-00750-0000 RES CH 75.0 EW 1% EA 1.00
R611 139-01002-0010 RES CH 10K TW 1% EA 1.00
R612 139-01002-0010 RES CH 10K TW 1% EA 1.00
R613 139-01002-0010 RES CH 10K TW 1% EA 1.00
R614 139-03320-0010 RES CH 332 .1W 1% EA 1.00
R615 139-01002-0010 RES CH 10K TW 1% EA 1.00
R616 139-01002-0010 RES CH 10K TW 1% EA 1.00
R617 139-01501-0010 RES CH 1500 .1W 1% EA 1.00
R618 139-01002-0010 RES CH 10K TW 1% EA 1.00
R619 139-01002-0010 RES CH 10K TW 1% EA 1.00
R62 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R66 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R67 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R68 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R70 139-01000-0010 RES CH 100 .1W 1% EA 1.00
R80 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R82 139-01003-0010 RES CH 100K TW 1% EA 1.00
R83 139-02802-0010 RES CH 28K TW 1% EA 1.00
R84 139-07501-0010 RES CH 7.5K .1W 1% EA 1.00
R85 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
T1 019-05099-0000 XFMR AUD EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-102

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
U1 120-02831-0003 80C186, 16 BIT MIC EA 1.00
U13 120-02716-0017 1-BIT LOW POWER BU EA 1.00
U16 120-02788-0001 TRANSLATOR, 10-BIT EA 1.00
U18 120-08212-0001 ARINC 429 XCVER EA 1.00
U19 120-02778-0001 UART, QUAD W/FIFO, EA 1.00
U2 120-02843-0070 SRAM, 3.3V EA 1.00
U20 120-03774-0001 RS-232 LINE DRIVER EA 1.00
U21 120-03163-0001 LM2901 SO-14 COMP EA 1.00
U22 120-03163-0001 LM2901 SO-14 COMP EA 1.00
U23 120-03163-0001 LM2901 SO-14 COMP EA 1.00
U3 120-02836-0070 FLASH MEMORY, TSOP EA 1.00
U30 120-03127-0011 IC LM2903 SO PKG EA 1.00
U32 120-03858-0005 3.3V MICROPROCESSO EA 1.00
U33 120-02850-0105 I.C., SINGLE GATE EA 1.00
U38 120-03593-0000 QUAD SW DG442 EA 1.00
U39 120-03593-0000 QUAD SW DG442 EA 1.00
U40 120-03174-0013 OP AMP BI FET SO EA 1.00
U41 120-03844-0031 3.3V RS485/RS422 T EA 1.00
U43 120-03127-0011 IC LM2903 SO PKG EA 1.00
U44 120-03843-0001 12-BIT A/D CONVERT EA 1.00
U45 120-02885-0322 SERIAL EEPROM EA 1.00
U46 120-03163-0001 LM2901 SO-14 COMP EA 1.00
U47 120-03127-0011 IC LM2903 SO PKG EA 1.00
U5 120-02884-4424 FIELD PROGRAMMABLE EA 1.00
U57 120-03436-0002 ADJ. SHUNT REGULAT EA 1.00
U58 120-03593-0000 QUAD SW DG442 EA 1.00
U60 120-03889-0002 9 BIT TEMPERATURE EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-103

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
U61 120-03899-0001 LOG TAPER DIGITAL EA 1.00
U69 120-03593-0000 QUAD SW DG442 EA 1.00
U7 120-03436-0002 ADJ. SHUNT REGULAT EA 1.00
U70 120-02551-0002 IC SPEECH SYNTHNE EA 1.00
U71 120-03065-0026 IC MC78L05ABD EA 1.00
U72 120-03174-0013 OP AMP BI FET SO EA 1.00
U73 120-03506-0000 MC33178 OP AMP EA 1.00
U9 120-03648-0001 LM337LM 3 TERMINA EA 1.00
Y1 044-00373-4000 XTAL OSC, SMD EA 1.00
002-09321-0000 SCHEMATIC, MAIN BO RF .00
009-09321-0000 PRINTED CIRCUIT BO RF .00
009-09321-0001 KT 73 PRINTED CIRC EA 1.00
047-09573-0003 FENCE W/PLATING EA 1.00
047-09574-0001 MAINBD COVER TOP EA 1.00
047-09575-0001 MAINBD FENCE BOT EA 1.00
047-09576-0001 MAINBD COVER BOT EA 1.00
047-12848-0002 SHIELD WITH FINISH EA 1.00
076-02234-0001 SPACER SWAGE EA 1.00
076-02241-0001 STAND-OFF SWAGE EA 1.00
089-06004-0002 SCR FHP 2-56X1/8 EA 4.00
300-09321-0000 ASSEMBLY, MAIN BOA RF .00
Rev. 1, May/2003 15563M01.JA Page 6-104

B KT 73
FIGURE 6-17 KT 73 MAIN BOARD

(Dwg. No. 300-09321-0000 R-E, Sheet 1 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-105

B KT 73

(Dwg. No. 300-09321-0000 R-E, Sheet 2 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-107

B KT 73

(Dwg. No. 300-09321-0000 R-E, Sheet 3 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-109

B KT 73

(Dwg. No. 300-09321-0000 R-E, Sheet 4 of 4)
Rev. 1, May/2003 15563M01.JA Page 6-111

B KT 73
FIGURE 6-18 KT 73 MAIN BOARD SCHEMATIC

(Dwg. No. 002-09321-0000 R-C, Sheet 1 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-113

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 2 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-115

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 3 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-117

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 4 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-119

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 5 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-121

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 6 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-123

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 7 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-125

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 8 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-127

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 9 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-129

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 10 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-131

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 11 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-133

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 12 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-135

B KT 73

(Dwg. No. 002-09321-0000 R-C, Sheet 13 of 13)
Rev. 1, May/2003 15563M01.JA Page 6-137

B KT 73
6.16 KT 73 POWER SUPPLY BOARD
200-09862-0000 KT 73 POWER SUPPLY Rev. C

---------------------------------------------------------------
---------------------------------------------------------------
C1 097-00207-0006 CAP AL 330UF 50V EA 1.00
C10 106-04562-0057 CAPCH5600PFX7R/100 EA 1.00
C11 106-04104-0047 CH 100KX7R/50V EA 1.00
C12 097-00207-0006 CAP AL 330UF 50V EA 1.00
C13 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C14 097-00217-0013 CAP EL 220UF 10V EA 1.00
C15 097-00217-0013 CAP EL 220UF 10V EA 1.00
C16 097-00217-0013 CAP EL 220UF 10V EA 1.00
C18 097-00217-0013 CAP EL 220UF 10V EA 1.00
C19 097-00217-0013 CAP EL 220UF 10V EA 1.00
C2 106-04104-0047 CH 100KX7R/50V EA 1.00
C20 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C21 097-07000-6101 CAP AL LOW ESR SMT EA 1.00
C22 106-04561-0016 CAP CH560PFNPO/50V EA 1.00
C23 106-04104-0047 CH 100KX7R/50V EA 1.00
C24 106-04104-0047 CH 100KX7R/50V EA 1.00
C25 097-00207-0006 CAP AL 330UF 50V EA 1.00
C26 097-00207-0006 CAP AL 330UF 50V EA 1.00
C27 106-05821-0047 CAP CH820PFX7R/50V EA 1.00
C28 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C29 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C3 097-00104-0036 CAP AL 47UF 25V EA 1.00
C30 097-00217-0008 CAP AL/0 68UF 20V EA 1.00
C32 097-07000-4515 CAP AL LOW ESR 220 EA 1.00
C33 097-00217-0008 CAP AL/0 68UF 20V EA 1.00
C35 097-07000-4515 CAP AL LOW ESR 220 EA 1.00
C44 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C45 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C46 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C47 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C48 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C49 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C5 106-04820-0026 CAP CH82PFNPO/100V EA 1.00
C50 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C51 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C52 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C53 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C54 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C55 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C56 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C57 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C58 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C59 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C6 097-07000-6101 CAP AL LOW ESR SMT EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-139

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
C60 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C61 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C62 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C63 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C64 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C65 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C7 106-04561-0016 CAP CH560PFNPO/50V EA 1.00
C8 106-04104-0047 CH 100KX7R/50V EA 1.00
C9 106-05153-0047 CAP CH 15K X7R/50V EA 1.00
CR1 007-05039-0002 DIO Z 40.2V EA 1.00
CR10 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR11 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR12 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR13 007-06175-0003 DIO MUR460 EA 1.00
CR14 007-06141-0001 DIO UF RECOV 200V EA 1.00
CR16 007-06175-0001 DIO RECT EA 1.00
CR2 007-06088-0001 DIO HC VSK140 EA 1.00
CR3 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR4 007-05115-0008 DIO Z 1N5526B EA 1.00
CR5 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR6 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR8 007-06175-0001 DIO RECT EA 1.00
L1 019-02695-0000 INDUCTOR EA 1.00
L2 019-02695-0000 INDUCTOR EA 1.00
L3 019-02084-0057 CH 33UH 10% EA 1.00
L5 019-02696-0000 INDUCTOR 51UH EA 1.00
L6 019-02696-0000 INDUCTOR 51UH EA 1.00
L7 019-02696-0000 INDUCTOR 51UH EA 1.00
P1 030-02174-0002 PIN CONN MALE EA 18.00
Q1 007-00335-0002 XSTR S PNP TIP42B EA 1.00
Q2 007-00467-0000 XSTR S NPN MMBTA06 EA 1.00
Q5 007-00542-0000 XSTR PNP MMBTA64 EA 1.00
Q7 007-00542-0000 XSTR PNP MMBTA64 EA 1.00
Q9 007-00813-0000 XSTR NPN S MMBTA14 EA 1.00
R1 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R10 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R11 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R12 139-09092-0000 RES CHIP 90.9KEW1% EA 1.00
R13 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R14 139-01212-0000 RES CHIP 12.1K1%EW EA 1.00
R15 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R16 133-00113-0014 RES VA 2K 20% A EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-140

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R17 139-01022-0000 RES CHIP 10.2KEW1% EA 1.00
R18 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R19 139-01502-0000 RES CHIP 15K EW 1% EA 1.00
R2 139-08251-0000 RES CH 8.25K EW 1% EA 1.00
R20 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R21 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R22 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R23 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R24 132-05046-0000 RES WW .05 2W 5% EA 1.00
R25 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R26 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R28 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R29 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R3 139-04750-0000 RES CH 475 EW 1% EA 1.00
R30 139-00000-0004 RES CH 0 EW EA 1.00
R31 139-05111-0000 RES CHIP 5.11KEW1% EA 1.00
R32 139-04751-0000 RES CH 4.75K EW 1% EA 1.00
R33 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R34 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R35 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R36 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R37 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R38 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R39 139-08871-0000 RES CH 8.87K EW 1% EA 1.00
R4 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R40 139-02552-0000 RES CH 25.5K EW 1% EA 1.00
R41 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R42 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R43 139-03320-0000 RES CHIP 332 EW 1% EA 1.00
R44 139-02430-0010 RES CH 243 TW 1% EA 1.00
R46 139-01212-0000 RES CHIP 12.1K1%EW EA 1.00
R47 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R48 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R49 139-01502-0000 RES CHIP 15K EW 1% EA 1.00
R5 139-01302-0000 RES CH 13K EW 1% EA 1.00
R50 139-05622-0000 RES CH 56.2K EW 1% EA 1.00
R51 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R52 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R53 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R54 132-00206-0000 RES WW .01 1% 4W EA 1.00
R55 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R56 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R57 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R58 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R59 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R6 139-04321-0000 RES CH 4.32K EW 1% EA 1.00
R7 139-01101-0000 RES CH 1.1K EW 1% EA 1.00
R74 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R75 139-00000-0004 RES CH 0 EW EA 1.00
R76 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R77 133-00100-0033 RES VA 100 QW 10% EA 1.00
R8 139-05110-0000 RES CH 511 EW 1% EA 1.00
Rev. 1, May/2003 15563M01.JA Page 6-141

B KT 73
---------------------------------------------------------------
---------------------------------------------------------------
R9 139-01003-0000 RES CHIP 100KEW1% EA 1.00
T1 019-07252-0000 XFMR FLYBACK EA 1.00
T2 019-07251-0000 XFMR FLYBACK EA 1.00
U1 120-03126-0005 LM317L EA 1.00
U2 120-03127-0014 LM 293 D EA 1.00
U3 120-02679-0001 NAND GATE, SINGLE EA 1.00
U4 120-03430-0000 IC 2843 EA 1.00
U5 120-03127-0014 LM 293 D EA 1.00
U6 120-03126-0006 IC LM317BT EA 1.00
U7 120-03026-0000 IC MC7805CT EA 1.00
U8 120-03430-0000 IC 2843 EA 1.00
U9 120-02679-0001 NAND GATE, SINGLE EA 1.00
002-09862-0000 KT 73 POWER SUPPLY RF .00
012-01005-0003 TAPE MYLAR .250 W IN 1.50
016-01082-0000 DC RTV 3145 AR 1.00
073-00892-0001 RIGHT RAIL & HT SK EA 1.00
089-05901-0004 SCR PHP 3-48X1/4 EA 2.00
089-05903-0004 SCR PHP 4-40X1/4 EA 5.00
091-00156-0000 BUSHING EA 4.00
091-00286-0002 INSUL XSTR .687 EA 4.00
300-09862-0000 KT 73 POWER SUPPLY RF .00
Rev. 1, May/2003 15563M01.JA Page 6-142

B KT 73
FIGURE 6-19 KT 73 POWER SUPPLY BOARD

(Dwg. No. 300-09862-0000 R-D, Sheet 1 of 3)
Rev. 1, May/2003 15563M01.JA Page 6-143

B KT 73

(Dwg. No. 300-09862-0000 R-D, Sheet 2 of 3)
Rev. 1, May/2003 15563M01.JA Page 6-145

B KT 73

(Dwg. No. 300-09862-0000 R-D, Sheet 3 of 3)
Rev. 1, May/2003 15563M01.JA Page 6-147

B KT 73
FIGURE 6-20 KT 73 POWER SUPPLY BOARD SCHEMATIC

(Dwg. No. 002-09862-0000 R-B, Sheet 1 of 2)
Rev. 1, May/2003 15563M01.JA Page 6-149

B KT 73
FIGURE 6-20 KT 73 POWER SUPPLY BOARD SCHEMATIC

(Dwg. No. 002-09862-0000 R-B, Sheet 2 of 2)
Rev. 1, May/2003 15563M01.JA Page 6-151

B KT 73
CONFIGURATION APPENDIX
HARDWARE/SOFTWARE
Rev. 1, May/2003 15563M01.JA Page APP-1

B KT 73

B KT 73
KT 73 HARDWARE/SOFTWARE CONFIGURATIONS
(Sheet 1 of 2)

B KT 73
KT 73 HARDWARE/SOFTWARE CONFIGURATIONS
(Sheet 2 of 2)

Maintenance Manual: MANUAL NUMBER 006-15563-0001 Revision 1 May, 2003

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Maintenance Manual: MANUAL NUMBER 006-15563-0001 Revision 1 May, 2003

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MAINTENANCE MANUAL

MANUAL NUMBER 006-15563-0001

©2003 Honeywell International Inc.

Part Number: 006-15563-XXXX

For each revision, add, delete, or replace pages as indicated.

REVISION: Rev. 0, April/2003

REVISION: Rev. 1, May/2003

Rev. 1, May/2003 15563M01.JA Page RH-1

THIS PAGE IS RESERVED

Rev. 1, May/2003 15563M01.JA Page RH-2

4.1 GENERAL 4-1

5.1 INTRODUCTION 5-1

Rev. 1, May/2003 15563M01.JA Page TC-1

5.2.5 RETURN TO SERVICE TESTS 5-15

6.1 GENERAL 6-1

Rev. 1, May/2003 15563M01.JA Page TC-2

6.14 KT 73 RECEIVER BOARD 6-65

KT 73 HARDWARE/SOFTWARE CONFIGURATIONS APP-1

4-1 MODE S TRANSPONDER SYSTEM, SIMPLIFIED BLOCK DIAGRAM 4-2

Rev. 1, May/2003 15563M01.JA Page TC-3

5-1 KT73 TRANSPONDER, TEST SETUP 5-5

Rev. 1, May/2003 15563M01.JA Page TC-4

5-33 WAVEFORM 26 5-88

Rev. 1, May/2003 15563M01.JA Page TC-5

6-4 KT 73 TRANSMITTER BOARD 6-19

5-1 Q8 MIXER 5-25

Rev. 1, May/2003 15563M01.JA Page TC-6

Rev. 1, May/2003 15563M01.JA Page 4-1

The main functions of the transponder are summarized below:

FIGURE 4-1 MODE S TRANSPONDER SYSTEM, SIMPLIFIED BLOCK DIAGRAM

Rev. 1, May/2003 15563M01.JA Page 4-2

4.1.1 INTERROGATOR-TRANSPONDER INTERACTION

4.1.2 INTERROGATION FORMATS

Rev. 1, May/2003 15563M01.JA Page 4-3

FIGURE 4-2 ATCRBS INTERROGATION PULSES FORMAT

FIGURE 4-3 ATCRBS/MODE S ALL-CALL FORMAT

Rev. 1, May/2003 15563M01.JA Page 4-4

FIGURE 4-4 SIDE LOBE SUPPRESSION CHARACTERISTICS

The KT 73 responds to these ATCRBS interrogations with standard ATCRBS reply

Rev. 1, May/2003 15563M01.JA Page 4-5

FIGURE 4-5 MODE S INTERROGATION, UPLINK FORMAT

Rev. 1, May/2003 15563M01.JA Page 4-6

UPLINK BINARY DATA FIELDS AND NUMBER OF BITS FUNCTIONS

4 0 0100 PC:3 RR:5 DI:3 SD:16 AP:24 Surveillance, Altitude

20 1 0100 PC:3 RR:5 DI:3 SD:16 MA:56 AP:24 Surveillance, Altitude

FIGURE 4-6 UPLINK FORMATS

Rev. 1, May/2003 15563M01.JA Page 4-7

3. DI (Designator Identification): identifies the coding contained in the SD field (ex-

Rev. 1, May/2003 15563M01.JA Page 4-8

4. SD (Special Designator): contains control codes affecting transponder protocol.

Rev. 1, May/2003 15563M01.JA Page 4-9

4.1.3 MODE S TRANSMISSION CONTENT

Rev. 1, May/2003 15563M01.JA Page 4-10

FIGURE 4-7 ATCRBS AND MODE S REPLY FORMAT

Rev. 1, May/2003 15563M01.JA Page 4-11

Rev. 1, May/2003 15563M01.JA Page 4-12

DOWNLINK BINARY DATA FIELDS AND

NOTE: Downlink format 16 is required only with TCAS operation.

Rev. 1, May/2003 15563M01.JA Page 4-13

FIGURE 4-8 DOWNLINK FORMATS

Rev. 1, May/2003 15563M01.JA Page 4-14

2. DR (Downlink Request): used to request extraction of downlink messages from

Rev. 1, May/2003 15563M01.JA Page 4-15