VLSI with VHDL. Course Code: 22062 Program Name __: Electronics Engineering Programme Group Program Code DE/EMET/EN/EX/EQ Semester sixth Course Title : VLSI with VADL Course Code +: 22062 1. RATIONALE In the present scenario of electronics technology, CMOS is a vital important and basic need in the design/development of almost all products in the range from consumer to industrial and telecommunication engineering area, Functional capabilities of this technology leads to advanced Very Large Scale Integration, large density of components, high speed of operation, less area with less power dissipation. Therefore imparting knowledge of VLSI and its tools is need of today. After completion of this course, students will be able to develop applications in the area of digital electronics using VLSI design tools. 2. COMPETENCY The aim of this course is to help the student to attain the following industry identified competency through various teaching learning experiences: © Maintain VLSI based electronic circuits . 3. COURSE OUTCOMES (COs) The theory, practical experiences and relevant soft skills associated with this course are to be taught and implemented, so that the student demonstrates the following industry oriented COs associated with the above mentioned competency: Develop design flow for the given application using VLSI tools. Interpret CMOS technology circuits with their specifications, Use relevant VHDL model for given application. Debug VHDL program for the given application. Maintain FPGA based circuits seoge 4. TEACHING AND EXAMINATION SCHEME Examination Scheme | tests = = u|v|e err E E [PA Total Max [Min Min Max | Min | Max | Min | Max | Min 2[-|2 4 - wfaf- 2s# | 10 | 25- 10 50. 20 (*): Under the theory PA, Out of 30 marks, 10 marks are for micro-project assessment 10 facilitate integration of COs and the remaining 20 marks is the average of 2 tests 10 be taken during the semester for the assessment of the cognitive domain UOs required for the attainment of the COs. Tutorial/Teacher Guided Theory Practice; P - Practical; C ~ Credit, MSBTE — Final Copy Dt. 24.09.2019 Page 1 of 8VLSI with VADL Course Code: 22062 This course map illustrates an overview of the flow and linkages of the topies at various levels of ‘outcomes (details in subsequent sections) to be attained by the student by the end of the course, in all domains of learning in terms of the industry/employer identified competency depicted at the centte of this map. Figure 1 - Course Map. ~ - 6. SUGGESTED PRACTICALS/ EXERCISES The practicals in this section are PrOs (i.e. sub-components of the COs) to be developed and assessed in the student for the attainment of the competency. ‘Approx. z Practical Outcomes (PrOs) Wait | ks. lo. No. | required T | Identify internal block and pin configuration of FPGA & CPLD T oo |_| using datasheet. 2 | Develop flow chart of CMOS IC Tabrication using relevant website. | Il oF 3 Install EDA tool (VHDL) for VLSI application. i | o* 4 [Implement any two gates using Data flow and Behavioral model iv_ | 0* [Implement Half /full adder /subtractor using FPGA eo) Iv @ MSBTE ~ Final Copy Dt. 24.09.2019 Page 2 of 8 aVLSI with VHDL, Course Code: 22062 | Approx. oe Practical Outcomes (PrOs) unit | Tire No. No. ; ‘ required 6 | Implement 8:1 multiplexer using FPGA - w | 7__| Implement 1:8 Demultiplexer using FPGA iv_| 02 8 ___| Implement T& D-flip-flop using FPGA. ~ IV 02 9 | Implement 2:4 Decoder using FPGA W_ | 02 10 | Implement 8°3 Encoder using FPGA W | 02 11 [Implement up-counter using FPGA iv} 02 12__[ Implement synchronous counter using FPGA Ww | 13_[ Implement binary to gray code converter using FPGA. v_|_@ 14_| Build Test DAC using FPGA v_[_a 15 _[ Implement Stepper motor controller using FPGA. Vv a 16~_[ Implement four Bit ALU or sequence generator using FPGA. v_|_ Total 32 Note i. A suggestive list of PrOs is given in the above table. More such PrOs can be added to attain the COs and competency. A judicial mix of minimum 12 or more practical need to be performed, out of which, the practicals marked as ‘*’ are compulsory, so that the student reaches the ‘Precision Level’ of Dave's ‘Psychomotor Domain Taxonomy’ as generally required by the industry. Ji, The ‘Process’ and ‘Product’ related skills associated with each PrO is to be assessed according to a suggested sample given below: S.No. Performance Indicators Weightage in % a. Preparation of experimental set up 20 b. Setting and operation 20 c Safety measures _| 10 4 Observations and Recording _ 10 e Interpretation of result and conclusion 2 f ‘Answer to sample questions - 10 B Submission of report in time — 10 Total 100 The above PrOs also comprise of the following social skills/attitudes which are Affective Domain Outcomes (ADOs) that are best developed through the laboratory/field based experiences: Follow safety practices. Practice good housekeeping. Demonstrate working as a leader/a team member. Maintain tools and equipment. Follow ethical practices. The ADOs are not specific to any one PrO, but are embedded in many PrOs. Hence, the acquisition of the ADOs takes place gradually in the student when s/he undertakes a series of practical experiences over a period of time. Moreover, the level of achievement of the ADOs according to Krathwohl’s ‘Affective Domain Taxonomy” “ons gy increase as planned 90 epaese below: 50 MSIE — Final Copy Bu. 24.09.2019 Paeesore 7 aVLSI with VHDL. 7. “Valuing Level’ in 1" year “Organizing Level’ in 2” year “Characterizing Level’ in 3" year. Course Code: 22062 MAJOR EQUIPMENT/ INSTRUMENTS REQUIRED The major equipment with broad specification mentioned here will usher in uniformity in conduct of experiments, as well as aid to procure equipment by authorities concerned. No Equipment Name with Broad Specifications : a | Personal Computer with latest configuration, All 2 [FPGA trainer kit with accessories — 10-15, 3 | VLSI trainer kit along with peripherals such as switches, Keyboard, LEDs, seven | 1-15 segment display. 4__| VLSI trainer kit along with DAC, ADC trainer kit 115 5__| ViSItrainer kit along with stepper motor. ~ 1-15 6 ITAG cable, DMM, Bread Board. 1-16 7_| Xilim/Altera or equivalent EDA tool. B 8. _ UNDERPINNING THEORY COMPONENTS. ‘The following topics/subtopics should be taught and assessed in order to develop UOs in cognitive domain for achieving the COs to attain the identified competency. Unit Incoming tower ‘Topies and Sub-topies Unit—1 Ta. Differentiate between 1 Review of Sequential Logie : Advanced asynchronous and synchronous | Asynchronous and Synchronous, Digital logic circuit forthe given Metastability, Noise margins, Power Design and parameters. Fan-out, Skew (Definitions only) ASIC, FPGA,| Ib. Develop the state diagram, state | 1.2 Moore and Mealy Models, state PLD. table forthe given sequential machine notation, logic. 1.3. Examples on Moore and mealy: le, Develop model of Moore and counter, sequence detector only Mealy machine of the given | 1.4 ASIC design flow Contents 1.5 CPLD - Details of internal block 1d. Describe the given ASIC, FPGA| diagram and CPLDs. 1.6 FPGA - architecture, details of | internal block diagram MSBTE ~ Final Copy Dt. 24.09.2019 Page 4 of 8VLSI with VHDL Course Code: 22062 . Unit Outcomes (UOs) Fr . Unit (in cognitive domain) Topies and Sub-topies Unit 1 2a, Compare the performance of | 2.1 Introduction of BJT and CMOS cmos BJT and CMOS for the given parameters ‘Technology parameters. 2.2 Basic gates using CMOS Inverter, concepts. | 2b. Draw the simplified CMOS logic] NOR, NAND, MOS transistor of the given gates. switches, transmission gates, CMOS 2c. Explain CMOS inverter inverter characteristics. characteristics with relevant | 2.3 Complex logic using CMOS. sketch. 2.4 Estimation of resistance and 2d. Describe the given MOS capacitance layout. fabrication process. 2.5 Fabrication process: Overview of wafer processing, Oxidation, epitaxy, deposition, 1on—Implementation and diffusion, silicon gate process. 2.6 Basics of NMOS, PMOS and CMOS: _ nwell, pwell, twin tub process. Unit 111 3a. Describe Hardware description [3.1 Introduction to HDL: History of Introduction Janguage, its components and VHDL, Pro’s and Con’s of VHDL to VHDL programming syntax. 3.2 VHDL Flow elements:-Entity, 3b. Describe the given VHDL flow | Architecture, configuration, package, elements. rary only definitions, 3c. Describe the use of given data | 3.3 Data Types, operators, operations. type declaration in VHDL. 3.4 Signal, constant and variables (syntax 3d. Describe the given type of and use). VHDL modeling. 3.5 VHDL Modeling: - Data flow, Behavioral, Structural | Unit-1V 4a, Develop program using 4.1 Concurrent constructs (when, with), VHDL concurrent statements for the | 4.2 Sequential Constructs (process, if, Programming, __ given application in VHDL. case, loop, assert, wait) 2 4b. Develop program using 4.3 VHDL program to implement Flip sequential statements for the Flop, Counter, shift register, MUX, given application in VHDL. DEMUX, ENCODER, DECODER, 4c, Develop program to implement MOORE, MEALY machines . the given combinational 4.4 Test bench and its applic /sequential logic circuit using VHDL. 4d, Describe the test bench for the given application in VHDL. Unit-V 5a. Describe VHDL simulation for | 5.1 Event scheduling, sensitivity list, HDL the given application. zero modeling, simulation cycle, Simulation | 5b, Draw HDL design flow of comparison of software and hardware and synthesis for the given description language, delta delay. Synthesis. application. 5.2. HDL Design flow for synthesi Se. Describe use of efficient coding | 5.3 Efficient Coding Styles, Optimizing styles, optimizing expression, sharing of complex operator. arithmetic expression, sharing of complex operator. MSBTE — Final Copy Dt. 24.09.2019 Page 5 of 8 orVLSI with VDL Course Code: 22062 Note: To attain the COs and competency, above listed UOs need (o be undertaken to achieve the ‘Application Level’ and above of Bloom's ‘Cognitive Domain Taxonomy’. 9. SUGGESTED SPECIFICATION TABLE FOR QUESTION PAPER DESIGN Unit Title Teaching | Distribution of Theory Marks Hours R U A Total a | Level | Level | Level | Marks Introduction to Advanced Digital "| Not Applicable as no theory paper I Design Specific & and ASIC, FPGA, 06 PLD. _ II_ | Introduction to CMOS Technology 04 TIL_| Introduction to VHDL 08 1V_| VHDL Programmin 08 v HDL Simulation and Synthe: 06 - Total| 32 _ Legends: R=Remember, U=Understand, A=Apply and above (Bloom's Revised taxonomy) Note: This specification table provides general guidelines to assist student for their learning and to teachers (0 teach and assess students with respect to attainment of UOs. The actual distribution of marks at different taxonomy levels (of R, U and A) in the question paper may vary from above table. 10. SUGGESTED STUDENT ACTIVITIES Other than the classroom and laboratory learning, following are the suggested student-related co- curricular activities which can be undertaken to accelerate the attainment of the various outcomes in this course: Students should conduct following activities in group and prepare reports of about 5 pages for each activity, also collect/record physical evidences for their (student's) portfolio which will be useful for their placement interviews: a, Prepare the survey report on the VLSI based applications. b. Compare technical specifications and applications of various types of memory, CPLDs, FPGA and Prepare report. c. Refer basic requirement of PC configuration to install VLSI EDA tool. 4d. Give seminar on any course relevant topic. €. Conduct library / internet survey regarding different data shect and manuals related CPLD, FPGA. {. Prepare power point presentation on VLSI and their applications. g. Undertake a market survey of companies profile related to VLSI and prepare report. h. Search for video / animations / power point presentation on internet for complex topic related to the course and make a presentation. i. SUGGESTED SPECIAL INSTRUCTIONAL STRATEGIES (if any) These are sample strategies, which the teacher can use to accelerate the attainment of the various learning outcomes in this course: a, Massive open online courses (MOOCs) may be used to teach various topics/sub topics. b. ‘L"in item No. 4 does not mean only the traditional lecture method, but different types of teaching methods and media that are to be employed to develop the outcomes. MSBTE ~ Final Copy Dt. 24.09.2019 Page 6 of 8 orVLSI with VHDL. Course Code: 22062 c. About 15-20% of the topics/sub-topics which is relatively simpler or descriptive in nature is to be given to the students for self-directed learning and assess the development of the COs through classroom presentations (see implementation guideline for details). d. With respect to item No.10, teachers need to ensure to create opportunities and provisions for co-curricular activities. e. Guide student(s) in undertaking micro-projects. f. PPTs/Animations may be used to explain the construction and working of electronic circuits. g. Guide students for using data sheets / manuals. 12. SUGGESTED MICRO-PROJECTS. Only one micro-project is planned to be undertaken by a student assigned to him/her in the beginning of the semester. S/he ought to submit it by the end of the semester to develop the industry oriented COs. Each micro-project should encompass two or more COs which are in fact, an integration of PrOs, UOs and ADOs. The micro-project could be industry application based, internet-based, workshop-based, laboratory-based or field-based. Each student will have to maintain dated work diary consisting of individual contribution in the project work and give @ seminar presentation of it before submission. The total duration of the micro-project should not be less than 16 (sixteen) student engagement hours during the course. In the first four semesters, the micro-project could be group-based. However, in higher semesters, it should be individually undertaken to build up the skill and confidence in every student to become problem solver so that s/he contributes to the projects of the industry. A suggestive list is given here. Similar micro-projects could be added by the concerned faculty: Prepare report of CMOS fabrication process. Market Survey related to CMOS IC’s and prepare report, Develop four bit addition/subtraction. Develop square wave generator of Frequeney = 1Hz/ 100Hz. A shopkeeper requires an alarm system when a customer enters into the shop through exits door. Develop a VLSI based system. f. An indication for any maloperation in the given application is to be indicated by blinking of LEDs. Build a VLSI based system for the same. saore Note: Use FPGA kit and general purpose PCB for making micro projects 13, SUGGESTED LEARNING RESOURCES NS. Litle of Book ‘Author; Publication 5 Pearson Education India, 2011 1 | VHDL Basics to Gaganpreet Kaur | ISBN 10: 8131732118 | Programming ISBN 13: 9788131732113 _ C.L Engineering, 2 a Koel design [J0hMM. Yarbrough | ISBN 10: 0314066756 ISBN 13: 978 pplication and design 0314066756 MSBTE — Final Copy Di. 24.09.2019 Page 7 of 8 orVLSI with VADL Course Code: 22062 S| Title of Book mntior Publication ‘An engineering Prentice- Hall of India 3 | approach to digital | Willian J. Fletcher | ISBN-13: 978-0132776998 design ISBN-10: 0132776995 | Principles of CMOS ane Pearson Education 4 | VLSI Design: A system | Ron IEE: Neste | ISBN 10: 0201082225 / ISBN perspective *shraghian | 13. 9780201082227 Tata Megraw-hill; 4 edition (2002) VHDL programming ISBN-10: 0070499446 5 | by example Douglas Perry ISBN-13: 978-0070499447 McGraw Hill | 6 | puoduction VLSI | Eugene D. Fabricus | ISBN-13: 978-0070199484 ha ISBN-10: 0070199485 Scitech Publications (India) Pvt Ltd VLSI design and EDA (December , 2013) T | tools Sarkar & Sarkar | FSBN-10: 8183714978 ISBN-13; 978-8183714976 8 | Xitinx Manual Xilinx woww.xilinx.com 14, SUGGESTED SOFTWARE/LEARNING WEBSITES a hitp:/etetf.bg.ac.rs/ti/tiSrv\/tutorial/TUTORIAL/HTML/HOMEPG.HTM b,_ hitp:/fiith.vlab.co.in/?sub=2 &breh=664esim=53 1 &ent=1 &lan=en-IN c._ http://www.vlsiencyclopedia.com/2012/12/loop-statement. htm! 4. https:/?books. google.co.in/books?id=RjdY EY 8dvwC&pg-SA3-PA47&Ipe-SA3- PAA7&dq=visi+next+statement&source=bl&ots~oS8dgIuQL 6&sig=K HqaQMigQsCW kpC_e8Y few_7h208&chl=enéesa=X&ved=OahUKEwjx_ SLOKSbLAVRSo4K HeoGDDM Q6AEIP|AN#v=onepage&q=visi2e20next”420statement&i=false e. http:/only-visi.blogspot.in/2007/12/vlsi-design-flow.html fhutp:/Avww.vhdl.renerta.com/source/vhd000 4. htm ghup://www.csee.umbe.edu/portal/help/ VHDL/summary. hl h._hutps//vlab,eo.in/ba_tabs_all.php?id=1 MSBTE ~ Final Copy Dt. 24.09.2019 Page 8 of 8