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COURSE: LINEAR AND DIGITAL IC APPLICATIONS BRANCH: Electrical and Electronics Engineering
LECTURE NOTES
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INDEX
S. NO. 1 2 CONTENT UNIT I: INTEGRATED CIRCUITS UNIT II: CHARACTERISTICS OF OP-AMP 3 UNIT III: APPLICATIONS OF OPAMPS 4 UNIT IV: TIMERS & PHASE 19 - 25 26 32 33 35 36 41 11 - 18 PAGE NO. 3-7 8 - 10
LOGIC DESIGN 7 UNIT VII: SEQUENTIAL LOGIC DESIGN 8 UNIT VIII: PROGRAMMABLE 42 - 47
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1.1 INTEGRATED CIRCUITS An integrated circuit (IC) is a miniature, low cost electronic circuit consisting of active and passive components fabricated together on a single crystal of silicon. The active components are transistors and diodes and passive components are resistors and capacitors. 1.2 Advantages of integrated circuits 1. Miniaturization and hence increased equipment density. 2. Cost reduction due to batch processing. 3. Increased system reliability due to the elimination of soldered joints. 4. Improved functional performance. 5. Matched devices. 6. Increased operating speeds. 7. Reduction in power consumption
Depending upon the number of active devices per chip,there are different levels of integration
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AC Analysis---------- Ad=RC/2re Ri1= Ri2=2acre R 0 = Rc (c) The single input, balanced output differential Amplifier DC Analysis ---------IE =VEE - VBE/(2RE+Rin/dc) VCE=Vcc+ VBE-RcICQ AC Analysis---------- IE =VEE - VBE/(2RE+Rin/dc) Ri=2acre R01=R02=Rc (d)The single input, unbalanced output differential Amplifier DC Analysis--------- IE =VEE - VBE/(2RE+Rin/dc) VCE=Vcc+ VBE-RcICQ AC Analysis--------- Ad=RC/2re Ri=2acre R0= Rc
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2.1 Ideal OP-AMP An ideal OP-AMP would have the following characteristics:
1. The input resistance RIN would be infinite 2. The output resistance ROUT would be zero 3. The voltage gain, VG would be infinite 4. The bandwidth (how quickly the output will follow the input) would be infinite 5. If the voltages on the two inputs are equal than the output voltage is zero ( If the output is not zero it is said to have an offset)
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2.5 PSRR:
PSRR is Power Supply Rejection Ratio. It is defined as the change in the input offset voltage due to the change in one of the two supply voltages when other voltage is maintained constant. Its ideal value should be Zero.
2.6 Slew Rate: The maximum rate of change of output voltage with respect to time is called Slew rate of the Op-amp. It is expressed as, S =
max and
measured in V/sec.
In application where one desires large bandwidth and lower closed loop gain, suitable compensation technique are used: Two types of compensation techniques are used 1. External compensation 2. Internal compensation
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3.3 Ideal characteristics of OPAMP 1. Open loop gain infinite 2. Input impedance infinite 3. Output impedance low 4. Bandwidth infinite 5. Zero offset, ie, Vo=0 when V1=V2=0 3.4 Inverting Op-Amp
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3.6 DC characteristics
A small voltage applied to the input terminals to make the output voltage as zero when the two input terminals are grounded is called input offset voltage
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3.7 AC characteristics
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is usually done with the help of transducers. The output of transducer has to be amplified So that it can drive the indicator or display system. This function is performed by an instrumentation amplifier
3.10 Differentiator The circuit which produces the differentiation of the input voltage at its output is called differentiator. The differentiator circuit which does not use any active device is called passive differentiator. While the differentiator using an active device like op-amp is called an active differentiator.
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3.11 Integrator:
This circuit amplifies only the difference between the two inputs. In this circuit there are two
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resistors labeled R
IN
Which means that their values are equal. The differential amplifier
amplifies the difference of two inputs while the differentiator amplifies the slope of an input
3.13 Summer:
3.14 Comparator:
A comparator is a circuit which compares a signal voltage applied at one input of an op- amp with a known reference voltage at the other input. It is an open loop op - amp with output.
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Square wave outputs are generated when the op-amp is forced to operate in the saturated region. That is, the output of the op-amp is forced to swing repetitively between positive saturation and negative saturation. The square wave generator is also called as freerunning or Astable mutivibrator
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5. Frequency divider 6. Pulse width modulation 7. FSK generator 8. Pulse position modulator 9. Schmitt trigger
4.4 Multivibrator
Multivibrators are a group of regenerative circuits that are used extensively in timing applications. It is a wave shaping circuit which gives symmetric or asymmetric square output. It has two states either stable or quasi- stable depending on the type of multivibrator
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and this output level is maintained indefinitely until an second trigger is applied. Thus, it requires two external triggers before it returns to its initial state
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recovery time tp. To speed up the recovery time, RD (= 0.1Rf) & CD can be added.
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5.1 Filter
Filter is a frequency selective circuit that passes signal of specified Band of frequencies and attenuates the signals of frequencies outside the band
1. Low pass filter 2. High pass filter 3. Band pass filter 4. Band reject filter
5.4 Active Filters Active filters use op-amp(s) and RC components. Advantages over passive filters: op-amp(s) provide gain and overcome circuit losses increase input impedance to minimize circuit loading higher output power sharp cutoff characteristics can be produced simply and efficiently without bulky inductors
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Single-chip universal filters (e.g. switched-capacitor ones) are available that can be configured for any type of filter or response.
5.5 Review of Filter Types & Responses 4 major types of filters: low-pass, high-pass, band pass, and band-reject or band-stop 0 dB attenuation in the pass band (usually) 3 dB attenuation at the critical or cutoff frequency, fc (for Butterworth filter) Roll-off at 20 dB/dec (or 6 dB/oct) per pole outside the passband (# of poles = # of reactive elements). Attenuation at any frequency, f, is Bandwidth of a filter: BW = fcu - fcl Phase shift: 45o/pole at fc; 90o/pole at >> fc 4 types of filter responses are commonly used: Butterworth - maximally flat in passband; highly non-linear phase response with frequency Bessel - gentle roll-off; linear phase shift with freq. Chebyshev - steep initial roll-off with ripples in passband Cauer (or elliptic) - steepest roll-off of the four types but has ripples in the passband and in the stop band 5.6 Frequency Response of Filters
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5.8 Design Procedure for Unity-Gain HPF The same procedure as for LP filters is used except for step #3, the normalized C value of 1 F is divided by Kf. Then pick a desired value for C, such as 0.001 mF to 0.1 mF, to calculate Kx. (Note that all capacitors have the same value). For step #6, multiply all normalized R values (from table) by Kx. E.g. Design a unity-gain Butterworth HPF with a critical frequency of 1 kHz, and a roll-off of 55 dB/dec. (Ans.: C = 0.01 mF, R1 = 4.49 kW, R2 = 11.43 kW, R3 = 78.64 kW.; pick standard values of 4.3 kW, 11 kW, and 75 kW). 5.9 Equal-Component Filter Design
Design an equal-component LPF with a critical frequency of 3 kHz and a roll-off of 20 dB/oct.
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Minimum # of poles = 4 Choose C = 0.01 mF; R = 5.3 kW From table, Av1 = 1.1523, and Av2 = 2.2346. Choose RI1 = RI2 = 10 kW; then RF1 = 1.5 kW, and RF2 = 12.3 kW . Select standard values: 5.1 kW, 1.5 kW, and 12 kW. 5.10 Bandpass and Band-Rejection Filter 5.10.1 A broadband BPF can be obtained by combining a LPF and a HPF
5.10.2 Broadband Band-Reject Filter A LPF and a HPF can also be combined to give a broadband BRF
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5.10.4 Narrow-band Band-Reject Filter Easily obtained by combining the inverting output of a narrow-band BRF and the original signal
The equations for R1, R2, R3, C1, and C2 are the same as before. RI = RF for unity gain and is often chosen to be >> R1.
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Dual slope conversion is an indirect method for A/D conversion where an analog voltage and a reference voltage are converted into time periods by an integrator, and then measured by a counter. The speed of this conversion is slow but the accuracy is high Advantages of dual slope ADC are 1. It is highly accurate 2. Its cost is low 3. It is immune to temperature caused variations in R1 and C1
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UNIT VI
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6.1 Decoder: A decoder is a multiple-input and multiple output combinational logic circuit which converts coded input into coded output where the input and output codes are different. A decoder has n-input lines and 2n output lines
6.2 Encoder: An encoder is multiple input and multiple output combinational circuit it performs reverse operation of a decoder .An encoder has 2n (or fewer) input lines and n output lines
6.3 Multiplexer: Multiplexer is a digital switch. it allows digital information from several sources to be routed onto a single output line 6.3.1 Applications of multiplexer: 1. The logic function generator 2. Digital counter with multiplexed displays 3. Data selection and data routing 4. Parallel to serial conversion 6.4 Demutiplexers: A demutiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. 6.4.1 Applications of Demultiplexer: 1. Data distributor 2. Secuirity monitoring system 3. Synchronous data transmission system 6.5 Code converter There is a wide variety of binary codes used in digital systems. Some of these codes are binary coded-decimal (BCD), Excess-3, gray, and so on. Many times it is required to convert one code to another
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6.6 Comparator A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers
Adders & sub tractors, Ripple Adder, Binary Parallel Adder, Binary Adder-Subtractor, Combinational multipliers, ALU Design considerations of the above combinational logic circuits with relevant Digital ICs.
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Sequential circuits are again classified in to two types 1. Asynchronous sequential circuit 2. Synchronous sequential circuit
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7.5 JK Flip-Flop:
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Applications of shift register: 1. Delay line 2. parallel to serial converter 3. Serial to parallel converter 4. Sequence generator 5. Shift register counters
7.7 Counter
Counters are basically classified in to two types
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UNIT VIII
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8.3 Three-State Outputs A further improvement to the original PAL structure of Figure is done by adding three-state controls to its outputs as shown in the partial structure of figure
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It consists of n input lines and m output lines. Each bit combination of the input variables is called on address. Each bit combination that comes out of the output lines is called a word
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8.6.2 PROM. Programmable ROM is a one-time programmable chip that, once programmed, cannot be erased or altered. In a PROM, all minterms in the AND-plane are generated, and connections of all AND-plane outputs to ORplane gate inputs are in place. By applying a high voltage, transistors in the OR-plane that correspond to the minterms that are not needed for a certain output are burned out. a fresh PROM has all transistors in its OR-plane connected. When programmed, some will be fused out permanently. Likewise, considering the diagram of Figure 4.8, an unprogrammed PROM has Xs in all wire crossings in its OR-plane. 8.6.3 EPROM. An Erasable PROM is a PROM that once programmed, can be completely erased and reprogrammed. Transistors in the OR-plane of an EPROM have a normal gate and a floating gate . The non-floating gate is a normal NMOS transistor gate, and the floatinggate is surrounded by insulating material that allows an accumulated charge to remain on the gate for a long time. When not programmed, or programmed as a 1, the floating gate has no extra charge on it and the transistor is controlled by the non-floating gate (access gate). To fuse-out a transistor, or program a 0 into a memory location, a high voltage is applied to the access gate of the transistor which causes accumulation of negative charge in the floating-gate area. This negative charge prevents logic 1 values on the access gate from turning on the transistor. The transistor, therefore, will act as an unconnected transistor for as long as the negative charge remains on its floating-gate. To erase an EPROM it must be exposed to ultra-violate light for several minutes. In this case, the insulating materials in the floating-gates become conductive and these gates start loosing their negative charge. In this case, all transistors return to their normal mode of operation. This means that all EPROM memory contents become 1, and ready to be reprogrammed. Writing data into an EPROM is generally about a 1000 times slower than reading from it. This is while not considering the time needed for erasing the entire EPROM.
8.6.4 EEPROM. An EEPROM is an EPROM that can electrically be erased, and hence the name: Electrically Erasable Programmable ROM. Instead of using ultraviolate to remove the charge on the non-floating gate of an EPROM transistor, a voltage is applied to the opposite end of the transistor gate to remove its accumulated negative charge. An EEPROM can be erased and reprogrammed without having to remove it. This is useful for reconfiguring a design, or saving system configurations. As in EPROMs, EEPROMs are non-volatile
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memories. This means that they save their internal data while not powered. In order for memories to be electrically erasable, the insulating material surrounding the floating-gate must be much thinner than those of the EPROMS. This makes the number of times EEPROMs can be reprogrammed much less than that of EPROMs and in the order of 10 to 20,000. Writing into a byte of an EEPROM is about 500 times slower than reading from it.
8.6.5 Flash Memory. Flash memories are large EEPROMs that are partitioned into smaller fixed-size blocks that can independently be erased. Internal to a system, flash memories are used for saving system configurations. They are used in digital cameras for storing pictures. As external devices, they are used for temporary storage of data that can be rapidly retrieved. Various forms of ROM are available in various sizes and packages. The popular 27xxx series EPROMs come in packages that are organized as byte addressable memories. For example, the 27256 EPROM has 256K bits of memory that are arranged into 32K bytes.
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8.9 FPGA
FPGAs (Field-Programmable Gate Arrays) are PLDs with large numbers of small macrocells each of which can be interconnected to only a few neighboring cells. A typical FPGA might have 100 cells, each with only 8 inputs and 2 outputs. The output of each cell can be programmed to be an arbitrary function of its inputs. FPGAs typically have a large number ( ) of I/O pins.
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