1 Introduction

In the recent years the development of biomedical applications in wireless communication has become very popular [1, 2]. The research on Electrocardiogram (ECG) and Electroencephalogram (EEG) acquisition boards are giving impeccable results in the biomedical applications [1, 2]. The role of bio signal acquisition board is to collect bio signals from the human body which are weak in amplitude and frequency and transmit in digital form after amplification. So, for continuous transmission of physiological signals, a battery life is required to prolong the work time and the device size should get reduced to be implanted on the human body. Most importantly, high data accuracy should be maintained [3,4,5,6,7,8,9,10]. While going towards advanced CMOS processes, the benefits are: feature size is edged off and operates with lower threshold voltages, but leakage currents will play dominant role in the power consumption. Therefore, besides accommodating a small supply voltage, we need to minimize the leakage power to achieve better power efficiency. While transmitting the physiological signals through wireless, high data accuracy should be required because the neural signals are weak in amplitude (< 100 μV) and weak in frequencies (few Hz to below 100 Hz) [7, 8]. Physiological signals are the pure analog signals which are captured from the human body with transducers. The successive approximation register (SAR) type analog-to-digital converter (ADC) is an essential part in the analog signal processing [11,12,13,14,15,16,17,18]. SAR ADCs are available from 8 to 18 bits resolution with sampling rates up to 50 Msps [11, 12]. So SAR ADC is well suited when compared to other ADC architectures for transmission of physiological signals [7, 8] as shown in the Fig. 1. The charge redistribution DAC with charge scaling single ended spilt capacitor array is designed with small capacitance values so that switching speed increases and area is reduced. DAC operates in two modes, one is sampling phase and second is conversion phase by additional controlling as proposed in references [14], This paper also proposes a novel comparator which is designed to operate in the sub threshold region to have very low power consumption. An adjustable body bias is arranged in the regenerative latch phase to operate the transistor in weak inversion region so that leakage current is reduced for 500 mV Supply voltage. Few optimization technologies are adopted in the ADC blocks to reduce power consumption [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]. To implement the low power multi-channel signal processing system, a 0.5 V bulk-driven folded-cascoded operational trans conductance amplifier is proposed in references [31].The digital data from SAR ADC is stored in the proposed design of low power 16 × 16 SRAM array in references [32].

Fig. 1
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Proposed SAR ADC architecture

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This paper is organized as follows: In Sect. 2, the proposed SAR ADC is described. Section 3 describes the detailed circuit design of the ADC’s blocks. Low power optimized techniques discussed in Sect. 4 The measurement results and comparison with previous works are shown in Sect. 5 followed by conclusion.

2 SAR architecture

As shown in Fig. 1 the architecture of SAR ADC resembles the general ADC architecture only, but the essential blocks which are used in SAR ADC is designed with low power optimized techniques. Such as low power Comparator and single ended switched capacitor and the SAR control logic, which controls the DAC switches based on the comparator output. In the overall power consumption of the system, Comparator and DAC plays the major role because of switching between Vref and Vin, so we opted dual transmission gate based switching method instead of static CMOS inverter. The additional privilege in the proposed design is Variable threshold CMOS technique (VTCMOS). It is adopted for operating transistor under sub threshold region while minimizing leakage current. The working of the ADC is as shown in the Fig. 2 the complete operation of the ADC divided into three stages. The first stage is sampling stage, Second stage is conversion stage and finally recycling stage. During the initial stage the bottom plates of all the capacitors are connected to ground. The upper plates of the capacitors are connected to the inverting terminal of the comparator. Non inverting input of the comparator is connected to the sampled output. Based on the comparator output and control signals of switches, sampled signal is converted into digital form during second and third stages. The input signal is sampled by a sample and hold circuit which was explained in the Sect. 3.2. A detailed design process of all the blocks are explained in the next sections.

Fig. 2
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Flowchart of proposed ADC

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3 Design details of SAR ADC

3.1 Comparator

The low power regenerative comparator circuit is the essential block in the ADC and many electronic devices. The main goal is to design a high speed and low power preamplifier regenerative comparator circuit [28, 29]. Figure 3 shows the schematic of proposed preamplifier regenerative comparator circuit. The operation of the comparator is divided into pre-amp phase (reset) stage and dynamic comparison phase (set) stage with additional low on resistance switches S1 and S2 with non-overlapping clock signals as shown in Fig. 3. During the reset phase switch S1 will be open and S2 will be closed then the single stage folded amplifier, amplifies the voltage difference between the two input signals with voltage gain 40.4 dB (1). During the set phase S1 will close and S2 opens during the time regenerative comparator circuit compares between two input signals during the opted sampling intervals. Because of this set and reset phases the nonlinear error and offset error at comparator are reduced during analog to digital conversion. When \(V_{in} > V_{ref}\) the output signal exhibits logic high means level 1 and \(V_{in} < V_{ref}\) the output signal exhibits logic low means level 0.

Fig. 3
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Proposed schematic of the preamplifier regenerative comparator circuit with low on-resistance transmission gate based switches

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$$A_{dm} = \frac{{g_{m2} }}{{g_{ds2} + g_{ds6} }}$$
(1)

The preamplifier is a single stage operational trans conductance amplifier (OTA) [32] as shown in Fig. 3. The current scaling technique is implemented by the transistors M5–M6 with higher widths. Transistors Mb1, Mb2, Mb3 form a current mirror which delivers the differential currents. These differential currents are feed to output stage, for voltage to current conversion. Transistors M1 to M6 are operated in weak inversion region with appropriate W/L ratio. The drain to source current IDS (2) in weak inversion region depends on reverse saturation current IS, T is the ambient temperature, n is the inclination of the curve in weak inversion, K is the Boltzmann constant, q the charge of the electron or hole. The total power consumption of the comparator is 1.8 μW with 500 mV rail to rail supply voltage.

$$I_{DS} = I_{S} \left( {\frac{W}{L}} \right)\exp \left( {q\frac{{V_{GS} - V_{th} }}{nKT}} \right)\left[ {1 - \exp \left( { - q\frac{{V_{DS} }}{KT}} \right)} \right]$$
(2)

Current scaling is achieved by increasing the output impedances and thereby ensuring current scaling. The source degenerated current mirrors are formed by transistors Mc1, M5 and M6, set the currents in the regenerative circuit (the difference between the currents in M3–M4 and M5–M6). In order to save the power, the bias circuit is designed in such a way that the currents of transistors in the regenerative circuit are only a small portion of the input pair. The current scaling ratio between Mb1 and Mb2 is 7:1(2ID/14). The currents in the regenerative transistors are ID/7; this is 1/3rd of the differential input pair current. Using the bias circuit formed by Mb2 and Mc1, we set the current in the M5 and M6 to be 8ID/7 [31] (Table 1).

Table 1 Design summary of pre-amplifier
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The Transmission gate based switch is used for switching between set and reset operations, but to avoid glitches during switching and without voltage drops while passing through the channel, on-resistance should be reduced. The parallel combination of one low and high on-resistance of the transistors results low on-resistance. So on-resistance of the transmission gate is reduced while connecting one low W: L ratio pMOS transistor with high W:L ratio pMOS transistor and similarly for nMOS transistor.

3.2 Sample and hold

A simple sample and hold circuit is designed with CMOS Transmission gate and a sampling capacitor. To avoid charge injection error, a dummy switch is arranged as shown in the Fig. 4. The dummy switch is driven by an inverted clock which absorbs the charge injection from sampling switch. The unwanted glitches are also eliminated by using this dummy switch. The minimization of DNL and INL for better ADC design can be possible by connecting a buffer at the end of the sample and hold circuit.

Fig. 4
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a Sample and hold circuit with dummy switch. b Simulation result with sampling rate 5 Ksps

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3.3 Digital to analog converter (DAC)

A 10 bit charge scaling capacitive DAC is designed with a combination of two 5 bit charge scaling sub-DACs with a scaling capacitor \(C_{s}\) as shown in the Fig. 5. The operation of the DAC with example of five levels of shifting is explained with the help of the Fig. 6. The series combination of scaling capacitor starts with LSB array and terminates with MSB array. The accuracy of the DAC depends upon the scaling capacitor \(C_{s}\) as it is the terminating capacitor between LSB and MSB array.

Fig. 5
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Digital to Analog Converter with proposed regenerative comparator

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Fig. 6
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Switching procedure of proposed ADC with an example of 5 levels shifting

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The area of the DAC is proportional to the size of the unit capacitor. From the simulation test results the unit capacitance whose value is 62.5 fF. The operational amplifier which is discussed in the previous section is utilized in the DAC as a buffer to increase the linearity and to decrease comparator offset error [31].Total capacitance on the right of the scaling capacitor 1.937 pF and left of the scaling capacitor is 2 pF. DAC plays almost 40% in the total power consumption of ADC because dynamic power consumption and switching event capacitances, charge up phase dissipates more heat in the circuit. Dual split switching minimizes the switching energy by reducing on resistance of the transmission gate that could be explained in later sections. The power analyses of all the modules are as shown in the Fig. 7.

Fig. 7
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Power analysis of ADC blocks

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The high performance of the DAC is defined from the calculations of differential nonlinearity (DNL) and integral nonlinearity (INL). In this paper, DAC design is carried out for low frequency applications such as Physiological signals so there is no much importance for DNL and INL. However, all the performance metrics are carried out for proposed ADC as shown in the simulation results. DNL is the difference between an actual step width and ideal value of 1 LSB (Least Significant Bit).

$$1 LSB = \frac{{V_{FSR} }}{{2^{N} }}$$

\(V_{FSR}\) is the full scale range and N is the resolution of the ADC. Resolution of proposed ADC is 10 bit and \(V_{FSR} = 100\,{\text{mV}}\), so 1 LSB value is 100 μV.

$$DNL = \left[ {\frac{{V_{D + 1} - V_{D} }}{{V_{LSB IDEAL } }} - 1} \right], where 0 < D < 2^{N - 2}$$

3.4 SAR control logic

The advantage of Successive approximation register is to give zero latency compared to remaining ADC architectures. The circuit schematic of SAR Control logic is considered from Ref. [29] but the basic cell which is used in SAR control is DFF, it is designed with low on-resistance transmission gate with VTCMOS technique explained in previous sections. The gate level circuit is shown in Fig. 8.

Fig. 8
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Gate level circuit of D Flip-Flop in SAR control logic

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4 Proposed low power techniques

4.1 Variable threshold CMOS (VTCMOS)

In this paper, MOS transistor substrate bias voltage is dynamically varied to control the threshold voltage as shown in Fig. 9 and followed equations. The substrate voltages of nMOS and pMOS transistors are generated by the variable substrate bias control circuit. The transmission gate using VTCMOS technique is shown in Fig. 3 The circuit operates with low-power dissipation (due to low \(V_{DD}\)) and a high switching speed (due to a low \(V_{TH}\)). When the circuit is in the standby mode, the substrate bias control circuit generates a lower substrate bias voltage for the nMOS transistor and a higher substrate bias voltage for the pMOS transistor. As a result, the magnitudes of the threshold voltages (\(V_{THn}\) and \(V_{THp}\)) increase in the standby mode due to the body bias effectively. Since the sub threshold leakage current drops exponentially with increasing threshold voltage, the leakage power dissipation in the standby mode can be significantly reduced with this circuit design technique. However, with technology scaling, the effectiveness of the VTCMOS technique reduces the channel length becomes smaller [33].

where \(V_{1b} = V_{in} \frac{{R_{4} }}{{R_{3} + R_{4} }} \,Similary \,V_{2b} = V_{in} \frac{{R_{2} }}{{R_{1} + R_{2} }}\).

Fig. 9
figure 9

VTCMOS technique

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4.2 Dual split switching

Dual Spilt switching is done with 2:1 MUX design. In charge scaling DAC, 2:1 Mux is used to switch between \(V_{in } \;to\; V_{ref}\) and at the Sect. 3 in Preamplifier regenerative comparator design also dual spilt switching is used to switch between amplifier and comparator. The primary element used in the dual splitting design is a transmission gate [34]. In the proposed transmission gate, another set of NMOS and PMOS transistors are connected in parallel, so that the on resistance and sampling distortion are maintained as low as possible. The length and widths are in 2:1 ratio. As mentioned in previous section transmission gate is operated with VTCMOS technique refer Fig. 10.

Fig. 10
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2:1 Mux with dual transmission gates with on-resistance reducing method

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5 Test simulation results

The schematic of ADC was designed in the UMC 180 nm CMOS process. Chip fabrication was not carried out, but Simulation test results are verified with the theoretical. The performance of ADC is characterised by differential nonlinearity(DNL) and integral nonlinearity(INL) calculations. The simulated DNL and INL are 0.9/− 0.82 LSB and 1.06/− 1.31 LSB respectively as shown in Figs. 11 and 12. The input signal is a sinusoidal signal with frequency 100 Hz sampled at 1 MS/s with effective number of bits 7.69 bit. The power supply voltage is 0.5 V. Figure 13 shows positive level shifting for positive analog cycle and negative level shifting for negative analog cycle and Fig. 14 shows the measured 10 bit DAC divides the input range up to 1024 levels. Figure 15 shows the regenerative comparator output. The simulated SNDR and SFDR and ENOB results are shown in the Fig. 16 and Tables 2, 3.

Fig. 11
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Simulated DNL

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Fig. 12
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Simulated INL

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Fig. 13
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Simulated ADC output for 100 Hz sine wave input

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Fig. 14
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Simulated 10 bit DAC dividing input range (100 mV) to 1024 levels

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Fig. 15
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Regenerative comparator output waveform

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Fig. 16
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Simulated FFT for a 100 Hz sine wave with sampling rate 1 MS/s

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Table 2 Key parameters of proposed SAR ADC
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Table 3 Comparison of low power ADCs
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6 Conclusion

A 10 bit SAR ADC with a 100 mV Vref input range using dual split switching network in DAC is presented. A regenerative comparator operating in the sub threshold region with low offset is used, along with low power SAR logic with negative edge triggered flip-flop at a 500 mV supply voltage. The proposed ADC consumes 13.99 μW power. The ENOB around 7.69 bits.